A new time-digital convert circuit based on digital delay line

International Nuclear Information System (INIS)

Liu Haifeng; Guo Ying; Zhang Zhi

2004-01-01

An introduction of a new method of time-digital convert circuit based on digital delay line is given. High precision and good reliability can be realized when it is combined with traditional counting convert method in the measurement of large scale pulse width and low frequency self-excitation oscillator. (authors)

High-speed and high-resolution analog-to-digital and digital-to-analog converters

NARCIS (Netherlands)

van de Plassche, R.J.

1989-01-01

Analog-to-digital and digital-to-analog converters are important building blocks connecting the analog world of transducers with the digital world of computing, signal processing and data acquisition systems. In chapter two the converter as part of a system is described. Requirements of analog

RESONANT STEP-DOWN DC-DC POWER CONVERTERS

DEFF Research Database (Denmark)

2015-01-01

The present invention relates to a resonant step-down DC-DC power converter which comprises a primary side circuit and a secondary side circuit coupled through a galvanic isolation barrier. The primary side circuit comprises a positive and a negative input terminal for receipt of an input voltage...... charged from the input voltage and discharged to the output capacitor through the galvanic isolation barrier by a semiconductor switch arrangement in accordance with a switch control signal to produce the converter output voltage. The resonant step-down DC-DC power converter comprises an electrical short......-circuit connection across the galvanic isolation barrier connecting, in a first case, the second negative electrode of the output capacitor to the positive input terminal of the primary side circuit or, in a second case, connecting the second positive electrode of the output capacitor to the negative input terminal...

Digital Receiver Phase Meter

Science.gov (United States)

Marcin, Martin; Abramovici, Alexander

2008-01-01

The software of a commercially available digital radio receiver has been modified to make the receiver function as a two-channel low-noise phase meter. This phase meter is a prototype in the continuing development of a phase meter for a system in which radiofrequency (RF) signals in the two channels would be outputs of a spaceborne heterodyne laser interferometer for detecting gravitational waves. The frequencies of the signals could include a common Doppler-shift component of as much as 15 MHz. The phase meter is required to measure the relative phases of the signals in the two channels at a sampling rate of 10 Hz at a root power spectral density measurements in laser metrology of moving bodies. To illustrate part of the principle of operation of the phase meter, the figure includes a simplified block diagram of a basic singlechannel digital receiver. The input RF signal is first fed to the input terminal of an analog-to-digital converter (ADC). To prevent aliasing errors in the ADC, the sampling rate must be at least twice the input signal frequency. The sampling rate of the ADC is governed by a sampling clock, which also drives a digital local oscillator (DLO), which is a direct digital frequency synthesizer. The DLO produces samples of sine and cosine signals at a programmed tuning frequency. The sine and cosine samples are mixed with (that is, multiplied by) the samples from the ADC, then low-pass filtered to obtain in-phase (I) and quadrature (Q) signal components. A digital signal processor (DSP) computes the ratio between the Q and I components, computes the phase of the RF signal (relative to that of the DLO signal) as the arctangent of this ratio, and then averages successive such phase values over a time interval specified by the user.

Large step-down DC-DC converters with reduced current stress

International Nuclear Information System (INIS)

Ismail, Esam H.

2009-01-01

In this paper, several DC-DC converters with large voltage step-down ratios are introduced. A simple modification in the output section of the conventional buck and quadratic converters can effectively extend the duty-cycle range. Only two additional components (an inductor and diode) are necessary for extending the duty-cycle range. The topologies presented in this paper show an improvement in the duty-cycle (about 40%) over the conventional buck and quadratic converters. Consequently, they are well suited for extreme step-down voltage conversion ratio applications. With extended duty-cycle, the current stress on all components is reduced, leading to a significant improvement of the system losses. The principle of operation, theoretical analysis, and comparison of circuit performances with other step-down converters is discussed regarding voltage and current stress. Experimental results of one prototype rated 40-W and operating at 100 kHz are provided in this paper to verify the performance of this new family of converters. The efficiency of the proposed converters is higher than the quadratic converters

Digitized self-oscillating loop for piezoelectric transformer-based power converters

DEFF Research Database (Denmark)

Ekhtiari, Marzieh; Andersen, Thomas; Zhang, Zhe

2016-01-01

A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitized delay, or digitized phase shift through the self-oscillating loop results in a very precise...... frequency control and ensures an optimum operation of the piezoelectric transformer in terms of voltage gain and efficiency. In this work, additional time delay is implemented digitally for the first time through 16 bit digital-to-analog converter to the self-oscillating loop. Delay control setpoints...... updates at a rate of 417 kHz. This allows the control loop to dynamically follow frequency changes of the transformer in each resonant cycle. The operation principle behind self-oscillating is discussed in this paper. Moreover, experimental results are reported....

Computer Simulation of Phase Shifted Series Resonant DC to DC Converter

Directory of Open Access Journals (Sweden)

P. PARVATHY

2016-01-01

Full Text Available This paper deals with digital simulation of phase shifted series resonant DC to DC converter using Matlab Simulink. The Simulink models for open loop and closed loop systems are developed and they are used for simulation studies. This converter is capable of producing ripple free DC output. Switching losses and switching stresses are reduced by using soft switching. This converter has advantages like high power density and low switching losses. Theoretical predictions are well supported by the simulation results.

Digital control of high-frequency switched-mode power converters

CERN Document Server

Corradini, Luca; Mattavelli, Paolo; Zane, Regan

This book is focused on the fundamental aspects of analysis, modeling and design of digital control loops around high-frequency switched-mode power converters in a systematic and rigorous manner Comprehensive treatment of digital control theory for power converters Verilog and VHDL sample codes are provided Enables readers to successfully analyze, model, design, and implement voltage, current, or multi-loop digital feedback loops around switched-mode power converters Practical examples are used throughout the book to illustrate applications of the techniques developed Matlab examples are also

Noise-shaping all-digital phase-locked loops modeling, simulation, analysis and design

CERN Document Server

Brandonisio, Francesco

2014-01-01

This book presents a novel approach to the analysis and design of all-digital phase-locked loops (ADPLLs), technology widely used in wireless communication devices. The authors provide an overview of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. Realistic examples illustrate how to analyze and simulate phase noise in the presence of sigma-delta modulation and time-to-digital conversion. Readers will gain a deep understanding of ADPLLs and the central role played by noise-shaping. A range of ADPLL and TDC architectures are presented in unified manner. Analytical and simulation tools are discussed in detail. Matlab code is included that can be reused to design, simulate and analyze the ADPLL architectures that are presented in the book.   • Discusses in detail a wide range of all-digital phase-locked loops architectures; • Presents a unified framework in which to model time-to-digital converters for ADPLLs; • Explains a procedure to predict and simulate phase noise in oscil...

A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

International Nuclear Information System (INIS)

Yang Weidong; Pu Jie; Zhang Ruitao; Chen Chao; Zang Jiandong; Li Tiehu; Luo Pu

2015-01-01

This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18 μm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB and INL less than ±4.3 LSB after the chip is calibrated. (paper)

Application of digital control techniques for satellite medium power DC-DC converters

Science.gov (United States)

Skup, Konrad R.; Grudzinski, Pawel; Nowosielski, Witold; Orleanski, Piotr; Wawrzaszek, Roman

2010-09-01

The objective of this paper is to present a work concerning a digital control loop system for satellite medium power DC-DC converters that is done in Space Research Centre. The whole control process of a described power converter bases on a high speed digital signal processing. The paper presents a development of a FPGA digital controller for voltage mode stabilization that was implemented using VHDL. The described controllers are a classical digital PID controller and a bang-bang controller. The used converter for testing is a simple model of 5-20 W, 200 kHz buck power converter. A high resolution digital PWM approach is presented. Additionally a simple and effective solution of filtering of an analog-to-digital converter output is presented.

High-Speed Universal Frequency-to-Digital Converter for Quasi-Digital Sensors and Transducers

Directory of Open Access Journals (Sweden)

Sergey Y. Yurish

2007-06-01

Full Text Available New fast, accurate universal integrated frequency-to-digital converter (UFDC-1M-16 is described in the article. It is based on the novel patented modified method of the dependent count and has non-redundant conversion time from 6.25 ms to 6.25 ms for 1 to 0.001 % relative errors respectively, comparable with conversion time for successive-approximation and S-D ADC. The IC can work with different sensors, transducers and encoders, which have frequency, period, duty-cycle, PWM, phase shift, pulse number, etc. output.

Interleaved Buck Converter with Variable Number of Active Phases and a Predictive Current Sharing Scheme

DEFF Research Database (Denmark)

Jakobsen, Lars Tønnes; Garcia, O.; Oliver, J. A.

2008-01-01

The efficiency of an interleaved Buck converter is typically low at light load conditions because of the switching losses in each of the switching stages. Improvements in the converter efficiency can be achieved by dynamically changing the number of active phases depending on the load current....... This paper addresses the issues related to the transient response of the converter when the number of active phases is changed by a digital control scheme. The problem arises because the current in the individual phases of the interleaved Buck converter will not be equal immediately after the controller has...... changed the number of active phases. This paper proposes a current equalisation scheme that adjusts the duty cycle of each phase in a manner that ensures equal average inductor current in all active phases in one or two PWM periods. The current equalisation scheme relies on the measurement of the output...

A 13-Bits wilkinson analog-digital converter for NIM acquisition system

International Nuclear Information System (INIS)

Acosta Toledo, R.; Osorio Deliz, J.; Arista Romeu, E.; Fernandez, J.

1994-01-01

A new 13-bits Wilkinson analog-digital converter is described. The aim of this work is to describe the circuits of sample and hold, memory condensator loading and releasing PROM based control memory logic, zero level detection and correction. The converter is designed for the digital measurement of the peak amplitudes of pulses with statistical or periodical time distribution. The analog-digital converter may be used in spectrometric systems, multi-channel analysers or any similar PC based system

Resonant Tunneling Analog-To-Digital Converter

Science.gov (United States)

Broekaert, T. P. E.; Seabaugh, A. C.; Hellums, J.; Taddiken, A.; Tang, H.; Teng, J.; vanderWagt, J. P. A.

1995-01-01

As sampling rates continue to increase, current analog-to-digital converter (ADC) device technologies will soon reach a practical resolution limit. This limit will most profoundly effect satellite and military systems used, for example, for electronic countermeasures, electronic and signal intelligence, and phased array radar. New device and circuit concepts will be essential for continued progress. We describe a novel, folded architecture ADC which could enable a technological discontinuity in ADC performance. The converter technology is based on the integration of multiple resonant tunneling diodes (RTD) and hetero-junction transistors on an indium phosphide substrate. The RTD consists of a layered semiconductor hetero-structure AlAs/InGaAs/AlAs(2/4/2 nm) clad on either side by heavily doped InGaAs contact layers. Compact quantizers based around the RTD offer a reduction in the number of components and a reduction in the input capacitance Because the component count and capacitance scale with the number of bits N, rather than by 2 (exp n) as in the flash ADC, speed can be significantly increased, A 4-bit 2-GSps quantizer circuit is under development to evaluate the performance potential. Circuit designs for ADC conversion with a resolution of 6-bits at 25GSps may be enabled by the resonant tunneling approach.

Real time event selection and flash analog-to-digital converters

International Nuclear Information System (INIS)

Imori, Masatosi

1983-01-01

In high-energy particle experiments, high-speed analog logic is employed to select events on a real-time basis. Flash analog-to-digital converters replace the high-speed analog logic with digital logic. The digital logic gives great flexibility to the scheme for real-time event selection. This paper proposes the use of flash A/D converters for the logic used to obtain the total sum of the energy deposited in individual counters in a shower detector. (author)

A high speed digital-to-analogue converter

International Nuclear Information System (INIS)

Hallgren, B.I.

1974-02-01

An 8-bit Digital-to-Analogue converter of the current-weighting type has been constructed using 8 monolithic integrated circuit transistor arrays -one for each bit. The D/A-converter has a voltage output within the range 0 to -2V. The settling time to within half of the least significant bit is about 50 nsec. The temperature dependence and transient response of the converter has been analysed using computer aided design techniques. A comparison is made between the experimental and simulated transient performance. (Auth.)

Energy savings assessment for digital-to-analog converter boxes

International Nuclear Information System (INIS)

Cheung, Hoi Ying; Meier, Alan; Brown, Richard

2011-01-01

The Digital Television (DTV) Converter Box Coupon Program was administered by the U.S. government to subsidize purchases of digital-to-analog converter boxes, with up to two $40 coupons for each eligible household. In order to qualify as Coupon Eligible Converter Boxes (CECBs), these devices had to meet a number of minimum performance specifications, including energy efficiency standards. The Energy Star Program also established voluntary energy efficiency specifications that are more stringent than the CECB requirements. In this study, we measured the power and energy consumptions for a sample of 12 CECBs (including 6 Energy Star labeled models) in-use in homes and estimated aggregate energy savings produced by the energy efficiency policies. Based on the 35 million coupons redeemed through the end of the program, our analysis indicates that between 2500 and 3700 GWh per year are saved as a result of the energy efficiency policies implemented on digital-to-analog converter boxes. The energy savings generated are equivalent to the annual electricity use of 280,000 average US homes. - Research highlights: → We examined energy efficiency policies on digital-to-analog converter boxes in US. → The government assistance program resulted in high participation. → 35 million coupons were redeemed for the purchases of energy efficient DTAs. → Between 2500 and 3700 GWh per year are saved as a result of the policies. → Savings are equivalent to the annual electricity use of 280,000 average US homes.

High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital...

Reference-Free CMOS Pipeline Analog-to-Digital Converters

CERN Document Server

Figueiredo, Michael; Evans, Guiomar

2013-01-01

This book shows that digitally assisted analog-to-digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low ...

A digital silicon photomultiplier with multiple time-to-digital converters

Energy Technology Data Exchange (ETDEWEB)

Garutti, Erika [University Hamburg (Germany); Silenzi, Alessandro [DESY, Hamburg (Germany); Xu, Chen [DESY, Hamburg (Germany); University Hamburg (Germany)

2013-07-01

A silicon photomultiplier (SiPM) with pixel level signal digitization and column-wise connected time-to-digital converters (TDCs) has been developed for an endoscopic Positron Emission Tomography (PET) detector. A digital SiPM has pixels consist of a single photon avalanche diode (SPAD) and circuit elements to optimize overall dark counts and temporal response. Compared with conventional analog SiPM, digital SiPM's direct signal route from SPAD to TDC improves single photon time resolution. In addition, using multiple TDCs can perform the statistical estimation of the time-of-arrival in multiple photon detection case such as readout of scintillation crystals. Characterization measurements of the prototype digital SiPM and a Monte-Carlo simulation to predict the timing performance of the PET detector are shown.

Mathematical Modeling and Digital Control of A Hybrid Switching Buck Converter

Directory of Open Access Journals (Sweden)

Muhammad Umar Abbasi

2017-06-01

Full Text Available The aim of this paper is to describe mathematical modeling and digital control of a hybrid switching buck converter. This converter belongs to a class of so called hybrid switching converters and contains a resonant capacitor, resonant inductor and a diode in addition to original buck converter components. The dc gain of this converter is shown to be independent of resonant branch parameters. Moreover the dc conversion ratio is derived for both ideal case and including main inductor dc resistance. Small signal model of the converter is derived and is shown to be similar to conventional buck converter. Simulation results in SIMPLIS Software as well as experimental results of digital control using an 8 bit STM microcontroller are presented. The potential advantages and applications of this converter are discussed.

Digitally Controlled Point of Load Converter with Very Fast Transient Response

DEFF Research Database (Denmark)

Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

2007-01-01

voltage mode control and very fast transient response. The DiSOM modulator is combined with a digital PID compensator algorithm is implemented in a hybrid CPLD/FPGA and is used to control a synchronous Buck converter, which is used in typical Point of Load applications. The computational time is only......This paper presents a new Digital Self-Oscillating Modulator (DiSOM) that allows the duty cycle to be changed instantly. The DiSOM modulator is shown to have variable switching that is a function of the duty cycle. Compared to a more traditional digital PWM modulator based on a counter...... and comparator the DiSOM modulator allows the sampling frequency of the output voltage control loop to be higher than the switching frequency of the power converter, typically a DC/DC converter. The features of the DiSOM modulator makes it possible to design a digitally controlled DC/DC converter with linear...

Inverter-based successive approximation capacitance-to-digital converter

KAUST Repository

Omran, Hesham

2017-03-23

An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog- to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter- based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.

Theory of two-photon interactions with broadband down-converted light and entangled photons

International Nuclear Information System (INIS)

Dayan, Barak

2007-01-01

When two-photon interactions are induced by down-converted light with a bandwidth that exceeds the pump bandwidth, they can obtain a behavior that is pulselike temporally, yet spectrally narrow. At low photon fluxes this behavior reflects the time and energy entanglement between the down-converted photons. However, two-photon interactions such as two-photon absorption (TPA) and sum-frequency generation (SFG) can exhibit such a behavior even at high power levels, as long as the final state (i.e., the atomic level in TPA, or the generated light in SFG) is narrow-band enough. This behavior does not depend on the squeezing properties of the light, is insensitive to linear losses, and has potential applications. In this paper we describe analytically this behavior for traveling-wave down conversion with continuous or pulsed pumping, both for high- and low-power regimes. For this we derive a quantum-mechanical expression for the down-converted amplitude generated by an arbitrary pump, and formulate operators that represent various two-photon interactions induced by broadband light. This model is in excellent agreement with experimental results of TPA and SFG with high-power down-converted light and with entangled photons [Dayan et al., Phys. Rev. Lett. 93, 023005 (2004); 94, 043602 (2005); Pe'er et al., ibid. 94, 073601 (2005)

Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA

Science.gov (United States)

Sano, Y.; Horii, Y.; Ikeno, M.; Sasaki, O.; Tomoto, M.; Uchida, T.

2017-12-01

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope with the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13-0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed.

Fixed switching frequency applied in single-phase boost AC to DC converter

International Nuclear Information System (INIS)

Chen, T.-C.; Ren, T.-J.; Ou, J.-C.

2009-01-01

The fixed switching frequency control for a single-phase boost AC to DC converter to achieve a sinusoidal line current and unity power factor is proposed in this paper. The relation between the line current error and the fixed switching frequency was developed. For a limit line current error, the minimum switching frequency for a boost AC to DC converter can be achieved. The proposed scheme was implemented using a 32-bit digital signal processor TMS320C32. Simulations and experimental results demonstrate the feasibility and fast dynamic response of the proposed control strategy.

Step-down switched-capacitor quasi-resonant PWM converter with continuous conversion ratio

NARCIS (Netherlands)

Turhan, M.; Hendrix, M.A.M.; Duarte, J.L.

2015-01-01

Inherent disadvantages of conventional switched-capacitor converters (SCC) are their discrete conversion ratio and inefficient energy transfer. In order to soften these downsides, a step-down switched-capacitor quasi-resonant PWM converter is proposed. The operation modes and steady-state

Combined analog-to-digital converter

International Nuclear Information System (INIS)

Zhukov, A.V.; Rzhendinskaya, S.N.

1983-01-01

A 10-bit analog-to-digital converter (ADC) designed for operating in spectrometers with time-dependent filters is described. The ADC operation is based on combining the parallel reading and sequential counting methods. At maximum conversion time of 12 μs, timing series frequency of 25 MHz and foUr reference levels the differential nonlinearity withoUt statistical smoothing (maximum relative channel width deviation from average value) is not more than 4%

Optimum phase shift in the self-oscillating loop for piezoelectric transformer-based power converters

DEFF Research Database (Denmark)

Ekhtiari, Marzieh; Zsurzsan, Tiberiu-Gabriel; Andersen, Michael A. E.

2017-01-01

A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitally controlled time delay through the self-oscillating loop results in very precise frequency control...... and ensures optimum operation of the piezoelectric transformer in terms of gain and efficiency. Time delay is implemented digitally for the first time through a 16 bit digital-to-analog converter in the self-oscillating loop. The new design of the delay circuit provides 45 ps time resolution, enabling fine......-grained control of phase in the self-oscillating loop. This allows the control loop to dynamically follow frequency changes of the transformer in each resonant cycle. Ultimately, by selecting the optimum phase shift, maximum efficiency under the load and temperature condition is achievable....

Digital beam position monitor for the HAPPEX experiment

International Nuclear Information System (INIS)

Sherlon Kauffman; John Musson; Hai Dong; Lisa Kaufman; Arne Freyberger

2005-01-01

The proposed HAPPEX experiment at CEBAF employs a three cavity monitor system for high precision (1um), high bandwidth (100 kHz) position measurements. This is performed using a cavity triplet consisting of two TM110-mode cavities (one each for X and Y planes) combined with a conventional TM010-mode cavity for a phase and magnitude reference. Traditional systems have used the TM010 cavity output to directly down convert the BPM cavity signals to base band. The multi-channel HAPPEX digital receiver simultaneously I/Q samples each cavity and extracts position using a CORDIC algorithm. The hardware design consists of a RF receiver daughter board and a digital processor motherboard that resides in a VXI crate. The daughter board down converts 1.497 GHz signals from the TM010 cavity and X and Y signals from the TM110 cavities to 3 MHz and extracts the quadrature digital signals. The motherboard processes this data and computes beam intensity and X-Y positions with resolution of 1um, 100 kHz output bandwidth, and overall latency of 1us. The results are available in both the analog and digital format

Designed cell consortia as fragrance-programmable analog-to-digital converters.

Science.gov (United States)

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Fast digital feedback control systems for accelerator RF system using FPGA

International Nuclear Information System (INIS)

Bagduwal, Pritam Singh; Sharma, Dheeraj; Tiwari, Nitesh; Lad, M.; Hannurkar, P.R.

2012-01-01

Feedback control system plays important role for proper injection and acceleration of beam in particle accelerators by providing the required amplitude and phase stability of RF fields in accelerating structures. Advancement in the field of digital technology enables us to develop fast digital feedback control system for RF applications. Digital Low Level RF (LLRF) system offers the inherent advantages of Digital System like flexibility, adaptability, good repeatability and reduced long time drift errors compared to analog system. To implement the feedback control algorithm, I/Q control scheme is used. By properly sampling the down converted IF signal using fast ADC we get accurate feedback signal and also eliminates the need of two separate detectors for amplitude and phase detection. Controller is implemented in Vertex-4 FPGA. Codes for control algorithms which controls the amplitude and phase in all four quadrants with good accuracy are written in the VHDL. I/Q modulator works as common actuator for both amplitude and phase correction. Synchronization between RF, LO and ADC clock is indispensable and has been achieved by deriving the clock and LO signal from RF signal itself. Control system has been successfully tested in lab with phase and amplitude stability better then ±1% and ±1° respectively. High frequency RF signal is down converted to IF using the super heterodyne technique. Super heterodyne principal not only brings the RF signal to the Low IF frequency at which it can be easily processed but also enables us to use the same hardware and software for other RF frequencies with some minor modification. (author)

A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

Directory of Open Access Journals (Sweden)

M. Rezvanyvardom

2015-09-01

Full Text Available This paper investigates a novel cyclic time-to-digital converter (TDC which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop. The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT variations. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. Also, this converter improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC reduces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM. In this converter, the integral nonlinearity (INL and differential nonlinearity (DNL errors are reduced. In order to evaluate the idea, the proposed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

Development of prototype digital LLRF system at RRCAT

International Nuclear Information System (INIS)

Tiwari, Nitesh; Bagduwal, Pritam S.; Sharma, Dheeraj; Chakraborty, Shoubhik; Lad, Mahendra; Hannurkar, P.R.

2013-01-01

RF field is used in accelerator to accelerate the charge particles. The beam parameters depend highly on the stability of the RF field. Due to dynamic beam loading conditions the variations in RF parameters of accelerating structures needs to be controlled precisely, hence low level RF feedback control system plays vital role. Considering revolutionary development in the field of digital electronics and inherent advantages of digital systems, digital LLRF control system work was taken up. The digital LLRF system consists of two major units namely RF processing and digital processing. RF processing unit uses I/Q modulator for amplitude and phase control. This unit provides synchronized clock using ÷16 pre-scalar and also performs up conversion and down conversion for synchronized LO and IF generation respectively, along with required amplification and filtering. Digital processing unit takes down converted IF signal with appropriate sampling rate for I/Q detection. To extract the amplitude and phase information I/Q data is digitally filtered and processed using CORDIC algorithm in FPGA. I/Q modulator is used for controlling the amplitude and phase of RF field. Prototype development of digital LLRF control system for 325 MHz, 650 MHz is in progress. Digital LLRF system at 505 MHz has been installed in one RF station of Indus-2 RF system. In this paper development of prototype Digital LLRF system at RFSD, Raja Ramanna Centre for Advanced Technology and results are presented. (author)

Large-scale digitizer system, analog converters

International Nuclear Information System (INIS)

Althaus, R.F.; Lee, K.L.; Kirsten, F.A.; Wagner, L.J.

1976-10-01

Analog to digital converter circuits that are based on the sharing of common resources, including those which are critical to the linearity and stability of the individual channels, are described. Simplicity of circuit composition is valued over other more costly approaches. These are intended to be applied in a large-scale processing and digitizing system for use with high-energy physics detectors such as drift-chambers or phototube-scintillator arrays. Signal distribution techniques are of paramount importance in maintaining adequate signal-to-noise ratio. Noise in both amplitude and time-jitter senses is held sufficiently low so that conversions with 10-bit charge resolution and 12-bit time resolution are achieved

Low power very high frequency resonant converter with high step down ratio

DEFF Research Database (Denmark)

Madsen, Mickey Pierre; Knott, Arnold; Andersen, Michael A. E.

2013-01-01

This paper presents the design of a resonant converter with a switching frequency in the very high frequency range (30-300MHz), a large step down ratio and low output power. This gives the designed converters specifications which are far from previous results. The class E inverter and rectifier...

A UWB down convert circuit and measurement

DEFF Research Database (Denmark)

Han, Bo; Liu, Mengmeng; Ge, Ning

2010-01-01

MHz, division ratio 1/160, it can be locked at 3.36 GHz with the phase noise of -83 dBc/Hz, the internal Digital VGA could be digitally controlled by FPGA with 30 dB tuning range. Though Chip scope verification, This receiver can demodulate 500 MHz Bandwidth signal without error bit rate by connected...

Simple Digital Control of a Two-Stage PFC Converter Using DSPIC30F Microprocessor

DEFF Research Database (Denmark)

Török, Lajos; Munk-Nielsen, Stig

2010-01-01

The use of dsPIC digital signal controllers (DSC) in Switch Mode Power Supply (SMPS) applications opens new perspectives for cheap and flexible digital control solutions. This paper presents the digital control of a two stage power factor corrector (PFC) converter. The PFC circuit is designed...... and built for 70W rated output power. Average current mode control for boost converter and current programmed control for forward converter are implemented on a dsPIC30F1010. Pulse Width Modulation (PWM) technique is used to drive the switching MOSFETs. Results show that digital solutions with ds...

Mismatch-Shaping Serial Digital-to-Analog Converter

DEFF Research Database (Denmark)

Steensgaard-Madsen, Jesper; Moon, Un-Ku; Temes, Gabor C.

1999-01-01

A simple but accurate pseudo-passive mismatch-shaping D/A converter is described. A digital state machine is used to control the switching sequence of a symmetric two-capacitor network that performs the D/A conversion. The error caused by capacitor mismatch is uncorrelated with the input signal...

Digitally Controlled Offline Converter with Galvanic Isolation Based on an 8-bit Microcontroller

DEFF Research Database (Denmark)

Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

2007-01-01

This paper presents an offline AC/DC converter with digital control and galvanic isolation that can be implemented using cheap commercially available components. An ATMEL ATTiny26 8-bit microcontroller is used to control the converter. The microcontroller is placed on the secondary side of the co......This paper presents an offline AC/DC converter with digital control and galvanic isolation that can be implemented using cheap commercially available components. An ATMEL ATTiny26 8-bit microcontroller is used to control the converter. The microcontroller is placed on the secondary side...

Single-Chip DC-DC Converter for Harsh Environments, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Alphacore Inc. will develop a digitally controlled, high switching rate, digital hysteresis based DCDC converter suitable for space and harsh environment...

Three-phase Resonant DC-link Converter

OpenAIRE

Munk-Nielsen, Stig

1997-01-01

The purpose of the project is to develop a three-phase resonant converter suitable for standard speed drives. The motivation for working with resonant converters is found in the problem of the standard converter type used today. In standard converter type Pulse Width Modulated-Voltage Source Inverter, PWM-VSI, the switches are subject to high current and voltage stress during switching, which causes losses. The fast switching of modern switches reduces switching losses. Unfortunately this pro...

CMOS based capacitance to digital converter circuit for MEMS sensor

Science.gov (United States)

Rotake, D. R.; Darji, A. D.

2018-02-01

Most of the MEMS cantilever based system required costly instruments for characterization, processing and also has large experimental setups which led to non-portable device. So there is a need of low cost, highly sensitive, high speed and portable digital system. The proposed Capacitance to Digital Converter (CDC) interfacing circuit converts capacitance to digital domain which can be easily processed. Recent demand microcantilever deflection is part per trillion ranges which change the capacitance in 1-10 femto farad (fF) range. The entire CDC circuit is designed using CMOS 250nm technology. Design of CDC circuit consists of a D-latch and two oscillators, namely Sensor controlled oscillator (SCO) and digitally controlled oscillator (DCO). The D-latch is designed using transmission gate based MUX for power optimization. A CDC design of 7-stage, 9-stage and 11-stage tested for 1-18 fF and simulated using mentor graphics Eldo tool with parasitic. Since the proposed design does not use resistance component, the total power dissipation is reduced to 2.3621 mW for CDC designed using 9-stage SCO and DCO.

A Capacitance-To-Digital Converter for MEMS Sensors for Smart Applications.

Science.gov (United States)

Pérez Sanjurjo, Javier; Prefasi, Enrique; Buffa, Cesare; Gaggl, Richard

2017-06-07

The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 µm CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm², which means a pressure resolution of 1 Pa, while consuming 146 µA from a 1.5 V power supply.

Modeling and reliability analysis of three phase z-source AC-AC converter

Directory of Open Access Journals (Sweden)

Prasad Hanuman

2017-12-01

Full Text Available This paper presents the small signal modeling using the state space averaging technique and reliability analysis of a three-phase z-source ac-ac converter. By controlling the shoot-through duty ratio, it can operate in buck-boost mode and maintain desired output voltage during voltage sag and surge condition. It has faster dynamic response and higher efficiency as compared to the traditional voltage regulator. Small signal analysis derives different control transfer functions and this leads to design a suitable controller for a closed loop system during supply voltage variation. The closed loop system of the converter with a PID controller eliminates the transients in output voltage and provides steady state regulated output. The proposed model designed in the RT-LAB and executed in a field programming gate array (FPGA-based real-time digital simulator at a fixedtime step of 10 μs and a constant switching frequency of 10 kHz. The simulator was developed using very high speed integrated circuit hardware description language (VHDL, making it versatile and moveable. Hardware-in-the-loop (HIL simulation results are presented to justify the MATLAB simulation results during supply voltage variation of the three phase z-source ac-ac converter. The reliability analysis has been applied to the converter to find out the failure rate of its different components.

Multilevel Converter by Cascading Two-Level Three-Phase Voltage Source Converter

Directory of Open Access Journals (Sweden)

Abdullrahman A. Al-Shamma’a

2018-04-01

Full Text Available This paper proposes a topology using isolated, cascaded multilevel voltage source converters (VSCs and employing two-winding magnetic elements for high-power applications. The proposed topology synthesizes 6 two-level, three-phase VSCs, so the power capability of the presented converter is six times the capability of each VSC module. The characteristics of the proposed topology are demonstrated through analyzing its current relationships, voltage relationships and power capability in detail. The power rating is equally shared among the VSC modules without the need for a sharing algorithm; thus, the converter operates as a single three-phase VSC. The comparative analysis with classical neutral-point clamped, flying capacitor and cascaded H-bridge exhibits the superior features of fewer insulated gate bipolar transistors (IGBTs, capacitor requirement and fewer diodes. To validate the theoretical performance of the proposed converter, it is simulated in a MATLAB/Simulink environment and the results are experimentally demonstrated using a laboratory prototype.

Three-phase Resonant DC-link Converter

DEFF Research Database (Denmark)

Munk-Nielsen, Stig

The purpose of the project is to develop a three-phase resonant converter suitable for standard speed drives. The motivation for working with resonant converters is found in the problem of the standard converter type used today. In standard converter type Pulse Width Modulated-Voltage Source...... Inverter, PWM-VSI, the switches are subject to high current and voltage stress during switching, which causes losses. The fast switching of modern switches reduces switching losses. Unfortunately this procedure increased dv/dt and the size of the input/output filters of the PWM-SVI must be increased...

Very High-Performance Advanced Filter Bank Analog-to-Digital Converter (AFB ADC) Project

National Research Council Canada - National Science Library

Velazquez, Scott

1999-01-01

... of the art by using a parallel array of individual commercial off the shelf converters. The significant performance improvements afforded by the Advanced Filter Bank Analog to Digital Converter (AFB ADC...

Digitally-controlled PC-interfaced Boost Converter for Educational Purposes

DEFF Research Database (Denmark)

Ljusev, Petar; Andersen, Michael A. E.

2004-01-01

This paper describes implementation of a simple digital PID control algorithm for a boost converter using a cheap fixed-point 8-bit microcontroller. Serial communication to a PC server program is established for easier downloading of compensator parameters and current and voltage waveform...

Controllable frequency entanglement via auto-phase-matched spontaneous parametric down-conversion

International Nuclear Information System (INIS)

Sergienko, A.V.; Walton, Z.D.; Booth, M.C.; Saleh, B.E.A.; Teich, M.C.

2005-01-01

Full text: A new method for generating entangled photons with controllable frequency correlation via spontaneous parametric down-conversion (SPDC) is presented. The method entails initiating counter-propagating SPDC in a single-mode nonlinear waveguide by pumping with a pulsed beam perpendicular to the waveguide. In a typical spontaneous parametric down-conversion (SPDC) experiment, a photon from a monochromatic pump beam decays into two photons (often referred to as signal and idler) via interaction with a nonlinear optical crystal. While the signal and idler may be broadband individually, conservation of energy requires that the sum of their respective frequencies equals the single frequency of the monochromatic pump. This engenders frequency anti-correlation in the down-converted beams. Two developments in quantum information theory have renewed interest in the generalized states of frequency correlation. First, quantum information processes requiring the synchronized creation of multiple photon pairs have been devised, such as quantum teleportation. The requisite temporal control can be achieved by pumping the crystal with a brief pulse. The availability of pump photons of differing frequencies relaxes the strict frequency anti-correlation in the down-converted beams. Second, applications such as entanglement-enhanced clock synchronization and one-way auto-compensating quantum cryptography have been introduced that specifically require frequency correlation, as opposed to the usual frequency anticorrelation. Our method for obtaining controllable frequency entanglement entails initiating type-I SPDC (signal and idler identically polarized) in a single-mode nonlinear waveguide by pumping with a pulsed beam perpendicular to the waveguide. The down-converted photons emerge from opposite ends of the waveguide with a joint spectrum that can be varied from frequency anti-correlated to frequency correlated by adjusting the temporal and spatial characteristics of the

A THREE-PHASE BOOST DC-AC CONVERTER

African Journals Online (AJOL)

dc-ac converter (inverter) based on the dc-dc boost converters. ... Sliding mode controllers are designed to perform a robust control for the ... Computer simulations and spectral analysis demon- ... the conventional three-phase buck inverter,.

Algorithm improvement for phase control of subharmonic buncher

International Nuclear Information System (INIS)

Zhang Junqiang; Yu Luyang; Yin Chongxian; Zhao Minghua; Zhong Shaopeng

2011-01-01

To realize digital phase control of subharmonic buncher,a low level radio frequency control system using down converter, IQ modulator and demodulator techniques, and commercial PXI system, was developed on the platform of LabVIEW. A single-neuron adaptive PID (proportional-integral-derivative) control algorithm with ability of self learning was adopted, satisfying the requirements of phase stability. By comparison with the traditional PID algorithm in field testing, the new algorithm has good stability, fast response and strong anti-interference ability. (authors)

Auxiliary controller for time-to-digital converter module readout

International Nuclear Information System (INIS)

Ermolin, Yu.V.

1992-01-01

The KD-225 auxiliary controller for time-to-digital converter module readout in the SUMMA crate is described. After readout and preliminary processing the data are written in the P-140 buffer memory module. The controller is used in the FODS-2 experimental setup data acquisition system. 12 refs.; 1 fig

Diamond-Shaped Semiconductor Ring Lasers for Analog to Digital Photonic Converters

National Research Council Canada - National Science Library

Green, Malcolm

2004-01-01

Photonic/ optoelectronic analog to digital converters (ADCs) have advantages in areas such as precise sampling times, narrow sampling apertures, and the ability to sample without contaminating the incident signal...

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

OpenAIRE

Zhang, Dai

2014-01-01

Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultralow- power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent A...

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-{mu}m CMOS technology

Energy Technology Data Exchange (ETDEWEB)

Yu Jinshan; Zhang Ruitao; Zhang Zhengping; Wang Yonglu; Zhu Can; Zhang Lei; Yu Zhou; Han Yong, E-mail: yujinshan@yeah.net [National Laboratory of Analog IC' s, Chongqing 400060 (China)

2011-01-15

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-{mu}m CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input. (semiconductor integrated circuits)

Analysis and characterization of cyclic-scale compensated analog-to-digital converters

International Nuclear Information System (INIS)

Gatti, E.; Manfredi, P.F.; Marino, D.

1979-01-01

The authors discuss characteristics and limitations of cyclic-scale compensated analog-to-digital converters. After summarizing the behaviour of the method implemented in an ideal way, they show how the inaccuracies in the auxillary analog levels affect the real design. Having stated under what approximations and with what cares a cyclic-scale compensated converter approaches the ideal case of channels having equal profiles, the consequences of this property, are studied. (Auth.)

Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update

CERN Document Server

Pickering, J.

2015-06-15

This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and implementing it in a design have not changed. Analogue to digital and digital to analogue converters are crucial components in the continued drive to replace analogue circuitry with more controllable and less costly digital processing. This paper discusses the technologies available to perform in the likely measurement and control applications that arise within accelerators. It covers much of the terminology and 'specmanship' together with an application-oriented analysis of the realisable performance of the various types. Finally, some hints and warnings on system integration problems are given.

Simulation of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

International Nuclear Information System (INIS)

Meng, X.T.; Levin, D.S.; Chapman, J.W.; Zhou, B.

2016-01-01

The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New Small Wheel endcap Phase-1 upgrade for higher luminosity LHC operation. These new trigger chambers, located in a high rate region of ATLAS, will improve overall trigger acceptance and reduce the fake muon trigger incidence. These chambers must generate a low level muon trigger to be delivered to a remote high level processor within a stringent latency requirement of 43 bunch crossings (1075 ns). To help meet this requirement the High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by CERN Microelectronics group, has been proposed for the digitization of the fast front end detector signals. This paper investigates the HPTDC performance in the context of the overall muon trigger latency, employing detailed behavioral Verilog simulations in which the latency in triggerless mode is measured for a range of configurations and under realistic hit rate conditions. The simulation results show that various HPTDC operational configurations, including leading edge and pair measurement modes can provide high efficiency (>98%) to capture and digitize hits within a time interval satisfying the Phase-1 latency tolerance.

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Directory of Open Access Journals (Sweden)

Taninki Sai Lakshmi

2014-01-01

Full Text Available An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL value of −0.30 LSB and differential nonlinearity (DNL value of −0.24 LSB, of the flash ADC.

Virtual unit delay for digital frequency adaptive T/4 delay phase-locked loop system

DEFF Research Database (Denmark)

Yang, Yongheng; Zhou, Keliang; Blaabjerg, Frede

2016-01-01

/processor with a fixed sampling rate considering the cost and complexity, where the number of unit delays that have been adopted should be an integer. For instance, in conventional digital control systems, a single-phase T/4 Delay Phase-Locked Loop (PLL) system takes 50 unit delays (i.e., in a 50-Hz system...... Delay PLL system should be done in its implementation. This process will result in performance degradation in the digital control system, as the exactly required number of delays is not realized. Hence, in this paper, a Virtual Unit Delay (VUD) has been proposed to address such challenges to the digital......Digital micro-controllers/processors enable the cost-effective control of grid-connected power converter systems in terms of system monitoring, signal processing (e.g., grid synchronization), control (e.g., grid current and voltage control), etc. Normally, the control is implemented in a micro-controller...

Modal spectrum in spontaneous parametric down-conversion with noncollinear phase matching

CSIR Research Space (South Africa)

Zhang, Y

2014-06-01

Full Text Available We investigate the effect of the down-conversion angle between the signal and idler beams in spontaneous parametric down-conversion on the bandwidth of the modal spectrum (Schmidt number) of the down-converted quantum state. For this purpose, we...

FPGA implementation of a single-input fuzzy logic controller for boost converter with the absence of an external analog-to-digital converter

DEFF Research Database (Denmark)

Taeed, Fazel; Salam, Z.; Ayob, S.

2012-01-01

converter (ADC). Instead, a simple analog-to-digital conversion scheme is implemented using the FPGA itself. Due to the simplicity of the SIFLC algorithm and the absence of an external ADC, the overall implementation requires only 408 logic elements and five input-output pins of the FPGA.......) and applied on a 50-W boost converter. The SIFLC is compared to the proportional-integral controller; the simulation and practical results indicate that SIFLC exhibits excellent performance for step load and input reference changes. Another feature of this work is the absence of an external analog-to-digital...

Static and Dynamic Characteristics of DC-DC Converter Using a Digital Filter

Science.gov (United States)

Kurokawa, Fujio; Okamatsu, Masashi

This paper presents the regulation and dynamic characteristics of the dc-dc converter with digital PID control, the minimum phase FIR filter or the IIR filter, and then the design criterion to improve the dynamic characteristics is discussed. As a result, it is clarified that the DC-DC converter using the IIR filter method has superior performance characteristics. The regulation range is within 1.3%, the undershoot against the step change of the load is less than 2% and the transient time is less than 0.4ms with the IIR filter method. In this case, the switching frequency is 100kHz and the step change of the load R is from 50 Ω to 10 Ω. Further, the superior characteristics are obtained when the first gain, the second gain and the second cut-off frequency are relatively large, and the first cut-off frequency and the passing frequency are relatively low. Moreover, it is important that the gain strongly decreases at the second cut-off frequency because the upper band pass frequency range must be always less than half of the sampling frequency based on the sampling theory.

Current Controller for Multi-level Front-end Converter and Its Digital Implementation Considerations on Three-level Flying Capacitor Topology

Science.gov (United States)

Tekwani, P. N.; Shah, M. T.

2017-10-01

This paper presents behaviour analysis and digital implementation of current error space phasor based hysteresis controller applied to three-phase three-level flying capacitor converter as front-end topology. The controller is self-adaptive in nature, and takes the converter from three-level to two-level mode of operation and vice versa, following various trajectories of sector change with the change in reference dc-link voltage demanded by the load. It keeps current error space phasor within the prescribed hexagonal boundary. During the contingencies, the proposed controller takes the converter in over modulation mode to meet the load demand, and once the need is satisfied, controller brings back the converter in normal operating range. Simulation results are presented to validate behaviour of controller to meet the said contingencies. Unity power factor is assured by proposed controller with low current harmonic distortion satisfying limits prescribed in IEEE 519-2014. Proposed controller is implemented using TMS320LF2407 16-bit fixed-point digital signal processor. Detailed analysis of numerical format to avoid overflow of sensed variables in processor, and per-unit model implementation in software are discussed and hardware results are presented at various stages of signal conditioning to validate the experimental setup. Control logic for the generation of reference currents is implemented in TMS320LF2407A using assembly language and experimental results are also presented for the same.

8-bit serial-parallel analog-to-digital converter for fast transient recorder

International Nuclear Information System (INIS)

Kulka, Z.; Nadachowski, M.; Zimek, Z.

1990-08-01

An 8-bit serial-parallel analog-to-digital converter with a sampling frequency 5 MHz is described. The most important circuits of the device are described and parameters are given. The converter is a central part of a transient recorder type TR-1 designed for recording pulse waveforms in measurements of the kinetics of chemical reactions which are radiation-induced using an electron linear accelerator. 9 refs., 9 figs. (author)

Floating high step-down stacked dc-dc converter based on buck-boost cells

NARCIS (Netherlands)

Tibola, G.; Duarte, J.L.; Blinov, A.

2015-01-01

In some high power dc-dc applications, where high voltage is present, a converter with high step-down ratio is required in order to provide an isolated low power auxiliary supply. This requirement represents a challenge and many topologies are currently being researched. The analysis of a

A study of analog-to digital sliding scale. Converter utilization

Energy Technology Data Exchange (ETDEWEB)

Maddaleno, F; Rossi, M

1996-12-31

The well-known Sliding Scale technique provides a statistical linearization of the Analog to Digital Converter, obtaining a high differential linearity. This technique sums at each conversion a known and uncorrelated variable signal (offset) to the analog input signal, and then subs tract numerically the offset from the conversion result. 2 refs.

Locality of Area Coverage on Digital Acoustic Communication in Air using Differential Phase Shift Keying

Science.gov (United States)

Mizutani, Keiichi; Ebihara, Tadashi; Wakatsuki, Naoto; Mizutani, Koichi

2009-07-01

We experimentally evaluate the locality of digital acoustic communication in air. Digital acoustic communication in air is suitable for a small cell system, because acoustic waves have a short propagation distance in air. In this study, optimal cell size is experimentally evaluated. Each base station (BS) transmits different commands. In our experiment, differential phase shift keying (DPSK), especially binary DPSK (DBPSK), is adopted as a modulation and demodulation scheme. The evaluated system consists of a personal computer (PC), a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a loud speaker (SP), a microphone (MIC), and transceiver software. All experiments are performed in an anechoic room. The cell size of the transmitter can be limited under low signal-to-noise ratio (SNR) condition. If another transmitter works, cell size is limited by the effect of the interference from that transmitter. The cell size-to-distance ratio of transmitter A to transmitter B is 37.5%, if cell edge bit-error-rate (BER) is taken as 10-3.

VHDL Implementation of Sigma-Delta Analog To Digital Converter

Science.gov (United States)

Chavan, R. N.; Chougule, D. G.

2010-11-01

Sigma-Delta modulation techniques provide a range of opportunities in a signal processing system for both increasing performance and data path optimization along the silicon area axis in the design space. One of the most challenging tasks in Analog to Digital Converter (ADC) design is to adapt the circuitry to ever new CMOS process technology. For digital circuits the number of gates per square mm app. doubles per chip generation. Integration of analog parts in newer deep submicron technologies is much more tough and additionally complicated because the usable voltage ranges are decreasing with every new integration step. This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs. Resolutions of up to 16 bit are achievable. Sample rates in the 1 MHz region are feasible so that the approach is also useful for ADCs for xDSL technologies.

Low-Power, Low-Voltage Resistance-to-Digital Converter for Sensing Applications

Directory of Open Access Journals (Sweden)

Sergey Y. YURISH

2016-09-01

Full Text Available IC (ASIP of Universal Sensors and Transducers Interface (USTI-MOB with low power consumption, working in the resistive measurement mode (one of 26 possible measuring modes is described in the article. The proposed IC has 20 W to 4.5 M W range of measurement, relative error< ±0.04 %, 0.85 mA supply current and 1.2 V supply voltage. The worst-case error of about< ±1.54 % is observed. IC has three popular serial interfaces: I2C, SPI and RS232/USB. Due to high metrological performance and technical characteristics the USTI- MOB is well suitable for such application as: sensor systems for IoT, wearable and mobile devices, and digital multimeters. The ICs can also work with any quasi-digital resistive converters, in which the resistance is converted to frequency, period, duty-cycle or pulse width.

Development of a digital solar simulator based on full-bridge converter

Science.gov (United States)

Liu, Chen; Feng, Jian; Liu, Zhilong; Tong, Weichao; Ji, Yibo

2014-02-01

With the development of solar photovoltaic, distribution schemes utilized in power grid had been commonly application, and photovoltaic (PV) inverter is an essential equipment in grid. In this paper, a digital solar simulator based on full-bridge structure is presented. The output characteristic curve of system is electrically similar to silicon solar cells, which can greatly simplify research methods of PV inverter, improve the efficiency of research and development. The proposed simulator consists on a main control board based on TM320F28335, phase-shifted zero-voltage-switching (ZVS) DC-DC full-bridge converter and voltage and current sampling circuit, that allows emulating the voltage-current curve with the open-circuit voltage (Voc) of 900V and the short-circuit current (Isc) of 18A .When the system connected to a PV inverter, the inverter can quickly track from the open-circuit to the maximum power point and keep stability.

2 GHz self-aligning tandem A/D converter for SAR

DEFF Research Database (Denmark)

Søbjærg, Sten Schmidl; Christensen, Erik Lintz

2001-01-01

digitizing, and the other is to digitize the signal before digital I/Q demodulation. In both cases the digitizing may be performed by a digital front end (DFE) with two parallel analog-to-digital-converters (ADCs) sampling at 1 GHz in phase or in anti-phase respectively, provided the analog bandwidth...... of the ADC is sufficient. In the first case each ADC has to digitize a 0-400 MHz signal, and in the second case both ADCs have to digitize a 100-900 MHz signal. In both cases the sampling time alignment is a critical parameter. The paper addresses some aspects of ADC alignment in the implementation of a DFE...

Connect high speed analog-digital converter with EPICS based on LabVIEW

International Nuclear Information System (INIS)

Wang Wei; Chi Yunlong

2008-01-01

This paper introduce a method to connect high speed analog-digital converter (ADC212/100) with EPICS on Windows platform using LabVIEW. We use labVIEW to communicate with the converter, then use interface sub-VIs between LabVIEW and EPICS to access the EPICS IOC by Channel Access (CA). For the easy use graph programming language of LabVIEW, this method could shorten the develop period and reduce manpower cost. (authors)

Double closed-loop resonant micro optic gyro using hybrid digital phase modulation.

Science.gov (United States)

Ma, Huilian; Zhang, Jianjie; Wang, Linglan; Jin, Zhonghe

2015-06-15

It is well-known that the closed-loop operation in optical gyros offers wider dynamic range and better linearity. By adding a stair-like digital serrodyne wave to a phase modulator can be used as a frequency shifter. The width of one stair in this stair-like digital serrodyne wave should be set equal to the optical transmission time in the resonator, which is relaxed in the hybrid digital phase modulation (HDPM) scheme. The physical mechanism for this relaxation is firstly indicated in this paper. Detailed theoretical and experimental investigations are presented for the HDPM. Simulation and experimental results show that the width of one stair is not restricted by the optical transmission time, however, it should be optimized according to the rise time of the output of the digital-to-analogue converter. Based on the optimum parameters of the HDPM, a bias stability of 0.05°/s for the integration time of 400 seconds in 1 h has been carried out in an RMOG with a waveguide ring resonator with a length of 7.9 cm and a diameter of 2.5 cm.

Graphical Evaluation of Time-Delay Compensation Techniques for Digitally Controlled Converters

DEFF Research Database (Denmark)

Lu, Minghui; Wang, Xiongfei; Loh, Poh Chiang

2018-01-01

A main design constraint of the digitally controlled power electronics converters is the time delay of control systems, which may lead to the reduced control loop bandwidth and even unstable dynamics. Numerous time-delay compensation methods have been developed, of which the model-free schemes...

New technologies for radiation-hardening analog to digital converters

International Nuclear Information System (INIS)

Gauthier, M.K.

1982-12-01

Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years

New technologies for radiation-hardening analog to digital converters

Science.gov (United States)

Gauthier, M. K.

1982-01-01

Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years.

Multisensor transducer based on a parallel fiber optic digital-to-analog converter

Directory of Open Access Journals (Sweden)

Grechishnikov Vladimir

2017-01-01

Full Text Available Considered possibility of creating a multisensory information converter (MSPI based on new fiber-optic functional element-digital-to-analog (DAC fiber optic converter. The use of DAC fiber-optic provides jamming immunity combined with low weight and cost of indicators .Because of that MSPI scheme was developed based on parallel DAC fiber-optic (Russian Federation Patent 157416. We came up with an equation for parallel DAC fiber-optic. An eleborate general mathematical model of the proposed converter. Developed a method for reducing conversion errors by placing the DAC transfer function between i and i + 1 ADC quantization levels. By using this model it allows you to obtain reliable information about the technical capabilities of a converter without the need for costly experiments.

Couplings in Phase Domain Impedance Modelling of Grid-Connected Converters

DEFF Research Database (Denmark)

Dowlatabadi, Mohammadkazem Bakhshizadeh; Wang, Xiongfei; Blaabjerg, Frede

2016-01-01

The output impedance of a power converter plays an important role in the stability assessment of the converter. The impedance can be expressed in different frames such as the stationary frame (phase domain) or in the synchronous frame (dq domain). To treat the three-phase system like a single...

Research on Parallel Three Phase PWM Converters base on RTDS

Science.gov (United States)

Xia, Yan; Zou, Jianxiao; Li, Kai; Liu, Jingbo; Tian, Jun

2018-01-01

Converters parallel operation can increase capacity of the system, but it may lead to potential zero-sequence circulating current, so the control of circulating current was an important goal in the design of parallel inverters. In this paper, the Real Time Digital Simulator (RTDS) is used to model the converters parallel system in real time and study the circulating current restraining. The equivalent model of two parallel converters and zero-sequence circulating current(ZSCC) were established and analyzed, then a strategy using variable zero vector control was proposed to suppress the circulating current. For two parallel modular converters, hardware-in-the-loop(HIL) study based on RTDS and practical experiment were implemented, results prove that the proposed control strategy is feasible and effective.

Spline-based high-accuracy piecewise-polynomial phase-to-sinusoid amplitude converters.

Science.gov (United States)

Petrinović, Davor; Brezović, Marko

2011-04-01

We propose a method for direct digital frequency synthesis (DDS) using a cubic spline piecewise-polynomial model for a phase-to-sinusoid amplitude converter (PSAC). This method offers maximum smoothness of the output signal. Closed-form expressions for the cubic polynomial coefficients are derived in the spectral domain and the performance analysis of the model is given in the time and frequency domains. We derive the closed-form performance bounds of such DDS using conventional metrics: rms and maximum absolute errors (MAE) and maximum spurious free dynamic range (SFDR) measured in the discrete time domain. The main advantages of the proposed PSAC are its simplicity, analytical tractability, and inherent numerical stability for high table resolutions. Detailed guidelines for a fixed-point implementation are given, based on the algebraic analysis of all quantization effects. The results are verified on 81 PSAC configurations with the output resolutions from 5 to 41 bits by using a bit-exact simulation. The VHDL implementation of a high-accuracy DDS based on the proposed PSAC with 28-bit input phase word and 32-bit output value achieves SFDR of its digital output signal between 180 and 207 dB, with a signal-to-noise ratio of 192 dB. Its implementation requires only one 18 kB block RAM and three 18-bit embedded multipliers in a typical field-programmable gate array (FPGA) device. © 2011 IEEE

Review of the Initial Phases of the LHC Power Converter Commissioning

CERN Document Server

Nisbet, D

2008-01-01

The LHC requires more than 1700 power converter systems that supply between 60A and 13kA of precisely regulated current to the superconducting magnets. For the first time at CERN these converters have been installed underground in close proximity to many other accelerator systems. In addition to the power converters themselves, many utilities such as air and water cooling, electrical power, communication networks and magnet safety systems needed to be installed and commissioned as a single system. Due to the complexity of installing and commissioning such a large infrastructure, with inevitable interaction between the different systems, a three phase test strategy was developed. The first phase comprised the manufacture, integration and reception tests of all converter sub-systems necessary for powering. The second phase covered the commissioning of all the power converters installed in their final environment with the utilities. The third phase will add the superconducting magnets and will not be covered by ...

New three-phase ac-ac converter incorporating three-phase boost integrated ZVT bridge and single-phase HF link

International Nuclear Information System (INIS)

Abdelhamid, Tamer H.; Sabzali, Ahmad J.

2008-01-01

This paper presents a new zero voltage transition (ZVT), power factor corrected three phase ac-ac converter with single phase high frequency (HF) link. It is a two stage converter; the first stage is a boost integrated bridge converter (combination of a 3 ph boost converter and a bridge converter) operated at fixed frequency and that operates in two modes at ZVT for all switches and establishes a 1 ph square wave HF link. The second stage is a bi-directional pulse width modulation (PWM) 3 ph bridge that converts the 1 ph HF link to a 3 ph voltage using a novel switching strategy. The converter modes of operation and key equations are outlined. Simulation of the overall system is conducted using Simulink. The switching strategy and its corresponding control circuit are clearly described. Experimental verification of the simulation is conducted for a prototype of 100 V, 500 W at 10 kHz link frequency

Real-time compression of analog-to-digital converter outputs

International Nuclear Information System (INIS)

Okumura, Haruhiko

1997-01-01

We describe a fast lossless data compression algorithm suitable for digitized data taken at regular time intervals, such as outputs from analog-to-digital converters (ADCs). It is designed on the assumptions that the present value can be predicted approximately from the past values, and that the distribution of the prediction error is approximately Gaussian with zero mean and small and slowly changing standard deviation. Unlike many offline compression tools such as LHA and gzip, our algorithm does not need future values to encode the present value. This property is important for real-time transmission of compressed data on the network. The algorithm is to be integrated into our data acquisition system for the Large Helical Device (LHD) experiments at the National Institute for Fusion Science (NIFS). (author)

Time-to-digital converter for a time-correlation analyzer

International Nuclear Information System (INIS)

Kumpf, S.

1979-01-01

An electronic circuit operating as a time-to-digital converter is described. It receives pulses from eight n-detectors on eight input channels which are converted into the first half of a 16-bit word. The work called 'label' is indicating the channel on which an event has arrived. Contemporarily a crystal controlled four stage 4-bit binary counter gives the time when the event arrives expressed in the form of a second 16-bit work called 'time'. These two words are fed via a FIFO-buffer and a DMA-control to a very fast minicomputer Miproc 16 from Plessey-Micro-Systems with a cycle time of 250 ns. The circuit is built in TTL-technique on two double Europa-format cards and is built into the card bay of the Miproc 16 and acts as a peripheral device

Data Converter for Multistandard Mobile Phones

DEFF Research Database (Denmark)

Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

2004-01-01

This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...... Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures....... The entire ADC consumes about 5.5 mW and occupies an active area of about 0.36 mm(2). A test circuit has been developed and fabricated and measurements show that both the required programmability and the required performance can be obtained using the proposed configurations....

Efficiency and hardware comparison of analog control-based and digital control-based 70 W two-stage power factor corrector and DC-DC converters

DEFF Research Database (Denmark)

Török, Lajos; Munk-Nielsen, Stig

2011-01-01

A comparison of an analog and a digital controller driven 70 W two-stage power factor corrector converter is presented. Both controllers are operated in average current-mode-control for the PFC and peak current control for the DC-DC converter. Digital controller design and converter modeling...... is described. Results show that digital control can compete with the analog one in efficiency, PFC and THD....

Digital logic circuit test

Energy Technology Data Exchange (ETDEWEB)

Yun, Gil Jung; Yang, Hong Young

2011-03-15

This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.

PIC microcontroller based external fast analog to digital converter to acquire wide-lined solid NMR spectra by BRUKER DRX and Avance-I spectrometers.

Science.gov (United States)

Koczor, Bálint; Rohonczy, János

2015-01-01

Concerning many former liquid or hybrid liquid/solid NMR consoles, the built in Analog-to-Digital Converters (ADCs) are incapable of digitizing the fids at sampling rates in the MHz range. Regarding both strong anisotropic interactions in the solid state and wide chemical shift dispersion nuclei in solution phase such as (195)Pt, (119)Sn, (207)Pb etc., the spectrum range of interest might be in the MHz range. As determining the informative tensor components of anisotropic NMR interactions requires nonlinear fitting over the whole spectrum including the asymptotic baseline, it is prohibited by low sampling rates of the ADCs. Wide spectrum width is also useful in solution NMR, since windowing of wide chemical shift ranges is avoidable. We built an external analog to digital converter with 10 MHz maximal sampling rate, which can work simultaneously with the built in ADC of the spectrometer. The ADC was tested on both Bruker DRX and Avance-I NMR consoles. In addition to the analog channels it only requires three external digital lines of the NMR console. The ADC sends data to PC via USB. The whole process is controlled by software written in JAVA which is implemented under TopSpin. Copyright © 2015 Elsevier Inc. All rights reserved.

Road Tripping down the Digital Preservation Highway, Part I: Hitting the Road

Science.gov (United States)

Colati, Jessica Branco; Colati, Gregory C.

2011-01-01

In this inaugural column, the authors introduce Peter Palmer, erstwhile librarian at Bellaluna University who is being tasked with managing the library's and university's digital content as he begins his journey down the Digital Highway. As head of access services at Bellaluna University, Peter had been, by default, made responsible for managing…

CMOS time-to-digital converters for mixed-mode signal processing

OpenAIRE

Fei Yuan

2014-01-01

This study provides an in-depth review of the principles, architectures and design techniques of CMOS time-to-digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs. Sampling TDCs including direct-counter TDCs, tapped delay-line TDCs, pulse-shrinking delay-line TDCs, cyclic pulse-shrinking TDCs, direct-counter TDCs with interpolation, vernier TDCs, flash TDCs, successive approximation TDCs an...

Design Strategy for a Pipelined ADC Employing Digital Post-correction

NARCIS (Netherlands)

Harpe, P.J.A.; Zanikopoulos, A.; Hegt, J.A.; Roermund, van A.H.M.

2004-01-01

This paper describes how the usage of digital post-correction techniques in pipelined analog-to-digital converters (ADC's) can be exploited optimally during the design-phase of the converter. It is known that post-correction algorithms reduce the influence of several cir- cuit impairments on the

High Input Voltage Hall Thruster Discharge Converter, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — The overall scope of this Phase I/II effort is the development of a high efficiency 15kW (nominal) Hall thruster discharge converter. In Phase I, Busek Co. Inc. will...

High-accuracy resolver-to-digital conversion via phase locked loop based on PID controller

Science.gov (United States)

Li, Yaoling; Wu, Zhong

2018-03-01

The problem of resolver-to-digital conversion (RDC) is transformed into the problem of angle tracking control, and a phase locked loop (PLL) method based on PID controller is proposed in this paper. This controller comprises a typical PI controller plus an incomplete differential which can avoid the amplification of higher-frequency noise components by filtering the phase detection error with a low-pass filter. Compared with conventional ones, the proposed PLL method makes the converter a system of type III and thus the conversion accuracy can be improved. Experimental results demonstrate the effectiveness of the proposed method.

A Single Phase to Three Phase PFC Half-Bridge Converter Using BLDC Drive with SPWM Technique.

OpenAIRE

Srinu Duvvada; Manmadha Kumar B

2014-01-01

In this paper, a buck half-bridge DC-DC converter is used as a single-stage power factor correction (PFC) converter for feeding a voltage source inverter (VSI) based permanent magnet brushless DC motor (BLDC) drive. The front end of this PFC converter is a diode bridge rectifier (DBR) fed from single-phase AC mains. The BLDC is used to drive a compressor load of an air conditioner through a three-phase VSI fed from a controlled DC link voltage. The speed of the compressor is controlled to ach...

Converting Topographic Maps into Digital Form to Aid in Archeological Research in the Peten, Guatemala

Science.gov (United States)

Aldrich, Serena R.

1999-01-01

The purpose of my project was to convert a topographical map into digital form so that the data can be manipulated and easily accessed in the field. With the data in this particular format, Dr. Sever and his colleagues can highlight the specific features of the landscape that they require for their research of the ancient Mayan civilization. Digital elevation models (DEMs) can also be created from the digitized contour features adding another dimension to their research.

Design and Analysis of Two-Phase Boost DC-DC Converter

OpenAIRE

Taufik Taufik; Tadeus Gunawan; Dale Dolan; Makbul Anwari

2010-01-01

Multiphasing of dc-dc converters has been known to give technical and economical benefits to low voltage high power buck regulator modules. A major advantage of multiphasing dc-dc converters is the improvement of input and output performances in the buck converter. From this aspect, a potential use would be in renewable energy where power quality plays an important factor. This paper presents the design of a 2-phase 200W boost converter for battery charging application. Analysis of results fr...

Design of a 12-bit 80MS/s pipeline analog-to-digital converter for PLC-VDSL applications

Science.gov (United States)

Ruiz-Amaya, Jesus; Delgado-Restituto, Manuel; Fernandez-Bootello, Juan F.; de la Rosa, Jose M.

2005-06-01

This paper describes the design of a 12-bit 80MS/s pipeline Analog-to-Digital converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation, synthesis and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is based on a 10-stage pipeline preceded by a sample/hold with bootstrapping technique. Each stage gives 1.5 effective bits, except for the first one which provides 2.5 effective bits to improve linearity. The Analog-to-Digital architecture uses redundant bits for digital correction, it is planned to be implemented without using calibration and employs a subranging pipeline look-ahead technique to increase speed. Substrate biased MOSFETs in the depletion region are used as capacitors, linearized by a series compensation. Simulation results show that the Multi-Tone Power Ratio is higher than 56dB for several DMT test signals and the estimated Signal-to-Noise Ratio yield is supposed to be better than 62 dB from DC to Nyquist frequency. The converter dissipates less than 150mW from a 3.3V supply and occupies less than 4 mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.

SEM analysis of ionizing radiation effects in an analog to digital converter /AD571/

Science.gov (United States)

Gauthier, M. K.; Perret, J.; Evans, K. C.

1981-01-01

The considered investigation is concerned with the study of the total-dose degradation mechanisms in an IIL analog to digital (A/D) converter. The A/D converter is a 10 digit device having nine separate functional units on the chip which encompass several hundred transistors and circuit elements. It was the objective of the described research to find the radiation sensitive elements by a systematic search of the devices on the LSI chip. The employed technique using a scanning electron microscope to determine the functional blocks of an integrated circuit which are sensitive to ionizing radiation and then progressively zeroing in on the soft components within those blocks, proved extremely successful on the AD571. Four functional blocks were found to be sensitive to radiation, including the Voltage Reference, DAC, IIL Clock, and IIL SAR.

Single-Stage Step up/down Driver for Permanent-Magnet Synchronous Machines

Science.gov (United States)

Chen, T. R.; Juan, Y. L.; Huang, C. Y.; Kuo, C. T.

2017-11-01

The two-stage circuit composed of a step up/down dc converter and a three-phase voltage source inverter is usually adopted as the electric vehicle’s motor driver. The conventional topology is more complicated. Additional power loss resulted from twice power conversion would also cause lower efficiency. A single-stage step up/down Permanent-Magnet Synchronous Motor driver for Brushless DC (BLDC) Motor is proposed in this study. The number components and circuit complexity are reduced. The low frequency six-step square-wave control is used to reduce the switching losses. In the proposed topology, only one active switch is gated with a high frequency PWM signal for adjusting the rotation speed. The rotor position signals are fed back to calculate the motor speed for digital close-loop control in a MCU. A 600W prototype circuit is constructed to drive a BLDC motor with rated speed 3000 rpm, and can control the speed of six sections.

A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

International Nuclear Information System (INIS)

Santos, D.M.; Dow, S.F.; Flasck, J.M.; Levi, M.E.

1996-01-01

Phase-locked loops have been employed in the past to obtain sub-nanosecond time resolution in high energy physics and nuclear science applications. An alternative solution based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Mueller C-element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multichannel, time-to-digital converter (TDC) targeted for one specific frequency. The two circuits, DLL and TDC, are implemented in CMOS 1.2 microm and 0.8 microm technologies, respectively. Test results show a timing jitter of less than 30 ps for the DLL circuit and less than 190 ps integral and differential nonlinearity for the TDC circuit

Hexuple-Inverter Configuration for Multilevel Nine-Phase Symmetrical Open-Winding Converter

DEFF Research Database (Denmark)

Padmanaban, Sanjeevi Kumar; Bhaskar, Mahajan Sagar; Maroti, Pandav Kiran

2016-01-01

Hexuple-inverter configuration for multilevel nine-phase symmetrical open-winding ac converter is articulated in this work. Power modular unit consists of six classical three-phase voltage source inverters (VSI). Each VSI includes one bi-directional device (MOSFET/IGBT) per each phase and link...... software’s (Matlab/PLECS). Results always showed good conformity with the developed theoretical background under working conditions. The proposed converter found suit for (low-voltage/high current) electric vehicles, ac tractions and ‘More-Electric Aircraft’ applications....

Investigation of Power Losses of Two-Stage Two-Phase Converter with Two-Phase Motor

Directory of Open Access Journals (Sweden)

Michal Prazenica

2011-01-01

Full Text Available The paper deals with determination of losses of two-stage power electronic system with two-phase variable orthogonal output. The simulation is focused on the investigation of losses in the converter during one period in steady-state operation. Modeling and simulation of two matrix converters with R-L load is shown in the paper. The simulation results confirm a very good time-waveform of the phase current and the system seems to be suitable for low-cost application in automotive/aerospace industries and in application with high frequency voltage sources.

Implementation of high-resolution time-to-digital converter in 8-bit microcontrollers.

Science.gov (United States)

Bengtsson, Lars E

2012-04-01

This paper will demonstrate how a time-to-digital converter (TDC) with sub-nanosecond resolution can be implemented into an 8-bit microcontroller using so called "direct" methods. This means that a TDC is created using only five bidirectional digital input-output-pins of a microcontroller and a few passive components (two resistors, a capacitor, and a diode). We will demonstrate how a TDC for the range 1-10 μs is implemented with 0.17 ns resolution. This work will also show how to linearize the output by combining look-up tables and interpolation. © 2012 American Institute of Physics

The RHIC general purpose multiplexed analog to digital converter system

International Nuclear Information System (INIS)

Michnoff, R.

1995-01-01

A general purpose multiplexed analog to digital converter system is currently under development to support acquisition of analog signals for the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory. The system consists of a custom intelligent VME based controller module (V113) and a 14-bit 64 channel multiplexed A/D converter module (V114). The design features two independent scan groups, where one scan group is capable of acquiring 64 channels at 60 Hz, concurrently with the second scan group acquiring data at an aggregate rate of up to 80 k samples/second. An interface to the RHIC serially encoded event line is used to synchronize acquisition. Data is stored in a circular static RAM buffer on the controller module, then transferred to a commercial VMEbus CPU board and higher level workstations for plotting, report Generation, analysis and storage

Digital peak current mode control with adaptive slope compensation for DC-DC converters

DEFF Research Database (Denmark)

Andersen, Karsten Holm; Nymand, Morten

2017-01-01

performance and stability of current mode control. The presented method adapt to DC-DC converter operating conditions by estimating the rising and falling inductor current slopes, to apply a current slope compensation value to obtain a constant quality factor. The experimental results verifies the theoretical......This paper presents an adaptive slope compensation method for peak current mode control of digital controlled DC-DC converters, which controls the quality factor of the complex conjugated poles at half the switching frequency. Using quality factor control enables optimization of the dynamic...

Frequency to digital converter for IUAC Linac control system

International Nuclear Information System (INIS)

Jain, Mamta; Subramaiam, E.T.; Sahu, B.K.

2015-01-01

A frequency to digital converter CAMAC module has been designed and developed for LINAC control systems. This module is used to see the frequency difference of master clock and the resonator frequency digitally without using the oscilloscope. Later on this can be used for automatic tuning and locking of the cavities using piezoelectric actuator based tunner control. This module has eight independent channels to fulfill the need of all the eight cavities of the cryostat. A Schmitt trigger along with level converaccepts almost any form of pulse train, with 30 Vp-p. The time period is measured by counters clocked from a high resolution clock (10 MHz +/- 250 ps). The counter values are cross checked at both the input levels. Frequency is obtained from the computed time period by a special divisor core implemented inside the FPGA. The major task was the implementation of eight individual divisor cores and routing inside one Spartan 3s500E FPGA chip

All-optical analog-to-digital converter based on Kerr effect in photonic crystal

Science.gov (United States)

Jafari, Dariush; Nurmohammadi, Tofiq; Asadi, Mohammad Javad; Abbasian, Karim

2018-05-01

In this paper, a novel all-optical analog-to-digital converter (AOADC) is proposed and simulated for proof of principle. This AOADC is designed to operate in the range of telecom wavelength (1550 nm). A cavity made of nonlinear Kerr material in photonic crystal (PhC), is designed to achieve an optical analog-to-digital conversion with 1 Tera sample per second (TS/s) and the total footprint of 42 μm2 . The simulation is done using finite-difference time domain (FDTD) method.

Sharing of nonlinear load in parallel-connected three-phase converters

DEFF Research Database (Denmark)

Borup, Uffe; Blaabjerg, Frede; Enjeti, Prasad N.

2001-01-01

compensation are connected in parallel. Without the new solution, they are normally not able to distinguish the harmonic currents that flow to the load and harmonic currents that circulate between the converters. Analysis and experimental results on two 90-kVA 400-Hz converters in parallel are presented......In this paper, a new control method is presented which enables equal sharing of linear and nonlinear loads in three-phase power converters connected in parallel, without communication between the converters. The paper focuses on solving the problem that arises when two converters with harmonic....... The results show that both linear and nonlinear loads can be shared equally by the proposed concept....

Small-Signal Analysis of Single-Phase and Three-phase DC/AC and AC/DC PWM Converters with the Frequency-Shift Technique

DEFF Research Database (Denmark)

Blaabjerg, Frede; Aquila, A. Dell’; Liserre, Marco

2004-01-01

of dc/dc converters via a 50 Hz frequency-shift. The input admittance is calculated and measured for two study examples (a three-phase active rectifier and a single-phase photovoltaic inverter). These examples show that the purpose of a well designed controller for grid-connected converters......A systematic approach to study dc/ac and ac/dc converters without the use of synchronous transformation is proposed. The use of a frequency-shift technique allows a straightforward analysis of single-phase and three-phase systems. The study of dc/ac and of ac/dc converters is reported to the study...... is to minimize the input admittance in order to make the grid converter more robust to grid disturbance....

Full range ZVS DC-DC converter

International Nuclear Information System (INIS)

Upadhyay, Rinki; Badapanda, M.K.; Hannurkar, P.R.

2011-01-01

A 500 V, 24 Amp DC-DC converter with digital signal processor (DSP) based control and protection has been designed, fabricated and tested. Its power circuit consists of IGBT based single phase inverter bridge, ferrite transformer and diode rectifier. All IGBTs in the inverter bridge are operated in zero voltage switching (ZVS) mode to minimize switching losses thereby increasing the efficiency of the converter significantly. The efficiency of this converter is measured to be greater than 97% at full load. In a conventional full bridge inverter, typically ZVS is achieved under full load condition while at light load ZVS is lost. An auxiliary LC circuit has been intentionally incorporated in this converter to achieve ZVS even at light loaded conditions. Detailed simulation of the converter circuit is carried out and crucial waveforms have been presented in this paper. Microchip make dsPIC30F2020 DSP is employed to provide phase shifted PWMs to IGBTs in the inverter bridge. All the crucial parameters are also monitored by this DSP and in case of any unfavorable conditions, the converter is tripped off. Suitable experiments were carried out in this DC-DC converter under different loaded conditions and a close match between the simulated and experimental results were obtained. Such DC-DC converters can be connected in series or parallel for the development of solid state modular power supplies for various applications. (author)

High-power three-port three-phase bidirectional DC-DC converter

NARCIS (Netherlands)

Tao, H.; Duarte, J.L.; Hendrix, M.A.M.

2007-01-01

This paper proposes a three-port three-phase bidirectional dc-dc converter suitable for high-power applications. The converter combines a slow primary source and a fast storage to power a common load (e.g., an inverter). Since this type of system is gaining popularity in sustainable energy

High Speed Digitizer for Remote Sensing, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Alphacore, Inc. proposes to design and characterize a 24Gsps (giga-samples per-second), 6-bit, low-power, and low-cost analog-to-digital converter (ADC) for use in a...

A DC to 3-phase series-resonant converter with low harmonic distortion

NARCIS (Netherlands)

Huisman, H.; Haan, de S.W.H.

1985-01-01

A type of dc to 3-phase series-resonant converter (s.r.converter) or potentially submegawatt industrial applications is presented. The converter provides variable-frequency sine-wave currents, with low harmonic distortion at the output terminals, and with the frequency ranging from -200 through dc

Radiation-hard analog-to-digital converters for space and strategic applications

Science.gov (United States)

Gauthier, M. K.; Dantas, A. R. V.

1985-01-01

During the course of the Jet Propulsion Laboratory's program to study radiation-hardened analog-to-digital converters (ADCs), numerous milestones have been reached in manufacturers' awareness and technology development and transfer, as well as in user awareness of these developments. The testing of ADCs has also continued with twenty different ADCs from seven manufacturers, all tested for total radiation dose and three tested for neutron effects. Results from these tests are reported.

Research of digital controlled DC/DC converter based on STC12C5410AD

Science.gov (United States)

Chen, Dan-Jiang; Jin, Xin; Xiao, Zhi-Hong

2010-02-01

In order to study application of digital control technology on DC/DC converter, principle of increment mode PID control algorithm was analyzed in the paper. Then, a SCM named STC12C5410AD was introduced with its internal resources and characteristics. The PID control algorithm can be implemented easily based on it. The output of PID control was used to change the value of a variable that is 255 times than duty cycle, and this reduced the error of calculation. The valid of the presented algorithm was verified by an experiment for a BUCK DC/DC converter. The experimental results indicated that output voltage of the BUCK converter is stable with low ripple.

Adaptive Reference Levels in a Level-Crossing Analog-to-Digital Converter

Directory of Open Access Journals (Sweden)

Andrew C. Singer

2008-11-01

Full Text Available Level-crossing analog-to-digital converters (LC ADCs have been considered in the literature and have been shown to efficiently sample certain classes of signals. One important aspect of their implementation is the placement of reference levels in the converter. The levels need to be appropriately located within the input dynamic range, in order to obtain samples efficiently. In this paper, we study optimization of the performance of such an LC ADC by providing several sequential algorithms that adaptively update the ADC reference levels. The accompanying performance analysis and simulation results show that as the signal length grows, the performance of the sequential algorithms asymptotically approaches that of the best choice that could only have been chosen in hindsight within a family of possible schemes.

Energy-Efficient Capacitance-to-Digital Converters for Smart Sensor Applications

KAUST Repository

Alhoshany, Abdulaziz

2017-12-01

One of the key requirements in the design of wireless sensor nodes and miniature biomedical devices is energy efficiency. For a sensor node, which is a sensor and readout circuit, to survive on limited energy sources such as a battery or harvested energy, its energy consumption should be minimized. Capacitive sensors are candidates for use in energy-constrained applications, as they do not consume static power and can be used in a wide range of applications to measure different physical, chemical or biological quantities. However, the energy consumption is dominated by the capacitive interface circuit, i.e. the capacitance-to-digital converter (CDC). Several energy-efficient CDC architectures are introduced in this dissertation to meet the demand for high resolution and energy efficiency in smart capacitive sensors. First, we propose an energy-efficient CDC based on a differential successive-approximation data converter. The proposed differential CDC employs an energy-efficient operational transconductance amplifier (OTA) based on an inverter. A wide capacitance range with fine absolute resolution is implemented in the proposed coarse-fine DAC architecture which saves 89% of silicon area. The proposed CDC achieves an energy efficiency figure-of-merit () of 45.8fJ/step, which is the best reported energy efficiency to date. Second, we propose an energy efficient CDC for high-precision capacitive resolution by using oversampling and noise shaping. The proposed CDC achieves 150 aF absolute resolution and an energy efficiency of 187fJ/conversion-step which outperforms state of the art high-precision differential CDCs. In the third and last part, we propose an in-vitro cancer diagnostic biosensor-CMOS platform for low-power, rapid detection, and low cost. The introduced platform is the first to demonstrate the ability to screen and quantify the spermidine/spermine N1 acetyltransferase (SSAT) enzyme which reveals the presence of early-stage cancer, on the surface of a

A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

Directory of Open Access Journals (Sweden)

Sergio Saponara

2010-01-01

Full Text Available The design of a 10-bit resistor-string digital-to-analog converter (DAC for MOEMS micromirror interfacing is addressed in this paper. The proposed DAC, realized in a 0.18-μm BCD technology, features a folded resistor-string stage with a switch matrix and address decoders plus an output voltage buffer stage. The proposed DAC and buffer circuitry are key elements of an innovative scanning micromirror actuator, characterized by direct digital input, full differential driving, and linear response. With respect to the the state-of-the-art resistor-string converters in similar technologies, the proposed DAC has comparable nonlinearity (INL, DNL performances while it has the advantage of a smaller area occupation, 0.17 mm2, including output buffer, and relatively low-power consumption, 200 μW at 500 kSPS and few μW in idle mode.

General phase-frequency shifting in the three-phase inductor-converter bridge

International Nuclear Information System (INIS)

Ehsani, M.; Kustom, R.L.; Fuja, R.E.; Barnard, T.J.

1979-01-01

A fundamental method of shifting phase frequency in the inductor-converter bridge (ICB) for the purpose of controlling the power in real time is presented. Transient switching sequences needed to implement phase-frequency shifting can be developed by the use of this method and the other five system constraints. Two of the constraints that have been expressed in equation form so far are presented. Finally, an alternative algorithm for computing the frequency shifting transient sequences in real time is suggested

Integrated power electronic converters and digital control

CERN Document Server

Emadi, Ali; Nie, Zhong

2009-01-01

Non-isolated DC-DC ConvertersBuck ConverterBoost ConverterBuck-Boost ConverterIsolated DC-DC ConvertersFlyback ConverterForward ConverterPush-Pull ConverterFull-Bridge ConverterHalf-Bridge ConverterPower Factor CorrectionConcept of PFCGeneral Classification of PFC CircuitsHigh Switching Frequency Topologies for PFCApplication of PFC in Advanced Motor DrivesIntegrated Switched-Mode Power ConvertersSwitched-Mode Power SuppliesThe Concept of Integrated ConverterDefinition of Integrated Switched-Mode Power Supplies (ISMPS)Boost-Type Integrated TopologiesGeneral Structure of Boost-Type Integrated T

Digital simulation of FM-ZCS-quasi resonant converter fed DD servo drive using Matlab Simulink

Directory of Open Access Journals (Sweden)

Kattamuri Narasimha Rao

2009-01-01

Full Text Available This paper deals with digital simulation of FM-ZCS-quasi resonant converter fed DC servo drive using Matlab Simulink. Quasi Resonant Converter (QRC is fast replacing conventional PWM converters in high frequency operation. The salient feature of QRC is that the switching devices can be either switched on at zero voltage or switched off at zero current, so that switching losses are zero ideally. Switching stresses are low, volumes are low and power density is high. This property imparts high efficiency and high power density to the converters. The output of QRC is regulated by varying the switching frequency of the converter. Hence it is called Frequency modulated Zero current/zero voltage switching quasi resonant converter. The present work deals with simulation of DC Servo motor fed from ZCS-QRC using Matlab. Simulation results show that the ZCS-QRC's have low total harmonic distortion. The ZCS-QRC operating in half wave and full wave modes are simulated successfully. .

Isolated DC-DC Converter for Bidirectional Power Flow Controlling with Soft-Switching Feature and High Step-Up/Down Voltage Conversion

Directory of Open Access Journals (Sweden)

Chih-Lung Shen

2017-03-01

Full Text Available In this paper, a novel isolated bidirectional DC-DC converter is proposed, which is able to accomplish high step-up/down voltage conversion. Therefore, it is suitable for hybrid electric vehicle, fuel cell vehicle, energy backup system, and grid-system applications. The proposed converter incorporates a coupled inductor to behave forward-and-flyback energy conversion for high voltage ratio and provide galvanic isolation. The energy stored in the leakage inductor of the coupled inductor can be recycled without the use of additional snubber mechanism or clamped circuit. No matter in step-up or step-down mode, all power switches can operate with soft switching. Moreover, there is a inherit feature that metal–oxide–semiconductor field-effect transistors (MOSFETs with smaller on-state resistance can be adopted because of lower voltage endurance at primary side. Operation principle, voltage ratio derivation, and inductor design are thoroughly described in this paper. In addition, a 1-kW prototype is implemented to validate the feasibility and correctness of the converter. Experimental results indicate that the peak efficiencies in step-up and step-down modes can be up to 95.4% and 93.6%, respectively.

A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

International Nuclear Information System (INIS)

Santos, D.M.; Dow, S.F.; Levi, M.E.

1995-12-01

Many high energy physics and nuclear science applications require sub-nanosecond time resolution measurements over many thousands of detector channels. Phase-locked loops have been employed in the past to obtain accurate time references for these measurements. An alternative solution, based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multi-channel, time to digital converter (TDC). Complex clock generation can be, achieved by taking symmetric taps off the delay elements. The two circuits, DLL and TDC, were implemented in a CMOS 1.2μm and 0.8μm technology, respectively. Test results show a timing jitter of less than 35 ps for the DLL circuit and better solution for the TDC circuit

A High Step-Down Interleaved Buck Converter with Active-Clamp Circuits for Wind Turbines

Directory of Open Access Journals (Sweden)

Chih-Lung Shen

2012-12-01

Full Text Available In this paper, a high step-down interleaved buck coupled-inductor converter (IBCC with active-clamp circuits for wind energy conversion has been studied. In high step-down voltage applications, an IBCC can extend duty ratio and reduce voltage stresses on active switches. In order to reduce switching losses of active switches to improve conversion efficiency, a IBCC with soft-switching techniques is usually required. Compared with passive-clamp circuits, the IBCC with active-clamp circuits have lower switching losses and minimum ringing voltage of the active switches. Thus, the proposed IBCC with active-clamp circuits for wind energy conversion can significantly increase conversion efficiency. Finally, a 240 W prototype of the proposed IBCC with active-clamp circuits was built and implemented. Experimental results have shown that efficiency can reach as high as 91%. The proposed IBCC with active-clamp circuits is presented in high step-down voltage applications to verify the performance and the feasibility for energy conversion of wind turbines.

Mixed Linear/Square-Root Encoded Single Slope Ramp Provides a Fast, Low Noise Analog to Digital Converter with Very High Linearity for Focal Plane Arrays

Science.gov (United States)

Wrigley, Christopher James (Inventor); Hancock, Bruce R. (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor)

2014-01-01

An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.

Algorithmic impediments filtration using the α-truncated mean method in resolver-to-digital converter

Directory of Open Access Journals (Sweden)

Gordiyenko V. I.

2009-02-01

Full Text Available A test diagram of the microcontroller-type resolver-to-digital converter and algorithms for impediments filtration therein are developed. Experimental verification of the α-truncated mean algorithm intended for the suppression of impulse and noise interference is conducted. The test results are given.

Phase alteration compensation in reflection digital holography

International Nuclear Information System (INIS)

Rincon, O; Amezquita, R; Monroy, F

2011-01-01

The phase maps obtained from digital holographic microscopy techniques carry information about the axial lengths of the object under study. Additionally, these phase maps have information of tilt and curvatures with origin in the off-axis geometry and the magnification lenses system, respectively. Only a complete compensation of these extra phases allows a correct interpretation of the phase information. In this article a numerical strategy to compensate for these alterations is designed, using a phase mask located in different planes. This strategy is applied in the measurement of a phase steps plate using a digital holography setup.

Examples of digital simulation of AC-DC power converter with the Electromagnetic Transients Program

International Nuclear Information System (INIS)

Tanahashi, Shugo; Yamada, Shuichi; Mugishima, Mituo; Kitagawa, Shiro.

1989-03-01

This article gives a practical guidance for analysis of power converter circuits using the Electromagnetic Transients Program (EMTP). First how to use the program is shown with two simple examples; (1) a power supply with three-phase diode bridge and (2) a feedback system for current control. Then its application to more complicated system is shown with an example of a power supply for Compact Helical System (CHS), where a hybrid power supply with multi-phase diode and thyristor bridges, and two three-phase thyristor converters are driven by an AC generator. (author)

Digitally intensive DC-DC converter for extreme space environments, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — The Space Micro-Arizona State University (ASU) team will develop an all-digitally controlled, wide temperature range point-of-load switch-mode DC-DC regulator core...

Digitally intensive DC-DC converter for extreme space environments, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — The Space Micro –Arizona State University (ASU) team will develop an all-digitally controlled, wide temperature range point-of-load switch-mode DC-DC regulator core...

Improving image quality of parallel phase-shifting digital holography

International Nuclear Information System (INIS)

Awatsuji, Yasuhiro; Tahara, Tatsuki; Kaneko, Atsushi; Koyama, Takamasa; Nishio, Kenzo; Ura, Shogo; Kubota, Toshihiro; Matoba, Osamu

2008-01-01

The authors propose parallel two-step phase-shifting digital holography to improve the image quality of parallel phase-shifting digital holography. The proposed technique can increase the effective number of pixels of hologram twice in comparison to the conventional parallel four-step technique. The increase of the number of pixels makes it possible to improve the image quality of the reconstructed image of the parallel phase-shifting digital holography. Numerical simulation and preliminary experiment of the proposed technique were conducted and the effectiveness of the technique was confirmed. The proposed technique is more practical than the conventional parallel phase-shifting digital holography, because the composition of the digital holographic system based on the proposed technique is simpler.

submitter Test strategies for industrial testers for converter controls equipment

CERN Document Server

Oleniuk, P; Kasampalis, V; Nisbet, D; Todd, B; Uznański, S

2017-01-01

Power converters and their controls electronics are key elements for the operation of the CERN accelerator complex, having a direct impact on its availability. To prevent early-life failures and provide means to verify electronics, a set of industrial testers is used throughout the converters controls electronics' life cycle. The roles of the testers are to validate mass production during the manufacturing phase and to provide means to diagnose and repair failed modules that are brought back from operation. In the converter controls electronics section of the power converters group in the technology department of CERN (TE/EPC/CCE), two main test platforms have been adopted: a PXI platform for mixed analogue-digital functional tests and a JTAG Boundary-Scan platform for digital interconnection and functional tests. Depending on the functionality of the device under test, the appropriate test platforms are chosen. This paper is a follow-up to results presented at the TWEPP 2015 conference, adding the boundary s...

Delta-Sigma AD-Converters Practical Design for Communication Systems

CERN Document Server

Gaggl, Richard

2013-01-01

The emphasis of this book is on practical design aspects for broadband A/D converters for communication systems. The embedded designs are employed for transceivers in the field of ADSL solutions and WLAN applications. An area- and power-efficient realization of a converter is mandatory to remain competitive in the market. The right choice for the converter topology and architecture needs to be done very carefully to result in a competitive FOM. The book begins with a brief overview of basic concepts about ADSL and WLAN to understand the ADC requirements. At architectural level, issues on different modulator topologies are discussed employing the provided technology node. The design issues are pointed out in detail for modern digital CMOS technologies, beginning with 180nm followed by 130nm and going down to 65nm feature size. Beside practical aspects, challenges to mixed-signal design level are addressed to optimize the converters in terms of consumed chip area, power consumption and design for high yield in ...

Effects of Analog-to-Digital Converter Nonlinearities on Radar Range-Doppler Maps

Energy Technology Data Exchange (ETDEWEB)

Doerry, Armin Walter [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Dubbert, Dale F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Tise, Bertice L. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2014-07-01

Radar operation, particularly Ground Moving Target Indicator (GMTI) radar modes, are very sensitive to anomalous effects of system nonlinearities. These throw off harmonic spurs that are sometimes detected as false alarms. One significant source of nonlinear behavior is the Analog to Digital Converter (ADC). One measure of its undesired nonlinearity is its Integral Nonlinearity (INL) specification. We examine in this report the relationship of INL to GMTI performance.

Digital control of grid connected converters for distributed power generation

Energy Technology Data Exchange (ETDEWEB)

Skjellnes, Tore

2008-07-01

Pulse width modulated converters are becoming increasingly popular as their cost decreases and power rating increases. The new trend of small scale power producers, often using renewable energy sources, has created new demands for delivery of energy to the grid. A major advantage of the pulse width modulated converter is the ability to control the output voltage at any point in the voltage period. This enables rapid response to load changes and non-linear loads. In addition it can shape the voltage in response to the output current to create an outward appearance of a source impedance. This is called a virtual impedance. This thesis presents a controller for a voltage controlled three phase pulse width modulated converter. This controller enables operation in standalone mode, in parallel with other converters in a micro grid, and in parallel with a strong main grid. A time varying virtual impedance is presented which mainly attenuates reactive currents. A method of investigating the overall impedance including the virtual impedance is presented. New net standards have been introduced, requiring the converter to operate even during severe dips in the grid voltage. Experiments are presented verifying the operation of the controller during voltage dips. (Author). 37 refs., 65 figs., 10 tabs

A New Concept of Two-Stage Multi-Element Resonant-/Cyclo-Converter for Two-Phase IM/SM Motor

Directory of Open Access Journals (Sweden)

Mahmud Ali Rzig Abdalmula

2013-01-01

Full Text Available The paper deals with a new concept of power electronic two-phase system with two-stage DC/AC/AC converter and two-phase IM/PMSM motor. The proposed system consisting of two-stage converter comprises: input resonant boost converter with AC output, two-phase half-bridge cyclo-converter commutated by HF AC input voltage, and induction or synchronous motor. Such a system with AC interlink, as a whole unit, has better properties as a 3-phase reference VSI inverter: higher efficiency due to soft switching of both converter stages, higher switching frequency, smaller dimensions and weight with lesser number of power semiconductor switches and better price. In comparison with currently used conventional system configurations the proposed system features a good efficiency of electronic converters and also has a good torque overloading of two-phase AC induction or synchronous motors. Design of two-stage multi-element resonant converter and results of simulation experiments are presented in the paper.

A NOVEL THREE PHASE UNITY POWER FACTOR CONVERTER

Directory of Open Access Journals (Sweden)

Bekir Sami SAZAK

1998-03-01

Full Text Available The proposed unity power factor converter system which is able to operate from a 150V three-phase supply whilst delivering the required 200V DC voltage has been built and tested. This circuit functions as a high power factor low harmonic rectifier based on the concept that the peak capacitor voltages are proportional to the line input currents. Hence the low frequency components of the capacitor voltages are also approximately proportional to the line input currents. The system can be designed to achieve nearly sinusoidal supply input currents, when operated with discontinuous resonant capacitor voltages Output power control is achieved by variations of the IGBTs switching frequency. The converter is therefore able to compensate for any changes in the load resistance. The proposed topology offers advantages, including: a relatively simple power, control and protection circuits, high power capability, and high converter efficiencies.

Design of a 12-bit 80-MS/s CMOS digital-to-analog converter for PLC-VDSL applications

Science.gov (United States)

Ruiz-Amaya, Jesus; Delgado-Restituto, Manuel; Fernandez-Bootello, J. Francisco; de la Rosa, Jose M.

2005-06-01

This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is segmented in a unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distribute in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and it is supposed to be better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.

Evaluation of multiphoton effects in down-conversion

International Nuclear Information System (INIS)

Yoshimi, Kazuyoshi; Koshino, Kazuki

2010-01-01

Multiphoton effects in down-conversion are investigated based on the full-quantum multimode formalism by considering a three-level system as a prototype nonlinear system. We analytically derive the three-photon output wave function for two input photons, where one of the two input photons is down-converted and the other one is not. Using this output wave function, we calculate the down-conversion probability, the purity, and the fidelity to evaluate the entanglement between a down-converted photon pair and a non-down-converted photon. It is shown that the saturation effect occurs by multiphoton input and that it affects both the down-conversion probability and the quantum correlation between the down-converted photon pair and the non-down-converted photon. We also reveal the necessary conditions for multiphoton effects to be strong.

Digital quadrature phase detection

Science.gov (United States)

Smith, J.A.; Johnson, J.A.

1992-05-26

A system for detecting the phase of a frequency or phase modulated signal that includes digital quadrature sampling of the frequency or phase modulated signal at two times that are one quarter of a cycle of a reference signal apart, determination of the arctangent of the ratio of a first sampling of the frequency or phase modulated signal to the second sampling of the frequency or phase modulated signal, and a determination of quadrant in which the phase determination is increased by 2[pi] when the quadrant changes from the first quadrant to the fourth quadrant and decreased by 2[pi] when the quadrant changes from the fourth quadrant to the first quadrant whereby the absolute phase of the frequency or phase modulated signal can be determined using an arbitrary reference convention. 6 figs.

An efficiency improved single-phase PFC converter for electric vehicle charger applications

DEFF Research Database (Denmark)

Zhu, Dexuan; Tang, Yi; Jin, Chi

2013-01-01

This paper presents an efficiency improved single-phase power factor correction (PFC) converter with its target application to plug-in hybrid electric vehicle (PHEV) charging systems. The proposed PFC converter features sinusoidal input current, three-level output characteristic, and wide range...

A new 12-bit spectroscopy analog-to-digital converter type SAA intended for CAMAC acquisition systems

International Nuclear Information System (INIS)

Borsuk, S.; Kulka, Z.

1989-12-01

A new 12-bit spectroscopy analog-to-digital converter (ADC) type SAA (Successive Approximation type with channel width Averaging) intended for CAMAC acquisition systems is decsribed. ADC type SAA initiates new series of spectroscopy ADC's based on a binary-approximation method in which differential nonlinearity is corrected by a statistical channel width averaging method. The structure and principle of operation, as well as some circuit realizations and specifications of the new converter are described. 41 refs., 5 figs. (author)

High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Ridgetop Group will design a high-speed, low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming...

Analog-to-digital conversion

CERN Document Server

Pelgrom, Marcel J M

2010-01-01

The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for...

RF applications in digital signal processing

CERN Document Server

Schilcher, T

2008-01-01

Ever higher demands for stability, accuracy, reproducibility, and monitoring capability are being placed on Low-Level Radio Frequency (LLRF) systems of particle accelerators. Meanwhile, continuing rapid advances in digital signal processing technology are being exploited to meet these demands, thus leading to development of digital LLRF systems. The rst part of this course will begin by focusing on some of the important building-blocks of RF signal processing including mixer theory and down-conversion, I/Q (amplitude and phase) detection, digital down-conversion (DDC) and decimation, concluding with a survey of I/Q modulators. The second part of the course will introduce basic concepts of feedback systems, including examples of digital cavity eld and phase control, followed by radial loop architectures. Adaptive feed-forward systems used for the suppression of repetitive beam disturbances will be examined. Finally, applications and principles of system identi cation approaches will be summarized.

Analog Fixed Maximum Power Point Control for a PWM Step-downConverter for Water Pumping Installations

DEFF Research Database (Denmark)

Beltran, H.; Perez, E.; Chen, Zhe

2009-01-01

This paper describes a Fixed Maximum Power Point analog control used in a step-down Pulse Width Modulated power converter. The DC/DC converter drives a DC motor used in small water pumping installations, without any electric storage device. The power supply is provided by PV panels working around....... The proposed Optimal Power Point fix voltage control system is analyzed in comparison to other complex controls....... their maximum power point, with a fixed operating voltage value. The control circuit implementation is not only simple and cheap, but also robust and reliable. System protections and adjustments are also proposed. Simulations and hardware are reported in the paper for a 150W water pumping application system...

Fermilab Recycler Ring BPM Upgrade Based on Digital Receiver Technology

Science.gov (United States)

Webber, R.; Crisp, J.; Prieto, P.; Voy, D.; Briegel, C.; McClure, C.; West, R.; Pordes, S.; Mengel, M.

2004-11-01

Electronics for the 237 BPMs in the Fermilab Recycler Ring have been upgraded from a log-amplifier based system to a commercially produced digitizer-digital down converter based system. The hardware consists of a pre-amplifier connected to a split-plate BPM, an analog differential receiver-filter module and an 8-channel 80-MHz digital down converter VME board. The system produces position and intensity with a dynamic range of 30 dB and a resolution of ±10 microns. The position measurements are made on 2.5-MHz bunched beam and barrier buckets of the un-bunched beam. The digital receiver system operates in one of six different signal processing modes that include 2.5-MHz average, 2.5-MHz bunch-by-bunch, 2.5-MHz narrow band, unbunched average, un-bunched head/tail and 89-kHz narrow band. Receiver data is acquired on any of up to sixteen clock events related to Recycler beam transfers and other machine activities. Data from the digital receiver board are transferred to the front-end CPU for position and intensity computation on an on-demand basis through the VME bus. Data buffers are maintained for each of the acquisition events and support flash, closed orbit and turn-by-turn measurements. A calibration system provides evaluation of the BPM signal path and application programs.

Digital phase-shifting atomic force microscope Moire method

International Nuclear Information System (INIS)

Liu Chiaming; Chen Lienwen

2005-01-01

In this study, the digital atomic force microscope (AFM) Moire method with phase-shifting technology is established to measure the in-plane displacement and strain fields. The Moire pattern is generated by the interference between the specimen grating and the virtual reference grating formed by digital image processes. The overlapped image is filtered by two-dimensional wavelet transformation to obtain the clear interference Moire patterns. The four-step phase-shifting method is realized by translating the phase of the virtual reference grating from 0 to 2π. The principle of the digital AFM Moire method and the phase-shifting technology are described in detail. Experimental results show that this method is convenient to use and efficient in realizing the microscale measurement

7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

KAUST Repository

Omran, Hesham

2014-08-01

In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35-μm CMOS process occupies 0.09 mm2 and consumes a total of 153 μA from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step. © 2004-2012 IEEE.

7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

KAUST Repository

Omran, Hesham; Arsalan, Muhammad; Salama, Khaled N.

2014-01-01

In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35-μm CMOS process occupies 0.09 mm2 and consumes a total of 153 μA from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step. © 2004-2012 IEEE.

Indirect Matrix Converter for Hybrid Electric Vehicle Application with Three-Phase and Single-Phase Outputs

Directory of Open Access Journals (Sweden)

Yeongsu Bak

2015-04-01

Full Text Available This paper presents an indirect matrix converter (IMC topology for hybrid electric vehicle (HEV application with three-phase and single-phase outputs. The HEV includes mechanical, electrical, control, and electrochemical systems among others. In the mechanical system, a traction motor and a compressor motor are used to drive the HEV. The traction motor and the compressor motor are usually operated as three-phase and single-phase motors, respectively. In this respect, a dual AC-drive system can operate the traction and the compressor motor simultaneously. Furthermore, compared to a conventional dual matrix converter system, the proposed topology can reduce the number of switches that the dual outputs share with a DC-link. The application of this system for HEV has advantages, like long lifetime and reduced volume due to the lack of a DC-link. The proposed control strategy and modulation schemes ensure the sinusoidal input and output waveforms and bidirectional power transmission. The proposed system for the HEV application is verified by simulation and experiments.

Development of a fast time-to-digital converter (TDC) using a programmable gate array

International Nuclear Information System (INIS)

Mine, Shun-ichi; Tokushuku, Katsuo; Yamada, Sakue.

1994-09-01

A fast time-to-digital converter with a 5 ns step was designed and tested by utilizing a user-programmable gate array. The stabilities against temperature and supply voltage variation were measured. A module was built with this TDC, and was successfully used in the first-level trigger system of the ZEUS detector to reject proton-beam induced background events. (author)

The H1 SPACAL time-to-digital converter system

International Nuclear Information System (INIS)

Eisenhandler, E.; Landon, M.; Thompson, G.

1995-01-01

This paper describes a pipelined 1,400-channel Time-to-Digital Converter (TDC) system for the H1 Scintillating Fiber Calorimeter, which will soon be installed in the H1 experiment at DESY. The main task of the TDC system is to determine the time of arrival of energy depositions, and send this information from bunch crossings that satisfy the event trigger into the H1 data acquisition system. In addition, the TDC system must monitor the timing trigger, which vetoes bunch crossings that contain too much background energy. Products of the interaction are separated from background on the basis of their different times of arrival with respect to the bunch crossing clock. For this monitoring the TDC system uses automatic on-board histogramming hardware that produces a family of histograms for each of 1,400 channels. The TDC function is performed by the TMC1004 ASIC. The system digitizes over a range of 32ns per bunch crossing with 1ns bins and a precision of 1ns. Because of the way the TMC1004 is designed, it is possible to vary the size of the bins between 0.6ns and 3ns by trading off measurement range for bin size. The system occupies two 9U VME crates

A new delay line loops shrinking time-to-digital converter in low-cost FPGA

Energy Technology Data Exchange (ETDEWEB)

Zhang, Jie, E-mail: zhangjie071063@163.com [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China); University of Chinese Academy of Sciences, Beijing, China, 100049 (China); Zhou, Dongming [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China)

2015-01-21

The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage.

A new delay line loops shrinking time-to-digital converter in low-cost FPGA

International Nuclear Information System (INIS)

Zhang, Jie; Zhou, Dongming

2015-01-01

The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage

An Integrated Inductor For Parallel Interleaved Three-Phase Voltage Source Converters

DEFF Research Database (Denmark)

Gohil, Ghanshyamsinh Vijaysinh; Bede, Lorand; Teodorescu, Remus

2016-01-01

Three phase Voltage Source Converters (VSCs) are often connected in parallel to realize high current output converter system. The harmonic quality of the resultant switched output voltage can be improved by interleaving the carrier signals of these parallel connected VSCs. As a result, the line...... of the state-of-the-art filtering solution. The performance of the integrated inductor is also verified by the experimental measurements....

Robust control of boost PFC converter using adaptive PLL for line synchronization

DEFF Research Database (Denmark)

Török, Lajos; Mathe, Laszlo; Munk-Nielsen, Stig

2013-01-01

The continuous development of the digital processing technology made advanced control strategies available for switched-mode power-supply applications. This paper presents the study and implementation of an adaptive Phased-Locked Loop (PLL)-based grid-fault tolerant control of a boost PFC converter...

47 CFR 15.122 - Closed caption decoder requirements for digital television receivers and converter boxes.

Science.gov (United States)

2010-10-01

... 47 Telecommunication 1 2010-10-01 2010-10-01 false Closed caption decoder requirements for digital television receivers and converter boxes. 15.122 Section 15.122 Telecommunication FEDERAL COMMUNICATIONS... code spaces C2, C3, and G3 is optional. All unsupported graphic symbols in the G3 code space are to be...

A Three-Phase Boost DC-AC Converter | Odeh | Nigerian Journal of ...

African Journals Online (AJOL)

Sliding mode controllers are designed to perform a robust control for the three boost dc-dc converters. Computer simulations and spectral analysis demonstrate the feasibility of the proposed three-phase inverter. The inverter is intended to be used in three-phase electric drives and uninterruptible power supply (UPS) ...

Decentralized Interleaving of Paralleled Dc-Dc Buck Converters: Preprint

Energy Technology Data Exchange (ETDEWEB)

Johnson, Brian B [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Rodriguez, Miguel [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Sinha, Mohit [University of Minnesota; Dhople, Sairaj [University of Minnesota; Poon, Jason [University of California at Berkeley

2017-09-01

We present a decentralized control strategy that yields switch interleaving among parallel connected dc-dc buck converters without communication. The proposed method is based on the digital implementation of the dynamics of a nonlinear oscillator circuit as the controller. Each controller is fully decentralized, i.e., it only requires the locally measured output current to synthesize the pulse width modulation (PWM) carrier waveform. By virtue of the intrinsic electrical coupling between converters, the nonlinear oscillator-based controllers converge to an interleaved state with uniform phase-spacing across PWM carriers. To the knowledge of the authors, this work represents the first fully decentralized strategy for switch interleaving of paralleled dc-dc buck converters.

Radiation-tolerant delta-sigma time-to-digital converters

CERN Document Server

Cao, Ying; Steyaert, Michiel

2015-01-01

This book focuses on the design of a Mega-Gray (a standard unit of total ionizing radiation) radiation-tolerant ps-resolution time-to-digital converter (TDC) for a light detection and ranging (LIDAR) system used in a gamma-radiation environment. Several radiation-hardened-by-design (RHBD) techniques are demonstrated throughout the design of the TDC and other circuit techniques to improve the TDC's resolution in a harsh environment are also investigated. Readers can learn from scratch how to design a radiation-tolerant IC. Information regarding radiation effects, radiation-hardened design techniques and  measurements are organized in such a way that readers can easily gain a thorough understanding of the topic. Readers will also learn the design theory behind the newly proposed delta-sigma TDC. Readers can quickly acquire knowledge about the design of radiation-hardened bandgap voltage references and low-jitter relaxation oscillators, which are introduced in the content from a designer's perspective.   · �...

A Digitally Controlled Power Converter for an Electrostatic Precipitator

Directory of Open Access Journals (Sweden)

Pedro J. Villegas

2017-12-01

Full Text Available Electrostatic precipitators (ESPs are devices used in industry to eliminate polluting particles in gases. In order to supply them, an interface must be included between the three-phase main line and the required high DC voltage of tens of kilovolts. This paper describes an 80-kW power supply for such an application. Its structure is based on the series parallel resonant converter with a capacitor as output filter (PRC-LCC, which can adequately cope with the parasitic elements of the step-up transformer involved. The physical implementation of the prototype includes the use of silicon carbide—SiC—semiconductors, which provide better switching capabilities than their traditional silicon—Si—counterparts. As a result, a new control strategy results as a better alternative in which the resonant current is maintained in phase with the first harmonic of the inverter voltage. Although this operation mode imposes hard switching in one of the inverter legs, it minimizes the reactive energy that circulates through the resonant tank, the resonant current amplitude itself and the switching losses. Overall efficiency of the converter benefits from this. These ideas are supported mathematically using the steady state and dynamic models of the topology. They are confirmed with experimental measurements that include waveforms, Bode plots and thermal behavior. The experimental setup delivers 80 kW with an estimated efficiency of 98%.

A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

International Nuclear Information System (INIS)

Chen Kai; Liu Shubin; An Qi

2010-01-01

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA's Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable. (authors)

Single-shot femtosecond-pulsed phase-shifting digital holography.

Science.gov (United States)

Kakue, Takashi; Itoh, Seiya; Xia, Peng; Tahara, Tatsuki; Awatsuji, Yasuhiro; Nishio, Kenzo; Ura, Shogo; Kubota, Toshihiro; Matoba, Osamu

2012-08-27

Parallel phase-shifting digital holography is capable of three-dimensional measurement of a dynamically moving object with a single-shot recording. In this letter, we demonstrated a parallel phase-shifting digital holography using a single femtosecond light pulse whose central wavelength and temporal duration were 800 nm and 96 fs, respectively. As an object, we set spark discharge in atmospheric pressure air induced by applying a high voltage to between two electrodes. The instantaneous change in phase caused by the spark discharge was clearly reconstructed. The reconstructed phase image shows the change of refractive index of air was -3.7 × 10(-4).

A novel double quad-inverter configuration for multilevel twelve-phase open-winding converter

DEFF Research Database (Denmark)

Padmanaban, Sanjeevi Kumar; Blaabjerg, Frede; Wheeler, Patrick William

2016-01-01

This paper describes a novel proposal of double quad-inverter configuration for multilevel twelve-phase open-winding ac converter. Modular power units are developed from reconfigured eight classical three-phase voltage source inverters (VSIs). Each VSI has one additional bi-directional switching...... numerical simulation software's (Matlab/PLECS) developments. Further, the results confirm the good agreement to the developed theoretical background. Proposed converter suits the need of low-voltage/high-current applications such as ac tractions and `More-Electric Aircraft' propulsion systems....

Grid converter for LED based intelligent light sources

DEFF Research Database (Denmark)

Török, Lajos

The purpose of this thesis was to investigate the applicability and effects of digital control to line connected switched mode power supplies with power factor correction. The main approach was cost effectiveness with high efficiency. This involved hardware design for increased switching frequency...... and their implemented control algorithms. As digital control has to be competitive with the existing solutions it was investigated what digital signal processing solutions exist. A performance and cost comparison was also presented. The chosen converter topologies were thoroughly analyzed. Different converters were...... chosen for different power levels. At low power simple boost converter as power factor corrector (PFC) and a RCD-clamped forward converter was chosen as DC-DC converter. This with has double output and coupled lter inductor. To design a digital controller with the tools of the classical control theory...

Converting analog interpretive data to digital formats for use in database and GIS applications

Science.gov (United States)

Flocks, James G.

2004-01-01

There is a growing need by researchers and managers for comprehensive and unified nationwide datasets of scientific data. These datasets must be in a digital format that is easily accessible using database and GIS applications, providing the user with access to a wide variety of current and historical information. Although most data currently being collected by scientists are already in a digital format, there is still a large repository of information in the literature and paper archive. Converting this information into a format accessible by computer applications is typically very difficult and can result in loss of data. However, since scientific data are commonly collected in a repetitious, concise matter (i.e., forms, tables, graphs, etc.), these data can be recovered digitally by using a conversion process that relates the position of an attribute in two-dimensional space to the information that the attribute signifies. For example, if a table contains a certain piece of information in a specific row and column, then the space that the row and column occupies becomes an index of that information. An index key is used to identify the relation between the physical location of the attribute and the information the attribute contains. The conversion process can be achieved rapidly, easily and inexpensively using widely available digitizing and spreadsheet software, and simple programming code. In the geological sciences, sedimentary character is commonly interpreted from geophysical profiles and descriptions of sediment cores. In the field and laboratory, these interpretations were typically transcribed to paper. The information from these paper archives is still relevant and increasingly important to scientists, engineers and managers to understand geologic processes affecting our environment. Direct scanning of this information produces a raster facsimile of the data, which allows it to be linked to the electronic world. But true integration of the content with

Down sampled signal processing for a B Factory bunch-by-bunch feedback system

International Nuclear Information System (INIS)

Hindi, H.; Hosseini, W.; Briggs, D.; Fox, J.; Hutton, A.

1992-03-01

A bunch-by-bunch feedback scheme is studied for damping coupled bunch synchrotron oscillations in the proposed PEP II B Factory. The quasi-linear feedback systems design incorporates a phase detector to provide a quantized measure of bunch phase, digital signal processing to compute an error correction signal and a kicker system to correct the energy of the bunches. A farm of digital processors, operating in parallel, is proposed to compute correction signals for the 1658 bunches of the B Factory. This paper studies the use of down sampled processing to reduce the computational complexity of the feedback system. We present simulation results showing the effect of down sampling on beam dynamics. Results show that down sampled processing can reduce the scale of the processing task by a factor of 10

Hybrid Modulation of Bidirectional Three-Phase Dual-Active-Bridge DC Converters for Electric Vehicles

Directory of Open Access Journals (Sweden)

Yen-Ching Wang

2016-06-01

Full Text Available Bidirectional power converters for electric vehicles (EVs have received much attention recently, due to either grid-supporting requirements or emergent power supplies. This paper proposes a hybrid modulation of the three-phase dual-active bridge (3ΦDAB converter for EV charging systems. The designed hybrid modulation allows the converter to switch its modulation between phase-shifted and trapezoidal modes to increase the conversion efficiency, even under light-load conditions. The mode transition is realized in a real-time manner according to the charging or discharging current. The operation principle of the converter is analyzed in different modes and thus design considerations of the modulation are derived. A lab-scaled prototype circuit with a 48V/20Ah LiFePO4 battery is established to validate the feasibility and effectiveness.

New down-converter for UV-stable perovskite solar cells: Phosphor-in-glass

Science.gov (United States)

Roh, Hee-Suk; Han, Gill Sang; Lee, Seongha; Kim, Sanghyun; Choi, Sungwoo; Yoon, Chulsoo; Lee, Jung-Kun

2018-06-01

Degradation of hybrid lead halide perovskite by UV light is a crucial issue that limits the commercialization of lead halide perovskite solar cells (PSCs). To address this problem, phosphor-in-glass (PiG) is used to convert UV to visible light. Down-conversion of UV light by PiG dramatically increases UV-stability of PSCs and enables PSCs to harvest UV light that is currently wasted. Performance of PSCs with PiG layer does not change significantly during 100 h-long UV-irradiation, while conventional PSCs degrade quickly by 1 h-long UV-irradiation. After 100 h long UV-irradiation, power conversion efficiency of PSCs with PiG is 440% larger than that of conventional PSCs. This result points a direction toward PSCs which are very stable and highly efficient under UV light.

Bandwidth broadening of a graphene-based circular polarization converter by phase compensation.

Science.gov (United States)

Gao, Xi; Yang, Wanli; Cao, Weiping; Chen, Ming; Jiang, Yannan; Yu, Xinhua; Li, Haiou

2017-10-02

We present a broadband tunable circular polarization converter composed of a single graphene sheet patterned with butterfly-shaped holes, a dielectric spacer, and a 7-layer graphene ground plane. It can convert a linearly polarized wave into a circularly polarized wave in reflection mode. The polarization converter can be dynamically tuned by varying the Fermi energy of the single graphene sheet. Furthermore, the 7-layer graphene acting as a ground plane can modulate the phase of its reflected wave by controlling the Femi energy, which provides constructive interference condition at the surface of the single graphene sheet in a broad bandwidth and therefore significantly broadens the tunable bandwidth of the proposed polarization converter.

Power quality improvement by using multi-pulse AC-DC converters for DC drives: Modeling, simulation and its digital implementation

Directory of Open Access Journals (Sweden)

Mohd Tariq

2014-12-01

Full Text Available The paper presents the modeling, simulation and digital implementation of power quality improvement of DC drives by using multi pulse AC–DC converter. As it is a well-known fact that power quality determines the fitness of electrical power to consumer devices, hence an effort has been made to improve power quality in this work. Simulation and digital implementation with the help of MATLAB/Simulink has been done and results obtained are discussed in detail to verify the theoretical results. The multipulse converter was connected with DC drives and was run at no load condition to find out the transient and steady state performances. FFT analysis has been performed and Total Harmonic Distortion (THD results obtained at different pulses are shown here.

A Calibration Method for Nonlinear Mismatches in M-Channel Time-Interleaved Analog-to-Digital Converters Based on Hadamard Sequences

Directory of Open Access Journals (Sweden)

Husheng Liu

2016-11-01

Full Text Available The time-interleaved analog-to-digital converter (TIADC is an architecture used to achieve a high sampling rate and high dynamic performance. However, estimation and compensation methods are required to maintain the dynamic performance of the constituent analog-to-digital converters (ADCs due to channel mismatches. This paper proposes a blind adaptive method to calibrate the nonlinear mismatches in M-channel TIADCs (M-TIADCs. The nonlinearity-induced error signal is reconstructed by the proposed multiplier Hadamard transform (MHT structure, and the nonlinear parameters are estimated by the filtered-X least-mean square (FxLMS algorithm. The performance of cascade calibration is also analyzed. The numerical simulation results show that the proposed method consumes much less hardware resources while maintaining the calibration performance.

Test strategies for industrial testers for converter controls equipment

International Nuclear Information System (INIS)

Oleniuk, P.; Kasampalis, V.; Cosmo, M. Di; Nisbet, D.; Todd, B.; Uznański, S.

2017-01-01

Power converters and their controls electronics are key elements for the operation of the CERN accelerator complex, having a direct impact on its availability. To prevent early-life failures and provide means to verify electronics, a set of industrial testers is used throughout the converters controls electronics' life cycle. The roles of the testers are to validate mass production during the manufacturing phase and to provide means to diagnose and repair failed modules that are brought back from operation. In the converter controls electronics section of the power converters group in the technology department of CERN (TE/EPC/CCE), two main test platforms have been adopted: a PXI platform for mixed analogue-digital functional tests and a JTAG Boundary-Scan platform for digital interconnection and functional tests. Depending on the functionality of the device under test, the appropriate test platforms are chosen. This paper is a follow-up to results presented at the TWEPP 2015 conference, adding the boundary scan test platform and the first results from exploitation of the test system. This paper reports on the test software, hardware design and test strategy applied for a number of devices that has resulted in maximizing test coverage and minimizing test design effort.

Energy-efficient three-phase bidirectional converter for grid-connected storage applications

International Nuclear Information System (INIS)

Colmenar-Santos, Antonio; Linares-Mena, Ana-Rosa; Velázquez, Jesús Fernández; Borge-Diez, David

2016-01-01

Highlights: • Storage control system developed based on AC DC three phase bidirectional converter. • Bidirectional AC DC converter for storage integration into distribution grids. • Efficiencies over 98% for values over 30% of the bidirectional converter rated power. • Sensitivity analysis of the parameters set by the transmission system operator. • Low-cost option for control and integration of new grid-connected storage systems. - Abstract: Grid connected energy storage systems are expected to play an essential role in the development of Smart Grids, providing, among other benefits, ancillary services to power grids. It is therefore crucial to design and develop control and conversion systems that represent the key instrument where intelligence for decision-making is applied, in order to validate and ensure its optimal operation as part and parcel of the electrical system. The present research describes the design and development of a battery energy storage system based on an AC-DC three-phase bidirectional converter capable of operating either in charge mode to store electrical energy, or in discharge mode to supply load demands. The design is modelled with MATLAB® Simulink® environment in order to evaluate the performance during load variations. Moreover, the assessment is complemented by a global sensitivity analysis for variations in the operating parameters set by the transmission system operator. The effectiveness of the simulation is confirmed by implementing the system and carrying out grid connection tests, obtaining efficiencies over 98% for values over the 30% of the bidirectional converter rated power.

A high-resolution, multi-stop, time-to-digital converter for nuclear time-of-flight measurements

International Nuclear Information System (INIS)

Spencer, D.F.; Cole, J.; Drigert, M.; Aryaeinejad, R.

2006-01-01

A high-resolution, multi-stop, time-to-digital converter (TDC) was designed and developed to precisely measure the times-of-flight (TOF) of incident neutrons responsible for induced fission and capture reactions on actinide targets. The minimum time resolution is ±1 ns. The TDC design was implemented into a single, dual-wide CAMAC module. The CAMAC bus is used for command and control as well as an alternative data output. A high-speed ECL interface, compatible with LeCroy FERA modules, was also provided for the principle data output path. An Actel high-speed field programmable gate array (FPGA) chip was incorporated with an external oscillator and an internal multiple clock phasing system. This device implemented the majority of the high-speed register functions, the state machine for the FERA interface, and the high-speed counting circuit used for the TDC conversion. An external microcontroller was used to monitor and control system-level changes. In this work we discuss the performance of this TDC module as well as its application

Reduction of the jitter of single-flux-quantum time-to-digital converters for time-of-flight mass spectrometry

International Nuclear Information System (INIS)

Sano, K.; Muramatsu, Y.; Yamanashi, Y.; Yoshikawa, N.; Zen, N.; Ohkubo, M.

2014-01-01

Highlights: • We proposed single-flux-quantum (SFQ) time-to-digital converters (TDCs) for TOF-MS. • SFQ TDC can measure time intervals between multiple signals with high-resolution. • SFQ TDC can directly convert the time intervals into binary data. • We designed two types of SFQ TDCs to reduce the jitter. • The jitter is reduced to less than 100 ps. - Abstract: We have been developing a high-resolution superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconducting strip ion detector (SSID) and a single-flux-quantum (SFQ) time-to-digital converter (TDC). The SFQ TDC can measure time intervals between multiple input signals and directly convert them into binary data. In our previous study, 24-bit SFQ TDC with a 3 × 24-bit First-In First-Out (FIFO) buffer was designed and implemented using the AIST Nb standard process 2 (STP2), whose time resolution and dynamic range are 100 ps and 1.6 ms, respectively. In this study we reduce the jitter of the TDC by using two different approaches: one uses an on-chip clock generator with an on-chip low-pass filter for reducing the noise in the bias current, and the other uses a low-jitter external clock source at room temperature. We confirmed that the jitter is reduced to less than 100 ps in the latter approach

Reduction of the jitter of single-flux-quantum time-to-digital converters for time-of-flight mass spectrometry

Energy Technology Data Exchange (ETDEWEB)

Sano, K., E-mail: sano-kyosuke-cw@ynu.jp [Department Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501 (Japan); Muramatsu, Y.; Yamanashi, Y.; Yoshikawa, N. [Department Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501 (Japan); Zen, N.; Ohkubo, M. [Research Institute of Instrumentation Frontier, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba 305-8568 (Japan)

2014-09-15

Highlights: • We proposed single-flux-quantum (SFQ) time-to-digital converters (TDCs) for TOF-MS. • SFQ TDC can measure time intervals between multiple signals with high-resolution. • SFQ TDC can directly convert the time intervals into binary data. • We designed two types of SFQ TDCs to reduce the jitter. • The jitter is reduced to less than 100 ps. - Abstract: We have been developing a high-resolution superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconducting strip ion detector (SSID) and a single-flux-quantum (SFQ) time-to-digital converter (TDC). The SFQ TDC can measure time intervals between multiple input signals and directly convert them into binary data. In our previous study, 24-bit SFQ TDC with a 3 × 24-bit First-In First-Out (FIFO) buffer was designed and implemented using the AIST Nb standard process 2 (STP2), whose time resolution and dynamic range are 100 ps and 1.6 ms, respectively. In this study we reduce the jitter of the TDC by using two different approaches: one uses an on-chip clock generator with an on-chip low-pass filter for reducing the noise in the bias current, and the other uses a low-jitter external clock source at room temperature. We confirmed that the jitter is reduced to less than 100 ps in the latter approach.

A zero-voltage-switched three-phase interleaved buck converter

Science.gov (United States)

Hsieh, Yao-Ching; Huang, Bing-Siang; Lin, Jing-Yuan; Pham, Phu Hieu; Chen, Po-Hao; Chiu, Huang-Jen

2018-04-01

This paper proposes a three-phase interleaved buck converter which is composed of three identical paralleled buck converters. The proposed solution has three shunt inductors connected between each other of three basic buck conversion units. With the help of the shunt inductors, the MOSFET parasitic capacitances will resonate to achieve zero-voltage-switching. Furthermore, the decreasing rate of the current through the free-wheeling diodes is limited, and therefore, their reverse-recovery losses can be minimised. The active power switches are controlled by interleaved pulse-width modulation signals to reduce the input and output current ripples. Therefore, the filtering capacitances on the input and output sides can be reduced. The power efficiency is measured to be as high as 98% in experiment with a prototype circuit.

Digital to Analog Converter Description

NARCIS (Netherlands)

van Tuijl, Adrianus Johannes Maria

2002-01-01

A circuit for analogue to digital or digital to analogue conversion comprising at least 2n matched current sources (40-1, 40-2, 40-n), where n is the resolution required of the conversion. Preferably more than 2n current sources (40-1, 40-2, 40-n) are used. The order in which the sources (40-1,

Power loss benchmark of nine-switch converters in three-phase online-UPS application

DEFF Research Database (Denmark)

Qin, Zian; Loh, Poh Chiang; Blaabjerg, Frede

2014-01-01

Three-phase online-UPS is an appropriate application for the nine-switch converter, where its high voltage stress of the power device caused by the reduced switch feature can be relieved significantly. Its power loss and loss distribution still have the flexibility from the control point of view...... as parameters like modulation index and phase angle of the load are taken into account. The benchmark of power loss will become a guidance for the users to make best use of the advantages and bypass the disadvantages of nine-switch converters. The results are finally verified on a 1.5 kW prototype....

Phase-locked loops. [in analog and digital circuits communication system

Science.gov (United States)

Gupta, S. C.

1975-01-01

An attempt to systematically outline the work done in the area of phase-locked loops which are now used in modern communication system design is presented. The analog phase-locked loops are well documented in several books but discrete, analog-digital, and digital phase-locked loop work is scattered. Apart from discussing the various analysis, design, and application aspects of phase-locked loops, a number of references are given in the bibliography.

3600 digital phase detector with 100-kHz bandwidth

International Nuclear Information System (INIS)

Reid, D.W.; Riggin, D.; Fazio, M.V.; Biddle, R.S.; Patton, R.D.; Jackson, H.A.

1981-01-01

The general availability of digital circuit components with propagation delay times of a few nanoseconds makes a digital phase detector with good bandwidth feasible. Such a circuit has a distinct advantage over its analog counterpart because of its linearity over wide range of phase shift. A phase detector that is being built at Los Alamos National Laboratory for the Fusion Materials Irradiation Test (FMIT) project is described. The specifications are 100-kHz bandwidth, linearity of +- 1 0 over +- 180 0 of phase shift, and 0.66 0 resolution. To date, the circuit has achieved the bandwidth and resolution. The linearity is approximately +- 3 0 over +- 180 0 phase shift

Digital polarization holography advancing geometrical phase optics.

Science.gov (United States)

De Sio, Luciano; Roberts, David E; Liao, Zhi; Nersisyan, Sarik; Uskova, Olena; Wickboldt, Lloyd; Tabiryan, Nelson; Steeves, Diane M; Kimball, Brian R

2016-08-08

Geometrical phase or the fourth generation (4G) optics enables realization of optical components (lenses, prisms, gratings, spiral phase plates, etc.) by patterning the optical axis orientation in the plane of thin anisotropic films. Such components exhibit near 100% diffraction efficiency over a broadband of wavelengths. The films are obtained by coating liquid crystalline (LC) materials over substrates with patterned alignment conditions. Photo-anisotropic materials are used for producing desired alignment conditions at the substrate surface. We present and discuss here an opportunity of producing the widest variety of "free-form" 4G optical components with arbitrary spatial patterns of the optical anisotropy axis orientation with the aid of a digital spatial light polarization converter (DSLPC). The DSLPC is based on a reflective, high resolution spatial light modulator (SLM) combined with an "ad hoc" optical setup. The most attractive feature of the use of a DSLPC for photoalignment of nanometer thin photo-anisotropic coatings is that the orientation of the alignment layer, and therefore of the fabricated LC or LC polymer (LCP) components can be specified on a pixel-by-pixel basis with high spatial resolution. By varying the optical magnification or de-magnification the spatial resolution of the photoaligned layer can be adjusted to an optimum for each application. With a simple "click" it is possible to record different optical components as well as arbitrary patterns ranging from lenses to invisible labels and other transparent labels that reveal different images depending on the side from which they are viewed.

High accuracy amplitude and phase measurements based on a double heterodyne architecture

International Nuclear Information System (INIS)

Zhao Danyang; Wang Guangwei; Pan Weimin

2015-01-01

In the digital low level RF (LLRF) system of a circular (particle) accelerator, the RF field signal is usually down converted to a fixed intermediate frequency (IF). The ratio of IF and sampling frequency determines the processing required, and differs in various LLRF systems. It is generally desirable to design a universally compatible architecture for different IFs with no change to the sampling frequency and algorithm. A new RF detection method based on a double heterodyne architecture for wide IF range has been developed, which achieves the high accuracy requirement of modern LLRF. In this paper, the relation of IF and phase error is systematically analyzed for the first time and verified by experiments. The effects of temperature drift for 16 h IF detection are inhibited by the amplitude and phase calibrations. (authors)

In-line digital holography with phase-shifting Greek-ladder sieves

Science.gov (United States)

Xie, Jing; Zhang, Junyong; Zhang, Yanli; Zhou, Shenlei; Zhu, Jianqiang

2018-04-01

Phase shifting is the key technique in in-line digital holography, but traditional phase shifters have their own limitations in short wavelength regions. Here, phase-shifting Greek-ladder sieves with amplitude-only modulation are introduced into in-line digital holography, which are essentially a kind of diffraction lens with three-dimensional array diffraction-limited foci. In the in-line digital holographic experiment, we design two kinds of sieves by lithography and verify the validity of their phase-shifting function by measuring a 1951 U.S. Air Force resolution test target and three-dimensional array foci. With advantages of high resolving power, low cost, and no limitations at shorter wavelengths, phase-shifting Greek-ladder sieves have great potential in X-ray holography or biochemical microscopy for the next generation of synchrotron light sources.

Power Controllability of Three-phase Converter with Unbalanced AC Source

DEFF Research Database (Denmark)

Ma, Ke; Chen, Wenjie; Liserre, Marco

2015-01-01

Three-phase DC-AC power converters suffer from power oscillation and overcurrent problems in case of unbalanced AC source voltage that can be caused by grid/generator faults. Existing solutions to handle these problems are properly selecting and controlling the positive and negative sequence...... currents. In this work a new series of control strategies which utilize the zerosequence components are proposed to enhance the power control ability under this adverse condition. It is concluded that by introducing proper zero sequence current controls and corresponding circuit configurations, the power...... converter can enable more flexible control targets, achieving better performances in the delivered power and load current when suffering from unbalanced AC voltage....

High Performance Ultra Low-Power ADCs and DACs, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — The objective of the Phase-I research is to design a multi-GHz high bandwidth Delta Sigma Analog-to-Digital and Digital-to-Analog converter using a deep sub-micron...

Energy down converting organic fluorophore functionalized mesoporous silica hybrids for monolith-coated light emitting diodes

Directory of Open Access Journals (Sweden)

Markus Börgardts

2017-04-01

Full Text Available The covalent attachment of organic fluorophores in mesoporous silica matrices for usage as energy down converting phosphors without employing inorganic transition or rare earth metals is reported in this article. Triethoxysilylpropyl-substituted derivatives of the blue emitting perylene, green emitting benzofurazane, and red emitting Nile red were synthesized and applied in the synthesis of mesoporous hybrid materials by postsynthetic grafting to commercially available MCM-41. These individually dye-functionalized hybrid materials are mixed in variable ratios to furnish a powder capable of emitting white light with CIE chromaticity coordinates of x = 0.33, y = 0.33 and an external quantum yield of 4.6% upon irradiation at 410 nm. Furthermore, as a proof of concept two different device setups of commercially available UV light emitting diodes, are coated with silica monoliths containing the three triethoxysilylpropyl-substituted fluorophore derivatives. These coatings are able to convert the emitted UV light into light with correlated color temperatures of very cold white (41100 K, 10700 K as well as a greenish white emission with correlated color temperatures of about 5500 K.

A three-phase to three-phase series-resonant power converter with optimal input current waveforms, Part II: implementation and results

NARCIS (Netherlands)

Huisman, H.

1988-01-01

For pt.I see ibid., vol.35, no.2, p.263-8 (1988). A 15 kW three-phase prototype series-resonant power converter is constructed. The converter features sinusoidal output voltage and sinusoidal input currents. The control concepts and necessary electronics, as well as the layout of the power circuit,

Proposition of a scheme for adaptive/intelligent analog-to-digital converters

International Nuclear Information System (INIS)

Vaidya, P.P.; Kataria, S.K.

2001-01-01

The paper proposes design of a new class of Analog to Digital Converters (ADC's) which we call as Intelligent ADC's with moving resolution. Unlike presently available ADC's which are designed for specific range of applications and give fixed resolution and conversion time, the intelligent ADC's described here can adjust their resolution during the process of conversion, depending upon nature of input signal to make optimum use of the hard-ware. It is possible to use an intelligent ADC to give resolution ranging from 8 bit to 16 bit and conversion time ranging from few nano sec. to few micro secs. These ADC's have significant advantages over conventional ones when used for nuclear pulse spectroscopy as well as for process control applications. (author)

A 41 ps ASIC time-to-digital converter for physics experiments

International Nuclear Information System (INIS)

Russo, Stefano; Petra, Nicola; De Caro, Davide; Barbarino, Giancarlo; Strollo, Antonio G.M.

2011-01-01

We present a novel Time-to-Digital (TDC) converter for physics experiments. Proposed TDC is based on a synchronous counter and an asynchronous fine interpolator. The fine part of the measurement is obtained using NORA inverters that provide improved resolution. A prototype IC was fabricated in 180 nm CMOS technology. Experimental measurements show that proposed TDC features 41 ps resolution associated with 0.35LSB differential non-linearity, 0.77LSB integral non-linearity and a negligible single shot precision. The whole dynamic range is equal to 18μs. The proposed TDC is designed using a flash architecture that reduces dead time. Data reported in the paper show that our design is well suited for present and future particle physics experiments.

High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

Directory of Open Access Journals (Sweden)

Hai Wang

2017-01-01

Full Text Available This paper presents the design and implementation of a new digital-to-time converter (DTC. The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL and integral nonlinearity (INL are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA chip.

Chapter 5: Modeling and Control of Three-Phase AC/DC Converter Including Phase-Locked Loop

DEFF Research Database (Denmark)

Zhou, Dao; Song, Yipeng; Blaabjerg, Frede

2018-01-01

In this chapter, a mathematical model of the power circuit of a three-phase AC/DC converter is developed in the stationary and synchronous reference frames. Then, the operation principle of the phasor locked loop is addressed to exact the angle information of the power grid to realize the accurat...

A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

KAUST Repository

Omran, Hesham

2016-11-16

A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.

A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

KAUST Repository

Omran, Hesham; Alhoshany, Abdulaziz; Alahmadi, Hamzah; Salama, Khaled N.

2016-01-01

A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.

Power Controllability of Three-phase Converter with Unbalanced AC Source

DEFF Research Database (Denmark)

Ma, Ke; Liserre, Marco; Blaabjerg, Frede

2013-01-01

Three-phase DC-AC power converters suffer from power oscillation and overcurrentt problems in case of unbalanced AC source voltage that can be caused by grid/generator faults. Existing solutions to handle these problems are properly selecting and controlling the positive and negative sequence...... currents. In this work a new series of control strategies which utilize the zero-sequence components are proposed to enhance the power control ability under this adverse conditions. It is concluded that by introducing proper zero sequence current controls and corresponding circuit configurations, the power...... converter can enable more flexible control targets, achieving better performances in the delivered power and load current when suffering from unbalanced AC sources....

A New Control Method for a Bi-Directional Phase-Shift-Controlled DC-DC Converter with an Extended Load Range

Directory of Open Access Journals (Sweden)

Wenzheng Xu

2017-10-01

Full Text Available Phase-shifted converters are practically important to provide high conversion efficiencies through soft-switching techniques. However, the limitation on a resonant inductor current in the converters often leads to a non-fulfillment of the requirement of minimum load current. This paper presents a new power electronics control technique to enable the dual features of bi-directional power flow and an extended load range for soft-switching in phase-shift-controlled DC-DC converters. The proposed technique utilizes two identical full bridge converters and inverters in conjunction with a new control logic for gate-driving signals to facilitate both Zero Current Switching (ZCS and Zero Voltage Switching (ZVS in a single phase-shift-controlled DC-DC converter. The additional ZCS is designed for light load conditions at which the minimum load current cannot be attained. The bi-directional phase-shift-controlled DC-DC converter can implement the function of synchronous rectification. Its fast dynamic response allows for quick energy recovery during the regenerative braking of traction systems in electrified trains.

Isolated/Non-Isolated Quad-Inverter Configuration for Multilevel Symmetrical/Asymmetrical Dual Six-Phase Star-Winding Converter

DEFF Research Database (Denmark)

Padmanaban, Sanjeevi Kumar; Hontz, Michael R.; Khanna, Raghav

2016-01-01

This article presents the developments of a novel isolated/non-isolated quad inverter configuration for multilevel dual six-phase (twelve-phase) star-winding converter. The modular circuit consists of four standard voltage source inverters (VSIs). Each VSI is incorporated with one bi-directional ...... systems, electrical vehicles, AC tractions, and `More-Electric Aircraft' propulsion systems....... converter is numerically modeled using Matlab/PLECS simulation software and the predicted behavior of the system is analyzed and presented. Good agreement is obtained between these results and the theoretical analysis. Suitable applications for the converter include (low-voltage/high-current) medium power...

A Digital Phase Lock Loop for an External Cavity Diode Laser

Science.gov (United States)

Wang, Xiao-Long; Tao, Tian-Jiong; Cheng, Bing; Wu, Bin; Xu, Yun-Fei; Wang, Zhao-Ying; Lin, Qiang

2011-08-01

A digital optical phase lock loop (OPLL) is implemented to synchronize the frequency and phase between two external cavity diode lasers (ECDL), generating Raman pulses for atom interferometry. The setup involves all-digital phase detection and a programmable digital proportional-integral-derivative (PID) loop in locking. The lock generates a narrow beat-note linewidth below 1 Hz and low phase-noise of 0.03rad2 between the master and slave ECDLs. The lock proves to be stable and robust, and all the locking parameters can be set and optimized on a computer interface with convenience, making the lock adaptable to various setups of laser systems.

Digital parallel-to-series pulse-train converter

Science.gov (United States)

Hussey, J.

1971-01-01

Circuit converts number represented as two level signal on n-bit lines to series of pulses on one of two lines, depending on sign of number. Converter accepts parallel binary input data and produces number of output pulses equal to number represented by input data.

Low cost time to digital converter in real time with +-1 ns resolution

Energy Technology Data Exchange (ETDEWEB)

Lenzi, G; Podini, P; Reverberi, R [Parma Univ. (Italy). Istituto di Fisica; Pernestaal, K [Uppsala Univ. (Sweden). Fysiska Institutionen

1977-04-15

A time to digital converter (TDC) with a time resolution of 1 ns has been designed. The deadtime is T+0.6 ..mu..s where T is the measured time. The time range can be preselected between 0.3 and 10 ..mu..s. The TDC has one START and three mutually exclusive STOP inputs which accept standard pulses (-16 mA). The time information is presented as a bit binary word, including the activated stop input address. The instrument has been successfully used in ..mu../sup +/SR (muon spin rotation) measurements and has proven itself advantageous over the more common TAC+ADC combination.

Data input from an analog-to-digital converter into the M-6000 computer

International Nuclear Information System (INIS)

Kalashnikov, A.M.; Sheremet'ev, A.K.

1978-01-01

A device for spectrometric data input from the ADC-4096 into the M-6000 computer memory operating in the information storage regime is described. The input device made on integrated circuits coordinates signal levels of the fast response analog-to-digital converter and computer with the help of resistors and inverters. Besides, the input forms a strobe to trigger an increment channel used to record information into the computer memory. The use of the input device permits to get rid of the intermediate information storage in the analyzer memory and ensures fast response of the devices

Compact FPGA-based beamformer using oversampled 1-bit A/D converters

DEFF Research Database (Denmark)

Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

2005-01-01

A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadr......% of the available logic resources in a commercially available midrange FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.......A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in......-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal...

A Digital Phase Lock Loop for an External Cavity Diode Laser

International Nuclear Information System (INIS)

Wang Xiao-Long; Tao Tian-Jiong; Cheng Bing; Wu Bin; Xu Yun-Fei; Wang Zhao-Ying; Lin Qiang

2011-01-01

A digital optical phase lock loop (OPLL) is implemented to synchronize the frequency and phase between two external cavity diode lasers (ECDL), generating Raman pulses for atom interferometry. The setup involves all-digital phase detection and a programmable digital proportional-integral-derivative (PID) loop in locking. The lock generates a narrow beat-note linewidth below 1 Hz and low phase-noise of 0.03rad 2 between the master and slave ECDLs. The lock proves to be stable and robust, and all the locking parameters can be set and optimized on a computer interface with convenience, making the lock adaptable to various setups of laser systems. (fundamental areas of phenomenology(including applications))

Study of key technology of ghost imaging via compressive sensing for a phase object based on phase-shifting digital holography

International Nuclear Information System (INIS)

Leihong, Zhang; Dong, Liang; Bei, Li; Zilan, Pan; Dawei, Zhang; Xiuhua, Ma

2015-01-01

In this article, the algorithm of compressing sensing is used to improve the imaging resolution and realize ghost imaging via compressive sensing for a phase object based on the theoretical analysis of the lensless Fourier imaging of the algorithm of ghost imaging based on phase-shifting digital holography. The algorithm of ghost imaging via compressive sensing based on phase-shifting digital holography uses the bucket detector to measure the total light intensity of the interference and the four-step phase-shifting method is used to obtain the total light intensity of differential interference light. The experimental platform is built based on the software simulation, and the experimental results show that the algorithm of ghost imaging via compressive sensing based on phase-shifting digital holography can obtain the high-resolution phase distribution figure of the phase object. With the same sampling times, the phase clarity of the phase distribution figure obtained by the algorithm of ghost imaging via compressive sensing based on phase-shifting digital holography is higher than that obtained by the algorithm of ghost imaging based on phase-shift digital holography. In this article, this study further extends the application range of ghost imaging and obtains the phase distribution of the phase object. (letter)

Dynamics Assessment of Grid-Synchronization Algorithms for Single-Phase Grid-Connected Converters

DEFF Research Database (Denmark)

Han, Yang; Luo, Mingyu; Guerrero, Josep M.

2015-01-01

Several advanced phase-lock-loop (PLL) algorithms have been proposed for single-phase power electronic systems. Among these algorithms, the orthogonal signal generators (OSGs) are widely utilized to generate a set of in-quadrature signals, owing to its benefit of simple digital implementation and...

Digital Control of a High Voltage (2.5 kV) Bidirectional Flyback DC-DC Converter for Driving a Capacitive Incremental Actuator

DEFF Research Database (Denmark)

Thummala, Prasanth; Maksimovic, Dragan; Zhang, Zhe

2016-01-01

This paper presents a digital control technique to achieve valley switching in a bidirectional flyback converter used to drive a dielectric electro-active polymer based capacitive incremental actuator. The paper also provides the design of a low input voltage (24 V) and variable high output voltage...... on the output high-voltage (HV) side. Experimental results verifying the bidirectional operation of a high voltage flyback converter are presented, using a 3 kV polypropylene film capacitor as the load. The energy loss distributions of the converter when 4 kV and 4.5 kV HV MOSFETs are used on HV side...

Multi-DSP and FPGA based Multi-channel Direct IF/RF Digital receiver for atmospheric radar

Science.gov (United States)

Yasodha, Polisetti; Jayaraman, Achuthan; Kamaraj, Pandian; Durga rao, Meka; Thriveni, A.

2016-07-01

Modern phased array radars depend highly on digital signal processing (DSP) to extract the echo signal information and to accomplish reliability along with programmability and flexibility. The advent of ASIC technology has made various digital signal processing steps to be realized in one DSP chip, which can be programmed as per the application and can handle high data rates, to be used in the radar receiver to process the received signal. Further, recent days field programmable gate array (FPGA) chips, which can be re-programmed, also present an opportunity to utilize them to process the radar signal. A multi-channel direct IF/RF digital receiver (MCDRx) is developed at NARL, taking the advantage of high speed ADCs and high performance DSP chips/FPGAs, to be used for atmospheric radars working in HF/VHF bands. Multiple channels facilitate the radar t be operated in multi-receiver modes and also to obtain the wind vector with improved time resolution, without switching the antenna beam. MCDRx has six channels, implemented on a custom built digital board, which is realized using six numbers of ADCs for simultaneous processing of the six input signals, Xilinx vertex5 FPGA and Spartan6 FPGA, and two ADSPTS201 DSP chips, each of which performs one phase of processing. MCDRx unit interfaces with the data storage/display computer via two gigabit ethernet (GbE) links. One of the six channels is used for Doppler beam swinging (DBS) mode and the other five channels are used for multi-receiver mode operations, dedicatedly. Each channel has (i) ADC block, to digitize RF/IF signal, (ii) DDC block for digital down conversion of the digitized signal, (iii) decoding block to decode the phase coded signal, and (iv) coherent integration block for integrating the data preserving phase intact. ADC block consists of Analog devices make AD9467 16-bit ADCs, to digitize the input signal at 80 MSPS. The output of ADC is centered around (80 MHz - input frequency). The digitized data is fed

Digital servo control of random sound test excitation. [in reverberant acoustic chamber

Science.gov (United States)

Nakich, R. B. (Inventor)

1974-01-01

A digital servocontrol system for random noise excitation of a test object in a reverberant acoustic chamber employs a plurality of sensors spaced in the sound field to produce signals in separate channels which are decorrelated and averaged. The average signal is divided into a plurality of adjacent frequency bands cyclically sampled by a time division multiplex system, converted into digital form, and compared to a predetermined spectrum value stored in digital form. The results of the comparisons are used to control a time-shared up-down counter to develop gain control signals for the respective frequency bands in the spectrum of random sound energy picked up by the microphones.

A VHF Interleaved Self-Oscillating Resonant SEPIC Converter with Phase-Shift Burst-Mode Control

DEFF Research Database (Denmark)

Kovacevic, Milovan; Knott, Arnold; Andersen, Michael A. E.

2014-01-01

This paper presents design and implementation of the phase-shift burst-mode control method for interleaved selfoscillating resonant SEPIC converters for LED lighting applications. The proposed control method utilizes delays in the turn-on and turn-off of the power stage and control circuitry...... in order to reduce requirements for the comparator in the regulation circuit. The control method is experimentally evaluated on a 49 MHz dc-dc converter prototype, and the results are presented. The designed converter demonstrates peak efficiency of 81%, maintains efficiency above 75% from 20% load to full...

Improving the phase measurement by the apodization filter in the digital holography

Science.gov (United States)

Chang, Shifeng; Wang, Dayong; Wang, Yunxin; Zhao, Jie; Rong, Lu

2012-11-01

Due to the finite size of the hologram aperture in digital holography, high frequency intensity and phase fluctuations along the edges of the images, which reduce the precision of phase measurement. In this paper, the apodization filters are applied to improve the phase measurement in the digital holography. Firstly, the experimental setup of the lensless Fourier transform digital holography is built, where the sample is a standard phase grating with the grating constant of 300μm and the depth of 150nm. Then, apodization filters are applied to phase measurement of the sample with three kinds of the window functions: Tukey window, Hanning window and Blackman window, respectively. Finally, the results were compared to the detection data given by the commercial white-light interferometer. It is shown that aperture diffraction effects can be reduced by the digital apodization, and the phase measurement with the apodization is more accurate than in the unapodized case. Meanwhile, the Blackman window function produces better effect than the other two window functions in the measurement of the standard phase grating.

A Standalone Solar Photovoltaic Power Generation using Cuk Converter and Single Phase Inverter

Science.gov (United States)

Verma, A. K.; Singh, B.; Kaushika, S. C.

2013-03-01

In this paper, a standalone solar photovoltaic (SPV) power generating system is designed and modeled using a Cuk dc-dc converter and a single phase voltage source inverter (VSI). In this system, a dc-dc boost converter boosts a low voltage of a PV array to charge a battery at 24 V using a maximum power point tracking control algorithm. To step up a 24 V battery voltage to 360 V dc, a high frequency transformer based isolated dc-dc Cuk converter is used to reduce size, weight and losses. The dc voltage of 360 V is fed to a single phase VSI with unipolar switching to achieve a 230 Vrms, 50 Hz ac. The main objectives of this investigation are on efficiency improvement, reduction in cost, weight and size of the system and to provide an uninterruptible power to remotely located consumers. The complete SPV system is designed and it is modeled in MATLAB/Simulink. The simulated results are presented to demonstrate its satisfactory performance for validating the proposed design and control algorithm.

Digital mineral logging system

International Nuclear Information System (INIS)

West, J.B.

1980-01-01

A digital mineral logging system acquires data from a mineral logging tool passing through a borehole and transmits the data uphole to an electronic digital signal processor. A predetermined combination of sensors, including a deviometer, is located in a logging tool for the acquisition of the desired data as the logging tool is raised from the borehole. Sensor data in analog format is converted in the logging tool to a digital format and periodically batch transmitted to the surface at a predetermined sampling rate. An identification code is provided for each mineral logging tool, and the code is transmitted to the surface along with the sensor data. The self-identifying tool code is transmitted to the digital signal processor to identify the code against a stored list of the range of numbers assigned to that type of tool. The data is transmitted up the d-c power lines of the tool by a frequency shift key transmission technique. At the surface, a frequency shift key demodulation unit transmits the decoupled data to an asynchronous receiver interfaced to the electronic digital signal processor. During a recording phase, the signals from the logging tool are read by the electronic digital signal processor and stored for later processing. During a calculating phase, the stored data is processed by the digital signal processor and the results are outputted to a printer or plotter, or both

A behavioral simulator for switched-capacitor sigma-delta modulator analog-to-digital converter

International Nuclear Information System (INIS)

San, H. Y.; Rezaul Hasan, S. M.

1998-01-01

In this paper, a PC-based simulator for state of the art oversampled switched-capacitor sigma-delta analog-to-digital converters is presented. The proposed simulator employs behavioral model of switched-capacitor integrator and non-linear quantizer to stimulate the system. The behavioral simulation of the integrator is also verified with SPICE. The simulator is fully integrated and standalone. It integrates an input netlist file interpreter, a behavioral simulator, a generic part library and a powerful post-processor to evaluate the SNR, SDR And TSNR. Both passive and active sensitivities can be investigated by the proposed simulator. The simulator is coded in C++, and is very fast

Fast digital recorders of signal shaping

International Nuclear Information System (INIS)

Meleshko, E.A.

1997-01-01

Methodology of fast digital registration and pulse signals through fast-action analog-to-digital converters is considered. Systems of digital recorders: sampling and storage devices and operational memory units are described. Main attention is paid to developing parallel analog-to-digital converters, making it possible to bring the conversion frequencies up to several gigahertzes are described. Parallel-sequential analog-to-digital converters, combining high action with increased accuracy are also considered. Concrete examples of designing universal and specialized digital signal recorders, applied in experimental physics, are presented. 44 refs., 12 figs

Digital base-band rf control system for the superconducting Darmstadt electron linear accelerator

Directory of Open Access Journals (Sweden)

M. Konrad

2012-05-01

Full Text Available The accelerating field in superconducting cavities has to be stabilized in amplitude and phase by a radio-frequency (rf control system. Because of their high loaded quality factor superconducting cavities are very susceptible for microphonics. To meet the increased requirements with respect to accuracy, availability, and diagnostics, the previous analog rf control system of the superconducting Darmstadt electron linear accelerator S-DALINAC has been replaced by a digital rf control system. The new hardware consists of two components: An rf module that converts the signal from the cavity down to the base-band and a field-programmable gate array board including a soft CPU that carries out the signal processing steps of the control algorithm. Different algorithms are used for normal-conducting and superconducting cavities. To improve the availability of the control system, techniques for automatic firmware and software deployment have been implemented. Extensive diagnostic features provide the operator with additional information. The architecture of the rf control system as well as the functionality of its components will be presented along with measurements that characterize the performance of the system, yielding, e.g., an amplitude stabilization down to (ΔA/A_{rms}=7×10^{-5} and a phase stabilization of (Δϕ_{rms}=0.8° for superconducting cavities.

Latin Letters Recognition Using Optical Character Recognition to Convert Printed Media Into Digital Format

Directory of Open Access Journals (Sweden)

Rio Anugrah

2017-12-01

Full Text Available Printed media is still popular now days society. Unfortunately, such media encountered several drawbacks. For example, this type of media consumes large storage that impact in high maintenance cost. To keep printed information more efficient and long-lasting, people usually convert it into digital format. In this paper, we built Optical Character Recognition (OCR system to enable automatic conversion the image containing the sentence in Latin characters into digital text-shaped information. This system consists of several interrelated stages including preprocessing, segmentation, feature extraction, classifier, model and recognition. In preprocessing, the median filter is used to clarify the image from noise and the Otsu’s function is used to binarize the image. It followed by character segmentation using connected component labeling. Artificial neural network (ANN is used for feature extraction to recognize the character. The result shows that this system enable to recognize the characters in the image whose success rate is influenced by the training of the system.

Modules of the SUMMA system for data readout to the oscillograph, digital display devices and digital printing

International Nuclear Information System (INIS)

Bushnin, Yu.B.; Denisenko, A.A.; Dunajtsev, A.F.; Rybakov, V.G.; Sytin, A.N.

1975-01-01

The modules of the ''Summa'' system are described which allow outputting of information to an oscilloscope, a digital tableau, and a digital printing mechanism; they are: a digital-analog converter, a converter that converts a binary code to a binary-decimal code, a digital display module, a block for outputting to a digital printing mechanism, and a block for stipulating the programs during information outputting. The block diagrams of the modules and the block diagram of the information-outputting programs are presented

Parallel phase-shifting digital holography based on the fractional Talbot effect

Energy Technology Data Exchange (ETDEWEB)

Martinez-Leon, Lluis; Climent, Vicent; Lancis, Jesus; Tajahuerce, Enrique [GROC-UJI, Departament de Fisica, Universitat Jaume I, 12071 Castello (Spain); Araiza-E, Maria [Laboratorio de Procesamiento Digital de Senales, Universidad Autonoma de Zacatecas, Zacatecas (Mexico); Javidi, Bahram [Department of Electrical and Computer Engineering, University of Connecticut, CT 06269-2157 (United States); Andres, Pedro, E-mail: enrique.tajahuerce@uji.e [Departament d' Optica, Universitat de Valencia, 46100 Burjassot (Spain)

2010-02-01

A method for recording on-axis single-shot digital holograms based on the self-imaging phenomenon is reported. A simple binary two-dimensional periodic amplitude is used to codify the reference beam in a Mach-Zehnder interferometer, generating a periodic three-step phase distribution with uniform irradiance over the sensor plane by fractional Talbot effect. An image sensor records only one shot of the interference between the light field scattered by the object and the codified parallel reference beam. Images of the object are digitally reconstructed from the digital hologram through the numerical evaluation of the Fresnel diffraction integral. This scheme provides an efficient way to perform dynamic phase-shifting interferometric techniques to determine the amplitude and phase of the object light field. Unlike other parallel phase-shifting techniques, neither complex pixelated polarization devices nor special phase diffractive elements are required. Experimental results confirm the feasibility and flexibility of our method.

A Novel Single Switch Transformerless Quadratic DC/DC Buck-Boost Converter

DEFF Research Database (Denmark)

Mostaan, Ali; A. Gorji, Saman; N. Soltani, Mohsen

2017-01-01

A novel quadratic buck-boost DC/DC converter is presented in this study. The proposed converter utilizes only one active switch and can step-up/down the input voltage, while the existing single switch quadratic buck/boost converters can only work in step-up or step-down mode. First, the proposed ...

Development of Michelson interferometer based spatial phase-shift digital shearography

Science.gov (United States)

Xie, Xin

Digital shearography is a non-contact, full field, optical measurement method, which has the capability of directly measuring the gradient of deformation. For high measurement sensitivity, phase evaluation method has to be introduced into digital shearography by phase-shift technique. Catalog by phase-shift method, digital phase-shift shearography can be divided into Temporal Phase-Shift Digital Shearography (TPS-DS) and Spatial Phase-Shift Digital Shearography (SPS-DS). TPS-DS is the most widely used phase-shift shearography system, due to its simple algorithm, easy operation and good phase-map quality. However, the application of TPS-DS is only limited in static/step-by-step loading measurement situation, due to its multi-step shifting process. In order to measure the strain under dynamic/continuous loading situation, a SPS-DS system has to be developed. This dissertation aims to develop a series of Michelson Interferometer based SPS-DS measurement methods to achieve the strain measurement by using only a single pair of speckle pattern images. The Michelson Interferometer based SPS-DS systems utilize special designed optical setup to introduce extra carrier frequency into the laser wavefront. The phase information corresponds to the strain field can be separated on the Fourier domain using a Fourier Transform and can further be evaluated with a Windowed Inverse Fourier Transform. With different optical setups and carrier frequency arrangements, the Michelson Interferometer based SPS-DS method is capable to achieve a variety of measurement tasks using only single pair of speckle pattern images. Catalog by the aimed measurand, these capable measurement tasks can be divided into five categories: 1) measurement of out-of-plane strain field with small shearing amount; 2) measurement of relative out-of-plane deformation field with big shearing amount; 3) simultaneous measurement of relative out-of-plane deformation field and deformation gradient field by using multiple

A BUNCH TO BUCKET PHASE DETECTOR USING DIGITAL RECEIVER TECHNOLOGY

International Nuclear Information System (INIS)

DELONG, J.; BRENNAN, J.M.; HAYES, T.; LE, T.N.; SMITH, K.

2003-01-01

Transferring high-speed digital signals to a Digital Signal Processor is limited by the IO bandwidth of the DSP. A digital receiver circuit is used to translate high frequency W signals to base-band. The translated output frequency is close to DC and the data rate can be reduced, by decimation, before transfer to the DSP. By translating both the longitudinal beam (bunch) and RF cavity pick-ups (bucket) to DC, a DSP can be used to measure their relative phase angle. The result can be used as an error signal in a beam control servo loop and any phase differences can be compensated

Measurement on Five-Phase IM Fed from Ten-Pulse Frequency Converter

Czech Academy of Sciences Publication Activity Database

Chomát, Miroslav; Schreier, Luděk; Bendl, Jiří

2012-01-01

Roč. 1, č. 2 (2012), s. 66-71 ISSN 1805-3386. [ISEM 2011. Prague, 07.09.2011-09.09.2011] R&D Projects: GA ČR GA102/09/1273 Institutional research plan: CEZ:AV0Z20570509 Keywords : five-phase induction machine * ten-pulse converter * symmetrical components Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering

Single-phase to three-phase converter system of high quality for rural applications and distributed generation; Sistema conversor mono-trifasico de alta qualidade para aplicacoes rurais e de geracao distribuida

Energy Technology Data Exchange (ETDEWEB)

Machado, Ricardo Q.; Pomilio, Jose A. [Universidade Estadual de Campinas (UNICAMP), SP (Brazil). Fac. de Engenharia Eletrica e de Computacao], e-mail: ricardom@dsce.fee.unicamp.br; Buso, Simone [Universidade de Padova, Padua (Italy). Dept. de Engenharia da Informacao], e-mail: simone.buso@dei.unipd.it

2004-07-01

This paper describes a line-interactive single-phase to three-phase converter. The typical application is in rural areas supplied by the single-wire with earth return. The traditional objective of feeding a three-phase induction motor is not anymore the main concern for such conversion. Due to the evolution of the agro business, some of the local load (as electronic power converters, computers, communication equipment, etc.) requires high quality power, intended as sinusoidal, symmetrical and balanced three-phase voltage. Additionally, to maximize the power got from the feeder, the system provides a unitary power factor to the feeder. A three-phase PWM converter is used for this purpose. The power converter does not process all the load power, as in the conventional solutions, but only the fraction necessary to regulate the three-phase bus voltage. The control strategy, design highlights and experimental results are presented. (author)

In-phase and quadrature imbalance modeling, estimation, and compensation

CERN Document Server

Li, Yabo

2013-01-01

This book provides a unified IQ imbalance model and systematically reviews the existing estimation and compensation schemes. It covers the different assumptions and approaches that lead to many models of IQ imbalance. In wireless communication systems, the In-phase and Quadrature (IQ) modulator and demodulator are usually used as transmitter (TX) and receiver (RX), respectively. For Digital-to-Analog Converter (DAC) and Analog-to-Digital Converter (ADC) limited systems, such as multi-giga-hertz bandwidth millimeter-wave systems, using analog modulator and demodulator is still a low power and l

Converter of a continuous code into the Grey code

International Nuclear Information System (INIS)

Gonchar, A.I.; TrUbnikov, V.R.

1979-01-01

Described is a converter of a continuous code into the Grey code used in a 12-charged precision amplitude-to-digital converter to decrease the digital component of spectrometer differential nonlinearity to +0.7% in the 98% range of the measured band. To construct the converter of a continuous code corresponding to the input signal amplitude into the Grey code used is the regularity in recycling of units and zeroes in each discharge of the Grey code in the case of a continuous change of the number of pulses of a continuous code. The converter is constructed on the elements of 155 series, the frequency of continuous code pulse passing at the converter input is 25 MHz

Analysis and Controller Design of a Universal Bidirectional DC-DC Converter

Directory of Open Access Journals (Sweden)

Kou-Bin Liu

2016-06-01

Full Text Available In this paper, first the operating principles of a non-isolated universal bidirectional DC-DC converter are studied and analyzed. The presented power converter is capable of operating in all power transferring directions in buck/boost modes. Zero voltage switching can be achieved for all the power switches through proper modulation strategy design, therefore, the presented converter can achieve high efficiency. To further improve the efficiency, the relationship between the phase-shift angle and the overall system efficiency is analyzed in detail, an adaptive phase-shift (APS control method which determines the phase-shift value between gating signals according to the load level is then proposed. As the modulation strategy is a software-based solution, there is no requirement for additional circuits, therefore, it can be implemented easily and instability and noise susceptibility problems can be reduced. To validate the correctness and the effectiveness of the proposed method, a 300 W prototyping circuit is implemented and tested. A low cost dsPIC33FJ16GS502 digital signal controller is adopted in this paper to realize the power flow control, DC-bus voltage regulation and APS control. According to the experimental results, a 12.2% efficiency improvement at light load and 4.0% efficiency improvement at half load can be achieved.

Electromagnetic Compatibility of Matrix Converter System

Directory of Open Access Journals (Sweden)

S. Fligl

2006-12-01

Full Text Available The presented paper deals with matrix converters pulse width modulation strategies design with emphasis on the electromagnetic compatibility. Matrix converters provide an all-silicon solution to the problem of converting AC power from one frequency to another, offering almost all the features required of an ideal static frequency changer. They possess many advantages compared to the conventional voltage or current source inverters. A matrix converter does not require energy storage components as a bulky capacitor or an inductance in the DC-link, and enables the bi-directional power flow between the power supply and load. The most of the contemporary modulation strategies are able to provide practically sinusoidal waveforms of the input and output currents with negligible low order harmonics, and to control the input displacement factor. The perspective of matrix converters regarding EMC in comparison with other types of converters is brightly evident because it is no need to use any equipment for power factor correction and current and voltage harmonics reduction. Such converter with proper control is properly compatible both with the supply mains and with the supplied load. A special digital control system was developed for the realized experimental test bed which makes it possible to achieve greater throughput of the digital control system and its variability.

360/degree/ digital phase detector with 100-kHz bandwidth

International Nuclear Information System (INIS)

Reid, D.W.; Riggin, D.; Fazio, M.V.; Biddle, R.S.; Patton, R.D.; Jackson, H.A.

1981-01-01

The general availability of digital circuit components with propagation delay times of a few nanoseconds makes a digital phase detector with good bandwidth feasible. Such a circuit has a distinct advantage over its analog counterpart because of its linearity over a wide range of phase shift. A description is given of a phase detector that is being built at Los Alamos National Laboratory for the Fusion Materials Irradiation Test (FMIT) project. The specifications are 100-kHz bandwidth, linearity of /plus or minus/1/degree/ over /plus or minus/180/degree/ of phase shift, and 0.66/degree/ resolution. To date, the circuit has achieved the bandwidth and resolution. The linearity is approximately /plus or minus/3/degree/ over /plus or minus/180/degree/ phase shift. 3 refs

Easy digital engineering

International Nuclear Information System (INIS)

Jin, Dal Bok

2002-02-01

This book lists basic of digital engineering, number system and digital code, Boolean algebra and basic logic circuit, simplify of logical expression, combinational circuit, arithmetic circuit, multivibrator circuit, sequential circuit, memory unit of semiconductor and logical element for program, D/A converter and A/D converter, logic element and integrated circuit and logic circuit and micro controller. It has exercises and answers about digital engineering and summary in the end of each chapter.

Cryocooled wideband digital channelizing radio-frequency receiver based on low-pass ADC

International Nuclear Information System (INIS)

Vernik, Igor V; Kirichenko, Dmitri E; Dotsenko, Vladimir V; Miller, Robert; Webber, Robert J; Shevchenko, Pavel; Talalaevskii, Andrei; Gupta, Deepnarayan; Mukhanov, Oleg A

2007-01-01

We have demonstrated a digital receiver performing direct digitization of radio-frequency signals over a wide frequency range from kilohertz to gigahertz. The complete system, consisting of a cryopackaged superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field programmable gate array (FPGA) based post-processing module, has been developed. The ADR chip comprises a low-pass analog-to-digital converter (ADC) delta modulator with phase modulation-demodulation architecture together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chip is fabricated using a 4.5 kA cm -2 process and is cryopackaged using a commercial-off-the-shelf cryocooler. Experimental results in HF, VHF, UHF and L bands and their analysis, proving consistent operation of the cryopackaged ADR chip up to 24.32 GHz clock frequency, are presented and discussed

The Impact of a Power Electronics Converter in Phase Failure Work on the Power System Network

Directory of Open Access Journals (Sweden)

Dariusz Zieliński

2016-09-01

Full Text Available The paper presents the impact of phase failure work on power converters. The study includes a three-level NPC inverter (Neutral Point Clamped, controlled by Voltage Oriented Control (VOC. The NPC converter integrates renewable energy sources with the power grid. The article includes a discussion about the causes of phase failure work and an analysis of the converter’s failure and its impact on the power grid. The simulations were performed in MATLAB/Simulink. The study also includes the concept of an integrated protection for IGBTs, controlled by the DSP microprocessor system.

Digital Conically Scanned L-Band Radar, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — The proposed effort seeks to develop a digitally steered polarimetric phased array L-Band radar utilizing a novel, high performance architecture leveraging recent...

Conception and realization of a multichannel amplitude converter

International Nuclear Information System (INIS)

Bendebiche, L.

1992-11-01

A compact Analog to Digital Converter system suitable for high resolution γ-ray analysers has been developed based on the ADADC84 12-bit converter from Analog Devices. The converter was equipped with a peak detector and a stretcher, and with a memory card providing the sliding scale circuits, the lower threshold, the channel number identification and the zero suppression. The conversion time is 10 μs and the differential non linearity is less than ±1% for a 12-bit resolution. The converter consists of a 12-bit spectroscopy analog-to-digital converter (ADC) while the memory card includes a 8K 24-bit buffer memory. The two cards are plugged into a slot of an IBM PC AT and using an emulation software converts the micro-computer into a full-featured pulse height analyser. In data acquisition mode, the cards can operate independently, making the computer free for other tasks. The software offers acquisition control, visualization, data handling functions and various types of result presentation

Amplitude-to-frequency converter of radioisotope instruments

International Nuclear Information System (INIS)

Demchenkov, V.P.; Korobkov, I.N.

1988-01-01

An amplitude-to-frequency converter designed for signal processing of radioisotope relay devices is descibed. The basic elements of the converter are a scaling amplifier, an analog-to-digital converter, a code-to-frequency converter, a null-organ, a delay unit and a clock-pulse generator. The designed amplitude-to-frequency converter takes into account a prior information about the signal shape of the energy spectrum. The converter processes input pulses of 0.10 V amplitude and duration more than 2μs. The energy channel number is 64

Deep Cryogenic Low Power 24 Bits Analog to Digital Converter with Active Reverse Cryostat

Science.gov (United States)

Turqueti, Marcos; Prestemon, Soren; Albright, Robert

LBNL is developing an innovative data acquisition module for superconductive magnets where the front-end electronics and digitizer resides inside the cryostat. This electronic package allows conventional electronic technologies such as enhanced metal-oxide-semiconductor to work inside cryostats at temperatures as low as 4.2 K. This is achieved by careful management of heat inside the module that keeps the electronic envelop at approximately 85 K. This approach avoids all the difficulties that arise from changes in carrier mobility that occur in semiconductors at deep cryogenic temperatures. There are several advantages in utilizing this system. A significant reduction in electrical noise from signals captured inside the cryostat occurs due to the low temperature that the electronics is immersed in, reducing the thermal noise. The shorter distance that signals are transmitted before digitalization reduces pickup and cross-talk between channels. This improved performance in signal-to-noise rate by itself is a significant advantage. Another important advantage is the simplification of the feedthrough interface on the cryostat head. Data coming out of the cryostat is digital and serial, dramatically reducing the number of lines going through the cryostat feedthrough interface. It is important to notice that all lines coming out of the cryostat are digital and low voltage, reducing the possibility of electric breakdown inside the cryostat. This paper will explain in details the architecture and inner workings of this data acquisition system. It will also provide the performance of the analog to digital converter when the system is immersed in liquid helium, and in liquid nitrogen. Parameters such as power dissipation, integral non-linearity, effective number of bits, signal-to-noise and distortion, will be presented for both temperatures.

Efficient textured colour conversion layer of a down-converted white organic light-emitting diode by transfer imprinting

International Nuclear Information System (INIS)

Zhu, Wenqing; Xiao, Teng; Qian, Bingjie; Sun, Liangliang

2015-01-01

In this paper, we demonstrated an efficient textured colour conversion layer (CCL) of a down-converted white organic light-emitting diode (WOLED), which was fabricated by a very simple transfer imprinting method based on silicon wafer. The textured CCL not only helped to extract wave-guided light in the device, but also had an outstanding performance in enhancing the colour conversion rate, which was 1.75 times greater than that of flat CCL. Compared to flat CCL, the lower-doped textured CCL produced better white emission and higher efficiency simultaneously. Moreover, the WOLED with textured CCL also exhibited good colour stability at various voltages. (paper)

Real-time quantitative phase reconstruction in off-axis digital holography using multiplexing.

Science.gov (United States)

Girshovitz, Pinhas; Shaked, Natan T

2014-04-15

We present a new approach for obtaining significant speedup in the digital processing of extracting unwrapped phase profiles from off-axis digital holograms. The new technique digitally multiplexes two orthogonal off-axis holograms, where the digital reconstruction, including spatial filtering and two-dimensional phase unwrapping on a decreased number of pixels, can be performed on both holograms together, without redundant operations. Using this technique, we were able to reconstruct, for the first time to our knowledge, unwrapped phase profiles from off-axis holograms with 1 megapixel in more than 30 frames per second using a standard single-core personal computer on a MATLAB platform, without using graphic-processing-unit programming or parallel computing. This new technique is important for real-time quantitative visualization and measurements of highly dynamic samples and is applicable for a wide range of applications, including rapid biological cell imaging and real-time nondestructive testing. After comparing the speedups obtained by the new technique for holograms of various sizes, we present experimental results of real-time quantitative phase visualization of cells flowing rapidly through a microchannel.

A tapped-inductor buck-boost converter for a multi-DEAP generator energy harvesting system

DEFF Research Database (Denmark)

Dimopoulos, Emmanouil; Munk-Nielsen, Stig

2014-01-01

the effective operational range of the power electronic converter. In this paper, a bidirectional tapped-inductor buck-boost converter is proposed, addressing high-efficient high step-up and high step-down voltage conversion ratios, for energy harvesting applications based on DEAP generators. The effective...... operational range of the converter is extended, by replacing its high-side switch with a string of three serialized MOSFETs, to accommodate the need for high-efficient high-voltage operation. Experiments conducted on a single DEAP generator - part of a quadruple DEAP generator energy harvesting system...... with all elements installed sequentially in the same circular disk with a 90 phase shift - validate the applicability of the proposed converter, demonstrating energy harvesting of 0.26 J, at 0.5 Hz and 60 % delta-strain; characterized by an energy density of 1.25 J per kg of active material....

Improved Design Methods for Robust Single- and Three-Phase ac-dc-ac Power Converters

DEFF Research Database (Denmark)

Qin, Zian

. The approaches for improving their performance, in terms of the voltage stress, efficiency, power density, cost, loss distribution, and temperature, will be studied. The structure of the thesis is as follows, Chapter 1 presents the introduction and motivation of the whole project as well as the background...... becomes a emerging challenge. Accordingly, installation of sustainable power generators like wind turbines and solar panels has experienced a large increase during the last decades. Meanwhile, power electronics converters, as interfaces in electrical system, are delivering approximately 80 % electricity...... back-to-back, and meanwhile improve the harmonics, control flexibility, and thermal distribution between the switches. Afterwards, active power decoupling methods for single-phase inverters or rectifiers that are similar to the single-phase ac-dc-ac converter, are studied in Chapter 4...

A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

International Nuclear Information System (INIS)

Perktold, L; Christiansen, J

2014-01-01

The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than ±0.9 LSB and integral-non-linearity (INL) of better than ±1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology

Double-Carrier Phase-Disposition Pulse Width Modulation Method for Modular Multilevel Converters

DEFF Research Database (Denmark)

Zhou, Fayun; Luo, An; Li, Yan

2017-01-01

Modular multilevel converters (MMCs) have become one of the most attractive topologies for high-voltage and high-power applications. A double-carrier phase disposition pulse width modulation (DCPDPWM) method for MMCs is proposed in this paper. Only double triangular carriers with displacement ang......, the proposed method and theoretical analysis are verified by simulation and experimental results. View Full-Text...

Comparison of soft and hard-switching effiency in a three-level single phase 60kW dc-ac converter

DEFF Research Database (Denmark)

Munk-Nielsen, Stig; Teodorescu, Remus; Bech, Michael Møller

2003-01-01

Efficiency measurements on a three-level single-phase soft-switched converter are presented and show a slightly improved efficiency compared with the hard-switched converter for output powers higher than 25 % of rated power. The resonant converter switches are Zero Voltage Switched (ZVS......) and a simple resonant circuit is used. Increased resonant converter efficiency enables a reduction in the semiconductor size pr. watt output power or an increase the switching frequency....

The Three-Phase Power Router and Its Operation with Matrix Converter toward Smart-Grid Applications

Directory of Open Access Journals (Sweden)

Alexandros Kordonis

2015-04-01

Full Text Available A power router has been recently developed for both AC and DC applications that has the potential for smart-grid applications. This study focuses on three-phase power switching through the development of an experimental setup which consists of a three-phase direct AC/AC matrix converter with a power router attached to its output. Various experimental switching scenarios with the loads connected to different input sources were investigated. The crescent introduction of decentralized power generators throughout the power-grid obligates us to take measurements for a better distribution and management of the power. Power routers and matrix converters have great potential to succeed this goal with the help of power electronics devices. In this paper, a novel experimental three-phase power switching was achieved and the advantages of this operation are presented, such as on-demand and constant power supply at the desired loads.

Analysis of reconstructed interference fields in digital holographic interferometry using the polynomial phase transform

International Nuclear Information System (INIS)

Gorthi, Sai Siva; Rastogi, Pramod

2009-01-01

A noisy wrapped phase map is the end-output of commonly employed phase estimation methods in digital holographic interferometry. Hence filtering and unwrapping are necessary to obtain continuous phase distributions. This paper introduces a new approach for phase estimation in digital holographic interferometry using the polynomial phase transform. The proposed approach directly provides an accurate estimation of the unwrapped phase distribution from a noisy reconstructed interference field, thereby bypassing cumbersome and error-prone filtering and 2D phase unwrapping procedures

Sampling phase lock loop (PLL) with low power clock buffer

NARCIS (Netherlands)

Gao, X.; Bahai, A.; Bohsali, M.; Djabbari, A.; Klumperink, Eric A.M.; Nauta, Bram; Socci, G.

2013-01-01

A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up

Design of High-Voltage Switch-Mode Power Amplifier Based on Digital-Controlled Hybrid Multilevel Converter

Directory of Open Access Journals (Sweden)

Yanbin Hou

2016-01-01

Full Text Available Compared with conventional Class-A, Class-B, and Class-AB amplifiers, Class-D amplifier, also known as switching amplifier, employs pulse width modulation (PWM technology and solid-state switching devices, capable of achieving much higher efficiency. However, PWM-based switching amplifier is usually designed for low-voltage application, offering a maximum output voltage of several hundred Volts. Therefore, a step-up transformer is indispensably adopted in PWM-based Class-D amplifier to produce high-voltage output. In this paper, a switching amplifier without step-up transformer is developed based on digital pulse step modulation (PSM and hybrid multilevel converter. Under the control of input signal, cascaded power converters with separate DC sources operate in PSM switch mode to directly generate high-voltage and high-power output. The relevant topological structure, operating principle, and design scheme are introduced. Finally, a prototype system is built, which can provide power up to 1400 Watts and peak voltage up to ±1700 Volts. And the performance, including efficiency, linearity, and distortion, is evaluated by experimental tests.

10-bit rapid single flux quantum digital-to-analog converter for ac voltage standard

International Nuclear Information System (INIS)

Maezawa, M; Hirayama, F

2008-01-01

Digital-to-analog (D/A) converters based on rapid single flux quantum (RSFQ) technology are under development for ac voltage standard applications. We present design and test results on a prototype 10-bit version integrated on a single chip. The 10-bit chip includes over 6000 Josephson junctions and consumes a bias current exceeding 1 A. To reduce the effects of the high bias current on circuit operation, a custom design method was employed in part and large circuit blocks were divided into smaller ones. The 10-bit chips were fabricated and tested at low speed. The test results suggested that our design approach could manage large bias currents on the order of 1 A per chip

Enhancing the performance of photovoltaic cells by using down-converting KCaGd(PO4)2∶Eu3+ phosphors

Institute of Scientific and Technical Information of China (English)

Yen-Chi Chen; Woan-Yu Huang; Teng-Ming Chen

2011-01-01

The goal of this work is aimed to improve the power conversion efficiency of single crystalline silicon-based photovoltaic (PV) cells by using the solar spectral conversion principle,which employed a down-converting phosphor to convert a high-energy ultraviolet photon to the less energetic red-emitting photons to improve the spectral response of Si solar cells.In this study,the surface of silicon solar cells was coated with a red-emitting KCaGd(PO4)2∶Eu3+ phosphor by using the screen-printing technique.In addition to the investigation on the microstructure using scanning electron microscopy (SEM),we measured the short circuit current (Isc),open circuit voltage (Voc),and power conversion efficiency (η) of spectral-conversion cells and compared with those of bare solar cells as a reference.Preliminary experimental results revealed that in an optimized PV cell,an enhancement of (0.64+0.01)％ (from 16.03％ to 16.67％) in △η ofa Si-based PV cell was achieved.

A digital, constant-frequency pulsed phase-locked-loop instrument for real-time, absolute ultrasonic phase measurements

Science.gov (United States)

Haldren, H. A.; Perey, D. F.; Yost, W. T.; Cramer, K. E.; Gupta, M. C.

2018-05-01

A digitally controlled instrument for conducting single-frequency and swept-frequency ultrasonic phase measurements has been developed based on a constant-frequency pulsed phase-locked-loop (CFPPLL) design. This instrument uses a pair of direct digital synthesizers to generate an ultrasonically transceived tone-burst and an internal reference wave for phase comparison. Real-time, constant-frequency phase tracking in an interrogated specimen is possible with a resolution of 0.000 38 rad (0.022°), and swept-frequency phase measurements can be obtained. Using phase measurements, an absolute thickness in borosilicate glass is presented to show the instrument's efficacy, and these results are compared to conventional ultrasonic pulse-echo time-of-flight (ToF) measurements. The newly developed instrument predicted the thickness with a mean error of -0.04 μm and a standard deviation of error of 1.35 μm. Additionally, the CFPPLL instrument shows a lower measured phase error in the absence of changing temperature and couplant thickness than high-resolution cross-correlation ToF measurements at a similar signal-to-noise ratio. By showing higher accuracy and precision than conventional pulse-echo ToF measurements and lower phase errors than cross-correlation ToF measurements, the new digitally controlled CFPPLL instrument provides high-resolution absolute ultrasonic velocity or path-length measurements in solids or liquids, as well as tracking of material property changes with high sensitivity. The ability to obtain absolute phase measurements allows for many new applications than possible with previous ultrasonic pulsed phase-locked loop instruments. In addition to improved resolution, swept-frequency phase measurements add useful capability in measuring properties of layered structures, such as bonded joints, or materials which exhibit non-linear frequency-dependent behavior, such as dispersive media.

Studies on a Hybrid Full-Bridge/Half-Bridge Bidirectional CLTC Multi-Resonant DC-DC Converter with a Digital Synchronous Rectification Strategy

Directory of Open Access Journals (Sweden)

Shu-huai Zhang

2018-01-01

Full Text Available This study presents a new bidirectional multi-resonant DC-DC converter, which is named CLTC. The converter adds an auxiliary transformer and an extra resonant capacitor based on a LLC resonant DC-DC converter, achieving zero-voltage switching (ZVS for the input inverting switches and zero-current switching (ZCS for the output rectifiers in all load range. The converter also has a wide gain range in two directions. When the load is light, a half-bridge configuration is adopted instead of a full-bridge configuration to solve the problem of voltage regulation. By this method, the voltage gain becomes monotonous and controllable. Besides, the digital synchronous rectification strategy is proposed in forward mode without adding any auxiliary circuit. The conduction time of synchronous rectifiers equals the estimation value of body diodes’ conduction time with the lightest load. Power loss analysis is also conducted in different situations. Finally, the theoretical analysis is validated by a 5 kW prototype.

Grid-Current-Feedback Active Damping for LCL Resonance in Grid-Connected Voltage-Source Converters

DEFF Research Database (Denmark)

Wang, Xiongfei; Blaabjerg, Frede; Loh, Poh Chiang

2016-01-01

This paper investigates active damping of LCL-filter resonance in a grid-connected voltage-source converter with only grid-current feedback control. Basic analysis in the s-domain shows that the proposed damping technique with a negative high-pass filter along its damping path is equivalent...... of phase-lag, in turn, helps to shrink the region of nonminimum-phase behavior caused by negative virtual resistance inserted unintentionally by most digitally implemented active damping techniques. The presented high-pass-filtered active damping technique with a single grid-current feedback loop is thus...

A Four-Phase High Voltage Conversion Ratio Bidirectional DC-DC Converter for Battery Applications

Directory of Open Access Journals (Sweden)

Li-Kun Xue

2015-06-01

Full Text Available This study presents a four-phase interleaved high voltage conversion ratio bidirectional DC-DC converter circuit based on coupled inductors and switched capacitors, which can eliminate the defects of conventional high voltage conversion ratio bidirectional DC-DC converters in terms of high-voltage/current stress, less efficiency and low-power limitation. Parallel channels are used to reduce current stress at the low-voltage side and series connected switched capacitors are used to enlarge voltage conversion ratio, reduce voltage stress and achieve auto current sharing. This paper proposes the operation principle, feature analysis and optimization design considerations. On this basis the objectives of high voltage conversion ratio, low voltage/current stress, high power density, high efficiency and high-power applications can be achieved. Some experimental results based on a 500 W prototype converter (24 V to 48 V at low-voltage side, 400 V at high-voltage side are given to verify the theoretical analysis and the effectiveness of the proposed converter.

Flexible Data Link

Science.gov (United States)

2015-04-01

DDC ) results in more complicated digital (FPGA) processing, yet simplifies the analog design significantly while improving the quality of the...Interleaved CP Cyclic Prefix DAC Digital to Analog Converter DDC Digital Down Converter DDR Double Data Rate DUC Digital Up Converter ENOB Effective

Analysis of an AC-DC full-controlled converter supplying two DC-Series-Motor loads

International Nuclear Information System (INIS)

Al-Hindawi, Mohammed M.; Al-Turki, Yusuf A.; Al-Subaie, Obaid T.

2000-01-01

Phase-controlled converters are widely used because these converters are simple, less expensive, reliable, and do not require any communication circuit. Series motors are extensively used in many applications that require both high starting torque and essentially constant horse power. This paper is concerned with the detailed study of the performance characteristics of an AC-DC full-controlled converter supplying two DC-series-motor loads. The converter loads combination is simulated on a digital computer. Different modes of operation (continuous and discontinuous converter currents) are considered. The critical firing angle at which the mode of operation changes from one mode to another is deduced. The performance characteristics such input power factor, supply current distortion factor, supply current fundamental power factor, torque speed, and motor current ripple factor have been derived and studied for both constant firing angle and constant load factor have been derived and studied for both constant firing angle and constant load power of one motor. Waveforms for each load current and converter current are investigated for different modes of operation. (author)

High-Performance Data Converters

DEFF Research Database (Denmark)

Steensgaard-Madsen, Jesper

-resolution internal D/A converters are required. Unit-element mismatch-shaping D/A converters are analyzed, and the concept of mismatch-shaping is generalized to include scaled-element D/A converters. Several types of scaled-element mismatch-shaping D/A converters are proposed. Simulations show that, when implemented...... in a standard CMOS technology, they can be designed to yield 100 dB performance at 10 times oversampling. The proposed scaled-element mismatch-shaping D/A converters are well suited for use as the feedback stage in oversampled delta-sigma quantizers. It is, however, not easy to make full use of their potential......-order difference of the output signal from the loop filter's first integrator stage. This technique avoids the need for accurate matching of analog and digital filters that characterizes the MASH topology, and it preserves the signal-band suppression of quantization errors. Simulations show that quantizers...

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

Science.gov (United States)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Circuit with a successive approximation analog to digital converter

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2011-01-01

During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and

Circuit with a successive approximation analog to digital converter

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2010-01-01

During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and

Einstein Critical-Slowing-Down is Siegel CyberWar Denial-of-Access Queuing/Pinning/ Jamming/Aikido Via Siegel DIGIT-Physics BEC ``Intersection''-BECOME-UNION Barabasi Network/GRAPH-Physics BEC: Strutt/Rayleigh-Siegel Percolation GLOBALITY-to-LOCALITY Phase-Transition Critical-Phenomenon

Science.gov (United States)

Buick, Otto; Falcon, Pat; Alexander, G.; Siegel, Edward Carl-Ludwig

2013-03-01

Einstein[Dover(03)] critical-slowing-down(CSD)[Pais, Subtle in The Lord; Life & Sci. of Albert Einstein(81)] is Siegel CyberWar denial-of-access(DOA) operations-research queuing theory/pinning/jamming/.../Read [Aikido, Aikibojitsu & Natural-Law(90)]/Aikido(!!!) phase-transition critical-phenomenon via Siegel DIGIT-Physics (Newcomb[Am.J.Math. 4,39(1881)]-{Planck[(1901)]-Einstein[(1905)])-Poincare[Calcul Probabilités(12)-p.313]-Weyl [Goett.Nachr.(14); Math.Ann.77,313 (16)]-{Bose[(24)-Einstein[(25)]-Fermi[(27)]-Dirac[(1927)]}-``Benford''[Proc.Am.Phil.Soc. 78,4,551 (38)]-Kac[Maths.Stat.-Reasoning(55)]-Raimi[Sci.Am. 221,109 (69)...]-Jech[preprint, PSU(95)]-Hill[Proc.AMS 123,3,887(95)]-Browne[NYT(8/98)]-Antonoff-Smith-Siegel[AMS Joint-Mtg.,S.-D.(02)] algebraic-inversion to yield ONLY BOSE-EINSTEIN QUANTUM-statistics (BEQS) with ZERO-digit Bose-Einstein CONDENSATION(BEC) ``INTERSECTION''-BECOME-UNION to Barabasi[PRL 876,5632(01); Rev.Mod.Phys.74,47(02)...] Network /Net/GRAPH(!!!)-physics BEC: Strutt/Rayleigh(1881)-Polya(21)-``Anderson''(58)-Siegel[J.Non-crystalline-Sol.40,453(80)

A Three-Phase Dual-Input Matrix Converter for Grid Integration of Two AC Type Energy Resources

DEFF Research Database (Denmark)

Liu, Xiong; Wang, Peng; Chiang Loh, Poh

2013-01-01

This paper proposes a novel dual-input matrix converter (DIMC) to integrate two three-phase ac type energy resources to a power grid. The proposed matrix converter is developed based on the traditional indirect matrix converter under reverse power flow operation mode, but with its six......-to-output voltage boost capability since power flows from the converter’s voltage source side to its current source side. Commanded currents can be extracted from the two input sources to the grid. The proposed control and modulation schemes guarantee sinusoidal input and output waveforms as well as unity input......-switch voltage source converter replaced by a nine-switch configuration. With the additional three switches, the proposed DIMC can provide six in put terminals, which make it possible to integrate two independent ac sources into a single grid-tied power electronics interface. The proposed converter has input...

Utilization of the series resonant dc link converter as a conditioning system for SMES

International Nuclear Information System (INIS)

Marschke, K.W.; Caldeira, P.P.A.; Lipo, T.A.

1992-01-01

In this paper a new superconductive magnetic energy storage (SMES) system utilizes a high-frequency series resonant dc link power converter of high efficiency as the conditioning converter is presented. This system generates a high-frequency (20 kHz or more) resonant current in a series link and switching is done at zero current instants, reducing switching losses to a minimal value. Through the utilization of an adequate control strategy, the input power factor can be fully adjusted during the charging, storing, and discharging modes of the SMES, improving the overall system efficiency. Different semiconductor devices are employed as the switching elements of the resonant converter and switching losses are established for each case. Experimental results from a monophase and three-phase system verified the results obtained from digital simulation

Non-Inverting Buck-Boost Converter for Fuel Cell Applications

DEFF Research Database (Denmark)

Schaltz, Erik; Rasmussen, Peter Omand; Khaligh, Alireza

2008-01-01

Fuel cell DC/DC converters often have to be able to both step-up and step-down the input voltage, and provide a high efficiency in the whole range of output power. Conventional negative output buck-boost and non-inverting buck-boost converters provide both step-up and step-down characteristics....... In this paper the non-inverting buck-boost with either diodes or synchronous rectifiers is investigated for fuel cell applications. Most of previous research does not consider  the parasitic in the evaluation of the converters. In this study, detailed analytical expressions of the efficiencies for the system...

Reconfigurable L-band Radar Transceiver using Digital Signal Synthesis, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — This Phase II proposal, builds upon the extensive research and digital radar design that has been successfully completed during the Phase I contract. Key innovations...

Decimal multiplication using compressor based-BCD to binary converter

Directory of Open Access Journals (Sweden)

Sasidhar Mukkamala

2018-02-01

Full Text Available The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit using parallel architecture. The proposed converters, along with binary coded decimal (BCD adder and binary to BCD converters, are used in parallel implementation of Urdhva Triyakbhyam (UT-based 32-bit BCD multiplier. To increase the performance, compressor circuits were used in converters and multiplier. The designed hardware circuits were verified by behavioural and post layout simulations. The implementation was carried out using Virtex-6 Field Programmable Gate Array (FPGA and Application Specific Integrated Circuit (ASIC with 90-nm technology library platforms. The results on FPGA shows that compressor based converters and multipliers produced less amount of propagation delay with a slight increase of hardware resources. In case of ASIC implementation, a compressor based converter delay is equivalent to conventional converter with a slight increase of gate count. However, the reduction of delay is evident in case of compressor based multiplier.

Generation of complementary sampled phase-only holograms.

Science.gov (United States)

Tsang, P W M; Chow, Y T; Poon, T-C

2016-10-03

If an image is uniformly down-sampled into a sparse form and converted into a hologram, the phase component alone will be adequate to reconstruct the image. However, the appearance of the reconstructed image is degraded with numerous empty holes. In this paper, we present a low complexity and non-iterative solution to this problem. Briefly, two phase-only holograms are generated for an image, each based on a different down-sampling lattice. Subsequently, the holograms are displayed alternately at high frame rate. The reconstructed images of the 2 holograms will appear to be a single, densely sampled image with enhance visual quality.

A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

International Nuclear Information System (INIS)

Hari Prasad, K.; Sukhwani, Menka; Saxena, Pooja; Chandratre, V.B.; Pithawa, C.K.

2014-01-01

A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively

Design of integrated all optical digital to analog converter (DAC) using 2D photonic crystals

Science.gov (United States)

Moniem, Tamer A.; El-Din, Eman S.

2017-11-01

A novel design of all optical 3 bit digital to analog (DAC) converter will be presented in this paper based on 2 Dimension photonic crystals (PhC). The proposed structure is based on the photonic crystal ring resonators (PCRR) with combining the nonlinear Kerr effect on the PCRR. The total size of the proposed optical 3 bit DAC is equal to 44 μm × 37 μm of 2D square lattice photonic crystals of silicon rods with refractive index equal to 3.4. The finite different time domain (FDTD) and Plane Wave Expansion (PWE) methods are used to back the overall operation of the proposed optical DAC.

Digital Resource Exchange About Music (DREAM): Phase 2 Usability Testing

Science.gov (United States)

Upitis, Rena; Boese, Karen; Abrami, Philip C.; Anwar, Zaeem

2015-01-01

The Digital Resource Exchange About Music (DREAM) is a virtual space for exchanging information about digital learning tools. The purpose of the present study was to determine how users responded to DREAM in the first four months after its public release. This study is the second phase of usability research on DREAM, and was conducted to guide…

Implementing The Automated Phases Of The Partially-Automated Digital Triage Process Model

Directory of Open Access Journals (Sweden)

Gary D Cantrell

2012-12-01

Full Text Available Digital triage is a pre-digital-forensic phase that sometimes takes place as a way of gathering quick intelligence. Although effort has been undertaken to model the digital forensics process, little has been done to date to model digital triage. This work discuses the further development of a model that does attempt to address digital triage the Partially-automated Crime Specific Digital Triage Process model. The model itself will be presented along with a description of how its automated functionality was implemented to facilitate model testing.

A Generic Topology Derivation Method for Single-phase Converters with Active Capacitive DC-links

DEFF Research Database (Denmark)

Wang, Haoran; Wang, Huai; Zhu, Guorong

2016-01-01

capacitive DCDC- link solutions, but important aspects of the topology assess-ment, such as the total energy storage, overall capacitive energy buffer ratio, cost, and reliability are still not available. This paper proposes a generic topology derivation method of single-phase power converters...

Radiation tolerant power converter controls

CERN Document Server

Todd, B; King, Q; Uznanski, S

2012-01-01

The Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is the world's most powerful particle collider. The LHC has several thousand magnets, both warm and super-conducting, which are supplied with current by power converters. Each converter is controlled by a purpose-built electronic module called a Function Generator Controller (FGC). The FGC allows remote control of the power converter and forms the central part of a closed-loop control system where the power converter voltage is set, based on the converter output current and magnet-circuit characteristics. Some power converters and FGCs are located in areas which are exposed to beam-induced radiation. There are numerous radiation induced effects, some of which lead to a loss of control of the power converter, having a direct impact upon the accelerator's availability. Following the first long shut down (LS1), the LHC will be able to run with higher intensity beams and higher beam energy. This is expected to lead to signifi...

High power density dc/dc converter: Selection of converter topology

Science.gov (United States)

Divan, Deepakraj M.

1990-01-01

The work involved in the identification and selection of a suitable converter topology is described. Three new dc/dc converter topologies are proposed: Phase-Shifted Single Active Bridge DC/DC Converter; Single Phase Dual Active Bridges DC/DC Converter; and Three Phase Dual Active Bridges DC/DC Converter (Topology C). The salient features of these topologies are: (1) All are minimal in structure, i.e., each consists of an input and output bridge, input and output filter and a transformer, all components essential for a high power dc/dc conversion process; (2) All devices of both the bridges can operate under near zero-voltage conditions, making possible a reduction of device switching losses and hence, an increase in switching frequency; (3) All circuits operate at a constant frequency, thus simplifying the task of the magnetic and filter elements; (4) Since, the leakage inductance of the transformer is used as the main current transfer element, problems associated with the diode reverse recovery are eliminated. Also, this mode of operation allows easy paralleling of multiple modules for extending the power capacity of the system; (5) All circuits are least sensitive to parasitic impedances, infact the parasitics are efficently utilized; and (6) The soft switching transitions, result in low electromagnetic interference. A detailed analysis of each topology was carried out. Based on the analysis, the various device and component ratings for each topology operating at an optimum point, and under the given specifications, are tabulated and discussed.

Speed Control of Matrix Converter-Fed Five-Phase Permanent Magnet Synchronous Motors under Unbalanced Voltages

Directory of Open Access Journals (Sweden)

Borzou Yousefi

2017-09-01

Full Text Available Five-phase permanent magnet synchronous motors (PMSM have special applications in which highly accurate speed and torque control of the motor are a strong requirement. Direct Torque Control (DTC is a suitable method for the driver structure of these motors. If in this method, instead of using a common five-phase voltage source inverter, a three-phase to five-phase matrix converter is used, the low-frequency current harmonics and the high torque ripple are limited, and an improved input power factor is obtained. Because the input voltages of such converters are directly supplied by input three-phase supply voltages, an imbalance in the voltages will cause problems such as unbalanced stator currents and electromagnetic torque fluctuations. In this paper, a new method is introduced to remove speed and torque oscillator factors. For this purpose, motor torque equations were developed and the oscillation components created by the unbalanced source voltage, determined. Then, using the active and reactive power reference generator, the controller power reference was adjusted in such a way that the electromagnetic torque of the motor did not change. By this means, a number of features including speed, torque, and flux of the motor were improved in terms of the above-mentioned conditions. Simulations were analyzed using Matlab/Simulink software.

Measurement of in-plane strain with dual beam spatial phase-shift digital shearography

International Nuclear Information System (INIS)

Xie, Xin; Chen, Xu; Li, Junrui; Yang, Lianxiang; Wang, Yonghong

2015-01-01

Full-field in-plane strain measurement under dynamic loading by digital shearography remains a big challenge in practice. A phase measurement for in-plane strain information within one time frame has to be achieved to solve this problem. This paper presents a dual beam spatial phase-shift digital shearography system with the capacity to measure phase distribution corresponding to in-plane strain information within a single time frame. Two laser beams with different wavelengths are symmetrically arranged to illuminate the object under test, and two cameras with corresponding filters, which enable simultaneous recording of two shearograms, are utilized for data acquisition. The phase information from the recorded shearograms, which corresponds to the in-plane strain, is evaluated by the spatial phase-shift method. The spatial phase-shift shearography system realizes a measurement of the in-plane strain through the introduction of the spatial phase-shift technique, using one frame after the loading and one frame before loading. This paper presents the theory of the spatial phase-shift digital shearography for in-plane strain measurement and its derivation, experimental results, and the technique’s potential. (paper)

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

Directory of Open Access Journals (Sweden)

Mostafa Chakir

2017-01-01

Full Text Available The CMOS Monolithic Active Pixel Sensor (MAPS for the International Linear Collider (ILC vertex detector (VXD expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC. This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor.

Science.gov (United States)

Chakir, Mostafa; Akhamal, Hicham; Qjidaa, Hassan

2017-01-01

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18  μ m CMOS process with a pixel pitch of 35  μ m. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76  μ m 2 . The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/-0.0787 LSB and 0.0811/-0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

Research on Single-Phase PWM Converter with Reverse Conducting IGBT Based on Loss Threshold Desaturation Control

Directory of Open Access Journals (Sweden)

Xianjin Huang

2017-11-01

Full Text Available In the application of vehicle power supply and distributed power generation, there are strict requirements for the pulse width modulation (PWM converter regarding power density and reliability. When compared with the conventional insulated gate bipolar transistor (IGBT module, the Reverse Conducting-Insulated Gate Bipolar Transistor (RC-IGBT with the same package has a lower thermal resistance and higher current tolerance. By applying the gate desaturation control, the reverse recovery loss of the RC-IGBT diode may be reduced. In this paper, a loss threshold desaturation control method is studied to improve the output characteristics of the single-phase PWM converter with a low switching frequency. The gate desaturation control characteristics of the RC-IGBT’s diode are studied. A proper current limit is set to avoid the ineffective infliction of the desaturation pulse, while the bridge arm current crosses zero. The expectation of optimized loss decrease is obtained, and the better performance for the RC-IGBTs of the single-phase PWM converter is achieved through the optimized desaturation pulse distribution. Finally, the improved predictive current control algorithm that is applied to the PWM converter with RC-IGBTs is simulated, and is operated and tested on the scaled reduced power platform. The results prove that the gate desaturation control with the improved predictive current algorithm may effectively improve the RC-IGBT’s characteristics, and realize the stable output of the PWM converter.

Number-to-voltage converter on commutated condensers

International Nuclear Information System (INIS)

Grekhov, Yu.N.

1975-01-01

A code-voltage converter using precision voltage dividers based on commutated capacitors [1] is described which is distinguished by the absence of precision elements. Each digit includes eight field-effect transistors in two 1KT682 microcircuit assemblies and three microcapacitors with a conventional unstable capacitance 6200 pF +- 50%. The converter has a speed of response that is not inferior to that of converters based on R-2R matrices, while in time stability of the characteristics, low interference level, and low output impedance it is superior to such converters

Time-interleaved high-speed D/A converters

NARCIS (Netherlands)

Olieman, E.

2016-01-01

This thesis is on power efficient very high-speed digital-to-analog converters (DACs) in CMOS technology, intended to generate signals from DC to RF. Components in RF signal chains are nowadays often moved from the analog domain to the digital domain. This allows for more flexibility and better

Digital in-line holography assessment for general phase and opaque particle

NARCIS (Netherlands)

Coëtmellec, S.; Wichitwong, W.; Gréhan, G.; Lebrun, D.; Brunel, M.; Janssen, A.J.E.M.

2014-01-01

We propose using the circle polynomials to describe a particle’s transmission function in a digital holography setup. This allows both opaque and phase particles to be determined. By means of this description, we demonstrate that it is possible to estimate the digital in-line hologram produced by a

Digital Simulation of Closed Loop Zvs-Zcs Bidirectional Dc-Dc Converter for Fuel Cell and Battery Application

Directory of Open Access Journals (Sweden)

V. V. Subrahmanya Kumar Bhajana

2010-08-01

Full Text Available A closed loop ZVS-ZCS bidirectional dc-dc converter is modeled and appropriate digital simulations are provided. With the ZVS-ZCS concept, the MATLAB simulation results of application to a fuel cell and battery application have been obtained whenever the input voltage exceeds the given 24V, at that time the load voltage will change from 180V to 230V. But due to this usage the load is disturbed and there is instability in the model. Using closed loop the output voltage is stabilized.

Phase unwrapping in digital holography based on non-subsampled contourlet transform

Science.gov (United States)

Zhang, Xiaolei; Zhang, Xiangchao; Xu, Min; Zhang, Hao; Jiang, Xiangqian

2018-01-01

In the digital holographic measurement of complex surfaces, phase unwrapping is a critical step for accurate reconstruction. The phases of the complex amplitudes calculated from interferometric holograms are disturbed by speckle noise, thus reliable unwrapping results are difficult to be obtained. Most of existing unwrapping algorithms implement denoising operations first to obtain noise-free phases and then conduct phase unwrapping pixel by pixel. This approach is sensitive to spikes and prone to unreliable results in practice. In this paper, a robust unwrapping algorithm based on the non-subsampled contourlet transform (NSCT) is developed. The multiscale and directional decomposition of NSCT enhances the boundary between adjacent phase levels and henceforth the influence of local noise can be eliminated in the transform domain. The wrapped phase map is segmented into several regions corresponding to different phase levels. Finally, an unwrapped phase map is obtained by elevating the phases of a whole segment instead of individual pixels to avoid unwrapping errors caused by local spikes. This algorithm is suitable for dealing with complex and noisy wavefronts. Its universality and superiority in the digital holographic interferometry have been demonstrated by both numerical analysis and practical experiments.

All Digital Switch-Mode DC/DC Converters with BIST Functionality for Harsh Space Environments, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — The Space Micro Arizona State University (ASU) team will develop an all-digitally controlled, wide temperature range point-of-load switch-mode DC-DC regulator core...

Utilization of the voltage frequency converter or digital representation and documentation of transient reactor operation

International Nuclear Information System (INIS)

Doane, Harry J.

1986-01-01

The ease and speed of handling transient data is enhanced by the use of a voltage to frequency converter (VFC). This analogue to digital semiconductor device provides an inexpensive and portable alternative to electro-mechanical recorders and hand entry of data into computer codes. The VFC used at The University of Arizona is a Teledyne Philbrick 4705/01. A zero to positive ten volt input signal provides a zero to one megahertz output signal which is TTL/DTL compatible. VFC is used at the University of Arizona to collect data for super prompt critical TRIGA excursions. The VFC provides a low cost, convenient method of transient data storage and retrieval for experimentation and laboratory demonstration

Digital control in LLRF system for CYCIAE-100 cyclotron

Energy Technology Data Exchange (ETDEWEB)

Yin, Zhiguo, E-mail: bitbearAT@hotmail.com; Fu, Xiaoliang; Ji, Bin; Zhang, Tianjue; Wang, Chuan

2016-05-21

As a driven accelerator, the CYCIAE-100 cyclotron is designed by China Institute of Atomic Energy for the Beijing Radio Ion-beam Facility project. The cyclotron RF system is designed to use two RF power sources of 100 kW to drive two half-wavelength cavities respectively. Two Dee accelerating electrodes are kept separately from each other inside the cyclotron, while their accelerating voltages are maintained in phase by the efforts of LLRF control. An analog–digital hybrid LLRF system has been developed to achieve cavity tuning control, dee voltage amplitude and phase stabilization etc. The analog subsystems designs are focused on RF signal up/down conversion, tuning control, and dee voltage regulation. The digital system provides an RF signal source, aligns the cavity phases and maintains a Finite State Machine. The digital parts combine with the analog functions to provide the LLRF control. A brief system hardware introduction will be given in this paper, followed by the review of several major characteristics of the digital control in the 100 MeV cyclotron LLRF system. The commissioning is also introduced, and most of the optimization during the process was done by changing the digital parts.

Phase recovering algorithms for extended objects encoded in digitally recorded holograms

Directory of Open Access Journals (Sweden)

Peng Z.

2010-06-01

Full Text Available The paper presents algorithms to recover the optical phase of digitally encoded holograms. Algorithms are based on the use of a numerical spherical reconstructing wave. Proof of the validity of the concept is performed through an experimental off axis digital holographic set-up. Two-color digital holographic reconstruction is also investigated. Application of the color set-up and algorithms concerns the simultaneous two-dimensional deformation measurement of an object submitted to a mechanical loading.

60 GHz 5-bit digital controlled phase shifter in a digital 40 nm CMOS technology without ultra-thick metals

NARCIS (Netherlands)

Gao, H.; Ying, K.; Matters-Kammerer, M.K.; Harpe, P.; Wang, B.; Liu, B.; Serdijn, W.A.; Baltus, P.G.M.

2016-01-01

A 5-bit digital controlled switch-type passive phase shifter realised in a 40 nm digital CMOS technology without ultra-thick metals for the 60 GHz Industrial, Scientific and Medical (ISM) band is presented. A patterned shielding with electromagnetic bandgap structure and a stacked metals method to

Performance evaluation of a three-phase dual active bridge DC-DC converter with different transformer winding configurations

NARCIS (Netherlands)

Baars, N.; Everts, J.; Wijnands, K.; Lomonova, E.

2016-01-01

This paper investigates the impact of three transformer winding configurations, i.e. the Y-Y, the Y-Delta, and the Delta-Delta configuration, on the performance of a three-phase dual active bridge (DAB) dc–dc converter. For each configuration, equations for the phase currents, power flow, and zero

A 12-bit spectroscopy analog-to-digital converter type SAA (Successive Approximation type with channel width Averaging) intended for multichannel pulse height analyzer SWAN-1 based on IBM PC/XT/AT

International Nuclear Information System (INIS)

Borsuk, S.; Kulka, Z.

1989-12-01

A 12-bit spectroscopy analog-to-digital converter (ADC) type SAA (Successive Approximation type with channel width Averaging) intended for multichannel pulse height analyzer SWAN-1 based on IBM PC/XT/AT has been described. Design principles, specifications and measurements of a fundamental SAA-2 converter version are reported. Finally, two next versions of the converter with introduced modifications are discussed. 6 refs., 7 figs. (author)

A digital-type fluxgate magnetometer using a sigma-delta digital-to-analog converter for a sounding rocket experiment

International Nuclear Information System (INIS)

Iguchi, Kyosuke; Matsuoka, Ayako

2014-01-01

One of the design challenges for future magnetospheric satellite missions is optimizing the mass, size, and power consumption of the instruments to meet the mission requirements. We have developed a digital-type fluxgate (DFG) magnetometer that is anticipated to have significantly less mass and volume than the conventional analog-type. Hitherto, the lack of a space-grade digital-to-analog converter (DAC) with good accuracy has prevented the development of a high-performance DFG. To solve this problem, we developed a high-resolution DAC using parts whose performance was equivalent to existing space-grade parts. The developed DAC consists of a 1-bit second-order sigma-delta modulator and a fourth-order analog low-pass filter. We tested the performance of the DAC experimentally and found that it had better than 17-bits resolution in 80% of the measurement range, and the linearity error was 2 −13.3  of the measurement range. We built a DFG flight model (in which this DAC was embedded) for a sounding rocket experiment as an interim step in the development of a future satellite mission. The noise of this DFG was 0.79 nT rms  at 0.1–10 Hz, which corresponds to a roughly 17-bit resolution. The results show that the sigma-delta DAC and the DFG had a performance that is consistent with our optimized design, and the noise was as expected from the noise simulation. Finally, we have confirmed that the DFG worked successfully during the flight of the sounding rocket. (paper)

A digital-type fluxgate magnetometer using a sigma-delta digital-to-analog converter for a sounding rocket experiment

Science.gov (United States)

Iguchi, Kyosuke; Matsuoka, Ayako

2014-07-01

One of the design challenges for future magnetospheric satellite missions is optimizing the mass, size, and power consumption of the instruments to meet the mission requirements. We have developed a digital-type fluxgate (DFG) magnetometer that is anticipated to have significantly less mass and volume than the conventional analog-type. Hitherto, the lack of a space-grade digital-to-analog converter (DAC) with good accuracy has prevented the development of a high-performance DFG. To solve this problem, we developed a high-resolution DAC using parts whose performance was equivalent to existing space-grade parts. The developed DAC consists of a 1-bit second-order sigma-delta modulator and a fourth-order analog low-pass filter. We tested the performance of the DAC experimentally and found that it had better than 17-bits resolution in 80% of the measurement range, and the linearity error was 2-13.3 of the measurement range. We built a DFG flight model (in which this DAC was embedded) for a sounding rocket experiment as an interim step in the development of a future satellite mission. The noise of this DFG was 0.79 nTrms at 0.1-10 Hz, which corresponds to a roughly 17-bit resolution. The results show that the sigma-delta DAC and the DFG had a performance that is consistent with our optimized design, and the noise was as expected from the noise simulation. Finally, we have confirmed that the DFG worked successfully during the flight of the sounding rocket.

Digital device for synchronous storage

International Nuclear Information System (INIS)

Kobzar', Yu.M.; Kovtun, V.G.; Pashechko, N.I.

1991-01-01

Synchronous storage digital device for IR electron-photon emission spectrometer operating with analogue-to-digital converter F4223 or monocrystal converter K572PV1 is described. The device accomplished deduction of noise-background in each storage cycle. Summation and deduction operational time equals 90 ns, device output code discharge - 20, number of storages -2 23

Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

International Nuclear Information System (INIS)

Jinyuan Wu; Zonghan Shi; Irena Y Wang

2003-01-01

A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

Crystal Phase Quantum Well Emission with Digital Control.

Science.gov (United States)

Assali, S; Lähnemann, J; Vu, T T T; Jöns, K D; Gagliano, L; Verheijen, M A; Akopian, N; Bakkers, E P A M; Haverkort, J E M

2017-10-11

One of the major challenges in the growth of quantum well and quantum dot heterostructures is the realization of atomically sharp interfaces. Nanowires provide a new opportunity to engineer the band structure as they facilitate the controlled switching of the crystal structure between the zinc-blende (ZB) and wurtzite (WZ) phases. Such a crystal phase switching results in the formation of crystal phase quantum wells (CPQWs) and quantum dots (CPQDs). For GaP CPQWs, the inherent electric fields due to the discontinuity of the spontaneous polarization at the WZ/ZB junctions lead to the confinement of both types of charge carriers at the opposite interfaces of the WZ/ZB/WZ structure. This confinement leads to a novel type of transition across a ZB flat plate barrier. Here, we show digital tuning of the visible emission of WZ/ZB/WZ CPQWs in a GaP nanowire by changing the thickness of the ZB barrier. The energy spacing between the sharp emission lines is uniform and is defined by the addition of single ZB monolayers. The controlled growth of identical quantum wells with atomically flat interfaces at predefined positions featuring digitally tunable discrete emission energies may provide a new route to further advance entangled photons in solid state quantum systems.

An efficient digital phase sensitive detector for use in electron spin resonance spectroscopy

International Nuclear Information System (INIS)

Vistnes, A.I; Wormald, D.I.; Isachsen, S.

1983-10-01

A digital sensitive detector for a modified Bruker electron spin resonance spectrometer, equipped with an Aspect 2000 minicomputer, is described. Magnetic field modulation is derived from a clock in the computer, which makes it possible to perform the data acquisition fully synchronously with the modulation. The resulting high phase accuracy makes it possible to compress the data to a single modulation period before the Fourier transformation. Both the in-phase and the phase-quadrature signals (of the first or second harmonic) are recorded simultaneously. The system makes the data processing, including the Fourier transformation, approximately 1000 times faster than previously reported digital phase sensitive detector systems for electron spin resonance spectrometers

The characterization and application of a low resource FPGA-based time to digital converter

Energy Technology Data Exchange (ETDEWEB)

Balla, Alessandro; Mario Beretta, Matteo; Ciambrone, Paolo; Gatta, Maurizio; Gonnella, Francesco [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); Iafolla, Lorenzo, E-mail: lorenzo.iafolla@lnf.infn.it [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); University of Rome “Tor Vergata” – Electronic Engineering Department (Italy); Mascolo, Matteo; Messi, Roberto [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); University of Rome “Tor Vergata” – Physics Department (Italy); Moricciani, Dario [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); Riondino, Domenico [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy)

2014-03-01

Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of “off-the-shelf” TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured. - Highlights: • We need to measure the Time of Flight of the detected particles to reconstruct physics events. • We looked for an embedded solution based on an FPGA to implement a TDC with its DAQ system. • The solution is based on the 4xOversampling technique which employs very effectively the FPGA. • The 4×Oversampling technique was characterized and the results and comparisons with the state of the art are presented.

LDRD final report: photonic analog-to-digital converter (ADC) technology; TOPICAL

International Nuclear Information System (INIS)

Bowers, M; Deri, B; Haigh, R; Lowry, M; Sargis, P; Stafford, R; Tong, T

1999-01-01

We report on an LDRD seed program of novel technology development (started by an FY98 Engineering Tech-base project) that will enable extremely high-fidelity analog-to-digital converters for a variety of national security missions. High speed (l0+ GS/s ), high precision (l0+ bits) ADC technology requires extremely short aperture times ((approx)1ps ) with very low jitter requirements (sub 10fs ). These fundamental requirements, along with other technological barriers, are difficult to realize with electronics: However, we outline here, a way to achieve these timing apertures using a novel multi-wavelength optoelectronic short-pulse optical source. Our approach uses an optoelectronic feedback scheme with high optical Q to produce an optical pulse train with ultra-low jitter ( sub 5fs) and high amplitude stability ( and lt;10(sup 10)). This approach requires low power and can be integrated into an optoelectronic integrated circuit to minimize the size. Under this seed program we have demonstrated that the optical feedback mechanism can be used to generate a high Q resonator. This has reduced the technical risk for further development, making it an attractive candidate for outside funding

A Novel Multilevel Quad-Inverter Configuration for Quasi Six-Phase Open-Winding Converter

DEFF Research Database (Denmark)

Padmanaban, Sanjeevi Kumar; Blaabjerg, Frede; Wheeler, Patrick

2016-01-01

This paper developed a novel quad-inverter configuration for multilevel six-phase asymmetrical open-winding AC converter. Proposal found to be suited for (low-voltage/high-current) applications such as AC tractions and `More-Electric Aircraft' propulsion systems. Modular power circuit comprises...... of standard four three-phase voltage source inverter (VSI) and each connected to the open-end windings. Each VSIs are incorporated with one bi-directional switching device (MOSFET/IGBT) per phase and two capacitors with neutral point connected. Further, an original modified single carrier five...... and quadruples the capabilities of VSIs. A set of observed results is presented with numerical software analysis (Matlab/PLECS) in balanced working conditions. Always the results shown good agreement in the developed theoretical background....

Performance Improvement for Two-Stage Single-Phase Grid-Connected Converters Using a Fast DC Bus Control Scheme and a Novel Synchronous Frame Current Controller

Directory of Open Access Journals (Sweden)

Bingzhang Li

2017-03-01

Full Text Available Two-stage single-phase grid-connected converters are widely used in renewable energy applications. Due to the presence of a second harmonic ripple across the DC bus voltage, it is very challenging to design the DC bus voltage control scheme in single-phase grid-connected inverters. The DC bus voltage controller must filter the ripple and balance a tradeoff between low harmonic distortion and high bandwidth. This paper presents a fast DC bus voltage controller, which uses a second order digital finite impulse response (FIR notch filter in conjunction with input power feedforward scheme to ensure the steady-state and dynamic performance. To gain the input power without extra hardware, a Kalman filter is incorporated to estimate the DC bus input current. At the same time, a modulation compensation strategy is implemented to eliminate the nonlinearity of the grid current control loop, which is caused by the DC bus voltage ripple. Moreover, a novel synchronous frame current controller for single-phase systems is also introduced, and its equivalent model in stationary frame has been derived. Simulation and experimental results are provided to verify the effective of the proposed control scheme.

Residual phase noise measurements of the input section in a receiver

International Nuclear Information System (INIS)

Mavric, Uros; Chase, Brian; Fermilab

2007-01-01

If not designed properly, the input section of an analog down-converter can introduce phase noise that can prevail over other noise sources in the system. In the paper we present residual phase noise measurements of a simplified input section of a classical receiver that is composed of various commercially available mixers and driven by an LO amplifier

PS BOOSTER BEAM TESTS OF THE NEW DIGITAL BEAM CONTROL SYSTEM FOR LEIR

CERN Document Server

Angoletta, Maria Elena; Bento, J; De Long, J H; Findlay, A; Matuszkiewicz, P; Pedersen, F; Salom-Sarasqueta, A; CERN. Geneva. AB Department

2005-01-01

We have been developing a scaled-down prototype of the new digital beam control and cavity servoing system for CERN’s Low Energy Ion Ring (LEIR) slated for commissioning in 2005. The system’s hardware and software, developed as part of a CERN-BNL collaboration, are based on new all-digital technology already deployed at BNL's AGS Booster. The system relies on VME modules, carrying Digital Signal Processors (DSPs) as well as Field Programmable Gate Arrays (FPGAs), and daughter cards. New concepts deployed include software implementation, through DSPs & FPGAs, of functions traditionally executed by analogue hardware, such as reference-functions and timings generation. Additionally, a user-selectable digital data acquisition functionality provides diagnostic and troubleshoot access points, a new feature which is very useful in a digital system. The scaled-down prototype implements frequency program, radial steering, phase and radial loops capabilities and it has been tested in CERN's PS Booster (PSB) dur...

A resonant dc-dc power converter assembly

DEFF Research Database (Denmark)

2015-01-01

The present invention relates to a resonant DC-DC power converter assembly comprising a first resonant DC-DC power converter and a second resonant DC-DC power converter having identical circuit topologies. A first inductor of the first resonant DC-DC power converter and a second inductor of the s......The present invention relates to a resonant DC-DC power converter assembly comprising a first resonant DC-DC power converter and a second resonant DC-DC power converter having identical circuit topologies. A first inductor of the first resonant DC-DC power converter and a second inductor...... of the second resonant DC-DC power converter are configured for magnetically coupling the first and second resonant DC-DC power converters to each other to forcing substantially 180 degrees phase shift, or forcing substantially 0 degree phase shift, between corresponding resonant voltage waveforms of the first...

The New Digital-Receiver-Based System for Antiproton Beam Diagnostics

CERN Document Server

Angoletta, Maria Elena; Ludwig, M; Marqversen, O; Pedersen, F

2001-01-01

An innovative system to measure antiproton beam intensity, momentum spread and mean momentum in CERN's Antiproton Decelerator (AD) is described. This system is based on a state-of-the-art Digital Receiver (DRX) board, consisting of 8 Digital Down-Converter (DDC) chips and one Digital Signal Processor (DSP). An ultra-low-noise, wide-band AC beam transformer (0.2 MHz - 30 MHz) is used to measure AC beam current modulation. For bunched beams, the intensity is obtained by measuring the amplitude of the fundamental and second RF Fourier components. On the magnetic plateaus the beam is debunched for stochastic or electron cooling and longitudinal beam properties (intensity, momentum spread and mean momentum) are measured by FFT-based spectral analysis of Schottky signals. The system thus provides real time information characterising the machine performance; it has been used for troubleshooting and to fine-tune the AD, thus achieving further improved performances. This system has been operating since May 2000 and ty...

Understanding delta-sigma data converters

CERN Document Server

Pavan, Shanti; Temes, Gabor C

2017-01-01

This new edition introduces novel analysis and design techniques for delta-sigma (ΔΣ) converters in physical and conceptual terms, and includes new chapters that explore developments in the field over the last decade. This book explains the principles and operation of delta-sigma analog-to-digital converters (ADCs) in physical and conceptual terms in accordance with the most recent developments in the field. The interest of ΔΣ converter designers has shifted significantly over the past decade, due to many new applications for data converters at the far ends of the frequency spectrum. Continuous-time delta-sigma A/D converters with GHz clocks, of both lowpass and bandpass types, are required for wireless applications. At the other extreme, multiplexed ADCs with very narrow (sometimes 10 Hz wide) signal bandwidths, but very high accuracy are needed in the interfaces of biomedical and environmental sensors. To reflect the changing eeds of designers, the second edition includes significant new material on bo...

An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

Directory of Open Access Journals (Sweden)

Chao Chen

2014-01-01

Full Text Available We describe the architecture of a time-to-digital converter (TDC, specially intended to measure the delay resolution of a programmable delay line (PDL. The configuration, which consists of a ring oscillator, a frequency divider (FD, and a period measurement circuit (PMC, is implemented in a field programmable gate array (FPGA device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits

International Nuclear Information System (INIS)

Nishigai, T.; Ito, M.; Yoshikawa, N.; Fujimaki, A.; Terai, H.; Yorozu, S.

2005-01-01

We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10 ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10 ps

A Control Method of Current Type Matrix Converter for Plasma Control Coil Power Supply

International Nuclear Information System (INIS)

Shimada, K.; Matsukawa, M.; Kurihara, K.; Jun-ichi Itoh

2006-01-01

In exploration to a tokamak fusion reactor, the control of plasma instabilities of high β plasma such as neoclassical tearing mode (NTM), resistive wall mode (RWM) etc., is the key issue for steady-state sustainment. One of the proposed methods to avoid suppressing RWM is that AC current having a phase to work for reduction the RWM growth is generated in a coil (sector coil) equipped spirally on the plasma vacuum vessel. To stabilize RWM, precise and fast real-time feedback control of magnetic field with proper amplitude and frequency is necessary. This implies that an appropriate power supply dedicated for such an application is expected to be developed. A matrix converter as one of power supply candidates for this purpose could provide a solution The matrix converter, categorized in an AC/AC direct converter composed of nine bi-directional current switches, has a great feature that a large energy storage element is unnecessary in comparison with a standard existing AC/AC indirect converter, which is composed of an AC/DC converter and a DC/AC inverter. It is also advantageous in cost and size of its applications. Fortunately, a voltage type matrix converter has come to be available at the market recently, while a current type matrix converter, which is advantageous for fast control of the large-inductance coil current, has been unavailable. On the background above mentioned, we proposed a new current type matrix converter and its control method applicable to a power supply with fast response for suppressing plasma instabilities. Since this converter is required with high accuracy control, the gate control method is adopted to three-phase switching method using middle phase to reduce voltage and current waveforms distortion. The control system is composed of VME-bus board with DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) for high speed calculation and control. This paper describes the control method of a current type matrix converter

Making the Switch to Digital Audio

Directory of Open Access Journals (Sweden)

Shannon Gwin Mitchell

2004-12-01

Full Text Available In this article, the authors describe the process of converting from analog to digital audio data. They address the step-by-step decisions that they made in selecting hardware and software for recording and converting digital audio, issues of system integration, and cost considerations. The authors present a brief description of how digital audio is being used in their current research project and how it has enhanced the “quality” of their qualitative research.

5kW phase-shifted full-bridge converter with current doubler using normally-off SiC JFETs designed for 98% efficiency

DEFF Research Database (Denmark)

Török, Lajos; Beczkowski, Szymon; Munk-Nielsen, Stig

2013-01-01

In this paper a 5kW step-down converter for low-voltage high-current application is presented using normally-off SiC JFETs as high voltage power switches, operating with efficiency close to 98%. Different low voltage side rectification solutions and loss estimations are also presented. As results...

A single-phase PWM controlled AC to DC converter based on control of unity displacement power factor

OpenAIRE

Funabiki, Shigeyuki

1990-01-01

A modified pulse-width modulation (PWM) technique that improves the displacement power factor and the input power factor of a single-phase AC to DC converter is discussed. The modified converter is shown to have a high input power factor and allows the of DC voltage from zero to more than the maximum value of the source voltage. The displacement power factor is unity, and the input power factor is almost unity in the wide range of current command

Influence of modulation method on using LC-traps with single-phase voltage source converters

DEFF Research Database (Denmark)

Wang, Xiongfei; Min, Huang; Bai, Haofeng

2015-01-01

The switching-frequency LC-trap filter has recently been employed with high-order passive filters for Voltage Source Inverters (VSIs). This paper investigates the influence of modulation method on using the LC-traps with single-phase VSIs. Two-level (bipolar) and three-level (unipolar) modulations...... that include phase distortion and alternative phase opposition distortion methods are analyzed. Harmonic filtering performances of four LC-trap-based filters with different locations of LC-traps are compared. It is shown that the use of parallel-LC-traps in series with filter inductors, either grid...... or converter side, has a worse harmonic filtering performance than using series-LC-trap in the shunt branch. Simulations and experimental results are presented for verifications....

SlaVaComp Fonts Converter

Directory of Open Access Journals (Sweden)

Simon Skilevic

2013-12-01

Full Text Available This paper presents a fonts converter that was developed as a part of the Freiburg project on historical corpus linguistics. The tool named SlaVaComp-Konvertierer converts Church Slavonic texts digitized with non-Unicode fonts into the Unicode format without any loss of information contained in the original file and without damage to the original formatting. It is suitable for the conversion of all idiosyncratic fonts—not only Church Slavonic—and therefore can be used not only in Palaeoslavistic, but also in all historical and philological studies.

Speed-controlled three-phase drives. Drehzahlgeregelte Drehstromantriebe

Energy Technology Data Exchange (ETDEWEB)

Steinmetz, E

1981-01-01

Present semiconductor circuit elements have made it possible to produce frequency converters for speed-controlled three-phase drives from the k'' range to the MW range at low cost. Line-powered frequency converter circuits are already in the standardisation stage while the development trends in the field of speed-controlled frequency converter circuits are not foreseeable as yet. Recent developments in the field of electronics have made the circuits simpler and able to implement an increasing number of functions. There is a trend towards programmable digital control systems with microcomputers. Of the 8 articles in the publication, the contribution by M. Wild and R. Wetzl (Synchronous motors with frequency converters drive boiler feed pumps at Bergkamen power plant) has been entered in the data base as a separate citation.

Image processing by use of the digital cross-correlator

International Nuclear Information System (INIS)

Katou, Yoshinori

1982-01-01

We manufactured for trial an instrument which achieved the image processing using digital correlators. A digital correlator perform 64-bit parallel correlation at 20 MH. The output of a digital correlator is a 7-bit word representing. An A-D converter is used to quantize it a precision of six bits. The resulting 6-bit word is fed to six correlators, wired in parallel. The image processing achieved in 12 bits, whose digital outputs converted an analog signal by a D-A converter. This instrument is named the digital cross-correlator. The method which was used in the image processing system calculated the convolution with the digital correlator. It makes various digital filters. In the experiment with the image processing video signals from TV camera were used. The digital image processing time was approximately 5 μs. The contrast was enhanced and smoothed. The digital cross-correlator has the image processing of 16 sorts, and was produced inexpensively. (author)

Digital low level rf control system with four different intermediate frequencies for the International Linear Collider

Science.gov (United States)

Wibowo, Sigit Basuki; Matsumoto, Toshihiro; Michizono, Shinichiro; Miura, Takako; Qiu, Feng; Liu, Na

2017-09-01

A field programmable gate array-based digital low level rf (LLRF) control system will be used in the International Linear Collider (ILC) in order to satisfy the rf stability requirements. The digital LLRF control system with four different intermediate frequencies has been developed to decrease the required number of analog-to-digital converters in this system. The proof of concept of this technique was demonstrated at the Superconducting RF Test Facility in the High Energy Accelerator Research Organization, Japan. The amplitude and phase stability has fulfilled the ILC requirements.

Digital Line Graphs (DLG) 24K

Data.gov (United States)

Kansas Data Access and Support Center — Digital line graph (DLG) data are digital representations of cartographic information. DLG's of map features are converted to digital form from maps and related...

Digital Line Graphs (DLG) 100K

Data.gov (United States)

Kansas Data Access and Support Center — Digital line graph (DLG) data are digital representations of cartographic information. DLG's of map features are converted to digital form from maps and related...

Electronic circuit for rapid digital NMR signal imaging

International Nuclear Information System (INIS)

Jurak, P.; Krejci, I.; Belusa, J.

1992-01-01

The circuit is made up of two analog-to-digital converters whose outputs are connected to a process computer and the synchronization inputs to the clock terminal. The one analog-to-digital converter is connected, via the signal input, to the terminal of the nuclear magnetic resonance locking signal. The signal input of the other analog-to-digital converter is connected to the time base generator, which can be switched off, and to the magnetic field sweep circuit. The assets of this citcuit include easy computerized processing of the digitized information independently of the time base generation, and prevention of interfering signals from penetrating into the magnetic field sweep circuits. (Z.S.). 1 fig

Design and assessment of a 6 ps-resolution time-to-digital converter with 5 MGy gamma-dose tolerance for nuclear instrumentation

International Nuclear Information System (INIS)

Cao, Y.; Leroux, P.; De Cock, W.; Steyaert, M.

2011-01-01

Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog signals in time domain. A short survey on state-of-the-art TDCs is given. In order to realize a TDC with picosecond time resolution as well as multi MGy gamma-dose radiation tolerance, a novel multi-stage noise-shaping (MASH) delta-sigma (ΔΣ) TDC structure is proposed. The converter, implemented in 0.13 μm, achieves a time resolution of 5.6 ps and an ENOB of 11 bits, when the over sampling ratio (OSR) is 250. The TDC core consumes only 1.7 mW, and occupies an area of 0.11 mm 2 . Owing to the usage of circuit level radiation hardened-by-design techniques, such as passive RC oscillators and constant-g m biasing, the TDC exhibits enhanced radiation tolerance. At a low dose rate of 1.2 kGy/h, the frequency of the counting clock in the TDC remains constant up to at least 160 kGy. Even after a total dose of 3.4 MGy at a high dose rate of 30 kGy/h, the TDC still achieves a time resolution of 10.5 ps with an OSR of 250. (authors)

Design and assessment of a 6 ps-resolution time-to-digital converter with 5 MGy gamma-dose tolerance for nuclear instrumentation

Energy Technology Data Exchange (ETDEWEB)

Cao, Y. [ESAT-MICAS Div., Katholieke Universiteit Leuven, B-3001 Heverlee (Belgium); SCK.CEN, Belgian Nuclear Research Centre, B-2400 Mol (Belgium); Leroux, P. [ESAT-MICAS Div., Katholieke Universiteit Leuven, B-3001 Heverlee (Belgium); ICT-RELIC Div., Katholieke Hogeschool Kempen, B-2440 Geel (Belgium); De Cock, W. [SCK.CEN, Belgian Nuclear Research Centre, B-2400 Mol (Belgium); Steyaert, M. [ESAT-MICAS Div., Katholieke Universiteit Leuven, B-3001 Heverlee (Belgium)

2011-07-01

Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog signals in time domain. A short survey on state-of-the-art TDCs is given. In order to realize a TDC with picosecond time resolution as well as multi MGy gamma-dose radiation tolerance, a novel multi-stage noise-shaping (MASH) delta-sigma ({Delta}{Sigma}) TDC structure is proposed. The converter, implemented in 0.13 {mu}m, achieves a time resolution of 5.6 ps and an ENOB of 11 bits, when the over sampling ratio (OSR) is 250. The TDC core consumes only 1.7 mW, and occupies an area of 0.11 mm{sup 2}. Owing to the usage of circuit level radiation hardened-by-design techniques, such as passive RC oscillators and constant-g{sub m} biasing, the TDC exhibits enhanced radiation tolerance. At a low dose rate of 1.2 kGy/h, the frequency of the counting clock in the TDC remains constant up to at least 160 kGy. Even after a total dose of 3.4 MGy at a high dose rate of 30 kGy/h, the TDC still achieves a time resolution of 10.5 ps with an OSR of 250. (authors)

Event-driven control of a speed varying digital displacement machine

DEFF Research Database (Denmark)

Pedersen, Niels Henrik; Johansen, Per; Andersen, Torben O.

2017-01-01

. The controller synthesis is carried out as a discrete optimal deterministic problem with full state feedback. Based on a linear analysis of the feedback control system, stability is proven in a pre-specified operation region. Simulation of a non-linear evaluation model with the controller implemented shows great...... be treated as a Discrete Linear Time Invariant control problem with synchronous sampling rate. To make synchronous linear control theory applicable for a variable speed digital displacement machine, a method based on event-driven control is presented. Using this method, the time domain differential equations...... are converted into the spatial (position) domain to obtain a constant sampling rate and thus allowing for use of classical control theory. The method is applied to a down scaled digital fluid power motor, where the motor speed is controlled at varying references under varying pressure and load torque conditions...

Development of a time-to-digital converter ASIC for the upgrade of the ATLAS Monitored Drift Tube detector

Science.gov (United States)

Wang, Jinhong; Liang, Yu; Xiao, Xiong; An, Qi; Chapman, John W.; Dai, Tiesheng; Zhou, Bing; Zhu, Junjie; Zhao, Lei

2018-02-01

The upgrade of the ATLAS muon spectrometer for the high-luminosity LHC requires new trigger and readout electronics for various elements of the detector. We present the design of a time-to-digital converter (TDC) ASIC prototype for the ATLAS Monitored Drift Tube (MDT) detector. The chip was fabricated in a GlobalFoundries 130 nm CMOS technology. Studies indicate that its timing and power dissipation characteristics meet the design specifications, with a timing bin variation of ±40 ps for all 48 TDC slices and a power dissipation of about 6.5 mW per slice.

Digitization errors using digital charge division positionsensitive detectors

International Nuclear Information System (INIS)

Berliner, R.; Mildner, D.F.R.; Pringle, O.A.

1981-01-01

The data acquisition speed and electronic stability of a charge division position-sensitive detector may be improved by using digital signal processing with a table look-up high speed multiply to form the charge division quotient. This digitization process introduces a positional quantization difficulty which reduces the detector position sensitivity. The degree of the digitization error is dependent on the pulse height spectrum of the detector and on the resolution or dynamic range of the system analog-to-digital converters. The effects have been investigated analytically and by computer simulation. The optimum algorithm for position sensing determination using 8-bit digitization and arithmetic has a digitization error of less than 1%. (orig.)

Phase-lock loop of Grid-connected Voltage Source Converter under non-ideal grid condition

DEFF Research Database (Denmark)

Wang, Haojie; Sun, Hai; Han, Minxiao

2015-01-01

It is a normal practice that the DC micro-grid is connected to AC main grid through Grid-connected Voltage Source Converter (G-VSC) for voltage support. Accurate control of DC micro-grid voltage is difficult for G-VSC under unbalanced grid condition as the fundamental positive-sequence component...... and distorted system voltage the proposed PLL can accurately detect the fundamental positive-sequence component of grid voltage thus accurate control of DC micro-grid voltage can be realized....... phase information cannot be accurately tracked. Based on analysis of the cause of double-frequency ripple when unbalance exists in main grid, a phase-locked loop (PLL) detection technique is proposed. Under the conditions of unsymmetrical system voltage, varying system frequency, single-phase system...

Test and Analysis of Metallurgical Converter Equipment

Directory of Open Access Journals (Sweden)

Shan Pang

2013-05-01

Full Text Available Oxygen top-blow converter is the main equipment in steel making, and its work reliability decides the security and economy of steel production. Therefore, how to design and test analysis of convertor has been an important subject of industry research. Geometric modelling and structure analysis of converter tilting device by using Pro/E program .The design Principle, basic design structure were analyzed in detail. The computer simulation software of metallurgical converter equipment and how to use it were introduced .It developed by VC++ software. The position of barycentre and moment curve in No.3 and No.4 are calculated. The converter acceleration down dip can be resolved by comparing the moment curve and center curve.

A 45.8fJ/Step, energy-efficient, differential SAR capacitance-to-digital converter for capacitive pressure sensing

KAUST Repository

Alhoshany, Abdulaziz

2016-05-03

An energy-efficient readout circuit for a capacitive sensor is presented. The capacitive sensor is digitized by a 12-bit energy efficient capacitance-to-digital converter (CDC) that is based on a differential successive-approximation architecture. This CDC meets extremely low power requirements by using an operational transconductance amplifier (OTA) that is based on a current-starved inverter. It uses a charge-redistribution DAC that involves coarse-fine architecture. We split the DAC into a coarse-DAC and a fine-DAC to allow a wide capacitance range in a compact area. It covers a wide range of capacitance of 16.14 pF with a 4.5 fF absolute resolution. An analog comparator is implemented by cross-coupling two 3-input NAND gates to enable power and area efficient operation. The prototype CDC was fabricated using a standard 180 nm CMOS technology. The 12-bit CDC has a measurement time of 42.5 μs, and consumes 3.54 μW and 0.29 μW from analog and digital supplies, respectively. This corresponds to a state-of-the-art figure-of-merit (FoM) of 45.8 fJ/conversion-step. © 2016 Elsevier B.V. All rights reserved.

Fast collimated neutron flux measurement using stilbene scintillator and flashy analog-to-digital converter in JT-60U

International Nuclear Information System (INIS)

Ishikawa, M.; Itoga, T.; Okuji, T.; Nakhostin, M.; Shinohara, K.; Hayashi, T.; Sukegawa, A.; Baba, M.; Nishitani, T.

2006-01-01

A line-integrated neutron emission profile is routinely measured using the radial neutron collimator system in JT-60U tokamak. Stilbene neuron detectors (SNDs), which combine a stilbene organic crystal scintillation detector (SD) with an analog neutron-gamma pulse shape discrimination (PSD) circuit, have been used to measure collimated neutron flux. Although the SND has many advantages as a neutron detector, the maximum count rate is limited up to ∼1x10 5 counts/s due to the analog PSD circuit. To overcome this issue, a digital signal processing system (DSPS) using a flash analog-to-digital converter (Acqiris DC252, 8 GHz, 10 bits) has been developed at Cyclotron and Radioisotope Center in Tohoku University. In this system anode signals from photomultiplier of the SD are directory stored and digitized. Then, the PSD between neutrons and gamma rays is performed using software. The DSPS has been installed in the vertical neutron collimator system in JT-60U and applied to deuterium experiments. It is confirmed that the PSD is sufficiently performed and collimated neutron flux is successfully measured with count rate up to ∼5x10 5 counts/s without the effect of pileup of detected pulses. The performance of the DSPS as a neutron detector, which supersedes the SND, is demonstrated

A 45.8fJ/Step, energy-efficient, differential SAR capacitance-to-digital converter for capacitive pressure sensing

KAUST Repository

Alhoshany, Abdulaziz; Omran, Hesham; Salama, Khaled N.

2016-01-01

An energy-efficient readout circuit for a capacitive sensor is presented. The capacitive sensor is digitized by a 12-bit energy efficient capacitance-to-digital converter (CDC) that is based on a differential successive-approximation architecture. This CDC meets extremely low power requirements by using an operational transconductance amplifier (OTA) that is based on a current-starved inverter. It uses a charge-redistribution DAC that involves coarse-fine architecture. We split the DAC into a coarse-DAC and a fine-DAC to allow a wide capacitance range in a compact area. It covers a wide range of capacitance of 16.14 pF with a 4.5 fF absolute resolution. An analog comparator is implemented by cross-coupling two 3-input NAND gates to enable power and area efficient operation. The prototype CDC was fabricated using a standard 180 nm CMOS technology. The 12-bit CDC has a measurement time of 42.5 μs, and consumes 3.54 μW and 0.29 μW from analog and digital supplies, respectively. This corresponds to a state-of-the-art figure-of-merit (FoM) of 45.8 fJ/conversion-step. © 2016 Elsevier B.V. All rights reserved.

Two phase interleaved buck converter for driving high power LEDs

DEFF Research Database (Denmark)

Beczkowski, Szymon; Munk-Nielsen, Stig

2011-01-01

The goal of this paper is to evaluate an interleaved buck topology for driving high current light-emitting diodes. Low output capacitor value allows the use of non-electrolytic capacitors extending the lifetime of the converter. Converter is operated as a constant, regulated current source which...... increases luminous efficacy of LED compared to PWM dimmed system. Because of the low dynamic resistance of LEDs the duty cycle of the converter does not change greatly with controlled current. By setting the input voltage of the buck converter to around twice the voltage of diode strings, converter can...

Digital control card based on digital signal processor

International Nuclear Information System (INIS)

Hou Shigang; Yin Zhiguo; Xia Le

2008-01-01

A digital control card based on digital signal processor was developed. Two Freescale DSP-56303 processors were utilized to achieve 3 channels proportional- integral-differential regulations. The card offers high flexibility for 100 MeV cyclotron RF system development. It was used as feedback controller in low level radio frequency control prototype, with the feedback gain parameters continuously adjustable. By using high precision analog to digital converter with 500 kHz sampling rate, a regulation bandwidth of 20 kHz was achieved. (authors)

Data Acquisition and Digital Filtering for Infrasonic Records on Active Volcanoes

Directory of Open Access Journals (Sweden)

José Chilo

2007-03-01

Full Text Available This paper presents the design of a digital data acquisition system for volcanic infrasound records. The system includes four electret condenser element microphones, a QF4A512 programmable signal converter from Quickfilter Technologies and a MSP430 microcontroller from Texas Instruments. The signal output of every microphone is converted to digital via a 16-bit Analog to Digital Converter (ADC. To prevent errors in the conversion process, Anti-Aliasing Filters are employed prior to the ADC. Digital filtering is performed after the ADC using a Digital Signal Processor, which is implemented on the QF4A512. The four digital signals are summed to get only one signal. Data storing and digital wireless data transmission will be described in a future paper.

Real Time Phase Noise Meter Based on a Digital Signal Processor

Science.gov (United States)

Angrisani, Leopoldo; D'Arco, Mauro; Greenhall, Charles A.; Schiano Lo Morille, Rosario

2006-01-01

A digital signal-processing meter for phase noise measurement on sinusoidal signals is dealt with. It enlists a special hardware architecture, made up of a core digital signal processor connected to a data acquisition board, and takes advantage of a quadrature demodulation-based measurement scheme, already proposed by the authors. Thanks to an efficient measurement process and an optimized implementation of its fundamental stages, the proposed meter succeeds in exploiting all hardware resources in such an effective way as to gain high performance and real-time operation. For input frequencies up to some hundreds of kilohertz, the meter is capable both of updating phase noise power spectrum while seamlessly capturing the analyzed signal into its memory, and granting as good frequency resolution as few units of hertz.

A Two-Phase Buck Converter with Optimum Phase Selection for Low Power Applications

OpenAIRE

Yeago, Taylor Craig

2015-01-01

Power consumption of smart cameras varies significantly between sleep mode and active mode, and a smart camera operates in sleep mode for 80 ��" 90% of time for typical use. To prolong the battery life of smart cameras, it is essential to increase the power converter efficiency for light load, while being able to manage heavy load. The power stage of traditional buck converter is optimized for maximum load, at the cost of light-load efficiency. Wei proposed a multiphase buck converter incorpo...

An analytical inductor design procedure for three-phase PWM converters in power factor correction applications

DEFF Research Database (Denmark)

Kouchaki, Alireza; Niroumand, Farideh Javidi; Haase, Frerk

2015-01-01

This paper presents an analytical method for designing the inductor of three-phase power factor correction converters (PFCs). The complex behavior of the inductor current complicates the inductor design procedure as well as the core loss and copper loss calculations. Therefore, this paper analyze...... to calculate the core loss in the PFC application. To investigate the impact of the dc link voltage level, two inductors for different dc voltage levels are designed and the results are compared.......This paper presents an analytical method for designing the inductor of three-phase power factor correction converters (PFCs). The complex behavior of the inductor current complicates the inductor design procedure as well as the core loss and copper loss calculations. Therefore, this paper analyzes...... circuit is used to provide the inductor current harmonic spectrum. Therefore, using the harmonic spectrum, the low and high frequency copper losses are calculated. The high frequency minor B-H loops in one switching cycle are also analyzed. Then, the loss map provided by the measurement setup is used...

A digital closed loop control system for automatic phase locking of superconducting cavities of IUAC Linac

International Nuclear Information System (INIS)

Dutt, R.N.; Rai, A.; Pandey, A.; Sahu, B.K.; Patra, P.; Karmakar, J.; Chaudhari, G.K.; Mathur, Y.; Ghosh, S.; Kanjilal, D.

2013-01-01

A closed loop digital control system has been designed and tested to automate the tuning process of superconducting resonators of LINAC at Inter-University Accelerator Centre, New Delhi. The mechanism controls the proportional valves of the He gas based pneumatic tuner in response to the phase and frequency errors of the cavity RF field. The main RF phase lock loop (PLL) is automatically closed once the resonant frequency is within locking range of the resonator PLL. The digital control scheme was successfully tested on few resonators of LINAC cryostat 1. A high stability of phase lock was observed. The details of the digital automation system are presented in the paper. (author)

Thermal heat-balance mode flow-to-frequency converter

Science.gov (United States)

Pawlowski, Eligiusz

2016-11-01

This paper presents new type of thermal flow converter with the pulse frequency output. The integrating properties of the temperature sensor have been used, which allowed for realization of pulse frequency modulator with thermal feedback loop, stabilizing temperature of sensor placed in the flowing medium. The system assures balancing of heat amount supplied in impulses to the sensor and heat given up by the sensor in a continuous way to the flowing medium. Therefore the frequency of output impulses is proportional to the heat transfer coefficient from sensor to environment. According to the King's law, the frequency of those impulses is a function of medium flow velocity around the sensor. The special feature of presented solution is total integration of thermal sensor with the measurement signal conditioning system. Sensor and conditioning system are not the separate elements of the measurement circuit, but constitute a whole in form of thermal heat-balance mode flow-to-frequency converter. The advantage of such system is easiness of converting the frequency signal to the digital form, without using any additional analogue-to-digital converters. The frequency signal from the converter may be directly connected to the microprocessor input, which with use of standard built-in counters may convert the frequency into numerical value of high precision. Moreover, the frequency signal has higher resistance to interference than the voltage signal and may be transmitted to remote locations without the information loss.

Low-complexity Joint Sub-carrier Phase Noise Compensation for Digital Multi-carrier Systems

DEFF Research Database (Denmark)

Yankov, Metodi Plamenov; Barletta, Luca; Zibar, Darko

2017-01-01

Joint sub-carrier phase noise processing is proposed which recovers the SNR penalty related to decreased sub-carrier baudrate w.r.t. single carrier systems. The method enables digital sub-banding to be safely employed for nonlinear mitigation for modulation formats of up to 256-QAM.......Joint sub-carrier phase noise processing is proposed which recovers the SNR penalty related to decreased sub-carrier baudrate w.r.t. single carrier systems. The method enables digital sub-banding to be safely employed for nonlinear mitigation for modulation formats of up to 256-QAM....

High performance control strategy for single-phase three-level neutral-point-clamped traction four-quadrant converters

DEFF Research Database (Denmark)

Kejian, Song; Konstantinou, Georgios; Jing, Li

2017-01-01

Operational data from Chinese railways indicate a number of challenges for traction four-quadrant converter (4QC) control including low-order voltage and current harmonics and reference tracking. A control strategy for a single-phase three-level neutral-point-clamped 4QC employed in the electric...

High-performance digital triggering system for phase-controlled rectifiers

International Nuclear Information System (INIS)

Olsen, R.E.

1983-01-01

The larger power supplies used to power accelerator magnets are most commonly polyphase rectifiers using phase control. While this method is capable of handling impressive amounts of power, it suffers from one serious disadvantage, namely that of subharmonic ripple. Since the stability of the stored beam depends to a considerable extent on the regulation of the current in the bending magnets, subharmonic ripple, especially that of low frequency, can have a detrimental effect. At the NSLS, we have constructed a 12-pulse, phase control system using digital signal processing techniques that essentially eliminates subharmonic ripple

4-bit digital to analog converter using R-2R ladder and binary weighted resistors

Science.gov (United States)

Diosanto, J.; Batac, M. L.; Pereda, K. J.; Caldo, R.

2017-06-01

The use of a 4-bit digital-to-analog converter using two methods; Binary Weighted Resistors and R-2R Ladder is designed and presented in this paper. The main components that were used in constructing both circuits were different resistor values, operational amplifier (LM741) and single pole double throw switches. Both circuits were designed using MULTISIM software to be able to test the circuit for its ideal application and FRITZING software for the layout designing and fabrication to the printed circuit board. The implementation of both systems in an actual circuit benefits in determining and comparing the advantages and disadvantages of each. It was realized that the binary weighted circuit is more efficient DAC, having lower percentage error of 0.267% compared to R-2R ladder circuit which has a minimum of percentage error of 4.16%.

Development and Performance Analysis of a Photonics-Assisted RF Converter for 5G Applications

Science.gov (United States)

Borges, Ramon Maia; Muniz, André Luiz Marques; Sodré Junior, Arismar Cerqueira

2017-03-01

This article presents a simple, ultra-wideband and tunable radiofrequency (RF) converter for 5G cellular networks. The proposed optoelectronic device performs broadband photonics-assisted upconversion and downconversion using a single optical modulator. Experimental results demonstrate RF conversion from DC to millimeter waves, including 28 and 38 GHz that are potential frequency bands for 5G applications. Narrow linewidth and low phase noise characteristics are observed in all generated RF carriers. An experimental digital performance analysis using different modulation schemes illustrates the applicability of the proposed photonics-based device in reconfigurable optical wireless communications.

Systems and methods for self-synchronized digital sampling

Science.gov (United States)

Samson, Jr., John R. (Inventor)

2008-01-01

Systems and methods for self-synchronized data sampling are provided. In one embodiment, a system for capturing synchronous data samples is provided. The system includes an analog to digital converter adapted to capture signals from one or more sensors and convert the signals into a stream of digital data samples at a sampling frequency determined by a sampling control signal; and a synchronizer coupled to the analog to digital converter and adapted to receive a rotational frequency signal from a rotating machine, wherein the synchronizer is further adapted to generate the sampling control signal, and wherein the sampling control signal is based on the rotational frequency signal.

Six switches solution for single-phase AC/DC/AC converter with capability of second-order power mitigation in DC-link capacitor

DEFF Research Database (Denmark)

Liu, Xiong; Wang, Peng; Loh, Poh Chiang

2011-01-01

This paper proposes an approach for DC-link second-order harmonic power cancellation in single-phase AC/DC/AC converter with reduced number of switches. The proposed six-switch converter has two bridges with three switches in each of them, where the middle switch in each bridge is shared by the A...

Digital temperature meter

Energy Technology Data Exchange (ETDEWEB)

Glowacki, S

1982-01-01

Digital temperature meter for precise temperature measurements is presented. Its parts such as thermostat, voltage-frequency converter and digital frequency meter are described. Its technical parameters such as temperature range 50degC-700degC, measurement precision 1degC, measurement error +-1degC are given. (A.S.).

Linear programming phase unwrapping for dual-wavelength digital holography.

Science.gov (United States)

Wang, Zhaomin; Jiao, Jiannan; Qu, Weijuan; Yang, Fang; Li, Hongru; Tian, Ailing; Asundi, Anand

2017-01-20

A linear programming phase unwrapping method in dual-wavelength digital holography is proposed and verified experimentally. The proposed method uses the square of height difference as a convergence standard and theoretically gives the boundary condition in a searching process. A simulation was performed by unwrapping step structures at different levels of Gaussian noise. As a result, our method is capable of recovering the discontinuities accurately. It is robust and straightforward. In the experiment, a microelectromechanical systems sample and a cylindrical lens were measured separately. The testing results were in good agreement with true values. Moreover, the proposed method is applicable not only in digital holography but also in other dual-wavelength interferometric techniques.

An all digital phase locked loop for synchronization of a sinusoidal signal embedded in white Gaussian noise

Science.gov (United States)

Reddy, C. P.; Gupta, S. C.

1973-01-01

An all digital phase locked loop which tracks the phase of the incoming sinusoidal signal once per carrier cycle is proposed. The different elements and their functions and the phase lock operation are explained in detail. The nonlinear difference equations which govern the operation of the digital loop when the incoming signal is embedded in white Gaussian noise are derived, and a suitable model is specified. The performance of the digital loop is considered for the synchronization of a sinusoidal signal. For this, the noise term is suitably modelled which allows specification of the output probabilities for the two level quantizer in the loop at any given phase error. The loop filter considered increases the probability of proper phase correction. The phase error states in modulo two-pi forms a finite state Markov chain which enables the calculation of steady state probabilities, RMS phase error, transient response and mean time for cycle skipping.

Successfully converting mine maps to CAD

Energy Technology Data Exchange (ETDEWEB)

Munn, M.D. (Image Conversion Services, Inc., Salt Lake City, UT (USA))

1991-03-01

Procedures followed by computer service bureaus to convert paper drawing to digital files that can be used by CAD systems are described. The conversion involves laser scanning of original drawings to produce an 'inactive image' (a form suitable for many drawings that do not need to be changed). Using optical character recognition software the image is then vectorized or converted from raster format to geometric elements usable in a CAD system. The vectorized image can then be cleaned up corrected and changed at the CAD workstation. 4 figs.

Low photon count based digital holography for quadratic phase cryptography.

Science.gov (United States)

Muniraj, Inbarasan; Guo, Changliang; Malallah, Ra'ed; Ryle, James P; Healy, John J; Lee, Byung-Geun; Sheridan, John T

2017-07-15

Recently, the vulnerability of the linear canonical transform-based double random phase encryption system to attack has been demonstrated. To alleviate this, we present for the first time, to the best of our knowledge, a method for securing a two-dimensional scene using a quadratic phase encoding system operating in the photon-counted imaging (PCI) regime. Position-phase-shifting digital holography is applied to record the photon-limited encrypted complex samples. The reconstruction of the complex wavefront involves four sparse (undersampled) dataset intensity measurements (interferograms) at two different positions. Computer simulations validate that the photon-limited sparse-encrypted data has adequate information to authenticate the original data set. Finally, security analysis, employing iterative phase retrieval attacks, has been performed.

Design of Two Feeder Three Phase Four Wire Distribution System Utilizing Multi Converter UPQC with Fuzzy Logic Controller

Directory of Open Access Journals (Sweden)

Chandra Babu Paduchuri

2014-01-01

Full Text Available This paper proposes the instantaneous p-q theory based fuzzy logic controller (FLC for multi converter unified power quality conditioner (MC-UPQC to mitigate power quality issues in two feeders three-phase four-wire distribution systems. The proposed system is extended system of the existing one feeder three-phase four-wire distribution system, which is operated with UPQC. This system is employed with three voltage source converters, which are connected commonly to two feeder distribution systems. The performance of this proposed system used to compensate voltage sag, neutral current mitigation and compensation of voltage and current harmonics under linear and nonlinear load conditions. The neutral current flowing in series transformers is zero in the implementation of the proposed system. The simulation performance analysis is carried out using MATLAB.

Non-synchronous control of self-oscillating resonant converters

Science.gov (United States)

Glaser, John Stanley; Zane, Regan Andrew

2002-01-01

A self-oscillating switching power converter has a controllable reactance including an active device connected to a reactive element, wherein the effective reactance of the reactance and the active device is controlled such that the control waveform for the active device is binary digital and is not synchronized with the switching converter output frequency. The active device is turned completely on and off at a frequency that is substantially greater than the maximum frequency imposed on the output terminals of the active device. The effect is to vary the average resistance across the active device output terminals, and thus the effective output reactance, thereby providing converter output control, while maintaining the response speed of the converter.

Development of a Novel Bidirectional DC/DC Converter Topology with High Voltage Conversion Ratio for Electric Vehicles and DC-Microgrids

Directory of Open Access Journals (Sweden)

Ching-Ming Lai

2016-05-01

Full Text Available The main objective of this paper was to study a bidirectional direct current to direct current converter (BDC topology with a high voltage conversion ratio for electric vehicle (EV batteries connected to a dc-microgrid system. In this study, an unregulated level converter (ULC cascaded with a two-phase interleaved buck-boost charge-pump converter (IBCPC is introduced to achieve a high conversion ratio with a simpler control circuit. In discharge state, the topology acts as a two-stage voltage-doubler boost converter to achieve high step-up conversion ratio (48 V to 385 V. In charge state, the converter acts as two cascaded voltage-divider buck converters to achieve high voltage step-down conversion ratio (385 V to 48 V. The features, operation principles, steady-state analysis, simulation and experimental results are made to verify the performance of the studied novel BDC. Finally, a 500 W rating prototype system is constructed for verifying the validity of the operation principle. Experimental results show that highest efficiencies of 96% and 95% can be achieved, respectively, in charge and discharge states.

A resonant dc-dc power converter assembly

OpenAIRE

Madsen, Mickey Pierre

2015-01-01

The present invention relates to a resonant DC-DC power converter assembly comprising a first resonant DC-DC power converter and a second resonant DC-DC power converter having identical circuit topologies. A first inductor of the first resonant DC-DC power converter and a second inductor of the second resonant DC-DC power converter are configured for magnetically coupling the first and second resonant DC-DC power converters to each other to forcing substantially 180 degrees phase shift, or fo...

Switching power converters medium and high power

CERN Document Server

Neacsu, Dorin O

2013-01-01

An examination of all of the multidisciplinary aspects of medium- and high-power converter systems, including basic power electronics, digital control and hardware, sensors, analog preprocessing of signals, protection devices and fault management, and pulse-width-modulation (PWM) algorithms, Switching Power Converters: Medium and High Power, Second Edition discusses the actual use of industrial technology and its related subassemblies and components, covering facets of implementation otherwise overlooked by theoretical textbooks. The updated Second Edition contains many new figures, as well as

CMOS sigma-delta converters practical design guide

CERN Document Server

De la Rosa, Jose M

2013-01-01

A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

Multiple low frequency dual reference PWM control of a grid connected photovoltaic three phase NPC inverter with DC/DC boost converter

Directory of Open Access Journals (Sweden)

Mechouma Rabiaa

2014-01-01

Full Text Available In recent years, power demand of industrial applications has increased significantly reaching some megawatts. The use of multilevel converters for applications of medium and high powers is proposed as a solution to drawback semiconductor technology. A multilevel converter not only achieves high power ratings, but also enables the use of renewable energy sources. Renewable energy sources such as photovoltaic can be easily interfaced to a multilevel converter system for a high power application. This paper presents the simulation study in Matlab/Simulink of a grid connected photovoltaic three phase Neutral Point Clamped (NPC inverter with DC/DC boost converter for constant and variable solar radiation.

Prospera Digital Phase II: Financial inclusion for low-income women ...

International Development Research Centre (IDRC) Digital Library (Canada)

Prospera Digital Phase II: Financial inclusion for low-income women in Mexico ... a research network in Latin America, to identify barriers and opportunities to scale up ... Call for new OWSD Fellowships for Early Career Women Scientists now open ... conference of McGill's Institute for the Study of International Development.

Design and Implementation of a linear-phase equalizer in digital audio signal processing

NARCIS (Netherlands)

Slump, Cornelis H.; van Asma, C.G.M.; Barels, J.K.P.; Barels, J.K.P.; Brunink, W.J.A; Drenth, F.B.; Pol, J.V.; Schouten, D.S.; Samsom, M.M.; Samsom, M.M.; Herrmann, O.E.

1992-01-01

This contribution presents the four phases of a project aiming at the realization in VLSI of a digital audio equalizer with a linear phase characteristic. The first step includes the identification of the system requirements, based on experience and (psycho-acoustical) literature. Secondly, the

Development of a Compact Matrix Converter

Directory of Open Access Journals (Sweden)

J. Bauer

2009-01-01

Full Text Available This paper deals with the development of a matrix converter. Matrix converters belong to the category of direct frequency converters. A converter does not contain DC-link and the output voltage is provided by direct switching of voltage from the input phases. This is enabled by 9 bidirectional switches, which are provided by anti-serial connection of 18 IGBT transistors. The absence of a DC-link is great advantage of the matrix converter, but it also increases the requirements on the converter control. For this reason a new prototype of a matrix converter is being developed with sophisticated modern components (FPGA, Power PC equipped in the control part of the converter. The converter will be used for testing new control algorithms and commutation methods. 

Digital Holographic Microscopy: Quantitative Phase Imaging and Applications in Live Cell Analysis

Science.gov (United States)

Kemper, Björn; Langehanenberg, Patrik; Kosmeier, Sebastian; Schlichthaber, Frank; Remmersmann, Christian; von Bally, Gert; Rommel, Christina; Dierker, Christian; Schnekenburger, Jürgen

The analysis of complex processes in living cells creates a high demand for fast and label-free methods for online monitoring. Widely used fluorescence methods require specific labeling and are often restricted to chemically fixated samples. Thus, methods that offer label-free and minimally invasive detection of live cell processes and cell state alterations are of particular interest. In combination with light microscopy, digital holography provides label-free, multi-focus quantitative phase imaging of living cells. In overview, several methods for digital holographic microscopy (DHM) are presented. First, different experimental setups for the recording of digital holograms and the modular integration of DHM into common microscopes are described. Then the numerical processing of digitally captured holograms is explained. This includes the description of spatial and temporal phase shifting techniques, spatial filtering based reconstruction, holographic autofocusing, and the evaluation of self-interference holograms. Furthermore, the usage of partial coherent light and multi-wavelength approaches is discussed. Finally, potentials of digital holographic microscopy for quantitative cell imaging are illustrated by results from selected applications. It is shown that DHM can be used for automated tracking of migrating cells and cell thickness monitoring as well as for refractive index determination of cells and particles. Moreover, the use of DHM for label-free analysis in fluidics and micro-injection monitoring is demonstrated. The results show that DHM is a highly relevant method that allows novel insights in dynamic cell biology, with applications in cancer research and for drugs and toxicity testing.

A phase-equalized digital multirate filter for 50 Hz signal processing

Energy Technology Data Exchange (ETDEWEB)

Vainio, O. [Tampere University of Technology, Signal Processing Laboratory, Tampere (Finland)

1997-12-31

A new multistage digital filter is proposed for 50 Hz line frequency signal processing in zero-crossing detectors and synchronous power systems. The purpose of the filter is to extract the fundamental sinusoidal signal from noise and impulsive disturbances so that the output is accurately in phase with the primary input signal. This is accomplished with a cascade of a median filter, a linear-phase FIR filter, and a phase corrector. A 10 kHz output timing resolution is achieved by up-sampling with a customized interpolation filter. (orig.) 15 refs.

Measuring Down: Evaluating Digital Storytelling as a Process for Narrative Health Promotion.

Science.gov (United States)

Gubrium, Aline C; Fiddian-Green, Alice; Lowe, Sarah; DiFulvio, Gloria; Del Toro-Mejías, Lizbeth

2016-05-15

Digital storytelling (DST) engages participants in a group-based process to create and share narrative accounts of life events. We present key evaluation findings of a 2-year, mixed-methods study that focused on effects of participating in the DST process on young Puerto Rican Latina's self-esteem, social support, empowerment, and sexual attitudes and behaviors. Quantitative results did not show significant changes in the expected outcomes. However, in our qualitative findings we identified several ways in which the DST made positive, health-bearing effects. We argue for the importance of "measuring down" to reflect the locally grounded, felt experiences of participants who engage in the process, as current quantitative scales do not "measure up" to accurately capture these effects. We end by suggesting the need to develop mixed-methods, culturally relevant, and sensitive evaluation tools that prioritize process effects as they inform intervention and health promotion. © The Author(s) 2016.

Efficient Phase Unwrapping Architecture for Digital Holographic Microscopy

Directory of Open Access Journals (Sweden)

Wen-Jyi Hwang

2011-09-01

Full Text Available This paper presents a novel phase unwrapping architecture for accelerating the computational speed of digital holographic microscopy (DHM. A fast Fourier transform (FFT based phase unwrapping algorithm providing a minimum squared error solution is adopted for hardware implementation because of its simplicity and robustness to noise. The proposed architecture is realized in a pipeline fashion to maximize through put of thecomputation. Moreover, the number of hardware multipliers and dividers are minimized to reduce the hardware costs. The proposed architecture is used as a custom user logic in a system on programmable chip (SOPC for physical performance measurement. Experimental results reveal that the proposed architecture is effective for expediting the computational speed while consuming low hardware resources for designing an embedded DHM system.

Multi-cell DC-DC converter with high step-down voltage ratio

NARCIS (Netherlands)

Tibola, G.; Duarte, J.L.; Blinov, A.

2015-01-01

The use of high voltage allows a power processing system to operate with low currents, improving efficiency. Nevertheless, final applications usually require low voltage inlet, which can be provided using modular multilevel converters submodules, for instance. However, every submodule's gate-unit

Beam Phase Detection for Proton Therapy Accelerators

CERN Document Server

Aminov, Bachtior; Getta, Markus; Kolesov, Sergej; Pupeter, Nico; Stephani, Thomas; Timmer, J

2005-01-01

The industrial application of proton cyclotrons for medical applications has become one of the important contributions of accelerator physics during the last years. This paper describes an advanced vector demodulating technique used for non-destructive measurements of beam intensity and beam phase over 360°. A computer controlled I/Q-based phase detector with a very large dynamic range of 70 dB permits the monitoring of beam intensity, phase and eventually energy for wide range of beam currents down to -130 dBm. In order to avoid interference from the fundamental cyclotron frequency the phase detection is performed at the second harmonic frequency. A digital low pass filter with adjustable bandwidth and steepness is implemented to improve accuracy. With a sensitivity of the capacitive pickup in the beam line of 30 nV per nA of proton beam current at 250 MeV, accurate phase and intensity measurements can be performed with beam currents down to 3.3 nA.

Matrix converter applied to energy saving for street lighting systems

OpenAIRE

Román Lumbreras, Manuel; Velasco Quesada, Guillermo; Conesa Roca, Alfons

2010-01-01

This work presents a three-phase AC-AC converter, with independent phase control, based on matrix-converter structure. This converter is applied to electrical energy saving on the public lighting systems by means of regulation and control of the voltage applied to the lamps. The developed converter represents a technological improvement with respect to the traditional systems based on an autotransformer: it reduces system cost and volume, and increases lamps lifetime.

Interleaved Boost-Half-Bridge Dual–Input DC-DC Converter with a PWM plus Phase-Shift Control for Fuel Cell Applications

DEFF Research Database (Denmark)

Zhang, Zhe; Andersen, Michael A. E.

2013-01-01

This paper presents an isolated dual-input DC-DC converter with a PWM plus phase-shift control for fuel cell hybrid energy systems. The power switches are controlled by phase shifted PWM signals with a variable duty cycle, and thus the two input voltages as well as the output voltage can...

Thumbs down: a molecular-morphogenetic approach to avian digit homology.

Science.gov (United States)

Capek, Daniel; Metscher, Brian D; Müller, Gerd B

2014-01-01

Avian forelimb digit homology remains one of the standard themes in comparative biology and EvoDevo research. In order to resolve the apparent contradictions between embryological and paleontological evidence a variety of hypotheses have been presented in recent years. The proposals range from excluding birds from the dinosaur clade, to assignments of homology by different criteria, or even assuming a hexadactyl tetrapod limb ground state. At present two approaches prevail: the frame shift hypothesis and the pyramid reduction hypothesis. While the former postulates a homeotic shift of digit identities, the latter argues for a gradual bilateral reduction of phalanges and digits. Here we present a new model that integrates elements from both hypotheses with the existing experimental and fossil evidence. We start from the main feature common to both earlier concepts, the initiating ontogenetic event: reduction and loss of the anterior-most digit. It is proposed that a concerted mechanism of molecular regulation and developmental mechanics is capable of shifting the boundaries of hoxD expression in embryonic forelimb buds as well as changing the digit phenotypes. Based on a distinction between positional (topological) and compositional (phenotypic) homology criteria, we argue that the identity of the avian digits is II, III, IV, despite a partially altered phenotype. Finally, we introduce an alternative digit reduction scheme that reconciles the current fossil evidence with the presented molecular-morphogenetic model. Our approach identifies specific experiments that allow to test whether gene expression can be shifted and digit phenotypes can be altered by induced digit loss or digit gain. © 2013 Wiley Periodicals, Inc.

Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes

KAUST Repository

Omran, Hesham

2015-11-01

Energy efficiency is a key requirement for wireless sensor nodes, biomedical implants, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement, or even better, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus, they are attractive from an energy efficiency perspective. In addition, they can be employed in a wide range of sensing applications. However, the sensor readout circuit–i.e., the capacitance-to-digital converter (CDC)–can be the dominant source of energy consumption in the system. Thus, the development of energy-efficient CDCs is crucial to minimizing the energy consumption of capacitive sensor nodes. In the first part of this dissertation, we propose several energy-efficient CDC architectures for low-energy sensor nodes. First, we propose a digitally-controlled coarsefine multislope CDC that employs both current and frequency scaling to achieve significant improvement in energy efficiency. Second, we analyze the limitations of successive approximation (SAR) CDC, and we address these limitations by proposing a robust parasitic-insensitive opamp-based SAR CDC. Third, we propose an inverter-based SAR CDC that achieves an energy efficiency figure-of-merit (FoM) of 31fJ/Step, which is the best energy efficiency FoM reported to date. Fourth, we propose a differential SAR CDC with quasi-dynamic operation to maintain excellent energy efficiency for a scalable sample rate. In the second part of this dissertation, we study the matching properties of small integrated capacitors, which are an integral component of energy-efficient CDCs. Despite conventional wisdom, we experimentally illustrate that the mismatch of small capacitors can be directly measured, and we report mismatch measurements for subfemtofarad integrated capacitors. We also correct the common misconception that lateral capacitors match better than vertical capacitors

A new on-chip all-digital three-phase full-bridge dc/ac power inverter with feedforward and frequency control techniques.

Science.gov (United States)

Chen, Jiann-Jong; Kung, Che-Min

2010-09-01

The communication speed between components is far from satisfactory. To achieve high speed, simple control system configuration, and low cost, a new on-chip all-digital three-phase dc/ac power inverter using feedforward and frequency control techniques is proposed. The controller of the proposed power inverter, called the shift register, consists of six-stage D-latch flip-flops with a goal of achieving low-power consumption and area efficiency. Variable frequency is achieved by controlling the clocks of the shift register. One advantage regarding the data signal (D) and the common clock (CK) is that, regardless of the phase difference between the two, all of the D-latch flip-flops are capable of delaying data by one CK period. To ensure stability, the frequency of CK must be six times higher than that of D. The operation frequency of the proposed power inverter ranges from 10 Hz to 2 MHz, and the maximum output loading current is 0.8 A. The prototype of the proposed circuit has been fabricated with TSMC 0.35 μm 2P4M CMOS processes. The total chip area is 2.333 x 1.698 mm2. The three-phase dc/ac power inverter is applicable in uninterrupted power supplies, cold cathode fluorescent lamps, and motors, because of its ability to convert the dc supply voltage into the three-phase ac power sources.

High-Repeatable Data Acquisition Systems for Pulsed Power Converters in Particle Accelerator Structures

CERN Document Server

AUTHOR|(CDS)2087245; Martino, Michele; Zinno, Raffaele

In this Ph.D. thesis, the issues related to the metrological characterization of high-performance pulsed power converters are addressed. Initially, a background and a state of the art on the measurement systems needed to correctly operate a high-performance power converter are presented. As a matter of fact, power converters usually exploits digital control loops to enhance their performance. In this context the final performance of a power converter has to be validated by a reference instrument with higher metrological characteristics. In addition, an on-line measurement systemis also needed to digitize the quantity to be controlled with high accuracy. Then, in industrial applications of power converters metrology, specifications are given in terms of Worst-Case Uncertainty (WCU). Therefore, an analytical model for predicting the Worst-Case Uncertainty (WCU) of a measurement system is discussed and detailed for an instrument affected by Gaussian noise. Furthermore, the study and the design of a Reference Acq...

A low cost rapid prototype platform for a three phase PFC rectifier application

DEFF Research Database (Denmark)

Haase, Frerk; Kouchaki, Alireza; Nymand, Morten

2015-01-01

In this paper the design and development of a low cost rapid prototype platform for a Three Phase PFC rectifier application is presented. The active rectifier consists of a SiC-MOSFET based PWM converter and a low cost rapid prototype platform for simulating and implementing the digital control...

Voltage-Sharing Converter to Supply Single-Phase Asymmetrical Four-Level Diode-Clamped Inverter With High Power Factor Loads

DEFF Research Database (Denmark)

Boora, Arash A.; Nami, Alireza; Zare, Firuz

2010-01-01

The output voltage quality of some of the single-phase multilevel inverters can be improved when their dc-link voltages are regulated asymmetrically. Symmetrical and asymmetrical multilevel diode-clamped inverters have the problem of dc-link capacitor voltage balancing, especially when power factor...... that the proposed combination of introduced multioutput dc–dc converter and single-phase ADCI is a good candidate for power conversion in residential photovoltaic (PV) utilization....

A New Topology for Interline Dynamic Voltage Restorer Based on Direct Three-Phase Converter

Directory of Open Access Journals (Sweden)

E. Babaei

2016-03-01

Full Text Available In this paper, a new topology for Interline Dynamic Voltage Restorer (IDVR is proposed. This topology contains two direct three-phase converters which have been connected together by a common fictitious dc-link. According to the kind of the disturbances, both of the converters can be employed as a rectifier or inverter. The converters receive the required compensation energy from the gird through the direct link which is provided by the dual-proposed switches. Due to the lack of the huge storage elements, the practical prototype of the proposed topology is more economical in comparison with the traditional structure. Moreover, compensating for long time duration is possible due to the unlimited eternal energy which is provided from the grids. The low volume, cost and weight are the additional features of the proposed topology in comparison with traditional types. This topology is capable to compensate both of the balanced and unbalanced disturbances. Furthermore, restoring the deep sags and power outages will be possible with the support from the other grid. Unlike the conventional topologies, the capability of compensation is independent from the power flow and the power factor of each grid. The performance of the proposed IDVR topology is validated by computer simulation with PSCAD/EMTDC software.

Crystal Phase Quantum Well Emission with Digital Control

DEFF Research Database (Denmark)

Assali, S.; Laehnemann, J.; Vu, Thi Thu Trang

2017-01-01

One of the major challenges in the growth of quantum well and quantum dot heterostructures is the realization of atomically sharp interfaces. Nanowires provide a new opportunity to engineer the band structure as they facilitate the controlled switching of the crystal structure between the zinc......-blende (ZB) and wurtzite (WZ) phases. Such a crystal phase switching results in the formation of crystal phase quantum wells (CPQWs) and quantum dots (CPQDs). For GaP CPQWs, the inherent electric fields due to the discontinuity of the spontaneous polarization at the WZ/ZB junctions lead to the confinement...... of both types of charge carriers at the opposite interfaces of the WZ/ZB/WZ structure. This confinement leads to a novel type of transition across a ZB flat plate barrier. Here, we show digital tuning of the visible emission of WZ/ZB/WZ CPQWs in a GaP nanowire by changing the thickness of the ZB barrier...

High resolution distributed time-to-digital converter (TDC) in a White Rabbit network

International Nuclear Information System (INIS)

Pan, Weibin; Gong, Guanghua; Du, Qiang; Li, Hongming; Li, Jianmin

2014-01-01

The Large High Altitude Air Shower Observatory (LHAASO) project consists of a complex detector array with over 6000 detector nodes spreading over 1.2 km 2 areas. The arrival times of shower particles are captured by time-to-digital converters (TDCs) in the detectors' frontend electronics, the arrival direction of the high energy cosmic ray are then to be reconstructed from the space-time information of all detector nodes. To guarantee the angular resolution of 0.5°, a time synchronization of 500 ps (RMS) accuracy and 100 ps precision must be achieved among all TDC nodes. A technology enhancing Gigabit Ethernet, called the White Rabbit (WR), has shown the capability of delivering sub-nanosecond accuracy and picoseconds precision of synchronization over the standard data packet transfer. In this paper we demonstrate a distributed TDC prototype system combining the FPGA based TDC and the WR technology. With the time synchronization and data transfer services from a compact WR node, separate FPGA-TDC nodes can be combined to provide uniform time measurement information for correlated events. The design detail and test performance will be described in the paper

High resolution distributed time-to-digital converter (TDC) in a White Rabbit network

Energy Technology Data Exchange (ETDEWEB)

Pan, Weibin, E-mail: pwb.thu@gmail.com; Gong, Guanghua; Du, Qiang; Li, Hongming; Li, Jianmin

2014-02-21

The Large High Altitude Air Shower Observatory (LHAASO) project consists of a complex detector array with over 6000 detector nodes spreading over 1.2 km{sup 2} areas. The arrival times of shower particles are captured by time-to-digital converters (TDCs) in the detectors' frontend electronics, the arrival direction of the high energy cosmic ray are then to be reconstructed from the space-time information of all detector nodes. To guarantee the angular resolution of 0.5°, a time synchronization of 500 ps (RMS) accuracy and 100 ps precision must be achieved among all TDC nodes. A technology enhancing Gigabit Ethernet, called the White Rabbit (WR), has shown the capability of delivering sub-nanosecond accuracy and picoseconds precision of synchronization over the standard data packet transfer. In this paper we demonstrate a distributed TDC prototype system combining the FPGA based TDC and the WR technology. With the time synchronization and data transfer services from a compact WR node, separate FPGA-TDC nodes can be combined to provide uniform time measurement information for correlated events. The design detail and test performance will be described in the paper.

Monolitic integrated circuit for the strobed charge-to-time converter

International Nuclear Information System (INIS)

Bel'skij, V.I.; Bushnin, Yu.B.; Zimin, S.A.; Punzhin, Yu.N.; Sen'ko, V.A.; Soldatov, M.M.; Tokarchuk, V.P.

1985-01-01

The developed and comercially produced semiconducting circuit - gating charge-to-time converter KR1101PD1 is described. The considered integrated circuit is a short pulse charge-to-time converter with integration of input current. The circuit is designed for construction of time-to-pulse analog-to-digital converters utilized in multichannel detection systems when studying complex topology processes. Input resistance of the circuit is 0.1 Ω permissible input current is 50 mA, maximum measured charge is 300-1000 pC

Three-dimensional motion-picture imaging of dynamic object by parallel-phase-shifting digital holographic microscopy using an inverted magnification optical system

Science.gov (United States)

Fukuda, Takahito; Shinomura, Masato; Xia, Peng; Awatsuji, Yasuhiro; Nishio, Kenzo; Matoba, Osamu

2017-04-01

We constructed a parallel-phase-shifting digital holographic microscopy (PPSDHM) system using an inverted magnification optical system, and succeeded in three-dimensional (3D) motion-picture imaging for 3D displacement of a microscopic object. In the PPSDHM system, the inverted and afocal magnification optical system consisted of a microscope objective (16.56 mm focal length and 0.25 numerical aperture) and a convex lens (300 mm focal length and 82 mm aperture diameter). A polarization-imaging camera was used to record multiple phase-shifted holograms with a single-shot exposure. We recorded an alum crystal, sinking down in aqueous solution of alum, by the constructed PPSDHM system at 60 frames/s for about 20 s and reconstructed high-quality 3D motion-picture image of the crystal. Then, we calculated amounts of displacement of the crystal from the amounts in the focus plane and the magnifications of the magnification optical system, and obtained the 3D trajectory of the crystal by that amounts.

A Novel Neural Network Vector Control for Single-Phase Grid-Connected Converters with L, LC and LCL Filters

Directory of Open Access Journals (Sweden)

Xingang Fu

2016-04-01

Full Text Available This paper investigates a novel recurrent neural network (NN-based vector control approach for single-phase grid-connected converters (GCCs with L (inductor, LC (inductor-capacitor and LCL (inductor-capacitor-inductor filters and provides their comparison study with the conventional standard vector control method. A single neural network controller replaces two current-loop PI controllers, and the NN training approximates the optimal control for the single-phase GCC system. The Levenberg–Marquardt (LM algorithm was used to train the NN controller based on the complete system equations without any decoupling policies. The proposed NN approach can solve the decoupling problem associated with the conventional vector control methods for L, LC and LCL-filter-based single-phase GCCs. Both simulation study and hardware experiments demonstrate that the neural network vector controller shows much more improved performance than that of conventional vector controllers, including faster response speed and lower overshoot. Especially, NN vector control could achieve very good performance using low switch frequency. More importantly, the neural network vector controller is a damping free controller, which is generally required by a conventional vector controller for an LCL-filter-based single-phase grid-connected converter and, therefore, can overcome the inefficiency problem caused by damping policies.

A Unified Impedance Model of Voltage-Source Converters with Phase-Locked Loop Effect

DEFF Research Database (Denmark)

Wang, Xiongfei; Harnefors, Lennart; Blaabjerg, Frede

2016-01-01

This paper proposes a unified impedance model for analyzing the effect of Phase-Locked Loop (PLL) on the stability of grid-connected voltage-source converters. In the approach, the dq-frame impedance model is transformed into the stationary αβ-frame by means of complex transfer functions...... and complex space vectors, which not only predicts the stability impact of the PLL, but reveals also its frequency coupling effect in the phase domain. Thus, the impedance models previously developed in the different domains can be unified. Moreover, the impedance shaping effects of PLL are structurally...... characterized for the current control in the rotating dq-frame and the stationary αβ-frame. Case studies based on the unified impedance model are presented, which are then verified in the time-domain simulations and experiments. The results closely correlate with the impedance-based analysis....

Large Signal Model of a Four-quadrant AC to DC Converter for Accelerator Magnets

CERN Document Server

De la Calle, R; Rinaldi, L; Völker, F V

2001-01-01

This paper presents the large signal model of a four-quadrant AC to DC converter, which is expected to be used in the area of particle accelerators. The system’s first stage is composed of a three-phase boost PWM (Pulse Width Modulated) rectifier with DSP (Digital Signal Processing) based power factor correction (PFC) and output voltage regulation. The second stage is a full-bridge PWM inverter that allows fast four-quadrant operation. The structure is fully reversible, and an additional resistance (brake chopper) is not needed to dissipate the energy when the beam deflection magnet acts as generator.

Phorbol-ester-induced down-regulation of protein kinase C in mouse pancreatic islets. Potentiation of phase 1 and inhibition of phase 2 of glucose-induced insulin secretion

DEFF Research Database (Denmark)

Thams, P; Capito, K; Hedeskov, C J

1990-01-01

and potentiated phase 1 of glucose-induced secretion. Furthermore, perifusion of islets in the presence of staurosporine (1 microM), an inhibitor of protein kinase C, potentiated phase 1 and inhibited phase 2 of glucose-induced secretion. In addition, down-regulation of protein kinase C potentiated phase 1...

Local digital control of power electronic converters in a dc microgrid based on a-priori derivation of switching surfaces

Science.gov (United States)

Banerjee, Bibaswan

In power electronic basedmicrogrids, the computational requirements needed to implement an optimized online control strategy can be prohibitive. The work presented in this dissertation proposes a generalized method of derivation of geometric manifolds in a dc microgrid that is based on the a-priori computation of the optimal reactions and trajectories for classes of events in a dc microgrid. The proposed states are the stored energies in all the energy storage elements of the dc microgrid and power flowing into them. It is anticipated that calculating a large enough set of dissimilar transient scenarios will also span many scenarios not specifically used to develop the surface. These geometric manifolds will then be used as reference surfaces in any type of controller, such as a sliding mode hysteretic controller. The presence of switched power converters in microgrids involve different control actions for different system events. The control of the switch states of the converters is essential for steady state and transient operations. A digital memory look-up based controller that uses a hysteretic sliding mode control strategy is an effective technique to generate the proper switch states for the converters. An example dcmicrogrid with three dc-dc boost converters and resistive loads is considered for this work. The geometric manifolds are successfully generated for transient events, such as step changes in the loads and the sources. The surfaces corresponding to a specific case of step change in the loads are then used as reference surfaces in an EEPROM for experimentally validating the control strategy. The required switch states corresponding to this specific transient scenario are programmed in the EEPROM as a memory table. This controls the switching of the dc-dc boost converters and drives the system states to the reference manifold. In this work, it is shown that this strategy effectively controls the system for a transient condition such as step changes

What progress has Germany made half way down the nuclear phase-out path?

International Nuclear Information System (INIS)

Kraev, Kamen

2017-01-01

The past year saw a number of anticipated developments related to Germany's policy of phasing out nuclear power by 2022. Ralf Gueldner, president of the German Atomic Forum (DAtF), spoke to NucNet about what has been accomplished and what remains to be done in Germany half way down the phaseout path.

What progress has Germany made half way down the nuclear phase-out path?

Energy Technology Data Exchange (ETDEWEB)

Kraev, Kamen [NucNet, Brussels (Belgium). The Independent Global Nuclear News Agency

2017-08-15

The past year saw a number of anticipated developments related to Germany's policy of phasing out nuclear power by 2022. Ralf Gueldner, president of the German Atomic Forum (DAtF), spoke to NucNet about what has been accomplished and what remains to be done in Germany half way down the phaseout path.

Considerations of digital phase modulation for narrowband satellite mobile communication

Science.gov (United States)

Grythe, Knut

1990-01-01

The Inmarsat-M system for mobile satellite communication is specified as a frequency division multiple access (FDMA) system, applying Offset Quadrature Phase Shift Keying (QPSK) for transmitting 8 kbit/sec in 10 kHz user channel bandwidth. We consider Digital Phase Modulation (DPM) as an alternative modulation format for INMARSAT-M. DPM is similar to Continuous Phase Modulation (CPM) except that DPM has a finite memory in the premodular filter with a continuous varying modulation index. It is shown that DPM with 64 states in the VA obtains a lower bit error rate (BER). Results for a 5 kHz system, with the same 8 kbit/sec transmitted bitstream, is also presented.

Analysis of first and second order binary quantized digital phase-locked loops for ideal and white Gaussian noise inputs

Science.gov (United States)

Blasche, P. R.

1980-01-01

Specific configurations of first and second order all digital phase locked loops are analyzed for both ideal and additive white gaussian noise inputs. In addition, a design for a hardware digital phase locked loop capable of either first or second order operation is presented along with appropriate experimental data obtained from testing of the hardware loop. All parameters chosen for the analysis and the design of the digital phase locked loop are consistent with an application to an Omega navigation receiver although neither the analysis nor the design are limited to this application.

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

NARCIS (Netherlands)

Veldhoven, van R.H.M.; Roermund, van A.H.M.

2011-01-01

Sigma Delta converters are a very popular choice for the A/D converter in multi-standard, mobile and cellular receivers. Key A/D converter specifications are high dynamic range, robustness, scalability, low-power and low EMI. Robust Sigma Delta Converters presents a requirement derivation of a Sigma

A digital correlator upgrade for the Arcminute MicroKelvin Imager

Science.gov (United States)

Hickish, Jack; Razavi-Ghods, Nima; Perrott, Yvette C.; Titterington, David J.; Carey, Steve H.; Scott, Paul F.; Grainge, Keith J. B.; Scaife, Anna M. M.; Alexander, Paul; Saunders, Richard D. E.; Crofts, Mike; Javid, Kamran; Rumsey, Clare; Jin, Terry Z.; Ely, John A.; Shaw, Clive; Northrop, Ian G.; Pooley, Guy; D'Alessandro, Robert; Doherty, Peter; Willatt, Greg P.

2018-04-01

The Arcminute Microkelvin Imager (AMI) telescopes located at the Mullard Radio Astronomy Observatory near Cambridge have been significantly enhanced by the implementation of a new digital correlator with 1.2 MHz spectral resolution. This system has replaced a 750-MHz resolution analogue lag-based correlator, and was designed to mitigate the effects of radio frequency interference, particularly that from geostationary satellites which are visible from the AMI site when observing at low declinations. The upgraded instrument consists of 18 ROACH2 Field Programmable Gate Array platforms used to implement a pair of real-time FX correlators - one for each of AMI's two arrays. The new system separates the down-converted RF baseband signal from each AMI receiver into two sub-bands, each of which are filtered to a width of 2.3 GHz and digitized at 5-Gsps with 8 bits of precision. These digital data streams are filtered into 2048 frequency channels and cross-correlated using FPGA hardware, with a commercial 10 Gb Ethernet switch providing high-speed data interconnect. Images formed using data from the new digital correlator show over an order of magnitude improvement in dynamic range over the previous system. The ability to observe at low declinations has also been significantly improved.

Microscopy imaging and quantitative phase contrast mapping in turbid microfluidic channels by digital holography.

Science.gov (United States)

Paturzo, Melania; Finizio, Andrea; Memmolo, Pasquale; Puglisi, Roberto; Balduzzi, Donatella; Galli, Andrea; Ferraro, Pietro

2012-09-07

We show that sharp imaging and quantitative phase-contrast microcopy is possible in microfluidics in flowing turbid media by digital holography. In fact, in flowing liquids with suspended colloidal particles, clear vision is hindered and cannot be recovered by any other microscopic imaging technique. On the contrary, using digital holography, clear imaging is possible thanks to the Doppler frequency shift experienced by the photons scattered by the flowing colloidal particles, which do not contribute to the interference process, i.e. the recorded hologram. The method is illustrated and imaging results are demonstrated for pure phase objects, i.e. biological cells in microfluidic channels.

Simulation and Implementation a Non-Isolated Buck Converter at ZCS Condition

Directory of Open Access Journals (Sweden)

Nahid Hematian

2013-10-01

Full Text Available A new soft-switching resonant inverting-buck converter with high efficiency is presented. The proposed converter steps down and inverts the input voltage. The zero-current-switching (ZCS technique is employed to reduce switching losses and Electromagnetic Interferences (EMI. An LLC resonant network is utilized to provide soft-switching conditions for all semiconductor devices. Experimental results verify the integrity of the proposed converter operation and the presented theoretical analysis.

Design and Testing of an Active Heat Rejection Radiator with Digital Turn-Down Capability

Science.gov (United States)

Sunada, Eric; Birur, Gajanana C.; Ganapathi, Gani B.; Miller, Jennifer; Berisford, Daniel; Stephan, Ryan

2010-01-01

NASA's proposed lunar lander, Altair, will be exposed to vastly different external environment temperatures. The challenges to the active thermal control system (ATCS) are compounded by unfavorable transients in the internal waste heat dissipation profile: the lowest heat load occurs in the coldest environment while peak loads coincide with the warmest environment. The current baseline for this fluid is a 50/50 inhibited propylene glycol/water mixture with a freeze temperature around -35 C. While the overall size of the radiator's heat rejection area is dictated by the worst case hot scenario, a turn-down feature is necessary to tolerate the worst case cold scenario. A radiator with digital turn-down capability is being designed as a robust means to maintain cabin environment and equipment temperatures while minimizing mass and power consumption. It utilizes active valving to isolate and render ineffective any number of parallel flow tubes which span across the ATCS radiator. Several options were assessed in a trade-study to accommodate flow tube isolation and how to deal with the stagnant fluid that would otherwise remain in the tube. Bread-board environmental tests were conducted for options to drain the fluid from a turned-down leg as well an option to allow a leg to freeze/thaw. Each drain option involved a positive displacement gear pump with different methods of providing a pressure head to feed it. Test results showed that a start-up heater used to generate vapor at the tube inlet held the most promise for tube evacuation. Based on these test results and conclusions drawn from the trade-study, a full-scale radiator design is being worked for the Altair mission profile.

The digital aqueous humor outflow meter: an alternative tool for screening of the human eye outflow facility

Directory of Open Access Journals (Sweden)

Vassilios P Kozobolis

2010-08-01

Full Text Available Vassilios P Kozobolis, Eleftherios I Paschalis, Nikitas C Foudoulakis, Stavrenia C Koukoula, Georgios LabirisDepartment of Ophthalmology and Eye Institute of Thrace, Democritus University of Thrace, Alexandroupolis, GreecePurpose: To develop, characterize, and validate a prototype digital aqueous humor outflow tonographer (DAHOM.Material and methods: The DAHOM was developed, characterized, and validated in three phases. Phase 1 involved construction of the sensor. This was broadly based on the fundamental design of a typical Schiotz tonographer with a series of improvements, including corneal indentation, which was converted to an electrical signal via a linear variable differential transducer, an analog signal which was converted to digital via ADC circuitry, and digital data acquisition and processing which was made possible by a serial port interface. Phase 2 comprised development of software for automated assessment of the outflow facility. Automated outflow facility assessment incorporated a series of fundamental improvements in comparison with traditional techniques, including software-based filtering of ripple noise and extreme variations, rigidity impact analysis, and evaluation of the impact of patient age, central corneal thickness, and ocular axial length. Phase 3 comprised characterization and validation of DAHOM, for which we developed an experimental setup using porcine cadaver eyes. DAHOM’s repeatability was evaluated by means of Cronbach’s alpha and intraclass correlation coefficient. The level of agreement with a standard Schiotz tonographer was evaluated by means of paired t-tests and Bland-Altman analysis in human eyes.Results: The experimental setup provided the necessary data for the characterization of DAHOM. A fourth order polynomial equation provided excellent fit (R square >0.999. DAHOM demonstrated high repeatability (Cronbach’s alpha ≥0.997; intraclass correlation coefficient ≥0.987 and an adequate level of

Digital readouts for large microwave low-temperature detector arrays

International Nuclear Information System (INIS)

Mazin, Benjamin A.; Day, Peter K.; Irwin, Kent D.; Reintsema, Carl D.; Zmuidzinas, Jonas

2006-01-01

Over the last several years many different types of low-temperature detectors (LTDs) have been developed that use a microwave resonant circuit as part of their readout. These devices include microwave kinetic inductance detectors (MKID), microwave SQUID readouts for transition edge sensors (TES), and NIS bolometers. Current readout techniques for these devices use analog frequency synthesizers and IQ mixers. While these components are available as microwave integrated circuits, one set is required for each resonator. We are exploring a new readout technique for this class of detectors based on a commercial-off-the-shelf technology called software defined radio (SDR). In this method a fast digital to analog (D/A) converter creates as many tones as desired in the available bandwidth. Our prototype system employs a 100MS/s 16-bit D/A to generate an arbitrary number of tones in 50MHz of bandwidth. This signal is then mixed up to the desired detector resonant frequency (∼10GHz), sent through the detector, then mixed back down to baseband. The baseband signal is then digitized with a series of fast analog to digital converters (80MS/s, 14-bit). Next, a numerical mixer in a dedicated integrated circuit or FPGA mixes the resonant frequency of a specified detector to 0Hz, and sends the complex detector output over a computer bus for processing and storage. In this paper we will report on our results in using a prototype system to readout a MKID array, including system noise performance, X-ray pulse response, and cross-talk measurements. We will also discuss how this technique can be scaled to read out many thousands of detectors

Digital beam position and phase monitor for P-LINAC for FAIR

Energy Technology Data Exchange (ETDEWEB)

Almalki, Mohammed

2013-07-01

For the planned P-LINAC for the FAIR facility, Beam Position Monitors (BPM) will be installed at 14 locations along the LINAC. The digital signal processing to derive the transverse beam position and the beam phase will be implemented by ''Libera Single Pass H''. The specification for position measurement is 0.1 mm spatial resolution and phase accuracy is 1 degree with respect to 325 MHz acceleration frequency. The results from the Libera digital signal processing were compared with the time-domain approach and the FFT analytic calculations. The first test was performed at the GSI UNILAC with a Ne4+ beam at 1.4 MeV / u. A single BPM was used to act as a ''Bunch arrival monitor'' to characterize the dependence of beam arrival time on bunch shape. The signals were sampled at 117.440 MHz with a 16-bit ADC to produce I and Q data streams. The first experimental results are reported.

Digital positron lifetime: the influence of noise

International Nuclear Information System (INIS)

Krille, Arnold; Krause-Rehberg, Reinhard; Anwand, Wolfgang

2011-01-01

In contrast to the world around where everything seems to go digital as soon as possible, positron lifetime spectrometers are kind of a 'last sanctuary' for analog measurements. Only a few of the newer spectrometers use the analog-digital-converters directly after the photomultipliers and extract the timing information via computer. Judging from their results it seems as if the current available converters and the timing mathematics are only as good as the conventional analog setup in the timing resolution. As it is decided that EPOS [1] will use digital positron lifetime, we try to find some reasons for limited timing resolution by simulating anode pulses from the photomultipliers and measuring the FWHM. We create pulses similar to current state-of-the-art 4GS/s digitizers but can control the level of noise and the bit-depth independently. We found that especially the noise (that would come from the analog electronics in/before the converters) has a great influence on the timing resolution. Also we try to use lowpass filtering to reduce that influence with great success.

Digital positron lifetime: the influence of noise

Energy Technology Data Exchange (ETDEWEB)

Krille, Arnold; Krause-Rehberg, Reinhard [Department of Physics, Martin-Luther-University Halle-Wittenberg, 06099 Halle (Germany); Anwand, Wolfgang, E-mail: arnold.krille@physik.uni-halle.de [Institute of Ion Beam Physics, Research Center Dresden-Rossendorf, 01314 Dresden (Germany)

2011-01-10

In contrast to the world around where everything seems to go digital as soon as possible, positron lifetime spectrometers are kind of a 'last sanctuary' for analog measurements. Only a few of the newer spectrometers use the analog-digital-converters directly after the photomultipliers and extract the timing information via computer. Judging from their results it seems as if the current available converters and the timing mathematics are only as good as the conventional analog setup in the timing resolution. As it is decided that EPOS [1] will use digital positron lifetime, we try to find some reasons for limited timing resolution by simulating anode pulses from the photomultipliers and measuring the FWHM. We create pulses similar to current state-of-the-art 4GS/s digitizers but can control the level of noise and the bit-depth independently. We found that especially the noise (that would come from the analog electronics in/before the converters) has a great influence on the timing resolution. Also we try to use lowpass filtering to reduce that influence with great success.

A Modified Design of a Thermocouple Based Digital Temperature Indicator with Opto-Isolation

Directory of Open Access Journals (Sweden)

S. C. BERA

2008-01-01

Full Text Available In the conventional thermocouple based digital temperature indicator the millivolt signal obtained from a thermocouple is first amplified and then converted into a digital signal by using analog-to-digital converter (ADC. This digital signal is then indicated as digital display of temperature using digital counter circuit or microprocessor/microcontroller based circuitry. In the present paper a modified AD conversion technique along with opto-isolation is used to indicate digitally the temperature without using any conventional analog-to-digital converter. The theory and design of the measuring technique are described in the paper. The non-linearity of thermocouple is eliminated by using look-up table within software program. The performance of the circuit has been experimentally tested by using mV input signal instead of a thermocouple as well as using a K-type thermocouple. The experimental results are reported in the paper.

Coherent time-stretch transformation for real-time capture of wideband signals.

Science.gov (United States)

Buckley, Brandon W; Madni, Asad M; Jalali, Bahram

2013-09-09

Time stretch transformation of wideband waveforms boosts the performance of analog-to-digital converters and digital signal processors by slowing down analog electrical signals before digitization. The transform is based on dispersive Fourier transformation implemented in the optical domain. A coherent receiver would be ideal for capturing the time-stretched optical signal. Coherent receivers offer improved sensitivity, allow for digital cancellation of dispersion-induced impairments and optical nonlinearities, and enable decoding of phase-modulated optical data formats. Because time-stretch uses a chirped broadband (>1 THz) optical carrier, a new coherent detection technique is required. In this paper, we introduce and demonstrate coherent time stretch transformation; a technique that combines dispersive Fourier transform with optically broadband coherent detection.

SIG Galileo final converter technical summary report

International Nuclear Information System (INIS)

Hinderman, J.D.

1979-05-01

The report is primarily concerned with the work performed for DOE on converter development and fabrication for the NASA Galileo Jupiter mission as a DOE prime contractor with interface primarily with Teledyne Energy Systems. The activities reported on were directed toward design, analysis and testing of modules and converters SN-1 thru SN-7 and attendant Quality Control and Reliability effort. Although assembly and testing of SN-1 was not accomplished due to the stop work order, the design was virtually completed and a significant amount of subcontracting and manufacturing of both module and converter components was underway. These subcontracting and manufacturing activities were selectively closed down depending upon degree of completion and material or hardware potential usage in the Technology Program

Digital Beamforming Scatterometer

Science.gov (United States)

Rincon, Rafael F.; Vega, Manuel; Kman, Luko; Buenfil, Manuel; Geist, Alessandro; Hillard, Larry; Racette, Paul

2009-01-01

feeds for vertical and horizontal polarization. System upgrades to dual polarization are currently under way. The DBSAR processor is a reconfigurable data acquisition and processor system capable of real-time, high-speed data processing. DBSAR uses an FPGA-based architecture to implement digitally down-conversion, in-phase and quadrature (I/Q) demodulation, and subsequent radar specific algorithms. The core of the processor board consists of an analog-to-digital (AID) section, three Altera Stratix field programmable gate arrays (FPGAs), an ARM microcontroller, several memory devices, and an Ethernet interface. The processor also interfaces with a navigation board consisting of a GPS and a MEMS gyro. The processor has been configured to operate in scatterometer, Synthetic Aperture Radar (SAR), and altimeter modes. All the modes are based on digital beamforming which is a digital process that generates the far-field beam patterns at various scan angles from voltages sampled in the antenna array. This technique allows steering the received beam and controlling its beam-width and side-lobe. Several beamforming techniques can be implemented each characterized by unique strengths and weaknesses, and each applicable to different measurement scenarios. In Scatterometer mode, the radar is capable to.generate a wide beam or scan a narrow beam on transmit, and to steer the received beam on processing while controlling its beamwidth and side-lobe level. Table I lists some important radar characteristics

A 10-bit 100 MSamples/s BiCMOS D/A Converter

DEFF Research Database (Denmark)

Jørgensen, Ivan Herald Holger; Tunheim, Svein Anders

1997-01-01

This paper presents a 10-bit Digital-to-Analogue Converter (DAC) based on the current steering principle. The DAC is processed in a 0.8 micron BiCMOS process and is designed to operate at a sampling rate of 100MSamples/s. The DAC is intended for applications using direct digital synthesis...

Analysis of parallel optical sampling rate and ADC requirements in digital coherent receivers

DEFF Research Database (Denmark)

Lorences Riesgo, Abel; Galili, Michael; Peucheret, Christophe

2012-01-01

We comprehensively assess analog-to-digital converter requirements in coherent digital receiver schemes with parallel optical sampling. We determine the electronic requirements in accordance with the properties of the free running local oscillator.......We comprehensively assess analog-to-digital converter requirements in coherent digital receiver schemes with parallel optical sampling. We determine the electronic requirements in accordance with the properties of the free running local oscillator....

Time-to-code converter with selection of time intervals on duration

International Nuclear Information System (INIS)

Atanasov, I.Kh.; Rusanov, I.R.; )

2001-01-01

Identification of elementary particles on the basis of time-of-flight represents the important approach of the preliminary selection procedure. Paper describes a time-to-code converter with preliminary selection of the measured time intervals as to duration. It consists of a time-to-amplitude converter, an analog-to-digital converter, a unit of selection of time intervals as to duration, a unit of total reset and CAMAC command decoder. The time-to-code converter enables to measure time intervals with 100 ns accuracy within 0-100 ns range. Output code capacity is of 10. Selection time constitutes 50 ns [ru

Calibrated Phase-Shifting Digital Holographic Microscope Using a Sampling Moiré Technique

Directory of Open Access Journals (Sweden)

Peng Xia

2018-05-01

Full Text Available A calibrated phase-shifting digital holographic microscope system capable of improving the quality of reconstructed images is proposed. Phase-shifting errors are introduced in phase-shifted holograms for numerous reasons, such as the non-linearity of piezoelectric transducers (PZTs, wavelength fluctuations in lasers, and environmental disturbances, leading to poor-quality reconstructions. In our system, in addition to the camera used to record object information, an extra camera is used to record interferograms, which are used to analyze phase-shifting errors using a sampling Moiré technique. The quality of the reconstructed object images can be improved by the phase-shifting error compensation algorithm. Both the numerical simulation and experiment demonstrate the effectiveness of the proposed system.

Converting Taxonomic Descriptions to New Digital Formats

Directory of Open Access Journals (Sweden)

Hong Cui

2008-01-01

Full Text Available Abstract.--The majority of taxonomic descriptions is currently in print format. The majority of digital descriptions are in formats such as DOC, HTML, or PDF and for human readers. These formats do not convey rich semantics in taxonomic descriptions for computer-aided process. Newer digital formats such as XML and RDF accommodate semantic annotations that allow computers to process the rich semantics on human's behalf, thus open up opportunities for a wide range of innovative usages of taxonomic descriptions, such as searching in more precise and flexible ways, integrating with gnomic and geographic information, generating taxonomic keys automatically, and text data mining and information visualization etc. This paper discusses the challenges in automated conversion of multiple collections of descriptions to XML format and reports an automated system, MARTT. MARTT is a machine-learning system that makes use of training examples to tag new descriptions into XML format. A number of utilities are implemented as solutions to the challenges. The utilities are used to reduce the effort for training example preparation, to facilitate the creation of a comprehensive schema, and to predict system performance on a new collection of descriptions. The system has been tested with several plant and alga taxonomic publications including Flora of China and Flora of North America.

Fast transient digitizer

International Nuclear Information System (INIS)

Villa, F.

1982-01-01

Method and apparatus for sequentially scanning a plurality of target elements with an electron scanning beam modulated in accordance with variations in a high-frequency analog signal to provide discrete analog signal samples representative of successive portions of the analog signal; coupling the discrete analog signal samples from each of the target elements to a different one of a plurality of high speed storage devices; converting the discrete analog signal samples to equivalent digital signals; and storing the digital signals in a digital memory unit for subsequent measurement or display

A Novel PPFHB Bidirectional DC-DC Converter for Supercapacitor Application

DEFF Research Database (Denmark)

Zhang, Zhe; Thomsen, Ole Cornelius; Andersen, Michael Andreas E.

2009-01-01

This paper presents a novel bidirectional DC-DC converter for the supercapacitor application. In the proposed converter, push-pull forward with half bridge (PPFHB) voltage doubler structure is used to reduce the number of the power switches and get higher voltage gain. Based on phase-shift modula......This paper presents a novel bidirectional DC-DC converter for the supercapacitor application. In the proposed converter, push-pull forward with half bridge (PPFHB) voltage doubler structure is used to reduce the number of the power switches and get higher voltage gain. Based on phase...

Digitally generated excitation and near-baseband quadrature detection of rapid scan EPR signals.

Science.gov (United States)

Tseitlin, Mark; Yu, Zhelin; Quine, Richard W; Rinard, George A; Eaton, Sandra S; Eaton, Gareth R

2014-12-01

The use of multiple synchronized outputs from an arbitrary waveform generator (AWG) provides the opportunity to perform EPR experiments differently than by conventional EPR. We report a method for reconstructing the quadrature EPR spectrum from periodic signals that are generated with sinusoidal magnetic field modulation such as continuous wave (CW), multiharmonic, or rapid scan experiments. The signal is down-converted to an intermediate frequency (IF) that is less than the field scan or field modulation frequency and then digitized in a single channel. This method permits use of a high-pass analog filter before digitization to remove the strong non-EPR signal at the IF, that might otherwise overwhelm the digitizer. The IF is the difference between two synchronized X-band outputs from a Tektronix AWG 70002A, one of which is for excitation and the other is the reference for down-conversion. To permit signal averaging, timing was selected to give an exact integer number of full cycles for each frequency. In the experiments reported here the IF was 5kHz and the scan frequency was 40kHz. To produce sinusoidal rapid scans with a scan frequency eight times IF, a third synchronized output generated a square wave that was converted to a sine wave. The timing of the data acquisition with a Bruker SpecJet II was synchronized by an external clock signal from the AWG. The baseband quadrature signal in the frequency domain was reconstructed. This approach has the advantages that (i) the non-EPR response at the carrier frequency is eliminated, (ii) both real and imaginary EPR signals are reconstructed from a single physical channel to produce an ideal quadrature signal, and (iii) signal bandwidth does not increase relative to baseband detection. Spectra were obtained by deconvolution of the reconstructed signals for solid BDPA (1,3-bisdiphenylene-2-phenylallyl) in air, 0.2mM trityl OX63 in water, 15 N perdeuterated tempone, and a nitroxide with a 0.5G partially-resolved proton

Measurement of Three-Dimensional Deformations by Phase-Shifting Digital Holographic Interferometry

Directory of Open Access Journals (Sweden)

Percival Almoro

2003-06-01

Full Text Available Out-of-plane deformations of a cantilever were measured using phase-shifting digital holographicinterferometry (PSDHI and the Fourier transform method (FTM. The cantilever was recorded in twodifferent states, and holograms were stored electronically with a charge-coupled device (CCD camera.When the holograms are superimposed and reconstructed jointly, a holographic interferogram results.The three-dimensional (3D surface deformations were successfully visualized by applying FTM toholographic interferogram analysis. The minimum surface displacement measured was 0.317 µm. Theprocessing time for the digital reconstruction and visualization of 3D deformation took about 1 minute.The technique was calibrated using Michelson interferometry setup.

An encryption scheme based on phase-shifting digital holography and amplitude-phase disturbance

International Nuclear Information System (INIS)

Hua Li-Li; Xu Ning; Yang Geng

2014-01-01

In this paper, we propose an encryption scheme based on phase-shifting digital interferometry. According to the original system framework, we add a random amplitude mask and replace the Fourier transform by the Fresnel transform. We develop a mathematical model and give a discrete formula based on the scheme, which makes it easy to implement the scheme in computer programming. The experimental results show that the improved system has a better performance in security than the original encryption method. Moreover, it demonstrates a good capability of anti-noise and anti-shear robustness

Analysis of a Multilevel Dual Active Bridge (ML-DAB DC-DC Converter Using Symmetric Modulation

Directory of Open Access Journals (Sweden)

M. A. Moonem

2015-04-01

Full Text Available Dual active bridge (DAB converters have been popular in high voltage, low and medium power DC-DC applications, as well as an intermediate high frequency link in solid state transformers. In this paper, a multilevel DAB (ML-DAB has been proposed in which two active bridges produce two-level (2L-5L, 5L-2L and 3L-5L voltage waveforms across the high frequency transformer. The proposed ML-DAB has the advantage of being used in high step-up/down converters, which deal with higher voltages, as compared to conventional two-level DABs. A three-level neutral point diode clamped (NPC topology has been used in the high voltage bridge, which enables the semiconductor switches to be operated within a higher voltage range without the need for cascaded bridges or multiple two-level DAB converters. A symmetric modulation scheme, based on the least number of angular parameters rather than the duty-ratio, has been proposed for a different combination of bridge voltages. This ML-DAB is also suitable for maximum power point tracking (MPPT control in photovoltaic applications. Steady-state analysis of the converter with symmetric phase-shift modulation is presented and verified using simulation and hardware experiments.

Three-phase electronic power converter for photovoltaic system connected to power line; Conversor eletronico de potencia trifasico para sistema fotovoltaico conectado a rede eletrica

Energy Technology Data Exchange (ETDEWEB)

Villalva, Marcelo Gradella

2010-10-15

This work is a contribution to the study of power converters for photovoltaic distributed generation systems. The main objective is to present the development and results of a three phase power converter for a grid-connected photovoltaic plant. The work presents experimental results and theoretical studies on the modeling and simulation of photovoltaic devices, regulation of the photovoltaic voltage, maximum power point tracking, and the modeling and control of a two-stage grid-connected power converter. (author)

State trajectories used to observe and control dc-to-dc converters

Science.gov (United States)

Burns, W. W., III; Wilson, T. G.

1976-01-01

State-plane analysis techniques are employed to study the voltage stepup energy-storage dc-to-dc converter. Within this framework, an example converter operating under the influence of a constant on-time and a constant frequency controller is examined. Qualitative insight gained through this approach is used to develop a conceptual free-running control law for the voltage stepup converter which can achieve steady-state operation in one on/off cycle of control. Digital computer simulation data are presented to illustrate and verify the theoretical discussions presented.

Digital citizens Digital nations: the next agenda

NARCIS (Netherlands)

A.W. (Bert) Mulder; M.W. (Martijn) Hartog

2015-01-01

DIGITAL CITIZENS CREATE A DIGITAL NATION Citizens will play the lead role as they – in the next phase of the information society – collectively create a digital nation. Personal adoption of information and communication technology will create a digital infrastructure that supports individual and

Simple explanation of the up-down ambiguity in πp and Kπ s-wave phase shifts

International Nuclear Information System (INIS)

Dean, N.W.; Chang, V.

1976-01-01

In both the π + π - and K + π - systems attempts to carry out a phase-shift analysis in the mass region below 1GeV/c 2 have consistently found two distinct solutions. This ''up-down'' ambiguity has been resolved by appealing to additional data and to arguments based on continuity in the energy variable. The letter shown that in both cases the up-down ambiguity is simply the lowest-order Gersten ambiguity, that is, the complex conjugation of the ''Barrelet zero''

A digital transducer and digital microphone using an optical technique

Science.gov (United States)

Ghelmansarai, F. A.

1996-09-01

A transducer is devised to measure pressure, displacements or angles by optical means. This transducer delivers a digital output without relying on interferometry techniques or analogue-to-digital converters. This device is based on an optical scanner and an optical detector. An inter-digital photoconductive detector (IDPC) is employed that delivers a series of pulses, whose number depends on the scan length. A pre-objective scanning configuration is used that allows for the possibility of a flat image plane. The optical scanner provides scanning of IDPC and the generated scan length is proportional to the measurand.

The ALTRO Chip A 16-channel A/D Converter and Digital Processor for Gas Detectors

CERN Document Server

Esteve-Bosch, R; Mota, B; Musa, L

2003-01-01

The ALTRO (ALICE TPC Read Out) chip is a mixed-signal integrated circuit designed to be one of the building blocks of the readout electronics for gas detectors. Originally conceived and optimised for the Time Projection Chamber (TPC) of the ALICE experiment at the CERN LHC, its architecture and programmability makes it suitable for the readout of a wider class of gas detectors. In one single chip, the analogue signals from 16 channels are digitised, processed, compressed and stored in a multi-acquisition memory. The Analogue-to- Digital converters embedded in the chip have a 10-bit dynamic range and a maximum sampling rate in the range of 20 to 40MHz. After digitisation, a pipelined hardwired Processor is able to remove from the input signal a wide range of systematic and non-systematic perturbations, related to the non-ideal behaviour of the detector, temperature variation of the electronics, environmental noise, etc. Moreover, the Processor is able to suppress the signal tail within 1mus after the pulse pea...

ITAR Free Commercial-of-the-Shelf DC/DC Converter

Science.gov (United States)

Denzinger, Wolfgang; Hintze, Thomas

2014-08-01

A commercial-of-the-shelf (COTS) DC/DC converter for digital space equipment has been developed by ASP under ESA contract with special emphasis on low cost, no use of ITAR listed EEE parts like Mosfets, minimum number of rad-hard digital IC's and a design tolerance against single event effects by appropriate filtering. However, the intention to qualify this discrete converter design for a low cost FM series production was difficult due to the high up-sceening cost of EEE-parts with one lot guarantee and minimum-by. To overcome this problem, in a next step a redesign of the DC/DC converter was performed with all semiconductors like bipolar transistors, rectifiers and zener diodes packaged into hybrids. With this approach it was possible to buy a high number of less expensive wafers or dies from one lot, to perform a lot acceptance test and to integrate the dies into hybrid packages with further up- screening for FM use. The semiconductors have been packaged into three signal hybrids with 44 pins and one power hybrid with 24 pins for the dissipating transistors and rectifiers. The design of the hybrids is such, that all integrated semiconductors can be tested individually. The qualification of four EQM DC/DC converters with different combinations of output voltages has been successfully performed and two FM's have been manufactured and tested.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

International Nuclear Information System (INIS)

Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-01-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array