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Sample records for digital circuit design

  1. Automatic design of digital synthetic gene circuits.

    Directory of Open Access Journals (Sweden)

    Mario A Marchisio

    2011-02-01

    Full Text Available De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.

  2. Automatic design of digital synthetic gene circuits.

    Science.gov (United States)

    Marchisio, Mario A; Stelling, Jörg

    2011-02-01

    De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.

  3. Practical design of digital circuits basic logic to microprocessors

    CERN Document Server

    Kampel, Ian

    1983-01-01

    Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible. The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his """"tools"""" - or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptio

  4. Design theory of digital circuits at switch level

    Institute of Scientific and Technical Information of China (English)

    吴训威; F.Prosser

    1996-01-01

    By analysing problems in the traditional design theory of digital circuits it is proposed that both switching variable and signal variable should be adopted for describing the switching state of internal elements and signal in digital circuits respectively.Based on the above viewpoint the switch-signal theory is established.According to the working principle in CMOS circuits,the related design technique at switch level is developed.By using the practical design examples it is shown that the circuits designed at switch level have simpler structures than their counterparts designed at the traditional gate level since the switch transistors are used as construction units in designs.

  5. Digital integrated circuit design using Verilog and SystemVerilog

    CERN Document Server

    Mehler, Ronald W

    2014-01-01

    For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

  6. Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

    Directory of Open Access Journals (Sweden)

    Ramesh Vaddi

    2009-01-01

    Full Text Available In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

  7. Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

    CERN Document Server

    Gielen, Georges; Christie, Phillip; Draxelmayr, Dieter; Janssens, Edmond; Maex, Karen; Vucurevich, Ted

    2011-01-01

    This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog blocks. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.

  8. Design of a New Chaos Circuit and Its Encryption to Digital Information

    Institute of Scientific and Technical Information of China (English)

    WANG Hong; PENG Jian-hua; ZHOU Zhen-gou

    2004-01-01

    A new hyperchaos circuit system with simple structure is designed in this paper. It can be implemented with changeable dimensions 3, 5, 7, 9, etc, therefore it can afford different security grades for applications. The dynamic characters of the 7th order circuit have been analyzed as an example. Using the hyperchaos time sequence produced by this circuit as key sequence, the encryption and decryption to digital signals of text and image files have been realized, and the real-time ability has been increased with encrypting digital signals per byte.

  9. Principles of transistor circuits introduction to the design of amplifiers, receivers and digital circuits

    CERN Document Server

    Amos, S W

    2013-01-01

    For over thirty years, Stan Amos has provided students and practitioners with a text they could rely on to keep them at the forefront of transistor circuit design. This seminal work has now been presented in a clear new format and completely updated to include the latest equipment such as laser diodes, Trapatt diodes, optocouplers and GaAs transistors, and the most recent line output stages and switch-mode power supplies.Although integrated circuits have widespread application, the role of discrete transistors is undiminished, both as important building blocks which students must understand an

  10. The circuit designer's companion

    CERN Document Server

    Williams, Tim

    2013-01-01

    The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll

  11. A Comparative Study of Ultra-Low Voltage Digital Circuit Design

    Directory of Open Access Journals (Sweden)

    Aaron Arthurs

    2012-07-01

    Full Text Available Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which,however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.

  12. A Comparative Study of Ultra-Low Voltage Digital Circuit Design

    Directory of Open Access Journals (Sweden)

    Aaron Arthurs,

    2012-06-01

    Full Text Available Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which,however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delay insensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the trade offs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.

  13. Hyper-chaotic LÜ System Simulation Design of Digital Circuit Based on DSP Builder

    Directory of Open Access Journals (Sweden)

    Zhang Xiaohong

    2013-05-01

    Full Text Available In order to overcome sensitive defects of components deviations and environment defects in analog circuit design, a novel four-dimensional hyperchaotic systems is constructed based on LÜ system. Basic nonlinear dynamics characteristics are analyzed to the new system. By optimizing the design of sampling frequency selection, gain adjustments, parameter configuration etc., the hyperchaotic circuit runs stably while the signal amplitude is reasonably controlled. Curves of the digital chaotic sequence show smooth without jagged shape. The circuit can be applied to other digital realization of chaotic systems with commonality and expandability. Its experimental results fully consistent with phase space structures of the continuous chaotic system, which shows the development of chaotic systems based on FPGA is feasible and practical.

  14. Analog circuit design

    CERN Document Server

    Dobkin, Bob

    2012-01-01

    Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <

  15. Design of Microcantilever-Based Biosensor with Digital Feedback Control Circuit

    Directory of Open Access Journals (Sweden)

    Jayu P. Kalambe

    2012-01-01

    Full Text Available This paper present the design of cantilever-based biosensors with new readout, which hold promises as fast and cheap “point of care” device as well as interesting research tools. The fabrication process and related issues of the cantilever based bio-sensor are discussed. Coventorware simulation is carried out to analyze the device behavior. A fully integrated control circuit has been designed to solve manufacturing challenge which will take care of positioning of the cantilever instead of creating nanometer gap between the electrodes. The control circuit will solve the manufacturing challenge faced by the readout methods where it is essential to maintain precise gap between the electrodes. The circuit can take care of variation obtained due to fabrication process and maintain the precise gap between the electrodes by electrostatic actuation. The control circuit consist of analog and digital modules. The reliability issues of the sensor are also discussed.

  16. Fundamental Approach in Digital Circuit Design for 1-MHz Frequency PWM Gate Drive Application

    Directory of Open Access Journals (Sweden)

    Nor Zaihar Yahaya

    2011-01-01

    Full Text Available This paper discusses the design of a digital programmable logic circuit to produce a 5 V - output square wave pulses for four high power MOSFET switches using a fixed PWM circuit. It will be applied to drive the synchronous rectifier buck converter(SRBC circuit. The PWM signals with multiple fixed time delay of 15 ns, 232 ns, 284 ns and 955 ns are generated. The steps taken to analyze each propagation time delay of each logic gate used and its combination are carefully studied. A multiplexer is added at the output of the logic circuit to select and produce the desired output pulses of 20% duty ratio. The logic outputs are compared with the analog pulses and results match each other within 1% in difference.

  17. Applying the problem-based learning approach in teaching digital integrated circuit design

    OpenAIRE

    Lei, CU

    2010-01-01

    The problem-based learning (PBL) method has been applied to curriculum development in some areas of electrical engineering. The overall result has been a positive learning experience for students. However, PBL has not, as yet, been used in the area of digital integrated circuit (IC) design. IC design is in a revolutionary phase at present. It could even be said that IC design is at the beginning of a new epoch. Design is moving toward nano-size. Thus, design techniques are advancing so rap...

  18. Principles of transistor circuits introduction to the design of amplifiers, receivers and digital circuits

    CERN Document Server

    Amos, S W

    2013-01-01

    Principles of Transistor Circuits: Sixth Edition discusses the principles, concepts, and practices involved integrated circuits. The current edition includes up-to-date circuits, the section on thyristors has been revised to give more information on modern types, and dated information has been eliminated. The book covers related topics such as semiconductors and junction diodes; the principles behind transistors; and common amplifiers. The book also covers bias and DC stabilization; large-signal and small-signal AF amplifiers; DC and pulse amplifiers; sinusoidal oscillators; pulse and sawtooth

  19. Digital circuit boards mach 1 GHz

    CERN Document Server

    Morrison, Ralph

    2012-01-01

    A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove

  20. Principles of transistor circuits introduction to the design of amplifiers, receivers and digital circuits

    CERN Document Server

    Amos, S W

    1990-01-01

    Principles of Transistor Circuits, Seventh Edition discusses the fundamental concepts of transistor circuits. The book is comprised of 16 chapters that cover amplifiers, oscillators, and generators. Chapter 1 discusses semiconductors and junction nodes, while Chapter 2 covers the basic principles of transistors. The subsequent chapters focus on amplifiers, where one of the chapters discusses bias and D.C. The book also talks about sinusoidal oscillators and covers modulators, demodulators, mixers, and receivers. Chapters 13 and 14 discuss pulse generators and sawtooth generators, respectively.

  1. Design of two digital radiation tolerant integrated circuits for high energy physics experiments data readout

    CERN Document Server

    Bonacini, Sandro

    2003-01-01

    High Energy Physics research (HEP) involves the design of readout electron- ics for its experiments, which generate a high radiation ¯eld in the detectors. The several integrated circuits placed in the future Large Hadron Collider (LHC) experiments' environment have to resist the radiation and carry out their normal operation. In this thesis I will describe in detail what, during my 10-months partic- ipation in the digital section of the Microelectronics group at CERN, I had the possibility to work on: - The design of a radiation-tolerant data readout digital integrated cir- cuit in a 0.25 ¹m CMOS technology, called \\the Kchip", for the CMS preshower front-end system. This will be described in Chapter 3. - The design of a radiation-tolerant SRAM integrated circuit in a 0.13 ¹m CMOS technology, for technology radiation testing purposes and fu- ture applications in the HEP ¯eld. The SRAM will be described in Chapter 4. All the work has carried out under the supervision and with the help of Dr. Kostas Klouki...

  2. The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits

    CERN Document Server

    Arora, Mohit

    2012-01-01

    This book highlights the complex issues, tasks and skills that must be mastered by an IP designer, in order to design an optimized and robust digital circuit to solve a problem. The techniques and methodologies described can serve as a bridge between specifications that are known to the designer and RTL code that is final outcome, reducing significantly the time it takes to convert initial ideas and concepts into right-first-time silicon.� Coverage focuses on real problems rather than theoretical concepts, with an emphasis on design techniques across various aspects of chip-design.�� Describes techniques to help IP designers get it right the first time, creating designs optimized in terms of power, area and performance; Focuses on practical aspects of chip design and minimizes theory; Covers chip design in a consistent way, starting with basics and gradually developing advanced concepts, such as electromagnetic compatibility (EMC) design techniques and low-power design techniques such as dynamic voltage...

  3. DATA BYPASSING ARCHITECTURE AND CIRCUIT DESIGN FOR 32-BIT DIGITAL SIGNAL PROCESSOR

    Institute of Scientific and Technical Information of China (English)

    Chen Xiaoyi; Yao Qingdong; Liu Peng

    2005-01-01

    This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0,18μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP's performance.The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.

  4. Digitally-assisted analog and RF CMOS circuit design for software-defined radio

    CERN Document Server

    Okada, Kenichi

    2011-01-01

    This book describes the state-of-the-art in RF, analog, and mixed-signal circuit design for Software Defined Radio (SDR). It synthesizes for analog/RF circuit designers the most important general design approaches to take advantage of the most recent CMOS technology, which can integrate millions of transistors, as well as several real examples from the most recent research results.

  5. Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

    Science.gov (United States)

    Taylor, B.

    1990-01-01

    The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

  6. Digital integrated circuits

    Science.gov (United States)

    Polasek, P.; Halamik, J.

    1984-05-01

    The term semicustom designed integrated circuits denotes integrated circuits of an all purpose character in which the production of chips is completed by using one to three custom design stencil type exposure masks. This involves in most cases interconnecting masks that are used to devise the circuit function desired by the customer. Silicon plates with an all purpose gate matrix are produced up to the interconnection level and can be kept at this phase in storage, after which a customer's specific demands can be met very expediently. All purpose logic fields containing 200 logic gates on a chip and an all purpose chip to be expanded to 1,000 logic gates are discussed. The technology facilitates the devising of fast gates with a delay of approximately 5 ns and power dissipation of 1 mW. In assembly it will be possible to make use of the entire assortment of the currently used casings with 16, 18, 20, 24, 28 and 40 outlets. In addition to the development of the mentioned technology, a general methodology for design of the mentioned gate fields is currently under way.

  7. Analog circuit design designing dynamic circuit response

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

  8. A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMS

    KAUST Repository

    Dadgour, Hamed F.

    2010-01-01

    Nano-Electro-Mechanical Switches (NEMS) offer the prospect of improved energy-efficiency in digital circuits due to their near-zero subthreshold leakage and extremely low subthreshold swing values. Among the different approaches of implementing NEMS, laterallyactuated double-gate NEMS devices have attracted much attention as they provide unique and exciting circuit design opportunities. For instance, this paper demonstrates that compact XOR/XNOR gates can be implemented using only two such NEMS transistors. While this in itself is a major improvement, its implications for minimizing Boolean functions using Karnaugh maps (K-maps) are even more significant. In the standard K-map technique, which is used in digital circuit design, adjacent "1s" (minterms) are grouped only in horizontal and/or vertical directions; the diagonal (or zig-zag) grouping of adjacent "1s" is not an option due to the absence of compact XOR/XNOR gates. However, this work demonstrates, for the first time ever, that in lateral double-gate NEMS-based circuits, grouping of minterms is possible in horizontal and vertical as well as diagonal fashions. This is because the diagonal groupings of minterms require XOR/XNOR operations, which are available in such NEMS-based circuits at minimal costs. This novel design paradigm facilitates more compact implementations of Boolean functions and thus, considerably improves their energy-efficiency. For example, a lateral NEMS-based full-adder is implemented using less than half the number of transistors, which is required by a CMOS-based full-adder. Furthermore, circuit simulations are performed to evaluate the energy-efficiencies of the NEMS-based 32-bit carry-save adders compared to their standard CMOS-based counterparts. Copyright 2010 ACM.

  9. Analog circuit design designing waveform processing circuits

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    The fourth volume in the set Designing Waveform-Processing Circuits builds on the previous 3 volumes and presents a variety of analog non-amplifier circuits, including voltage references, current sources, filters, hysteresis switches and oscilloscope trigger and sweep circuitry, function generation, absolute-value circuits, and peak detectors.

  10. Design and Realization of GaAs Digital Circuit for Mixed Signal MMIC Implementation in AESA Applications

    Directory of Open Access Journals (Sweden)

    Andrea Bentini

    2011-01-01

    Full Text Available A complete design flow starting from the technological process development up to the fabrication of digital circuits is presented. The aim of this work is to demonstrate the GaAs Enhancement/Depletion (E/D double stop-etch technology implementation feasibility for digital applications, aimed at mixed signal circuit integration. On the basis of the characterization of small E/D devices with different Gate peripheries, developed by the SELEX-SI foundry, and the analysis of several GaAs-based logical families, the most suitable logic for the available technology has been selected. Then, simple test vehicles (level shifters, NOR logic gates and D Flip-Flops have been designed, realized, and measured to validate the design strategy applied to the GaAs E/D process. These logical circuits are preliminary to the design of a more complex serial-to-parallel converter, to be implemented onto the same chip together with RF analog blocks, such as stepped attenuators and phase shifters.

  11. Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Lun Li

    2006-04-01

    Full Text Available The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stages can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses upon a technique that integrates the best characteristics of both simulation and formal verification methods to provide an effective design validation tool, referred as Integrated Design Validation (IDV. The novelty in this approach consists of three components, circuit complexity analysis, partitioning based on design hierarchy, and coverage analysis. The circuit complexity analyzer and partitioning decompose a large design into sub-components and feed sub-components to different verification and/or simulation tools based upon known existing strengths of modern verification and simulation tools. The coverage analysis unit computes the coverage of design validation and improves the coverage by further partitioning. Various simulation and verification tools comprising IDV are evaluated and an example is used to illustrate the overall validation process. The overall process successfully validates the example to a high coverage rate within a short time. The experimental result shows that our approach is a very promising design validation method.

  12. Digital signal processing in power electronics control circuits

    CERN Document Server

    Sozanski, Krzysztof

    2013-01-01

    Many digital control circuits in current literature are described using analog transmittance. This may not always be acceptable, especially if the sampling frequency and power transistor switching frequencies are close to the band of interest. Therefore, a digital circuit is considered as a digital controller rather than an analog circuit. This helps to avoid errors and instability in high frequency components. Digital Signal Processing in Power Electronics Control Circuits covers problems concerning the design and realization of digital control algorithms for power electronics circuits using

  13. Intuitive analog circuit design

    CERN Document Server

    Thompson, Marc

    2013-01-01

    Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi

  14. Automatic Test Pattern Generation for Digital Circuits

    Directory of Open Access Journals (Sweden)

    S. Hemalatha

    2014-04-01

    Full Text Available Digital circuits complexity and density are increasing and at the same time it should have more quality and reliability. It leads with high test costs and makes the validation more complex. The main aim is to develop a complete behavioral fault simulation and automatic test pattern generation (ATPG system for digital circuits modeled in verilog and VHDL. An integrated Automatic Test Generation (ATG and Automatic Test Executing/Equipment (ATE system for complex boards is developed here. An approach to use memristors (resistors with memory in programmable analog circuits. The Main idea consists in a circuit design in which low voltages are applied to memristors during their operation as analog circuit elements and high voltages are used to program the memristor’s states. This way, as it was demonstrated in recent experiments, the state of memristors does not essentially change during analog mode operation. As an example of our approach, we have built several programmable analog circuits demonstrating memristor -based programming of threshold, gain and frequency. In these circuits the role of memristor is played by a memristor emulator developed by us. A multiplexer is developed to generate a class of minimum transition sequences. The entire hardware is realized as digital logical circuits and the test results are simulated in Model sim software. The results of this research show that behavioral fault simulation will remain as a highly attractive alternative for the future generation of VLSI and system-on-chips (SoC.

  15. Ultra-low-voltage design of energy-efficient digital circuits

    CERN Document Server

    Reynders, Nele

    2015-01-01

    This book focuses on increasing the energy-efficiency of electronic devices so that portable applications can have a longer stand-alone time on the same battery. The authors explain the energy-efficiency benefits that ultra-low-voltage circuits provide and provide answers to tackle the challenges which ultra-low-voltage operation poses. An innovative design methodology is presented, verified, and validated by four prototypes in advanced CMOS technologies. These prototypes are shown to achieve high energy-efficiency through their successful functionality at ultra-low supply voltages.

  16. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  17. Digital signal processing in power electronics control circuits

    CERN Document Server

    Sozański, Krzysztof

    2017-01-01

    This book discusses problems concerning the design and realization of digital control algorithms for power electronics circuits using digital signal processing (DSP) methods. It includes Matlab examples for illustration of considered problems.

  18. Statistical circuit design for yield improvement in CMOS circuits

    Science.gov (United States)

    Kamath, H. J.; Purviance, J. E.; Whitaker, S. R.

    1990-01-01

    This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

  19. Bounded Algebra and Current-Mode Digital Circuits

    Institute of Scientific and Technical Information of China (English)

    WU Xunwei; Massoud Pedram

    1999-01-01

    This paper proposes two boundedarithmetic operations, which are easily realized with current signals.Based on these two operations, a bounded algebra system suitable fordescribing current-mode digital circuits is developed and itsrelationship with the Boolean algebra, which is suitable for representingvoltage-mode digital circuits, is investigated. Design procedure forcurrent-mode circuits using the proposed algebra system is demonstratedon a number of common circuit elements which are used to realizearithmetic operations, such as adders and multipliers.

  20. Digital simulation software used in digital circuit design%数字仿真软件在数字电路设计中的应用

    Institute of Scientific and Technical Information of China (English)

    窦群

    2014-01-01

    Information age is an age of information can not be separated.The greatest feature of this era is the computer application is very broad, almost throw into confusion all aspects of society,including,in particular,electronic products,turns out to be omnipresent.This paper begins with a brief introduction about some relevant content digital simulation software and digital circuits,and focuses on the three in today's society is very frequent and extensive use of digital simulation software,respectively,they were briefly highlighting a significant role in promoting digital simulation software for digital circuit design.%信息化的时代就是一个离不开信息的时代。这个时代最大的特点就是计算机应用的十分的广泛,几乎攘括了社会所有的方面,尤其是电子产品,真可谓是无所不在。本文首先简要的介绍了一下数字仿真软件和数字电路的一些相关的内容,并重点阐述了三种在现今的社会使用的十分频繁并且广泛的数字仿真软件,分别对他们进行了简单介绍,着重说明数字仿真软件对数字电路设计中的重大促进作用。

  1. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  2. Introduction to RIMEP2: A Multi-Expression Programming System for the Design of Reversible Digital Circuits

    OpenAIRE

    Hadjam, Fatima; Moraga, Claudio

    2014-01-01

    Quantum computers are considered as a future alternative to circumvent the heat dissipation problem of VLSI circuits. The synthesis of reversible circuits is a very promising area of study considering the expected further technological advances towards quantum computing. In this report, we propose a linear genetic programming system to design reversible circuits -RIMEP2-. The system has evolved reversible circuits starting from scratch without resorting to a pre-existing library. The results ...

  3. Design of Static Flip-Flops for Low-Power Digital Sequential Circuits

    Directory of Open Access Journals (Sweden)

    E. Jaya Kumar

    2015-12-01

    Full Text Available In this paper, we correlated various Master and slave flip-flops i.e., single edge triggered flipflops. The low-power flip-flops have place utmost necessary elements all the range of the constructing static or successive circuits. We accomplish the comparison for their performance, Delay, Rise time, Fall Time and Power dissipation. Because Power confide in the number of transistors in the circuits, so we are comparing and calculating the number of transistors of the each flip-flops. Analysis of a static/sequential circuits is done by Linear Feed Back Shift Register (LFSR using 45nm Technology with 5MHZ frequencies and their performance analysis.

  4. Controllability/observability analysis of digital circuits

    Energy Technology Data Exchange (ETDEWEB)

    Goldstein, L.H.

    1978-11-01

    The testability of a digital circuit is directy related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively. A method for analyzing digital circuits in terms of six functions which characterize combinational and sequential controllability and observability is presented.

  5. Controllability/observability analysis of digital circuits

    Energy Technology Data Exchange (ETDEWEB)

    Goldstein, L.H.

    1979-01-01

    The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively. A method for analyzing digital circuits in terms of six functions which characterize combinational and sequential controllability and observability is presented.

  6. Controllability/observability analysis of digital circuits

    Energy Technology Data Exchange (ETDEWEB)

    Goldstein, L.H.

    1979-09-01

    The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively. A method for analyzing digital circuits in terms of six functions which characterize combinational and sequential controllability and observability is presented.

  7. Emulational Design of Digits Touring Inspection Circuit%数字巡回检测电路的仿真设计

    Institute of Scientific and Technical Information of China (English)

    孔维成; 杨海明; 李悦; 张光敏

    2012-01-01

    用数字集成设计完成的巡回检测电路能够实现对多路信号进行巡回检测,并对被检测线路工作情况及时监测显示,对出现故障的线路及时报警,通知维修人员及时维修,为设备安全可靠的运行提供有力保障。所以,该设计可广泛推广应用于现代化生产中。本文用数字集成电路完成八路巡回检测电路设计,并对电路设计原理进行了详细阐述,用Muhisim10电路仿真软件对电路的可行性和可操作性进行了模拟仿真,通过模拟仿真充分验证了本电路设计稳定可靠易于实现。%The touring inspection circuits designed by the digital integrated circuit can inspect multiple signals, and timely monitor the working status of the inspected circuits, alarming when finding the bad circuits, noticing the maintenance personnel, providing strong safeguards for the reliable operation of the equipments. Therefore, the design can be widely used in the industrial and agricul- tural production. The article designs the eight-channel touring inspection circuit by the digital integrated circuit, and expounds the design principles in detail, making the emulation to the feasibility and maneuverability of the circuits by the circuit emulation soft- ware Multisin lO. The emulation fully proved that the circuit design is stable, reliable, and easy to be realized.

  8. Digital system design with VHDL

    Energy Technology Data Exchange (ETDEWEB)

    Kang, Jin Gu; Lee, Da Young; Song, Je Chel

    2000-09-15

    This book is comprised of eleven chapters, which are review of basic logic design including combinational logic circuit, KARNAUGH MAPS, Hazard of combinational circuit, Melay order circuit design and synchronous design, introduction of VHDL like VHDL module of Multiplexer and VHDL Function, design with PLD for program, circuit design for arithmetical operation, digital design using SM chart, PGA and CPLD design, Floating-point calculation, extra issues on VHDL, VHDL module for memory and bus,design for hardware test and a testing and examples for design such as UART design and M68HC05 micro controller.

  9. Genetic circuit design automation.

    Science.gov (United States)

    Nielsen, Alec A K; Der, Bryan S; Shin, Jonghyeon; Vaidyanathan, Prashant; Paralanov, Vanya; Strychalski, Elizabeth A; Ross, David; Densmore, Douglas; Voigt, Christopher A

    2016-04-01

    Computation can be performed in living cells by DNA-encoded circuits that process sensory information and control biological functions. Their construction is time-intensive, requiring manual part assembly and balancing of regulator expression. We describe a design environment, Cello, in which a user writes Verilog code that is automatically transformed into a DNA sequence. Algorithms build a circuit diagram, assign and connect gates, and simulate performance. Reliable circuit design requires the insulation of gates from genetic context, so that they function identically when used in different circuits. We used Cello to design 60 circuits forEscherichia coli(880,000 base pairs of DNA), for which each DNA sequence was built as predicted by the software with no additional tuning. Of these, 45 circuits performed correctly in every output state (up to 10 regulators and 55 parts), and across all circuits 92% of the output states functioned as predicted. Design automation simplifies the incorporation of genetic circuits into biotechnology projects that require decision-making, control, sensing, or spatial organization.

  10. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  11. Digital and analog gene circuits for biotechnology.

    Science.gov (United States)

    Roquet, Nathaniel; Lu, Timothy K

    2014-05-01

    Biotechnology offers the promise of valuable chemical production via microbial processing of renewable and inexpensive substrates. Thus far, static metabolic engineering strategies have enabled this field to advance industrial applications. However, the industrial scaling of statically engineered microbes inevitably creates inefficiencies due to variable conditions present in large-scale microbial cultures. Synthetic gene circuits that dynamically sense and regulate different molecules can resolve this issue by enabling cells to continuously adapt to variable conditions. These circuits also have the potential to enable next-generation production programs capable of autonomous transitioning between steps in a bioprocess. Here, we review the design and application of two main classes of dynamic gene circuits, digital and analog, for biotechnology. Within the context of these classes, we also discuss the potential benefits of digital-analog interconversion, memory, and multi-signal integration. Though synthetic gene circuits have largely been applied for cellular computation to date, we envision that utilizing them in biotechnology will enhance the efficiency and scope of biochemical production with living cells.

  12. Hardware synthesis from DDL description. [simulating a digital system for computerized design of large scale integrated circuits

    Science.gov (United States)

    Shiva, S. G.; Shah, A. M.

    1980-01-01

    The details of digital systems can be conveniently input into the design automation system by means of hardware description language (HDL). The computer aided design and test (CADAT) system at NASA MSFC is used for the LSI design. The digital design language (DDL) was selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. Problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system are addressed.

  13. A Comparative Analysis of Low Power and Area Efficient Digital Circuit Design

    OpenAIRE

    B. Dilli Kumar; Chandra Babu, A.; Prasad, V.

    2013-01-01

    VLSI design technology. If the power consumption is less, then the amount of power dissipation is also less. The power dissipation of a device can be reduced by using different low power techniques. In the present paper the performance of 4x1 multiplexer in different low power techniques was analyzed and its power dissipation in those techniques is compared with the conventional CMOS design. Each of these techniques has different advantages depending on their logic of operation. The simulatio...

  14. Circuit design for reliability

    CERN Document Server

    Cao, Yu; Wirth, Gilson

    2015-01-01

    This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.

  15. New Active Digital Pixel Circuit for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.

  16. Design of a reliable PUF circuit based on R-2R ladder digital-to-analog convertor

    Science.gov (United States)

    Pengjun, Wang; Xuelong, Zhang; Yuejun, Zhang; Jianrui, Li

    2015-07-01

    A novel physical unclonable functions (PUF) circuit is proposed, which relies on non-linear characteristic of analog voltage generated by R-2R ladder DAC. After amplifying the deviation signal, the robustness of the DAC-PUF circuit has increased significantly. The DAC-PUF circuit is designed in TSMC 65 nm CMOS technology and the layout occupies 86.06 × 63.56 μm2. Monte Carlo simulation results show that the reliability of the DAC-PUF circuit is above 98% over a comprehensive range of environmental variation, such as temperature and supply voltage. Project supported by the National Natural Science Foundation of China (Nos. 61474068, 61404076, 61274132), the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), and the K. C. Wong Magna Fund in Ningbo University, China.

  17. Power management of digital circuits in deep sub-micron CMOS technologies

    CERN Document Server

    Henzler, Stephan

    2006-01-01

    In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. This book mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side.

  18. ESD analog circuits and design

    CERN Document Server

    Voldman, Steven H

    2014-01-01

    A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design.  It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres

  19. 基于数字电路的汽车尾灯控制电路设计%On the Application of Digital Circuit to the Design of Control Circuit of Automobile Taillight

    Institute of Scientific and Technical Information of China (English)

    朱建武; 叶丽

    2012-01-01

    介绍了一种纯数字电路的汽车尾灯控制电路的设计方案,分析汽车尾灯控制电路的工作状态及其实现功能的关键点。将寄存器和计数器结合在一起实现该电路。%Based on an application of a pure digital design of controlled circuit of automobile taillight ,this thesis introduces the working state of the control circuit of automobile taillight and analyzes the keys to fulfill the function of it. The circuit can be realized by combining the register and counter.

  20. A novel 2-phase reliability improvement of digital circuits

    Science.gov (United States)

    Shojaei, Maryam; Mahani, Ali

    2016-12-01

    Nowadays several methods based on modular redundancy are proposed to increase the reliability of digital circuits. Redundant fault tolerant techniques increase the consumed power and area overhead. So in this paper a two phase fault tolerant design is proposed to get the balance between reliability and area overhead. In the first phase, reliability optimization of digital circuits which utilizes the architecture with higher reliability as an objective function is considered. Then the automatic insertion of selective non-uniform redundancy is applied to improve the reliability of obtained circuit as second phase. To show the effectiveness of the proposed method, simulation results are compared with triple modular redundancy.

  1. Modeling digital switching circuits with linear algebra

    CERN Document Server

    Thornton, Mitchell A

    2014-01-01

    Modeling Digital Switching Circuits with Linear Algebra describes an approach for modeling digital information and circuitry that is an alternative to Boolean algebra. While the Boolean algebraic model has been wildly successful and is responsible for many advances in modern information technology, the approach described in this book offers new insight and different ways of solving problems. Modeling the bit as a vector instead of a scalar value in the set {0, 1} allows digital circuits to be characterized with transfer functions in the form of a linear transformation matrix. The use of transf

  2. GLITCH ANALYSIS AND REDUCTION IN DIGITAL CIRCUITS

    Directory of Open Access Journals (Sweden)

    Ronak Shah

    2016-08-01

    Full Text Available Hazard in digital circuits is unnecessary transitions due to gate propagation delay in that circuit. Hazards occur due to uneven delay offered in the path of the various ongoing signals. One of the important reasons for power dissipation in CMOS circuits is the switching activity .This include activities such as spurious pulses, called glitches. Power optimization techniques that concentrate on the reduction of switching power dissipation of a given circuit are called glitch reduction techniques. In this paper, we analyse various Glitch reduction techniques such as Hazard filtering Technique, Balanced Path Technique, Multiple Threshold Technique and Gate Freezing Technique. We also measure the parameters such as noise and delay of the circuits on application of various techniques to check the reliability of different circuits in various situations.

  3. Design and Implementation of Ultra-Small-Size and Ultra-Low-Power Digital Systems on GaAs-based Hexagonal Nanowire Networks Utilizing a Hexagonal BDD Quantum Circuit Approach

    OpenAIRE

    Kasai, S.; Yumoto, M; Sato, T.; Hasegawa, H.

    2004-01-01

    This paper discusses feasibility of design and future implementation of ultrasmall-size and ultra-low-power digital logic systems by a hexagonal BDD (binary-decision diagram) quantum circuit approach. The discussion is based on various circuits formed on GaAs-based hexagonal nanowire networks controlled by nanometer scale Schottky wrap gates (WPGs). Starting from basic node devices and elementary logic function blocks, fabrication technology of hexagonal BDD quantum circuits up to 8-bit adder...

  4. Assessing Design Activity in Complex CMOS Circuit Design.

    Science.gov (United States)

    Biswas, Gautam; And Others

    This report characterizes human problem solving in digital circuit design. Protocols of 11 different designers with varying degrees of training were analyzed by identifying the designers' problem solving strategies and discussing activity patterns that differentiate the designers. These methods are proposed as a tentative basis for assessing…

  5. Automated Design of Quantum Circuits

    Science.gov (United States)

    Williams, Colin P.; Gray, Alexander G.

    2000-01-01

    In order to design a quantum circuit that performs a desired quantum computation, it is necessary to find a decomposition of the unitary matrix that represents that computation in terms of a sequence of quantum gate operations. To date, such designs have either been found by hand or by exhaustive enumeration of all possible circuit topologies. In this paper we propose an automated approach to quantum circuit design using search heuristics based on principles abstracted from evolutionary genetics, i.e. using a genetic programming algorithm adapted specially for this problem. We demonstrate the method on the task of discovering quantum circuit designs for quantum teleportation. We show that to find a given known circuit design (one which was hand-crafted by a human), the method considers roughly an order of magnitude fewer designs than naive enumeration. In addition, the method finds novel circuit designs superior to those previously known.

  6. Recursive Optimization of Digital Circuits

    Science.gov (United States)

    1990-12-14

    capability will become increasingly important as the application-specific integrated circuit (ASIC) market continues to meet its rapid growth projections... market (ASIC) continues to grow (18). The recursive optimization system presented in this thesis was developed to inves- tigate a new approach to global...f)) (narg (bar arg)) (fO (divide f narg)) (f1 (divide f arg)) (gO (divide g narg)) (gi (divide g arg)) ( productO (mult fO gO)) (producti (mult fl gl

  7. Advances in Analog Circuit Design 2015

    CERN Document Server

    Baschirotto, Andrea; Harpe, Pieter

    2016-01-01

    This book is based on the 18 tutorials presented during the 24th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of efficient sensor interfaces and low-power RF systems. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development. ·         Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; ·         Presents material in a tutorial-based format; ·         Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing.

  8. Inverter-based circuit design techniques for low supply voltages

    CERN Document Server

    Palani, Rakesh Kumar

    2017-01-01

    This book describes intuitive analog design approaches using digital inverters, providing filter architectures and circuit techniques enabling high performance analog circuit design. The authors provide process, supply voltage and temperature (PVT) variation-tolerant design techniques for inverter based circuits. They also discuss various analog design techniques for lower technology nodes and lower power supply, which can be used for designing high performance systems-on-chip.    .

  9. Design of digital circuits using inverse-mode cascode SiGe HBTs for single event upset mitigation.

    Energy Technology Data Exchange (ETDEWEB)

    Thrivikraman, Tushar K. (Georgia Institute of Technology, Atlanta, GA); Phillips, Stanley D. (Georgia Institute of Technology, Atlanta, GA); Dodd, Paul Emerson; Cressler, John D. (Georgia Institute of Technology, Atlanta, GA); Marshall, Paul W. (Consultant to NASA, Brookneal, VA); Vizkelethy, Gyorgy; Marshall, Cheryl (NASA Goddard Space Flight Center, Greenbelt, MD); Wilcox, Edward (Georgia Institute of Technology, Atlanta, GA)

    2010-07-01

    We report on the design and measured results of a new SiGe HBT radiation hardening by design technique called the 'inverse-mode cascode' (IMC). A third-generation SiGe HBT IMC device was tested in a time resolved ion beam induced charge collection (TRIBICC) system, and was found to have over a 75% reduction in peak current transients with the use of an n-Tiedown on the IMC sub-collector node. Digital shift registers in a 1st-generation SiGe HBT technology were designed and measured under a heavy-ion beam, and shown to increase the LET threshold over standard npn only shift registers. Using the CREME96 tool, the expected orbital bit-errors/day were simulated to be approximately 70% lower with the IMC shift register. These measured results help demonstrate the efficacy of using the IMC device as a low-cost means for improving the SEE radiation hardness of SiGe HBT technology without increasing area or power.

  10. 基于数字集成电路流水灯的设计%Design of Water Lights Based on Digital Integrated Circuit

    Institute of Scientific and Technical Information of China (English)

    卢翠珍

    2011-01-01

    In order to make the low cost, clean and pollution-free LED lamps widely applied in the fields of electronic product decoration, screen display advertisement, numerical code and character display, and energy saving lamps, the decoration with the LED lamps has become a fashion. In combition with decimal system counter/decoding circuit, the control method for digital integrated circuit is employed to design the control system of water lights. This system is composed of power source, clock circuit, counter and decoding display circuit. It can realize the random running water way. So long as the number and pattern of each group LED are changed, any running water pattern can be realized.%为了使造价低廉、清洁无污染的LED灯在电子产品装饰、显示屏电子广告、数码与字符显示、节能灯等领域得到广泛的应用,采用LED灯来作装饰已成为一种时尚.采用数字集成电路的控制方法,结合十进制计数器/译码电路设计了该控制系统.该系统由电源、时钟电路、计数器和译码显示电路4部分组成.能实现任意方式的流水,只要改变每路发光二极管的数目和图案,就可以实现随心所欲的流水花样.它可作为工作状态指示,具有环保、节能等特点.

  11. Designing Low Power Circuits: A Review

    Directory of Open Access Journals (Sweden)

    Rohan M Joshi

    2012-09-01

    Full Text Available The growing market of battery-operated portable applications like laptop, mobile etc requires microelectronic devices with low power consumption. As transistor size continues to shrink and as need for more complex chips increases, power management of the chip is one of the key challenges in VLSI industry. The manufacturers are looking for low power designs because providing adequate cooling and packaging increases the cost and limits the functionality of the device. This paper surveys the optimization techniques used to reduce power consumption in CMOS at all the levels of the design flow. It includes the technology used to implement digital circuits, the circuit design style and topology, the architecture for implementing the circuits, and at the highest level the software and algorithms that are implemented.

  12. High speed sampling circuit design for pulse laser ranging

    Science.gov (United States)

    Qian, Rui-hai; Gao, Xuan-yi; Zhang, Yan-mei; Li, Huan; Guo, Hai-chao; Guo, Xiao-kang; He, Shi-jie

    2016-10-01

    In recent years, with the rapid development of digital chip, high speed sampling rate analog to digital conversion chip can be used to sample narrow laser pulse echo. Moreover, high speed processor is widely applied to achieve digital laser echo signal processing algorithm. The development of digital chip greatly improved the laser ranging detection accuracy. High speed sampling and processing circuit used in the laser ranging detection system has gradually been a research hotspot. In this paper, a pulse laser echo data logging and digital signal processing circuit system is studied based on the high speed sampling. This circuit consists of two parts: the pulse laser echo data processing circuit and the data transmission circuit. The pulse laser echo data processing circuit includes a laser diode, a laser detector and a high sample rate data logging circuit. The data transmission circuit receives the processed data from the pulse laser echo data processing circuit. The sample data is transmitted to the computer through USB2.0 interface. Finally, a PC interface is designed using C# language, in which the sampling laser pulse echo signal is demonstrated and the processed laser pulse is plotted. Finally, the laser ranging experiment is carried out to test the pulse laser echo data logging and digital signal processing circuit system. The experiment result demonstrates that the laser ranging hardware system achieved high speed data logging, high speed processing and high speed sampling data transmission.

  13. Circuit design on plastic foils

    CERN Document Server

    Raiteri, Daniele; Roermund, Arthur H M

    2015-01-01

    This book illustrates a variety of circuit designs on plastic foils and provides all the information needed to undertake successful designs in large-area electronics.  The authors demonstrate architectural, circuit, layout, and device solutions and explain the reasons and the creative process behind each. Readers will learn how to keep under control large-area technologies and achieve robust, reliable circuit designs that can face the challenges imposed by low-cost low-temperature high-throughput manufacturing.   • Discusses implications of problems associated with large-area electronics and compares them to standard silicon; • Provides the basis for understanding physics and modeling of disordered material; • Includes guidelines to quickly setup the basic CAD tools enabling efficient and reliable designs; • Illustrates practical solutions to cope with hard/soft faults, variability, mismatch, aging and bias stress at architecture, circuit, layout, and device levels.

  14. Logic Circuit Design Selected Methods

    CERN Document Server

    Vingron, Shimon P

    2012-01-01

        In three main divisions the  book covers combinational circuits, latches, and asynchronous sequential circuits. Combinational circuits have  no memorising ability, while sequential circuits have such an ability to various degrees. Latches are the simplest sequential circuits, ones with the shortest memory. The presentation is decidedly non-standard.         The design of combinational circuits is discussed in an orthodox manner using normal forms and in an unorthodox manner using set-theoretical evaluation formulas relying heavily on Karnaugh maps. The latter approach allows for a new design technique called composition.          Latches are covered very extensively. Their memory functions are expressed mathematically in a time-independent manner allowing the use of (normal, non-temporal) Boolean logic in their calculation. The theory of latches is then used as the basis for calculating asynchronous circuits.         Asynchronous circuits are specified in a tree-representation, eac...

  15. 数字调制器载波产生电路的FPGA设计%Design of Digital Modulator Carrier Producing Circuit Based on FPGA

    Institute of Scientific and Technical Information of China (English)

    雷能芳

    2011-01-01

    The common approach to implement Digital Modulator Carrier producing circuit on FPGA is based on a lookup table, which requires a huge volume of ROM to achieve high resolution. This paper porposes a pipelined architecture for implementation of digital modulator carrier on FPGA, which, based on CORDIC algorithm, can save considerable hardware resources and improve the speed performance as well. The system was implemented in EP1C12Q240C8, and the hardware practical test was done by embedded logic analyzer SignalTap Ⅱ of Quartus Ⅱ. The correctness and feasibility of this design is verified by practical test result.%数字调制器载波产生电路的FPGA实现通常都是基于查找表的方法,为了达到高精度要求,需要耗费大量的ROM资源去建立庞大的查找表.文中提出了一种基于流水线CORDIC算法的实现方案,可有效地节省FPGA的硬件资源,提高运算速度.电路在FPGA芯片EPIC12Q240C8上实现,并通过QuartusⅡ嵌入式逻辑分析仪SignalTapⅡ对硬件进行了实时测试,测试结果验证了设计的正确性及可行性.

  16. Simplified design of filter circuits

    CERN Document Server

    Lenk, John

    1999-01-01

    Simplified Design of Filter Circuits, the eighth book in this popular series, is a step-by-step guide to designing filters using off-the-shelf ICs. The book starts with the basic operating principles of filters and common applications, then moves on to describe how to design circuits by using and modifying chips available on the market today. Lenk's emphasis is on practical, simplified approaches to solving design problems.Contains practical designs using off-the-shelf ICsStraightforward, no-nonsense approachHighly illustrated with manufacturer's data sheets

  17. Inter Digital Transducer Modelling through Mason Equivalent Circuit Model

    DEFF Research Database (Denmark)

    Mishra, Dipti; Singh, Abhishek; Hussain, Dil muhammed Akbar

    2016-01-01

    The frequency reliance of inter-digital transducer is analyzed with the help of MASON’s Equivalent circuit which is based on Smith’s Equivalent circuit which is further based on Foster’sNetwork. An inter-digital transducer has been demonstratedas a RLC network. The circuit is simulated by Simulat...

  18. Inter digital transducer modelling through Mason equivalent circuit model

    DEFF Research Database (Denmark)

    Mishra, Dipti; Singh, Abhishek; Hussain, Dil muhammed Akbar

    2016-01-01

    The frequency reliance of inter-digital transducer is analyzed with the help of MASON's Equivalent circuit which is based on Smith's Equivalent circuit which is further based on Foster's Network. An inter-digital transducer has been demonstrated as a RLC network. The circuit is simulated by Simul...

  19. 由C++到Verilog实现数字逻辑设计的方法%Design Method for Digital Logic Circuits from C ++ to Verilog

    Institute of Scientific and Technical Information of China (English)

    孟祥鹤; 吕楠; 韩路; 吴春瑜; 王绩伟; 梁洁

    2011-01-01

    A mode for designing the digital logic circuit through C ++ language matching with Verilog HDL was introduced. Base on this, a brand-new method of designing logic circuit from C ++ to Verilog was presented. This method starts from the system design ( virtual machine) and used C ++ to build the required system model. Then, the software design is accurately translated into a hardware level by Verilog and C ++ consistency. So the logical design upwards can undertake joint simulation by software and hardware, and downwards can realize physical level outspread. This method can effectively avoid logic inconsistency when the SOC design is translated from system design to physical design. Some contrastive analyses about the difference of two languages were given after some language characteristics of C ++ were formulated. Then translation way was given between C ++ and Verilog HDL. Besides, the example of DSP designing was provided which can perform application of this method directly. Finally,the system description was verified by comparing the simulation data of C ++ and Verilog.%通过介绍C++语言配合Verilog HDL来进行数字逻辑设计的模式,提出了一种由C++到Verilog来实现逻辑设计的崭新方法.此方法从系统设计(虚拟机)入手,用C++来搭建所需要的系统模型,再由Verilog与C++的一致性转化,将软件设计精确地转化到硬件级上,使得逻辑设计向上可进行软硬件的联合仿真,向下能够实现物理级延伸.通过该方法可有效地避免SOC设计中从系统到物理实现在转化过程中产生的逻辑不一致.在简叙C++的语言特性后,将Verilog与C++进行了对比分析,给出了两种语言之间进行转化设计的实现方式.结合数字信号处理器的设计,对此方法进行了设计应用,最终通过比对C++与Verilog两者的仿真数据文件,对两种层次系统描述进行了测试验证.

  20. Digital hydraulic valving system. [design and development

    Science.gov (United States)

    1973-01-01

    The design and development are reported of a digital hydraulic valving system that would accept direct digital inputs. Topics include: summary of contractual accomplishments, design and function description, valve parameters and calculations, conclusions, and recommendations. The electrical control circuit operating procedure is outlined in an appendix.

  1. Design in the digital textbook

    DEFF Research Database (Denmark)

    Ebbesen, Toke Riis

    reorganization of the publishing company, web based user interfaces, and ultimately the branding, that market these new digital objects, are building powerful discourses around the product. Thus it is suggested that the design process of the iBog-case can be understood in a model of database-based publishing......Building on a preliminary case study of the Danish educational publisher, Systime A/S, and its flagship product, the web based ‘iBog’ {Systime 2014}, this paper explores how digital textbooks can be understood as design. The shaping of digital books is seen as intertwined in a wider circuit...... with multiple levels. In the final analysis, the iBog is much more than a product and a technology. It is a brand that goes beyond what can be studied by looking at the digital textbook as a singular artefact....

  2. Transistor Level Implementation of Digital Reversible Circuits

    Directory of Open Access Journals (Sweden)

    K.Prudhvi Raj

    2015-12-01

    Full Text Available Now a days each and every electronic gadget is desi gning smartly and provides number of applications, so these designs dissipate high amount of power. Rever sible logic is becoming one of the best emerging de sign technologies having its applications in low power C MOS, Quantum computing and Nanotechnology. Reversible logic plays an important role in the des ign of energy efficient circuits. Adders and subtra ctors are the essential blocks of the computing systems. In this paper, reversible gates and circuits are de signed and implemented in CMOS and pass transistor logic u sing Mentor graphics backend tools. A four-bit ripp le carry adder/subtractor and an eight-bit reversible Carry Skip Adder are implemented and compared with the conventional circuits

  3. 23rd workshop on Advances in Analog Circuit Design

    CERN Document Server

    Baschirotto, Andrea; Makinwa, Kofi

    2015-01-01

    This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design.  Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.    • Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing; • Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; • Presents material in a tutorial-based format.

  4. Control circuits in power electronics practical issues in design and implementation

    CERN Document Server

    Castilla, Miguel

    2016-01-01

    Control circuits are a key element in the operation and performance of power electronics converters. This book describes practical issues related to the design and implementation of these control circuits, and is divided into three parts - analogue control circuits, digital control circuits, and new trends in control circuits.

  5. Methodology for the digital calibration of analog circuits and systems with case studies

    CERN Document Server

    Pastre, Marc

    2006-01-01

    Methodology for the Digital Calibration of Analog Circuits and Systems shows how to relax the extreme design constraints in analog circuits, allowing the realization of high-precision systems even with low-performance components. A complete methodology is proposed, and three applications are detailed. To start with, an in-depth analysis of existing compensation techniques for analog circuit imperfections is carried out. The M/2+M sub-binary digital-to-analog converter is thoroughly studied, and the use of this very low-area circuit in conjunction with a successive approximations algorithm for digital compensation is described. A complete methodology based on this compensation circuit and algorithm is then proposed. The detection and correction of analog circuit imperfections is studied, and a simulation tool allowing the transparent simulation of analog circuits with automatic compensation blocks is introduced. The first application shows how the sub-binary M/2+M structure can be employed as a conventional di...

  6. Digital Integrated Circuit Design of Urban Traffic Light%城市交通信号灯的数字集成电路设计

    Institute of Scientific and Technical Information of China (English)

    尹凡; 潘洁

    2016-01-01

    随着城市的发展,城市的交通枢纽问题越来越引起人们的关注。在道路交通形势日益紧张的城市道路系统中,如何利用现有道路交通系统对人、车、路三者的通行结构进行调配,是当前交通管理系统亟需解决的问题。本文阐述了城市交通控制系统中最关键的控制系统———交通灯控制系统的工作原理,提出了一种简单实用的基于数字集成电路的设计方法。%With the development of the city, the transportation hub of the city gets more and more attention. In the urban road system of the road traffic situation, how to allocate the traffic structure of people, vehicles and road by the existing road traffic system is an urgent problem to be solved in the current traffic management system. This paper describes the most critical control system in the urban traffic control system: the principle of traffic lights control system and puts forward a simple and practical design method based on digital integrated circuits.

  7. Digitally Programmable Analogue Circuits for Sensor Conditioning Systems

    Science.gov (United States)

    Zatorre, Guillermo; Medrano, Nicolás; Sanz, María Teresa; Aldea, Concepción; Calvo, Belén; Celma, Santiago

    2009-01-01

    This work presents two current-mode integrated circuits designed for sensor signal preprocessing in embedded systems. The proposed circuits have been designed to provide good signal transfer and fulfill their function, while minimizing the load effects due to building complex conditioning architectures. The processing architecture based on the proposed building blocks can be reconfigured through digital programmability. Thus, sensor useful range can be expanded, changes in the sensor operation can be compensated for and furthermore, undesirable effects such as device mismatching and undesired physical magnitudes sensor sensibilities are reduced. The circuits were integrated using a 0.35 μm standard CMOS process. Experimental measurements, load effects and a study of two different tuning strategies are presented. From these results, system performance is tested in an application which entails extending the linear range of a magneto-resistive sensor. Circuit area, average power consumption and programmability features allow these circuits to be included in embedded sensing systems as a part of the analogue conditioning components. PMID:22412331

  8. Digitally programmable analogue circuits for sensor conditioning systems.

    Science.gov (United States)

    Zatorre, Guillermo; Medrano, Nicolás; Sanz, María Teresa; Aldea, Concepción; Calvo, Belén; Celma, Santiago

    2009-01-01

    This work presents two current-mode integrated circuits designed for sensor signal preprocessing in embedded systems. The proposed circuits have been designed to provide good signal transfer and fulfill their function, while minimizing the load effects due to building complex conditioning architectures. The processing architecture based on the proposed building blocks can be reconfigured through digital programmability. Thus, sensor useful range can be expanded, changes in the sensor operation can be compensated for and furthermore, undesirable effects such as device mismatching and undesired physical magnitudes sensor sensibilities are reduced. The circuits were integrated using a 0.35 μm standard CMOS process. Experimental measurements, load effects and a study of two different tuning strategies are presented. From these results, system performance is tested in an application which entails extending the linear range of a magneto-resistive sensor. Circuit area, average power consumption and programmability features allow these circuits to be included in embedded sensing systems as a part of the analogue conditioning components.

  9. Digitally Programmable Analogue Circuits for Sensor Conditioning Systems

    Directory of Open Access Journals (Sweden)

    Santiago Celma

    2009-05-01

    Full Text Available This work presents two current-mode integrated circuits designed for sensor signal preprocessing in embedded systems. The proposed circuits have been designed to provide good signal transfer and fulfill their function, while minimizing the load effects due to building complex conditioning architectures. The processing architecture based on the proposed building blocks can be reconfigured through digital programmability. Thus, sensor useful range can be expanded, changes in the sensor operation can be compensated for and furthermore, undesirable effects such as device mismatching and undesired physical magnitudes sensor sensibilities are reduced. The circuits were integrated using a 0.35 mm standard CMOS process. Experimental measurements, load effects and a study of two different tuning strategies are presented. From these results, system performance is tested in an application which entails extending the linear range of a magneto-resistive sensor. Circuit area, average power consumption and programmability features allow these circuits to be included in embedded sensing systems as a part of the analogue conditioning components.

  10. Radio frequency integrated circuit design

    CERN Document Server

    Rogers, John W M

    2010-01-01

    This newly revised and expanded edition of the 2003 Artech House classic, Radio Frequency Integrated Circuit Design, serves as an up-to-date, practical reference for complete RFIC know-how. The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results. By emphasizing working designs, this book practically transports you into the authors' own RFIC lab so you can fully understand the function of each design detailed in this book. Among the RFIC designs examined are RF integrated LC

  11. Logic designer's handbook circuits and systems

    CERN Document Server

    Parr, E A

    2013-01-01

    Easy-to-read, but nonetheless thorough, this book on digital circuits is for use by students and engineers, and is a readily accessible source of data on devices in the TTL and CMOS families. The book is written to be used as a Designer's Handbook and will spend its days on the designer's bench rather than their bookshelf. The basic theory is explained and then supported with specific practical examples.* Revised, enlarged, reduced price edition * Easy-to-read, jargon free book suitable for professionals and students * Plenty of basic theory and practical information * Based on authors practi

  12. Foundations for microstrip circuit design

    CERN Document Server

    Edwards, Terry

    2016-01-01

    Building on the success of the previous three editions, Foundations for Microstrip Circuit Design offers extensive new, updated and revised material based upon the latest research. Strongly design-oriented, this fourth edition provides the reader with a fundamental understanding of this fast expanding field making it a definitive source for professional engineers and researchers and an indispensable reference for senior students in electronic engineering. Topics new to this edition: microwave substrates, multilayer transmission line structures, modern EM tools and techniques, microstrip and planar transmision line design, transmission line theory, substrates for planar transmission lines, Vias, wirebonds, 3D integrated interposer structures, computer-aided design, microstrip and power-dependent effects, circuit models, microwave network analysis, microstrip passive elements, and slotline design fundamentals.

  13. Wavy Channel TFT-Based Digital Circuits

    KAUST Repository

    Hanna, Amir

    2016-02-23

    We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.

  14. Performance analysis of a digital capacitance measuring circuit.

    Science.gov (United States)

    Xu, Lijun; Sun, Shijie; Cao, Zhang; Yang, Wuqiang

    2015-05-01

    This paper presents the design and study of a digital capacitance measuring circuit with theoretical analysis, numerical simulation, and experimental evaluation. The static and dynamic performances of the capacitance measuring circuit are first defined, including signal-to-noise ratio (SNR), standard deviation, accuracy, linearity, sensitivity, and response time, within a given measurement range. Then numerical simulation is carried out to analyze the SNR and standard deviation of the circuit, followed by experiments to validate the overall performance of the circuit. The simulation results show that when the standard deviation of noise is 0.08 mV and the measured capacitance decreases from 6 pF to 3 fF, the SNR decreases from 90 dB to 22 dB and the standard deviation is between 0.17 fF and 0.24 fF. The experimental results show that when the measured capacitance decreases from 6 pF to 40 fF and the data sampled in a single period are used for demodulation, the SNR decreases from 88 dB to 40 dB and the standard deviation is between 0.18 fF and 0.25 fF. The maximum absolute error and relative error are 5.12 fF and 1.26%, respectively. The SNR and standard deviation can be further improved if the data sampled in more than one period are used for demodulation by the circuit.

  15. Design and implementation of a hybrid circuit system for micro sensor signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Wang Zhuping; Chen Jing; Liu Ruqing, E-mail: wangzhuping169@163.com [School of Information and Electronics, Beijing Institute of Technology, Beijing 100081 (China)

    2011-04-15

    This paper covers a micro sensor analog signal processing circuit system (MASPS) chip with low power and a digital signal processing circuit board implementation including hardware connection and software design. Attention has been paid to incorporate the MASPS chip into the digital circuit board. The ultimate aim is to form a hybrid circuit used for mixed-signal processing, which can be applied to a micro sensor flow monitoring system. (semiconductor integrated circuits)

  16. Design infrastructure for Rapid Single Flux Quantum circuits

    Science.gov (United States)

    Toepfer, Hannes; Ortlepp, Thomas

    2009-11-01

    Cryoelectronic integrated circuits based on Rapid Single Flux Quantum (RSFQ) technology are promising candidates for realizing systems exhibiting very high performance in combination with very low-power consumption. Like other superconductive logic circuits, they are characterized by a high switching speed. Their unique feature consists in the particular representation of binary information by means of short transient voltage pulses. The development of RSFQ circuits and systems requires a comprehensive design approach, supported by appropriate tools. Within the recent years, a dedicated design infrastructure has been developed in Europe in close association with a foundry for digital RSFQ integrated circuits. As a result, RSFQ technology has matured to such a level that engineering efforts enable the development of integrated circuits. In the contribution, the basic features of the RSFQ circuit design are addressed within the context of technical and infrastructural issues of implementation from a European perspective.

  17. Designing Asynchronous Circuits for Low Power: An IFIR Filter

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Sparsø, Jens

    1999-01-01

    by numerically small samples). Apart from the improved RAM design, these measures are only viable in an asynchronous design. The principles and techniques explained in this paper are of a general nature, and they apply to the design of asynchronous low-power digital signal-processing circuits in a broader...

  18. Printed Circuit Board Design with HDL Designer

    Science.gov (United States)

    Winkert, Thomas K.; LaFourcade, Teresa

    2004-01-01

    Staying up to date with the latest CAD tools both from a cost and time perspective is difficult. Within a given organization there may be experts in Printed Circuit Board Design tools and experts in FPGA/VHDL tools. Wouldn't it be great to have someone familiar with HDL Designer be able to design PCBs without having to learn another tool? This paper describes a limited experiment to do this.

  19. Inter Digital Transducer Modelling through Mason Equivalent Circuit Model

    DEFF Research Database (Denmark)

    Mishra, Dipti; Singh, Abhishek; Hussain, Dil muhammed Akbar

    2016-01-01

    by Simulation program with Integrated Circuit Emphasis (HSPICE), a well-liked electronic path simulator. The acoustic wave devices are not suitable to simulation through circuit simulator.In this paper, an electrical model of Mason’s Equivalent electricalcircuit for an inter-digital transducer (IDT......The frequency reliance of inter-digital transducer is analyzed with the help of MASON’s Equivalent circuit which is based on Smith’s Equivalent circuit which is further based on Foster’sNetwork. An inter-digital transducer has been demonstratedas a RLC network. The circuit is simulated......) is projected which is well-suitedwith a broadlycast-offuniversalresolution circuit simulator SPICE built-in out with the proficiency to simulatethenegative capacitances and inductances. The investigationis done to prove the straightforwardness of establishing the frequency and time domain physical...

  20. Improved digital thermometer design.

    Science.gov (United States)

    Swift, C S

    1981-01-01

    A simple digital thermometer design using a self-contained 3 1/2 digit LCD meter module is presented. The Celsius-reading (Centigrade) thermometer is powered by a single 9-V battery, has very low power drain, and uses an inexpensive NPN silicon transistor for the temperature sensor. A short bibliography on temperature measurement instrumentation is included.

  1. A new pixel level digital read out integrated circuits for ultraviolet imaging sensors

    Science.gov (United States)

    Xu, Bin; Lan, Tian-yi; Yuan, Yong-gang; Li, Xiang-yang

    2014-11-01

    The ultraviolet imaging sensors consist of two important parts: the array of detectors and the read out integrated circuits. Along with the demand for the fine resolution, large input dynamic range and high integration degree of the imaging sensors, the functions of read out integrated circuits are becoming more and more important. The on chip analog to digital conversion is the main directions of research on this area. In this paper, we presented a new digital read out integrated circuits for ultraviolet imaging sensors. The proposed circuits have an analog to digital converter in each pixel, which enable the parallel analog to digital conversion of the whole pixel array. The developed circuits have a 50um×50um pixel area with a 128×128 size, and are designed in a 0.35um four metal double poly mixed signal CMOS process. The simulation results show that the designed analog to digital converter has an accuracy of 0.2mV and can achieve the dynamic range of 88dB. The proposed circuits realize the low noise and high speed digital output of read out integrated circuits for ultraviolet imaging sensors.

  2. Nanoelectronic circuit design and test

    Science.gov (United States)

    Simsir, Muzaffer Orkun

    Controlling power consumption in CMOS integrated circuits (ICs) during normal mode of operation is becoming one of the limiting factors to further scaling. In addition, it is a well known fact that during testing of a complex IC, power consumption can far exceed the values reached during its normal operation. High power consumption, combined with limited cooling support, leads to overheating of ICs. This can cause permanent damage to the chip or can invalidate test results due to the fact that extreme temperature variations lead to changes in path delays. Therefore, even good chips can fail the test. For these reasons, thermal problems during test need to be identified to prevent the loss of yield in CMOS ICs. In this thesis, we propose a methodology for thermally characterizing circuits under test. Using this methodology, it is possible to simulate the thermal profiles of the chips during test and prevent possible yield loss because of thermal problems. In addition to the problems associated with power and temperature, a more important barrier is the scaling limitations of the CMOS technology. It has been predicted that in next decade, it will not be possible to scale it further. In the near future, rather than a transition to a completely new technology, extensions to CMOS seem to be more realistic. Double-gate CMOS technology is one of the most promising alternatives that offers a simple extension to CMOS. The transistors of this technology are formed by adding a second gate across the conventional CMOS transistor gate. Designing circuits using this technology has attracted a lot of attention. However, as circuit design methods mature, there is a need to identify how these circuits can be tested. From a circuit testing viewpoint, it is unclear if CMOS fault models are comprehensive enough to model all defects in double-gate CMOS circuits. Therefore, fault models of this technology need to be defined to enable manufacturing-time testing. In this thesis, we

  3. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    Science.gov (United States)

    Clark, Lawrence T.; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  4. Variation-aware adaptive voltage scaling for digital CMOS circuits

    CERN Document Server

    Wirnshofer, Martin

    2013-01-01

    Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted “on the fly” by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engine...

  5. Digital computer structure and design

    CERN Document Server

    Townsend, R

    2014-01-01

    Digital Computer Structure and Design, Second Edition discusses switching theory, counters, sequential circuits, number representation, and arithmetic functions The book also describes computer memories, the processor, data flow system of the processor, the processor control system, and the input-output system. Switching theory, which is purely a mathematical concept, centers on the properties of interconnected networks of ""gates."" The theory deals with binary functions of 1 and 0 which can change instantaneously from one to the other without intermediate values. The binary number system is

  6. 用于生物医学成像的多通道流水线数字化电路设计%Design of Multi-channel Pipeline Digitization Circuit for Biomedical Imaging

    Institute of Scientific and Technical Information of China (English)

    卢双第; 高德远; 魏廷存; 高武; 曾蕙明; 高原

    2012-01-01

    针对生物医学成像中前端读出电路多通道以及要求高速数字化的特点,设计了一个16通道的流水线数字化电路.整个电路由模拟多路选择器、单端转差分电路、8-bit 25Ms/s 1.5bit/stage流水线ADC以及数据输出模块组成.模数转换和数据输出在两相邻时间窗口内采用流水线方式进行.电路采用TSMC 0.18μm mixed signalCMOS工艺实现.电路仿真结果表明,流水线ADC的DNL为-0.62/0.67LSB,INL为-0.39/0.72LSB,SNR为45.99dB,ENOB为6.03bit,该电路能够在两个相邻时间窗口内完成16通道的信号数字化并输出,满足系统设计要求.%Based on the multi-channel and high-speed digitization features of front-end readout circuits for biomedical imaging,a 16-channel pipeline digitization circuits is designed.The whole circuits consist of analog multiplexer,single end to differential signal conversion circuit,8-bit 25-Msample/s pipeline ADC,and data output module.Analog-to-digital conversion and data output will be executed in the pipeline way.The circuit is designed in TSMC 0.18 μm mixed signal CMOS technology.Simulation results show that,pipeline ADC has-0.62/0.67 LSB DNL,-0.39/0.72 LSB INL,45.99 dB SNR,and 6.03 bit ENOB.The designed circuits can accomplish the digitization and output of 16-channel analog signals within two adjacent timing windows,satisfying the performance requirements of the system.

  7. A Novel Design Of An NTC Thermistor Linearization Circuit

    Directory of Open Access Journals (Sweden)

    Lukić Jelena

    2015-09-01

    Full Text Available A novel design of a circuit used for NTC thermistor linearization is proposed. The novelty of the proposed design consists in a specific combination of two linearization circuits, a serial-parallel resistive voltage divider and a two-stage piecewise linear analog-to-digital converter. At the output of the first linearization circuit the quasi-linear voltage is obtained. To remove the residual voltage nonlinearity, the second linearization circuit, i.e., a two-stage piecewise linear analog-to-digital converter is employed. This circuit is composed of two flash analog-to-digital converters. The first analog-to-digital converter is piecewise linear and it is actually performing the linearization, while the second analog-to-digital converter is linear and it is performing the reduction of the quantization error introduced by the first converter. After the linearization is performed, the maximal absolute value of a difference between the measured and real temperatures is 0.014°C for the temperature range between −25 and 75°C, and 0.001°C for the temperature range between 10 and 40°C.

  8. Synthetic analog and digital circuits for cellular computation and memory

    OpenAIRE

    Purcell, Oliver; Lu, Timothy K.

    2014-01-01

    Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss r...

  9. Design and implementation of a hybrid circuit system for micro sensor signal processing*

    Institute of Scientific and Technical Information of China (English)

    Wang Zhuping; Chen Jing; Liu Ruqing

    2011-01-01

    This paper covers a micro sensor analog signal processing circuit system (MASPS) chip with low power and a digital signal processing circuit board implementation including hardware connection and software design.Attention has been paid to incorporate the MASPS chip into the digital circuit board. The ultimate aim is to form a hybrid circuit used for mixed-signal processing, which can be applied to a micro sensor flow monitoring system.

  10. Analog approach to mixed analog-digital circuit simulation

    Science.gov (United States)

    Ogrodzki, Jan

    2013-10-01

    Logic simulation of digital circuits is a well explored research area. Most up-to-date CAD tools for digital circuits simulation use an event driven, selective trace algorithm and Hardware Description Languages (HDL), e.g. the VHDL. This techniques enable simulation of mixed circuits, as well, where an analog part is connected to the digital one through D/A and A/D converters. The event-driven mixed simulation applies a unified, digital-circuits dedicated method to both digital and analog subsystems. In recent years HDL techniques have been also applied to mixed domains, as e.g. in the VHDL-AMS. This paper presents an approach dual to the event-driven one, where an analog part together with a digital one and with converters is treated as the analog subsystem and is simulated by means of circuit simulation techniques. In our problem an analog solver used yields some numerical problems caused by nonlinearities of digital elements. Efficient methods for overriding these difficulties have been proposed.

  11. Molectronics: a circuit design perspective

    Science.gov (United States)

    Nackashi, David P.; Franzon, Paul D.

    2001-03-01

    Recently, several mechanisms have been proposed as a basis for designing molecular electronic logic switching elements. Many two terminal molecular devices functioning as diodes have been synthesized with responses similar to silicon devices such as rectifying and resonant tunneling diodes. In this paper, the feasibility of integrating these molecular diodes into current circuit architectures is explored. A series of logic gates and a memory element are simulated based on the voltage-controlled current flow method using the Tour-Reed molecular diode exhibiting negative differential resistance (NDR). HSPICE simulation results are used to illustrate the performance of these devices and to quantify additional component and interconnect requirements. Finally, future system design approaches using molecular components are discussed.

  12. The Immunity of Evolvable Digital Circuits to ESD Interference

    Institute of Scientific and Technical Information of China (English)

    Shanghe Liu; Menghua Man; Zhengquan Ju; Xiaolong Chang; Jie Chu; Liang Yuan

    2012-01-01

    With the rapid development of semiconductor technology and the increasing proliferation of emission sources,digital circuits are frequently used in harsh and hostile electromagnetic environments.Electrostatic Discharge (ESD) interferences are gradually gaining prominence,resulting in performance degradations,malfunctions and disturbances in component and/or system level applications.Conventional solutions to such problems are shielding,filtering and grounding.This paper proposes a novel Evolvable Digital Circuit (EDC) for intrinsic immunity.The key idea is motivated by the noise-robustness and fault-tolerance of the biological system.First,the architecture of the EDC is designed based on the cell structure.Then,ESD immunity tests are carried out on the most fragile element of the EDC in operation.Based on the results,fault models are also presented to simulate different functional disturbances.Finally,the immunity of the EDC is evaluated while it is exposed to a variety of simulated environments.The results which demonstrate a graceful immunity to ESD interference are presented.

  13. Analog circuit design art, science, and personalities

    CERN Document Server

    Williams, Jim

    1991-01-01

    Analog Circuit Design: Art, Science, and Personalities discusses the many approaches and styles in the practice of analog circuit design. The book is written in an informal yet informative manner, making it easily understandable to those new in the field. The selection covers the definition, history, current practice, and future direction of analog design; the practice proper; and the styles in analog circuit design. The book also includes the problems usually encountered in analog circuit design; approach to feedback loop design; and other different techniques and applications. The text is

  14. The analysis and design of linear circuits

    CERN Document Server

    Thomas, Roland E; Toussaint, Gregory J

    2009-01-01

    The Analysis and Design of Linear Circuits, 6e gives the reader the opportunity to not only analyze, but also design and evaluate linear circuits as early as possible. The text's abundance of problems, applications, pedagogical tools, and realistic examples helps engineers develop the skills needed to solve problems, design practical alternatives, and choose the best design from several competing solutions. Engineers searching for an accessible introduction to resistance circuits will benefit from this book that emphasizes the early development of engineering judgment.

  15. Innovative devices for integrated circuits - A design perspective

    Science.gov (United States)

    Schmitt-Landsiedel, D.; Werner, C.

    2009-04-01

    MOS devices go 3D, new quantum effect devices appear in the research labs. This paper discusses the impact of various innovative device architectures on circuit design. Examples of circuits with FinFETs or Multi-Gate-FETs are shown and their performance is compared with classically scaled CMOS circuits both for digital and analog applications. As an example for novel quantum effect devices beyond CMOS we discuss circuits with Tunneling Field Effect Transistors and their combination with classical MOSFETs and MuGFETs. Finally the potential of more substantial paradigm changes in circuit design will be exploited for the example of magnetic quantum cellular automata using a novel integrated magnetic field clocking scheme.

  16. Automatic ranging circuit for a digital panel meter

    Science.gov (United States)

    Mueller, Theodore R.; Ross, Harley H.

    1976-01-01

    This invention relates to a range changing circuit that operates in conjunction with a digital panel meter of fixed sensitivity. The circuit decodes the output of the panel meter and uses that information to change the gain of an input amplifier to the panel meter in order to insure that the maximum number of significant figures is always displayed in the meter. The circuit monitors five conditions in the meter and responds to any of four combinations of these conditions by means of logic elements to carry out the function of the circuit.

  17. 76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...

    Science.gov (United States)

    2011-09-19

    ... COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice... certain digital televisions containing integrated circuit devices and components thereof by reason of... the sale within the United States after importation of certain digital televisions containing...

  18. 关于数字电子电路设计之中EDA技术的应用探究%Application Exploration of the digital electronic circuit design into the EDA technology

    Institute of Scientific and Technical Information of China (English)

    李如发

    2016-01-01

    Vocational electrical specialty,the electronic circuit technology is an important professional courses.This course in addition to learning theory textbook knowledge, but more important is to have some of the skills test.This paper focuses on the application of inquiry into the digital electronic circuit design EDA technology.%中职电类专业中,电子电路技术是一门重要的专业课程.学习这门课程除了要学习课本上的理论知识外,更重要的是要掌握一些的实验操作技能.本文重点阐述了数字电子电路设计之中EDA技术的应用探究.

  19. Integrated circuits in digital electronics (2nd revised and enlarged edition)

    Science.gov (United States)

    Barna, Arpad; Porat, Dan I.

    This book provides a link between elementary logic design theory and its practical applications. New information on Schottky TTL, ECL, and CMOS is given, along with a study of number systems and a detailed description of the design of sequential logic with emphasis on counters and shift registers and a discussion of arithmetic circuits. A chapter on latches and flip-flops emphasizes the differences between these two storage elements. A summary of coding, code conversion, and error detection and correction is given along with descriptions of digital-to-analog and analog-to-digital converters. Up-to-date treatment of LSI and VLSI circuits is given, including static and dynamic circuits, RASMs, ROMs, PLSAs, associative memories, and gate arrays. There is also a unified presentation of practical considerations in digital equipment design.

  20. High accuracy digital aging monitor based on PLL-VCO circuit

    Science.gov (United States)

    Yuejun, Zhang; Zhidi, Jiang; Pengjun, Wang; Xuelong, Zhang

    2015-01-01

    As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm2. After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.

  1. Computer-Aided Pneumatic Circuit Design

    OpenAIRE

    TEKİNER, Zafer; KORKUT, İhsan

    2001-01-01

    In this study, a user-interactive computer program was developed for computer-aided pneumatic circuit design. The pneumatic circuit elements were selected and designed by the determination of the main principles that are in accordance with the aim the user is going to specify. A database was established by forming IGES files for pneumatic circuit elements. In addition to this database, lists displaying the connection nodes of each element were prepared. The coordinates will be conne...

  2. Design of analog circuits through symbolic analysis

    CERN Document Server

    Fakhfakh, Mourad; V Fernández, Francisco

    2012-01-01

    Symbolic analyzers have the potential to offer knowledge to sophomores as well as practitioners of analog circuit design. Actually, they are an essential complement to numerical simulators, since they provide insight into circuit behavior which numerical analyzers do not provide. Symbolic analysis of electronic circuits addresses the generation of symbolic expressions for the parameters that describe the performance of linear and nonlinear circuits in three domains: DC, AC and time; some or all the circuit parameters can be kept as symbols. Due to the fact that these expressions remain va

  3. Analog circuit design for communication SOC

    CERN Document Server

    Tu, Steve Hung-Lung

    2012-01-01

    This e-book provides several state-of-the-art analog circuit design techniques. It presents both empirical and theoretical materials for system-on-a-chip (SOC) circuit design. Fundamental communication concepts are used to explain a variety of topics including data conversion (ADC, DAC, S-? oversampling data converters), clock data recovery, phase-locked loops for system timing synthesis, supply voltage regulation, power amplifier design, and mixer design. This is an excellent reference book for both circuit designers and researchers who are interested in the field of design of analog communic

  4. An integrated energy-efficient capacitive sensor digital interface circuit

    KAUST Repository

    Omran, Hesham

    2014-06-19

    In this paper, we propose an energy-efficient 13-bit capacitive sensor interface circuit. The proposed design fully relies on successive approximation algorithm, which eliminates the need for oversampling and digital decimation filtering, and thus low-power consumption is achieved. The proposed architecture employs a charge amplifier stage to acheive parasitic insensitive operation and fine absolute resolution. Moreover, the output code is not affected by offset voltages or charge injection. The successive approximation algorithm is implemented in the capacitance-domain using a coarse-fine programmable capacitor array, which allows digitizing wide capacitance range in compact area. Analysis for the maximum achievable resolution due to mismatch is provided. The proposed design is insensitive to any reference voltage or current which translates to low temperature sensitivity. The operation of a prototype fabricated in a standard CMOS technology is experimentally verified using both on-chip and off-chip capacitive sensors. Compared to similar prior work, the fabricated prototype achieves and excellent energy efficiency of 34 pJ/step.

  5. An Undergraduate Design Experience in Digital Logic Design Course of Special Purpose Arithmetic Logic Unit Using Multisim, Ultiboard and Print Circuit Board

    Science.gov (United States)

    Al-Haija, Qasem Abu; Al-Amri, Hasan; Al-Nashri, Mohamed; Al-Muhaisen, Sultan

    2013-01-01

    Project-Based Curriculum (PBC) is considered one of the most powerful methods in the engineering education where each course or courses-cluster is assigned a design project which considers a series of inter-related concepts that have been shown theoretically for the students. Using this approach, the student will gain the required knowledge in an…

  6. Microelectronic circuit design for energy harvesting systems

    CERN Document Server

    Di Paolo Emilio, Maurizio

    2017-01-01

    This book describes the design of microelectronic circuits for energy harvesting, broadband energy conversion, new methods and technologies for energy conversion. The author also discusses the design of power management circuits and the implementation of voltage regulators. Coverage includes advanced methods in low and high power electronics, as well as principles of micro-scale design based on piezoelectric, electromagnetic and thermoelectric technologies with control and conditioning circuit design. Provides a single-source reference to energy harvesting and its applications; Serves as a practical guide to microelectronics design for energy harvesting, with application to mobile power supplies; Enables readers to develop energy harvesting systems for wearable/mobile electronics.

  7. Signal Digitizer and Cross-Correlation Application Specific Integrated Circuit

    Science.gov (United States)

    Baranauskas, Dalius (Inventor); Baranauskas, Gytis (Inventor); Zelenin, Denis (Inventor); Kangaslahti, Pekka (Inventor); Tanner, Alan B. (Inventor); Lim, Boon H. (Inventor)

    2017-01-01

    According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.

  8. Circuit design in organic semiconductor technologies

    NARCIS (Netherlands)

    Heremans, P.; Dehaene, W.; Steyaert, M.; Myny, K.; Mariën, H.; Genoe, J.; Gelinck, G.H.; Veenendaal, E. van

    2011-01-01

    In this paper, we review the state of the art of digital and analog circuits that have been shown in recent years in organic thin-film transistor technology on flexible plastic foil. The transistors are developed for backplanes of displays, and therefore have the characteristics to be unipolar and t

  9. Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

    Science.gov (United States)

    Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

    2012-10-21

    Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

  10. Digital Art and Design

    Directory of Open Access Journals (Sweden)

    Khaldoun A. A. BESOUL

    2006-07-01

    Full Text Available The desire to create unique things and give free rain to one's imagination served as a powerful impetus to the development of digital art and design software. The commoner was the use of computers the wider variety of professional software was developed. Nowadays the creators and computer designers are receiving more and more new and advanced programs that allow their ideas becoming virtual reality. This research paper looks at the history of the development of graphic editors from the simplest to the most modern and advanced. This brief survey includes the history of different graphic editors’ creation, their features and abilities. This paper highlights the two basic branches of graphic editors – these that are in free use and commercial graphic editors design software. The researcher selected the most powerful and influential graphic editors design software brands like Paint.NET and GIMP among free software and commercial Adobe Photoshop. This paper also dwells upon the way digital art transferred from the exclusively professional business into the hobby for ordinary users. This research paper bears implications for those who are interested in features and potentiality of most popular graphic editors design software.

  11. A guide to printed circuit board design

    CERN Document Server

    Hamilton, Charles

    1984-01-01

    A Guide to Printed Circuit Board Design discusses the basic design principles of printed circuit board (PCB). The book consists of nine chapters; each chapter provides both text discussion and illustration relevant to the topic being discussed. Chapter 1 talks about understanding the circuit diagram, and Chapter 2 covers how to compile component information file. Chapter 3 deals with the design layout, while Chapter 4 talks about preparing the master artworks. The book also covers generating computer aided design (CAD) master patterns, and then discusses how to prepare the production drawing a

  12. All-Digital ADC Design in 65 nm CMOS Technology

    OpenAIRE

    Pathapati, Srinivasa Rao

    2014-01-01

    The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital domain. The advantage of using a fully digital ADC design rather than a traditional analog ADC design is that the circuit is defined by an HDL description and automatically synthesized by tools. It offers low power consumption, low silicon area and a fully optimized gate-level circuit that reduces the ...

  13. Special section on analysis, design and optimization of nonlinear circuits

    Science.gov (United States)

    Okumura, Kohshi

    Nonlinear theory plays an indispensable role in analysis, design and optimization of electric/electronic circuits because almost all circuits in the real world are modeled by nonlinear systems. Also, as the scale and complexity of circuits increase, more effective and systematic methods for the analysis, design and optimization are desired. The goal of this special section is to bring together research results from a variety of perspectives and academic disciplines related to nonlinear electric/electronic circuits.This special section includes three invited papers and six regular papers. The first invited paper by Kennedy entitled “Recent advances in the analysis, design and optimization of digital delta-sigma modulators” gives an overview of digital delta-sigma modulators and some techniques for improving their efficiency. The second invited paper by Trajkovic entitled “DC operating points of transistor circuits” surveys main theoretical results on the analysis of DC operating points of transistor circuits and discusses numerical methods for calculating them. The third invited paper by Nishi et al. entitled “Some properties of solution curves of a class of nonlinear equations and the number of solutions” gives several new theorems concerning solution curves of a class of nonlinear equations which is closely related to DC operating point analysis of nonlinear circuits. The six regular papers cover a wide range of areas such as memristors, chaos circuits, filters, sigma-delta modulators, energy harvesting systems and analog circuits for solving optimization problems.The guest editor would like to express his sincere thanks to the authors who submitted their papers to this special section. He also thanks the reviewers and the editorial committee members of this special section for their support during the review process. Last, but not least, he would also like to acknowledge the editorial staff of the NOLTA journal for their continuous support of this

  14. Nonlinear dynamics based digital logic and circuits.

    Science.gov (United States)

    Kia, Behnam; Lindner, John F; Ditto, William L

    2015-01-01

    We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

  15. Design of drive circuit of laser diode

    Science.gov (United States)

    Ran, Yingying; Huang, Xuegong; Xu, Xiaobin

    2016-10-01

    Aiming at the difficult problem of high precision frequency stabilization of semiconductor laser diode, the laser frequency control is realized through the design of the semiconductor drive system. Above all, the relationship between the emission frequency and the temperature of LD is derived theoretically. Then the temperature corresponding to the stable frequency is obtained. According to the desired temperature stability of LD, temperature control system is designed, which is composed of a temperature setting circuit, temperature gathering circuit, the temperature display circuit, analog PID control circuit and a semiconductor refrigerator control circuit module. By sampling technology, voltage of platinum resistance is acquired, and the converted temperature is display on liquid crystal display. PID analog control circuit controls speed stability and precision of temperature control. The constant current source circuit is designed to provide the reference voltage by a voltage stabilizing chip, which is buffered by an operational amplifier. It is connected with the MOSFET to drive the semiconductor laser to provide stable current for the semiconductor laser. PCB circuit board was finished and the experimental was justified. The experimental results show that: the design of the temperature control system could achieve the goal of temperature monitoring. Meanwhile, temperature can be stabilized at 40°C +/- 0.1°C. The output voltage of the constant current source is 2 V. The current is 35 mA.

  16. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern mul

  17. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  18. Fingerprinting Digital Circuits on Programmable Hardware

    Science.gov (United States)

    2007-11-02

    signature data in image, video, and audio signals have received a great deal of attention. A spectrum of steganographic techniques for protection of...several recent techniques provide protection against all known attacks [15]. Although protection of digital audio signals emerged as a more difficult...task, at least three different techniques have been proposed [12, 16, 17]. The protection of video streams using steganography has been demonstrated

  19. Digital Operation of Microelectronic Circuits Analogous to Protein Hydrogen Bonding Networks

    Directory of Open Access Journals (Sweden)

    Elitsa Gieva

    2012-12-01

    Full Text Available Two hydrogen bonding networks with water molecules and branching residues extracted from β-lactamase protein are investigated and their proton transfer characteristics are studied by creating analogous electrical circuits consisting of block-elements. The block-elements and their proton transfer are described by polynomials that are coded in Matlab and in Verilog-A for use in the Spectre simulator of Cadence IC design system. DC and digital pulse analyses are performed to demonstrate that some circuit outputs behave as repeaters while other - behave as inverters. The results also showed that the HBN circuits might behave as a D-latch and a demultiplexer.

  20. Semiconductors integrated circuit design for manufacturability

    CERN Document Server

    Balasinki, Artur

    2011-01-01

    Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

  1. RF Circuit Design in Nanometer CMOS

    OpenAIRE

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern multi-band communication systems as these systems move toward software-defined radio. These trends in technology and system design call for a re-thinking of analog and RF circuit design in nanometer C...

  2. Design of multi-functional digital chip's out buffer circuit in CMOS process%CMOS工艺多功能数字芯片的输出缓冲电路设计

    Institute of Scientific and Technical Information of China (English)

    周子昂; 姚遥; 徐坤; 张利红

    2012-01-01

    为了提高数字集成电路芯片的驱动能力,采用优化比例因子的等比缓冲器链方法,通过Hspice软件仿真和版图设计测试.提出了一种基于CSMC2P2M0.6μmCMOS工艺的输出缓冲电路设计方案。本文完成了系统的电原理图设计和版图设计,整体电路采用Hspice和CSMC2P2M的0.6μmCMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC2P2M0.6μmCMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1mm×1mm,并参与MPW(多项目晶圆)计划流片。流片测试结果表明,在输出负载很大时,本设计能提供足够的驱动电流,同时延迟时间短、并占用版图面积小。%In order to improve the driving ability of the digital integrated circuit chip ,by optimizing the scale factor ratio buffer chain method,the design of output buffer circuit based on CSMC 2P2M 0.6 μm CMOS process is designed in this paper by simulation of Hspice Software and layout design testing, The paper complete system of electrical schematic design and layout design.The circuit is simulated using Hspice and the process of the CSMC 2P2M 0.6μm CMOS (06 mixddct02v24), the layout is based on CSMC 2P2M 0.6 μm CMOS and is used in a Multi-functional Digital Chip, The chip area is 1 mmxl mm. The design has been successfully implemented by participating in the plan of the Multi Project Wafer. Measurements indicate that t the design can provide sufficient drive current, and short delay time, and small layout when the output load is very large.

  3. Enzyme-Free Scalable DNA Digital Design Techniques: A Review.

    Science.gov (United States)

    Konampurath George, Aby; Singh, Harpreet

    2016-12-02

    With the recent developments in DNA nanotechnology, DNA has been used as the basic building block for the design of nanostructures, autonomous molecular motors, various devices, and circuits. DNA is considered as a possible candidate for replacing silicon for designing digital circuits in a near future, especially in implantable medical devices, because of its parallelism, computational powers, small size, light weight, and compatibility with bio-signals. The research in DNA digital design is in early stages of development, and electrical and computer engineers are not much attracted towards this field. In this paper, we give a brief review of the existing enzyme-free scalable DNA digital design techniques which are recently developed. With the developments in DNA circuits, it would be possible to design synthetic molecular systems, therapeutic molecular devices, and other molecular scale devices and instruments. The ultimate aim will be to build complex digital designs using DNA strands which may even be placed inside a human body.

  4. An Educational Laboratory for Digital Control and Rapid Prototyping of Power Electronic Circuits

    Science.gov (United States)

    Choi, Sanghun; Saeedifard, M.

    2012-01-01

    This paper describes a new educational power electronics laboratory that was developed primarily to reinforce experimentally the fundamental concepts presented in a power electronics course. The developed laboratory combines theoretical design, simulation studies, digital control, fabrication, and verification of power-electronic circuits based on…

  5. Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

    OpenAIRE

    石橋, 孝昭

    2012-01-01

    This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

  6. Design guidelines for SAR digital receiver/exciter boards.

    Energy Technology Data Exchange (ETDEWEB)

    Dudley, Peter A.

    2009-08-01

    High resolution radar systems generally require combining fast analog to digital converters and digital to analog converters with very high performance digital signal processing logic. These mixed analog and digital printed circuit boards present special challenges with respect to electromagnetic interference. This document first describes the mechanisms of interference on such boards then follows up with a discussion of prevention techniques and finally provides a checklist for designers to help avoid common mistakes.

  7. Digital design and computer architecture

    CERN Document Server

    Harris, David

    2010-01-01

    Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of D

  8. Dynamical Systems in Circuit Designer's Eyes

    Energy Technology Data Exchange (ETDEWEB)

    Odyniec, M.

    2011-05-09

    Examples of nonlinear circuit design are given. Focus of the design process is on theory and engineering methods (as opposed to numerical analysis). Modeling is related to measurements It is seen that the phase plane is still very useful with proper models Harmonic balance/describing function offers powerful insight (via the combination of simulation with circuit and ODE theory). Measurement and simulation capabilities increased, especially harmonics measurements (since sinusoids are easy to generate)

  9. 49 CFR 236.5 - Design of control circuits on closed circuit principle.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Design of control circuits on closed circuit..., AND APPLIANCES Rules and Instructions: All Systems General § 236.5 Design of control circuits on closed circuit principle. All control circuits the functioning of which affects safety of train...

  10. Simplified design of micropower and battery circuits

    CERN Document Server

    Lenk, John

    1995-01-01

    'Simplified Design of Micropower and Battery Circuits' provides a simplified, step-by-step approach to micropower and supply cell circuit design. No previous experience in design is required to use the techniques described, thus making the book well suited for the beginner, student, or experimenter as well as the design professional.The book concentrates on the use of commercial micropower ICs by discussing selections of external components that modify the IC-package characteristics. The basic approach is to start design problems with approximations for trial-value components in expe

  11. RF microwave circuit design for wireless applications

    CERN Document Server

    Rohde, Ulrich L

    2012-01-01

    Provides researchers and engineers with a complete set of modeling, design, and implementation tools for tackling the newest IC technologies Revised and completely updated, RF/Microwave Circuit Design for Wireless Applications, Second Edition is a unique, state-of-the-art guide to wireless integrated circuit design that provides researchers and engineers with a complete set of modeling, design, and implementation tools for tackling even the newest IC technologies. It emphasizes practical design solutions for high-performance devices and circuitry, incorporating ample exa

  12. On automatic synthesis of analog/digital circuits

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-12-31

    The paper builds on a recent explicit numerical algorithm for Kolmogorov`s superpositions, and will show that in order to synthesize minimum size (i.e., size-optimal) circuits for implementing any Boolean function, the nonlinear activation function of the gates has to be the identity function. Because classical and--or implementations, as well as threshold gate implementations require exponential size, it follows that size-optimal solutions for implementing arbitrary Boolean functions can be obtained using analog (or mixed analog/digital) circuits. Conclusions and several comments are ending the paper.

  13. Design of Digital Hybrid Chaotic Sequence Generator

    Institute of Scientific and Technical Information of China (English)

    RAO Nini; ZENG Dong

    2004-01-01

    The feasibility of the hybrid chaotic sequences as the spreading codes in code divided multiple access(CDMA) system is analyzed.The design and realization of the digital hybrid chaotic sequence generator by very high speed integrated circuit hardware description language(VHDL) are described.A valid hazard canceledl method is presented.Computer simulations show that the stable digital sequence waveforms can be produced.The correlations of the digital hybrid chaotic sequences are compared with those of m-sequences.The results show that the correlations of the digital hybrid chaotic sequences are almost as good as those of m-sequences.The works in this paper explored a road for the practical applications of chaos.

  14. A Parallel Genetic Algorithm for Automated Electronic Circuit Design

    Science.gov (United States)

    Lohn, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris; Norvig, Peter (Technical Monitor)

    2000-01-01

    We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

  15. Design of Digital Control Circuit of Massaging Machine Drive Based on MCU%基于单片机的按摩机传动数字控制电路设计

    Institute of Scientific and Technical Information of China (English)

    张新荣; 张宇林; 周红标; 唐中一

    2011-01-01

    对基于单片机的按摩机传动控制电路进行设计。以单片机为核心控制芯片.以直流电机PWM调速技术为基础设计电源电路、复位电路、电机和指示灯控制电路、按键及显示电路等部分,利用软件编程实现人机交互及按摩功能。按键操作选择按摩机工作状态,报警装置示警或提示按摩完成,指示灯显示当前工作状态,LED数码管显示当前电机转速。经过理论分析及实验研究,该系统能够实现基本的按摩功能,结构简单、性价比高、体积小,可较好地满足人体腰部、足部以及颈部的按摩需要。%The digital control circuit of massaging machine drive based on MCU is designed. The MCU is used as the kernel control chip. The power circuit based on DC motor PWM speed control technology, reset circuit, motor, indicating lamp control circuit, key and display circuit are designed. The massaging machine working state is selected through the button. When massage is complete, the alarm device will prompt the user. The indicating lamp indicates the current work status. The LED displays the current speed of motor. Theory analysis and experimental study show that the system can implement basic massaging function and has advantages of simple structure, higher performance-cost ratio, small size and can better meet the human waist, foot and neck massage needs.

  16. Analog circuit design art, science and personalities

    CERN Document Server

    Williams, Jim

    1991-01-01

    This book is far more than just another tutorial or reference guide - it's a tour through the world of analog design, combining theory and applications with the philosophies behind the design process. Readers will learn how leading analog circuit designers approach problems and how they think about solutions to those problems. They'll also learn about the `analog way' - a broad, flexible method of thinking about analog design tasks.A comprehensive and useful guide to analog theory and applications. Covers visualizing the operation of analog circuits. Looks at how to rap

  17. The multiplicity of the digital textbook as design object

    DEFF Research Database (Denmark)

    Riis Ebbesen, Toke

    2015-01-01

    Building on a preliminary case study of the Danish educational publisher Systime A/S and its flagship product, the web-based ‘iBog’/‘iBook’, this article explores how digital textbooks can be understood as design. The shaping of digital books is seen as being intertwined in a wider circuit of des...

  18. Evolvable designs of experiments applications for circuits

    CERN Document Server

    Iordache, Octavian

    2009-01-01

    Adopting a groundbreaking approach, the highly regarded author shows how to design methods for planning increasingly complex experiments. He begins with a brief introduction to standard quality methods and the technology in standard electric circuits. The book then gives numerous examples of how to apply the proposed methodology in a series of real-life case studies. Although these case studies are taken from the printed circuit board industry, the methods are equally applicable to other fields of engineering.

  19. Upset susceptibility study employing circuit analysis and digital simulation

    Science.gov (United States)

    Carreno, V. A.

    1984-01-01

    This paper describes an approach to predicting the susceptibility of digital systems to signal disturbances. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, Electromagnetic Interference (EMI) and Electromagnetic Pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload will bring the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The Super-Sceptre (system for circuit evaluation of transient radiation effects) Program was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.

  20. Upset susceptibility study employing circuit analysis and digital simulation

    Science.gov (United States)

    Carreno, V. A.

    1984-12-01

    An approach to predict the susceptibility of digital systems to signal disturbances is described. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, electromagnetic interference (EMI), and electromagnetic pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload brings the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The super-sceptre (system for circuit evaluation of transient radiation effects) programs was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.

  1. Ones and zeros understanding Boolean algebra digital circuits and the logic of sets

    CERN Document Server

    Gregg, John

    1998-01-01

    "Ones and Zeros explains, in lay terms, Boolean algebra, the suprisingly simple system of mathematical logic used in digital computer circuitry. Ones and Zeros follows the development of this logic system from its origins in Victorian England to its rediscovery in this century as the foundation of all modern computing machinery. Readers will learn about the interesting history of the development of symbolic logic in particular, and the often misunderstood process of mathematical invention and scientific discovery, in general. Ones and Zeros also features practical exercises with answers, real-world examples of digital circuit design, and a reading list." "Ones and Zeros will be of particular interest to software engineers who want to gain a comprehensive understanding of computer hardware." "Outstanding features include: a history of mathematical logic, an explanation of the logic of digital circuits, and hands-on exercises and examples."--Jacket.

  2. Lithium Circuit Test Section Design and Fabrication

    Science.gov (United States)

    Godfroy, Thomas; Garber, Anne; Martin, James

    2006-01-01

    The Early Flight Fission - Test Facilities (EFF-TF) team has designed and built an actively pumped lithium flow circuit. Modifications were made to a circuit originally designed for NaK to enable the use of lithium that included application specific instrumentation and hardware. Component scale freeze/thaw tests were conducted to both gain experience with handling and behavior of lithium in solid and liquid form and to supply anchor data for a Generalized Fluid System Simulation Program (GFSSP) model that was modified to include the physics for freeze/thaw transitions. Void formation was investigated. The basic circuit components include: reactor segment, lithium to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. This paper discusses the overall system design and build and the component testing findings.

  3. The Biological Property of Synthetic Evolved Digital Circuits with ESD Immunity-Redundancy or Degeneracy?

    Institute of Scientific and Technical Information of China (English)

    Menghua Man; Shanghe Liu; Xiaolong Chang; Mai Lu

    2013-01-01

    In the ongoing evolutionary process,biological systems have displayed a fundamental and remarkable property of robustness,i.e.,the property allows the system to maintain its functions despite external and internal perturbations.Redundancy and degeneracy are thought to be the underlying structural mechanisms of biological robustness.Inspired by this,we explored the proximate cause of the immunity of the synthetic evolved digital circuits to ESD interference and discussed the biological characteristics behind the evolutionary circuits.First,we proposed an evolutionary method for intrinsic immune circuit design.The circuits' immunity was evaluated using the functional fault models based on probability distributions.Then,several benchmark circuits,including ADDER,MAJORITY,and C17,were evolved for high intrinsic immunity.Finally,using the quantitative definitions based on information theory,we measured the topological characteristics of redundancy and degeneracy in the evolved circuits and compared their contributions to the immunity.The results show that redundant elements are necessary for the ESD immune circuit design,whereas degeneracy is the key to making use of the redundancy robustly and efficiently.

  4. Optimal design of APD biasing circuit

    Institute of Scientific and Technical Information of China (English)

    SUN Chun-sheng; QIN Shi-qiao; WANG Xing-shu; ZHU Dong-hua

    2007-01-01

    This paper proposes a control method for avalanche photodiode (APD) reverse bias with temperature compensation and load resistance compensation. The influence of background light and load resistance on APD detection circuit is analyzed in detail. A theoretical model of temperature compensation and load resistance compensation is established, which is used for APD biasing circuit designing. It is predicted that this control method is especially suitable for LD laser range finder used on vehicles. Experimental results confirm thatthe design proposed in this paper can considerablely improve the performance of range finder.

  5. 数字家庭网关射频滤波电路设计与仿真%Design and Simulation on RF-Filter Circuit of Digital Home Gateway

    Institute of Scientific and Technical Information of China (English)

    曾清祺

    2013-01-01

    This paper describes the framework of digital home gateway and the detailed design of RF-filter. Based on two design ideas of the lumped and distributed parameters, the complete design steps from theoretical calculation, ADS aided design, simulation to individual optimization are provided. As an example, based on the Chebyshev LPF and its transformation, a RF band-pass filter with center frequency of 2.4 GHz is implemented. With ADS, LC band-pass filter circuits and the microstrip line band-pass filter are designed, and their simulation and optimization results are given. Furthermore, for parallel coupled microstrip line filter, the circuit layout and its Momentum simulation results are obtained. Finally, these simulation results verify the design requirements and show that these two design schemes are feasible. When working at high frequency, the microstrip line filer design methodology is recommended.%  介绍了数字家庭网关硬件设计架构,对其中的射频滤波器设计进行了详细阐述,给出了集总参数和分布参数两种设计思路下从理论计算、ADS 辅助设计到仿真、优化的完整滤波器设计步骤.结合目前常用的中心频率为2.4GHz 的射频带通滤波器的设计实例,采用 Chebyshev 滤波器设计的低通原型进行变换,借助 ADS 分别设计了 LC 滤波电路和平行耦合微带线滤波电路,给出了原理图仿真和优化结果,对平行耦合微带线滤波电路,更进一步给出了电路版图和 Momentum 仿真结果.仿真结果表明:这两种设计方案满足设计的要求,是可行的,在高频段工作时应首要考虑微带线滤波的方法进行设计.

  6. New digital circuits at Thomson semiconductor in France

    Science.gov (United States)

    Dellamussia, J. P.

    1985-11-01

    DCS, Thomson Semiconductors' Semi-Standard Circuits Department, has just announced a CMOS gate array with up to 4,200 gates, standard cells, and a unique 900-component, 3 GHz linear gate array. All of Thomson's gate arrays are supported by Daisy, Valid and Mentor workstations. These are the first fruits of a reorganization begun several months ago to distance the department from the actual design and manufacture of integrated circuits, making it more of an archestrator among customers, workstation manufacturers, independent designers and the various Thomson Semiconductors division. Thomson Semiconductors' silicon sales based on DCS contracts totaled 25,000,000 Frances in 1984. This figure should be double in 1985. Thomson Semiconductors plans to offer 120 new integrated circuits this year, twice the number available in 1984. At the same time, the Munich design center and the American subsidiary, VSI, should open new markets in 1985, bringing exports to an estimated 30 percent of sales.

  7. Digitized adiabatic quantum computing with a superconducting circuit.

    Science.gov (United States)

    Barends, R; Shabani, A; Lamata, L; Kelly, J; Mezzacapo, A; Las Heras, U; Babbush, R; Fowler, A G; Campbell, B; Chen, Yu; Chen, Z; Chiaro, B; Dunsworth, A; Jeffrey, E; Lucero, E; Megrant, A; Mutus, J Y; Neeley, M; Neill, C; O'Malley, P J J; Quintana, C; Roushan, P; Sank, D; Vainsencher, A; Wenner, J; White, T C; Solano, E; Neven, H; Martinis, John M

    2016-06-09

    Quantum mechanics can help to solve complex problems in physics and chemistry, provided they can be programmed in a physical device. In adiabatic quantum computing, a system is slowly evolved from the ground state of a simple initial Hamiltonian to a final Hamiltonian that encodes a computational problem. The appeal of this approach lies in the combination of simplicity and generality; in principle, any problem can be encoded. In practice, applications are restricted by limited connectivity, available interactions and noise. A complementary approach is digital quantum computing, which enables the construction of arbitrary interactions and is compatible with error correction, but uses quantum circuit algorithms that are problem-specific. Here we combine the advantages of both approaches by implementing digitized adiabatic quantum computing in a superconducting system. We tomographically probe the system during the digitized evolution and explore the scaling of errors with system size. We then let the full system find the solution to random instances of the one-dimensional Ising problem as well as problem Hamiltonians that involve more complex interactions. This digital quantum simulation of the adiabatic algorithm consists of up to nine qubits and up to 1,000 quantum logic gates. The demonstration of digitized adiabatic quantum computing in the solid state opens a path to synthesizing long-range correlations and solving complex computational problems. When combined with fault-tolerance, our approach becomes a general-purpose algorithm that is scalable.

  8. Digitized adiabatic quantum computing with a superconducting circuit

    Science.gov (United States)

    Barends, R.; Shabani, A.; Lamata, L.; Kelly, J.; Mezzacapo, A.; Heras, U. Las; Babbush, R.; Fowler, A. G.; Campbell, B.; Chen, Yu; Chen, Z.; Chiaro, B.; Dunsworth, A.; Jeffrey, E.; Lucero, E.; Megrant, A.; Mutus, J. Y.; Neeley, M.; Neill, C.; O'Malley, P. J. J.; Quintana, C.; Roushan, P.; Sank, D.; Vainsencher, A.; Wenner, J.; White, T. C.; Solano, E.; Neven, H.; Martinis, John M.

    2016-06-01

    Quantum mechanics can help to solve complex problems in physics and chemistry, provided they can be programmed in a physical device. In adiabatic quantum computing, a system is slowly evolved from the ground state of a simple initial Hamiltonian to a final Hamiltonian that encodes a computational problem. The appeal of this approach lies in the combination of simplicity and generality; in principle, any problem can be encoded. In practice, applications are restricted by limited connectivity, available interactions and noise. A complementary approach is digital quantum computing, which enables the construction of arbitrary interactions and is compatible with error correction, but uses quantum circuit algorithms that are problem-specific. Here we combine the advantages of both approaches by implementing digitized adiabatic quantum computing in a superconducting system. We tomographically probe the system during the digitized evolution and explore the scaling of errors with system size. We then let the full system find the solution to random instances of the one-dimensional Ising problem as well as problem Hamiltonians that involve more complex interactions. This digital quantum simulation of the adiabatic algorithm consists of up to nine qubits and up to 1,000 quantum logic gates. The demonstration of digitized adiabatic quantum computing in the solid state opens a path to synthesizing long-range correlations and solving complex computational problems. When combined with fault-tolerance, our approach becomes a general-purpose algorithm that is scalable.

  9. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  10. Performance of digital integrated circuit technologies at very high temperatures

    Energy Technology Data Exchange (ETDEWEB)

    Prince, J.L.; Draper, B.L.; Rapp, E.A.; Kromberg, J.N.; Fitch, L.T.

    1980-01-01

    Results of investigations of the performance and reliability of digital bipolar and CMOS integrated circuits over the 25 to 340/sup 0/C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results of experimental simulations of dielectrically isolated CMOS are also discussed. It was found that commercial Schottky clamped TTL, and dielectrically isolated, low power Schottky-clamped TTL, functioned to junction temperatures in excess of 325/sup 0/C. Standard gold doped TTL functioned only to 250/sup 0/C, while commercial, isolated I/sup 2/L functioned to the range 250/sup 0/C to 275/sup 0/C. Commercial junction isolated CMOS, buffered and unbuffered, functioned to the range 280/sup 0/C to 310/sup 0/C/sup +/, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340/sup 0/C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious life limiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated ciruits at temperatures in excess of 300/sup 0/C has been found.

  11. Design of Multivalued Circuits Based on an Algebra for Current—Mode CMOS Multivalued Circuits

    Institute of Scientific and Technical Information of China (English)

    陈偕雄; ClaudioMoraga

    1995-01-01

    An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed.this paper discusses its application in the design of multivalued circuits.Several current-mode CMOS quaternary and quinary circuits are designed by algebraic means.The design method based on this algebra may offer a design simpler than the previously known ones.

  12. Design of Digital Imaging System for Optimization of Control Parameters

    Institute of Scientific and Technical Information of China (English)

    SONG Yong; HAO Qun; YANG Guang; SUN Hong-wei

    2007-01-01

    The design of experimental system of digital imaging system for control parameter is discussed in detail. Signal processing of digital CCD imaging system is first analyzed. Then the real time control of CCD driver and digital processing circuit and man-machine interaction are achieved by the design of digital CCD imaging module and control module. Experimental results indicate that the image quality of CCD experimental system makes a good response to the change of control parameters. The system gives an important base for improving image quality and the applicability of micro imaging system in complex environment.

  13. Analog circuit design designing high performance amplifiers

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    The third volume Designing High Performance Amplifiers applies the concepts from the first two volumes. It is an advanced treatment of amplifier design/analysis emphasizing both wideband and precision amplification.

  14. Digital Animation Character Creation Design

    Institute of Scientific and Technical Information of China (English)

    潘锋

    2014-01-01

    The purpose of this article is to discuss the proper method for Chinese digital animation character design on the foundation of certain cultural elements. The method used in this study is known as comparative analysis of Disney and Japanese animation styles in action, appearance, facial expression and voice design. These dynamic factors are the best carrier of the animation spirit and native culture, so it is important to take the dynamic factors into account when producing the digital animation, and it will be an excellent starting point to innovate Chinese digital animation.

  15. Design of organic complementary circuits and systems on foil

    CERN Document Server

    Abdinia, Sahel; Cantatore, Eugenio

    2015-01-01

    This book describes new approaches to fabricate complementary organic electronics, and focuses on the design of circuits and practical systems created using these manufacturing approaches. The authors describe two state-of-the-art, complementary organic technologies, characteristics and modeling of their transistors and their capability to implement circuits and systems on foil. Readers will benefit from the valuable overview of the challenges and opportunities that these extremely innovative technologies provide. ·         Demonstrates first circuits implemented using specific complementary organic technologies, including first printed analog to digital converter, first dynamic logic on foil and largest complementary organic circuit ·         Includes step-by-step design from single transistor level to complete systems on foil ·         Provides a platform for comparing state-of-the-art complementary organic technologies and for comparing these with other similar technologies, spec...

  16. Power management techniques for integrated circuit design

    CERN Document Server

    Chen, Ke-Horng

    2016-01-01

    This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

  17. The research of digital circuit system for high accuracy CCD of portable Raman spectrometer

    Science.gov (United States)

    Yin, Yu; Cui, Yongsheng; Zhang, Xiuda; Yan, Huimin

    2013-08-01

    The Raman spectrum technology is widely used for it can identify various types of molecular structure and material. The portable Raman spectrometer has become a hot direction of the spectrometer development nowadays for its convenience in handheld operation and real-time detection which is superior to traditional Raman spectrometer with heavy weight and bulky size. But there is still a gap for its measurement sensitivity between portable and traditional devices. However, portable Raman Spectrometer with Shell-Isolated Nanoparticle-Enhanced Raman Spectroscopy (SHINERS) technology can enhance the Raman signal significantly by several orders of magnitude, giving consideration in both measurement sensitivity and mobility. This paper proposed a design and implementation of driver and digital circuit for high accuracy CCD sensor, which is core part of portable spectrometer. The main target of the whole design is to reduce the dark current generation rate and increase signal sensitivity during the long integration time, and in the weak signal environment. In this case, we use back-thinned CCD image sensor from Hamamatsu Corporation with high sensitivity, low noise and large dynamic range. In order to maximize this CCD sensor's performance and minimize the whole size of the device simultaneously to achieve the project indicators, we delicately designed a peripheral circuit for the CCD sensor. The design is mainly composed with multi-voltage circuit, sequential generation circuit, driving circuit and A/D transition parts. As the most important power supply circuit, the multi-voltage circuits with 12 independent voltages are designed with reference power supply IC and set to specified voltage value by the amplifier making up the low-pass filter, which allows the user to obtain a highly stable and accurate voltage with low noise. What's more, to make our design easy to debug, CPLD is selected to generate sequential signal. The A/D converter chip consists of a correlated

  18. Scalable, Time-Responsive, Digital, Energy-Efficient Molecular Circuits using DNA Strand Displacement

    CERN Document Server

    Chiniforooshan, Ehsan; Kari, Lila; Seki, Shinnosuke

    2010-01-01

    We propose a novel theoretical biomolecular design to implement any Boolean circuit using the mechanism of DNA strand displacement. The design is scalable: all species of DNA strands can in principle be mixed and prepared in a single test tube, rather than requiring separate purification of each species, which is a barrier to large-scale synthesis. The design is time-responsive: the concentration of output species changes in response to the concentration of input species, so that time-varying inputs may be continuously processed. The design is digital: Boolean values of wires in the circuit are represented as high or low concentrations of certain species, and we show how to construct a single-input, single-output signal restoration gate that amplifies the difference between high and low, which can be distributed to each wire in the circuit to overcome signal degradation. This means we can achieve a digital abstraction of the analog values of concentrations. Finally, the design is energy-efficient: if input sp...

  19. Process Variations and Probabilistic Integrated Circuit Design

    CERN Document Server

    Haase, Joachim

    2012-01-01

    Uncertainty in key parameters within a chip and between different chips in the deep sub micron era plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process.  Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development.   This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits.  Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.  Trains IC designers to recognize problems caused by parameter variations during manufacturing and to choose the best methods available to mitigate these issues during the design process; Offers both qual...

  20. Low Power Design of High Speed CMOS Pulse Stream Neuron Circuit

    Institute of Scientific and Technical Information of China (English)

    陈继伟; 石秉学

    2000-01-01

    A new pulse stream neuron circuit is presented, which can be obtained in the digital CMOS process and combines both the merits of digital circuits and analog ones. The output is expressed by the frequency of the pulses with transfer characteristic, which is correspondent with the ideal sigmoid curve perfectly. Moreover, the pulse-active strategy is introduced into the design of this CMOS pulse stream neuron circuit for the first time in order to reduce the power dissipation, which is applicable to the low-power design of mixed-signal circuits,too. A simple technical process and compact architecture make this circuit work at a higher speed and with lower power dissipation and smaller area.

  1. Electronic Circuit Design Using HEP Computational Tools

    Science.gov (United States)

    Vaz, MÁRio

    CPSPICE is an eletronic circuit statistical simulation program develloped to run in a parallel environment under UNIX operating system and TCP/IP communications protocol, using CPS - Cooperative Processes Software, SPICE program and CERNLIB software package. It is part of a set of tools being devellop, intended to help electronic engineers to design, model and simulate complex systems and circuits for High Energy Physics detectors, based on statistical methods, using the same software and methodology used by HEP physicists for data analysis. CPSPICE simulates electronic circuits by Monte Carlo method, through several different processes running simultaneously SPICE in UNIX paralell computers or workstation farms. Data transfer between CPS processes for a modified version of SPICE2G6 is done by RAM memory, but can also be done through hard disk files if no source files are available for the simulator, and for bigger simulation output files. Simulation results are written in a HBOOK file as a NTUPLE, to be examined by HBOOK in batch model or interactevely by PAW - Physics Analysis Workstation -programs. The results can be visualized through histograms and graphics, and analyzed by statistical procedures available. The HBOOK file can be stored on hard disk for small amount of data, or into Exabyte tape file for large amount of data. HEP tools also helps circuit or component modelling, like MINUIT program from CERNLIB, that implements Nelder & Mead Simplex and Gradient with or without derivatives algorithms, and can be used for design optimization. This paper presents CPSPICE program implementation. The scheme adopted is suitable to make parallel other electronic circuit simulators.

  2. Optimization Design for Digital Binoculars

    Institute of Scientific and Technical Information of China (English)

    CEN Jun-bo; CHEN Wei-min; LI Hui; HUANG Shang-lian

    2005-01-01

    In order to develop competitive and high performance/cost ratio of digital binoculars, design scheme should be optimized in term of technical capacity, economic benefit, product performance, risk management, etc. The common optimization method is limited in qualitative analysis, and the parameter optimization method is limited in obtaining optimal parameter only from technical side. Each method has its limitation. Based on the analysis of digital binoculars parameters, optional design schemes are laid down.Analytic hierarchy process combined the qualitative analysis with the quantitative analysis together. The design schemes are optimized, and result is worked out.

  3. Energy efficient circuit design using nanoelectromechanical relays

    Science.gov (United States)

    Venkatasubramanian, Ramakrishnan

    Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS

  4. Simplified design of microprocessor-supervisory circuits

    CERN Document Server

    Lenk, John

    1998-01-01

    This is the seventh book in the popular Simplified Design series from John Lenk, which teaches engineers, technicians, and students to use and modify off-the-shelf ICs to suit their individual design needs.The first chapter of this book describes the basic operation of microprocessor supervisory circuits and how to use manufacturer data sheets to make your component selections. Later chapters describe the internal operations of various commonly-available ICs and how to select and modify them.The most common microprocessor-supervisory functions include: power-on reset, low-volta

  5. Principles of modern digital design

    CERN Document Server

    Lala, Parag K

    2007-01-01

    A major objective of this book is to fill the gap between traditional logic design principles and logic design/optimization techniques used in practice. Over the last two decades several techniques for computer-aided design and optimization of logic circuits have been developed. However, underlying theories of these techniques are inadequately covered or not covered at all in undergraduate text books. This book covers not only the ""classical"" material found in current text books but also selected materials that modern logic designers need to be familiar with.

  6. 13-bit 200MSPS Pipeline ADC Analog Circuits Design with LMS Digital Calibration%采用LMS数字校准的13位200MSPS ADC设计

    Institute of Scientific and Technical Information of China (English)

    高俊枫; 谌博; 李广军; 李强

    2011-01-01

    本文设计了无采保电路流水线ADC,并且采用LMS校准技术对ADC前三级3阶和5阶非线性误差进行数字校准。精心设计的运放和开关使MDAC的闭环非线性仅为7LSB左右。仿真结果表示200MSPS采样率的流水线ADC在输入达到83.13M时可以达到77dB的SNDR。%A SHA less pipeline ADC is designed by the paper, with the 3rd-order and 5th-order nonlinearity of thefirst three stages calibrated by LMS calibration technique. Around 7LSB closed-loop nonlinearity of MDAC is achieved by carefully consider the opamps and switches. Simulation shows the SNDR of the proposed ADC at200MSPS sampling rate is 77dB with 83.13MHz input.

  7. On Using Current Steering Logic in Mixed Analogue-digital Circuits

    DEFF Research Database (Denmark)

    Lehmann, Torsten

    1998-01-01

    The authors investigate power supply noise in mixed analogue-digital circuits, arising from communication between the analogue and digital parts of the circuit. Current steering techniques and proper buffering are used to show which noise currents can be reduced and which cannot. In addition...

  8. Upset susceptibility study employing circuit analysis and digital simulation. [digital systems and electromagnetic interference

    Science.gov (United States)

    Carreno, V. A.

    1984-01-01

    An approach to predict the susceptibility of digital systems to signal disturbances is described. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, electromagnetic interference (EMI), and electromagnetic pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload brings the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The super-sceptre (system for circuit evaluation of transient radiation effects) programs was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.

  9. Design of Reversible Sequential Circuit Using Reversible Logic Synthesis

    Directory of Open Access Journals (Sweden)

    Md. Belayet Ali

    2011-12-01

    Full Text Available Reversible logic is one of the most vital issue at present time and it has different areas for its application,those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP, quantum dot cellular auto meta, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.

  10. Design of Reversible Sequential Circuit Using Reversible Logic Synthesis

    Directory of Open Access Journals (Sweden)

    Md. Mosharof Hossin

    2012-01-01

    Full Text Available Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP, quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designedRS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.

  11. Research and design of the protection circuits in LD controller

    Institute of Scientific and Technical Information of China (English)

    SHAN Jiang-dong; TIAN Xiao-jian; DENG Jun; ZHANG Shuang

    2006-01-01

    According to the parameters and applications of laser diode (LD), three protection circuits were designed: the time-delay soft-start protection circuit, the power-on impulse protection circuit and the limit-current protection circuit. In this article, the structure and the principle of every protection circuit have been detailed. From several tests and feedbacks from customers, the expected goals have been completed.

  12. A low complexity, low spur digital IF conversion circuit for high-fidelity GNSS signal playback

    Science.gov (United States)

    Su, Fei; Ying, Rendong

    2016-01-01

    A low complexity high efficiency and low spur digital intermediate frequency (IF) conversion circuit is discussed in the paper. This circuit is key element in high-fidelity GNSS signal playback instrument. We analyze the spur performance of a finite state machine (FSM) based numerically controlled oscillators (NCO), by optimization of the control algorithm, a FSM based NCO with 3 quantization stage can achieves 65dB SFDR in the range of the seventh harmonic. Compare with traditional lookup table based NCO design with the same Spurious Free Dynamic Range (SFDR) performance, the logic resource require to implemented the NCO is reduced to 1/3. The proposed design method can be extended to the IF conversion system with good SFDR in the range of higher harmonic components by increasing the quantization stage.

  13. On Design of Parity Preserving Reversible Adder Circuits

    Science.gov (United States)

    Haghparast, Majid; Bolhassani, Ali

    2016-12-01

    In this paper novel parity preserving reversible logic blocks are presented and verified. Then, we present cost-effective parity preserving reversible implementations of Full Adder, 4:2 Compressor, Binary to BCD converter, and BCD adder using these blocks. The proposed parity preserving reversible BCD adder is designed by cascading the presented 4-digit parity preserving reversible Full Adder and a parity preserving reversible Binary to BCD Converter. In this design, instead of realizing the detection and correction unit, we design a Binary to BCD converter that its inputs are the output of parity preserving binary adder, and its output is a parity preserving BCD digit. In addition, several theorems on the numbers of garbage outputs, constant inputs, quantum cost and delay of the designs have been presented to show its optimality. In the presented circuits, the delay and the quantum cost are reduced by deriving designs based on the proposed parity preserving reversible blocks. The advantages of the proposed designs over the existing ones are quantitatively described and analysed. All the scales are in the Nano-metric area.

  14. Digi Island: A Serious Game for Teaching and Learning Digital Circuit Optimization

    Science.gov (United States)

    Harper, Michael; Miller, Joseph; Shen, Yuzhong

    2011-01-01

    Karnaugh maps, also known as K-maps, are a tool used to optimize or simplify digital logic circuits. A K-map is a graphical display of a logic circuit. K-map optimization is essentially the process of finding a minimum number of maximal aggregations of K-map cells. with values of 1 according to a set of rules. The Digi Island is a serious game designed for aiding students to learn K-map optimization. The game takes place on an exotic island (called Digi Island) in the Pacific Ocean . The player is an adventurer to the Digi Island and will transform it into a tourist attraction by developing real estates, such as amusement parks.and hotels. The Digi Island game elegantly converts boring 1s and Os in digital circuits into usable and unusable spaces on a beautiful island and transforms K-map optimization into real estate development, an activity with which many students are familiar and also interested in. This paper discusses the design, development, and some preliminary results of the Digi Island game.

  15. Designer's handbook of instrumentation and control circuits

    CERN Document Server

    Carr, Joseph J

    1991-01-01

    Here is a comprehensive, practical guide to the entire process of analog instrumentation and control, from sensor input to data conversion circuitry and final output. This readable handbook avoids complex mathematical treatments, instead taking an applications-oriented approach and presenting many sample circuits and concrete examples. It is an essential reference for engineers and high-level technicians in a variety of scientific and engineering fields--anywhere data is collected electronically and where such data is used to control physical processes.Key Features* Covers design o

  16. Analog circuit design techniques at 0.5V

    CERN Document Server

    Chatterjee, Shouri; Stanic, Nebojša

    2010-01-01

    This book tackles challenges for the design of analog integrated circuits that operate from ultra-low power supply voltages (down to 0.5V). Coverage demonstrates the signal processing circuit and circuit biasing approaches through the design of operational transconductance amplifiers (OTAs). These amplifiers are then used to build analog system functions including continuous time filter and a sample and hold amplifier.

  17. Design of Nonlinear Circuits: The Linear Time-Varying Approach

    NARCIS (Netherlands)

    Kuijstermans, F.C.M.

    2003-01-01

    Over the last years the ever-growing demand for higher performance has led to much interest in using nonlinear circuit concepts for electronic circuit design. For this we have to deal with analysis and synthesis of dynamic nonlinear circuits. This thesis proposes to handle the nonlinear design

  18. Design of Nonlinear Circuits: The Linear Time-Varying Approach

    NARCIS (Netherlands)

    Kuijstermans, F.C.M.

    2003-01-01

    Over the last years the ever-growing demand for higher performance has led to much interest in using nonlinear circuit concepts for electronic circuit design. For this we have to deal with analysis and synthesis of dynamic nonlinear circuits. This thesis proposes to handle the nonlinear design comp

  19. ARSITEKTUR DVD (Digital Virtual Design

    Directory of Open Access Journals (Sweden)

    Danny Santoso Mintorogo

    2000-01-01

    Full Text Available Soon after the millennium year of 2000 and toward 21th century, the ways of architecture design will be a great change from traditional hand design and drawings to super computer digital virtual design models with tremendous of high-end architectural 3D software domains. Virtual Technology will be a plus to architectural design stage to obtain several "scheme" and observe with real - time feedback of the quality (height, light, furniture, shape, and environment as well as the sequential of the space, site context or massing studies. Abstract in Bahasa Indonesia : Strategi dalam desain arsitektur pada abad 22 atau setelah tahun milinium 2000 ini akan banyak didominasi dengan perangkap teknologi canggih yang tentunya akan mengandalkan pada perangkap keras (komputer dan perangkap lunak (software untuk tujuan desain arsitektur secara digital. Teknologi "Virtual" akan dimanfaatkan untuk bidang arsitektur dalam mengoptimasikan disain arsitektur secara digital maya, untuk mengobservasi/mengkaji kwalitas ruang, model suatu ruang/massa secara maya dalam phase perancangan arsitektur. Kata kunci: arsitektur, desain, digital, maya.

  20. Interface design for digital courses

    NARCIS (Netherlands)

    Tabbers, Huib; Kester, Liesbeth; Hummel, Hans; Nadolski, Rob

    2005-01-01

    This text should be referred to as: Tabbers, H., Kester, L., Hummel, H. G. K., & Nadolski, R. J. (2003). Interface design for digital courses. In W. Jochems, J. van Merriënboer, & R. Koper (Eds). Integrated e-learning: implications for pedagogy, technology & organisation (pp. 100-111). London: Routl

  1. Interface design for digital courses

    NARCIS (Netherlands)

    Tabbers, Huib; Kester, Liesbeth; Hummel, Hans; Nadolski, Rob

    2005-01-01

    This text should be referred to as: Tabbers, H., Kester, L., Hummel, H. G. K., & Nadolski, R. J. (2003). Interface design for digital courses. In W. Jochems, J. van Merriënboer, & R. Koper (Eds). Integrated e-learning: implications for pedagogy, technology & organisation (pp. 100-111). London: Routl

  2. FORTRAN IV Digital Filter Design Programs. Digital Systems Education Project.

    Science.gov (United States)

    Reuss, E.; And Others

    The goals of the Digital Systems Education Project (DISE) include the development and distribution of educational/instructional materials in the digital systems area. Toward that end, this document contains three reports: (1) A FORTRAN IV Design Program for Low-Pass Butterworth and Chebychev Digital Filters; (2) A FORTRAN IV Design Program for…

  3. Circuit and interconnect design for high bit-rate applications

    NARCIS (Netherlands)

    Veenstra, H.

    2006-01-01

    This thesis presents circuit and interconnect design techniques and design flows that address the most difficult and ill-defined aspects of the design of ICs for high bit-rate applications. Bottlenecks in interconnect design, circuit design and on-chip signal distribution for high bit-rate applicati

  4. Analogue Square Root Calculator Circuit Designed With Logarithmic Amplifiers

    OpenAIRE

    2016-01-01

    In many applications, it has been necessary to calculate square roots of some numbers which are correspond to some voltages values. In this study such an analogue calculator has been designed and simulated in computer medium. Circuit consist of one logarithmic and one antilogarithmic amplifier connected in cascade. The component values of circuit chosen so that the output voltage of circuit is equal to square root of input voltage. The performance of designed circuit is investigated by applyi...

  5. Dynamic Power Reduction of Digital Circuits by ClockGating

    Directory of Open Access Journals (Sweden)

    Varsha Dewre

    2017-04-01

    Full Text Available In this paper we have presented clock gating process for low power VLSI (very large scale integration circuit design. Clock gating is one of the most quite often used systems in RTL to shrink dynamic power consumption without affecting the performance of the design. One process involves inserting gating requisites in the RTL, which the synthesis tool translates to clock gating cells in the clock-path of a register bank. This helps to diminish the switching activity on the clock network, thereby decreasing dynamic power consumption within the design. Due to the fact the translation accomplished via the synthesis tool is solely combinational; it is referred to as combinational clock gating. This transformation does not alter the behavior of the register being gated

  6. Digital Jacquard Fabric Design in Colorful Mode

    Institute of Scientific and Technical Information of China (English)

    周赳

    2004-01-01

    Digital image design is one of advanced technique in textile design. The investigation into digital Jacquard textile design in the colorful mode is one form of research in digital Jacquard fabric design, which aimed at expanding past and present jacquard design and production methods towards innovative ends. In this paper, the design principles and design methods for unconventional digital Jacquard fabric design in colorful mode have been analyzed based on the new technologies and computer applied color theory. The results of this study will enhance further research in the area of digital textile.

  7. Design and Implementation of the Digital Detection Circuit for RFOG Based on a Single FPGA%基于单片FPGA的谐振式光纤陀螺数字系统设计与实现

    Institute of Scientific and Technical Information of China (English)

    姚灵芝; 马慧莲; 金仲和

    2011-01-01

    谐振式光纤陀螺( Resonator Fiber Optic Gyro,RFOG)是基于Sagnac效应产生的谐振频率差来测量旋转角速度的一种新型光学传感器,在小型化和集成化方面具有明显优势.相比于传统的模拟检测技术,数字检测技术具有稳定性好、抗干扰能力强、处理速度快和体积小、易于集成等优势.本文设计了基于现场可编程门阵列(Field Programmable Gate Array,FPGA)的数字RFOG系统,在单片FPGA上实现了基于比例积分控制的谐振频率伺服回路、相位调制器复位电压漂移补偿回路和第二闭环反馈控制回路.最后将研制的基于单片FPGA的闭环数字检测电路应用于实际RFOG系统,验证了上述功能,并实际检测了陀螺信号.%Resonator fiber optic gyro ( RFOG) is a late-model optical sensor to measure rotation velocity, of which resonant frequency is changed through the Sagnac effect. Compared with the traditional analogue circuit, the detection system based on a digital circuit has advantages of high stability, strong anti-interference ability and swift signal processing, small size and easy integration. A digital RFOG based on FPGA is set up. The resonant frequency servo loop based on the proportion integration controller and the automatic compensation circuits for voltage drift of the phase modulator, as well as the second closed-loop are all realized with a single FPGA. Applying the digital detection circuit with the closed-loop operation to the RFOG system,the functions of the FPGA are verified experimentally. On this basis, the gyro rotation signal is observed successfully.

  8. Designing asynchronous circuits using NULL convention logic (NCL)

    CERN Document Server

    Smith, Scott

    2009-01-01

    Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design

  9. CMOS RF circuit design for reliability and variability

    CERN Document Server

    Yuan, Jiann-Shiun

    2016-01-01

    The subject of this book is CMOS RF circuit design for reliability. The device reliability and process variation issues on RF transmitter and receiver circuits will be particular interest to the readers in the field of semiconductor devices and circuits. This proposed book is unique to explore typical reliability issues in the device and technology level and then to examine their impact on RF wireless transceiver circuit performance. Analytical equations, experimental data, device and circuit simulation results will be given for clear explanation. The main benefit the reader derive from this book will be clear understanding on how device reliability issues affects the RF circuit performance subjected to operation aging and process variations.

  10. A Digital Coreless Maximum Power Point Tracking Circuit for Thermoelectric Generators

    Science.gov (United States)

    Kim, Shiho; Cho, Sungkyu; Kim, Namjae; Baatar, Nyambayar; Kwon, Jangwoo

    2011-05-01

    This paper describes a maximum power point tracking (MPPT) circuit for thermoelectric generators (TEG) without a digital controller unit. The proposed method uses an analog tracking circuit that samples the half point of the open-circuit voltage without a digital signal processor (DSP) or microcontroller unit for calculating the peak power point using iterative methods. The simulation results revealed that the MPPT circuit, which employs a boost-cascaded-with-buck converter, handled rapid variation of temperature and abrupt changes of load current; this method enables stable operation with high power transfer efficiency. The proposed MPPT technique is a useful analog MPPT solution for thermoelectric generators.

  11. A design on low noise imaging circuit for SWIR sensor

    Science.gov (United States)

    Fan, Ben; Han, Zhixue; Ma, Fei; Dong, Shuli

    2016-11-01

    SWIR (Short Wave Infrared) imaging is an important imaging technology in space remote sensing. According to the characteristics of SWIR detector, the whole scheme of low noise imaging circuit is presented in this paper. For certain key circuit which noise is sensitive in the design, such as bias generation circuit, analysis of noise sources and calculation of theoretical noise value of actual circuit which is usually ignored in previous researches are proposed in order to estimate the level of circuit noise and optimize the circuit to reduce noise. The structure of analog filter amplifier circuit is also analyzed by introducing noise-factor analytic approach, based on the analysis result some design principles of the circuit are proposed. The noise suppression methods in the design are separately analyzed in both time suppression and space suppression; some specific methods for these two kinds of measures are listed in this paper. The final experiment results indicate that the low noise imaging circuit design based on above methods is reasonable and effective, the circuit has a higher SNR and can work normally at room temperature, and the whole design meets the original requirement of low noise. This low noise circuit for SWIR detector and its methods to analyze and calculate noise value are valuable examples for future similar designs.

  12. Nyquist AD Converters, Sensor Interfaces, and Robustness Advances in Analog Circuit Design, 2012

    CERN Document Server

    Baschirotto, Andrea; Steyaert, Michiel

    2013-01-01

    This book is based on the presentations during the 21st workshop on Advances in Analog Circuit Design.  Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity.  This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.  Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; Presents material in a tutorial-based format; Includes coverage of Nyquist A/D converters, capacitive sensor interfaces, reliability, variability, and connectivity.

  13. Designing TSVs for 3D Integrated Circuits

    CERN Document Server

    Khan, Nauman

    2013-01-01

    This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits.  It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks.  Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available....

  14. Digital Demodulation Algorithm for Multi-Tone FM Signal in New Type Track Circuit

    Institute of Scientific and Technical Information of China (English)

    ZHU Lin-xiao; WU Si-liang

    2006-01-01

    The multi-tone frequency modulation (FM) signal transferred through track circuit in automatic train control (ATC) system is analyzed. A digital filter with ideal sloping shape in frequency domain is designed for frequency discrimination. With this filter, the FM signal is converted into AM-FM signal by frequency-to-amplitude conversion. The modulating signal is finally extracted from the envelope of the AM-FM signal. Simulations show that the digital demodulation method could accurately recover the modulating signal in low signal noise ratio (SNR) circumstance, and has good performance in suppressing interference of harmonics of traction current frequency. The feasibility of the proposed method is proved in a hardware system based on SHARC DSP.

  15. Design of superconductor frame compression circuits

    Science.gov (United States)

    Sakurai, T.; Miyaho, N.; Miyahara, K.

    2007-10-01

    We proposed previously a novel interface circuit which was used between semiconductor data-input circuits and superconductor high-speed routers. The frame length of data packets is compressed in the interface circuit. Our proposed interface circuit has rather narrow timing margin. The problem was that our control circuit of the interface circuit could allow only very small timing delay. In this paper we propose a modified control circuit. We have improved the timing margin of the control circuit using RS-flip flop (RS-FF), where two shift registers and one control circuit are driven by clock pulses provided from a master clock-pulse generator. In this circuit, we have assumed fixed frame length packets. Our final target of master clock frequency is 100 GHz which will be realized with the device-parameter set of future advanced process. As the first step of realizing this target value, we aimed at 40 GHz clock operation with the conventional device-parameter set of NECs standard I process. The behavior of the whole frame compression circuit was simulated by a computer, and it was confirmed that it operated properly up to the master clock frequency of 23 GHz.

  16. Wireless transceiver circuits system perspectives and design aspects

    CERN Document Server

    Rhee, Woogeun

    2015-01-01

    This cutting-edge work contains comprehensive coverage of integrated circuit (IC) design for modern transceiver circuits and wireless systems. Ranging in scope from system perspectives to practical circuit design for emerging wireless applications, the book includes detailed discussions of transceiver architectures and system parameters, mm-wave circuits, ultra-low-power radios for biomedical and sensor applications, and the latest circuit techniques. Written by renowned international experts in IC industry and academia, the text is an ideal reference for engineers and researchers in the area

  17. Systeme digital : de l'algorithme au circuit

    OpenAIRE

    Vuillemin, Jean

    2014-01-01

    Licence; Plan1 Contexte historique . . . . . . . . . . . . . . . . . . . . . . . . . 2I Principes 271 Circuit math´ematique 291.1 Composants de base . . . . . . . . . . . . . . . . . . . . . . . . . 311.2 Forme des circuits digitaux synchrones . . . . . . . . . . . . . . . 351.3 Fonction des circuits . . . . . . . . . . . . . . . . . . . . . . . . 411.4 Montre digitale . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Alg`ebre binaire 572.1 Num´erations de position . . . . . . . . . ....

  18. Design of Asynchronous Sequential Circuits using Reversible Logic Gates

    Directory of Open Access Journals (Sweden)

    Bahram Dehghan

    2012-09-01

    Full Text Available In recent literature, Reversible logic has become one of the promising arena in low power dissipating circuit design in the past few years and has found its applications in low power CMOS circuits ,optical information processing and nanotechnology. The reversible circuits form the basic building block of quantum computers as all quantum operations are reversible. This paper presents asynchronoussequential circuits and circuits without hazard effect using reversible logic gates. I illustrate that we can produce AND, OR, NAND, NOR, EXOR and EXNOR outputs in one design using reversible logic gates. Also, I will evaluate the proposed circuits. The results show that reversible logic can be used to design these circuits. In this paper, the number of gates and garbage outputs is considered.

  19. Design of the Efficient Nanometric Reversible Subtractor Circuit

    Directory of Open Access Journals (Sweden)

    Mozhgan Shiri

    2012-11-01

    Full Text Available Reversible logic has comprehensive applications in communications, quantum computing, low power VLSI design, computer graphics, cryptography, nanotechnology, and optical computing. It has received significant attention in low power dissipating circuit design in the past few years. While several researchers have inspected the design of reversible logic units, there is not much reported works on reversible subtractors. In this paper we proposed the quantum equivalent circuit for SRK gate and we have computed the quantum cost of SRK gate. We also showed that how SRK gate can work singly as a half-subtractor circuit. It is being tried to design the circuit optimal in terms of number of reversible gates, number of garbage outputs, number of constant inputs, and quantum cost with compared to the existing circuits. At last we proposed an implementation of the new full-subtractor circuit based on SRK gate. All the designs have nanometric scales.

  20. Oscillator circuits frontiers in design, analysis and applications

    CERN Document Server

    2016-01-01

    This book surveys recent developments in the design, analysis and applications of oscillator circuit design. It highlights developments in the analysis of synchronization and wave phenomena, new analytical and design methods and their application, and novel engineering applications of oscillator circuits.

  1. RELATIONAL THEORY APPLICATION FOR OPTIMAL DESIGN OF INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    D. V. Demidov

    2014-09-01

    Full Text Available This paper deals with a method of relational theory adaptation for integrated circuits CAD systems. A new algorithm is worked out for optimal search of implicit Don’t Care values for combinational multiple-level digital circuits. The algorithm is described in terms of the adapted relational theory that gives the possibility for a very simple algorithm description for both intuitive understanding and formal analysis. The proposed method makes it possible to apply progressive experience of relational databases in efficient implementation of relational algebra operations (including distributed ones. Comparative analysis of the proposed algorithm and a classic one for optimal search of implicit Don’t Cares is carried out. The analysis has proved formal correctness of the proposed algorithm and its considerably less worst-case complexity. The search of implicit Don’t Care values in the integrated circuits design makes it easier to optimize such characteristics of IC as chip area, power, verifiability and reliability. However, the classic algorithm for optimal search of implicit Don’t Care values is not used in practice due to its very high computational complexity. Application of algorithms for sub-optimal search doesn’t give the possibility to realize the potential of IC optimization to the full. Implementation of the proposed algorithm in IC CAD (a.k.a., EDA systems is adequate due to much lower computational complexity, and potentially makes it possible to improve the quality-development time ratio of IC (chip area, power, verifiability and reliability. Developed method gives the possibility for creation of distributed EDA system with higher computational power and, consequently, for design automation of more complex IC.

  2. 77 FR 40381 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice...

    Science.gov (United States)

    2012-07-09

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice of Commission Determination Not To Review an Initial Determination Terminating the Investigation as...

  3. Analog circuit design structured mixed-mode design, multi-bit sigma-delta converters, short range RF circuits

    CERN Document Server

    van Roermund, Arthur

    2007-01-01

    Preface. Part I: Structured Mixed-Mode Design. Introduction. Structured Oscillator Design; C. Verhoeven, A. van Staveren. Systematic Design of High-frequency gm-C Filters; E. Lauwers, G. Gielen. Structured LNA Design; E.H. Nordholt. High-Level Simulation and Modeling Tools for Mixed-Signal Front-ends of Wireless Systems; P. Wambacq, et al. Structured Simulation-Based Analog Design Synthesis; R.A. Rutenbar. Structured Analog layout Design; K. Lampaert. Part II: Multi-Bit Sigma Delta Converters. Introduction. Architecture Considerations for Multi-Bit SigmaDelta ADCs; T. Brooks. Multirate Sigma-Delta Modulators, an Alternative to Multibit; F. Colodro, A. Torralba. Circuit Design Aspects of Multi-Bit Delta-Sigma Converters; Y. Geerts, et al. High-speed Digital to Analog Converter Issues with Applications to Sigma Delta Modulators; K. Doris, et al. Correction-Free Multi-Bit Sigma-Delta Modulators for ADSL; R. del Rio, et al. Sigma Delta Converters in Wireline Communications; A. Wiesbauer, et al. Part III: Short Ra...

  4. Application of the DRS4 Chip for GHz Waveform Digitizing Circuit

    CERN Document Server

    Yang, HaiBo; Kong, Jie; Cheng, Ke; Chen, JinDa; Du, ChengMing; Zhang, JingZhe

    2014-01-01

    At present, fast waveform digitizing circuit is more and more employed in modern physics experiments for processing the signals from an array detector. A new fast waveform sampling digitizing circuit developed by us is presented in this paper. Different with the traditional waveform digitizing circuit constructed with analog to digital converter(ADC) or time to digital converter(TDC), it is developed based on domino ring sampler(DRS), a switched capacitor array(SCA) chip. A DRS4 chip is used as a core device in our circuit, which has a fast sampling rate up to five gigabit samples per second (GSPS). The circuit has advantages of high resolution, low cost, low power dissipation, high channel density and small size. The quite satisfactory results are acquired by the preliminary performance test of this circuit board. Eight channels can be provided by one board, which has a 1-volt input dynamic range for each channel. The circuit linearity is better than 0.1%, the noise is less than 0.5 mV (root mean square, RMS...

  5. SEMICONDUCTOR INTEGRATED CIRCUITS: A high-performance, low-power σ Δ ADC for digital audio applications

    Science.gov (United States)

    Hao, Luo; Yan, Han; Cheung, Ray C. C.; Xiaoxia, Han; Shaoyu, Ma; Peng, Ying; Dazhong, Zhu

    2010-05-01

    A high-performance low-power σ Δ analog-to-digital converter (ADC) for digital audio applications is described. It consists of a 2-1 cascaded σ Δ modulator and a decimation filter. Various design optimizations are implemented in the system design, circuit implementation and layout design, including a high-overload-level coefficient-optimized modulator architecture, a power-efficient class A/AB operational transconductance amplifier, as well as a multi-stage decimation filter conserving area and power consumption. The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process. The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm2, which dissipates only 2.1 mA quiescent current in the analog circuits.

  6. Control theory applied to the design of AGC circuits

    OpenAIRE

    Bertran Albertí, Eduardo; Palacin, J M

    1991-01-01

    Applications of control theory in the design of automatic gain control (AGC) circuits are presented. A general model for AGC circuits is presented, and an equivalent linear system is proposed. Its behavior is compared with the dynamical response of two implemented AGC circuits. The results of classic and state variable correctors based on the model are presented. These results show the usefulness of this linear model in the design of the AGC dynamic response. By using a linear and t-variant s...

  7. Digital Games, Design, and Learning

    Science.gov (United States)

    Clark, Douglas B.; Tanner-Smith, Emily E.; Killingsworth, Stephen S.

    2016-01-01

    In this meta-analysis, we systematically reviewed research on digital games and learning for K–16 students. We synthesized comparisons of game versus nongame conditions (i.e., media comparisons) and comparisons of augmented games versus standard game designs (i.e., value-added comparisons). We used random-effects meta-regression models with robust variance estimates to summarize overall effects and explore potential moderator effects. Results from media comparisons indicated that digital games significantly enhanced student learning relative to nongame conditions (g¯ = 0.33, 95% confidence interval [0.19, 0.48], k = 57, n = 209). Results from value-added comparisons indicated significant learning benefits associated with augmented game designs (g¯ = 0.34, 95% confidence interval [0.17, 0.51], k = 20, n = 40). Moderator analyses demonstrated that effects varied across various game mechanics characteristics, visual and narrative characteristics, and research quality characteristics. Taken together, the results highlight the affordances of games for learning as well as the key role of design beyond medium. PMID:26937054

  8. Design and Development of New Digital Thermostat

    Institute of Scientific and Technical Information of China (English)

    DAI Xun-jiang; CHAO Qin

    2008-01-01

    The designed thermostat is based on the microcontroller featuring intelligence, programmable, environmental protection and power saving. The thermostat design is mainly composed of hardware and software design, the hardware includes the power supply circuit, temperature measurement circuit, humidity measurement circuit and backlight circuit; while the software design includes temperature measurement and compensation algorithm, moreover software flowchart is given as well. Finally the power supply circuit is simulated by the software of Pspice and the creative power stealing mode is verified by the simulation results. A target board is stuffed by hand with Pb-free electronic components and used to test hardware and debug software. Since the Pb-free components were used, power stealing mode is designed in hardware and temperature compensation algorithm is accomplished in software, and the thermostat is outstanding with its features of "green" and "power saving".

  9. Operational amplifier circuits analysis and design

    CERN Document Server

    Nelson, J C C

    1995-01-01

    This book, a revised and updated version of the author's Basic Operational Amplifiers (Butterworths 1986), enables the non-specialist to make effective use of readily available integrated circuit operational amplifiers for a range of applications, including instrumentation, signal generation and processing.It is assumed the reader has a background in the basic techniques of circuit analysis, particularly the use of j notation for reactive circuits, with a corresponding level of mathematical ability. The underlying theory is explained with sufficient but not excessive, detail. A range of compu

  10. Circuit design techniques for non-crystalline semiconductors

    CERN Document Server

    Sambandan, Sanjiv

    2012-01-01

    Despite significant progress in materials and fabrication technologies related to non-crystalline semiconductors, fundamental drawbacks continue to limit real-world application of these devices in electronic circuits. To help readers deal with problems such as low mobility and intrinsic time variant behavior, Circuit Design Techniques for Non-Crystalline Semiconductors outlines a systematic design approach, including circuit theory, enabling users to synthesize circuits without worrying about the details of device physics. This book: Offers examples of how self-assembly can be used as a powerf

  11. Design of delay insensitive circuits using multi-ring structures

    DEFF Research Database (Denmark)

    Sparsø, Jens; Staunstrup, Jørgen; Dantzer-Sørensen, Michael

    1992-01-01

    The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined...... into larger multi ring structures by the joining and forking of signals. The implementation is based on a small set of building blocks (latches, combinational circuits and switches) that are composed of C-elements and simple gates. By following this approach, delay insensitive circuits with nontrivial...

  12. Design of a DTCTGAL circuit and its application

    Institute of Scientific and Technical Information of China (English)

    Wang Pengjun; Li Kunpeng; Mei Fengna

    2009-01-01

    By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.

  13. Robust design of biological circuits: evolutionary systems biology approach.

    Science.gov (United States)

    Chen, Bor-Sen; Hsu, Chih-Yuan; Liou, Jing-Jia

    2011-01-01

    Artificial gene circuits have been proposed to be embedded into microbial cells that function as switches, timers, oscillators, and the Boolean logic gates. Building more complex systems from these basic gene circuit components is one key advance for biologic circuit design and synthetic biology. However, the behavior of bioengineered gene circuits remains unstable and uncertain. In this study, a nonlinear stochastic system is proposed to model the biological systems with intrinsic parameter fluctuations and environmental molecular noise from the cellular context in the host cell. Based on evolutionary systems biology algorithm, the design parameters of target gene circuits can evolve to specific values in order to robustly track a desired biologic function in spite of intrinsic and environmental noise. The fitness function is selected to be inversely proportional to the tracking error so that the evolutionary biological circuit can achieve the optimal tracking mimicking the evolutionary process of a gene circuit. Finally, several design examples are given in silico with the Monte Carlo simulation to illustrate the design procedure and to confirm the robust performance of the proposed design method. The result shows that the designed gene circuits can robustly track desired behaviors with minimal errors even with nontrivial intrinsic and external noise.

  14. Analog integrated circuits design for processing physiological signals.

    Science.gov (United States)

    Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

    2010-01-01

    Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

  15. Digital system design and application with VHDL and FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Gang; Jo, Yun Seok

    2002-09-15

    Contents of this book are digital system design modeling using VHDL like VHDL basics, writing VHDL for synthesis and VHDL environments, combinational logic design such as 4bit full adder and parallel combinational BCD multiplier sequential logic design, including Johnson counter, stop-watch, Dice game, traffic light controller, elevator controller and alarm clock, complex applications design like dynamic input/output circuit, PS/2 keyboard, LCD, VGA and UART. It also has a supplement about free license for ModelSim and Guide for 3100 X board user.

  16. Design Thinking for Digital Fabrication in Education

    DEFF Research Database (Denmark)

    Smith, Rachel Charlotte; Iversen, Ole Sejer; Hjorth, Mikkel

    2015-01-01

    In this paper, we argue that digital fabrication in education may benefit from design thinking, to foster a more profound understanding of digital fabrication processes among students. Two related studies of digital fabrication in education are presented in the paper. In an observational study we...... found that students (eleven to fifteen) lacked an understanding of the complexity of the digital fabrication process impeding on the potentials of digital fabrication in education. In a second explorative research through design study, we investigated how a focus on design thinking affected the students......’ performance in digital fabrication processes. Our findings indicate that design thinking can provide students with a general understanding of the creative and complex process through which artifacts and futures emerge in processes of digital fabrication....

  17. 25th workshop on Advances in Analog Circuit Design

    CERN Document Server

    Harpe, Pieter; Makinwa, Kofi

    2017-01-01

    This book is based on the 18 tutorials presented during the 25th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of continuous-time sigma-delta modulators, automotive electronics, and power management. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

  18. Designer cell signal processing circuits for biotechnology.

    Science.gov (United States)

    Bradley, Robert W; Wang, Baojun

    2015-12-25

    Microorganisms are able to respond effectively to diverse signals from their environment and internal metabolism owing to their inherent sophisticated information processing capacity. A central aim of synthetic biology is to control and reprogramme the signal processing pathways within living cells so as to realise repurposed, beneficial applications ranging from disease diagnosis and environmental sensing to chemical bioproduction. To date most examples of synthetic biological signal processing have been built based on digital information flow, though analogue computing is being developed to cope with more complex operations and larger sets of variables. Great progress has been made in expanding the categories of characterised biological components that can be used for cellular signal manipulation, thereby allowing synthetic biologists to more rationally programme increasingly complex behaviours into living cells. Here we present a current overview of the components and strategies that exist for designer cell signal processing and decision making, discuss how these have been implemented in prototype systems for therapeutic, environmental, and industrial biotechnological applications, and examine emerging challenges in this promising field.

  19. Sketching in digital clay: Digital sculpture for costume design visualization

    OpenAIRE

    Armstrong, Barry; Unver, Ertu; Taylor, Andrew

    2012-01-01

    Background\\ud ‘Costume Illustration in the Digital Age: Creating a Costume Technical Sheet’\\ud (Bradley, 2009) explores the benefits of using 2D digital character templates and drawing software to improve the visual quality and accurate communication of costume designs. This practice-based research expands upon Bradley’s work through the creation of 3D digital costume templates for use within 3D digital sculpture software.\\ud  \\ud Method: \\ud Problems are identified within existing costume vi...

  20. Direct-referencing Two-dimensional-array Digital Microfluidics Using Multi-layer Printed Circuit Board

    Science.gov (United States)

    Gong, Jian; Kim, Chang-Jin “CJ”

    2008-01-01

    Digital (i.e. droplet-based) microfluidics, by the electrowetting-on-dielectric (EWOD) mechanism, has shown great potential for a wide range of applications, such as lab-on-a-chip. While most reported EWOD chips use a series of electrode pads essentially in one-dimensional line pattern designed for specific tasks, the desired universal chips allowing user-reconfigurable paths would require the electrode pads in two-dimensional pattern. However, to electrically access the electrode pads independently, conductive lines need to be fabricated underneath the pads in multiple layers, raising a cost issue especially for disposable chip applications. In this article, we report the building of digital microfluidic plates based on a printed-circuit-board (PCB), in which multilayer electrical access lines were created inexpensively using mature PCB technology. However, due to its surface topography and roughness and resulting high resistance against droplet movement, as-fabricated PCB surfaces require unacceptably high (~500 V) voltages unless coated with or immersed in oil. Our goal is EWOD operations of aqueous droplets not only on oil-covered but also on dry surfaces. To meet varying levels of performances, three types of gradually complex post-PCB microfabrication processes are developed and evaluated. By introducing land-grid-array (LGA) sockets in the packaging, a scalable digital microfluidics system with reconfigurable and low-cost chip is also demonstrated. PMID:19234613

  1. Documentation of Stainless Steel Lithium Circuit Test Section Design. Suppl

    Science.gov (United States)

    Godfroy, Thomas J. (Compiler); Martin, James J.

    2010-01-01

    The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005. This supplement contains drawings, analysis, and calculations

  2. Documentation of Stainless Steel Lithium Circuit Test Section Design

    Science.gov (United States)

    Godfroy, T. J.; Martin, J. J.; Stewart, E. T.; Rhys, N. O.

    2010-01-01

    The Early Flight Fission-Test Facilities (EFF-TF) team was tasked by Naval Reactors Prime Contract Team (NRPCT) to design, fabricate, and test an actively pumped lithium (Li) flow circuit. This Li circuit takes advantage of work in progress at the EFF TF on a stainless steel sodium/potassium (NaK) circuit. The effort involved modifying the original stainless steel NaK circuit such that it could be operated with Li in place of NaK. This new design considered freeze/thaw issues and required the addition of an expansion tank and expansion/extrusion volumes in the circuit plumbing. Instrumentation has been specified for Li and circuit heaters have been placed throughout the design to ensure adequate operational temperatures and no uncontrolled freezing of the Li. All major components have been designed and fabricated prior to circuit redesign for Li and were not modified. Basic circuit components include: reactor segment, Li to gas heat exchanger, electromagnetic liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and trace heaters. The reactor segment, based on a Los Alamos National Laboratory 100-kW design study with 120 fuel pins, is the only prototypic component in the circuit. However, due to earlier funding constraints, a 37-pin partial-array of the core, including the central three rings of fuel pins (pin and flow path dimensions are the same as those in the full design), was selected for fabrication and test. This Technical Publication summarizes the design and integration of the pumped liquid metal Li flow circuit as of May 1, 2005.

  3. Application of the DRS4 chip for GHz waveform digitizing circuits

    Science.gov (United States)

    Yang, Hai-Bo; Su, Hong; Kong, Jie; Cheng, Ke; Chen, Jin-Da; Du, Cheng-Ming; Zhang, Jing-Zhe

    2015-05-01

    A new fast waveform sampling digitizing circuit based on the domino ring sampler (DRS), a switched capacitor array (SCA) chip, is presented in this paper, which is different from the traditional waveform digitizing circuit constructed with an analog to digital converter (ADC) or time to digital converter. A DRS4 chip is used as a core device in our circuit, which has a fast sampling rate up to five gigabit samples per second (GSPS). Quite satisfactory results are acquired by the preliminary performance test for this circuit board. Eight channels can be provided by one board, which has a 1 V input dynamic range for each channel. The circuit linearity is better than 0.1%, the noise is less than 0.5 mV (root mean square, RMS), and its time resolution is about 50 ps. Several boards can be cascaded to construct a multi-board system. The advantages of high resolution, low cost, low power dissipation, high channel density and small size make the circuit board useful not only for physics experiments, but also for other applications. Supported by National Natural Science Foundation of China (11305233), Specific Fund Research Based on Large-scale Science Instrument Facilities of China (2011YQ12009604)

  4. [Design of High Frequency Signal Detecting Circuit of Human Body Impedance Used for Ultrashort Wave Diathermy Apparatus].

    Science.gov (United States)

    Fan, Xu; Wang, Yunguang; Cheng, Haiping; Chong, Xiaochen

    2016-02-01

    The present circuit was designed to apply to human tissue impedance tuning and matching device in ultra-short wave treatment equipment. In order to judge if the optimum status of circuit parameter between energy emitter circuit and accepter circuit is in well syntony, we designed a high frequency envelope detect circuit to coordinate with automatic adjust device of accepter circuit, which would achieve the function of human tissue impedance matching and tuning. Using the sampling coil to receive the signal of amplitude-modulated wave, we compared the voltage signal of envelope detect circuit with electric current of energy emitter circuit. The result of experimental study was that the signal, which was transformed by the envelope detect circuit, was stable and could be recognized by low speed Analog to Digital Converter (ADC) and was proportional to the electric current signal of energy emitter circuit. It could be concluded that the voltage, transformed by envelope detect circuit can mirror the real circuit state of syntony and realize the function of human tissue impedance collecting.

  5. Parts & pools: a framework for modular design of synthetic gene circuits.

    Science.gov (United States)

    Marchisio, Mario Andrea

    2014-01-01

    Published in 2008, Parts & Pools represents one of the first attempts to conceptualize the modular design of bacterial synthetic gene circuits with Standard Biological Parts (DNA segments) and Pools of molecules referred to as common signal carriers (e.g., RNA polymerases and ribosomes). The original framework for modeling bacterial components and designing prokaryotic circuits evolved over the last years and brought, first, to the development of an algorithm for the automatic design of Boolean gene circuits. This is a remarkable achievement since gene digital circuits have a broad range of applications that goes from biosensors for health and environment care to computational devices. More recently, Parts & Pools was enabled to give a proper formal description of eukaryotic biological circuit components. This was possible by employing a rule-based modeling approach, a technique that permits a faithful calculation of all the species and reactions involved in complex systems such as eukaryotic cells and compartments. In this way, Parts & Pools is currently suitable for the visual and modular design of synthetic gene circuits in yeast and mammalian cells too.

  6. Circuit Design of Surface Acoustic Wave Based Micro Force Sensor

    Directory of Open Access Journals (Sweden)

    Yuanyuan Li

    2014-01-01

    Full Text Available Pressure sensors are commonly used in industrial production and mechanical system. However, resistance strain, piezoresistive sensor, and ceramic capacitive pressure sensors possess limitations, especially in micro force measurement. A surface acoustic wave (SAW based micro force sensor is designed in this paper, which is based on the theories of wavelet transform, SAW detection, and pierce oscillator circuits. Using lithium niobate as the basal material, a mathematical model is established to analyze the frequency, and a peripheral circuit is designed to measure the micro force. The SAW based micro force sensor is tested to show the reasonable design of detection circuit and the stability of frequency and amplitude.

  7. Design of 3D integrated circuits and systems

    CERN Document Server

    Sharma, Rohit

    2014-01-01

    Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

  8. Design of Integrated Circuits Approaching Terahertz Frequencies

    DEFF Research Database (Denmark)

    Yan, Lei

    In this thesis, monolithic microwave integrated circuits(MMICs) are presented for millimeter-wave and submillimeter-wave or terahertz(THz) applications. Millimeter-wave power generation from solid state devices is not only crucial for the emerging high data rate wireless communications but also...

  9. Design Centering and Yield Optimisation of MMIC’s with Off-Chip Digital Controllers

    OpenAIRE

    Centurelli, F.; Luzzi, R; Scotti, G.; Tommasino, P.; Trifiletti, A.

    2002-01-01

    In this paper, a new methodology to perform yield-oriented design of MMIC’s in III-V technologies is proposed. A digital control of MMIC bias, based on process parameters estimation by on-chip auxiliary circuits, allows yield enhancement. The design centering approach and a distance-dependent correlated statistical model of HEMT devices are used to design the external controller. The design of a MMIC for optical digital systems has highlighted significant yield improvement with respect to pre...

  10. Analog circuit design a tutorial guide to applications and solutions

    CERN Document Server

    Williams, Jim

    2011-01-01

    * Covers the fundamentals of linear/analog circuit and system design to guide engineers with their design challenges. * Based on the Application Notes of Linear Technology, the foremost designer of high performance analog products, readers will gain practical insights into design techniques and practice. * Broad range of topics, including power management tutorials, switching regulator design, linear regulator design, data conversion, signal conditioning, and high frequency/RF design. * Contributors include the leading lights in analog design, Robert Dobkin, Jim Willia

  11. State assignment approach to asynchronous CMOS circuit design

    Science.gov (United States)

    Kantabutra, Vitit; Andreou, Andreas G.

    1994-04-01

    We present a new algorithm for state assignment in asynchronous circuits so that for each circuit state transition, only one (secondary) state variable switches. No intermediate unstable states are used. The resultant circuits operate at optimum speed in terms of the number of transitions made and use only static CMOS gates. By reducing the number of switching events per state transition, noise due to the switching events is reduced and dynamic power dissipation may also be reduced. Our approach is suitable for asynchronous sequential circuits that are designed from flow tables or state transition diagrams. The proposed approach may also be useful for designing synchronous circuits, but explorations into the subject of clock power would be necessary to determine its usefulness.

  12. DESIGN OF TERNARY COUNTER BASED ON ADIABATIC DOMINO CIRCUIT

    Institute of Scientific and Technical Information of China (English)

    Yang Qiankun; Wang Pengjun; Zheng Xuesong

    2013-01-01

    By researching the ternary counter and low power circuit design method,a novel design of low power ternary Domino counter on switch-level is proposed.Firstly,the switch-level structure expression of ternary loop operation circuit with enable pin is derived according to the switch-signal theory,and the one bit ternary counter is obtained combining the ternary adiabatic Domino literal operation circuit and buffer.Then the switch-level structure expression of enable signal circuit is derived,and the four bits ternary counter is obtained by cascade connection.Finally,the circuit is simulated by Spice tool and the output waveforms transform in proper order indicating that the logic function is correct.The energy consumption of the four bits ternary adiabatic Domino counter is 63% less than the conventional Domino counterpart.

  13. Construction safety and digital design: a review

    OpenAIRE

    Zhou, Wei; Whyte, Jennifer; Sacks, Rafael

    2012-01-01

    As digital technologies become widely used in designing buildings and infrastructure, questions arise about\\ud their impacts on construction safety. This review explores relationships between construction safety and\\ud digital design practices with the aim of fostering and directing further research. It surveys state-of-the-art\\ud research on databases, virtual reality, geographic information systems, 4D CAD, building information\\ud modeling and sensing technologies, finding various digital t...

  14. Design of High Performance Dynamic CMOS Circuits in Deep Submicron Technology

    Directory of Open Access Journals (Sweden)

    Salendra.Govindarajulu

    2010-07-01

    Full Text Available Technology scaling of transistor feature size has provided a remarkable advancement in silicon industry for the last three decades. The demand and popularity of portable electronics is driving designers to strive for small silicon area, higher speeds, low power dissipation and reliability. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favoured in high performance designs because of the speed advantage offered over static CMOS logic circuits. This paper compares static CMOS, domino (dynamic logic design implementations of 16-bit Ripple carry adder, 16-bit Comparator and Linear Feedback Shift Register (LFSR in terms of CMOS layout power consumption, delay, power delay product, area for 65 nm and 45 nm technologies. The techniques are compared by performing detailed transistor simulations on benchmark circuits using Microwind 3 and DSCH3 CMOS layout CAD tools.

  15. Computer programs: Electronic circuit design criteria: A compilation

    Science.gov (United States)

    1973-01-01

    A Technology Utilization Program for the dissemination of information on technological developments which have potential utility outside the aerospace community is presented. The 21 items reported herein describe programs that are applicable to electronic circuit design procedures.

  16. 22nd Workshop on Advances in Analog Circuit Design

    CERN Document Server

    Makinwa, Kofi; Harpe, Pieter

    2014-01-01

    This book is based on the 18 tutorials presented during the 22nd workshop on Advances in Analog Circuit Design.  Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including frequency reference, power management for systems-on-chip, and smart wireless interfaces.  This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.    ·         Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; ·         Presents material in a tutorial-based format; ·         Includes coverage of frequency reference, power management for systems-on-chip, and smart wireless interfaces.

  17. Digital-analog quantum simulation of generalized Dicke models with superconducting circuits

    Science.gov (United States)

    Lamata, Lucas

    2017-01-01

    We propose a digital-analog quantum simulation of generalized Dicke models with superconducting circuits, including Fermi- Bose condensates, biased and pulsed Dicke models, for all regimes of light-matter coupling. We encode these classes of problems in a set of superconducting qubits coupled with a bosonic mode implemented by a transmission line resonator. Via digital-analog techniques, an efficient quantum simulation can be performed in state-of-the-art circuit quantum electrodynamics platforms, by suitable decomposition into analog qubit-bosonic blocks and collective single-qubit pulses through digital steps. Moreover, just a single global analog block would be needed during the whole protocol in most of the cases, superimposed with fast periodic pulses to rotate and detune the qubits. Therefore, a large number of digital steps may be attained with this approach, providing a reduced digital error. Additionally, the number of gates per digital step does not grow with the number of qubits, rendering the simulation efficient. This strategy paves the way for the scalable digital-analog quantum simulation of many-body dynamics involving bosonic modes and spin degrees of freedom with superconducting circuits. PMID:28256559

  18. Digital-analog quantum simulation of generalized Dicke models with superconducting circuits

    Science.gov (United States)

    Lamata, Lucas

    2017-03-01

    We propose a digital-analog quantum simulation of generalized Dicke models with superconducting circuits, including Fermi- Bose condensates, biased and pulsed Dicke models, for all regimes of light-matter coupling. We encode these classes of problems in a set of superconducting qubits coupled with a bosonic mode implemented by a transmission line resonator. Via digital-analog techniques, an efficient quantum simulation can be performed in state-of-the-art circuit quantum electrodynamics platforms, by suitable decomposition into analog qubit-bosonic blocks and collective single-qubit pulses through digital steps. Moreover, just a single global analog block would be needed during the whole protocol in most of the cases, superimposed with fast periodic pulses to rotate and detune the qubits. Therefore, a large number of digital steps may be attained with this approach, providing a reduced digital error. Additionally, the number of gates per digital step does not grow with the number of qubits, rendering the simulation efficient. This strategy paves the way for the scalable digital-analog quantum simulation of many-body dynamics involving bosonic modes and spin degrees of freedom with superconducting circuits.

  19. A New Design Methodology for Composing Complex Digital Systems

    Directory of Open Access Journals (Sweden)

    S.L. Chu

    2013-04-01

    Full Text Available Continuous growth in the use of multimedia applications on portable devices makes the mobile computer systems have an increasing complexity. The functionalities of the used SOC chips and silicon intelligent properties in these portable devices are become complicated and hard to design. Traditional digital circuit designs adopt register transfer level with timing control methodologies, which focus on the datapath composition, timing control of registers, and the functions of combinational circuits. However, the huge amount of control and synchronous signals of the above components are difficult to design and debug. The timing costs of design and verification are increased dramatically. This paper proposed a new design methodology of digital system, called data-oriented methodology, to deal with the above problems, by using Bluespec SystemVerilog HDL and the corresponding tools. Instead of conventional timing-control mechanism, the data-oriented methodology adopts simple handshaking protocol, blocking transferring, and explicitly register/FIFO declaration for communicating between adjacent modules. The designs of FDCT/IDCT and pipelined MIPS-like CPU are adopted to compare the design costs of conventional timing-control and data-oriented methodologies. The chip performance and FPGA proven of these two designs are discussed

  20. A New Design Methodology for Composing Complex Digital Systems

    Directory of Open Access Journals (Sweden)

    S. L. Chu

    2013-03-01

    Full Text Available Continuous growth in the use of multimedia applications on portable devices makes the mobile computer systemshave an increasing complexity. The functionalities of the used SOC chips and silicon intelligent properties in theseportable devices are become complicated and hard to design. Traditional digital circuit designs adopt register transferlevel with timing control methodologies, which focus on the datapath composition, timing control of registers, and thefunctions of combinational circuits. However, the huge amount of control and synchronous signals of the abovecomponents are difficult to design and debug. The timing costs of design and verification are increased dramatically.This paper proposed a new design methodology of digital system, called data-oriented methodology, to deal with theabove problems, by using Bluespec SystemVerilog HDL and the corresponding tools. Instead of conventional timingcontrolmechanism, the data-oriented methodology adopts simple handshaking protocol, blocking transferring, andexplicitly register/FIFO declaration for communicating between adjacent modules. The designs of FDCT/IDCT andpipelined MIPS-like CPU are adopted to compare the design costs of conventional timing-control and data-orientedmethodologies. The chip performance and FPGA proven of these two designs are discussed

  1. Designing meaningful intergenerational digital games

    NARCIS (Netherlands)

    Loos, Eugène|info:eu-repo/dai/nl/078758475

    2014-01-01

    This paper will focus on intergenerational digital games between grandparents and their grandchildren, which could enhance not only their physical and social well-being but also social bonding between them. This is a topic which has been neglected in digital game research. Therefore, after having

  2. Designing meaningful intergenerational digital games

    NARCIS (Netherlands)

    Loos, Eugène

    2014-01-01

    This paper will focus on intergenerational digital games between grandparents and their grandchildren, which could enhance not only their physical and social well-being but also social bonding between them. This is a topic which has been neglected in digital game research. Therefore, after having di

  3. Conceptual design of a versatile radiation tolerant integrated signal conditioning circuit for resistive sensors

    Energy Technology Data Exchange (ETDEWEB)

    Leroux, P. [Katholieke Hogeschool Kempen, Kleinhoefstraat 4, B-2440 Geel (Belgium); Katholieke Universiteit Leuven, Dept. ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee (Belgium); SCK-CEN, Belgian Nuclear Research Centre, Boeretang 200, B-2400 Mol (Belgium); Sterckx, J. [Katholieke Hogeschool Kempen, Kleinhoefstraat 4, B-2440 Geel (Belgium); Van Uffelen, M.; Damiani, C. [Fusion 4 Energy, Ed. B3, c/Josep, no 2, Torres Diagonal Litoral, 08019 Barcelona (Spain)

    2011-07-01

    This paper presents the design of a radiation tolerant configurable discrete time CMOS signal conditioning circuit for use with resistive sensors like strain gauge pressure sensors. The circuit is intended to be used for remote handling in harsh environments in the International Thermonuclear Experimental fusion Reactor (ITER). The design features a 5 V differential preamplifier using a Correlated Double Sampling (CDS) architecture at a sample rate of 20 kHz and a 24 V discrete time post amplifier. The gain is digitally controllable between 27 and 400 in the preamplifier and between 1 and 8 in the post amplifier. The nominal input referred noise voltage is only 8.5 {mu}V while consuming only 1 mW. The circuit has a simulated radiation tolerance of more than 1 MGy. (authors)

  4. Circuit Design: An inquiry lab activity at Maui Community College

    CERN Document Server

    Morzinski, Katie; Downs, Cooper; Favaloro, Tela; Park, Jung; U, Vivian

    2010-01-01

    We present an inquiry lab activity on Circuit Design that was conducted in Fall 2009 with first-year community college students majoring in Electrical Engineering Technology. This inquiry emphasized the use of engineering process skills, including circuit assembly and problem solving, while learning technical content. Content goals of the inquiry emphasized understanding voltage dividers (Kirchoff's voltage law) and analysis and optimization of resistive networks (Thevenin equivalence). We assumed prior exposure to series and parallel circuits and Ohm's law (the relationship between voltage, current, and resistance) and designed the inquiry to develop these skills. The inquiry utilized selection of engineering challenges on a specific circuit (the Wheatstone Bridge) to realize these learning goals. Students generated questions and observations during the starters, which were categorized into four engineering challenges or design goals. The students formed teams and chose one challenge to focus on during the i...

  5. Satisfactory Optimization Design of IIR Digital Filters

    Institute of Scientific and Technical Information of China (English)

    Jin Weidong; Zhang Gexiang; Zhao Duo

    2005-01-01

    A new method called satisfactory optimization method is proposed to design IIR (Infinite Impulse Response) digital filters, and the satisfactory optimization model is presented. The detailed algorithm of designing IIR digital filters using satisfactory optimization method is described. By using quantum genetic algorithm characterized by rapid convergence and good global search capability, the satisfying solutions are achieved in the experiment of designing lowpass and bandpass IIR digital filters. Experimental results show that the performances of IIR filters designed by the introduced method are better than those by traditional methods.

  6. Circuit bridging of digital equipment caused by smoke from a cable fire

    Energy Technology Data Exchange (ETDEWEB)

    Tanaka, T.J.; Anderson, D.J.

    1997-03-01

    Advanced reactor systems are likely to use protection systems with digital electronics that ideally should be resistant to environmental hazards, including smoke from possible cable fires. Previous smoke tests have shown that digital safety systems can fail even at relatively low levels of smoke density and that short-term failures are likely to be caused by circuit bridging. Experiments were performed to examine these failures, with a focus on component packaging and protection schemes. Circuit bridging, which causes increased leakage currents and arcs, was gauged by measuring leakage currents among the leads of component packages. The resistance among circuit leads typically varies over a wide range, depending on the nature of the circuitry between the pins, bias conditions, circuit board material, etc. Resistance between leads can be as low as 20 k{Omega} and still be good, depending on the component. For these tests, the authors chose a printed circuit board and components that normally have an interlead resistance above 10{sup 12} {Omega}, but if the circuit is exposed to smoke, circuit bridging causes the resistance to fall below 10{sup 3} {Omega}. Plated-through-hole (PTH) and surface-mounted (SMT) packages were exposed to a series of different smoke environments using a mixture of environmentally qualified cables for fuel. Conformal coatings and enclosures were tested as circuit protection methods. High fuel levels, high humidity, and high flaming burns were the conditions most likely to cause circuit bridging. The inexpensive conformal coating that was tested - an acrylic spray - reduced leakage currents, but enclosure in a chassis with a fan did not. PTH packages were more resistant to smoke-induced circuit bridging than SMT packages. Active components failed most often in tests where the leakage currents were high, but failure did not always accompany high leakage currents.

  7. A Web-Based Visualization and Animation Platform for Digital Logic Design

    Science.gov (United States)

    Shoufan, Abdulhadi; Lu, Zheng; Huss, Sorin A.

    2015-01-01

    This paper presents a web-based education platform for the visualization and animation of the digital logic design process. This includes the design of combinatorial circuits using logic gates, multiplexers, decoders, and look-up-tables as well as the design of finite state machines. Various configurations of finite state machines can be selected…

  8. Design of a high linearity and high gain accuracy analog baseband circuit for DAB receiver

    Science.gov (United States)

    Li, Ma; Zhigong, Wang; Jian, Xu; Yiqiang, Wu; Junliang, Wang; Mi, Tian; Jianping, Chen

    2015-02-01

    An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm RFCMOS process. The circuit comprises a 3rd-order active-RC complex filter (CF) and a programmable gain amplifier (PGA). An automatic tuning circuit is also designed to tune the CF's pass band. Instead of the class-A fully differential operational amplifier (FDOPA) adopted in the conventional CF and PGA design, a class-AB FDOPA is specially employed in this circuit to achieve a higher linearity and gain accuracy for its large current swing capability with lower static current consumption. In the PGA circuit, a novel DC offset cancellation technique based on the MOS resistor is introduced to reduce the settling time significantly. A reformative switching network is proposed, which can eliminate the switch resistor's influence on the gain accuracy of the PGA. The measurement result shows the gain range of the circuit is 10-50 dB with a 1-dB step size, and the gain accuracy is less than ±0.3 dB. The OIP3 is 23.3 dBm at the gain of 10 dB. Simulation results show that the settling time is reduced from 100 to 1 ms. The image band rejection is about 40 dB. It only draws 4.5 mA current from a 1.8 V supply voltage.

  9. Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

    Science.gov (United States)

    Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

    2015-11-01

    We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80-120%, with respect to the designed bias currents.

  10. Advances in genetic circuit design: novel biochemistries, deep part mining, and precision gene expression.

    Science.gov (United States)

    Nielsen, Alec A K; Segall-Shapiro, Thomas H; Voigt, Christopher A

    2013-12-01

    Cells use regulatory networks to perform computational operations to respond to their environment. Reliably manipulating such networks would be valuable for many applications in biotechnology; for example, in having genes turn on only under a defined set of conditions or implementing dynamic or temporal control of expression. Still, building such synthetic regulatory circuits remains one of the most difficult challenges in genetic engineering and as a result they have not found widespread application. Here, we review recent advances that address the key challenges in the forward design of genetic circuits. First, we look at new design concepts, including the construction of layered digital and analog circuits, and new approaches to control circuit response functions. Second, we review recent work to apply part mining and computational design to expand the number of regulators that can be used together within one cell. Finally, we describe new approaches to obtain precise gene expression and to reduce context dependence that will accelerate circuit design by more reliably balancing regulators while reducing toxicity. Copyright © 2013. Published by Elsevier Ltd.

  11. Designers' cognition in traditional versus digital media during conceptual design

    OpenAIRE

    Bilda, Zafer

    2001-01-01

    Cataloged from PDF version of article. Designers depend on representations to externalize their design thoughts. External representations are usually in the form of sketches (referred to as traditional media) in architectural design during the conceptual design. There are also attempts to integrate the use of digital representations into the conceptual design in order to construct a digital design medium. This thesis aims at gaining an insight on designers’ cognitive process...

  12. Computational design of nucleic acid feedback control circuits.

    Science.gov (United States)

    Yordanov, Boyan; Kim, Jongmin; Petersen, Rasmus L; Shudy, Angelina; Kulkarni, Vishwesh V; Phillips, Andrew

    2014-08-15

    The design of synthetic circuits for controlling molecular-scale processes is an important goal of synthetic biology, with potential applications in future in vitro and in vivo biotechnology. In this paper, we present a computational approach for designing feedback control circuits constructed from nucleic acids. Our approach relies on an existing methodology for expressing signal processing and control circuits as biomolecular reactions. We first extend the methodology so that circuits can be expressed using just two classes of reactions: catalysis and annihilation. We then propose implementations of these reactions in three distinct classes of nucleic acid circuits, which rely on DNA strand displacement, DNA enzyme and RNA enzyme mechanisms, respectively. We use these implementations to design a Proportional Integral controller, capable of regulating the output of a system according to a given reference signal, and discuss the trade-offs between the different approaches. As a proof of principle, we implement our methodology as an extension to a DNA strand displacement software tool, thus allowing a broad range of nucleic acid circuits to be designed and analyzed within a common modeling framework.

  13. A Powerful Optimization Tool for Analog Integrated Circuits Design

    Directory of Open Access Journals (Sweden)

    M. Kubar

    2013-09-01

    Full Text Available This paper presents a new optimization tool for analog circuit design. Proposed tool is based on the robust version of the differential evolution optimization method. Corners of technology, temperature, voltage and current supplies are taken into account during the optimization. That ensures robust resulting circuits. Those circuits usually do not need any schematic change and are ready for the layout.. The newly developed tool is implemented directly to the Cadence design environment to achieve very short setup time of the optimization task. The design automation procedure was enhanced by optimization watchdog feature. It was created to control optimization progress and moreover to reduce the search space to produce better design in shorter time. The optimization algorithm presented in this paper was successfully tested on several design examples.

  14. Design and Testing of Digital Microfluidic Biochips

    CERN Document Server

    Zhao, Yang

    2013-01-01

    This book provides a comprehensive methodology for automated design, test and diagnosis, and use of robust, low-cost, and manufacturable digital microfluidic systems. It focuses on the development of a comprehensive CAD optimization framework for digital microfluidic biochips that unifies different design problems. With the increase in system complexity and integration levels, biochip designers can utilize the design methods described in this book to evaluate different design alternatives, and carry out design-space exploration to obtain the best design point. Describes practical design automation tools that address different design problems (e.g., synthesis, droplet routing, control-pin mapping, testing and diagnosis, and error recovery) in a unified manner; Applies test pattern generation and error-recovery techniques for digital microfluidics-based biochips; Uses real bioassays as evaluation examples, e.g., multiplexed in vitro human physiological fluids diagnostics, PCR, protein crystallization.  

  15. Design of synthetic biological logic circuits based on evolutionary algorithm.

    Science.gov (United States)

    Chuang, Chia-Hua; Lin, Chun-Liang; Chang, Yen-Chang; Jennawasin, Tanagorn; Chen, Po-Kuei

    2013-08-01

    The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real-structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis-regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer-based modelling technology has been verified showing its great advantages in the purpose.

  16. Using Combinational Circuits for Control Purposes

    Directory of Open Access Journals (Sweden)

    Maher A. Nabulsi

    2009-01-01

    Full Text Available Problem statement: Combinational circuits are used in computers for generating binary control decisions and for providing digital components for data processing. Approach: The use of combinational circuits and logic gates to control other circuits was discussed. Different systems that use logic gates, multiplexers, decoders and encoders to control different circuits were presented. This study presented a design and implementation of some combinational circuits such as a decoder, an encoder, a multiplexer, a bus system and read/write memory operations. Results: When we connected some types of combinational circuits to the inputs/outputs of digital circuit, these combinational circuits can help us to manage and flow a different types of control signals through a large digital circuit. Conclusion: Many combinational circuits had a good function which can be used for controlling different parts of any digital system and they produce a suitable way to transfer a control signals between different digital components of any large digital system.

  17. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

    Science.gov (United States)

    Aull, Brian

    2016-04-08

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  18. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    Directory of Open Access Journals (Sweden)

    Brian Aull

    2016-04-01

    Full Text Available This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  19. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    OpenAIRE

    Brian Aull

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  20. A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit*

    Institute of Scientific and Technical Information of China (English)

    He Xiaofeng; Mo Taishan; Ma Chengyan; Ye Tianchun

    2011-01-01

    An analog/digital reconfigurable automatic gain control (AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What's more, a novel DC offset cancellation (DCOC) circuit with an HPCF (high pass cutoff frequency) less than 10 kHz is proposed. The AGC is fabricated by a 0.18 μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 × 300μm2.

  1. Logic design for array-based circuits a structured design methodology

    CERN Document Server

    White, D E

    1992-01-01

    This book will show you how to approach the design covering everything from the circuit specification to the final design acceptance, including what support you can expect, sizing, timing analysis, power and packaging, various simulations, design verification, and design submission.

  2. Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

    Directory of Open Access Journals (Sweden)

    Sudarshan Tiwari

    2012-05-01

    Full Text Available This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T logic circuits. Gate Diffusion Input (GDI technique of low-power digital combinatorial circuit design is also described. This technique helps inreducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Severalsimulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T based full adder designs in term of delay, power and powerdelay product (PDP compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP.

  3. Printed circuit board designer's reference basics

    CERN Document Server

    Robertson, Chris

    2003-01-01

    PCB design instruction and reference manual, all in one book, with in- depth explanation of the processes and tools used in modern PCB design Standards, formulas, definitions, and procedures, plus software to tie it all together.

  4. Readout circuit design of the retina-like CMOS image sensor

    Science.gov (United States)

    Cao, Fengmei; Song, Shengyu; Bai, Tingzhu; Cao, Nan

    2015-02-01

    Readout circuit is designed for a special retina-like CMOS image sensor. To realize the pixels timing drive and readout of the sensor, the Altera's Cyclone II FPGA is used as a control chip. The voltage of the sensor is supported by a voltage chip initialized by SPI with AVR MCU system. The analog image signal outputted by the sensor is converted to digital image data by 12-bits A/D converter ADS807 and the digital data is memorized in the SRAM. Using the Camera-link image grabber, the data stored in SRAM is transformed to image shown on PC. Experimental results show the circuit works well on retina-like CMOS timing drive and image readout and images can be displayed properly on the PC.

  5. Design and Implementation of A Circuit Board Calibration System

    Directory of Open Access Journals (Sweden)

    Bai Hang

    2016-01-01

    Full Text Available With the development of science and technology, the traditional artificial detection methods cannot meet the requirements of modern equipment testing and calibration. Combined with the actual demand, a kind of circuit boards calibration system are put forward. It can to realize automatic testing and calibration of the circuit boards. Many functions of the calibration system such as automatic testing, self-test and monitoring are summarized. The hardware is introduced which including the industrial computer system, calibration adapter and so on. Then, development platform, the thought of program design and the structure of the software are introduced in detail. The function of automatic calibration to specific circuit boards are realized. Because the system has good commonality and easy to extend to upgrade, the development ideas and experiences can be applied to similar circuit boards automatic testing system.

  6. Digital Production and Students as Learning Designers

    DEFF Research Database (Denmark)

    Sørensen, Birgitte Holm; Levinsen, Karin

    2014-01-01

    Today’s digitalization allows users to interact, collaborate, communicate and create user-generated content. The technology is intuitive and easy to use even for young children, and new learning opportunities emerge. Particularly, students’ production as a learning form benefits from digitalization...... as the new opportunities enable young students to integrate their playing competencies and skills into the formal school learning. This paper presents and discusses a theory regarding students’ digital production from a learning and design-for-learning perspective, which is generated based on the project...... and agency, and in the study, we have examined and found that students are capable of operating as learning designers....

  7. Wireless Communication Electronics Introduction to RF Circuits and Design Techniques

    CERN Document Server

    Sobot, Robert

    2012-01-01

    This book is intended for senior undergraduate and graduate students as well as practicing engineers who are involved in design and analysis of radio frequency (RF) circuits.  Detailed tutorials are included on all major topics required to understand fundamental principles behind both the main sub-circuits required to design an RF transceiver and the whole communication system. Starting with review of fundamental principles in electromagnetic (EM) transmission and signal propagation, through detailed practical analysis of RF amplifier, mixer, modulator, demodulator, and oscillator circuit topologies, all the way to the system communication theory behind the RF transceiver operation, this book systematically covers all relevant aspects in a way that is suitable for a single semester university level course.   Offers readers a complete, self-sufficient tutorial style textbook; Includes all relevant topics required to study and design an RF receiver in a consistent, coherent way with appropriate depth for a on...

  8. Low power RF circuit design in standard CMOS technology

    CERN Document Server

    Alvarado, Unai; Adín, Iñigo

    2012-01-01

    Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

  9. Introduction to logic circuits & logic design with verilog

    CERN Document Server

    LaMeres, Brock J

    2017-01-01

    This textbook for courses in Digital Systems Design introduces students to the fundamental hardware used in modern computers. Coverage includes both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). Using this textbook enables readers to design digital systems using the modern HDL approach, but they have a broad foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the presentation with learning Goals and assessment at its core. Each section addresses a specific learning outcome that the student should be able to “do” after its completion. The concept checks and exercise problems provide a rich set of assessment tools to measure student performance on ...

  10. Three-dimensional integrated circuit design

    CERN Document Server

    Xie, Yuan; Sapatnekar, Sachin S

    2009-01-01

    This book presents an overview of the field of 3D IC design, with an emphasis on electronic design automation (EDA) tools and algorithms that can enable the adoption of 3D ICs, and the architectural implementation and potential for future 3D system design. The aim of this book is to provide the reader with a complete understanding of: the promise of 3D ICs in building novel systems that enable the chip industry to continue along the path of performance scaling, the state of the art in fabrication technologies for 3D integration, the most prominent 3D-specific EDA challenges, along with solutio

  11. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  12. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  13. Digitally controlled oscillator design with a variable capacitance XOR gate

    Institute of Scientific and Technical Information of China (English)

    Manoj Kumar; Sandeep K. Arya; Sujata Pandey

    2011-01-01

    A digitally controlled oscillator (DCO) using a three-transistor XOR gate as the variable load has been presented.A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed.Three-,five- and seven-stage DCO circuits have been designed using the proposed delay cell.The output frequency is controlled digitally with bits applied to the delay cells.The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486-4.0267 GHz and 0.6121-0.3901 mW,respectively,with a change in the control word 1 1 1-000.The five-bit DCO achieves frequency and power of 1.8553-2.3506 GHz and 1.0202-0.6501 mW,respectively,with a change in the control word 11111-00000.Moreover,the seven-bit DCO shows a frequency and power consumption variation of 1.3239-1.6817 GHz and 1.4282-0.9102 m W,respectively,with a varying control word 1111111-0000000.The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements.

  14. Design and Implementation of a Digital Angular Rate Sensor

    Directory of Open Access Journals (Sweden)

    Zhen Peng

    2010-10-01

    Full Text Available With the aim of detecting the attitude of a rotating carrier, the paper presents a novel, digital angular rate sensor. The sensor consists of micro-sensing elements (gyroscope and accelerometer, signal processing circuit and micro-processor (DSP2812. The sensor has the feature of detecting three angular rates of a rotating carrier at the same time. The key techniques of the sensor, including sensing construction, sensing principles, and signal processing circuit design are presented. The test results show that the sensor can sense rolling, pitch and yaw angular rate at the same time and the measurement error of yaw (or pitch angular rate and rolling rate of the rotating carrier is less than 0.5%.

  15. Design and implementation of a digital angular rate sensor.

    Science.gov (United States)

    Wu, Li-Feng; Peng, Zhen; Zhang, Fu-Xue

    2010-01-01

    With the aim of detecting the attitude of a rotating carrier, the paper presents a novel, digital angular rate sensor. The sensor consists of micro-sensing elements (gyroscope and accelerometer), signal processing circuit and micro-processor (DSP2812). The sensor has the feature of detecting three angular rates of a rotating carrier at the same time. The key techniques of the sensor, including sensing construction, sensing principles, and signal processing circuit design are presented. The test results show that the sensor can sense rolling, pitch and yaw angular rate at the same time and the measurement error of yaw (or pitch) angular rate and rolling rate of the rotating carrier is less than 0.5%.

  16. Circuits and filters handbook

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi

  17. Essential knowledge for transistor-level LSI circuit design

    CERN Document Server

    Nakura, Toru

    2016-01-01

    This book is a collection of the miscellaneous knowledge essential for transistor-level LSI circuit design, summarized as the issues that need to be considered in each design step. To design an LSI that actually functions and to be able to properly measure it, an extremely large amount of diverse, detailed knowledge is necessary. Even though one may read a textbook about an op-amp, for example, the op-amp circuit design may not actually be possible to complete in one’s CAD tools. The first half of this text explains important design issues such as the operating principles of CAD tools, including schematic entry, SPICE simulation, layout and verification, and RC extraction. Then, mistake-prone topics for many circuit design beginners, resulting from their lack of consideration of these subjects, are explained including IO buffers, noise, and problems due to the progress of miniaturization. Following these topics, basic but very specialized issues for LSI circuit measurement are explained including measuremen...

  18. A Discrete Event System approach to On-line Testing of digital circuits with measurement limitation

    Directory of Open Access Journals (Sweden)

    P.K. Biswal

    2016-09-01

    Full Text Available In the present era of complex systems like avionics, industrial processes, electronic circuits, etc., on-the-fly or on-line fault detection is becoming necessary to provide uninterrupted services. Measurement limitation based fault detection schemes are applied to a wide range of systems because sensors cannot be deployed in all the locations from which measurements are required. This paper focuses towards On-Line Testing (OLT of faults in digital electronic circuits under measurement limitation using the theory of discrete event systems. Most of the techniques presented in the literature on OLT of digital circuits have emphasized on keeping the scheme non-intrusive, low area overhead, high fault coverage, low detection latency etc. However, minimizing tap points (i.e., measurement limitation of the circuit under test (CUT by the on-line tester was not considered. Minimizing tap points reduces load on the CUT and this reduces the area overhead of the tester. However, reduction in tap points compromises fault coverage and detection latency. This work studies the effect of minimizing tap points on fault coverage, detection latency and area overhead. Results on ISCAS89 benchmark circuits illustrate that measurement limitation have minimal impact on fault coverage and detection latency but reduces the area overhead of the tester. Further, it was also found that for a given detection latency and fault coverage, area overhead of the proposed scheme is lower compared to other similar schemes reported in the literature.

  19. Design of Multi-Valued Quaternary Based Analog-to-Digital Converter

    Directory of Open Access Journals (Sweden)

    A. H.M.Z. Alam

    2009-01-01

    Full Text Available Problem statement: The design of multi-valued quaternary based Analog-to-Digital Converter (ADC circuit was presented. The ADC generates multi-valued logic outputs rather than the conventional binary output system to overall reduction in circuit complexity and size. Approach: Design was implemented using pipeline ADC architecture and was simulated using model parameters based on standard 0.13 µm CMOS process. Results: Performance analysis of the design showed desirable performance parameters in terms of response, low power consumption, and a sampling rate of 10 MHz at a supply voltage of 1.3V was achieved. Conclusion/Recommendations: The ADC design was suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design.

  20. Design of Threshold Controller Based Chaotic Circuits

    DEFF Research Database (Denmark)

    Mohamed, I. Raja; Murali, K.; Sinha, Sudeshna

    2010-01-01

    We propose a very simple implementation of a second-order nonautonomous chaotic oscillator, using a threshold controller as the only source of nonlinearity. We demonstrate the efficacy and simplicity of our design through numerical and experimental results. Further, we show that this approach of ...

  1. Simple Digital Feed-Forward Circuit to Compensate for AOM Thermal Lensing

    Science.gov (United States)

    Hill, Joshua; Aman, James; Killian, Thomas; Neutral Experiment Team

    2016-05-01

    I demonstrate a simple digital feed-forward circuit which, when combined with two-frequency radio frequency (RF) electronics, maintains constant total RF power driving an acousto-optic modulator (AOM). Consistency in total power is desirable to mitigate thermal lensing effects that otherwise displace and misshape the laser beam when the primary frequency drive RF power is changed to, for example, alter the laser power in a diffracted beam. The Arduino-based feed-forward circuit is cost-effective, quick to implement, and easily modified.

  2. Digital Design of Virtual Prototype based on Multidisciplinary Design Optimization

    Institute of Scientific and Technical Information of China (English)

    WU Baogui; HUANG Hongzhong; TAO Ye

    2006-01-01

    In order to obtain digital design of complex mechanical product as optimal as possible in an efficient way, multidiscipline integrated design method is proposed, which integrates multidisciplinary design optimization (MDO) into digital design process to design virtual prototype (VP) efficiently. Through combining MDO and multi-body system dynamics, MDO integration platform, which takes VP as the core, is constructed. Then automated MDO design of VP is realized and changes of mechanical design project can be expressed intuitively during MDO design process. The proposed approach is also demonstrated by using integrated analyzing flow of vehicle engineering design. The result shows that the method not only can feasibly realize the MDO of VP, but also can solve the optimization problem of vehicle multi-body system dynamic performance. It can be adopted to the digital design of other complex system.

  3. Circuit design for the retina-like image sensor based on space-variant lens array

    Science.gov (United States)

    Gao, Hongxun; Hao, Qun; Jin, Xuefeng; Cao, Jie; Liu, Yue; Song, Yong; Fan, Fan

    2013-12-01

    Retina-like image sensor is based on the non-uniformity of the human eyes and the log-polar coordinate theory. It has advantages of high-quality data compression and redundant information elimination. However, retina-like image sensors based on the CMOS craft have drawbacks such as high cost, low sensitivity and signal outputting efficiency and updating inconvenience. Therefore, this paper proposes a retina-like image sensor based on space-variant lens array, focusing on the circuit design to provide circuit support to the whole system. The circuit includes the following parts: (1) A photo-detector array with a lens array to convert optical signals to electrical signals; (2) a strobe circuit for time-gating of the pixels and parallel paths for high-speed transmission of the data; (3) a high-precision digital potentiometer for the I-V conversion, ratio normalization and sensitivity adjustment, a programmable gain amplifier for automatic generation control(AGC), and a A/D converter for the A/D conversion in every path; (4) the digital data is displayed on LCD and stored temporarily in DDR2 SDRAM; (5) a USB port to transfer the data to PC; (6) the whole system is controlled by FPGA. This circuit has advantages as lower cost, larger pixels, updating convenience and higher signal outputting efficiency. Experiments have proved that the grayscale output of every pixel basically matches the target and a non-uniform image of the target is ideally achieved in real time. The circuit can provide adequate technical support to retina-like image sensors based on space-variant lens array.

  4. A digital-to-analog conversion circuit using third-order polynomial interpolation

    Science.gov (United States)

    Dotson, W. P., Jr.; Wilson, J. H.

    1972-01-01

    Zero- and third-order digital-to-analog conversion techniques are described, and the theoretical error performances are compared. The design equations and procedures for constructing a third-order digital-to-analog converter by using analog design elements are presented. Both a zero- and a third-order digital-to-analog converter were built, and the performances are compared with various signal inputs.

  5. Multiple Valued Logic for Synthesis and Simulation of Digital Circuits

    Directory of Open Access Journals (Sweden)

    Bharathi.S.L

    2015-04-01

    Full Text Available The Multiple valued logic(MVL has increased attention in the last decades because of the possibility to represent the information with more than two discrete levels.Advancing from two-valued to four-valued logic provides a progressive approach. In new technologies, the most delay and power occurs in the connections between gates. When designing a function using MVL, we need fewer gates,which implies less number of connections, then less delay. In the existing system, the 4:1 multiplexer is designed using the MVL logic and various paramaters are analysed. In the proposed system, the idea of designing a Barrel shifter using the multiple valued logic and the parameters are all analyzed. All these designs are verified using Modelsim simulator.

  6. Local Random Quantum Circuits are Approximate Polynomial-Designs

    Science.gov (United States)

    Brandão, Fernando G. S. L.; Harrow, Aram W.; Horodecki, Michał

    2016-09-01

    We prove that local random quantum circuits acting on n qubits composed of O( t 10 n 2) many nearest neighbor two-qubit gates form an approximate unitary t-design. Previously it was unknown whether random quantum circuits were a t-design for any t > 3. The proof is based on an interplay of techniques from quantum many-body theory, representation theory, and the theory of Markov chains. In particular we employ a result of Nachtergaele for lower bounding the spectral gap of frustration-free quantum local Hamiltonians; a quasi-orthogonality property of permutation matrices; a result of Oliveira which extends to the unitary group the path-coupling method for bounding the mixing time of random walks; and a result of Bourgain and Gamburd showing that dense subgroups of the special unitary group, composed of elements with algebraic entries, are ∞-copy tensor-product expanders. We also consider pseudo-randomness properties of local random quantum circuits of small depth and prove that circuits of depth O( t 10 n) constitute a quantum t-copy tensor-product expander. The proof also rests on techniques from quantum many-body theory, in particular on the detectability lemma of Aharonov, Arad, Landau, and Vazirani. We give applications of the results to cryptography, equilibration of closed quantum dynamics, and the generation of topological order. In particular we show the following pseudo-randomness property of generic quantum circuits: Almost every circuit U of size O( n k ) on n qubits cannot be distinguished from a Haar uniform unitary by circuits of size O( n ( k-9)/11) that are given oracle access to U.

  7. Robert Lacoste's the darker side practical applications for electronic design concepts from circuit cellar

    CERN Document Server

    Lacoste, Robert

    2009-01-01

    Robert Lacoste's The Darker Side column has quickly become a must read among Circuit Cellar devotees. His column provides readers with succinct theoretical concepts and practical applications on topics as far reaching as digital modulation to antenna basics. Difficult concepts are demystified as Robert shines a light on complex topics within electronic design.This book collects sixteen Darker Side articles that have been enriched with new, exclusive content from the author. An intro into The Darker Side will give examples of material that can enhance and optimize the way you design. A

  8. Radio frequency integrated circuit design for cognitive radio systems

    CERN Document Server

    Fahim, Amr

    2015-01-01

    This book fills a disconnect in the literature between Cognitive Radio systems and a detailed account of the circuit implementation and architectures required to implement such systems.  Throughout the book, requirements and constraints imposed by cognitive radio systems are emphasized when discussing the circuit implementation details.  In addition, this book details several novel concepts that advance state-of-the-art cognitive radio systems.  This is a valuable reference for anybody with background in analog and radio frequency (RF) integrated circuit design, needing to learn more about integrated circuits requirements and implementation for cognitive radio systems. ·         Describes in detail cognitive radio systems, as well as the circuit implementation and architectures required to implement them; ·         Serves as an excellent reference to state-of-the-art wideband transceiver design; ·         Emphasizes practical requirements and constraints imposed by cognitive radi...

  9. Analog Circuit Design Optimization Based on Evolutionary Algorithms

    Directory of Open Access Journals (Sweden)

    Mansour Barari

    2014-01-01

    Full Text Available This paper investigates an evolutionary-based designing system for automated sizing of analog integrated circuits (ICs. Two evolutionary algorithms, genetic algorithm and PSO (Parswal particle swarm optimization algorithm, are proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through specific electrical simulation, to the optimization system in the MATLAB environment, for the selected topology. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met. Comparisons with available methods like genetic algorithms show that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.

  10. Man-machine interactive system simplifies computer-aided circuit design

    Science.gov (United States)

    Bavuso, S. J.

    1970-01-01

    Langley interactive computerized circuit analysis capability /LICCA/ enables designer to draw electronic circuit diagrams on cathode ray tube screen. This information is submitted as input to user-selected circuit analysis program. LICCA accommodates binary logic circuits and circuits with discrete components, and monitors operator's instructions to detect errors.

  11. Digital Modeling and Shaping of Design Practices

    DEFF Research Database (Denmark)

    Reijonen, Satu

    This paper focuses on the role of digital modeling in shaping coordinative practices between architects and energy engineers in construction design. The paper presents a case study of the use of an energy performance calculation programme, a numeric digital modeling tool, that not only enables......, 2010), and the socio-material constructivist studies of technology (Akrich 1992, Akrich et al. 2000, Latour 1991). The programme influences the coordinative practices in following ways: it shapes the modus of interaction between energy engineers and architects and enforces particular jurisdictional...... of this study suggest that generative potential of digital modeling tools such as the calculation programme resides in their ability to restrictively define the possible roles in, focus of and sequence of working. In addition, digital modeling provides a separate medium with the help of which the design object...

  12. Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

    Energy Technology Data Exchange (ETDEWEB)

    Yamada, Takahiro, E-mail: yamada-takahiro@aist.go.jp [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Maezawa, Masaaki [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Urano, Chiharu [National Metrology Institute of Japan, National Institute of Advanced Industrial Science and Technology, Central 3, Umezono 1-1-1, Tsukuba, Ibaraki 305-8563 (Japan)

    2015-11-15

    Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

  13. Biomedically relevant circuit-design strategies in mammalian synthetic biology.

    Science.gov (United States)

    Bacchus, William; Aubel, Dominique; Fussenegger, Martin

    2013-01-01

    The development and progress in synthetic biology has been remarkable. Although still in its infancy, synthetic biology has achieved much during the past decade. Improvements in genetic circuit design have increased the potential for clinical applicability of synthetic biology research. What began as simple transcriptional gene switches has rapidly developed into a variety of complex regulatory circuits based on the transcriptional, translational and post-translational regulation. Instead of compounds with potential pharmacologic side effects, the inducer molecules now used are metabolites of the human body and even members of native cell signaling pathways. In this review, we address recent progress in mammalian synthetic biology circuit design and focus on how novel designs push synthetic biology toward clinical implementation. Groundbreaking research on the implementation of optogenetics and intercellular communications is addressed, as particularly optogenetics provides unprecedented opportunities for clinical application. Along with an increase in synthetic network complexity, multicellular systems are now being used to provide a platform for next-generation circuit design.

  14. Advanced Breakdown Modeling for Solid-State Circuit Design

    NARCIS (Netherlands)

    Milovanović, V.

    2010-01-01

    Modeling of the effects occurring outside the usual region of application of semiconductor devices is becoming more important with increasing demands set upon electronic systems for simultaneous speed and output power. Analog integrated circuit designers are forced to enter regimes of transistor ope

  15. FPGA Circuit Design Based on Xilinx ISE%基于Xilinx ISE平台的FPGA电路设计

    Institute of Scientific and Technical Information of China (English)

    于东阳; 苏彬

    2012-01-01

    Xilinx ISE is a tool set to design FPGA digital circuit. This tool set can make CPLD/FP-GA digital circuit layout facilely and fleetly. A calculate unit controlled by microinstruction is introduced to describe how to apply VHDL to designing FPGA circuit based on Xilinx.%Xilinx ISE集成综合环境是Xilinx公司的现场可编程逻辑器件数字电路开发工具集.其集成的工具可以使设计人员方便的完成CPLD/FPGA数字电路开发全过程.通过设计一个微指令控制的计算单元,描述基于ISE平台使用VHDL语言进行FPGA电路设计的原理和方法.

  16. Digital Hardware Design Teaching: An Alternative Approach

    Science.gov (United States)

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  17. Digital Hardware Design Teaching: An Alternative Approach

    Science.gov (United States)

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  18. Thermal Design of Power Electronic Circuits

    CERN Document Server

    Künzi, R

    2015-01-01

    The heart of every switched mode converter consists of several switching semiconductor elements. Due to their non-ideal behaviour there are ON state and switching losses heating up the silicon chip. That heat must effectively be transferred to the environment in order to prevent overheating or even destruction of the element. For a cost-effective design, the semiconductors should be operated close to their thermal limits. Unfortunately the chip temperature cannot be measured directly. Therefore a detailed understanding of how losses arise, including their quantitative estimation, is required. Furthermore, the heat paths to the environment must be understood in detail. This paper describes the main issues of loss generation and its transfer to the environment and how it can be estimated by the help of datasheets and/or experiments.

  19. Partially resonant active filter using the digital PWM control circuit with the DSP

    Energy Technology Data Exchange (ETDEWEB)

    Matsuo, Hirofumi; Kurokawa, Fujio; Luo, Zongxin; Makino, Yutaka; Ishizuka, Yoichi [Nagasaki Univ. (Japan); Oshikata, Tetsuya [Shindengen Elect. Mfg. Co. Ltd. (Japan)

    2000-07-01

    The partially resonant active filter, as a pre-regulator, using the digital PWM control circuit with the DSP is proposed to improve the power factor and input current harmonic distortion factor. The steady-state and dynamic characteristics of this active filter are analysed and the relationship among the circuit parameters, variables and performance characteristics such as the pre-regulation of the output voltage, input power factor, input current harmonic distortion, boundaries of stability and so forth are defined. Using the partially resonant active filter, the high power efficiency over 91% is obtained and the high frequency switching noise is suppressed. Also, the digital control with the DSP is versatile and consequently, the power factor over 0.99 and total harmonic distortion factor less than 1% are easily realized. (orig.)

  20. Design automation for integrated nonlinear logic circuits (Conference Presentation)

    Science.gov (United States)

    Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

    2016-05-01

    A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

  1. RF circuit design techniques for MF-UHF applications

    CERN Document Server

    Eroglu, Abdullah

    2013-01-01

    Magnetic resonance imaging, semiconductor processing, and RFID are some of the critical applications within the medium frequency (MF) to ultrahigh frequency (UHF) range that require RF designers to have a solid understanding of analytical and experimental RF techniques. Designers need to be able to design components and devices cost effectively, and integrate them with high efficiency, minimal loss, and required power. Computer-aided design (CAD) tools also play an important part in helping to reduce costs and improve accuracy through optimization. RF Circuit Design Techniques for MF-UHF Appli

  2. Design of Optoelectric Detection Circuit for Difference Absorption Gas Sensor

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    Since the gas infrared absorption spectrum linewidth is only several nanometers occupying the source intensity of several in a thousand, it is even less than the noise of light source. The signal of gas absorption is submerged in the noise, so it is impossible to measure the concentration of gas with spectrum absorption directly. According to the principle and parameters of difference absorption system of CH4 gas, a detection circuit consisted of the lock-in amplifier is designed. The experiment results indicated that the detection circuit can satisfy the demand of the whole system, and the limit concentration is 150×10-6.

  3. Design techniques for low-voltage analog integrated circuits

    Science.gov (United States)

    Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

    2017-08-01

    In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

  4. Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques

    CERN Document Server

    Neiroukh, Osama

    2011-01-01

    A new approach for enhancing the process-variation tolerance of digital circuits is described. We extend recent advances in statistical timing analysis into an optimization framework. Our objective is to reduce the performance variance of a technology-mapped circuit where delays across elements are represented by random variables which capture the manufacturing variations. We introduce the notion of statistical critical paths, which account for both means and variances of performance variation. An optimization engine is used to size gates with a goal of reducing the timing variance along the statistical critical paths. We apply a pair of nested statistical analysis methods deploying a slower more accurate approach for tracking statistical critical paths and a fast engine for evaluation of gate size assignments. We derive a new approximation for the max operation on random variables which is deployed for the faster inner engine. Circuit optimization is carried out using a gain-based algorithm that terminates w...

  5. Frontiers in Planar Lightwave Circuit Technology Design, Simulation, and Fabrication

    CERN Document Server

    Janz, Siegfried; Tanev, Stoyan

    2005-01-01

    This book is the result of the NATO Advanced Research Workshop on Frontiers in Planar Lightwave Circuit Technology, which took place in Ottawa, Canada from September 21-25, 2004. Many of the world’s leading experts in integrated photonic design, theory and experiment were invited to give lectures in their fields of expertise, and participate in discussions on current research and applications, as well as the new directions planar lightwave circuit technology is evolving towards. The sum of their contributions to this book constitutes an excellent record of many key issues and scientific problems in planar lightwave circuit research at the time of writing. In this volume the reader will find detailed overviews of experimental and theoretical work in high index contrast waveguide systems, micro-optical resonators, nonlinear optics, and advanced optical simulation methods, as well as articles describing emerging applications of integrated optics for medical and biological applications.

  6. Quantum circuit physical design methodology with emphasis on physical synthesis

    Science.gov (United States)

    Mohammadzadeh, Naser; Saheb Zamani, Morteza; Sedighi, Mehdi

    2013-11-01

    In our previous works, we have introduced the concept of "physical synthesis" as a method to consider the mutual effects of quantum circuit synthesis and physical design. While physical synthesis can involve various techniques to improve the characteristics of the resulting quantum circuit, we have proposed two techniques (namely gate exchanging and auxiliary qubit selection) to demonstrate the effectiveness of the physical synthesis. However, the previous contributions focused mainly on the physical synthesis concept, and the techniques were proposed only as a proof of concept. In this paper, we propose a methodological framework for physical synthesis that involves all previously proposed techniques along with a newly introduced one (called auxiliary qubit insertion). We will show that the entire flow can be seen as one monolithic methodology. The proposed methodology is analyzed using a large set of benchmarks. Experimental results show that the proposed methodology decreases the average latency of quantum circuits by about 36.81 % for the attempted benchmarks.

  7. Design of a biochemical circuit motif for learning linear functions.

    Science.gov (United States)

    Lakin, Matthew R; Minnich, Amanda; Lane, Terran; Stefanovic, Darko

    2014-12-06

    Learning and adaptive behaviour are fundamental biological processes. A key goal in the field of bioengineering is to develop biochemical circuit architectures with the ability to adapt to dynamic chemical environments. Here, we present a novel design for a biomolecular circuit capable of supervised learning of linear functions, using a model based on chemical reactions catalysed by DNAzymes. To achieve this, we propose a novel mechanism of maintaining and modifying internal state in biochemical systems, thereby advancing the state of the art in biomolecular circuit architecture. We use simulations to demonstrate that the circuit is capable of learning behaviour and assess its asymptotic learning performance, scalability and robustness to noise. Such circuits show great potential for building autonomous in vivo nanomedical devices. While such a biochemical system can tell us a great deal about the fundamentals of learning in living systems and may have broad applications in biomedicine (e.g. autonomous and adaptive drugs), it also offers some intriguing challenges and surprising behaviours from a machine learning perspective.

  8. A low-power 32-channel digitally programmable neural recording integrated circuit.

    Science.gov (United States)

    Wattanapanitch, W; Sarpeshkar, R

    2011-12-01

    We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier's input-referred noise to suit the background noise at the recording site. The amplifier's input-referred noise can be adjusted from 11.2 μVrms (total power of 5.4 μW) down to 5.4 μVrms (total power of 20 μW) in the spike-recording setting. The ADC in each recording module digitizes the a.c. signal input to each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel, with an average power consumption of 483 nW per channel, and, because of a.c. coupling, allows d.c. operation over a wide dynamic range. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented chip was successfully tested in an in vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 μ W. The neural amplifier and the ADC occupy areas of 0.03 mm(2) and 0.02 mm(2) respectively, making our design simultaneously area efficient and power efficient, thus enabling scaling to high channel-count systems.

  9. Digital design and verilog HDL fundamentals

    CERN Document Server

    Cavanagh, Joseph

    2011-01-01

    Comprehensive and self contained, this tutorial covers the design of a plethora of combinational and sequential logic circuits using conventional logic design and Verilog HDL. Number systems and number representations are presented along with various binary codes. Several advanced topics are covered, including functional decomposition and iterative networks. A variety of examples are provided for combinational and sequential logic, computer arithmetic, and advanced topics such as Hamming code error correction. Constructs supported by Verilog are described in detail. All designs are continued to completion. Each chapter includes numerous design issues of varying complexity to be resolved by the reader.

  10. Instrumentation and test gear circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Instrumentation and Test Gear Circuits Manual provides diagrams, graphs, tables, and discussions of several types of practical circuits. The practical circuits covered in this book include attenuators, bridges, scope trace doublers, timebases, and digital frequency meters. Chapter 1 discusses the basic instrumentation and test gear principles. Chapter 2 deals with the design of passive attenuators, and Chapter 3 with passive and active filter circuits. The subsequent chapters tackle 'bridge' circuits, analogue and digital metering techniques and circuitry, signal and waveform generation, and p

  11. A Parallel Genetic Algorithm for Automated Electronic Circuit Design

    Science.gov (United States)

    Long, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris

    2000-01-01

    Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency

  12. Printed Circuit Board Design (PCB) with HDL Designer

    Science.gov (United States)

    Winkert, Thomas K.; LaFourcade, Teresa

    2004-01-01

    Contents include the following: PCB design with HDL designer, design process and schematic capture - symbols and diagrams: 1. Motivation: time savings, money savings, simplicity. 2. Approach: use single tool PCB for FPGA design, more FPGA designs than PCB designers. 3. Use HDL designer for schematic capture.

  13. Design and Implementation of Wave Digital Filters

    Directory of Open Access Journals (Sweden)

    V. Davidek

    2001-09-01

    Full Text Available One of possibilities of the Wave Digital Filters (WDF design isusing the classical LC-filters theory. The aim of this paper is todemonstrate the design of WDF from the LC filter and the implementationof WDF on the fixed-point digital signal processor. The theory of wavedigital filter has been developed by using the classical scatteringparameter theory. The theory of ladder filters is well-known, and soour present problem can thus be reduced to a problem how to replace theL and C elements of the filters by adaptors and delay elements, addersand multipliers.

  14. Integrated Circuit Design in US High-Energy Physics

    CERN Document Server

    De Geronimo, G; Bebek, C; Garcia-Sciveres, M; Von der Lippe, H; Haller, G; Grillo, A A; Newcomer, M

    2013-01-01

    This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies...

  15. Design and Radiation Assessment of Optoelectronic Transceiver Circuits for ITER

    CERN Document Server

    Leroux, P; Van Uffelen, M; Steyaert, M

    2008-01-01

    The presented work describes the design and characterization results of different electronic building blocks for a MGy gamma radiation tolerant optoelectronic transceiver aiming at ITER applications. The circuits are implemented using the 70GHz fT SiGe HBT in a 0.35μm BiCMOS technology. A VCSEL driver circuit has been designed and measured up to a TID of 1.6 MGy and up to a bit rate of 622Mbps. No significant degradation is seen in the eye opening of the output signal. On the receiver side, both a 1GHz, 3kΩ transimpedance and a 5GHz Cherry-Hooper amplifier with over 20dB voltage gain have been designed.

  16. Electrostatic discharge current linear approach and circuit design method

    Energy Technology Data Exchange (ETDEWEB)

    Katsivelis, P. K.; Fotis, G. P.; Gonos, I. F.; Koussiouris, T. G.; Stathopulos, I. A. [School of Electrical and Computer Engineering, National Technical University of Athens, 9 Iroon Polytechniou Str., Zographou 157 80, Athens (Greece)

    2010-11-15

    The electrostatic discharge (ESD) phenomenon is a great threat to all electronic devices and ICs. An electric charge passing rapidly from a charged body to another can seriously harm the last one. However, there is a lack in a linear mathematical approach which will make it possible to design a circuit capable of producing such a sophisticated current waveform. The commonly accepted electrostatic discharge current waveform is the one set by the IEC 61000-4-2. However, the over-simplified circuit included in the same standard is incapable of producing such a waveform. Treating the electrostatic discharge current waveform of the IEC 61000-4-2 as reference, an approximation method, based on Prony's method, is developed and applied in order to obtain a linear system's response. Considering a known input, a method to design a circuit, able to generate this ESD current waveform in presented. The circuit synthesis assumes ideal active elements. A simulation is carried out using the PSpice software. (authors)

  17. Design of Low Power CMOS Circuits using Leakage Control Transistor and Multi-Threshold CMOS Techniques

    OpenAIRE

    2012-01-01

    The scaling down of technology in CMOS circuits, results in the down scaling of threshold voltage thereby increasing the sub-threshold leakage current. An IC consists of many circuits of which some circuits consists critical path like full adder, whereas some circuits like multiplexer and decoder has no specified critical path. LECTOR is a technique for designing leakage power reduced CMOS circuits without affecting the dynamic power dissipation, which can be used for circuits with no specifi...

  18. Flexible Simulation E-Learning Environment for Studying Digital Circuits and Possibilities for It Deployment as Semantic Web Service

    Science.gov (United States)

    Radoyska, P.; Ivanova, T.; Spasova, N.

    2011-01-01

    In this article we present a partially realized project for building a distributed learning environment for studying digital circuits Test and Diagnostics at TU-Sofia. We describe the main requirements for this environment, substantiate the developer platform choice, and present our simulation and circuit parameter calculation tools.…

  19. Flexible Simulation E-Learning Environment for Studying Digital Circuits and Possibilities for It Deployment as Semantic Web Service

    Science.gov (United States)

    Radoyska, P.; Ivanova, T.; Spasova, N.

    2011-01-01

    In this article we present a partially realized project for building a distributed learning environment for studying digital circuits Test and Diagnostics at TU-Sofia. We describe the main requirements for this environment, substantiate the developer platform choice, and present our simulation and circuit parameter calculation tools.…

  20. Interface design for digital courses

    NARCIS (Netherlands)

    Tabbers, H.; Kester, L.; Hummel, H.; Nadolski, R.; Jochems, W.; Merriënboer, J.; Koper, R.

    2003-01-01

    An important question in web-based education is how to deal with the design of the interface. What will the actual screen look like? Two main issues that are especially relevant for educational purposes are discussed, both from a Human-Computer Interaction and an Educational Psychology perspective.

  1. Digital Gaming and Sustainable Design

    Directory of Open Access Journals (Sweden)

    Shahin Vassigh

    2012-10-01

    Full Text Available The American building industry is one of the major consumers of energy. Buildings use 39% of thetotal energy consumed in the United States, significantly impacting national energy demand andcontributing to global warming. The vast majority of architectural practice in US leads to construction of buildings with a little concern to sustainability leading to environmental degradation. Although the bulk of architecture practice continues to produce unsustainable buildings, there is growing stream of exemplary models of sustainable design. Examining the success of suchpractices leads into two a two-folded finding; first that achieving sustainable design is closelylinked to “integrated Design”1 - a type of practice in which various disciplines involved in building design work together to achieve efficiency and other synergetic benefits. Second is that theadvances in computing and simulation algorithms are paving the way to achieve “integrateddesign”. These technologies are enabling the designers to collaborate, visualize, foresee, andmodify building performance with relatively high accuracy. They are increasing used to analyze complex systems to achieve streamlined structures, reduce dependence on mechanical systems, produce more effective construction processes, and reduce waste.If such practices were to become widespread, the architectural education needs to be restructured.The traditional American architectural curriculum that is based on a schism between“design” and “technology” is inherently in conflict with the principal of integration. Though largescalereform of architectural curricula is a complex, ongoing, and difficult debate; producing teaching tools that can simulate integrated design can impact and promote an understanding of sustainable practice in architecture. The proposed paper will present the progress of a multi-disciplinary team of faculty who arecollectively working on the completion, implementation and evaluation

  2. Design of Digital Adder Using Reversible Logic

    Directory of Open Access Journals (Sweden)

    Gowthami P

    2016-02-01

    Full Text Available Reversible logic circuits have promising applications in Quantum computing, Low power VLSI design, Nanotechnology, optical computing, DNA computing and Quantum dot cellular automata. In spite of them another main prominent application of reversible logic is Quantum computers where the quantum devices are essential which are ideally operated at ultra high speed with less power dissipation must be built from reversible logic components. This makes the reversible logic as a one of the most promising research areas in the past few decades. In VLSI design the delay is the one of the major issue along with area and power. This paper presents the implementation of Ripple Carry Adder (RCA circuits using reversible logic gates are discussed.

  3. APPLICATION SPECIFIC INTEGRATED CIRCUITS DESIGN AND IMPLEMENTATION OF RADEMACHER AND WALSH FUNCTIONS

    Directory of Open Access Journals (Sweden)

    A. Abbasi

    2013-01-01

    Full Text Available The orthogonal functions, specially the Rademacher and Walsh functions are being increasingly used in Digital Signal Processing (DSP. Today’s DSP applications require fast processing time in order to meet the challenges of the real time systems. State-of-the-art implementation technologies are therefore being used. This study describes the design and implementation of Rademacher and Walsh functions targeted to the state-of-the-art Cell Based Integrated Circuits (CBIC technology. High level design techniques are used with the help of advanced EDA tools from SYNOPSYS International. Optimized VHDL models have been developed and used for design entry. The design is thoroughly verified using advanced verifications tools. The design is implemented and processing has been done with 90 nm CMOS Technology from TSMC foundry. It is observed that the results obtained, are far better than the FPGA implementation reported earlier in the literature.

  4. Analysis and Evaluation of Statistical Models for Integrated Circuits Design

    Directory of Open Access Journals (Sweden)

    Sáenz-Noval J.J.

    2011-10-01

    Full Text Available Statistical models for integrated circuits (IC allow us to estimate the percentage of acceptable devices in the batch before fabrication. Actually, Pelgrom is the statistical model most accepted in the industry; however it was derived from a micrometer technology, which does not guarantee reliability in nanometric manufacturing processes. This work considers three of the most relevant statistical models in the industry and evaluates their limitations and advantages in analog design, so that the designer has a better criterion to make a choice. Moreover, it shows how several statistical models can be used for each one of the stages and design purposes.

  5. Design of digital systems and devices

    CERN Document Server

    Adamski, Marian; Wegrzyn, Marek

    2011-01-01

    This book includes a variety of design and test methods targeted on different digital devices, as well as different logic elements. The authors of the book represent such countries as Israel, Poland, Russia, and Ukraine. The book is divided by three main parts, including thirteen different Chapters.

  6. Designing and Managing Your Digital Library.

    Science.gov (United States)

    Guenther, Kim

    2000-01-01

    Discusses digital libraries and Web site design issues. Highlights include accessibility issues, including standards, markup languages like HTML and XML, and metadata; building virtual communities; the use of Web portals for customized delivery of information; quality assurance tools, including data mining; and determining user needs, including…

  7. High performance printed N and P-type OTFTs enabling digital and analog complementary circuits on flexible plastic substrate

    Science.gov (United States)

    Jacob, S.; Abdinia, S.; Benwadih, M.; Bablet, J.; Chartier, I.; Gwoziecki, R.; Cantatore, E.; van Roermund, A. H. M.; Maddiona, L.; Tramontana, F.; Maiellaro, G.; Mariucci, L.; Rapisarda, M.; Palmisano, G.; Coppard, R.

    2013-06-01

    This paper presents a printed organic complementary technology on flexible plastic substrate with high performance N and P-type Organic Thin Film Transistors (OTFTs), based on small-molecule organic semiconductors in solution. Challenges related to the integration of both OTFT types in a common complementary flow are addressed, showing the importance of surface treatments. Stability on single devices and on an elementary complementary digital circuit (ring oscillator) is studied, demonstrating that a robust and reliable flow with high electrical performances can be established for printed organic devices. These devices are used to manufacture several analog and digital building blocks. The design is carried out using a model specifically developed for this technology, and taking into account the parametric variability. High-frequency measurements of printed envelope detectors show improved speed performance, resulting from the high mobility of the OTFTs. In addition, a compact dynamic flip-flop and a low-offset comparator are demonstrated, thanks to availability of both n-type and p-type OTFTs in the technology. Measurement results are in good agreement with the simulations. The circuits presented establish a complete library of building blocks for the realization of a printed RFID tag.

  8. Cost Analysis of Different Digital Fir Filter Design Methods

    Directory of Open Access Journals (Sweden)

    Amninder Singh,

    2014-05-01

    Full Text Available FIR digital filters are widely used in the communication world. The implementation cost of filter circuit is counted by the number of multipliers & adders used, that decides the chip area. In this paper, design techniques of low pass FIR filter using the different windows are presented. The simulation is done in MATLAB. It is shown that filter designed using Hamming and Blackman windows are better than rest of the windows used. Out of two, Hamming window is better as its transition width is narrow, 0.019 than Blackman, 0.034. Further the performance analysis of Kaiser Window, Equiripple and Minimum phase filters was obtained, for same 0.04 transition width. There is a disparity in implementation cost & area. The minimum phase filter can be implemented with lesser number of filter coefficients with tolerable pass-band, stop-band ripples specifications.

  9. Multimedia foundations core concepts for digital design

    CERN Document Server

    Costello, Vic; Youngblood, Susan

    2012-01-01

    Understand the core concepts and skills of multimedia production and digital storytelling using text, graphics, photographs, sound, motion, and video. Then, put it all together using the skills that you have developed for effective project planning, collaboration, visual communication, and graphic design. Presented in full color with hundreds of vibrant illustrations, Multimedia Foundations trains you in the principles and skill sets common to all forms of digital media production, enabling you to create successful, engaging content, no matter what tools you are using. Companion website

  10. An Investigation of Digital Payment Platform Designs

    DEFF Research Database (Denmark)

    Kazan, Erol; Damsgaard, Jan

    2014-01-01

    platforms that combines platform, technology and business design aspects. The framework is applied to conduct a comparative case study of digital payment platforms. Four types of market actors are considered: banks, mobile network operators, merchants, and startups, which are incumbents and disrupters....... By hosting third-party services, payment instruments are evolving from single-purpose to multi-functional ones. Our research extends existing payment literature from the MSP perspective to emphasize certain digital payment platform components, which impact strategies and complementary products....

  11. Simulated Laboratory in Digital Logic.

    Science.gov (United States)

    Cleaver, Thomas G.

    Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…

  12. Research of Digital Circuit Robustness Based on Degeneracy%基于简并性的数字电路鲁棒性研究

    Institute of Scientific and Technical Information of China (English)

    侯海峰; 丁国良; 褚杰

    2014-01-01

    借鉴生物系统中的简并性理论,对数字电路的简并性进行了定义,并利用生物鲁棒度概念和简并性的计算方法,实现了数字电路的简并度度量与鲁棒性计算,通过实验分析了简并度、覆盖率、关键节点与电路鲁棒度的关系。实验结果表明,在数字电路冗余结构中,简并度越高,覆盖率越大,关键节点比例越小,电路的鲁棒度越高。为数字电路可靠性设计提供了一种新的技术途径。%The paper refers to the degeneracy theory in biology system,defines the digital circuit degeneracy and achieves the computation of digital circuit degeneracy and robustness with the concept of biological robustness and the computing method of degeneracy.The paper analyzes the relationship of degeneracy,cover rate,key nodes and digital circuit robustness via experiment.The result of experiment indicates that the higher degeneracy,the larger cover rate and the less the proportion of key nodes,the higher the digital circuit's robustness.The conclusion can provide a new technology approach for digital circuit reliability design.

  13. [Design of amplifier circuit for thermal conductivity detector in micro gas chromatography].

    Science.gov (United States)

    Liu, Hongfei; Chen, Zhong

    2010-08-01

    Agilent 3000 + is a typical micro gas chromatograph (micro GC) which is widely used for its fast analysis, high resolution, wide dynamic range and energy-efficient. However its amplifier circuit and analog-to-digital convertor (ADC) are of high power consumption and high working temperature. Based on the results of theoretical calculation, ADS1255, a 24-bit delta-sigma ADC from TI, was selected as the core component for its low noise and energy-efficient. Furthermore, a low noise, high common-mode voltage durable full differential amplifier circuit was designed to accomplish the functions of impedance matching, filtering, and level shifting in front of ADC. The full differential amplifier was optimized with the analysis of noise model and theoretical calculation. In addition, a testing platform was developed to test the full differential amplifier and ADC. The testing results showed that the American Society for Testing and Materials (ASTM) noise value of new full different amplifier and ADC was as low as 1.25 microV and the power dissipation was 3.7 W lower than that of the old circuit. The new circuit is low noise, energy-efficient, compact and cheap and can cater for the requirement of the micro GC of next generation.

  14. The Interface Circuit Design and Imitation Based on MAX+PLUSII

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    This paper introduces the design method of control system interface using VHDL hardware description language under the MAX+PLUSII working platform, Plans resources of the LPT circuit,and works out design programming of interface circuit and result imitation.

  15. Phase-locked loops. [in analog and digital circuits communication system

    Science.gov (United States)

    Gupta, S. C.

    1975-01-01

    An attempt to systematically outline the work done in the area of phase-locked loops which are now used in modern communication system design is presented. The analog phase-locked loops are well documented in several books but discrete, analog-digital, and digital phase-locked loop work is scattered. Apart from discussing the various analysis, design, and application aspects of phase-locked loops, a number of references are given in the bibliography.

  16. Noise-shaping gradient descent-based online adaptation algorithms for digital calibration of analog circuits.

    Science.gov (United States)

    Chakrabartty, Shantanu; Shaga, Ravi K; Aono, Kenji

    2013-04-01

    Analog circuits that are calibrated using digital-to-analog converters (DACs) use a digital signal processor-based algorithm for real-time adaptation and programming of system parameters. In this paper, we first show that this conventional framework for adaptation yields suboptimal calibration properties because of artifacts introduced by quantization noise. We then propose a novel online stochastic optimization algorithm called noise-shaping or ΣΔ gradient descent, which can shape the quantization noise out of the frequency regions spanning the parameter adaptation trajectories. As a result, the proposed algorithms demonstrate superior parameter search properties compared to floating-point gradient methods and better convergence properties than conventional quantized gradient-methods. In the second part of this paper, we apply the ΣΔ gradient descent algorithm to two examples of real-time digital calibration: 1) balancing and tracking of bias currents, and 2) frequency calibration of a band-pass Gm-C biquad filter biased in weak inversion. For each of these examples, the circuits have been prototyped in a 0.5-μm complementary metal-oxide-semiconductor process, and we demonstrate that the proposed algorithm is able to find the optimal solution even in the presence of spurious local minima, which are introduced by the nonlinear and non-monotonic response of calibration DACs.

  17. Principle and Method for Structural Design of Digital Woven Fabric

    Institute of Scientific and Technical Information of China (English)

    ZHOU Jiu; NG Frankie

    2006-01-01

    Digital woven textiles are one of the latest research areas of digital textiles. The key of research on design of digital woven fabrics lies in structural design. Nowadays, the application of digital design technology has fundamentally changed the concept of structural design of woven fabric,giving rise to design methods and effects that were deemed impossible before. A study has been carried out to analyze the nature of woven structures and the methods of structural design. This paper proposes an innovative principle and method of structural design under digital design concept, on which the design of digital gamut weaves and establishment of weave-database were presented to meet the requirement of balanced interlacement. It is envisaged that the results of this study will enhance future research in creation of digital woven fabrics, with particular emphasis on digital jacquard fabrics. Meanwhile, this study is also laid the foundation for the intelligent design of woven textile.

  18. Digital Production and Students as Learning Designers

    Directory of Open Access Journals (Sweden)

    Birgitte Holm Sørensen

    2014-12-01

    Full Text Available Today’s digitalization allows users to interact, collaborate, communicate and create user-generated content. The technology is intuitive and easy to use even for young children, and new learning opportunities emerge. Particularly, students’ production as a learning form benefits from digitalization as the new opportunities enable young students to integrate their playing competencies and skills into the formal school learning. This paper presents and discusses a theory regarding students’ digital production from a learning and design-for-learning perspective, which is generated based on the project Netbook 1:1 (2009–2012, where information and communication technology (ICT was readily accessible for each child at school and at home in grades 1–3 at two Danish public schools. The paper presents a Four Levels Design for Learning Model, which can be used for both design for learning and analyses of learning processes. The discussion is supported by empirical examples from the project, which explored emerging relations amongst ICT, production and subject matter-specific practice (Danish, mathematics and interdisciplinary activities. We understand design for learning as related to both process and agency, and in the study, we have examined and found that students are capable of operating as learning designers.

  19. Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

    KAUST Repository

    Hanna, Amir

    2015-12-04

    High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

  20. low crosstalk packaging design for Josephson logic circuits

    Energy Technology Data Exchange (ETDEWEB)

    Aoki, K.; Tazoh, Y.; Yoshikiyo, H.

    1985-03-01

    Theoretical and experimental studies are accomplished for inductive crosstalk noise reductions at Josephson chip-to-card connectors. This noise is induced by large AC power and high switching speed signal currents. The crosstalk mechanism was analyzed using a Partial Element Equivalent Circuits Model. Ground inductance causes not only crosstalk noise between connectors but also ground fluctuation noise inside the chip. This ground noise is large enough to cause false logic operations. Test chips and cards with improved connectors were produced for an experimental evaluation. Power crosstalk noise was measured using Josephson sampling circuits fabricated on the chip. The crosstalk noise - signal level ratio was less than 2.5%, when 250 MHz, 50 mA power currents were supplied. Crosstalk noise between neighboring signal connectors was also reduced to negligible level, including the worst case. These results favorably agree with calculations. This low crosstalk packaging design can be applied to high speed Josephson logic systems.

  1. Special design topics in digital wideband receivers

    CERN Document Server

    Tsui, James B Y

    2009-01-01

    Offering engineers a thorough examination of special, more advanced aspects of digital wideband receiver design, this practical book builds on fundamental resources on the topic, helping you gain a more comprehensive understanding of the subject. This in-depth volume presents a detailed look at a complete receiver design, including the encoder. Moreover, it discusses the detection of exotic signals and provides authoritative guidance on designing receivers used in electronic warfare. From frequency modulation and biphase shifting keys, to parameter encoders in electronic warfare receivers and

  2. ASIC design of a digital fuzzy system on chip for medical diagnostic applications.

    Science.gov (United States)

    Roy Chowdhury, Shubhajit; Roy, Aniruddha; Saha, Hiranmay

    2011-04-01

    The paper presents the ASIC design of a digital fuzzy logic circuit for medical diagnostic applications. The system on chip under consideration uses fuzzifier, memory and defuzzifier for fuzzifying the patient data, storing the membership function values and defuzzifying the membership function values to get the output decision. The proposed circuit uses triangular trapezoidal membership functions for fuzzification patients' data. For minimizing the transistor count, the proposed circuit uses 3T XOR gates and 8T adders for its design. The entire work has been carried out using TSMC 0.35 µm CMOS process. Post layout TSPICE simulation of the whole circuit indicates a delay of 31.27 ns and the average power dissipation of the system on chip is 123.49 mW which indicates a less delay and less power dissipation than the comparable embedded systems reported earlier.

  3. 100 Gbps Wireless System and Circuit Design Using Parallel Spread-Spectrum Sequencing

    Science.gov (United States)

    Scheytt, J. Christoph; Javed, Abdul Rehman; Bammidi, Eswara Rao; KrishneGowda, Karthik; Kallfass, Ingmar; Kraemer, Rolf

    2017-08-01

    In this article mixed analog/digital signal processing techniques based on parallel spread-spectrum sequencing (PSSS) and radio frequency (RF) carrier synchronization for ultra-broadband wireless communication are investigated on system and circuit level.

  4. The Moab Design for Digital Object Versioning

    Directory of Open Access Journals (Sweden)

    Richard Anderson

    2013-07-01

    Full Text Available The Stanford Digital Repository has adopted the "Moab" design for versioned archiving of digital objects--a locally developed approach that optimizes data transfer, storage, and replication while providing efficient single file retrieval or full object reconstruction for any version of an object. This paper includes a review of various versioning strategies including forward-delta, reverse-delta and content-addressable mechanisms, the pro's and cons of each, and highlights the relative advantages of the Moab design. In our approach, the fixity information of a file manifestation is used as its primary identifier and the filename is treated as metadata. Storage and retrieval of an object's files is faciliated by mapping between a virtual version inventory and the physical location via a file signature catalog.

  5. Automatic Circuit Design and Optimization Using Modified PSO Algorithm

    Directory of Open Access Journals (Sweden)

    Subhash Patel

    2016-04-01

    Full Text Available In this work, we have proposed modified PSO algorithm based optimizer for automatic circuit design. The performance of the modified PSO algorithm is compared with two other evolutionary algorithms namely ABC algorithm and standard PSO algorithm by designing two stage CMOS operational amplifier and bulk driven OTA in 130nm technology. The results show the robustness of the proposed algorithm. With modified PSO algorithm, the average design error for two stage op-amp is only 0.054% in contrast to 3.04% for standard PSO algorithm and 5.45% for ABC algorithm. For bulk driven OTA, average design error is 1.32% with MPSO compared to 4.70% with ABC algorithm and 5.63% with standard PSO algorithm.

  6. Design of Greenhouse Temperature and Light Intensity Control Circuit

    Institute of Scientific and Technical Information of China (English)

    Chao; ZHANG

    2014-01-01

    In view of domestic scientific and technological achievements at present,real-time control circuit for greenhouse temperature and light intensity has been designed in line with the principle of cost saving and easy control.With advanced temperature sensor and light sensor applied to measure the temperature and light intensity,an execution unit is controlled by single-chip microcomputer(SCM)to regulate the temperature and light intensity,creating a hardware design scheme and software design idea.In case of high temperature and high light intensity in greenhouse,the sunshade net will be put down and the blower will be started automatically;in case of low temperature and light intensity,the sunshade net will be folded up and the heating valve will be turned up automatically.In this way,the temperature and light intensity in greenhouse will be controlled within the designed range.

  7. Efficient Circuit Configuration for Enhancing Resolution of 8-bit flash Analog to Digital Convertor

    Directory of Open Access Journals (Sweden)

    Gururaj Balikatti

    2012-11-01

    Full Text Available The need constantly exists for converters with higher resolution, faster conversion speeds and lower power dissipation. High speed analog to digital converters (ADCs have been based on flash architecture, because all comparators sample the analog input voltage simultaneously, this ADC is thus inherently fast. Unfortunately flash ADC requires 2N - 1 comparators to convert N bit digital code from an analog sample. This makes flash ADCs unsuitable for high resolution applications. The focus of this paper is on efficient circuit configuration to enhance resolution of available 8-bit flash ADC, while maintaining number of comparators only 256 for 12 bit conversion. This technique optimizes the number of comparator requirements. In this approach, an 8-bit flash ADC partitions the analog input range into 256 quantization cells, separated by 255 boundary points. An 8-bit binary code 00000000 to 11111111 is assigned to each cell. The Microcontroller decides within which cell the input sample lies and assigns a 12-bit binary center code 000000000000 to 111111111111 according to the cell value. The exact 12-bit digital code is obtained by successive approximation technique. In this paper the focus will be on all-around efficient circuit for enhancing resolution of 8-bit Flash ADC. It is shown that by adopting this configuration, we can obtain 12-bit digital data just using 256 comparators. Therefore this technique is best suitable when high speed combined with high resolution is required. An experimental prototype of proposed 12-bit ADC was implemented using Philips P89V51RD2BN Microcontroller. Use of Microcontroller has greatly reduced the hardware requirement and cost. An ADC result of 12-bit prototype is presented. The results show that the ADC exhibits a maximum DNL of 0.52LSB and a maximum INL of 0.55LSB.

  8. Design and application of multilayer monolithic microwave integrated circuit transformers

    Energy Technology Data Exchange (ETDEWEB)

    Economides, S.B

    1999-07-01

    The design and performance of planar spiral transformers, using multilayer GaAs and silicon MMIC technology, are presented. This multilayer technology gives new opportunities for improving the performance of planar transformers, couplers and baluns. Planar transformers have high parasitic resistance and capacitance and low levels of coupling. Using multilayer technology these problems are overcome by applying a multilayer structure of three metal layers separated by two polyimide dielectric layers. The improvements gained by placing the conductors on different metal layers, and using conductors raised on polyimide layers for low capacitance, have been investigated. The circuits were fabricated using a novel experimental fabrication process, which uses entirely standard materials and techniques and is compatible with BJT's and silicon-germanium HBT's. The transformers were all characterised up to 20 GHz using RF-on-wafer measurements. They demonstrated good performance, considering the experimental nature of in-house multilayer technology and the difficulties in simulating these three-dimensional new geometries. With high resistivity substrates, the silicon components achieved virtually the same performance as their gallium arsenide counterparts. The transformers were then used in simulations of transformer-coupled HBT amplifier circuits, to demonstrate their capabilities. It was shown that these circuits present good performance compared to standard off-the shelf component circuits and are very promising for use in most multilayer MMIC applications. The structures were further used in coupling configurations, and applied in balun circuits and pushpull amplifiers. The spiral transformer coupler can operate at low frequencies without using up much chip area. In a balun configuration, the balun can compensate for coupling and phase imbalance and operates over 5 to 15 GHz. The spiral coupler does not always need multilayer processing, so the balun may be

  9. Design Multipurpose Circuits with Minimum Garbage Outputs Using CMVMIN Gate

    Directory of Open Access Journals (Sweden)

    Bahram Dehghan

    2014-01-01

    Full Text Available Quantum-dot cellular automata (QCA suggest an emerging computing paradigm for nanotechnology. The QCA offers novel approach in electronics for information processing and communication. QCA have recently become the focus of interest in the field of low power nanocomputing and nanotechnology. The fundamental logic elements of this technology are the majority voter (MV and the inverter (INV. This paper presents a novel design with less garbage output and minimum quantum cost in nanotechnology. In the paper we show how to create multipurpose reversible gates. By development of suitable gates in logic circuits as an example, we can combine MFA and HS in one design using CMVMIN gate. We offer CMVMIN gate implementations to be used in multipurpose circuit. We can produce concurrent half adder/subtractor and one bit comparator in one design using reversible logic gates and CMVMIN gates. Also, a 2×4 decoder from recent architecture has been shown independently. We investigate the result of the proposed design using truth table. A significant improvement in quality of the calculated parameters and variety of required outputs has been achieved.

  10. Design of arithmetic circuits in quantum dot cellular automata nanotechnology

    CERN Document Server

    Sridharan, K

    2015-01-01

    This research monograph focuses on the design of arithmetic circuits in Quantum Dot Cellular Automata (QCA). Using the fact that the 3-input majority gate is a primitive in QCA, the book sets out to discover hitherto unknown properties of majority logic in the context of arithmetic circuit designs. The pursuit for efficient adders in QCA takes two forms. One involves application of the new results in majority logic to existing adders. The second involves development of a custom adder for QCA technology. A QCA adder named as hybrid adder is proposed and it is shown that it outperforms existing multi-bit adders with respect to area and delay. The work is extended to the design of a low-complexity multiplier for signed numbers in QCA. Furthermore the book explores two aspects unique to QCA technology, namely thermal robustness and the role of interconnects. In addition, the book introduces the reader to QCA layout design and simulation using QCADesigner. Features & Benefits: This research-based book: ·  �...

  11. High performance integer arithmetic circuit design on FPGA architecture, implementation and design automation

    CERN Document Server

    Palchaudhuri, Ayan

    2016-01-01

    This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from us...

  12. Design of Timer Circuit for Dynamic Data System

    Science.gov (United States)

    Young, Nathaniel, III

    2004-01-01

    The Branch That I work in is in the Aero Electronic Test Branch, which is part of the Research and Testing Division. The Aero Electronic Test Branch deals with electronic control and instrumentation systems. This branch supports the research and test study of wind tunnels such as the l0x10,9x15, and 8x6. Wind tunnels are used in research to test certain parts of a jet, plane, shuttle or any other flying object in certain test conditions. My assignment is to design a programmable trigger circuit on a 19 standard rack mount that will allow the circuit to latch and hold for a predefined amount of time entered by the user when receiving a signal. It should then re-arm itself within 0.25 seconds after the time is finished. The time should be able to be seen on a display showing the time entered. The time range has to be from 0-600 seconds in 0.01 second increments (600.00). From the information given, counters will be needed to design and build this circuit. A counter, in it s simplest form, is a group of flip flops that can temporarily store bits of information put into the circuit. They can be constructed in many different ways, such as in 4 flip flops (4-bit counter) or 8 flip flops and even higher. Counters are usually cascaded with other counters to reach higher bits, such as 16 or 24 bit counters. The application in which I will use the counters will be to count down from any programmable number that I input either by a keyboard or a thumbwheel. Also, I will use counters that will be used specifically as a frequency divider to divide the pulses that enter the circuit through an input signal from a crystal clock. The pulses will need to be divided so that it will function as a 100Hz clock putting out 100 pulses per second. A switch will be used to load my inputs in and more than likely a button also so that I can stop and hold the count at any point of time. I will use 5 BCD up/down programmable counters, and a certain amount (depending on what kind of "divide by N

  13. Manufacturing Methods and Technology for Digital Fault Isolation for Printed Circuit Boards.

    Science.gov (United States)

    1979-08-25

    SOlE=2,ALL=3) IF PREVIOUS QUESTION IS NOT 1, 2). CAN SYNCHOCNOUS LOOPS BE BROKEN OR INTERRUPTED? .......... 0.0 SPECIFY ( JONHE =IMINODP =2,MEDIlI=3...Computer Science Press, Woodland Hills, CA 1976. CHANG H. Y., E. Manning, G. Metz. Fault Diagnosis of Digital Systems. Wiley - Interscience (1970...1969). HILL R. J. and G. R. Peterson. Digital Systems Hardware Organization and Design. Wiley , New York, 1973. 95 --- | J .1 JENSEN R. W. and M. D

  14. Design of an improved RCD buffer circuit for full bridge circuit

    Science.gov (United States)

    Yang, Wenyan; Wei, Xueye; Du, Yongbo; Hu, Liang; Zhang, Liwei; Zhang, Ou

    2017-05-01

    In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubber circuit with the improved RCD snubber circuit. By comparing and analyzing, it is proved that the improved buffer circuit can absorb surge voltage. Finally, experiments are demonstrated to validate that the correctness of the RC formula and the improved RCD snubber circuit.

  15. Integrated Digital Design Tool for Form Finding

    DEFF Research Database (Denmark)

    Kirkegaard, Poul Henning

    2009-01-01

    The present paper outlines the idea of a conceptual design tool which can be used in the early conceptual design phase. The tool is based on a parametric approach using Generative Components with embedded structural analysis. Each of these components uses the geometry, material properties and fixed...... point characteristics to calculate the dimensions and subsequent feasibility of any architectural design. The proposed conceptual design tool provides the possibility for the architect to work with both the aesthetic as well as the structural aspects of architecture without jumping from aesthetics...... to structural digital design tools and back, but to work with both simultaneously and real time. The engineering level of knowledge is incorporated at a conceptual thinking level, i.e. qualitative information is used in stead of using quantitative information. An example with a static determinate roof structure...

  16. Considerations on Circuit Design and Data Acquisition of a Portable Surface Plasmon Resonance Biosensing System.

    Science.gov (United States)

    Chang, Keke; Chen, Ruipeng; Wang, Shun; Li, Jianwei; Hu, Xinran; Liang, Hao; Cao, Baiqiong; Sun, Xiaohui; Ma, Liuzheng; Zhu, Juanhua; Jiang, Min; Hu, Jiandong

    2015-08-19

    The aim of this study was to develop a circuit for an inexpensive portable biosensing system based on surface plasmon resonance spectroscopy. This portable biosensing system designed for field use is characterized by a special structure which consists of a microfluidic cell incorporating a right angle prism functionalized with a biomolecular identification membrane, a laser line generator and a data acquisition circuit board. The data structure, data memory capacity and a line charge-coupled device (CCD) array with a driving circuit for collecting the photoelectric signals are intensively focused on and the high performance analog-to-digital (A/D) converter is comprehensively evaluated. The interface circuit and the photoelectric signal amplifier circuit are first studied to obtain the weak signals from the line CCD array in this experiment. Quantitative measurements for validating the sensitivity of the biosensing system were implemented using ethanol solutions of various concentrations indicated by volume fractions of 5%, 8%, 15%, 20%, 25%, and 30%, respectively, without a biomembrane immobilized on the surface of the SPR sensor. The experiments demonstrated that it is possible to detect a change in the refractive index of an ethanol solution with a sensitivity of 4.99838 × 10(5) ΔRU/RI in terms of the changes in delta response unit with refractive index using this SPR biosensing system, whereby the theoretical limit of detection of 3.3537 × 10(-5) refractive index unit (RIU) and a high linearity at the correlation coefficient of 0.98065. The results obtained from a series of tests confirmed the practicality of this cost-effective portable SPR biosensing system.

  17. Considerations on Circuit Design and Data Acquisition of a Portable Surface Plasmon Resonance Biosensing System

    Directory of Open Access Journals (Sweden)

    Keke Chang

    2015-08-01

    Full Text Available The aim of this study was to develop a circuit for an inexpensive portable biosensing system based on surface plasmon resonance spectroscopy. This portable biosensing system designed for field use is characterized by a special structure which consists of a microfluidic cell incorporating a right angle prism functionalized with a biomolecular identification membrane, a laser line generator and a data acquisition circuit board. The data structure, data memory capacity and a line charge-coupled device (CCD array with a driving circuit for collecting the photoelectric signals are intensively focused on and the high performance analog-to-digital (A/D converter is comprehensively evaluated. The interface circuit and the photoelectric signal amplifier circuit are first studied to obtain the weak signals from the line CCD array in this experiment. Quantitative measurements for validating the sensitivity of the biosensing system were implemented using ethanol solutions of various concentrations indicated by volume fractions of 5%, 8%, 15%, 20%, 25%, and 30%, respectively, without a biomembrane immobilized on the surface of the SPR sensor. The experiments demonstrated that it is possible to detect a change in the refractive index of an ethanol solution with a sensitivity of 4.99838 × 105 ΔRU/RI in terms of the changes in delta response unit with refractive index using this SPR biosensing system, whereby the theoretical limit of detection of 3.3537 × 10−5 refractive index unit (RIU and a high linearity at the correlation coefficient of 0.98065. The results obtained from a series of tests confirmed the practicality of this cost-effective portable SPR biosensing system.

  18. Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

    Science.gov (United States)

    Reagor, James A; Holt, David W

    2016-03-01

    Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

  19. Circuit design and exponential stabilization of memristive neural networks.

    Science.gov (United States)

    Wen, Shiping; Huang, Tingwen; Zeng, Zhigang; Chen, Yiran; Li, Peng

    2015-03-01

    This paper addresses the problem of circuit design and global exponential stabilization of memristive neural networks with time-varying delays and general activation functions. Based on the Lyapunov-Krasovskii functional method and free weighting matrix technique, a delay-dependent criteria for the global exponential stability and stabilization of memristive neural networks are derived in form of linear matrix inequalities (LMIs). Two numerical examples are elaborated to illustrate the characteristics of the results. It is noteworthy that the traditional assumptions on the boundness of the derivative of the time-varying delays are removed.

  20. Transceiver and system design for digital communications

    CERN Document Server

    Bullock, Scott

    2009-01-01

    Now in a 3rd edition, this successful book provides an intuitive approach to transceiver design, allowing a broad spectrum of readers to understand the topics clearly. It covers a wide range of data link communication design techniques, including link budgets, dynamic range and system analysis of receivers and transmitters used in data link communications, digital modulation and demodulation techniques of phase-shift keyed and frequency hopped spread spectrum systems using phase diagrams, multipath, gain control, an intuitive approach to probability, jamming reduction method using various adap

  1. Introduction to logic circuits & logic design with VHDL

    CERN Document Server

    LaMeres, Brock J

    2017-01-01

    This textbook introduces readers to the fundamental hardware used in modern computers. The only pre-requisite is algebra, so it can be taken by college freshman or sophomore students or even used in Advanced Placement courses in high school. This book presents both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). This textbook enables readers to design digital systems using the modern HDL approach while ensuring they have a solid foundation of knowledge of the underlying hardware and theory of their designs. This book is designed to match the way the material is actually taught in the classroom. Topics are presented in a manner which builds foundational knowledge before moving onto advanced topics. The author has designed the content with learning goals and assessment at its core. Each section addresses a specific learning outcome that the learner should be able to “do” after its completion...

  2. 30 CFR 75.907 - Design of trailing cables for medium-voltage circuits.

    Science.gov (United States)

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Design of trailing cables for medium-voltage... Medium-Voltage Alternating Current Circuits § 75.907 Design of trailing cables for medium-voltage circuits. Trailing cables for medium-voltage circuits shall include grounding conductors, a ground check...

  3. Design of Low Noise 16-bit CMOS Digitally Controlled Oscillator

    Directory of Open Access Journals (Sweden)

    Nitin Kumar

    2012-02-01

    Full Text Available In this paper, a new differential delay cell is proposed and 16-bit Digital Controlled Oscillator (DCO based on proposed delay cell is designed. The 16-bit DCO consist of 4-stages differential delay cell in ring structure and a digital control scheme has been used to improved noise characteristics. The structure of the DCO utilizes dual delay path techniques to achieve high oscillation frequency and awide tuning range. The DCO circuit has been simulated in SPICE with 0.5μm technology operating with supply voltage of 5V. DCO achieved a controllable frequency range of [1.7324-4.8649] GHz with a tuningrange of 3.1325GHz (≈64%. The measured output noise is -161.2dB/Hz and the total harmonic distortion have been found 75.4865dB with 6666H control word. The phase noise in proposed DCO design is -179.4dB/Hz at a frequency of 1.7324GHz.

  4. Microfluidic pneumatic logic circuits and digital pneumatic microprocessors for integrated microfluidic systems.

    Science.gov (United States)

    Rhee, Minsoung; Burns, Mark A

    2009-11-07

    We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprocessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner.

  5. Using digital electronic design flow to create a Genetic Design Automation tool.

    Science.gov (United States)

    Gendrault, Y; Madec, M; Wlotzko, V; Andraud, M; Lallement, C; Haiech, J

    2012-01-01

    Synthetic bio-systems become increasingly more complex and their development is lengthy and expensive. In the same way, in microelectronics, the design process of very complex circuits has benefited from many years of experience. It is now partly automated through Electronic Design Automation tools. Both areas present analogies that can be used to create a Genetic Design Automation tool inspired from EDA tools used in digital electronics. This tool would allow moving away from a totally manual design of bio-systems to assisted conception. This ambitious project is presented in this paper, with a deep focus on the tool that automatically generates models of bio-systems directly usable in electronic simulators.

  6. Design principles and realization of electro-optical circuit boards

    Science.gov (United States)

    Betschon, Felix; Lamprecht, Tobias; Halter, Markus; Beyer, Stefan; Peterson, Harry

    2013-02-01

    The manufacturing of electro-optical circuit boards (EOCB) is based to a large extent on established technologies. First products with embedded polymer waveguides are currently produced in series. The range of applications within the sensor and data communication markets is growing with the increasing maturity level. EOCBs require design flows, processes and techniques similar to existing printed circuit board (PCB) manufacturing and appropriate for optical signal transmission. A key aspect is the precise and automated assembly of active and passive optical components to the optical waveguides which has to be supported by the technology. The design flow is described after a short introduction into the build-up of EOCBs and the motivation for the usage of this technology within the different application fields. Basis for the design of EOCBs are the required optical signal transmission properties. Thereafter, the devices for the electro-optical conversion are chosen and the optical coupling approach is defined. Then, the planar optical elements (waveguides, splitters, couplers) are designed and simulated. This phase already requires co-design of the optical and electrical domain using novel design flows. The actual integration of an optical system into a PCB is shown in the last part. The optical layer is thereby laminated to the purely electrical PCB using a conventional PCB-lamination process to form the EOCB. The precise alignment of the various electrical and optical layers is thereby essential. Electrical vias are then generated, penetrating also the optical layer, to connect the individual electrical layers. Finally, the board has to be tested electrically and optically.

  7. The Challenges of Designing Digital Services for Multiple Mobile Platforms

    DEFF Research Database (Denmark)

    Ghazawneh, Ahmad

    2016-01-01

    to tap into and join the digital ecosystem. However, while there is an emerging literature on designing digital services, little empirical evidence exists about challenges faced by third-party developers while designing digital services, and in particular for multiple mobile platforms. Drawing......The value of digital services is increasingly recognized by owners of digital platforms. These services have central role in building and sustaining the business of the digital platform. In order to sustain the design of digital services, owners of digital platforms encourage third-party developers...... on a multiple case study of three mobile application development firms from Sweden, Denmark and Norway, we synthesize the digital service design taxonomy to understand the challenges faced by third-party developers. Our study identifies a set of challenges in four different levels: user level, platform level...

  8. Digital media and the beginning designer.

    Science.gov (United States)

    Goldman, Glenn

    2012-01-01

    Use and creation of computer graphics can be effectively taught to beginning design students in the context of discipline-specific design projects. In particular, a case study of the pedagogy implemented by the New Jersey Institute of Technology's College of Architecture + Design provides examples of how teachers harness the students' desire to create and provide educational opportunities for undergraduates to learn about the use of digital media in the processes and products of design. Employing a carefully constructed sequence, students are exposed to (and use) computer applications for raster imaging, vector drawing, 3D modeling and rendering, and eventually building information modeling and time-based sequential representation all while producing original work through analysis and synthesis.

  9. Digital design (Verilog) an embedded systems approach using Verilog

    CERN Document Server

    Ashenden, Peter J

    2007-01-01

    Digital Design: An Embedded Systems Approach Using Verilog provides a foundation in digital design for students in computer engineering, electrical engineering and computer science courses. It takes an up-to-date and modern approach of presenting digital logic design as an activity in a larger systems design context. Rather than focus on aspects of digital design that have little relevance in a realistic design context, this book concentrates on modern and evolving knowledge and design skills. Hardware description language (HDL)-based design and verification is emphasized--Veril

  10. Digital design (VHDL) an embedded systems approach using VHDL

    CERN Document Server

    Ashenden, Peter J

    2007-01-01

    Digital Design: An Embedded Systems Approach Using VHDL provides a foundation in digital design for students in computer engineering, electrical engineering and computer science courses. It takes an up-to-date and modern approach of presenting digital logic design as an activity in a larger systems design context. Rather than focus on aspects of digital design that have little relevance in a realistic design context, this book concentrates on modern and evolving knowledge and design skills. Hardware description language (HDL)-based design and verification is emphasized--VHDL exa

  11. High performance digital read out integrated circuit (DROIC) for infrared imaging

    Science.gov (United States)

    Mizuno, Genki; Olah, Robert; Oduor, Patrick; Dutta, Achyut K.; Dhar, Nibir K.

    2016-05-01

    Banpil Photonics has developed a high-performance Digital Read-Out Integrated Circuit (DROIC) for image sensors and camera systems targeting various military, industrial and commercial Infrared (IR) imaging applications. The on-chip digitization of the pixel output eliminates the necessity for an external analog-to-digital converter (ADC), which not only cuts costs, but also enables miniaturization of packaging to achieve SWaP-C camera systems. In addition, the DROIC offers new opportunities for greater on-chip processing intelligence that are not possible in conventional analog ROICs prevalent today. Conventional ROICs, which typically can enhance only one high performance attribute such as frame rate, power consumption or noise level, fail when simultaneously targeting the most aggressive performance requirements demanded in imaging applications today. Additionally, scaling analog readout circuits to meet such requirements leads to expensive, high-power consumption with large and complex systems that are untenable in the trend towards SWaP-C. We present the implementation of a VGA format (640x512 pixels 15μm pitch) capacitivetransimpedance amplifier (CTIA) DROIC architecture that incorporates a 12-bit ADC at the pixel level. The CTIA pixel input circuitry has two gain modes with programmable full-well capacity values of 100K e- and 500K e-. The DROIC has been developed with a system-on-chip architecture in mind, where all the timing and biasing are generated internally without requiring any critical external inputs. The chip is configurable with many parameters programmable through a serial programmable interface (SPI). It features a global shutter, low power, and high frame rates programmable from 30 up 500 frames per second in full VGA format supported through 24 LVDS outputs. This DROIC, suitable for hybridization with focal plane arrays (FPA) is ideal for high-performance uncooled camera applications ranging from near IR (NIR) and shortwave IR (SWIR) to mid

  12. Novel design of an all-cryogenic RF pound circuit

    DEFF Research Database (Denmark)

    Basu, Ronni; Wang, R. T.; Dick, G. J.

    2005-01-01

    We report on the design, construction and test of a new all-cryogenic RF Pound circuit used to stabilize a 100 MHz VCXO. Here, all active and passive RF components used to accomplish the phase modulation and detect a PM to AM conversion have been installed into the cryogenic environment. In conju......We report on the design, construction and test of a new all-cryogenic RF Pound circuit used to stabilize a 100 MHz VCXO. Here, all active and passive RF components used to accomplish the phase modulation and detect a PM to AM conversion have been installed into the cryogenic environment....... In conjunction with a high-Q cryogenic sapphire resonator a Pound discriminator sensitivity of 0.1 mV/Hz was seen experimentally. Based on this sensitivity and the noise properties of the pre-amplifier of the Pound signal, we calculate a limit of the oscillator's Allan deviation as low as 4middot10-16/radictau...

  13. A digital neuron-type processor and its VLSI design

    Science.gov (United States)

    Akel, H.; Habib, Mahmoud K.

    1989-05-01

    A set of neuron-type circuits elements based on logic gate circuits with multiinput multifan output capability is described. Three types of elements are introduced, one called the cell body with its dendritic inputs and synaptic junction, another representing the axon base, and the axon circuit. These three elements are cascaded to form a neuron-type processing element. The circuit performs input temporal and spatial summation as well as thresholding. The entire neuron circuit is simulated and a design is given using VSLI techniques.

  14. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Directory of Open Access Journals (Sweden)

    M. Elsobky

    2017-09-01

    Full Text Available Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI substrate to form a Hybrid System-in-Foil (HySiF, which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC. The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC, a differential difference amplifier (DDA, and a 10-bit successive approximation register (SAR ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  15. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Science.gov (United States)

    Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

    2017-09-01

    Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  16. SuperSpec: design concept and circuit simulations

    CERN Document Server

    Kovács, Attila; Bradford, Charles M; Chattopadhyay, Goutam; Day, Peter; Doyle, Simon; Hailey-Dunsheath, Steve; Hollister, Matthew; McKenney, Christopher; LeDuc, Henry G; Llombart, Nuria; Marrone, Daniel P; Mauskopf, Philip; O'Brient, Roger; Padin, Stephen; Swenson, Loren J; Zmuidzinas, Jonas; 10.1117/12.927160

    2012-01-01

    SuperSpec is a pathfinder for future lithographic spectrometer cameras, which promise to energize extra-galactic astrophysics at (sub)millimeter wavelengths: delivering 200--500 km/s spectral velocity resolution over an octave bandwidth for every pixel in a telescope's field of view. We present circuit simulations that prove the concept, which enables complete millimeter-band spectrometer devices in just a few square-millimeter footprint. We evaluate both single-stage and two-stage channelizing filter designs, which separate channels into an array of broad-band detectors, such as bolometers or kinetic inductance detector (KID) devices. We discuss to what degree losses (by radiation or by absorption in the dielectric) and fabrication tolerances affect the resolution or performance of such devices, and what steps we can take to mitigate the degradation. Such design studies help us formulate critical requirements on the materials and fabrication process, and help understand what practical limits currently exist ...

  17. CMOS Low Power Cell Library for Digital Design

    Directory of Open Access Journals (Sweden)

    Kanika Kaur

    2013-06-01

    Full Text Available Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since dynamic power is proportional to V2 dd and static power is proportional to Vdd, lowering the supply voltage and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required performance. In case of static power, the power is consumed during the steady state condition i.e when there are no input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized. Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel devices. In this paper we have been proposed the new CMOS library for the complex digital design using scaling the supply voltage and device dimensions and also suggest the methods to control the leakage current to obtain the minimum power dissipation at optimum value of supply voltage and transistor threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um and TSMC (90nm technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and simulations.

  18. 电磁耦合式位移传感器的直接数字解调电路设计%Design of direct digital demodulation circuit for electromagnetic coupling displacement sensor

    Institute of Scientific and Technical Information of China (English)

    杨睿; 程雪

    2014-01-01

    针对电磁耦合式位移传感器轴角位置的测量,采用了由旋转变压器AD2S80A构成的测角系统,介绍了其工作原理、硬件构成及相关参数的选择。研究了系统与DSP的接口设计,并提出了利用锁存器解决在读取AD2S80A时出现的延时问题,从而提高了伺服控制系统的实时性。%An angle measuring system based on resolver AD2S80A was used for measurement of shaft angle position of elec-tromagnetic coupling displacement sensor. The system working principles,hardware composition and correlative parameter are in-troduced. The design of interface between the system and DSP is researched. The latch is used to eliminate the time delay occur-ing when DSP reads AD2S80A data. Therefore,the real-time performance of the servo control system was improved.

  19. The Study of Tactical Missile's Airframe Digital Optimization Design

    Institute of Scientific and Technical Information of China (English)

    LUO Zhiqing; QIAN Airong; LI Xuefeng; GAO Lin; LEI Jian

    2006-01-01

    Digital design and optimal are very important in modern design. The traditional design methods and procedure are not fit for the modern missile weapons research and development. Digital design methods and optimal ideas were employed to deal with this problem. The disadvantages of the traditional missile's airframe design procedure and the advantages of the digital design methods were discussed. A new concept of design process reengineering (DPR) was put forward. An integrated missile airframe digital design platform and the digital design procedure, which integrated the optimization ideas and methods, were developed. Case study showed that the design platform and the design procedure could improve the efficiency and quality of missile's airframe design, and get the more reasonable and optimal results.

  20. Energy-aware design of digital systems

    Energy Technology Data Exchange (ETDEWEB)

    Gruian, F.

    2000-02-01

    Power and energy consumption are important issues in many digital applications, for reasons such as packaging cost and battery life-span. With the development of portable computing and communication, an increasing number of research groups are addressing power and energy related issues at various stages during the design process. Most of the work done in this area focuses on lower abstraction levels, such as gate or transistor level. Ideally, a power and energy-efficient design flow should consider the power and energy issues at every stage in the design process. Therefore, power and energy aware methods, applicable early in the design process are required. In this trend, the thesis presents two high-level design methods addressing power and energy consumption minimization. The first of the two approaches we describe, targets power consumption minimization during behavioral synthesis. This is carried out by minimizing the switching activity, while taking the correlations between signals into account. The second approach performs energy consumption minimization during system-level design, by choosing the most energy-efficient schedule and configuration of resources. Both methods make use of the constraint programming paradigm to model the problems in an elegant manner. The experimental results presented in this thesis show the impact of addressing the power and energy related issues early in the design process.

  1. Design of a Modular Signal Conditioning Circuit for Biopotential Sensors

    Directory of Open Access Journals (Sweden)

    Winncy Y. DU

    2010-09-01

    Full Text Available Biosignal conditioning (BC is critical in biomedical instruments because it directly affects measurement accuracy, reliability, and repeatability. BC also presents a great challenge due to the small amplitude of biosignals and their ease of corruption with noise and other disturbances. This paper describes a modular BC system developed for biopotential sensors that can preserve useful information while removing unwanted noise and interference components. This BC circuit includes an instrumentation amplifier, an active 1st-order high-pass filter with Sallen-Key configuration, a 5th-order low-pass Bessel filter, and a 2nd-order Twin-T notch filter. The order of these filters and the associated components in each filter can be easily changed to adapt to different biosignals (modular feature. Data acquisition and sampling were performed using a USB6009 module with a built-in A/D converter. Testing of a real electrocardiogram on the designed signal conditioning circuit demonstrated comparable outputs to commercial devices.

  2. Circuit Design for Sensor Detection Signal Conditioner Nitrate Content

    Directory of Open Access Journals (Sweden)

    Robeth Manurung

    2011-09-01

    Full Text Available Nitrate is one of macro nutrients very important for agriculture. The availability of nitrate in soil is limited because it is very easy to leaching by rain, therefore nitrate could be contaminated ground water by  over-process of fertilizer. This process could also produce inefficiency in agriculture if it happened continuesly without pre-analysis of farm field. The answer those problems, it is need to develop the ion sensor system to measure concentrations of nitrat in soil. The system is consist of nitrate ion sensor device, signal conditioning and data acquisition circuit. The design and fabrications of signal conditioning circuit which integrated into ion nitrate sensor system and will apply for agriculture. This sensor has been used amperometric with three electrodes configuration: working, reference  and auxiliarry; the ion senstive membrane has use conductive polymer. The screen printing technique has been choosen to fabricate electrodes and deposition technique for ion sensitive membrane is electropolymerization. The characterization of sensor has been conducted using nitrate standard solution with range of concentration between 1 µM–1 mM. The characterization has shown that sensor has a good response with cureent output between 2.8–4.71 µA, liniearity factor is 99.65% and time response 250 second.

  3. Design and implementation of a simple acousto optic dual control circuit

    Science.gov (United States)

    Li, Biqing; Li, Zhao

    2017-04-01

    This page proposed a simple light control circuit which designed by using power supply circuit, sonic circuits, electric circuit and delay circuit four parts. The main chip for CD4011, have inside of the four and to complete the sonic or circuit, electric, delay logic circuit. During the day, no matter how much a pedestrian voice, is ever shine light bulb. Dark night, circuit in a body to make the microphone as long as testing noise, and will automatically be bright for pedestrians lighting, several minutes after the automatic and put out, effective energy saving. Applicable scope and the working principle of the circuit principle diagram and given device parameters selection, power saving effect is obvious, at the same time greatly reduce the maintenance quantity, saving money, use effect is good.

  4. On the SCTC-OCTC Method for the Analysis and Design of Circuits

    Science.gov (United States)

    Salvatori, S.; Conte, G.

    2009-01-01

    This paper discusses guidelines that emphasize the relevance of short-circuit- and open-circuit-time constant (SCTC and OCTC, respectively) methods in the analysis and design of electronic amplifiers. It is demonstrated that it is only necessary to grasp a few concepts in order to understand that the two short- and open-circuit cases fall into a…

  5. Testing Cross-Talk Induced Delay Faults in Digital Circuit Based on Transient Current Analysis

    Institute of Scientific and Technical Information of China (English)

    WANG Youren; DENG Xiaoqian; CUI Jiang; YAO Rui; ZHANG Zhai

    2006-01-01

    The delay fault induced by cross-talk effect is one of the difficult problems in the fault diagnosis of digital circuit. An intelligent fault diagnosis based on IDDT testing and support vector machines (SVM) classifier was proposed in this paper. Firstly, the fault model induced by cross-talk effect and the IDDT testing method were analyzed, and then a delay fault localization method based on SVM was presented. The fault features of the sampled signals were extracted by wavelet packet decomposition and served as input parameters of SVM classifier to classify the different fault types. The simulation results illustrate that the method presented is accurate and effective, reaches a high diagnosis rate above 95%.

  6. A 750 MHz semi-digital clock and data recovery circuit with 10-12 BER

    Institute of Scientific and Technical Information of China (English)

    Wei Xueming; Wang Yiwen; Li Ping; Luo Heping

    2011-01-01

    A semi-digital clock and data recovery(CDR)is presented.In order to lower CDR trace jitter and decrease loop latency,an average-based phase detection algorithm is adopted and realized with a novel circuit.Implemented in a 0.13 μm standard 1P8M CMOS process,our CDR is integrated into a high speed serial and de-serial(SERDES)chip.Measurement results of the chip show that the CDR can trace the phase of the input data well and the RMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency,while the bit error rate of the recovery data is less than 10 × 10-12.

  7. The Design and Application of the Digital Backpack

    Science.gov (United States)

    Basham, James D.; Meyer, Helen; Perry, Ernest

    2010-01-01

    In this study, we introduce the digital backpack as a means for creating a rich learning experience for students of multiple ages. Development, design, and refinement of the digital backpack are grounded in the theoretical framework of Universal Design for Learning using a Design-Based Research (DBR) model. This article presents the design and…

  8. Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

    Science.gov (United States)

    Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

    2011-07-01

    This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

  9. IIP framework: A tool for reuse-centric analog circuit design

    OpenAIRE

    2016-01-01

    Current design of analog integrated circuits is still a time-consuming manual process resulting in static analog blocks which can hardly be reused. In order to address this problem, a new framework to ease reuse-centric bottom-up design of analog integrated circuits is introduced. Our IIP Framework (IIP: Intelligent Intellectual Property) enables the development of highly technology-independent analog circuit generators applicable in multiple design environments. IIP Generators are parameteri...

  10. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  11. SEMICONDUCTOR INTEGRATED CIRCUITS: Sigma-delta modulator modeling analysis and design

    Science.gov (United States)

    Binjie, Ge; Xin'an, Wang; Xing, Zhang; Xiaoxing, Feng; Qingqin, Wang

    2010-09-01

    This paper introduces a new method for SC sigma-delta modulator modeling. It studies the integrator's different equivalent circuits in the integrating and sampling phases. This model uses the OP-AMP input pair's tail current (I0) and overdrive voltage (von) as variables. The modulator's static and dynamic errors are analyzed. A group of optimized I0 and von for maximum SNR and power × area ratio can be obtained through this model. As examples, a MASH21 modulator for digital audio and a second order modulator for RFID baseband are implemented and tested, and they can achieve 91 dB and 72 dB respectively, which verifies the modeling and design criteria.

  12. Hardware/software co-design and optimization for cyberphysical integration in digital microfluidic biochips

    CERN Document Server

    Luo, Yan; Ho, Tsung-Yi

    2015-01-01

    This book describes a comprehensive framework for hardware/software co-design, optimization, and use of robust, low-cost, and cyberphysical digital microfluidic systems. Readers with a background in electronic design automation will find this book to be a valuable reference for leveraging conventional VLSI CAD techniques for emerging technologies, e.g., biochips or bioMEMS. Readers from the circuit/system design community will benefit from methods presented to extend design and testing techniques from microelectronics to mixed-technology microsystems. For readers from the microfluidics domain,

  13. 2-D electromagnetic simulation of passive microstrip circuits

    CERN Document Server

    Dueñas Jiménez, Alejandro

    2009-01-01

    A reference for circuit design engineers and microwave engineers. It uses a simple 2-D electromagnetic simulation procedure to provide basic knowledge and practical insight into quotidian problems of microstrip passive circuits applied to microwave systems and digital technologies.

  14. Real-Time Digital Image Exposure Status Detection and Circuit Implementation

    Directory of Open Access Journals (Sweden)

    Li Hongqin

    2015-05-01

    Full Text Available Auto exposure is an important part of digital image signal processing. We studied the detection of the exposure status in this paper, and fast and parallel detection method was presented. The method comprises the following steps: first obtaining the current image, counting the numbers of pixels in bright and dark regions of the image and obtaining these pixels brightness; then determining exposure parameters based on the proportions of the counted numbers of pixels in bright and dark regions with preset value respectively; if the actual proportion is lower than preset value, then continue to adjust exposure parameters until pixel brightness value reaches preset brightness threshold. Experiments show that the computational complexity and operation demand is low, which can quickly determine the exposure status of the image, improving the real-time capability in image exposure control. The proposed method will make the whole digital image signal processing system works smoothly and be reliable. The circuit implementation of this method is simple with high real-time controllability. This method has been applied for China patent successfully.

  15. Integrated digital printing of flexible circuits for wireless sensing (Conference Presentation)

    Science.gov (United States)

    Mei, Ping; Whiting, Gregory L.; Schwartz, David E.; Ng, Tse Nga; Krusor, Brent S.; Ready, Steve E.; Daniel, George; Veres, Janos; Street, Bob

    2016-09-01

    Wireless sensing has broad applications in a wide variety of fields such as infrastructure monitoring, chemistry, environmental engineering and cold supply chain management. Further development of sensing systems will focus on achieving light weight, flexibility, low power consumption and low cost. Fully printed electronics provide excellent flexibility and customizability, as well as the potential for low cost and large area applications, but lack solutions for high-density, high-performance circuitry. Conventional electronics mounted on flexible printed circuit boards provide high performance but are not digitally fabricated or readily customizable. Incorporation of small silicon dies or packaged chips into a printed platform enables high performance without compromising flexibility or cost. At PARC, we combine high functionality c-Si CMOS and digitally printed components and interconnects to create an integrated platform that can read and process multiple discrete sensors. Our approach facilitates customization to a wide variety of sensors and user interfaces suitable for a broad range of applications including remote monitoring of health, structures and environment. This talk will describe several examples of printed wireless sensing systems. The technologies required for these sensor systems are a mix of novel sensors, printing processes, conventional microchips, flexible substrates and energy harvesting power solutions.

  16. Nano-scale CMOS analog circuits models and CAD techniques for high-level design

    CERN Document Server

    Pandit, Soumya; Patra, Amit

    2014-01-01

    Reliability concerns and the limitations of process technology can sometimes restrict the innovation process involved in designing nano-scale analog circuits. The success of nano-scale analog circuit design requires repeat experimentation, correct analysis of the device physics, process technology, and adequate use of the knowledge database.Starting with the basics, Nano-Scale CMOS Analog Circuits: Models and CAD Techniques for High-Level Design introduces the essential fundamental concepts for designing analog circuits with optimal performances. This book explains the links between the physic

  17. Pre-Service Teachers Designing and Constructing "Good Digital Games"

    Science.gov (United States)

    Artym, Corbett; Carbonaro, Mike; Boechler, Patricia

    2016-01-01

    There is a growing interest in the application of digital games to enhance learning across many educational levels. This paper investigates pre-service teachers' ability to operationalize the learning principles that are considered part of a good digital game (Gee, 2007) by designing digital games in Scratch. Forty pre-service teachers, enrolled…

  18. Sketchtube; integrating digital media in the education of design skills

    NARCIS (Netherlands)

    Mulder-Nijkamp, Maaike; Eggink, Wouter

    2013-01-01

    In this paper we discuss the application of new opportunities and chances of digital learning in design education by means of the implementation of a digital sketching forum into a sketching course. The so called ‘blended learning’ method combines face to face education and a digital forum called Sk

  19. Digital libraries philosophies, technical design considerations, and example scenarios

    CERN Document Server

    Stern, David

    1999-01-01

    An unparalleled overview of current design considerations for your digital library! Digital Libraries: Philosophies, Technical Design Considerations, and Example Scenarios is a balanced overview of public services, collection development, administration, and systems support, for digital libraries, with advice on adopting the latest technologies that appear on the scene. As a professional in the library and information science field, you will benefit from this special issue that serves as an overview of selected directions, trends, possibilities, limitations, enhancements, design principals, an

  20. Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology

    OpenAIRE

    2011-01-01

    Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mi...

  1. Design of Digital Control System for Cement Raw Material Preparation

    Institute of Scientific and Technical Information of China (English)

    ZHOU Ying; LI Hongsheng

    2006-01-01

    This paper describes the design of cement raw material prepared digital control system by PROFIBUS. It uses the digital technology to implement the digital control system for raw material prepared of the cement factory. This system improves the communication between the industrial system and locale instrument devices. It applies digital communication to replace the 4-20 mA or 24VDC signal between locale lever device and controller.

  2. Reliable interface design for combining asynchronous and synchronous circuits

    Science.gov (United States)

    Josephson, Lueli; Brunvand, Erik L.; Gopalakrishan, Ganesh; Hurdle, John F.

    1993-01-01

    In order to successfully integrate asynchronous and synchronous designs, great care must be taken at the interface between the two types of systems. Synchronizing asynchronous inputs with a free running clock can cause well-known problems with metastability in the synchronization circuits. Stretchable clocks allow a clock cycle to expand dynamically in response to the metastability effects of sampling asynchronous inputs. We use an interface organization where the special circuitry for detecting metastability and for stretching the clock that is delivered to the synchronous part of the system is encapsulated in a Q-flop-based interface. This provides a very convenient method for interfacing mixed systems, as the interface and clock generation circuitry are isolated into one special module, and neither the asynchronous nor the synchronous system need be modified internally to accommodate the interface. This is especially important when standard synchronous components are used as there is no opportunity to modify these parts. We show that this interface module is suitable for most mixed design needs and conclude with an example.

  3. Lower Power Design for UHF RF CMOS Circuits Based on the Power Consumption Acuity

    Directory of Open Access Journals (Sweden)

    Niu Xiang-jie

    2014-01-01

    Full Text Available Excessive energy consumption of UHF tag is the bottleneck of energy saving in its wide range of applications. To address this issue, a lower power design for UHF RF CMOS circuits based on power consumption acuity is proposed in this paper. Through in-depth analysis of the static and dynamic power generation principle of UHF RF circuits in the work, the power consumption acuity can be calculated by using the correlation of circuit power and input vector. Subsequently, under the guide of this acuity, the UHF RF CMOS circuits with better energy saving can be designed. Furthermore, according to the performance indicators of EPC CIG2 UHF RFID in UHF identification, the corresponding circuit is designed and implemented. The test results show that the design of UHF RF circuit based on the acuity of power consumption can reduce 35%–40% power consumption.

  4. Design of a Low Power Combinational Circuit by using Adiabatic Logic

    Directory of Open Access Journals (Sweden)

    B.Jeevan Rao

    2014-04-01

    Full Text Available A novel low power and Positive Feedback Adiabatic Logic (PFAL combinational low power circuit is presented in this paper. The power consumption and general characteristics of the PFAL combinationallow power circuit arethen compared against two combinational low power circuit Efficient Charge Recovery Logic (ECRL, Conventional CMOS. The proposed PFAL combinational low power circuit design was proven to be superior to the other two designs in power dissipation and area. The combination of low power and low transistor count makes the new PFAL cell a viable option for low power design.

  5. State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 2: Hardware design verification

    Science.gov (United States)

    Carlan, A. J.; Breuer, M. A.

    1982-10-01

    The complexity of digital circuits requires that more emphasis be placed on design specifications and verification. Specification of design requirements currently advocated is done with formal hardware descriptive languages (HDLs) to describe hardware function. Industry's current use of HDLs is primarily for simulation. Verifying a design is a less mature discipline. Three approaches are considered: simulation, symbolic simulation amd formal proofs. While symbolic simulation shows promise, much research and development is required.

  6. CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) circuit design for nanosecond quantum-bit read-out.

    Energy Technology Data Exchange (ETDEWEB)

    Gurrieri, Thomas M.; Lilly, Michael Patrick; Carroll, Malcolm S.; Levy, James E.

    2008-08-01

    Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

  7. An Approach for Self-Timed Synchronous CMOS Circuit Design

    Science.gov (United States)

    Walker, Alvernon; Lala, Parag K.

    2001-01-01

    In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.

  8. Design of a multispectral digital colposcope

    Science.gov (United States)

    MacKinnon, N. B.; Cardeno, M.; Au, S.; MacAulay, C. E.; Pikkula, B. M.; Serachitopol, D.; Follen, M.; Park, S. Y.; Richards-Kortum, R.

    2007-02-01

    Measurement quality assurance plans for optical devices should be a mandatory part of grant funding submissions and should explicitly affect scoring during review. These should include calibration strategy, standards selection strategy, performance verification plan, performance validation plan and thorough preclinical performance validation. A multispectral digital colposcope (MDC) has been designed to collect image data from patients as part of an NIH sponsored clinical trial, based on a technology assessment model. Calibration strategy, standards selection and performance verification methods are presented that may be used as a template for smaller groups or more limited studies. With the MDC, red green and blue fluorescence images are captured under ultraviolet light excitation and red and green images are captured under blue light excitation. Red, green and blue reflectance images are captured under broadband white light illumination from a metal halide lamp in three modes - ordinary reflectance, and with polarized illumination in combination with parallel and cross-polarized filtered imaging. The highly automated system was designed to collect images of the cervix prior to and following the application of acetic acid. Three systems have been built and will be operated in clinics in Vancouver, Canada, Houston, Texas and other locations in the developed and developing world including Nigeria. The system is designed with a comprehensive set of calibration and performance verification standards, based on our experience with large scale multi-center spectroscopy clinical trials and measurements are made frequently prior to and following patient measurements. Automated performance verification procedures are being designed based on measurements made during pilot studies to facilitate larger clinical trials.

  9. Analysis and design of the system of a total digital Si-gyroscope

    Science.gov (United States)

    Huang, Fuxiang; Liang, Yin

    2017-03-01

    In order to get a thorough understanding of the total digital silicon micro-gyroscope, a novel system-level model with details of both the sense and circuit is presented in this paper. Unlike the traditional structures of the digital part of the digital gyroscope, a structure with programmable delay units (PDUs) instead of DPLLs gives a brief and robust character of the whole system. And the PDUs coordinating with the FIR filter could lead to a removal of the IF filters of the sigma-delta DAC for feedback, which saves a lot of consumption. Two MASH sigma-delta ADCs are designed to convert the output of the charge-voltage converters to digital signals, which also bring a better stability. The ADCs achieve an SNR of 102.5 dB with a 10 kHz bandwidth. The stabilization of the closed drive mode has also been analyzed including how the noise caused by the quantization of the digital circuit is affecting the stabilization of both the amplitude and frequency of the driving signals. In the end, a final result of simulation of the gyroscope shows the correctness and accuracy of the whole model of the gyroscope.

  10. Establishing a Seismometer at PARI and Designing a Switching Circuit Utilizing Fiber Communications

    Science.gov (United States)

    Ritchie, Justin

    2007-12-01

    At Pisgah Astronomical Research Institute (PARI) in Rosman, NC I spent ten weeks as the first NC Space Grant/Cline Astronomy Scholar developing multiple projects that helped to establish PARI as a resource for the scientific community. The first project that I worked on was establishing PARI's seismometer which serves as a resource for the region and utilizes sensitive equipment to measure 2.8 magnitude earthquakes occurring anywhere on earth. After basic seismometer operating principles were studied, multiple locations were surveyed to find an ideal location with little ambient noise and no disturbance from human or mechanical sources. Disturbances were generated at several locations identified as potential sites for the seismometer at 10, 20 and 30 feet by dropping a basketball and by driving a car around the location in an established pattern. Noise response was analyzed using the WinSDR software package which generates digital records of analog seismometer data and an ideal location was identified. The second project involved designing a circuit around the specific needs of the PARI optical telescope ridge. This ridge is susceptible to equipment that is damaged or improperly reset due to lightning. The circuit utilized the insulated properties of optical fiber to transmit a switching signal to the weather stations on the PARI optical ridge. This signal reset those stations that transmitted asynchronously after a lightning strike. Fiber optic transmitters were incorporated into the circuit along with TTL logic to provide a solid system that met the necessary specifications. After a rewarding an interesting summer I will follow up on my work next year for ten more weeks.

  11. Comparison of Heuristic Methods for the Design of Edge Disjoint Circuits

    NARCIS (Netherlands)

    Phillipson, F.

    2015-01-01

    In this paper heuristics are studied for the design of edge disjoint circuits. We formulate the Edge Disjoint Circuits Problem (EDCP) in the context of a telecommunication network design problem: the roll-out of Fibre to the Cabinet. This problem setting can be represented by a graph. A small subset

  12. Circuit Design to Stabilize the Reflectometer Local Oscillator Signals

    Energy Technology Data Exchange (ETDEWEB)

    Kung, C. C.; Kramer, G. J.; Johnson, E.; Solomon, W.; Nazikian, R.

    2005-10-04

    Reflectometry, which uses the microwave radar technique to probe the magnetically confined fusion plasmas, is a very powerful tool to observe the density fluctuations in the fusion plasmas. Typically, two or more microwave beams of different frequencies are used to study the plasma density fluctuations. The frequency separation between these two beams of the PPPL designed reflectometer system upgrade on the DIII-D tokamak can be varied over 18 GHz. Due to the performance of the associated electronics, the local oscillator (LO) power level at the LO port of the I/Q demodulator suffers more than 12 dB of power fluctuations when the frequency separation is varied. Thus, the I/Q demodulator performance is impaired. In order to correct this problem, a power leveling circuit is introduced in the PPPL upgrade. According to the test results, the LO power fluctuation was regulated to be within 1 dB for greater than 16 dB of input power variation over the full dynamic bandwidth of the receiver.

  13. Development of receiving-detecting circuit for digital radiographic systems with improved spatial resolution

    Science.gov (United States)

    Ryzhikov, Volodymir D.; Opolonin, Oleksandr D.; Galkin, Serhiy M.; Voronkin, Yevheniy F.; Lysetska, Olena K.; Kostyukevych, Serhiy A.

    2009-08-01

    Detection of X-ray radiation by digital radiographic systems (DRS) is realized using multi-element detector arrays of scintillator-photodiode (S-PD) type. Accounting for our experience in development of X-ray introscopy systems, possibilities can be found for improvement of DRS detection efficiency. Namely, a more efficient use of the dynamic range of the analog-to-digit converter by means of instrumental compensation of scatter of detector characteristics and smaller apertures of individual detection channels. However, smaller apertures lead to lower levels of useful signals, and a problem emerges of signal interference over neighboring channels, which is related to optical separation of the scintillation elements. Also, more compact arrangement of electronic components of preamplifiers is achieved. The latter problem is solved by using multi-channel (from 32 to 1024 channels) photoreceiving devices (PRD). PRD has a set of photosensitive elements formed on one crystal, as well as shift registers ensuring preliminary amplification of signals and series connection to one outlet. The work envisages creation of receiving-detecting circuit (RDC) with improved spatial resolution (ISR) with the aim of producing advanced DRS with improved characteristics: density resolution better than 0.9%, and detecting ability allowing detection of θ 0.5 mm steel wire behind 6 mm steel. The work will result in the development of RDC with ISR (800-200 microns). In combination with various ionizing radiation sources and scanning mechanisms this will allow creation of DRS for many tasks of non-destructive testing (NDT) and technical diagnostics (TD), in particular, for check-up of pipelines, objects of oil and gas industries, etc. This work was supported by the Ministry of Education and Science of Ukraine, the U.S. Civilian Research and Development Foundation (CRDF), and by the NATO Science for Peace and Security Program (Project SfP-982823).

  14. Design Principles of Next-Generation Digital Gaming for Education.

    Science.gov (United States)

    Squire, Kurt; Jenkins, Henry; Holland, Walter; Miller, Heather; O'Driscoll, Alice; Tan, Katie Philip; Todd, Katie.

    2003-01-01

    Discusses the rapid growth of digital games, describes research at MIT that is exploring the potential of digital games for supporting learning, and offers hypotheses about the design of next-generation educational video and computer games. Highlights include simulations and games; and design principles, including context and using information to…

  15. Development of analog-digital readout integrated circuits for infrared focal plane arrays

    Science.gov (United States)

    Dem'yanenko, M. A.; Kozlov, A. I.; Marchishin, I. V.; Ovsyuk, V. N.

    2016-11-01

    This paper describes the design of readout integrated circuits (ROICs) for hybrid infrared focal plane arrays (IR FPAs). This work contains the estimation of the noise equivalent temperature difference (NETD) of IR FPAs based on frame and row integration of pixel signals in the spectral ranges of 8 to 14 and 3 to 5 μm. This paper also describes the development of ROICs for IR FPAs created with the use of mercury—cadmium—telluride (MCT) photodiodes and quantum well infrared photodetectors (QWIPs). The designed ROICs ensure the use of matrix and linear photodetector chips, including those with increased dark currents, in order to produce IR FPAs with temperature resolution corresponding to the world level of array analogs.

  16. Algebraic circuits

    CERN Document Server

    Lloris Ruiz, Antonio; Parrilla Roure, Luis; García Ríos, Antonio

    2014-01-01

    This book presents a complete and accurate study of algebraic circuits, digital circuits whose performance can be associated with any algebraic structure. The authors distinguish between basic algebraic circuits, such as Linear Feedback Shift Registers (LFSRs) and cellular automata, and algebraic circuits, such as finite fields or Galois fields. The book includes a comprehensive review of representation systems, of arithmetic circuits implementing basic and more complex operations, and of the residue number systems (RNS). It presents a study of basic algebraic circuits such as LFSRs and cellular automata as well as a study of circuits related to Galois fields, including two real cryptographic applications of Galois fields.

  17. Hybrid CMOS/Nanodevice Integrated Circuits Design and Fabrication

    Science.gov (United States)

    2008-08-25

    This approach combines a semiconductor transistor system with a nanowire crossbar, with simple two-terminal nanodevices self-assembled at each...hybrid CMOS/nanodevice integrated circuits [10-12]. Such circuit combines a semiconductor transistors system with a nanowire crossbar, with simple two...both with and without embedded metallic clusters), self-assembled molecular monolayers, and thin chalcogenide and crystalline perovskite layers [20

  18. Printed, sub-3V digital circuits on plastic from aqueous carbon nanotube inks.

    Science.gov (United States)

    Ha, Mingjing; Xia, Yu; Green, Alexander A; Zhang, Wei; Renn, Mike J; Kim, Chris H; Hersam, Mark C; Frisbie, C Daniel

    2010-08-24

    Printing electronic components on plastic foils with functional liquid inks is an attractive approach for achieving flexible and low-cost circuitry for applications such as bendable displays and large-area sensors. The challenges for printed electronics, however, include characteristically slow switching frequencies and associated high supply voltages, which together impede widespread application. Combining printable high-capacitance dielectrics with printable high-mobility semiconductors could potentially solve these problems. Here we demonstrate fast, flexible digital circuits based on semiconducting carbon nanotube (CNT) networks and high-capacitance ion gel gate dielectrics, which were patterned by jet printing of liquid inks. Ion gel-gated CNT thin-film transistors (TFTs) with 50 microm channel lengths display ambipolar transport with electron and hole mobilities >20 cm(2)/V.s; these devices form the basis of printed inverters, NAND gates, and ring oscillators on both polyimide and SiO(2) substrates. Five-stage ring oscillators achieve frequencies >2 kHz at supply voltages of 2.5 V, corresponding to stage delay times of 50 micros. This performance represents a substantial improvement for printed circuitry fabricated from functional liquid inks.

  19. Novel Design of a Nano-metric Fast 4*4 Reversible unsigned Wallace Multiplier Circuit

    Directory of Open Access Journals (Sweden)

    Ehsan PourAliAkbar

    2015-12-01

    Full Text Available One of the most promising technologies in designing low-power circuits is reversible computing. It is used in nanotechnology, quantum computing, quantum dot cellular automata (QCA, DNA computing, optical computing and in CMOS low-power designs. Since reversible logic is subject to certain restrictions (e.g. fan-out and feedback are not allowed, traditional synthesis methods are not applicable and specific methods have been developed. In this paper, we offer a Wallace 4*4 reversible multiplier circuits which have faster speed and lower complexity in comparison with the other multiplier circuits. This circuit performs better, regarding to the number of gates, garbage outputs and constant inputs work better than the same circuits. In this paper, Peres gate is used as HA and HNG gate is used as FA. We offer the best method to multiply two 4 bit numbers. These Nano-metric circuits can be used in very complex systems.

  20. FinFET Based Tunable Analog Circuit: Design and Analysis at 45 nm Technology

    Directory of Open Access Journals (Sweden)

    Ravindra Singh Kushwah

    2013-01-01

    Full Text Available We included a designing of low power tunable analog circuits built using independently driven FinFETs devices, where the controlling of the back gate provide the output on the front gate. We show that this could be an effective solution to conveniently tune the output of bulk CMOS analog circuits particularly for Schmitt trigger and operational transconductance amplifier circuits. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both are independently controlled. FinFET device has a higher controllability, resulting relatively high Ion/Ioff ratio. In this paper, we proposed a tunable analog circuit such as CMOS amplifier circuit, Schmitt trigger circuit, and operational transconductance amplifier circuit, these circuit blocks are necessary for low noise high performance ICs for analog applications. Gain, phase, group delay, and output response of analog tunable circuits have been discussed in this paper. The proposed FinFET based analog tunable circuits have been designed using Cadence Virtuoso tool at 45 nm.

  1. Patient engagement and the design of digital health

    Science.gov (United States)

    Birnbaum, Faith; Lewis, Dana M.; Rosen, Rochelle; Ranney, Megan L.

    2015-01-01

    Digital health is an area of growing interest for physicians, patients, and technology companies alike. It promises the ability to engage patients in their care, before, during, and after an emergency department visit. Current efforts to create, study, and disseminate digital health have been limited by lack of user engagement. In this commentary, we outline the imperative for engaging end-users in each phase of digital health design, as well as a few techniques to facilitate better digital health design and implementation. PMID:25997375

  2. Innovative Principle and Method for Digital Jacquard Fabric Designing

    Institute of Scientific and Technical Information of China (English)

    ZHOU Jiu; NG Fran-kie; SZETO Y C; HUI C L

    2007-01-01

    Digital jacquard fabric has its design concept and method directly borrowed from computer images and color modes, which enabled creation of jacquard fabric design that is far beyond what freehand patterns can express. In this paper, the principles of digital jacquard fabric design were classified into two parts: colorless mode and colorful mode, and an innovative layered combination design method has been suggested contenting with this new design concept, by which digital jacquard fabric can be designed from colorless single-layer structure to colorful compound structure. As a result, designed colorless and colorful jacquard fabrics are capable of expressing picturesque and photo-realistic effects with a mega level color number on face of fabric. It is envisaged that the results of the study are of tremendous benefit to the creation of new jacquard fabric ith an inimitable digital effect and this creation pose no problem in mass production.

  3. Design and performance of a multi-channel, multi-sampling, PSD-enabling integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Engel, G.L., E-mail: gengel@siue.ed [Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Southern Illinois University Edwardsville, Engineering Building, Room 3043 Edwardsville, IL 62026 1081 (United States); Hall, M.J.; Proctor, J.M. [Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Southern Illinois University Edwardsville, Engineering Building, Room 3043 Edwardsville, IL 62026 1081 (United States); Elson, J.M.; Sobotka, L.G.; Shane, R.; Charity, R.J. [Departments of Chemistry and Physics, Washington University, Saint Louis, MO 63130 (United States)

    2009-12-21

    This paper presents the design and test results of an eight-channel prototype integrated circuit chip intended to greatly simplify the pulse-processing electronics needed for large arrays of scintillation detectors. Because the chip design employs (user-controlled) multi-region charge integration, particle identification is incorporated into the basic design. Each channel on the chip also contains a time-to-voltage converter which provides relative time information. The pulse-height integrals and the relative time are all stored on capacitors and are either reset, after a user controlled time, or sequentially read out if acquisition of the event is desired. Each of the three pulse-height sub-channels consists of a gated integrator with eight programmable charging rates and an externally programmable gate generator that defines the start (with four time ranges) and width (with four time ranges) of the gate relative to an external discriminator signal. The chip supports three triggering modes, two time ranges, two power modes, and produces four sparsified analog pulse trains (three for the integrators and another for the time) with synchronized addresses for off-chip digitization with a pipelined ADC. The eight-channel prototype chip occupies an area of 2.8 mmx5.7 mm, dissipates 60 mW (low-power mode), and was fabricated in the AMI 0.5-mum process (C5N).

  4. Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits.

    Science.gov (United States)

    Guo, Xinjie; Merrikh-Bayat, Farnood; Gao, Ligang; Hoskins, Brian D; Alibart, Fabien; Linares-Barranco, Bernabe; Theogarajan, Luke; Teuscher, Christof; Strukov, Dmitri B

    2015-01-01

    The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC) with up to 8 bits of precision. Major shortcomings affecting the ADC's precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2- x /Pt memristors and CMOS integrated circuit components.

  5. Development of an optical parallel logic device and a half-adder circuit for digital optical processing

    Science.gov (United States)

    Athale, R. A.; Lee, S. H.

    1978-01-01

    The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

  6. Development of an optical parallel logic device and a half-adder circuit for digital optical processing

    Science.gov (United States)

    Athale, R. A.; Lee, S. H.

    1978-01-01

    The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

  7. A digital filter optimization method for low power digital wireless communication system

    OpenAIRE

    Tarumi, Kousuke; Tsujimoto, Taizo; Yasuura, Hiroto

    2003-01-01

    In this paper, we introduce a design method for a low power digital baseband processing circuit. In particular, we focus on a digital FIR(Finite Impulse Response) filter that is a part of the digital baseband processing. Because the digital filter contains large power consuming components, such as adders and multipliers. We propose a design method to reduce power consumption of the digital FIR filter circuit by optimizing bitwidth of inputs of the mutipliers and the adders. We found that the ...

  8. Implementation of integrated circuit and design of SAR ADC for fully implantable hearing aids.

    Science.gov (United States)

    Kim, Jong Hoon; Lee, Jyung Hyun; Cho, Jin-Ho

    2017-07-20

    The hearing impaired population has been increasing; many people suffer from hearing problems. To deal with this difficulty, various types of hearing aids are being rapidly developed. In particular, fully implantable hearing aids are being actively studied to improve the performance of existing hearing aids and to reduce the stigma of hearing loss patients. It has to be of small size and low-power consumption for easy implantation and long-term use. The objective of the study was to implement a small size and low-power consumption successive approximation register analog-to-digital converter (SAR ADC) for fully implantable hearing aids. The ADC was selected as the SAR ADC because its analog circuit components are less required by the feedback circuit of the SAR ADC than the sigma-delta ADC which is conventionally used in hearing aids, and it has advantages in the area and power consumption. So, the circuit of SAR ADC is designed considering the speech region of humans because the objective is to deliver the speech signals of humans to hearing loss patients. If the switch of sample and hold works in the on/off positions, the charge injection and clock feedthrough are produced by a parasitic capacitor. These problems affect the linearity of the hold voltage, and as a result, an error of the bit conversion is generated. In order to solve the problem, a CMOS switch that consists of NMOS and PMOS was used, and it reduces the charge injection because the charge carriers in the NMOS and PMOS have inversed polarity. So, 16 bit conversion is performed before the occurrence of the Least Significant Bit (LSB) error. In order to minimize the offset voltage and power consumption of the designed comparator, we designed a preamplifier with current mirror. Therefore, the power consumption was reduced by the power control switch used in the comparator. The layout of the designed SAR ADC was performed by Virtuoso Layout Editor (Cadence, USA). In the layout result, the size of the

  9. Intervention on digital printers: a graphic design method

    OpenAIRE

    Türkmen, Doruk; Turkmen, Doruk

    2014-01-01

    Print culture has become a mere representation of computer data. With practical solutions digital printing has brought, appreciation of printed matter and visual aesthetics lost their emphasis. While those practical solutions are useful, a lot of opportunities the digital printing could have offered were being missed out. This distant relationship between printed material and graphic design will be investigated in this thesis. In this experiment, opportunities that digital printing offers wil...

  10. Intervention on digital printers: a graphic design method

    OpenAIRE

    Türkmen, Doruk; Turkmen, Doruk

    2014-01-01

    Print culture has become a mere representation of computer data. With practical solutions digital printing has brought, appreciation of printed matter and visual aesthetics lost their emphasis. While those practical solutions are useful, a lot of opportunities the digital printing could have offered were being missed out. This distant relationship between printed material and graphic design will be investigated in this thesis. In this experiment, opportunities that digital printing offers wil...

  11. Designable DNA-binding domains enable construction of logic circuits in mammalian cells.

    Science.gov (United States)

    Gaber, Rok; Lebar, Tina; Majerle, Andreja; Šter, Branko; Dobnikar, Andrej; Benčina, Mojca; Jerala, Roman

    2014-03-01

    Electronic computer circuits consisting of a large number of connected logic gates of the same type, such as NOR, can be easily fabricated and can implement any logic function. In contrast, designed genetic circuits must employ orthogonal information mediators owing to free diffusion within the cell. Combinatorial diversity and orthogonality can be provided by designable DNA- binding domains. Here, we employed the transcription activator-like repressors to optimize the construction of orthogonal functionally complete NOR gates to construct logic circuits. We used transient transfection to implement all 16 two-input logic functions from combinations of the same type of NOR gates within mammalian cells. Additionally, we present a genetic logic circuit where one input is used to select between an AND and OR function to process the data input using the same circuit. This demonstrates the potential of designable modular transcription factors for the construction of complex biological information-processing devices.

  12. Research study on IPS digital controller design

    Science.gov (United States)

    Kuo, B. C.; Folkerts, C.

    1976-01-01

    The performance is investigated of the simplified continuous-data model of the Instrument Pointing System (IPS). Although the ultimate objective is to study the digital model of the system, knowledge on the performance of the continuous-data model is important in the sense that the characteristics of the digital system should approach those of the continuous-data system as the sampling period approaches zero.

  13. Designing a simple dynamic Digital Signage Network

    OpenAIRE

    Hagen, Andreas Ødegård

    2006-01-01

    Digital Signage Networks (DSN) is a continious emerging digital advertisment medium. Display devices, typically large format plasma or LCD screens, are used to provide rich multimedia advertisments in shops, buses, at airports and other public premises. Such networks have turned out to gain significant cost-effective advantages over traditional printed signage by eliminating the need for manual distribution. Animated graphics, audio and video effects makes a DSN highly suitable to attract the...

  14. Design of ispPAC-based Humidity Sensor Signal Processing Circuits

    Institute of Scientific and Technical Information of China (English)

    Duren Liu; Jin Liu; Zhichun Ren

    2006-01-01

    The widely used sensitive etements of humidity sensors can be divided into 3 types, i.e., resistor, capacitor, and electrolyte. Humidity sensors consisting of these sensitive elements have corresponding signal processing circuit unique to each type of sensitive elements. This paper presents an ispPAC (in-system programmable Programmable Analog Circuit)-based humidity sensor signal processing circuit designed with software method and implemented with in-system programmable simulators. Practical operation shows that humidity sensor signal processing circuits of this kind, exhibit stable and reliable performance.

  15. Designing digital health information in a health literacy context

    NARCIS (Netherlands)

    Meppelink, C.S.

    2016-01-01

    Digital health information is widely available, but not everyone fully benefits due to limited health literacy. Until now, little was known about how health literacy influences information processing and how design features of digital health information can be used to create optimal health messages

  16. Designing digital health information in a health literacy context

    NARCIS (Netherlands)

    Meppelink, C.S.

    2016-01-01

    Digital health information is widely available, but not everyone fully benefits due to limited health literacy. Until now, little was known about how health literacy influences information processing and how design features of digital health information can be used to create optimal health messages

  17. Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications

    Science.gov (United States)

    Zhuge, Jing; Verhulst, Anne S.; Vandenberghe, William G.; Dehaene, Wim; Huang, Ru; Wang, Yangyuan; Groeseneken, Guido

    2011-08-01

    This paper investigates the potential of tunnel field-effect transistors (TFETs), with emphasis on short-gate TFETs, by simulation for low-power digital applications having a supply voltage lower than 0.5 V. A transient study shows that the tunneling current has a negligible contribution in charging and discharging the gate capacitance of TFETs. In spite of a higher resistance region in the short-gate TFET, the gate (dis)charging speed still meets low-voltage application requirements. A circuit analysis is performed on short-gate TFETs with different materials, such as Si, Ge and heterostructures in terms of voltage overshoot, delay, static power, energy consumption and energy delay product (EDP). These results are compared to MOSFET and full-gate TFET performance. It is concluded that short-gate heterostructure TFETs (Ge-source for nTFET, In0.6Ga0.4As-source for pTFET) are promising candidates to extend the supply voltage to lower than 0.5 V because they combine the advantage of a low Miller capacitance, due to the short-gate structures, and strong drive current in TFETs, due to the narrow bandgap material in the source. At a supply voltage of 0.4 V and for an EOT and channel length of 0.6 nm and 40 nm, respectively, a three-stage inverter chain based on short-gate heterostructure TFETs saves 40% energy consumption per cycle at the same delay and shows 60%-75% improvement of EDP at the same static power, compared to its full-gate counterpart. When compared to the MOSFET, better EDP can be achieved in the heterostructure TFET especially at low static power consumption.

  18. Efficient modeling of interconnects and capacitive discontinuities in high-speed digital circuits. Thesis

    Science.gov (United States)

    Oh, K. S.; Schutt-Aine, J.

    1995-01-01

    Modeling of interconnects and associated discontinuities with the recent advances high-speed digital circuits has gained a considerable interest over the last decade although the theoretical bases for analyzing these structures were well-established as early as the 1960s. Ongoing research at the present time is focused on devising methods which can be applied to more general geometries than the ones considered in earlier days and, at the same time, improving the computational efficiency and accuracy of these methods. In this thesis, numerically efficient methods to compute the transmission line parameters of a multiconductor system and the equivalent capacitances of various strip discontinuities are presented based on the quasi-static approximation. The presented techniques are applicable to conductors embedded in an arbitrary number of dielectric layers with two possible locations of ground planes at the top and bottom of the dielectric layers. The cross-sections of conductors can be arbitrary as long as they can be described with polygons. An integral equation approach in conjunction with the collocation method is used in the presented methods. A closed-form Green's function is derived based on weighted real images thus avoiding nested infinite summations in the exact Green's function; therefore, this closed-form Green's function is numerically more efficient than the exact Green's function. All elements associated with the moment matrix are computed using the closed-form formulas. Various numerical examples are considered to verify the presented methods, and a comparison of the computed results with other published results showed good agreement.

  19. 组合逻辑电路设计在EDA技术中的应用%Application of Combinational Logic Circuit Design in the EDA Technologies

    Institute of Scientific and Technical Information of China (English)

    杨旭; 杨云; 佟妍

    2012-01-01

    Multisim9 software is specially designed for electronic circuit simulation and design of EDA software. This will design a lifting of the voting circuit circuit examples of application to EDA. the oretical teaching and EDA technologies combined.for learning theoretical knowledge of digital electronic technology to expand the space.%Multisim9软件是专门用于电子电路仿真与设计的EDA软件,本文将设计一个举重裁判表决电路的组合电路实例应用到EDA中,将理论教学与EDA技术的结合在一起,为学习教字电子技术的理论知识拓展了空间.

  20. 75 FR 80853 - Designing a Digital Future: Federally Funded Research and Development in Networking and...

    Science.gov (United States)

    2010-12-23

    ... Designing a Digital Future: Federally Funded Research and Development in Networking and Information... ``Designing a Digital Future: Federally Funded Research and Development in Networking and Information... report entitled ``Designing a Digital Future: Federally Funded Research and Development in Networking and...

  1. 从表决器设计看组合逻辑电路设计方法%Design Method of Combinational Logic Circuit from the View of the Voting Machine Design

    Institute of Scientific and Technical Information of China (English)

    马惠兰

    2016-01-01

    The combinational logic circuits is very important part of the digital circuit,design method for the master degree directly related to digital system design capacity.In this paper,by three experiments, use different method to design the four variables majority voter,and verify its logic function,further of combinational logic circuit design methods are analyzed and summarized, showing the flexibility of digital circuit design,exercise the students' practical ability.%组合逻辑电路是数字电路很重要的组成部分,其设计方法的掌握程度直接关系到数字系统的设计能力。本文通过三个实验,采用不同的方法设计了四变量多数表决器,并验证了其逻辑功能,进一步对组合逻辑电路的设计方法进行了分析总结,表现了数字电路设计的灵活性,锻炼了学生的动手能力。

  2. Design of a novel digital phantom for EIT system calibration.

    Science.gov (United States)

    Li, Nan; Wang, Wei; Xu, Hui

    2011-01-01

    This paper presented the design method of a novel digital phantom for electrical impedance tomography system calibration. By current sensing, voltage generating circuitry and digital processing algorithms implemented in FPGA, the digital phantom can simulate different impedances of tissues. The hardware of the digital phantom mainly consists of current sensing section, voltage generating section, electrodes switching section and a FPGA. Concerning software, the CORDIC algorithm is implemented in the FPGA to realize direct digital synthesis (DDS) technique and related algorithms. Simulation results show that the suggested system exhibits sufficient accuracy in the frequency range 10 Hz to 2 MHz. With the advantages offered by digital techniques, our approach has the potential of speed, accuracy and flexibility of the EIT system calibration process.

  3. The Signal Detection and Control Circuit Design for Confocal Auto-Focus System

    Directory of Open Access Journals (Sweden)

    Yin Liu

    2016-01-01

    Full Text Available Based on the demands of Confocal Auto-Focus system, the implementation method of signal measurement circuit and control circuit is given. Using the high performance instrumental amplifier AD620BN, low noise precision FET Op amplifier AD795JRZ and ultralow offset voltage Op amplifier OP07EP, a signal measurement circuit used to converse the two differential light intensity signal to electric signal is designed. And a control circuit which takes MCU MSP430F149 as core processes the former signal and generate a control signal driving the platform for auto-focusing. The experimental results proved the feasibility and correctness of circuits. And the system meets the design requirement.

  4. Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

    Science.gov (United States)

    Yu, Lili; El-Damak, Dina; Radhakrishna, Ujwal; Ling, Xi; Zubair, Ahmad; Lin, Yuxuan; Zhang, Yuhao; Chuang, Meng-Hsi; Lee, Yi-Hsien; Antoniadis, Dimitri; Kong, Jing; Chandrakasan, Anantha; Palacios, Tomas

    2016-10-12

    Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

  5. Behavioral study and design of a digital interpolator filter for wireless reconfigurable transmitters

    Science.gov (United States)

    Ferragina, V.; Frassone, A.; Ghittori, N.; Malcovati, P.; Vigna, A.

    2005-06-01

    The behavioral analysis and the design in a 0.13 μm CMOS technology of a digital interpolator filter for wireless applications are presented. The proposed block is designed to be embedded in the baseband part of a reconfigurable transmitter (WLAN 802.11a, UMTS) to operate as a sampling frequency boost between the digital signal processor (DSP) and the digital-to-analog converter (DAC). In recent trends the DAC of such transmitters usually operates at high conversion frequencies (to allow a relaxed implementation of the following analog reconstruction filter), while the DSP output flows at low frequencies (typically Nyquist rate). Thus a block able to increase the digital data rate, like the one proposed, is needed before the DAC. For example, in the WLAN case, an interpolation factor of 4 has been used, allowing the digital data frequency to raise from 20 MHz to 80 MHz. Using a time-domain model of the TX chain, a behavioral analysis has been performed to determine the impact of the filter performance on the quality of the signal at the antenna. This study has led to the evaluation of the z-domain filter transfer function, together with the specifications concerning a finite precision implementation. A VHDL description has allowed an automatic synthesis of the circuit in a 0.13 μm CMOS technology (with a supply voltage of 1.2 V). Post-synthesis simulations have confirmed the effectiveness of the proposed study.

  6. A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

    Science.gov (United States)

    Moradi, Behzad; Mirzaei, Abdolreza

    2016-11-01

    A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer's knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.

  7. Operational amplifier speed and accuracy improvement analog circuit design with structural methodology

    CERN Document Server

    Ivanov, Vadim V

    2004-01-01

    Operational Amplifier Speed and Accuracy Improvement proposes a new methodology for the design of analog integrated circuits. The usefulness of this methodology is demonstrated through the design of an operational amplifier. This methodology consists of the following iterative steps: description of the circuit functionality at a high level of abstraction using signal flow graphs; equivalent transformations and modifications of the graph to the form where all important parameters are controlled by dedicated feedback loops; and implementation of the structure using a library of elementary cells. Operational Amplifier Speed and Accuracy Improvement shows how to choose structures and design circuits which improve an operational amplifier's important parameters such as speed to power ratio, open loop gain, common-mode voltage rejection ratio, and power supply rejection ratio. The same approach is used to design clamps and limiting circuits which improve the performance of the amplifier outside of its linear operat...

  8. Design of a High Performance Green-Mode PWM Controller IC with Smart Sensing Protection Circuits

    National Research Council Canada - National Science Library

    Shen-Li Chen; Shih-Hua Hsu

    2014-01-01

      A design of high performance green-mode pulse-width-modulation (PWM) controller IC with smart sensing protection circuits for the application of lithium-ion battery charger is investigated in this article...

  9. DESIGN OF MTCMOS LOGIC CIRCUITS FOR LOW POWER APPLICATIONS

    Directory of Open Access Journals (Sweden)

    V.LeelaRani

    2014-07-01

    Full Text Available Technology scaling leads to sub threshold leakages in deep sub micron regime. There is a need for effective leakage reduction techniques to minimize MOS leakage currents. Reduced leakage currents extend the life of all battery operated devices like cell phones, Laptops etc. This paper presents multi threshold CMOS circuit level technique to minimize leakages. MTCMOS technique is an effective solution for high-speed low-power applications. The proposed technique has been implemented in cadence virtuoso tool using standard cells of 90nm CMOS technology. For performance evaluation a full adder and 4x4 multipliers are considered as test circuits and applied with MTCMOS technique. Simulation results proved that MTCMOS technique is best in minimizing power compared with the conventional and dual threshold voltage techniques and can be used for low power applications.

  10. A circuit design for multi-inputs stateful OR gate

    Science.gov (United States)

    Chen, Qiao; Wang, Xiaoping; Wan, Haibo; Yang, Ran; Zheng, Jian

    2016-09-01

    The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.

  11. Design of an Inter-plane Circuit for Clocked PLAs

    Directory of Open Access Journals (Sweden)

    Chua-Chin Wang

    2002-01-01

    Full Text Available Since the Programmable Logic Arrays (PLAs can implement almost any Boolean function, they have become popular devices in realization of both combinational and sequential circuits. We present a power-saving fast half swing CMOS circuit implementation for NOR–NOR PLA implementation. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced. Detailed simulation results reveal appropriate L/W guidelines. The analysis of effects of the 1/2 VDD on power and speed is also provided in this work.

  12. Derandomizing Quantum Circuits with Measurement-Based Unitary Designs

    Science.gov (United States)

    Turner, Peter S.; Markham, Damian

    2016-05-01

    Entangled multipartite states are resources for universal quantum computation, but they can also give rise to ensembles of unitary transformations, a topic usually studied in the context of random quantum circuits. Using several graph state techniques, we show that these resources can "derandomize" circuit results by sampling the same kinds of ensembles quantum mechanically, analogously to a quantum random number generator. Furthermore, we find simple examples that give rise to new ensembles whose statistical moments exactly match those of the uniformly random distribution over all unitaries up to order t , while foregoing adaptive feedforward entirely. Such ensembles—known as t designs—often cannot be distinguished from the "truly" random ensemble, and so they find use in many applications that require this implied notion of pseudorandomness.

  13. Semantics for Digital Engineering Archives Supporting Engineering Design Education

    OpenAIRE

    Regli, William C.; Drexel University; Kopena, Joseph B.; Drexel University; Grauer, Michael; Drexel University; Simpson, Timothy W.; Penn State University; Stone, Robert B.; Oregon State University; Lewis, Kemper; University at Buffalo - SUNY; Bohm, Matt R.; Oregon State University; Wilkie, David; Drexel University; Piecyk, Martin; Drexel University; Osecki, Jordan; Drexel University

    2010-01-01

    This article introduces the challenge of digital preservation in the area of engineering design and manufacturing and presents a methodology to apply knowledge representation and semantic techniques to develop Digital Engineering Archives. This work is part of an ongoing, multiuniversity, effort to create cyber infrastructure-based engineering repositories for undergraduates (CIBER-U) to support engineering design education. The technical approach is to use knowledge representation techniques...

  14. Foundations of Digital Methods : Query Design

    NARCIS (Netherlands)

    Rogers, R.; Schäfer, M.T.; van Es, K.

    2017-01-01

    Broadly speaking digital methods may be considered the deployment of online tools and data for the purposes of social and medium research. More speci cally, they derive from online methods, or methods of the medium, which are reimagined and repurposed for research. The methods to be repurposed are

  15. Designing Digital Game-Based Learning Environments

    Science.gov (United States)

    An, Yun-Jo; Bonk, Curtis J.

    2009-01-01

    With the emergence of the Web 2.0 and other technologies for learning, there are a variety of special places that did not exist previously in which to pursue learning. Not just a few dozen more but millions more. Many of these are not the physical learning spaces one might envision but entirely virtual or digital ones. As an example, the area of…

  16. Analytical Study on Thermal and Mechanical Design of Printed Circuit Heat Exchanger

    Energy Technology Data Exchange (ETDEWEB)

    Yoon, Su-Jong [Idaho National Lab. (INL), Idaho Falls, ID (United States); Sabharwall, Piyush [Idaho National Lab. (INL), Idaho Falls, ID (United States); Kim, Eung-Soo [Idaho National Lab. (INL), Idaho Falls, ID (United States)

    2013-09-01

    The analytical methodologies for the thermal design, mechanical design and cost estimation of printed circuit heat exchanger are presented in this study. In this study, three flow arrangements of parallel flow, countercurrent flow and crossflow are taken into account. For each flow arrangement, the analytical solution of temperature profile of heat exchanger is introduced. The size and cost of printed circuit heat exchangers for advanced small modular reactors, which employ various coolants such as sodium, molten salts, helium, and water, are also presented.

  17. Noise in Large-Signal, Time-Varying RF CMOS Circuits: Theory & Design

    OpenAIRE

    Murphy, David Patrick

    2012-01-01

    RF CMOS design is now a mature field and CMOS radio transceivers have become standard in most consumer wireless devices. Like any wireless RF design, at the heart of the endeavor is the requirement to frequency translate signals between baseband and RF with minimal introduction of noise and distortion. This translation is generally accomplished using time-varying, strongly nonlinear circuits, whose operation and noise performance cannot be understood using standard LTI circuit analysis techni...

  18. Design and Fabrication of a Monolithic Optoelectronic Integrated Circuit Chip Based on CMOS Compatible Technology

    Institute of Scientific and Technical Information of China (English)

    GUO Wei-Feng; ZHAO Yong; WANG Wan-Jun; SHAO Hai-Feng; YANG Jian-Yi; JIANG Xiao-Qing

    2012-01-01

    A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology.The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function.Test results show that the extinction ratio of the MZM is close to 20dB and the small-signal gain of the CMOS driving circuit is about 26.9dB.A 50m V 10 MHz sine wave signal is amplified by the driving circuit,and then drives the MZM successfully.%A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology. The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function. Test results show that the extinction ratio of the MZM is close to 20 dB and the small-signal gain of the CMOS driving circuit is about 26.9dB. A 50mV 10MHz sine wave signal is amplified by the driving circuit, and then drives the MZM successfully.

  19. Alternative Design Concepts for Multi-Circuit HTS Link Systems

    CERN Document Server

    Ballarino, A

    2011-01-01

    Superconducting cables for power transmission usually contain two conductors for DC application, or three conductors for AC, with high voltage insulation. In contrast, for some applications related to accelerators it is convenient to transfer high currents via superconducting links feeding a number of circuits at relatively low voltage, of the order of a kilovolt, over distances of up to a few hundred meters. For power transmission applications based on cooling via sub-cooled liquid nitrogen, suitable HTS conductors are only available in the form of tape, and a multi-layer variant can be envisaged for the multi-circuit links. However, where cooling to temperatures of the order of 20 K is feasible, MgB2 conductor, available in the form of both tape and wire, can also be envisaged and in the latter case used to assemble round cables. There are, therefore, two distinct topologies - based on the use of wires or tapes - that can be envisaged for use in applications to multi-circuit link systems. In this paper the ...

  20. External cavity based single mode Fabry-Pérot laser diode and its application towards all-optical digital circuits

    Science.gov (United States)

    Nakarmi, Bikash; Zhang, Xuping; Won, Yong Hyub

    2012-11-01

    We have proposed a novel approach of realizing all-optical logic gates and combinational circuit using external cavity based single mode Fabry-Pérot laser diodes (SMFP-LDs). Different techniques and critical parameters for injection locking the any one of the modes of SMFP-LDs are discussed. Taking consideration of wavelength detuning and input injected power, we have proposed and demonstrated multi-input injection locking, supporting beam injection locking with the conventional injection locking which are used for demonstrating different logic gates (NAND, AND, XNOR, XOR, NOT, NOR) and digital circuits (Half adder and Comparator). Since we have used SMFP-LDs, there is no requirement of additional probe beam and associated components as required by other optical technologies making the realization simple in configuration, cost effective and power efficient. Clear output waveforms, eye diagrams, risingfalling times and BER are presented to verify the proposed method. All-optical logic units and digital circuit are demonstrated at the data rate of 10 Gbps with the waveform of NRZ signal waveform and measured eye diagram and BER of the PRBS of 231-1 signal. The maximum power penalty among all demonstrated units is below 1.4 dB at the BER of 10-9.

  1. CIRCUS--A digital computer program for transient analysis of electronic circuits

    Science.gov (United States)

    Moore, W. T.; Steinbert, L. L.

    1968-01-01

    Computer program simulates the time domain response of an electronic circuit to an arbitrary forcing function. CIRCUS uses a charge-control parameter model to represent each semiconductor device. Given the primary photocurrent, the transient behavior of a circuit in a radiation environment is determined.

  2. Digital sonar design in underwater acoustics principles and applications

    CERN Document Server

    Li, Qihu

    2012-01-01

    "Digital Sonar Design in Underwater Acoustics Principles and Applications" provides comprehensive and up-to-date coverage of research on sonar design, including the basic theory and techniques of digital signal processing, basic concept of information theory, ocean acoustics, underwater acoustic signal propagation theory, and underwater signal processing theory. This book discusses the general design procedure and approaches to implementation, the design method, system simulation theory and techniques, sonar tests in the laboratory, lake and sea, and practical validation criteria and methods for digital sonar design. It is intended for researchers in the fields of underwater signal processing and sonar design, and also for navy officers and ocean explorers. Qihu Li is a professor at the Institute of Acoustics, Chinese Academy of Sciences, and an academician of the Chinese Academy of Sciences.

  3. On the Integration of Digital Design and Analysis Tools

    DEFF Research Database (Denmark)

    Klitgaard, Jens; Kirkegaard, Poul Henning

    The aim of this research is to look into integrated digital design and analysis tools in order to find out if it is suited for use by architects and designers or only by specialists and technicians - and if not, then to look at what can be done to make them more available to architects...... and designers....

  4. Relaxation Based Electrical Simulation for VLSI Circuits

    Directory of Open Access Journals (Sweden)

    S. Rajkumar

    2012-06-01

    Full Text Available Electrical circuit simulation was one of the first CAD tools developed for IC design. The conventional circuit simulators like SPICE and ASTAP were designed initially for the cost effective analysis of circuits containing a few hundred transistors or less. A number of approaches have been used to improve the performances of congenital circuit simulators for the analysis of large circuits. Thereafter relaxation methods was proposed to provide more accurate waveforms than standard circuit simulators with up to two orders of magnitude speed improvement for large circuits. In this paper we have tried to highlights recently used waveform and point relaxation techniques for simulation of VLSI circuits. We also propose a simple parallelization technique and experimentally demonstrate that we can solve digital circuits with tens of million transistors in a few hours.

  5. Verilog Based Design and Simulation of MAC and PHY Layers for Zigbee Digital Transmitter

    Directory of Open Access Journals (Sweden)

    Pasala Raja Prakasha Rao

    2014-12-01

    Full Text Available The past several years have witnessed a rapid development in the wireless network area. So far wireless networking has been focused on high-speed and long range applications. Zigbee technology was developed for a Wireless Personal Area Networks (WPAN, aimed at control and military applications with low data rate and low power consumption. Zigbee is a standard defines the set of communication protocols for low-data-rate short-range wireless networking. Zigbee-based wireless devices operate in 868 MHz, 915 MHz, and 2.4 GHz frequency bands. The maximum data rate is 250K bits per second. Zigbee is mainly for battery-powered applications where low data rate, low cost, and long battery life are main requirements. This paper explores Verilog design for various blocks in Zigbee Transmitter architecture for an acknowledgement frame. The word digital has made a dramatic impact on our society. Developments of digital solutions have been possible due to good digital system design and modeling techniques. Further developments have been made and introduced VLSI in order to reduce size of the architecture, to improve speed of operation, improvements in predictability of the circuit behavior. Digital Zigbee Transmitter comprises of Cyclic Redundancy Check, Bit-to-Symbol block, Symbol-to-chip block, Modulator and Pulse shaping block. The work here is to show how we can design Zigbee transmitter with its specifications by using Verilog with less number of slices and Look up tables (LUTs.

  6. Total Dose Effects on Single Event Transients in Digital CMOS and Linear Bipolar Circuits

    Science.gov (United States)

    Buchner, S.; McMorrow, D.; Sibley, M.; Eaton, P.; Mavis, D.; Dusseau, L.; Roche, N. J-H.; Bernard, M.

    2009-01-01

    This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.

  7. A study of relaxation techniques for the transient analysis of digital circuits

    Science.gov (United States)

    Chia, W. K.

    1985-06-01

    In the VLSI microelectronics era, the cost of the immense CPU time and memory storage for a standard circuit simulator has become prohibitive. In order to achieve dramatic improvement in the performance of the circuit simulator, there are two principal points of departure from the standard simulation approach, namely, tearing decomposition and relaxation decomposition. This research is to study the numerical convergence and stability properties of several of the relaxation algorithms that have been proposed for the simulation of VLSI circuits. The time-point Gauss-Seidel method with prediction, the exploitation of latency and event scheduling algorithms are implemented into a general purpose circuit simulator SLATE-R (a Simulator with Latency and Tearing--Relaxed version). The performance of the SLATE-R program in the analysis of various types of integrated circuit technologies is studied.

  8. Process design kit and circuits at a 2 µm technology node for flexible wearable electronics applications (Conference Presentation)

    Science.gov (United States)

    Torres-Miranda, Miguel; Petritz, Andreas; Gold, Herbert; Stadlober, Barbara

    2016-09-01

    In this work we present our most advanced technology node of organic thin film transistors (OTFTs) manufactured with a channel length as short as 2 μm by contact photolithography and a self-alignment process directly on a plastic substrate. Our process design kit (PDK) is described with P-type transistors, capacitors and 3 metal layers for connections of complex circuits. The OTFTs are composed of a double dielectric layer with a photopatternable ultra thin polymer (PNDPE) and alumina, with a thickness on the order of 100 nm. The organic semiconductor is either Pentacene or DNTT, which have a stable average mobility up to 0.1 cm2/Vs. Finally, a polymer (e.g.: Parylene-C) is used as a passivation layer. We describe also our design rules for the placement of standard circuit cells. A "plastic wafer" is fabricated containing 49 dies. Each die of 1 cm2 has between 25 to 50 devices, proving larger scale integration in such a small space, unique in organic technologies. Finally, we present the design (by simulations using a Spice model for OTFTs) and the test of analog and digital basic circuits: amplifiers with DC gains of about 20 dB, comparators, inverters and logic gates working in the frequency range of 1-10 kHz. These standard circuit cells could be used for signal conditioning and integrated as active matrices for flexible sensors from 3rd party institutions, thus opening our fab to new ideas and sophisticated pre-industrial low cost applications for the emerging fields of biomedical devices and wearable electronics for virtual/augmented reality.

  9. Digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs)

    Science.gov (United States)

    Ceylan, Omer; Shafique, Atia; Burak, Abdurrahman; Caliskan, Can; Yazici, Melik; Abbasi, Shahbaz; Galioglu, Arman; Kayahan, Huseyin; Gurbuz, Yasar

    2016-11-01

    This paper presents a digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs) with a charge handling capacity of 44.8 Me- while achieving quantization noise of 198 e- and power consumption of 14.35 mW. Conventional pulse frequency modulation (PFM) method is supported by a single slope ramp ADC technique to have a very low quantization noise together with a low power consumption. The proposed digital TDI ROIC converts the photocurrent into digital domain in two phases; in the first phase, most significant bits (MSBs) are generated by the conventional PFM technique in the charge domain, while in the second phase least significant bits (LSBs) are generated by a single slope ramp ADC in the time domain. A 90 × 8 prototype has been fabricated and verified, showing a significantly improved signal-to-noise ratio (SNR) of 51 dB for low illumination levels (280,000 collected electrons), which is attributed to the TDI implementation method and very low quantization noise due to the single slope ADC implemented for LSBs. Proposed digital TDI ROIC proves the benefit of digital readouts for scanning arrays enabling smaller pixel pitches, better SNR for the low illumination levels and lower power consumption compared to analog TDI readouts for scanning arrays.

  10. On the Integration of Digital Design and Analysis Tools

    DEFF Research Database (Denmark)

    Klitgaard, Jens; Kirkegaard, Poul Henning; Mullins, Michael

    2006-01-01

    the two types of tools. The paper therefore looks at integration of the two types in a prototype for a tool which allows aesthetics evaluation, and at the same time gives the architect instant technical feedback on ideas already in the initial sketching phase. The aim of the research is to look...... possible approaches for working with digital tectonics by means of acoustics: The architects, the architect-engineer or hybrid practitioner and finally a prototype for a possible digital tectonic tool. For the third approach in the case study a prototype digital tectonic tool is tested on the design......The digital design tools used by architects and engineers today are very useful with respect to their specific fields of aesthetical or technical evaluation. It is not yet possible to fully use the potential of the computer in the design process, as there is no well functioning interplay between...

  11. System Guidelines for EMC Safety-Critical Circuits: Design, Selection, and Margin Demonstration

    Science.gov (United States)

    Lawton, R. M.

    1996-01-01

    Demonstration of required safety margins on critical electrical/electronic circuits in large complex systems has become an implementation and cost problem. These margins are the difference between the activation level of the circuit and the electrical noise on the circuit in the actual operating environment. This document discusses the origin of the requirement and gives a detailed process flow for the identification of the system electromagnetic compatibility (EMC) critical circuit list. The process flow discusses the roles of engineering disciplines such as systems engineering, safety, and EMC. Design and analysis guidelines are provided to assist the designer in assuring the system design has a high probability of meeting the margin requirements. Examples of approaches used on actual programs (Skylab and Space Shuttle Solid Rocket Booster) are provided to show how variations of the approach can be used successfully.

  12. Measuring Io's Lava Eruption Temperatures with a Novel Infrared Detector and Digital Readout Circuit

    Science.gov (United States)

    Davies, Ashley; Gunapala, Sarath; Rafol, B., Sir; Soibel, Alexander; Ting, David Z.

    2016-10-01

    One method of determining lava eruption temperature of Io's dominant silicate lavas is by measuring radiant flux at two or more wavelengths and fitting a black-body thermal emission function. Only certain styles of volcanic activity are suitable, those where thermal emission is from a restricted range of surface temperatures close to eruption temperature. Such processes include [1] large lava fountains; [2] fountaining in lava lakes; and [3] lava tube skylights. Problems that must be overcome are (1) the cooling of the lava between data acquisitions at different wavelengths; (2) the unknown magnitude of thermal emission, which often led to detector saturation; and (3) thermal emission changing on a shorter timescale than the observation integration time. We can overcome these problems by using the HOT-BIRD detector [4] and an advanced digital readout circuit [5]. We have created an instrument model that allows different instrument parameters (including mirror diameter, number of signal splits, exposure duration, filter band pass, and optics transmissivity) to be tested so as to determine eruption detectability. We find that a short-wavelength infrared instrument on an Io flyby mission can achieve simultaneity of observations by splitting the incoming signal for all relevant eruption processes and obtain data fast enough to remove uncertainties in accurate determination of the highest lava surface temperatures exposed. Observations at 1 and 1.5 μm are sufficient to do this. Lava temperature determinations are also possible with a visible wavelength detector [3] so long as data at different wavelengths are obtained simultaneously and integration time is very short. This is especially important for examining the thermal emission from lava tube skylights [3] due to rapidly-changing viewing geometry during close flybys. References: [1] Davies et al., 2001, JGR, 106, 33079-33104. [2] Davies et al., 2011, GRL, 38, L21308. [3] Davies et al., 2016, Icarus, in press. [4

  13. A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

    National Research Council Canada - National Science Library

    F. Khateb; S. Bay Abo Dabbous; S. Vlassis

    2013-01-01

    ...). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application...

  14. Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs

    Directory of Open Access Journals (Sweden)

    Reza Hashemian

    2010-01-01

    Full Text Available A new technique is presented for biasing of analog circuits. The biasing design begins with local biasing of the nonlinear components (transistors, done according to the pre-specified operating points (OPs and for the best performance of the circuit. Next, the transistors are replaced with their linear models to perform the AC design. Upon finishing with the AC design we need to move from the local biasing to global (normal biasing while the OPs are kept unchanged. Here fixators—nullators plus sources—are shown to be very instrumental and with norators—as the place holders for the DC supplies in the circuit—they make pairs. The solution of the circuit so prepared provides the DC supplies at the designated locations in the circuit. The rules to engage in circuit analysis with fixator-norator pairs are discussed, and numerous pitfalls in this line are specified. Finally, two design examples are worked out that clearly demonstrate the capability and power of the proposed technique for biasing any analog circuit.

  15. Dynamic SVL and body bias for low leakage power and high performance in CMOS digital circuits

    Science.gov (United States)

    Deshmukh, Jyoti; Khare, Kavita

    2012-12-01

    In this article, a new complementary metal oxide semiconductor design scheme called dynamic self-controllable voltage level (DSVL) is proposed. In the proposed scheme, leakage power is controlled by dynamically disconnecting supply to inactive blocks and adjusting body bias to further limit leakage and to maintain performance. Leakage power measurements at 1.8 V, 75°C demonstrate power reduction by 59.4% in case of 1 bit full adder and by 43.0% in case of a chain of four inverters using SVL circuit as a power switch. Furthermore, we achieve leakage power reduction by 94.7% in case of 1 bit full adder and by 91.8% in case of a chain of four inverters using dynamic body bias. The forward body bias of 0.45 V applied in active mode improves the maximum operating frequency by 16% in case of 1 bit full adder and 5.55% in case of a chain of inverters. Analysis shows that additional benefits of using the DSVL and body bias include high performance, low leakage power consumption in sleep mode, single threshold implementation and state retention even in standby mode.

  16. Analysis, synchronization and circuit design of a novel butterfly attractor

    Science.gov (United States)

    Pehlivan, Ihsan; Moroz, Irene M.; Vaidyanathan, Sundarapandian

    2014-09-01

    This research paper introduces a novel three-dimensional autonomous system, whose dynamics support periodic and chaotic butterfly attractors as certain parameters vary. A special case of this system, exhibiting reflectional symmetry, is amenable to analytical and numerical analysis. Qualitative properties of the new chaotic system are discussed in detail. Adaptive control laws are derived to achieve global chaotic synchronization of the new chaotic system with unknown parameters. Furthermore, a novel electronic circuit realization of the new chaotic system is presented, examined and realized using Orcad-PSpice program and physical components. The proposed novel butterfly chaotic attractor is very useful for the deliberate generation of chaos in applications.

  17. Recent advances in the analysis, design and optimization of Digital Delta-Sigma Modulators

    Science.gov (United States)

    Kennedy, Michael Peter

    Digital Delta-Sigma Modulators (DDSMs) are almost univerally used in integrated circuits for wireless communications and digital audio, particularly in fractional-N frequency synthesizers and oversampled digital-to-analog converters (DACs). A DDSM is a nonlinear dynamical system which reduces the wordlength of an oversampled digital signal without significantly degrading the SNR in the signal band. DDSMs can exhibit a number of behaviors that are characteristic of nonlinear dynamical systems such as oscillation, coexisting steady-state solutions, sensitivity to initial conditions, and sensitivity to the input. This paper explains the root cause of deterministic spurious and idle tones in DDSMs—short periodic cycles—and describes strategies to eliminate them. The use of a DDSM simplifies the design of analog circuitry in a mixed-signal system. By reducing the bus width in a prescribed way, a DDSM can also permit more efficient downstream digital signal processing—in terms of power and speed—with negligible degradation in performance.

  18. Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits

    Directory of Open Access Journals (Sweden)

    Anindya Jana

    2012-05-01

    Full Text Available Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET. SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.

  19. Design and application of cotranscriptional non-enzymatic RNA circuits and signal transducers.

    Science.gov (United States)

    Bhadra, Sanchita; Ellington, Andrew D

    2014-04-01

    Nucleic acid circuits are finding increasing real-life applications in diagnostics and synthetic biology. Although DNA has been the main operator in most nucleic acid circuits, transcriptionally produced RNA circuits could provide powerful alternatives for reagent production and their use in cells. Towards these goals, we have implemented a particular nucleic acid circuit, catalytic hairpin assembly, using RNA for both information storage and processing. Our results demonstrated that the design principles developed for DNA circuits could be readily translated to engineering RNA circuits that operated with similar kinetics and sensitivities of detection. Not only could purified RNA hairpins perform amplification reactions but RNA hairpins transcribed in vitro also mediated amplification, even without purification. Moreover, we could read the results of the non-enzymatic amplification reactions using a fluorescent RNA aptamer 'Spinach' that was engineered to undergo sequence-specific conformational changes. These advances were applied to the end-point and real-time detection of the isothermal strand displacement amplification reaction that produces single-stranded DNAs as part of its amplification cycle. We were also able to readily engineer gate structures with RNA similar to those that have previously formed the basis of DNA circuit computations. Taken together, these results validate an entirely new chemistry for the implementation of nucleic acid circuits.

  20. Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID: Device and Circuit Co-Design

    Directory of Open Access Journals (Sweden)

    Tony T. Kim

    2011-07-01

    Full Text Available Recently, double-gate MOSFETs (DGMOSFETs have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.