Structural and composition investigations at delayered locations of low k integrated circuit device by gas-assisted focused ion beam

Energy Technology Data Exchange (ETDEWEB)

Wang, Dandan, E-mail: dandan.wang@globalfoundries.com; Kee Tan, Pik; Yamin Huang, Maggie; Lam, Jeffrey; Mai, Zhihong [Technology Development Department, GLOBALFOUNDRIES Singapore Pte. Ltd., 60 Woodlands Industrial Park D, Street 2, Singapore 738406 (Singapore)

2014-05-15

The authors report a new delayering technique – gas-assisted focused ion beam (FIB) method and its effects on the top layer materials of integrated circuit (IC) device. It demonstrates a highly efficient failure analysis with investigations on the precise location. After removing the dielectric layers under the bombardment of an ion beam, the chemical composition of the top layer was altered with the reduced oxygen content. Further energy-dispersive x-ray spectroscopy and Fourier transform infrared analysis revealed that the oxygen reduction lead to appreciable silicon suboxide formation. Our findings with structural and composition alteration of dielectric layer after FIB delayering open up a new insight avenue for the failure analysis in IC devices.

Managing contamination delay to improve Timing Speculation architectures

Directory of Open Access Journals (Sweden)

Naga Durga Prasad Avirneni

2016-08-01

Full Text Available Timing Speculation (TS is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. Also, we propose an algorithm to efficiently add delay buffers to selected short paths while keeping down the area penalty. We present our algorithm results for ISCAS-85 suite and show that it is possible to increase the circuit contamination delay by up to 30% without affecting the propagation delay. We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact.

Temperature Dependent Wire Delay Estimation in Floorplanning

DEFF Research Database (Denmark)

Winther, Andreas Thor; Liu, Wei; Nannarelli, Alberto

2011-01-01

Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability. In this w......Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability....... In this work, we show that using wirelength as the evaluation metric does not always produce a floorplan with the shortest delay. We propose a temperature dependent wire delay estimation method for thermal aware floorplanning algorithms, which takes into account the thermal effect on wire delay. The experiment...

Development of a non-delay-line constant-fraction discriminator

International Nuclear Information System (INIS)

Yang Tao; Zhao Bo; Zhang Chi

2002-01-01

A Non-Delay-Line Constant-Fraction Discriminator (CFD) timing circuit is introduced. The delay line in the CFD is replaced with a low pass filter in this simplified circuit. The timing resolution of the CFD is better than 150 ps

Hybdrid integral circuit for proportional chambers

International Nuclear Information System (INIS)

Yanik, R.; Khudy, M.; Povinets, P.; Strmen', P.; Grabachek, Z.; Feshchenko, A.A.

1978-01-01

Outlined briefly are a hybrid integrated circuit of the channel. One channel contains an input amplifier, delay circuit, and memory register on the base of the D-type flip-flop and controlled by the recording gate pulse. Provided at the output of the channel is a readout gating circuit. Presented are the flowsheet of the channel, the shaper amplifier and logical channel. At present the logical circuit was accepted for manufacture

Dynamics of Nonlinear Time-Delay Systems

CERN Document Server

Lakshmanan, Muthusamy

2010-01-01

Synchronization of chaotic systems, a patently nonlinear phenomenon, has emerged as a highly active interdisciplinary research topic at the interface of physics, biology, applied mathematics and engineering sciences. In this connection, time-delay systems described by delay differential equations have developed as particularly suitable tools for modeling specific dynamical systems. Indeed, time-delay is ubiquitous in many physical systems, for example due to finite switching speeds of amplifiers in electronic circuits, finite lengths of vehicles in traffic flows, finite signal propagation times in biological networks and circuits, and quite generally whenever memory effects are relevant. This monograph presents the basics of chaotic time-delay systems and their synchronization with an emphasis on the effects of time-delay feedback which give rise to new collective dynamics. Special attention is devoted to scalar chaotic/hyperchaotic time-delay systems, and some higher order models, occurring in different bran...

Global synchronization criteria with channel time-delay for chaotic time-delay system

International Nuclear Information System (INIS)

Sun Jitao

2004-01-01

Based on the Lyapunov stabilization theory, matrix measure, and linear matrix inequality (LMIs), this paper studies the chaos synchronization of time-delay system using the unidirectional linear error feedback coupling with time-delay. Some generic conditions of chaos synchronization with time-delay in the transmission channel is established. The chaotic Chua's circuit is used for illustration, where the coupling parameters are determined according to the criteria under which the global chaos synchronization of the time-delay coupled systems is achieved

Low cost design of microprocessor EDAC circuit

International Nuclear Information System (INIS)

Hao Li; Yu Lixin; Peng Heping; Zhuang Wei

2015-01-01

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)

Modeling delay in genetic networks: from delay birth-death processes to delay stochastic differential equations.

Science.gov (United States)

Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Bennett, Matthew R; Josić, Krešimir; Ott, William

2014-05-28

Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay.

Modeling delay in genetic networks: From delay birth-death processes to delay stochastic differential equations

Energy Technology Data Exchange (ETDEWEB)

Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Ott, William [Department of Mathematics, University of Houston, Houston, Texas 77004 (United States); Bennett, Matthew R. [Department of Biochemistry and Cell Biology, Rice University, Houston, Texas 77204, USA and Institute of Biosciences and Bioengineering, Rice University, Houston, Texas 77005 (United States); Josić, Krešimir [Department of Mathematics, University of Houston, Houston, Texas 77004 (United States); Department of Biology and Biochemistry, University of Houston, Houston, Texas 77204 (United States)

2014-05-28

Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay.

Modeling delay in genetic networks: From delay birth-death processes to delay stochastic differential equations

International Nuclear Information System (INIS)

Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Ott, William; Bennett, Matthew R.; Josić, Krešimir

2014-01-01

Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay

Break-before-make CMOS inverter for power-efficient delay implementation.

Science.gov (United States)

Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

2014-01-01

A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

A high-precision synchronization circuit for clock distribution

International Nuclear Information System (INIS)

Lu Chong; Tan Hongzhou; Duan Zhikui; Ding Yi

2015-01-01

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm 2 , and the power consumption is 1.64 mW at 500 MHz. (paper)

Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

Directory of Open Access Journals (Sweden)

Michael S. Hsiao

2002-01-01

Full Text Available Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

UWB delay and multiply receiver

Energy Technology Data Exchange (ETDEWEB)

Dallum, Gregory E.; Pratt, Garth C.; Haugen, Peter C.; Romero, Carlos E.

2013-09-10

An ultra-wideband (UWB) delay and multiply receiver is formed of a receive antenna; a variable gain attenuator connected to the receive antenna; a signal splitter connected to the variable gain attenuator; a multiplier having one input connected to an undelayed signal from the signal splitter and another input connected to a delayed signal from the signal splitter, the delay between the splitter signals being equal to the spacing between pulses from a transmitter whose pulses are being received by the receive antenna; a peak detection circuit connected to the output of the multiplier and connected to the variable gain attenuator to control the variable gain attenuator to maintain a constant amplitude output from the multiplier; and a digital output circuit connected to the output of the multiplier.

A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

Science.gov (United States)

Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

2016-01-01

A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

An electronic implementation for Liao's chaotic delayed neuron model with non-monotonous activation function

International Nuclear Information System (INIS)

Duan Shukai; Liao Xiaofeng

2007-01-01

A new chaotic delayed neuron model with non-monotonously increasing transfer function, called as chaotic Liao's delayed neuron model, was recently reported and analyzed. An electronic implementation of this model is described in detail. At the same time, some methods in circuit design, especially for circuit with time delayed unit and non-monotonously increasing activation unit, are also considered carefully. We find that the dynamical behaviors of the designed circuits are closely similar to the results predicted by numerical experiments

Control circuits for the 1.3 GeV electron synchrotron

International Nuclear Information System (INIS)

Asaoka, S.; Shiino, K.; Yoshioka, M.; Norimura, K.

1980-01-01

Following control circuits for the 1.3 GeV electron synchrotron, Institute for Nuclear Study, University of Tokyo, have been designed and constructed. 1. Variable delay circuits for the timing pulse of the synchrotron. 2. An alarm circuit for sputter ion pumps. 3. A sample and hold circuit for digital display and computer control of the beam intensity. This report describes detailes of the circuits and their specificatons. (author)

Variable Delay Element For Jitter Control In High Speed Data Links

Science.gov (United States)

Livolsi, Robert R.

2002-06-11

A circuit and method for decreasing the amount of jitter present at the receiver input of high speed data links which uses a driver circuit for input from a high speed data link which comprises a logic circuit having a first section (1) which provides data latches, a second section (2) which provides a circuit generates a pre-destorted output and for compensating for level dependent jitter having an OR function element and a NOR function element each of which is coupled to two inputs and to a variable delay element as an input which provides a bi-modal delay for pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in the driver circuit. A fifth section is used for logic testing the driver circuit.

An electronic implementation for Liao's chaotic delayed neuron model with non-monotonous activation function

Energy Technology Data Exchange (ETDEWEB)

Duan Shukai [Department of Computer Science and Engineering, Chongqing University, Chongqing 400044 (China); School of Electronic and Information Engineering, Southwest University, Chongqing 400715 (China)], E-mail: duansk@swu.edu.cn; Liao Xiaofeng [Department of Computer Science and Engineering, Chongqing University, Chongqing 400044 (China)], E-mail: xfliao@cqu.edu.cn

2007-09-10

A new chaotic delayed neuron model with non-monotonously increasing transfer function, called as chaotic Liao's delayed neuron model, was recently reported and analyzed. An electronic implementation of this model is described in detail. At the same time, some methods in circuit design, especially for circuit with time delayed unit and non-monotonously increasing activation unit, are also considered carefully. We find that the dynamical behaviors of the designed circuits are closely similar to the results predicted by numerical experiments.

Synchronization circuit for shaping electron beam picosecond pulses

International Nuclear Information System (INIS)

Pavlov, Yu.S.; Solov'ev, N.G.; Tomnikov, A.P.

1985-01-01

A fast response circuit of modulator trigger pulse synchronization of a deflector of the electron linear accelerator at 13 MeV with the given phase of HF-voltage is described. The circuit is constructed using K500 and K100 integrated emitter-coupled logics circuits. Main parameters of a synchropulse are duration of 20-50 ns, pulse rise time of 1-5 ns, pulse amplitude >=10 V, delay instability of a trigger pulse <=+-0.05 ns. A radiopulse with 3 μs duration, 5 V amplitude and 400 Hz frequency enters the circuit input. The circuit can operate at both pulsed operation and continuous modes

Non-noise instabilities in oscilloscope trigger circuits

International Nuclear Information System (INIS)

Burd, Aleksander

2011-01-01

The paper discusses two phenomena called tremor, which result in incorrect operation of the oscilloscope trigger circuits. Both of them change delays introduced by the trigger circuit, resulting in horizontal shifts of traces on the screen, but the origins of the two phenomena are different. Both kinds of tremors in the oscilloscope trigger circuits produce images on the screen, which often are similar to those resulting from the noise jitter. Hence, limited knowledge of tremor may be a source of improper interpretation of the oscilloscope measurements. On the other hand tremor can be considered as a different approach to the problem of flip-flop circuit's metastability

CHEETAH: circuit-switched high-speed end-to-end transport architecture

Science.gov (United States)

Veeraraghavan, Malathi; Zheng, Xuan; Lee, Hyuk; Gardner, M.; Feng, Wuchun

2003-10-01

Leveraging the dominance of Ethernet in LANs and SONET/SDH in MANs and WANs, we propose a service called CHEETAH (Circuit-switched High-speed End-to-End Transport ArcHitecture). The service concept is to provide end hosts with high-speed, end-to-end circuit connectivity on a call-by-call shared basis, where a "circuit" consists of Ethernet segments at the ends that are mapped into Ethernet-over-SONET long-distance circuits. This paper focuses on the file-transfer application for such circuits. For this application, the CHEETAH service is proposed as an add-on to the primary Internet access service already in place for enterprise hosts. This allows an end host that is sending a file to first attempt setting up an end-to-end Ethernet/EoS circuit, and if rejected, fall back to the TCP/IP path. If the circuit setup is successful, the end host will enjoy a much shorter file-transfer delay than on the TCP/IP path. To determine the conditions under which an end host with access to the CHEETAH service should attempt circuit setup, we analyze mean file-transfer delays as a function of call blocking probability in the circuit-switched network, probability of packet loss in the IP network, round-trip times, link rates, and so on.

Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

International Nuclear Information System (INIS)

Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun

2016-01-01

The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD

Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

Energy Technology Data Exchange (ETDEWEB)

Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun [KHNP CRI, Daejeon (Korea, Republic of)

2016-10-15

The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD.

Updating Procedures Can Reorganize the Neural Circuit Supporting a Fear Memory.

Science.gov (United States)

Kwapis, Janine L; Jarome, Timothy J; Ferrara, Nicole C; Helmstetter, Fred J

2017-07-01

Established memories undergo a period of vulnerability following retrieval, a process termed 'reconsolidation.' Recent work has shown that the hypothetical process of reconsolidation is only triggered when new information is presented during retrieval, suggesting that this process may allow existing memories to be modified. Reconsolidation has received increasing attention as a possible therapeutic target for treating disorders that stem from traumatic memories, yet little is known about how this process changes the original memory. In particular, it is unknown whether reconsolidation can reorganize the neural circuit supporting an existing memory after that memory is modified with new information. Here, we show that trace fear memory undergoes a protein synthesis-dependent reconsolidation process following exposure to a single updating trial of delay conditioning. Further, this reconsolidation-dependent updating process appears to reorganize the neural circuit supporting the trace-trained memory, so that it better reflects the circuit supporting delay fear. Specifically, after a trace-to-delay update session, the amygdala is now required for extinction of the updated memory but the retrosplenial cortex is no longer required for retrieval. These results suggest that updating procedures could be used to force a complex, poorly defined memory circuit to rely on a better-defined neural circuit that may be more amenable to behavioral or pharmacological manipulation. This is the first evidence that exposure to new information can fundamentally reorganize the neural circuit supporting an existing memory.

High-explosive-driven delay line pulse generator

International Nuclear Information System (INIS)

Shearer, J.W.

1982-01-01

The inclusion of a delay line circuit into the design of a high-explosive-driven generator shortens the time constant of the output pulse. After a brief review of generator concepts and previously described pulse-shortening methods, a geometry is presented which incorporates delay line circuit techcniques into a coil generator. The circuit constants are adjusted to match the velocity of the generated electromagnetic wave to the detonation velocity of the high explosive. The proposed generator can be modeled by adding a variable inductance term to the telegrapher's equation. A particular solution of this equation is useful for exploring the operational parameters of the generator. The duration of the electromagnetic pulse equals the radial expansion time of the high-explosive-driven armature until it strikes the coil. Because the impedance of the generator is a constant, the current multiplication factor is limited only by nonlinear effects such as voltage breakdown, diffusion, and compression at high energies

Global chaos synchronization with channel time-delay

International Nuclear Information System (INIS)

Jiang Guoping; Zheng Weixing; Chen Guanrong

2004-01-01

This paper addresses a practical issue in chaos synchronization where there is a time-delay in the receiver as compared with the transmitter. A new synchronization scheme and a general criterion for global chaos synchronization are proposed and developed from the approach of unidirectional linear error feedback coupling with time-delay. The chaotic Chua's circuit is used for illustration, where the coupling parameters are determined according to the criterion under which the global chaos synchronization of the time-delay coupled systems is achieved

A Quantized Analog Delay for an ir-UWB Quadrature Downconversion Autocorrelation Receiver

NARCIS (Netherlands)

Bagga, S.; Zhang, L.; Serdijn, W.A.; Long, J.R.; Busking, E.B.

2005-01-01

A quantized analog delay is designed as a requirement for the autocorrelation function in the quadrature downconversion autocorrelation receiver (QDAR). The quantized analog delay is comprised of a quantizer, multiple binary delay lines and an adder circuit. Being the foremost element, the quantizer

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Shikha Panwar

2014-01-01

Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

Multiwire proportional counter (lecture by an electromagnetic delay line)

International Nuclear Information System (INIS)

Bruere-Dawson, R.

1989-01-01

For track localisation of ionizing particles with multiwire proportional chamber, an electronic chain including amplifying, shaping and memorizing circuits is required for each wire. In order to lower the cost of this type of detector, an electromagnetic delay line is proposed among various possibilities. In this paper, different coupling modes between chamber and delay line are studied with their respective advantages. The realization of one meter long delay line with a unit delay time of 15 ns per cm is also presented [fr

Estimating Delays In ASIC's

Science.gov (United States)

Burke, Gary; Nesheiwat, Jeffrey; Su, Ling

1994-01-01

Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.

Delay line clipping in a scintillation camera system

International Nuclear Information System (INIS)

Hatch, K.F.

1979-01-01

The present invention provides a novel base line restoring circuit and a novel delay line clipping circuit in a scintillation camera system. Single and double delay line clipped signal waveforms are generated for increasing the operational frequency and fidelity of data detection of the camera system by base line distortion such as undershooting, overshooting, and capacitive build-up. The camera system includes a set of photomultiplier tubes and associated amplifiers which generate sequences of pulses. These pulses are pulse-height analyzed for detecting a scintillation having an energy level which falls within a predetermined energy range. Data pulses are combined to provide coordinates and energy of photopeak events. The amplifiers are biassed out of saturation over all ranges of pulse energy level and count rate. Single delay line clipping circuitry is provided for narrowing the pulse width of the decaying electrical data pulses which increase operating speed without the occurrence of data loss. (JTA)

The review of radiation effects of γ total dose in CMOS circuits

International Nuclear Information System (INIS)

Chen Panxun; Gao Wenming; Xie Zeyuan; Mi Bang

1992-01-01

Radiation performances of commercial and rad-hard CMOS circuits are reviewed. Threshold voltage, static power current, V in -V out characteristic and propagation delay time related with total dose are presented for CMOS circuits from several manufacturing processes. The performance of radiation-annealing of experimental circuits had been observed for two years. The comparison has been made between the CMOS circuits made in China and the commercial RCA products. 60 Co γ source can serve as γ simulator of the nuclear explosion

Circuit, especially for digital nuclear gyroscope systems

International Nuclear Information System (INIS)

Lowdenslager, J.R.

1974-01-01

The circuit with at least one or two spin generator shows a digital phase synchronizing loop in solid-state construction without movable mechanical parts. It is stable, may be turned in one direction any number of times without saturation, and also remains phase-synchronized when input signals are turned off. For this purpose, crystal oscillators with certain resonance frequencies are used. The spin generators are coupled at the outled side with filtering, squaring, and differential connections generating control impulses synchronous to the spin generators. Step divider circuits are connected to the oscillators, which act upon flip-flop registers. This is controlled by the filtering, squaring, and differential connections. Furthermore, field proportional control circuits with registers, advancing and delay circuits are provided, the registers being connected at the outlet side with digital adders and subtractors. The digital adder serves inertial-related purposes. (DG) [de

4-channel time delayed pulse generator

International Nuclear Information System (INIS)

Wetzel, L.F.S.; Rossi, J.O.; Del Bosco, E.

1987-02-01

It is described the project of a 4-channel delayed pulse generator employed to trigger the plasma centrifuge experiment of the Laboratorio Associado de Plasmas. The circuit delivers pulses with amplitude of 15V, full width at half maximum of 50μs and rise time of 0.7μs. The maximum time delay is 100ms. There are two channels with a fine adjustment of 0-1ms. The system can be manually or automatically driven. (author) [pt

Thermal Aware Floorplanning Incorporating Temperature Dependent Wire Delay Estimation

DEFF Research Database (Denmark)

Winther, AndreasThor; Liu, Wei; Nannarelli, Alberto

2015-01-01

Temperature has a negative impact on metal resistance and thus wire delay. In state-of-the-art VLSI circuits, large thermal gradients usually exist due to the uneven distribution of heat sources. The difference in wire temperature can lead to performance mismatch because wires of the same length...... can have different delay. Traditional floorplanning algorithms use wirelength to estimate wire performance. In this work, we show that this does not always produce a design with the shortest delay and we propose a floorplanning algorithm taking into account temperature dependent wire delay as one...

A monolithic constant-fraction discriminator using distributed R-C delay-line shaping

International Nuclear Information System (INIS)

Simpson, M.L.; Young, G.R.; Xu, M.

1995-01-01

A monolithic, CMOS, constant-fraction discriminator (CFD) was fabricated in the Orbit Semiconductor, 1.2 μ N-well process. This circuit uses an on-chip, distributed, R-C delay-line to realize the constant-fraction shaping. The delay-line is constructed from a narrow, 500-μ serpentine layer of polysilicon above a wide, grounded, second layer of polysilicon. This R-C delay-line generates about 1.1 ns of delay for 5 ns risetime signals with a slope degradation of only ≅ 15% and an amplitude reduction of about 6.1%. The CFD also features an automatic walk adjustment. The entire circuit, including the delay line, has a 200 μ pitch and is 950 μ long. The walk for a 5 ns risetime signal was measured as ± 100 ps over the 100:1 dynamic range from -15 mV to -1.5 mV. to -1.5 V. The CFD consumes 15 mW

Delay Insensitive Ternary CMOS Logic for Secure Hardware

Directory of Open Access Journals (Sweden)

Ravi S. P. Nair

2015-09-01

Full Text Available As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI. This paper develops the Delay-Insensitive Ternary Logic (DITL asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB and NULL Convention Logic (NCL on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

Science.gov (United States)

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Set of CAMAC modules on the base of large integrated circuits for an accelerator synchronization system

International Nuclear Information System (INIS)

Glejbman, Eh.M.; Pilyar, N.V.

1986-01-01

Parameters of functional moduli in the CAMAC standard developed for accelerator synchronization system are presented. They comprise BZN-8K and BZ-8K digital delay circuits, timing circuit and pulse selection circuit. In every module 3 large integral circuits of KR 580 VI53 type programmed timer, circuits of the given system bus bar interface with bus bars of crate, circuits of data recording control, 2 peripheric storage devices, circuits of initial regime setting, input and output shapers, circuits of installation and removal of blocking in channels are used

A self-adjusting delay circuit for pixel read-out chips

International Nuclear Information System (INIS)

Raith, B.

1997-01-01

A simple concept for automatic adjustment of important VLSI-circuit properties was proposed in (Fischer and Joens, Nucl. Instr. and. Meth.). As an application, a self-adjusting monoflop is reviewed, and detailed measurements are discussed regarding a possible implementation in the LHC 1 read-out chip for the ATLAS experiment (ATLAS Internal Note, 1995). (orig.)

New reactor safety circuit for low-power-level operation

International Nuclear Information System (INIS)

McDowell, W.P.; Keefe, D.J.; Rusch, G.K.

1978-01-01

In the operation of nuclear reactors at low-power levels, one of the primary instrumentation problems is that the statistical fluctuations of reactor neutron population are accentuated by conventional log-count-rate and differentiating circuits and can cause frequent spurious scrams unless long time constants are incorporated in the circuit. Excessive time constants may introduce undesirable delay in the circuit response to legitimate scram signals. The paper develops the concept of a count doubling-time monitor which generates a scram signal if the number of counts from a pulse type neutron detector doubles in a given period of time. The paper demonstrates the theoretical relation between count doubling time and asymptomatic periods. A practical circuit to implement the function is described

Multiplier less high-speed squaring circuit for binary numbers

Science.gov (United States)

Sethi, Kabiraj; Panda, Rutuparna

2015-03-01

The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

Design and implementation of high-precision and low-jitter programmable delay circuitry

International Nuclear Information System (INIS)

Gao Yuan; Cui Ke; Zhang Hongfei; Luo Chunli; Yang Dongxu; Liang Hao; Wang Jian

2011-01-01

A programmable delay circuit design which has characteristics of high-precision, low-jitter, wide-programmable-range and low power is introduced. The delay circuitry uses the scheme which has two parts: the coarse delay and the fine delay that could be controlled separately. Using different coarse delay chip can reach different maximum programmable range. And the fine delay programmable chip has the minimum step which is down to 10 ps. The whole circuitry jitter will be less than 100 ps. The design has been successfully applied in Quantum Key Distribution experiment. (authors)

Stochastic Mesocortical Dynamics and Robustness of Working Memory during Delay-Period.

Directory of Open Access Journals (Sweden)

Melissa Reneaux

Full Text Available The role of prefronto-mesoprefrontal system in the dopaminergic modulation of working memory during delayed response tasks is well-known. Recently, a dynamical model of the closed-loop mesocortical circuit has been proposed which employs a deterministic framework to elucidate the system's behavior in a qualitative manner. Under natural conditions, noise emanating from various sources affects the circuit's functioning to a great extent. Accordingly in the present study, we reformulate the model into a stochastic framework and investigate its steady state properties in the presence of constant background noise during delay-period. From the steady state distribution, global potential landscape and signal-to-noise ratio are obtained which help in defining robustness of the circuit dynamics. This provides insight into the robustness of working memory during delay-period against its disruption due to background noise. The findings reveal that the global profile of circuit's robustness is predominantly governed by the level of D1 receptor activity and high D1 receptor stimulation favors the working memory-associated sustained-firing state over the spontaneous-activity state of the system. Moreover, the circuit's robustness is further fine-tuned by the levels of excitatory and inhibitory activities in a way such that the robustness of sustained-firing state exhibits an inverted-U shaped profile with respect to D1 receptor stimulation. It is predicted that the most robust working memory is formed possibly at a subtle ratio of the excitatory and inhibitory activities achieved at a critical level of D1 receptor stimulation. The study also paves a way to understand various cognitive deficits observed in old-age, acute stress and schizophrenia and suggests possible mechanistic routes to the working memory impairments based on the circuit's robustness profile.

Stochastic Mesocortical Dynamics and Robustness of Working Memory during Delay-Period.

Science.gov (United States)

Reneaux, Melissa; Gupta, Rahul; Karmeshu

2015-01-01

The role of prefronto-mesoprefrontal system in the dopaminergic modulation of working memory during delayed response tasks is well-known. Recently, a dynamical model of the closed-loop mesocortical circuit has been proposed which employs a deterministic framework to elucidate the system's behavior in a qualitative manner. Under natural conditions, noise emanating from various sources affects the circuit's functioning to a great extent. Accordingly in the present study, we reformulate the model into a stochastic framework and investigate its steady state properties in the presence of constant background noise during delay-period. From the steady state distribution, global potential landscape and signal-to-noise ratio are obtained which help in defining robustness of the circuit dynamics. This provides insight into the robustness of working memory during delay-period against its disruption due to background noise. The findings reveal that the global profile of circuit's robustness is predominantly governed by the level of D1 receptor activity and high D1 receptor stimulation favors the working memory-associated sustained-firing state over the spontaneous-activity state of the system. Moreover, the circuit's robustness is further fine-tuned by the levels of excitatory and inhibitory activities in a way such that the robustness of sustained-firing state exhibits an inverted-U shaped profile with respect to D1 receptor stimulation. It is predicted that the most robust working memory is formed possibly at a subtle ratio of the excitatory and inhibitory activities achieved at a critical level of D1 receptor stimulation. The study also paves a way to understand various cognitive deficits observed in old-age, acute stress and schizophrenia and suggests possible mechanistic routes to the working memory impairments based on the circuit's robustness profile.

A current-mode multi-valued adder circuit for multi-operand addition

Science.gov (United States)

Cini, Ugur; Morgül, Avni

2011-06-01

Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.

Improved On-Chip Measurement of Delay in an FPGA or ASIC

Science.gov (United States)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Test and Diagnosis for Small-Delay Defects

CERN Document Server

Tehranipoor, Mohammad; Chakrabarty, Krishnendu

2012-01-01

This book introduces new techniques for detecting and diagnosing small-delay defects (SDD) in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first book to introduce effective and scalable methodologies for screening and diagnosing small-delay defects, including important parameters such as process variations, crosstalk, and power supply noise. This book presents new techniques and methodologies to improve overall SDD detection with very small pattern sets. These methods can result in pattern counts as low as a traditional 1-detect pattern set and long path sensitization and SDD detection similar to or even better than n-detect or timing-aware pattern sets. The important design parameters and pattern-induced noises such as process variations,power supply noise (PSN) and crosstalk are taken into account in the methodologies presented. A diagnostic flow is also presented to identify whether the failure is ...

A new circuit for at-speed scan SoC testing

International Nuclear Information System (INIS)

Lin Wei; Shi Wenlong

2013-01-01

It is very important to detect transition-delay faults and stuck-at faults in system on chip (SoC) under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock (OCC) controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design. (semiconductor integrated circuits)

Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

Science.gov (United States)

Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

2011-07-01

This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

Analytical and experimental study of two delay-coupled excitable units.

Science.gov (United States)

Weicker, Lionel; Erneux, Thomas; Keuninckx, Lars; Danckaert, Jan

2014-01-01

We investigate the onset of time-periodic oscillations for a system of two identical delay-coupled excitable (nonoscillatory) units. We first analyze these solutions by using asymptotic methods. The oscillations are described as relaxation oscillations exhibiting successive slow and fast changes. The analysis highlights the determinant role of the delay during the fast transition layers. We then study experimentally a system of two coupled electronic circuits that is modeled mathematically by the same delay differential equations. We obtain quantitative agreements between analytical and experimental bifurcation diagrams.

Data readout system utilizing photonic integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

2013-10-11

We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

Science.gov (United States)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

Technology CAD for germanium CMOS circuit

Energy Technology Data Exchange (ETDEWEB)

Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

2006-12-15

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

Technology CAD for germanium CMOS circuit

International Nuclear Information System (INIS)

Saha, A.R.; Maiti, C.K.

2006-01-01

Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

Basic Guidelines for Application of Performance Standards to Commissioning of DCS Digital Circuits

Science.gov (United States)

1992-06-01

V6Z2J7 Canada Gustavo A. Cubas E. 1 Engineered Systems, Inc 2 Seccion De Transmission ATTN: Mr. David Gilfillan Direccion De Ingenieria Y Proyectos 14775...buffering, and and filter delay (for a voice circuit). Propagation delay is independent of data rate, while buffering delay is inversely proportional to...Complexe Des Jardins, 15th Fl. 171 N. Covington Drive 75 Rene Levesque West Bloomingdale, IL 60108 Montreal, PG H2Z Canada DISTRIBUTION LIST Department

Generalized synchronization-based multiparameter estimation in modulated time-delayed systems

Science.gov (United States)

Ghosh, Dibakar; Bhattacharyya, Bidyut K.

2011-09-01

We propose a nonlinear active observer based generalized synchronization scheme for multiparameter estimation in time-delayed systems with periodic time delay. A sufficient condition for parameter estimation is derived using Krasovskii-Lyapunov theory. The suggested tool proves to be globally and asymptotically stable by means of Krasovskii-Lyapunov method. With this effective method, parameter identification and generalized synchronization of modulated time-delayed systems with all the system parameters unknown, can be achieved simultaneously. We restrict our study for multiple parameter estimation in modulated time-delayed systems with single state variable only. Theoretical proof and numerical simulation demonstrate the effectiveness and feasibility of the proposed technique. The block diagram of electronic circuit for multiple time delay system shows that the method is easily applicable in practical communication problems.

Superconducting flux flow digital circuits

International Nuclear Information System (INIS)

Martens, J.S.; Zipperian, T.E.; Hietala, V.M.; Ginley, D.S.; Tigges, C.P.; Phillips, J.M.; Siegal, M.P.

1993-01-01

The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-μm linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps, and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic

Effect of a Diagram on Primary Students' Understanding About Electric Circuits

Science.gov (United States)

Preston, Christine Margaret

2017-09-01

This article reports on the effect of using a diagram to develop primary students' conceptual understanding about electric circuits. Diagrammatic representations of electric circuits are used for teaching and assessment despite the absence of research on their pedagogical effectiveness with young learners. Individual interviews were used to closely analyse Years 3 and 5 (8-11-year-old) students' explanations about electric circuits. Data was collected from 20 students in the same school providing pre-, post- and delayed post-test dialogue. Students' thinking about electric circuits and changes in their explanations provide insights into the role of diagrams in understanding science concepts. Findings indicate that diagram interaction positively enhanced understanding, challenged non-scientific views and promoted scientific models of electric circuits. Differences in students' understanding about electric circuits were influenced by prior knowledge, meta-conceptual awareness and diagram conventions including a stylistic feature of the diagram used. A significant finding that students' conceptual models of electric circuits were energy rather than current based has implications for electricity instruction at the primary level.

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

Science.gov (United States)

Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

Fast 4-2 Compressor of Booth Multiplier Circuits for High-Speed RISC Processor

Science.gov (United States)

Yuan, S. C.

2008-11-01

We use different XOR circuits to optimize the XOR structure 4-2 compressor, and design the transmission gates(TG) 4-2 compressor use single to dual rail circuit configurations. The maximum propagation delay, the power consumption and the layout area of the designed 4-2 compressors are simulated with 0.35μm and 0.25μm CMOS process parameters and compared with results of the synthesized 4-2 circuits, and show that the designed 4-2 compressors are faster and area smaller than the synthesized one.

Installations having pressurised fluid circuits

International Nuclear Information System (INIS)

Rigg, S.; Grant, J.

1977-01-01

Reference is made to nuclear installations having pressurised coolant flow circuits. Breaches in such circuits may quickly result in much damage to the plant. Devices such as non-return valves, orifice plates, and automatically operated shut-off valves have been provided to prevent or reduce fluid flow through a breached pipe line, but such devices have several disadvantages; they may present large restrictions to normal flow of coolant, and may depend on the operation of ancillary equipment, with consequent delay in bringing them into operation in an emergency. Other expedients that have been adopted to prevent or reduce reverse flow through an upstream breach comprise various forms of hydraulic counter flow brakes. The arrangement described has at least one variable fluid brake comprising a fluidic device connected into a duct in the pressurised circuit, the device having an inlet, an outlet, a vortex chamber between the inlet and outlet, a control jet for introducing fluid into the vortex chamber, connections communicating the inlet and the outlet into one part of the circuit and the control jet into another region at a complementary pressure so that, in the event of a breach in the circuit in one region, fluid passes from the other region to enter the vortex chamber to stimulate pressure to create a flow restricting vortex in the chamber that reduces flow through the breach. The system finds particular application to stream generating pressure tube reactors, such as the steam generating heavy water reactor at UKAEA, Winfrith. (U.K.)

Synthesis for robust synchronization of chaotic systems under output feedback control with multiple random delays

International Nuclear Information System (INIS)

Wen Guilin; Wang Qingguo; Lin Chong; Han Xu; Li Guangyao

2006-01-01

Synchronization under output feedback control with multiple random time delays is studied, using the paradigm in nonlinear physics-Chua's circuit. Compared with other synchronization control methods, output feedback control with multiple random delay is superior for a realistic synchronization application to secure communications. Sufficient condition for global stability of delay-dependent synchronization is established based on the LMI technique. Numerical simulations fully support the analytical approach, in spite of the random delays

Refractory silicides for integrated circuits

International Nuclear Information System (INIS)

Murarka, S.P.

1980-01-01

Transition metal silicides have, in the past, attracted attention because of their usefulness as high temperature materials and in integrated circuits as Schottky barrier and ohmic contacts. More recently, with the increasing silicon integrated circuits (SIC) packing density, the line widths get narrower and the sheet resistance contribution to the RC delay increases. The possibility of using low resistivity silicides, which can be formed directly on the polysilicon, makes these silicides highly attractive. The usefulness of a silicide metallization scheme for integrated circuits depends, not only on the desired low resistivity, but also on the ease with which the silicide can be formed and patterned and on the stability of the silicides throughout device processing and during actual device usage. In this paper, various properties and the formation techniques of the silicides have been reviewed. Correlations between the various properties and the metal or silicide electronic or crystallographic structure have been made to predict the more useful silicides for SIC applications. Special reference to the silicide resistivity, stress, and oxidizability during the formation and subsequent processing has been given. Various formation and etching techniques are discussed

Approaching the Processes in the Generator Circuit Breaker at Disconnection through Sustainability Concepts

Directory of Open Access Journals (Sweden)

Carmen A. Bulucea

2013-03-01

Full Text Available Nowadays, the electric connection circuits of power plants (based on fossil fuels as well as renewable sources entail generator circuit-breakers (GCBs at the generator terminals, since the presence of that electric equipment offers many advantages related to the sustainability of a power plant. In an alternating current (a.c. circuit the interruption of a short circuit is performed by the circuit-breaker at the natural passing through zero of the short-circuit current. During the current interruption, an electric arc is generated between the opened contacts of the circuit-breaker. This arc must be cooled and extinguished in a controlled way. Since the synchronous generator stator can flow via highly asymmetrical short-circuit currents, the phenomena which occur in the case of short-circuit currents interruption determine the main stresses of the generator circuit-breaker; the current interruption requirements of a GCB are significantly higher than for the distribution network circuit breakers. For shedding light on the proper moment when the generator circuit-breaker must operate, using the space phasor of the short-circuit currents, the time expression to the first zero passing of the short-circuit current is determined. Here, the manner is investigated in which various factors influence the delay of the zero passing of the short-circuit current. It is shown that the delay time is influenced by the synchronous machine parameters and by the load conditions which precede the short-circuit. Numerical simulations were conducted of the asymmetrical currents in the case of the sudden three-phase short circuit at the terminals of synchronous generators. Further in this study it is emphasized that although the phenomena produced in the electric arc at the terminals of the circuit-breaker are complicated and not completely explained, the concept of exergy is useful in understanding the physical phenomena. The article points out that just after the short-circuit

Topological Acoustic Delay Line

Science.gov (United States)

Zhang, Zhiwang; Tian, Ye; Cheng, Ying; Wei, Qi; Liu, Xiaojun; Christensen, Johan

2018-03-01

Topological protected wave engineering in artificially structured media is at the frontier of ongoing metamaterials research that is inspired by quantum mechanics. Acoustic analogues of electronic topological insulators have recently led to a wealth of new opportunities in manipulating sound propagation with strikingly unconventional acoustic edge modes immune to backscattering. Earlier fabrications of topological insulators are characterized by an unreconfigurable geometry and a very narrow frequency response, which severely hinders the exploration and design of useful devices. Here we establish topologically protected sound in reconfigurable phononic crystals that can be switched on and off simply by rotating its three-legged "atoms" without altering the lattice structure. In particular, we engineer robust phase delay defects that take advantage of the ultrabroadband reflection-free sound propagation. Such topological delay lines serve as a paradigm in compact acoustic devices, interconnects, and electroacoustic integrated circuits.

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Tooraj Nikoubin

2010-01-01

Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

Electron commutator on integrated circuits

International Nuclear Information System (INIS)

Demidenko, V.V.

1975-01-01

The scheme and the parameters of an electron 16-channel contactless commutator based entirely on integrated circuits are described. The device consists of a unit of analog keys based on field-controlled metal-insulator-semiconductor (m.i.s.) transistors, operation amplifier comparators controlling these keys, and a level distributor. The distributor is based on a ''matrix'' scheme and comprises two ring-shaped shift registers plugged in series and a decoder base on two-input logical elements I-NE. The principal dynamical parameters of the circuit are as follows: the control signal delay in the distributor. 50 nsec; the total channel switch-over time, 500-600 nsec. The commutator transmits both constant signals and pulses whose duration reaches tens of nsec. The commutator can be used in data acquisition and processing systems, for shaping complicated signals (for example), (otherwise signals), for simultaneous oscillographing of several signals, and so forth [ru

Photonic integrated circuits unveil crisis-induced intermittency.

Science.gov (United States)

Karsaklian Dal Bosco, Andreas; Akizawa, Yasuhiro; Kanno, Kazutaka; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki

2016-09-19

We experimentally investigate an intermittent route to chaos in a photonic integrated circuit consisting of a semiconductor laser with time-delayed optical feedback from a short external cavity. The transition from a period-doubling dynamics to a fully-developed chaos reveals a stage intermittently exhibiting these two dynamics. We unveil the bifurcation mechanism underlying this route to chaos by using the Lang-Kobayashi model and demonstrate that the process is based on a phenomenon of attractor expansion initiated by a particular distribution of the local Lyapunov exponents. We emphasize on the crucial importance of the distribution of the steady-state solutions introduced by the time-delayed feedback on the existence of this intermittent dynamics.

Logic delays of 5-μm resistor coupled Josephson logic

International Nuclear Information System (INIS)

Sone, J.; Yoshida, T.; Tahara, S.; Abe, H.

1982-01-01

Logic delays of resistor coupled Josephson logic (RCJL) have been investigated. An experimental circuit with a cascade chain of ten RCJL OR gates was fabricated using Pb-alloy Josephson IC technology with 5-μm minimum linewidth. Logic delay was measured to be as low as 10.8 ps with power dissipation of 11.7 μW. This demonstrates a switching operation faster than those reported for other Josephson gate designs. Comparison with computer-simulation results is also presented

Study of the phase delay in the amplitude-modulated harmonic oscillator

International Nuclear Information System (INIS)

Krupska, Aldona; Krupski, Marcin

2003-01-01

The delayed response of a damped harmonic oscillator (RLC circuit) to a slow periodic disturbance is presented. This communication is supplementary to the paper published recently (Krupska et al 2001 Eur. J. Phys. 22 133-8)

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

Miniaturization of Josephson logic circuits

International Nuclear Information System (INIS)

Ko, H.; Van Duzer, T.

1985-01-01

The performances of Current Injection Logic (CIL) and Resistor Coupled Josephson Logic (RCJL) have been evaluated for minimum features sizes ranging from 5 μm to 0.2 μm. The logic delay is limited to about 10 ps for both the CIL AND gate and the RCJL OR gate biased at 70% of maximum bias current. The maximum circuit count on an 6.35 x 6.35 chip is 13,000 for CIL gates and 20,000 for RCJL gates. Some suggestions are given for further improvements

Damping Resonant Current in a Spark-Gap Trigger Circuit to Reduce Noise

Science.gov (United States)

2009-06-01

DAMPING RESONANT CURRENT IN A SPARK- GAP TRIGGER CIRCUIT TO REDUCE NOISE E. L. Ruden Air Force Research Laboratory, Directed Energy Directorate, AFRL...REPORT TYPE N/A 3. DATES COVERED - 4. TITLE AND SUBTITLE Damping Resonant Current In A Spark- Gap Trigger Circuit To Reduce Noise 5a...thereby triggering 2 after delay 0, is 1. Each of the two rail- gaps (represented by 2) is trig- gered to close after the spark- gap (1) in the

Fractional Delayer Utilizing Hermite Interpolation with Caratheodory Representation

Directory of Open Access Journals (Sweden)

Qiang DU

2018-04-01

Full Text Available Fractional delay is indispensable for many sorts of circuits and signal processing applications. Fractional delay filter (FDF utilizing Hermite interpolation with an analog differentiator is a straightforward way to delay discrete signals. This method has a low time-domain error, but a complicated sampling module than the Shannon sampling scheme. A simplified scheme, which is based on Shannon sampling and utilizing Hermite interpolation with a digital differentiator, will lead a much higher time-domain error when the signal frequency approaches the Nyquist rate. In this letter, we propose a novel fractional delayer utilizing Hermite interpolation with Caratheodory representation. The samples of differential signal are obtained by Caratheodory representation from the samples of the original signal only. So, only one sampler is needed and the sampling module is simple. Simulation results for four types of signals demonstrate that the proposed method has significantly higher interpolation accuracy than Hermite interpolation with digital differentiator.

Analysis of the effects of time delay in clock recovery circuits based on Phase-locked loops

DEFF Research Database (Denmark)

Zibar, Darko; Oxenløwe, Leif Katsuo; Clausen, Anders

2004-01-01

Influence of time delay in a balanced optical phase-locked loops (OPLL) with a proportional integrator (Pl) filter is investigated using a delayed differential equation (DDE) is investigated. The limitations, which a time delay imposes on the Pl filter bandwidth, at increasing values of loop gain...

Proposal for a fast, zero suppressing circuit for the digitization of analog pulses over long memory times

International Nuclear Information System (INIS)

Bourgeois, F.

1984-01-01

This report describes the design principles of a fast (100 MHz) time and pulse height digitizer that can record up to 15 analog pulses over 10-80 μs memory times. Unlike other triggered circuits prepulse samples are recorded without the help of an analog delay line. The low power requirements of the circuit as well as its fast read-out characteristics make it very attractive for detectors with many digitizing channels. Conventional circuits are described as a reference for the evaluation of this new design. An ECL 10 K implementation of the circuit is presented in the third section. (orig.)

Novel concept of TDI readout circuit for LWIR detector

Science.gov (United States)

Kim, Byunghyuck; Yoon, Nanyoung; Lee, Hee Chul; Kim, Choong-Ki

2000-07-01

Noise property is the prime consideration in readout circuit design. The output noise caused by the photon noise, which dominates total noise in BLIP detectors, is limited by the integration time that an element looks at a specific point in the scene. Large integration time leads to a low noise performance. Time-delay integration (TDI) is used to effectively increase the integration time and reduce the photon noise. However, it increases the number of dead pixels and requires large integration capacitors and low noise output stage of the readout circuit. In this paper, to solve these problems, we propose a new concept of readout circuit, which performs background suppression, cell-to-cell background current non-uniformity compensation, and dead pixel correction using memory, ADC, DAC, and current copier cell. In simulation results, comparing with the conventional TDI readout circuit, the integration capacitor size can be reduced to 1/5 and trans-impedance gain can be increased by five times. Therefore, the new TDI readout circuit does not require large area and low noise output stage. And the error of skimming current is less than 2%, and the fixed pattern noise induced by cell-to-cell background current variation is reduced to less than 1%.

A note on exponential convergence of neural networks with unbounded distributed delays

Energy Technology Data Exchange (ETDEWEB)

Chu Tianguang [Intelligent Control Laboratory, Center for Systems and Control, Department of Mechanics and Engineering Science, Peking University, Beijing 100871 (China)]. E-mail: chutg@pku.edu.cn; Yang Haifeng [Intelligent Control Laboratory, Center for Systems and Control, Department of Mechanics and Engineering Science, Peking University, Beijing 100871 (China)

2007-12-15

This note examines issues concerning global exponential convergence of neural networks with unbounded distributed delays. Sufficient conditions are derived by exploiting exponentially fading memory property of delay kernel functions. The method is based on comparison principle of delay differential equations and does not need the construction of any Lyapunov functionals. It is simple yet effective in deriving less conservative exponential convergence conditions and more detailed componentwise decay estimates. The results of this note and [Chu T. An exponential convergence estimate for analog neural networks with delay. Phys Lett A 2001;283:113-8] suggest a class of neural networks whose globally exponentially convergent dynamics is completely insensitive to a wide range of time delays from arbitrary bounded discrete type to certain unbounded distributed type. This is of practical interest in designing fast and reliable neural circuits. Finally, an open question is raised on the nature of delay kernels for attaining exponential convergence in an unbounded distributed delayed neural network.

A note on exponential convergence of neural networks with unbounded distributed delays

International Nuclear Information System (INIS)

Chu Tianguang; Yang Haifeng

2007-01-01

This note examines issues concerning global exponential convergence of neural networks with unbounded distributed delays. Sufficient conditions are derived by exploiting exponentially fading memory property of delay kernel functions. The method is based on comparison principle of delay differential equations and does not need the construction of any Lyapunov functionals. It is simple yet effective in deriving less conservative exponential convergence conditions and more detailed componentwise decay estimates. The results of this note and [Chu T. An exponential convergence estimate for analog neural networks with delay. Phys Lett A 2001;283:113-8] suggest a class of neural networks whose globally exponentially convergent dynamics is completely insensitive to a wide range of time delays from arbitrary bounded discrete type to certain unbounded distributed type. This is of practical interest in designing fast and reliable neural circuits. Finally, an open question is raised on the nature of delay kernels for attaining exponential convergence in an unbounded distributed delayed neural network

Radiofrequency spark chambers and delay line resonators

International Nuclear Information System (INIS)

Sayag, Jacques

1971-01-01

According to a suggestion of A. Kastler, a spark chamber was excited by an undamped radiofrequency pulse and tracks about 1 mm wide obtained; the result was interpreted by computation of the coefficients of electronic amplification and partial ambipolar diffusion. This work led us to the construction of a new fast triggering undamped wave-train generator of very high tension (patent taken out by the C.E.A. under the no.: EN 7 134 650 the 27.9.1971). Since this apparatus uses a resonant storage line, its design implied a precise knowledge of high impedance delay lines. The experimental radiofrequency spectra of the input impedance of opened or short-circuited lines were plotted completely and analysed by the circuits theory, new measuring methods were established, dispersion relations accurately checked and the equivalence of the formulas, within the third order, with theses of Debye's Dipolar Absorption demonstrated. General properties of Hilbert's transform were also investigated. From the experimental point of view, the electromagnetic energy storage process was extended to the case of a liquid nitrogen-immersed resonant delay line. The good behavior of the cryogenic experiment, where the main difficulty of icing was overcame by the construction of special electrodes, offers great promise for extrapolation to superconductivity. (author) [fr

Short- circuit tests of circuit breakers

OpenAIRE

Chorovský, P.

2015-01-01

This paper deals with short-circuit tests of low voltage electrical devices. In the first part of this paper, there are described basic types of short- circuit tests and their principles. Direct and indirect (synthetic) tests with more details are described in the second part. Each test and principles are explained separately. Oscilogram is obtained from short-circuit tests of circuit breakers at laboratory. The aim of this research work is to propose a test circuit for performing indirect test.

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Directory of Open Access Journals (Sweden)

Yoni Aizik

2011-01-01

Full Text Available A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.

Investigation of SFQ integrated circuits using Nb fabrication technology

International Nuclear Information System (INIS)

Numata, H.; Tanaka, M.; Kitagawa, Y.; Tahara, S.

1999-01-01

In NEC's standard process, the minimum junction size is 2 μm and the critical current density (J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation (σ) of the critical current (I C ) was 0.9% for the 2 μm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits. (author)

Is the use of albumin in colloid prime solution of cardiopulmonary bypass circuit justified?

NARCIS (Netherlands)

Boks, RH; van Herwerden, LA; Takkenberg, JJM; van Oeveren, W; Gu, YJ; Wijers, MJ; Bogers, AJJC

Background. Albumin in the priming solution precoats the surface of the cardiopulmonary bypass circuit, supposedly causing delayed adsorption of fibrinogen and reduced activation and adhesion of platelets. This action may result in lower transoxygenator resistance. Because our institution uses a

Delayed Dopamine Signaling of Energy Level Builds Appetitive Long-Term Memory in Drosophila

OpenAIRE

Pierre-Yves Musso; Paul Tchenio; Thomas Preat

2015-01-01

Sensory cues relevant to a food source, such as odors, can be associated with post-ingestion signals related either to food energetic value or toxicity. Despite numerous behavioral studies, a global understanding of the mechanisms underlying these long delay associations remains out of reach. Here, we demonstrate in Drosophila that the long-term association between an odor and a nutritious sugar depends on delayed post-ingestion signaling of energy level. We show at the neural circuit level t...

Non-Foster Circuits for High Performance Antennas: Advantages and Practical Limitations

Science.gov (United States)

Jacob, Minu Mariam

The demand for miniaturized, broadband communication systems has created a need for electrically small, broadband antennas. However, all passive electrically small antennas have a fundamental gain-bandwidth limitation related to their electrical size, as first described by Wheeler and Chu. This limitation can be overcome using active non-Foster circuits (negative inductors and/or negative capacitors), which can deliver a broadband input match with active matching techniques, or can help reduce phase dispersion using negative delay effects. This thesis will illustrate the advantages of non-Foster circuits in obtaining broadband small antennas, in addition to examining their practical limitations due to noise in receive applications, and nonlinearity in transmit applications.

Commutation circuit for an HVDC circuit breaker

Science.gov (United States)

Premerlani, William J.

1981-01-01

A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

Introduction to Focus Issue: Time-delay dynamics

Science.gov (United States)

Erneux, Thomas; Javaloyes, Julien; Wolfrum, Matthias; Yanchuk, Serhiy

2017-11-01

The field of dynamical systems with time delay is an active research area that connects practically all scientific disciplines including mathematics, physics, engineering, biology, neuroscience, physiology, economics, and many others. This Focus Issue brings together contributions from both experimental and theoretical groups and emphasizes a large variety of applications. In particular, lasers and optoelectronic oscillators subject to time-delayed feedbacks have been explored by several authors for their specific dynamical output, but also because they are ideal test-beds for experimental studies of delay induced phenomena. Topics include the control of cavity solitons, as light spots in spatially extended systems, new devices for chaos communication or random number generation, higher order locking phenomena between delay and laser oscillation period, and systematic bifurcation studies of mode-locked laser systems. Moreover, two original theoretical approaches are explored for the so-called Low Frequency Fluctuations, a particular chaotical regime in laser output which has attracted a lot of interest for more than 30 years. Current hot problems such as the synchronization properties of networks of delay-coupled units, novel stabilization techniques, and the large delay limit of a delay differential equation are also addressed in this special issue. In addition, analytical and numerical tools for bifurcation problems with or without noise and two reviews on concrete questions are proposed. The first review deals with the rich dynamics of simple delay climate models for El Nino Southern Oscillations, and the second review concentrates on neuromorphic photonic circuits where optical elements are used to emulate spiking neurons. Finally, two interesting biological problems are considered in this Focus Issue, namely, multi-strain epidemic models and the interaction of glucose and insulin for more effective treatment.

Global exponential stability of fuzzy cellular neural networks with delays and reaction-diffusion terms

International Nuclear Information System (INIS)

Wang Jian; Lu Junguo

2008-01-01

In this paper, we study the global exponential stability of fuzzy cellular neural networks with delays and reaction-diffusion terms. By constructing a suitable Lyapunov functional and utilizing some inequality techniques, we obtain a sufficient condition for the uniqueness and global exponential stability of the equilibrium solution for a class of fuzzy cellular neural networks with delays and reaction-diffusion terms. The result imposes constraint conditions on the network parameters independently of the delay parameter. The result is also easy to check and plays an important role in the design and application of globally exponentially stable fuzzy neural circuits

QCA Gray Code Converter Circuits Using LTEx Methodology

Science.gov (United States)

Mukherjee, Chiradeep; Panda, Saradindu; Mukhopadhyay, Asish Kumar; Maji, Bansibadan

2018-04-01

The Quantum-dot Cellular Automata (QCA) is the prominent paradigm of nanotechnology considered to continue the computation at deep sub-micron regime. The QCA realizations of several multilevel circuit of arithmetic logic unit have been introduced in the recent years. However, as high fan-in Binary to Gray (B2G) and Gray to Binary (G2B) Converters exist in the processor based architecture, no attention has been paid towards the QCA instantiation of the Gray Code Converters which are anticipated to be used in 8-bit, 16-bit, 32-bit or even more bit addressable machines of Gray Code Addressing schemes. In this work the two-input Layered T module is presented to exploit the operation of an Exclusive-OR Gate (namely LTEx module) as an elemental block. The "defect-tolerant analysis" of the two-input LTEx module has been analyzed to establish the scalability and reproducibility of the LTEx module in the complex circuits. The novel formulations exploiting the operability of the LTEx module have been proposed to instantiate area-delay efficient B2G and G2B Converters which can be exclusively used in Gray Code Addressing schemes. Moreover this work formulates the QCA design metrics such as O-Cost, Effective area, Delay and Cost α for the n-bit converter layouts.

Oscillator circuits

CERN Document Server

Graf, Rudolf F

1996-01-01

This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing

Measuring circuits

CERN Document Server

Graf, Rudolf F

1996-01-01

This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings

Delay Estimator and Improved Proportionate Multi-Delay Adaptive Filtering Algorithm

Directory of Open Access Journals (Sweden)

E. Verteletskaya

2012-04-01

Full Text Available This paper pertains to speech and acoustic signal processing, and particularly to a determination of echo path delay and operation of echo cancellers. To cancel long echoes, the number of weights in a conventional adaptive filter must be large. The length of the adaptive filter will directly affect both the degree of accuracy and the convergence speed of the adaptation process. We present a new adaptive structure which is capable to deal with multiple dispersive echo paths. An adaptive filter according to the present invention includes means for storing an impulse response in a memory, the impulse response being indicative of the characteristics of a transmission line. It also includes a delay estimator for detecting ranges of samples within the impulse response having relatively large distribution of echo energy. These ranges of samples are being indicative of echoes on the transmission line. An adaptive filter has a plurality of weighted taps, each of the weighted taps having an associated tap weight value. A tap allocation/control circuit establishes the tap weight values in response to said detecting means so that only taps within the regions of relatively large distributions of echo energy are turned on. Thus, the convergence speed and the degree of estimation in the adaptation process can be improved.

How to induce multiple delays in coupled chaotic oscillators?

Energy Technology Data Exchange (ETDEWEB)

Bhowmick, Sourav K. [CSIR-Indian Institute of Chemical Biology, Jadavpur, Kolkata 700032 (India); Department of Electronics, Asutosh College, Kolkata 700026 (India); Ghosh, Dibakar [Physics and Applied Mathematics Unit, Indian Statistical Institute, Kolkata 700108 (India); Roy, Prodyot K. [Department of Physics, Presidency University, Kolkata 700073 (India); Kurths, Jürgen [Potsdam Institute for Climate Impact Research, 14473 Potsdam (Germany); Institute for Physics, Humboldt University, 12489 Berlin (Germany); Dana, Syamal K. [CSIR-Indian Institute of Chemical Biology, Jadavpur, Kolkata 700032 (India)

2013-12-15

Lag synchronization is a basic phenomenon in mismatched coupled systems, delay coupled systems, and time-delayed systems. It is characterized by a lag configuration that identifies a unique time shift between all pairs of similar state variables of the coupled systems. In this report, an attempt is made how to induce multiple lag configurations in coupled systems when different pairs of state variables attain different time shift. A design of coupling is presented to realize this multiple lag synchronization. Numerical illustration is given using examples of the Rössler system and the slow-fast Hindmarsh-Rose neuron model. The multiple lag scenario is physically realized in an electronic circuit of two Sprott systems.

Resonance circuits for adiabatic circuits

Directory of Open Access Journals (Sweden)

C. Schlachta

2003-01-01

Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

Multi-format all-optical processing based on a large-scale, hybridly integrated photonic circuit.

Science.gov (United States)

Bougioukos, M; Kouloumentas, Ch; Spyropoulou, M; Giannoulis, G; Kalavrouziotis, D; Maziotis, A; Bakopoulos, P; Harmon, R; Rogers, D; Harrison, J; Poustie, A; Maxwell, G; Avramopoulos, H

2011-06-06

We investigate through numerical studies and experiments the performance of a large scale, silica-on-silicon photonic integrated circuit for multi-format regeneration and wavelength-conversion. The circuit encompasses a monolithically integrated array of four SOAs inside two parallel Mach-Zehnder structures, four delay interferometers and a large number of silica waveguides and couplers. Exploiting phase-incoherent techniques, the circuit is capable of processing OOK signals at variable bit rates, DPSK signals at 22 or 44 Gb/s and DQPSK signals at 44 Gbaud. Simulation studies reveal the wavelength-conversion potential of the circuit with enhanced regenerative capabilities for OOK and DPSK modulation formats and acceptable quality degradation for DQPSK format. Regeneration of 22 Gb/s OOK signals with amplified spontaneous emission (ASE) noise and DPSK data signals degraded with amplitude, phase and ASE noise is experimentally validated demonstrating a power penalty improvement up to 1.5 dB.

A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

International Nuclear Information System (INIS)

Santos, D.M.; Dow, S.F.; Levi, M.E.

1995-12-01

Many high energy physics and nuclear science applications require sub-nanosecond time resolution measurements over many thousands of detector channels. Phase-locked loops have been employed in the past to obtain accurate time references for these measurements. An alternative solution, based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multi-channel, time to digital converter (TDC). Complex clock generation can be, achieved by taking symmetric taps off the delay elements. The two circuits, DLL and TDC, were implemented in a CMOS 1.2μm and 0.8μm technology, respectively. Test results show a timing jitter of less than 35 ps for the DLL circuit and better solution for the TDC circuit

Project Circuits in a Basic Electric Circuits Course

Science.gov (United States)

Becker, James P.; Plumb, Carolyn; Revia, Richard A.

2014-01-01

The use of project circuits (a photoplethysmograph circuit and a simple audio amplifier), introduced in a sophomore-level electric circuits course utilizing active learning and inquiry-based methods, is described. The development of the project circuits was initiated to promote enhanced engagement and deeper understanding of course content among…

Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

Science.gov (United States)

Shahrjerdi, Davood; Bedell, Stephen W

2013-01-09

In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

Science.gov (United States)

Russinoff, David M.

1995-01-01

We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

Delayed self-regulation and time-dependent chemical drive leads to novel states in epigenetic landscapes

Science.gov (United States)

Mitra, Mithun K.; Taylor, Paul R.; Hutchison, Chris J.; McLeish, T. C. B.; Chakrabarti, Buddhapriya

2014-01-01

The epigenetic pathway of a cell as it differentiates from a stem cell state to a mature lineage-committed one has been historically understood in terms of Waddington's landscape, consisting of hills and valleys. The smooth top and valley-strewn bottom of the hill represent their undifferentiated and differentiated states, respectively. Although mathematical ideas rooted in nonlinear dynamics and bifurcation theory have been used to quantify this picture, the importance of time delays arising from multistep chemical reactions or cellular shape transformations have been ignored so far. We argue that this feature is crucial in understanding cell differentiation and explore the role of time delay in a model of a single-gene regulatory circuit. We show that the interplay of time-dependent drive and delay introduces a new regime where the system shows sustained oscillations between the two admissible steady states. We interpret these results in the light of recent perplexing experiments on inducing the pluripotent state in mouse somatic cells. We also comment on how such an oscillatory state can provide a framework for understanding more general feedback circuits in cell development. PMID:25165605

Generation of optical vortices in an integrated optical circuit

Science.gov (United States)

Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

2017-09-01

In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = -1.

Design and performance analysis of delay insensitive multi-ring structures

DEFF Research Database (Denmark)

Sparsø, Jens; Staunstrup, Jørgen

1993-01-01

A set of simple design and performance analysis techniques that have been successfully used to design a number of nontrivial delay insensitive circuits is described. Examples are building blocks for digital filters and a vector multiplier using a serial-parallel multiply and accumulate algorithm....... The vector multiplier circuit has been laid out, submitted for fabrication and successfully tested. Throughout the analysis elements from this design are used to illustrate the design and performance analysis techniques. The design technique is based on a data flow approach using pipelines and rings...... that are composed into larger multiring structures by joining and forking of signals. By limiting to this class of structures, it is possible, even for complex designs, to analyze the performance and establish an understanding of the bottlenecks....

Organizing of delay, input gate and memory of proportional chamber channel basing on D-trigger

International Nuclear Information System (INIS)

Vladimirov, S.V.; Kuzichev, V.F.; Rabin, N.V.

1980-01-01

Economical organization of delay, input gate and proportional chamber (PC) channel memory on the 155 TM2 D trigger basis is described. The channel consists of an amplifier; delay element permitting to synchronize PC signal and recording strobe-signal; input gate, where coincidence of the above signals occurs; memory element, where the data from a wire are recorded and stored; read gate through which the data are transmitted for further processing. Presented is one of the versions of circuit solution for delay element, input gate and momory element. Flowsheet peculiarity is the simplicity of fabrication and tuning as well as low cost of the device

Wavy Channel TFT-Based Digital Circuits

KAUST Repository

Hanna, Amir

2016-02-23

We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.

Wavy Channel TFT-Based Digital Circuits

KAUST Repository

Hanna, Amir; Hussain, Aftab M.; Hussain, Aftab M.; Hussain, Aftab M.; Omran, Hesham; Alsharif, Sarah M.; Salama, Khaled N.; Hussain, Muhammad Mustafa

2016-01-01

We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.

An improved superconducting neural circuit and its application for a neural network solving a combinatorial optimization problem

International Nuclear Information System (INIS)

Onomi, T; Nakajima, K

2014-01-01

We have proposed a superconducting Hopfield-type neural network for solving the N-Queens problem which is one of combinatorial optimization problems. The sigmoid-shape function of a neuron output is represented by the output of coupled SQUIDs gate consisting of a single-junction and a double-junction SQUIDs. One of the important factors for an improvement of the network performance is an improvement of a threshold characteristic of a neuron circuit. In this paper, we report an improved design of coupled SQUID gates for a superconducting neural network. A step-like function with a steep threshold at a rising edge is desirable for a neuron circuit to solve a combinatorial optimization problem. A neuron circuit is composed of two coupled SQUIDs gates with a cascade connection in order to obtain such characteristics. The designed neuron circuit is fabricated by a 2.5 kA/cm 2 Nb/AlOx/Nb process. The operation of a fabricated neuron circuit is experimentally demonstrated. Moreover, we discuss about the performance of the neural network using the improved neuron circuits and delayed negative self-connections.

Inductive circuit arrangements

International Nuclear Information System (INIS)

Mansfield, Peter; Coxon, R.J.

1987-01-01

A switched coil arrangement is connected in a bridge configuration of four switches S 1 , S 2 , S 3 and S 4 which are each shunted by diodes D 1 , D 2 , D 3 and D 4 so that current can flow in either direction through a coil L depending on the setting of the switches. A capacitor C is connected across the bridge through a switch S 5 to receive the inductive energy stored in coil L on breaking the current flow path through the coil. The electrostatic energy stored in capacitor C can then be used to supply current through the coil in the reverse direction either immediately or after a time delay. Coil L may be a superconductive coil. Losses in the circuit can be made up by a trickle charge of capacitor C from a separate supply V 2 . The device may be used in nuclear magnetic resonance imaging. (author)

Ultra-low power integrated circuit design circuits, systems, and applications

CERN Document Server

Li, Dongmei; Wang, Zhihua

2014-01-01

This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

Spiking neuron devices consisting of single-flux-quantum circuits

International Nuclear Information System (INIS)

Hirose, Tetsuya; Asai, Tetsuya; Amemiya, Yoshihito

2006-01-01

Single-flux-quantum (SFQ) circuits can be used for making spiking neuron devices, which are useful elements for constructing intelligent, brain-like computers. The device we propose is based on the leaky integrate-and-fire neuron (IFN) model and uses a SFQ pulse as an action signal or a spike of neurons. The operation of the neuron device is confirmed by computer simulator. It can operate with a short delay of 100 ps or less and is the highest-speed neuron device ever reported

Memorizing circuit for long pulses; Circuit de memoire pour impulsions longues; Zapominayushchee ustrojstvo dlya dlitel'nykh impul'sov; Circuito memorizador para impulsos de larga duracion

Energy Technology Data Exchange (ETDEWEB)

Coli, M; Horn, G [Sorin Centro Ricerche Nucleari di Saluggia (Italy)

1962-04-15

The circuit allows unlimited memorization of a positive pulse of any shape, and retains both amplitude and width. Theoretically a rectangular pulse of amplitude A and width t produced as a single pulse when t = 0 can be reproduced in its own area after any time {tau}, so that it may be retained on an oscilloscope synchronized at a repetition frequency {approx_equal} 1/{tau}. The rise form of pulse is not memorized, so that the pulse rise and decay time retained by the oscilloscope are those inherent to the memorizing circuit. Basically the circuit may be considered as being formed by two stretching circuits. These transform the input width from t to t + {tau}. The lengthened pulses of opposite phases are added to obtain at the output a pulse of amplitude A and width t. The delay {tau} is controlled by two monostables triggered at an interval t (delay control circuit) by a saturated amplifier which squares the input and gives two pulses, through a differentiating circuit (delay-measuring circuit). The output pulse is fed back to the input through an attenuator and a delay line. The cycle is repeated with a repetition rate of {approx} l/{tau}. The memorized pulse has a width from 50 {mu}s to over 10 ms. The repetition rate may vary from 10{sup 4} Hz to 30 Hz and less. Another circuit, obtained by using the same principle, is described in the original paper. It can also memorize input pulse shape apart from the amplitude and width. (author) [French] Le circuit permet la memorisation illimitee d'une impulsion positive de n'importe quelle forme; il en conserve a la fois l'amplitude et la largeur. Theoriquement, une impulsion rectangulaire d'une amplitude A et d'une largeur t, produite sous forme d'impulsion unique a un temps t = 0, peut etre reproduite apres un temps {tau}, ce qui permet de la conserver sur un oscilloscope synchronise a une frequence de repetition {approx_equal} 1/{tau}. La forme de la montee de l'impulsion n'etant pas memorisee, les temps de montee et

Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits

International Nuclear Information System (INIS)

Nishigai, T.; Ito, M.; Yoshikawa, N.; Fujimaki, A.; Terai, H.; Yorozu, S.

2005-01-01

We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10 ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10 ps

Electronic circuit encyclopedia 2

Energy Technology Data Exchange (ETDEWEB)

Park, Sun Ho

1992-10-15

This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

Electronic circuit encyclopedia 2

International Nuclear Information System (INIS)

Park, Sun Ho

1992-10-01

This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

Solid-state circuits

CERN Document Server

Pridham, G J

2013-01-01

Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

Sistem Proteksi Arus Bocor Menggunakan Earth Leakage Circuit Breaker Berbasis Arduino

Directory of Open Access Journals (Sweden)

Syukriyadin Syukriyadin

2017-02-01

Full Text Available Touching a live part of electrical equipment either intentionally or unintentionally can cause an electric shock. The touch can occur directly or indirectly and results in the flow of electric current through the human body to the ground. This electric current is known as the leakage current and can have fatal effects on the human body such as burns, cramps, faint and death. This paper aims to design a prototype protection model of the earth leakage circuit breaker device based on Arduino (ELCBA to protect the human body from the electrical hazards. The performance of the ELCBA is investigated by detecting the earth leakage current to the grounding system (TN.  The prototype is designed and simulated by using Proteus software. Based on the response test carried out on the prototype, it can be concluded that the ELCBA can operate properly to disconnect the electric circuit if the leakage current is detected greater than or equal to 30 mA with a time delay of 15 ms and to reclose the circuit again after 5 minutes.

The design of infrared information collection circuit based on embedded technology

Science.gov (United States)

Liu, Haoting; Zhang, Yicong

2013-07-01

S3C2410 processor is a 16/32 bit RISC embedded processor which based on ARM920T core and AMNA bus, and mainly for handheld devices, and high cost, low-power applications. This design introduces a design plan of the PIR sensor system, circuit and its assembling, debugging. The Application Circuit of the passive PIR alarm uses the invisibility of the infrared radiation well into the alarm system, and in order to achieve the anti-theft alarm and security purposes. When the body goes into the range of PIR sensor detection, sensors will detect heat sources and then the sensor will output a weak signal. The Signal should be amplified, compared and delayed; finally light emitting diodes emit light, playing the role of a police alarm.

Collective of mechatronics circuit

International Nuclear Information System (INIS)

1987-02-01

This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

Collective of mechatronics circuit

Energy Technology Data Exchange (ETDEWEB)

NONE

1987-02-15

This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

OpenAIRE

石橋, 孝昭

2012-01-01

This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

Note: Large active area solid state photon counter with 20 ps timing resolution and 60 fs detection delay stability

Science.gov (United States)

Prochazka, Ivan; Kodet, Jan; Eckl, Johann; Blazej, Josef

2017-10-01

We are reporting on the design, construction, and performance of a photon counting detector system, which is based on single photon avalanche diode detector technology. This photon counting device has been optimized for very high timing resolution and stability of its detection delay. The foreseen application of this detector is laser ranging of space objects, laser time transfer ground to space and fundamental metrology. The single photon avalanche diode structure, manufactured on silicon using K14 technology, is used as a sensor. The active area of the sensor is circular with 200 μm diameter. Its photon detection probability exceeds 40% in the wavelength range spanning from 500 to 800 nm. The sensor is operated in active quenching and gating mode. A new control circuit was optimized to maintain high timing resolution and detection delay stability. In connection to this circuit, timing resolution of the detector is reaching 20 ps FWHM. In addition, the temperature change of the detection delay is as low as 70 fs/K. As a result, the detection delay stability of the device is exceptional: expressed in the form of time deviation, detection delay stability of better than 60 fs has been achieved. Considering the large active area aperture of the detector, this is, to our knowledge, the best timing performance reported for a solid state photon counting detector so far.

Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

Directory of Open Access Journals (Sweden)

Huei Chaeng Chin

2014-01-01

Full Text Available Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET for applications in ultralarge-scale integration (ULSI is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP and power-delay product (PDP of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (Id-Vd and Id-Vg, for subthreshold swing (SS, drain-induced barrier lowering (DIBL, and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.

Delayed Maturation of Fast-Spiking Interneurons Is Rectified by Activation of the TrkB Receptor in the Mouse Model of Fragile X Syndrome.

Science.gov (United States)

Nomura, Toshihiro; Musial, Timothy F; Marshall, John J; Zhu, Yiwen; Remmers, Christine L; Xu, Jian; Nicholson, Daniel A; Contractor, Anis

2017-11-22

Fragile X syndrome (FXS) is a neurodevelopmental disorder that is a leading cause of inherited intellectual disability, and the most common known cause of autism spectrum disorder. FXS is broadly characterized by sensory hypersensitivity and several developmental alterations in synaptic and circuit function have been uncovered in the sensory cortex of the mouse model of FXS ( Fmr1 KO). GABA-mediated neurotransmission and fast-spiking (FS) GABAergic interneurons are central to cortical circuit development in the neonate. Here we demonstrate that there is a delay in the maturation of the intrinsic properties of FS interneurons in the sensory cortex, and a deficit in the formation of excitatory synaptic inputs on to these neurons in neonatal Fmr1 KO mice. Both these delays in neuronal and synaptic maturation were rectified by chronic administration of a TrkB receptor agonist. These results demonstrate that the maturation of the GABAergic circuit in the sensory cortex is altered during a critical developmental period due in part to a perturbation in BDNF-TrkB signaling, and could contribute to the alterations in cortical development underlying the sensory pathophysiology of FXS. SIGNIFICANCE STATEMENT Fragile X (FXS) individuals have a range of sensory related phenotypes, and there is growing evidence of alterations in neuronal circuits in the sensory cortex of the mouse model of FXS ( Fmr1 KO). GABAergic interneurons are central to the correct formation of circuits during cortical critical periods. Here we demonstrate a delay in the maturation of the properties and synaptic connectivity of interneurons in Fmr1 KO mice during a critical period of cortical development. The delays both in cellular and synaptic maturation were rectified by administration of a TrkB receptor agonist, suggesting reduced BDNF-TrkB signaling as a contributing factor. These results provide evidence that the function of fast-spiking interneurons is disrupted due to a deficiency in neurotrophin

Cycles of self-pulsations in a photonic integrated circuit.

Science.gov (United States)

Karsaklian Dal Bosco, Andreas; Kanno, Kazutaka; Uchida, Atsushi; Sciamanna, Marc; Harayama, Takahisa; Yoshimura, Kazuyuki

2015-12-01

We report experimentally on the bifurcation cascade leading to the appearance of self-pulsation in a photonic integrated circuit in which a laser diode is subjected to delayed optical feedback. We study the evolution of the self-pulsing frequency with the increase of both the feedback strength and the injection current. Experimental observations show good qualitative accordance with numerical results carried out with the Lang-Kobayashi rate equation model. We explain the mechanism underlying the self-pulsations by a phenomenon of beating between successive pairs of external cavity modes and antimodes.

Color Coding of Circuit Quantities in Introductory Circuit Analysis Instruction

Science.gov (United States)

Reisslein, Jana; Johnson, Amy M.; Reisslein, Martin

2015-01-01

Learning the analysis of electrical circuits represented by circuit diagrams is often challenging for novice students. An open research question in electrical circuit analysis instruction is whether color coding of the mathematical symbols (variables) that denote electrical quantities can improve circuit analysis learning. The present study…

An analysis of periodic solutions of bi-directional associative memory networks with time-varying delays

International Nuclear Information System (INIS)

Cao Jinde; Jiang Qiuhao

2004-01-01

In this Letter, several sufficient conditions are derived for the existence and uniqueness of periodic oscillatory solution for bi-directional associative memory (BAM) networks with time-varying delays by employing a new Lyapunov functional and an elementary inequality, and all other solutions of the BAM networks converge exponentially to the unique periodic solution. These criteria are presented in terms of system parameters and have important leading significance in the design and applications of periodic neural circuits for delayed BAM. As an illustration, two numerical examples are worked out using the results obtained

Design of an improved RCD buffer circuit for full bridge circuit

Science.gov (United States)

Yang, Wenyan; Wei, Xueye; Du, Yongbo; Hu, Liang; Zhang, Liwei; Zhang, Ou

2017-05-01

In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubber circuit with the improved RCD snubber circuit. By comparing and analyzing, it is proved that the improved buffer circuit can absorb surge voltage. Finally, experiments are demonstrated to validate that the correctness of the RC formula and the improved RCD snubber circuit.

Analog circuit design designing dynamic circuit response

CERN Document Server

Feucht, Dennis

2010-01-01

This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

Science.gov (United States)

Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

2013-09-01

A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

Four-deep charge-time and pulse-width scaling discriminator for delay line MWPC's

International Nuclear Information System (INIS)

Lee, K.L.; Kirsten, F.A.; Grigorian, A.; Guiragossian, Z.G.T.

1976-01-01

A discriminator has been developed for digitizing both intercepted total charge and location of electromagnetic shower and particle trajectories in multi-wire proportional chambers read by delay lines. Determination of shower trajectory is aided by video signal integration followed by centroid-locating discrimination. Calibrated run-down of the signal integrating capacitor gives the charge information above a given threshold level. The discriminator is designed to handle up to four shower-induced video signals per event by incorporating steering circuits within the module. Each video signal is examined for time over an adjustable threshold. Video pulses with separation of less than 20 nsec are treated as a single pulse. Counter-logic circuits indicate the number of video signals digitized. These signal processing circuits provide a first level of data sifting which otherwise must be carried out with additional discriminator channels and added complexity in data recognition

Development of ball surface acoustic wave trace moisture analyzer using burst waveform undersampling circuit

Science.gov (United States)

Tsuji, Toshihiro; Oizumi, Toru; Fukushi, Hideyuki; Takeda, Nobuo; Akao, Shingo; Tsukahara, Yusuke; Yamanaka, Kazushi

2018-05-01

The measurement and control of trace moisture, where the water concentration is lower than 1 ppmv [-76.2 °C for the frost point (°CFP)], are essential for improving the yield rate of semiconductor devices and for ensuring their reliability. A ball surface acoustic wave (SAW) sensor with a sol-gel silica coating exhibited useful characteristics for a trace moisture analyzer (TMA) when the temperature drift of the delay time output was precisely compensated using two-frequency measurement (TFM), where the temperature-compensated relative delay time change (RDTC) was obtained by subtracting the RDTC at the fundamental frequency from that at the third harmonic frequency on an identical propagation path. However, the cost of the measurement circuit was a problem. In this study, a burst waveform undersampling (BUS) circuit based on the theory of undersampling measurement was developed as a practical means. The BUS circuit was useful for precise temperature compensation of the RDTC, and the ball SAW TMA was prototyped by calibrating the RDTC using a TMA based on cavity ring-down spectroscopy (CRDS), which is the most reliable method for trace moisture measurement. The ball SAW TMA outputted a similar concentration to that obtained by the CRDS TMA, and its response time at a set concentration in N2 with a flow rate of 1 l/min was about half that of the CRDS TMA, suggesting that moisture of -80 °CFP was measured within only 1 min. The detection limit at a signal-to-noise ratio of 3 was estimated to be 0.05 ppbv, comparable with that of the CRDS TMA. From these results, it was demonstrated that a practical ball SAW TMA can be realized using the developed BUS circuit.

MOS Current Mode Logic Near Threshold Circuits

Directory of Open Access Journals (Sweden)

Alexander Shapiro

2014-06-01

Full Text Available Near threshold circuits (NTC are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.

Pulse advancement and delay in an integrated optical two-port ring-resonator circuit: direct experimental observations

NARCIS (Netherlands)

Uranus, H.P.; Zhuang, L.; Roeloffzen, C.G.H.; Hoekstra, Hugo

We report experimental observations of the negative-group-velocity (v_g) phenomenon in an integrated-optical two-port ring-resonator circuit. We demonstrate that when the v_g is negative, the (main) peak of output pulse appears earlier than the peak of a reference pulse, while for a positive v_g,

Multi-channel control circuit for real-time control of events in Aditya tokamak

Energy Technology Data Exchange (ETDEWEB)

Edappala, Praveenlal, E-mail: praveen@ipr.res.in; Shah, Minsha; Rajpal, Rachana; Tanna, R.L.; Ghosh, Joydeep; Chattopadhyay, P.K.; Jha, R.

2016-11-15

Highlights: • Low cost microcontroller based control circuit. • The control hardware can be programmed/configured very easily for different applications. • Microcontroller programming is done in assembly language so that precise timing can be achieved with micro seconds resolution. • Successful implementation of this circuit in noisy tokamak environment. • Efficient noise and burst elimination. • Can be integrated in to the other subsystems. • Low cost solution for implementing feedback control in small and medium size tokamaks and other experiments requiring feedback control. - Abstract: Tokamak plasma is prone to many random events having potential for causing severe damages to the machine, such as disruptions, production and elimination of high-energy runaway electrons etc. These events can be mitigated by obtaining pre-cursor signal leading to these events and then taking proper measures just before their onset to avoid their happenings, like disruptions can be mitigated by massive gas injection or putting a bias voltage on an electrode placed inside the plasma, the runaways can be mitigated by gas injection and by applying specific magnetic fields. Hence for real time control of these events, the pre-cursors should be electronically recorded and the mitigation techniques should be initiated by sending triggers to their individual operational systems. To implement these methodologies of real-time controlling of events in Aditya Tokamak, a low cost multi-channel Micro-Controller based timing circuit is designed and developed in-house. This circuit first compares the precursor signals fed into it with the pre-set values and gives a trigger output whenever the signals overshoot the pre-set values. The circuit readies itself for operation along with start of the tokamak discharge and waits up to an initial pre-determined delay and then initiates a trigger at the time of overshooting of precursor signal. The circuit is fully integrated and assembled in

Scaling of graphene integrated circuits.

Science.gov (United States)

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

A low-jitter RF PLL frequency synthesizer with high-speed mixed-signal down-scaling circuits

International Nuclear Information System (INIS)

Tang Lu; Wang Zhigong; Xue Hong; He Xiaohu; Xu Yong; Sun Ling

2010-01-01

A low-jitter RF phase locked loop (PLL) frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed. Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL. An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit. Through integrating the D-latch with 'OR' logic for dual-modulus operation, the delays associated with both the 'OR' and D-flip-flop (DFF) operations are reduced, and the complexity of the circuit is also decreased. The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model. The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system. The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process. The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz. The circuit exhibits a low RMS jitter of 3.3 ps. The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply. (semiconductor integrated circuits)

A novel integrated circuit for semiconductor radiation detectors with sparse readout

International Nuclear Information System (INIS)

Zhang Yacong; Chen Zhognjian; Lu Wengao; Zhao Baoying; Ji Lijiu

2008-01-01

A novel fully integrated CMOS readout circuit for semiconductor radiation detector with sparse readout is presented. The new sparse scheme is: when one channel is being read out, the trigger signal from other channels is delayed and then processed. Therefore, the dead time is reduced and so is the error rate. Besides sparse readout, sequential readout is also allowed, which means the analog voltages and addresses of all the channels are read out sequentially once there is a channel triggered. The circuit comprises Charge Sensitive Amplifier (CSA), pulse shaper, peak detect and hold circuit, and digital logic. A test chip of four channels designed in a 0.5 μ DPTM CMOS technology has been taped out. The results of post simulation indicate that the gain is 79.3 mV/fC with a linearity of 99.92%. The power dissipation is 4 mW per channel. Theory analysis and calculation shows that the error probability is approximately 2.5%, which means a reduction of about 37% is obtained compared with the traditional scanning scheme, assuming a 16-channel system with a particle rate of 100 k/s per channel. (authors)

Mutations in KPTN Cause Macrocephaly, Neurodevelopmental Delay, and Seizures

Science.gov (United States)

Baple, Emma L.; Maroofian, Reza; Chioza, Barry A.; Izadi, Maryam; Cross, Harold E.; Al-Turki, Saeed; Barwick, Katy; Skrzypiec, Anna; Pawlak, Robert; Wagner, Karin; Coblentz, Roselyn; Zainy, Tala; Patton, Michael A.; Mansour, Sahar; Rich, Phillip; Qualmann, Britta; Hurles, Matt E.; Kessels, Michael M.; Crosby, Andrew H.

2014-01-01

The proper development of neuronal circuits during neuromorphogenesis and neuronal-network formation is critically dependent on a coordinated and intricate series of molecular and cellular cues and responses. Although the cortical actin cytoskeleton is known to play a key role in neuromorphogenesis, relatively little is known about the specific molecules important for this process. Using linkage analysis and whole-exome sequencing on samples from families from the Amish community of Ohio, we have demonstrated that mutations in KPTN, encoding kaptin, cause a syndrome typified by macrocephaly, neurodevelopmental delay, and seizures. Our immunofluorescence analyses in primary neuronal cell cultures showed that endogenous and GFP-tagged kaptin associates with dynamic actin cytoskeletal structures and that this association is lost upon introduction of the identified mutations. Taken together, our studies have identified kaptin alterations responsible for macrocephaly and neurodevelopmental delay and define kaptin as a molecule crucial for normal human neuromorphogenesis. PMID:24239382

Circuit analysis for dummies

CERN Document Server

Santiago, John

2013-01-01

Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help

Current limiter circuit system

Science.gov (United States)

Witcher, Joseph Brandon; Bredemann, Michael V.

2017-09-05

An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

The voltage—current relationship and equivalent circuit implementation of parallel flux-controlled memristive circuits

International Nuclear Information System (INIS)

Bao Bo-Cheng; Feng Fei; Dong Wei; Pan Sai-Hu

2013-01-01

A flux-controlled memristor characterized by smooth cubic nonlinearity is taken as an example, upon which the voltage—current relationships (VCRs) between two parallel memristive circuits — a parallel memristor and capacitor circuit (the parallel MC circuit), and a parallel memristor and inductor circuit (the parallel ML circuit) — are investigated. The results indicate that the VCR between these two parallel memristive circuits is closely related to the circuit parameters, and the frequency and amplitude of the sinusoidal voltage stimulus. An equivalent circuit model of the memristor is built, upon which the circuit simulations and experimental measurements of both the parallel MC circuit and the parallel ML circuit are performed, and the results verify the theoretical analysis results

Subwavelength grating enabled on-chip ultra-compact optical true time delay line.

Science.gov (United States)

Wang, Junjia; Ashrafi, Reza; Adams, Rhys; Glesk, Ivan; Gasulla, Ivana; Capmany, José; Chen, Lawrence R

2016-07-26

An optical true time delay line (OTTDL) is a basic photonic building block that enables many microwave photonic and optical processing operations. The conventional design for an integrated OTTDL that is based on spatial diversity uses a length-variable waveguide array to create the optical time delays, which can introduce complexities in the integrated circuit design. Here we report the first ever demonstration of an integrated index-variable OTTDL that exploits spatial diversity in an equal length waveguide array. The approach uses subwavelength grating waveguides in silicon-on-insulator (SOI), which enables the realization of OTTDLs having a simple geometry and that occupy a compact chip area. Moreover, compared to conventional wavelength-variable delay lines with a few THz operation bandwidth, our index-variable OTTDL has an extremely broad operation bandwidth practically exceeding several tens of THz, which supports operation for various input optical signals with broad ranges of central wavelength and bandwidth.

Structure of the EGF receptor transactivation circuit integrates multiple signals with cell context

Energy Technology Data Exchange (ETDEWEB)

Joslin, Elizabeth J.; Shankaran, Harish; Opresko, Lee K.; Bollinger, Nikki; Lauffenburger, Douglas A.; Wiley, H. S.

2010-05-10

Transactivation of the epidermal growth factor receptor (EGFR) has been proposed to be a mechanism by which a variety of cellular inputs can be integrated into a single signaling pathway, but the regulatory topology of this important system is unclear. To understand the transactivation circuit, we first created a “non-binding” reporter for ligand shedding. We then quantitatively defined how signals from multiple agonists were integrated both upstream and downstream of the EGFR into the extracellular signal regulated kinase (ERK) cascade in human mammary epithelial cells. We found that transactivation is mediated by a recursive autocrine circuit where ligand shedding drives EGFR-stimulated ERK that in turn drives further ligand shedding. The time from shedding to ERK activation is fast (<5 min) whereas the recursive feedback is slow (>15 min). Simulations showed that this delay in positive feedback greatly enhanced system stability and robustness. Our results indicate that the transactivation circuit is constructed so that the magnitude of ERK signaling is governed by the sum of multiple direct inputs, while recursive, autocrine ligand shedding controls signal duration.

State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

Science.gov (United States)

Breuer, M. A.; Carlan, A. J.

1982-10-01

Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

30 CFR 75.518 - Electric equipment and circuits; overload and short circuit protection.

Science.gov (United States)

2010-07-01

... short circuit protection. 75.518 Section 75.518 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... Equipment-General § 75.518 Electric equipment and circuits; overload and short circuit protection... installed so as to protect all electric equipment and circuits against short circuit and overloads. Three...

Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS

Directory of Open Access Journals (Sweden)

David Bol

2011-01-01

Full Text Available Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.

30 CFR 77.506 - Electric equipment and circuits; overload and short-circuit protection.

Science.gov (United States)

2010-07-01

... short-circuit protection. 77.506 Section 77.506 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... circuits; overload and short-circuit protection. Automatic circuit-breaking devices or fuses of the correct type and capacity shall be installed so as to protect all electric equipment and circuits against short...

Power ion beam production in a magnetic-insulated diode placed in a circuit with an inductive storage with a plasmoerosion circuit breaker

International Nuclear Information System (INIS)

Anan'in, P.S.; Karpov, V.B.; Krasik, Ya.E.; Paul', E.A.

1991-01-01

Consideration is given to results of experimental studies of modes of operation of plasma current breaker and magnetic insulated diode, placed parallel in a circuit with inductive storage and microsecond generator, as well as parameters of high-power ion beam, generated in gas-filled diode. Magnetic field of mirror configuration, which enabled to locate the gas-filled diode dose to breaking region was used for decrease of electrodynamic plasma transfer. It is shown that time delay (of the order of ten and more) of power maximum in gas-filled diode with respect to power maximum in plasma breaker is observed when using passive plasma source on anode

Volumetric and chemical control auxiliary circuit for a PWR primary circuit

International Nuclear Information System (INIS)

Costes, D.

1990-01-01

The volumetric and chemical control circuit has an expansion tank with at least one water-steam chamber connected to the primary circuit by a sampling pipe and a reinjection pipe. The sampling pipe feeds jet pumps controlled by valves. An action on these valves and pumps regulates the volume of the water in the primary circuit. A safety pipe controlled by a flap automatically injects water from the chamber into the primary circuit in case of ruptures. The auxiliary circuit has also systems for purifying the water and controlling the boric acid and hydrogen content [fr

Stability Analysis of Nonlinear Time–Delayed Systems with Application to Biological Models

Directory of Open Access Journals (Sweden)

Kruthika H.A.

2017-03-01

Full Text Available In this paper, we analyse the local stability of a gene-regulatory network and immunotherapy for cancer modelled as nonlinear time-delay systems. A numerically generated kernel, using the sum-of-squares decomposition of multivariate polynomials, is used in the construction of an appropriate Lyapunov–Krasovskii functional for stability analysis of the networks around an equilibrium point. This analysis translates to verifying equivalent LMI conditions. A delay-independent asymptotic stability of a second-order model of a gene regulatory network, taking into consideration multiple commensurate delays, is established. In the case of cancer immunotherapy, a predator–prey type model is adopted to describe the dynamics with cancer cells and immune cells contributing to the predator–prey population, respectively. A delay-dependent asymptotic stability of the cancer-free equilibrium point is proved. Apart from the system and control point of view, in the case of gene-regulatory networks such stability analysis of dynamics aids mimicking gene networks synthetically using integrated circuits like neurochips learnt from biological neural networks, and in the case of cancer immunotherapy it helps determine the long-term outcome of therapy and thus aids oncologists in deciding upon the right approach.

Intuitive analog circuit design

CERN Document Server

Thompson, Marc

2013-01-01

Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi

The circuit designer's companion

CERN Document Server

Williams, Tim

1991-01-01

The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1972-01-01

Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of

Monitoring Sodium Circuits and ACSR cables using Fiber Optic Sensors

International Nuclear Information System (INIS)

Kasinathan, M.; Sosamma, S.; Babu-Rao, C.; Kumar, Anish; Purna-Chandra-Rao, B.; Murali, N; Jayakumar, T.

2013-06-01

Raman Distributed Temperature Sensors (RDTS) are attractive for the monitoring of coolant loop systems in nuclear power plants and monitoring of overhead power transmission lines. This paper discusses deployment of RDTS on double walled pipelines of primary sodium circuits in Fast Breeder Reactors (FBR). It is demonstrated as a proof-of-concept on a test loop with water as the leaking medium. Path delay multiplexing is adopted to improve the spatial resolution from 1.02 m to 0.5 m. A second application focuses on the influence of environmental factors on the detectability of defects in the ACSR cables using RDTS. (authors)

Signal sampling circuit

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2011-01-01

A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

Signal sampling circuit

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2010-01-01

A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

Electric circuits essentials

CERN Document Server

REA, Editors of

2012-01-01

REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph

Approximate circuits for increased reliability

Science.gov (United States)

Hamlet, Jason R.; Mayo, Jackson R.

2015-08-18

Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

Two-phase flow in the cooling circuit of a cryogenic rocket engine

Science.gov (United States)

Preclik, D.

1992-07-01

Transient two-phase flow was investigated for the hydrogen cooling circuit of the HM7 rocket engine. The nuclear reactor code ATHLET/THESEUS was adapted to cryogenics and applied to both principal and prototype experiments for validation and simulation purposes. The cooling circuit two-phase flow simulation focused on the hydrogen prechilling and pump transient phase prior to ignition. Both a single- and a multichannel model were designed and employed for a valve leakage flow, a nominal prechilling flow, and a prechilling with a subsequent pump-transient flow. The latter case was performed in order to evaluate the difference between a nominal and a delayed turbo-pump start-up. It was found that an extension of the nominal prechilling sequence in the order of 1 second is sufficient to finally provide for liquid injection conditions of hydrogen which, as commonly known, is undesirable for smooth ignition and engine starting transients.

Short-circuit logic

NARCIS (Netherlands)

Bergstra, J.A.; Ponse, A.

2010-01-01

Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of

Delayed Dopamine Signaling of Energy Level Builds Appetitive Long-Term Memory in Drosophila

Directory of Open Access Journals (Sweden)

Pierre-Yves Musso

2015-02-01

Full Text Available Sensory cues relevant to a food source, such as odors, can be associated with post-ingestion signals related either to food energetic value or toxicity. Despite numerous behavioral studies, a global understanding of the mechanisms underlying these long delay associations remains out of reach. Here, we demonstrate in Drosophila that the long-term association between an odor and a nutritious sugar depends on delayed post-ingestion signaling of energy level. We show at the neural circuit level that the activity of two pairs of dopaminergic neurons is necessary and sufficient to signal energy level to the olfactory memory center. Accordingly, we have identified in these dopaminergic neurons a delayed calcium trace that correlates with appetitive long-term memory formation. Altogether, these findings demonstrate that the Drosophila brain remembers food quality through a two-step mechanism that consists of the integration of olfactory and gustatory sensory information and then post-ingestion energetic value.

Delayed dopamine signaling of energy level builds appetitive long-term memory in Drosophila.

Science.gov (United States)

Musso, Pierre-Yves; Tchenio, Paul; Preat, Thomas

2015-02-24

Sensory cues relevant to a food source, such as odors, can be associated with post-ingestion signals related either to food energetic value or toxicity. Despite numerous behavioral studies, a global understanding of the mechanisms underlying these long delay associations remains out of reach. Here, we demonstrate in Drosophila that the long-term association between an odor and a nutritious sugar depends on delayed post-ingestion signaling of energy level. We show at the neural circuit level that the activity of two pairs of dopaminergic neurons is necessary and sufficient to signal energy level to the olfactory memory center. Accordingly, we have identified in these dopaminergic neurons a delayed calcium trace that correlates with appetitive long-term memory formation. Altogether, these findings demonstrate that the Drosophila brain remembers food quality through a two-step mechanism that consists of the integration of olfactory and gustatory sensory information and then post-ingestion energetic value. Copyright © 2015 The Authors. Published by Elsevier Inc. All rights reserved.

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Science.gov (United States)

Gupta, Neha; Parihar, Priyanka; Neema, Vaibhav

2018-04-01

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DECODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.

Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

International Nuclear Information System (INIS)

Holland, S.

1991-11-01

A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers are used in the process. The NMOS device is formed in a retrograde well while the PMOS device is fabricated directly in the high-resistivity silicon. Isolation characteristics are similar to a standard foundary CMOS process. Circuit performance using 3 μm design rules has been evaluated. The measured propagation delay and power-delay product for a 51-stage ring oscillator was 1.5 ns and 43 fJ, respectively. Measurements on a simple cascode amplifier results in a gain-bandwidth product of 200 MHz at a bias current of 15 μA. The input-referred noise of the cascode amplifier is 20 nV/√Hz at 1 MHz

Multi-channel logical circuit module used for high-speed, low amplitude signals processing and QDC gate signals generation

International Nuclear Information System (INIS)

Su Hong; Li Xiaogang; Zhu Haidong; Ma Xiaoli; Yin Weiwei; Li Zhuyu; Jin Genming; Wu Heyu

2001-01-01

A new kind of logical circuit will be introduced in brief. There are 16 independent channels in the module. The module receives low amplitude signals(≥40 mV), and processes them to amplify, shape, delay, sum and etc. After the processing each channel produces 2 pairs of ECL logical signal to feed the gate of QDC as the gate signal of QDC. The module consists of high-speed preamplifier unit, high-speed discriminate unit, delaying and shaping unit, summing unit and trigger display unit. The module is developed for 64 CH. 12 BIT Multi-event QDC. The impedance of QDC is 110 Ω. Each gate signal of QDC requires a pair of differential ECL level, Min. Gate width 30 ns and Max. Gate width 1 μs. It has showed that the outputs of logical circuit module satisfy the QDC requirements in experiment. The module can be used on data acquisition system to acquire thousands of data at high-speed ,high-density and multi-parameter, in heavy particle nuclear physics experiment. It also can be used to discriminate multi-coincidence events

Load testing circuit

DEFF Research Database (Denmark)

2009-01-01

A load testing circuit a circuit tests the load impedance of a load connected to an amplifier. The load impedance includes a first terminal and a second terminal, the load testing circuit comprising a signal generator providing a test signal of a defined bandwidth to the first terminal of the load...

Timergenerator circuits manual

CERN Document Server

Marston, R M

2013-01-01

Timer/Generator Circuits Manual is an 11-chapter text that deals mainly with waveform generator techniques and circuits. Each chapter starts with an explanation of the basic principles of its subject followed by a wide range of practical circuit designs. This work presents a total of over 300 practical circuits, diagrams, and tables.Chapter 1 outlines the basic principles and the different types of generator. Chapters 2 to 9 deal with a specific type of waveform generator, including sine, square, triangular, sawtooth, and special waveform generators pulse. These chapters also include pulse gen

CMOS circuits manual

CERN Document Server

Marston, R M

1995-01-01

CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

Design of arithmetic circuits in quantum dot cellular automata nanotechnology

CERN Document Server

Sridharan, K

2015-01-01

This research monograph focuses on the design of arithmetic circuits in Quantum Dot Cellular Automata (QCA). Using the fact that the 3-input majority gate is a primitive in QCA, the book sets out to discover hitherto unknown properties of majority logic in the context of arithmetic circuit designs. The pursuit for efficient adders in QCA takes two forms. One involves application of the new results in majority logic to existing adders. The second involves development of a custom adder for QCA technology. A QCA adder named as hybrid adder is proposed and it is shown that it outperforms existing multi-bit adders with respect to area and delay. The work is extended to the design of a low-complexity multiplier for signed numbers in QCA. Furthermore the book explores two aspects unique to QCA technology, namely thermal robustness and the role of interconnects. In addition, the book introduces the reader to QCA layout design and simulation using QCADesigner. Features & Benefits: This research-based book: ·  �...

30 CFR 75.601-1 - Short circuit protection; ratings and settings of circuit breakers.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Short circuit protection; ratings and settings... Trailing Cables § 75.601-1 Short circuit protection; ratings and settings of circuit breakers. Circuit breakers providing short circuit protection for trailing cables shall be set so as not to exceed the...

Computational modeling of stuttering caused by impairments in a basal ganglia thalamo-cortical circuit involved in syllable selection and initiation

Science.gov (United States)

Civier, Oren; Bullock, Daniel; Max, Ludo; Guenther, Frank H.

2013-01-01

A typical white-matter integrity and elevated dopamine levels have been reported for individuals who stutter. We investigated how such abnormalities may lead to speech dysfluencies due to their effects on a syllable-sequencing circuit that consists of basal ganglia (BG), thalamus, and left ventral premotor cortex (vPMC). “Neurally impaired” versions of the neurocomputational speech production model GODIVA were utilized to test two hypotheses: (1) that white-matter abnormalities disturb the circuit via corticostriatal projections carrying copies of executed motor commands, and (2) that dopaminergic abnormalities disturb the circuit via the striatum. Simulation results support both hypotheses: in both scenarios, the neural abnormalities delay readout of the next syllable’s motor program, leading to dysfluency. The results also account for brain imaging findings during dysfluent speech. It is concluded that each of the two abnormality types can cause stuttering moments, probably by affecting the same BG-thalamus-vPMC circuit. PMID:23872286

Embedding the dynamics of a single delay system into a feed-forward ring.

Science.gov (United States)

Klinshov, Vladimir; Shchapin, Dmitry; Yanchuk, Serhiy; Wolfrum, Matthias; D'Huys, Otti; Nekorkin, Vladimir

2017-10-01

We investigate the relation between the dynamics of a single oscillator with delayed self-feedback and a feed-forward ring of such oscillators, where each unit is coupled to its next neighbor in the same way as in the self-feedback case. We show that periodic solutions of the delayed oscillator give rise to families of rotating waves with different wave numbers in the corresponding ring. In particular, if for the single oscillator the periodic solution is resonant to the delay, it can be embedded into a ring with instantaneous couplings. We discover several cases where the stability of a periodic solution for the single unit can be related to the stability of the corresponding rotating wave in the ring. As a specific example, we demonstrate how the complex bifurcation scenario of simultaneously emerging multijittering solutions can be transferred from a single oscillator with delayed pulse feedback to multijittering rotating waves in a sufficiently large ring of oscillators with instantaneous pulse coupling. Finally, we present an experimental realization of this dynamical phenomenon in a system of coupled electronic circuits of FitzHugh-Nagumo type.

Multi-objective optimization of MOSFETs channel widths and supply voltage in the proposed dual edge-triggered static D flip-flop with minimum average power and delay by using fuzzy non-dominated sorting genetic algorithm-II.

Science.gov (United States)

Keivanian, Farshid; Mehrshad, Nasser; Bijari, Abolfazl

2016-01-01

D Flip-Flop as a digital circuit can be used as a timing element in many sophisticated circuits. Therefore the optimum performance with the lowest power consumption and acceptable delay time will be critical issue in electronics circuits. The newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is defined as a multi-objective optimization problem. For this, an optimum fuzzy inference system with fuzzy rules is proposed to enhance the performance and convergence of non-dominated sorting Genetic Algorithm-II by adaptive control of the exploration and exploitation parameters. By using proposed Fuzzy NSGA-II algorithm, the more optimum values for MOSFET channel widths and power supply are discovered in search space than ordinary NSGA types. What is more, the design parameters involving NMOS and PMOS channel widths and power supply voltage and the performance parameters including average power consumption and propagation delay time are linked. To do this, the required mathematical backgrounds are presented in this study. The optimum values for the design parameters of MOSFETs channel widths and power supply are discovered. Based on them the power delay product quantity (PDP) is 6.32 PJ at 125 MHz Clock Frequency, L = 0.18 µm, and T = 27 °C.

Sequential circuit design for radiation hardened multiple voltage integrated circuits

Science.gov (United States)

Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

2009-11-24

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Low latency asynchronous interface circuits

Science.gov (United States)

Sadowski, Greg

2017-06-20

In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

Piezoelectric drive circuit

Science.gov (United States)

Treu, C.A. Jr.

1999-08-31

A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

A Simple Snap Oscillator with Coexisting Attractors, Its Time-Delayed Form, Physical Realization, and Communication Designs

Science.gov (United States)

Rajagopal, Karthikeyan; Jafari, Sajad; Akgul, Akif; Karthikeyan, Anitha; Çiçek, Serdar; Shekofteh, Yasser

2018-05-01

In this paper, we report a novel chaotic snap oscillator with one nonlinear function. Dynamic analysis of the system shows the existence of bistability. To study the time delay effects on the proposed snap oscillator, we introduce multiple time delay in the fourth state equation. Investigation of dynamical properties of the time-delayed system shows that the snap oscillator exhibits the same multistable properties as the nondelayed system. The new multistable hyperjerk chaotic system has been tested in chaos shift keying and symmetric choc shift keying modulated communication designs for engineering applications. It has been determined that the symmetric chaos shift keying modulated communication system implemented with the new chaotic system is more successful than the chaos shift keying modulation for secure communication. Also, circuit implementation of the chaotic snap oscillator with tangent function is carried out showing its feasibility.

Feedback in analog circuits

CERN Document Server

Ochoa, Agustin

2016-01-01

This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...

Fine Output Voltage Control Method considering Time-Delay of Digital Inverter System for X-ray Computed Tomography

Science.gov (United States)

Shibata, Junji; Kaneko, Kazuhide; Ohishi, Kiyoshi; Ando, Itaru; Ogawa, Mina; Takano, Hiroshi

This paper proposes a new output voltage control for an inverter system, which has time-delay and nonlinear load. In the next generation X-ray computed tomography of a medical device (X-ray CT) that uses the contactless power transfer method, the feedback signal often contains time-delay due to AD/DA conversion and error detection/correction time. When the PID controller of the inverter system is received the adverse effects of the time-delay, the controller often has an overshoot and a oscillated response. In order to overcome this problem, this paper proposes a compensation method based on the Smith predictor for an inverter system having a time-delay and the nonlinear loads which are the diode bridge rectifier and X-ray tube. The proposed compensation method consists of the hybrid Smith predictor system based on an equivalent analog circuit and DSP. The experimental results confirm the validity of the proposed system.

Analog circuits cookbook

CERN Document Server

Hickman, Ian

2013-01-01

Analog Circuits Cookbook presents articles about advanced circuit techniques, components and concepts, useful IC for analog signal processing in the audio range, direct digital synthesis, and ingenious video op-amp. The book also includes articles about amplitude measurements on RF signals, linear optical imager, power supplies and devices, and RF circuits and techniques. Professionals and students of electrical engineering will find the book informative and useful.

Electric circuits and signals

CERN Document Server

Sabah, Nassir H

2007-01-01

Circuit Variables and Elements Overview Learning Objectives Electric Current Voltage Electric Power and Energy Assigned Positive Directions Active and Passive Circuit Elements Voltage and Current Sources The Resistor The Capacitor The Inductor Concluding Remarks Summary of Main Concepts and Results Learning Outcomes Supplementary Topics on CD Problems and Exercises Basic Circuit Connections and Laws Overview Learning Objectives Circuit Terminology Kirchhoff's Laws Voltage Division and Series Connection of Resistors Current Division and Parallel Connection of Resistors D-Y Transformation Source Equivalence and Transformation Reduced-Voltage Supply Summary of Main Concepts and Results Learning Outcomes Supplementary Topics and Examples on CD Problems and Exercises Basic Analysis of Resistive Circuits Overview Learning Objectives Number of Independent Circuit Equations Node-Voltage Analysis Special Considerations in Node-Voltage Analysis Mesh-Current Analysis Special Conside...

[Shunt and short circuit].

Science.gov (United States)

Rangel-Abundis, Alberto

2006-01-01

Shunt and short circuit are antonyms. In French, the term shunt has been adopted to denote the alternative pathway of blood flow. However, in French, as well as in Spanish, the word short circuit (court-circuit and cortocircuito) is synonymous with shunt, giving rise to a linguistic and scientific inconsistency. Scientific because shunt and short circuit made reference to a phenomenon that occurs in the field of the physics. Because shunt and short circuit are antonyms, it is necessary to clarify that shunt is an alternative pathway of flow from a net of high resistance to a net of low resistance, maintaining the stream. Short circuit is the interruption of the flow, because a high resistance impeaches the flood. This concept is applied to electrical and cardiovascular physiology, as well as to the metabolic pathways.

Macromodels of digital integrated circuits for program packages of circuit engineering design

Science.gov (United States)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

Circuit arrangement of an electronic component for the design of fail-safe protective circuits

International Nuclear Information System (INIS)

Centmaier, W.; Bernhard, U.; Friederich, B.; Heisecke, I.

1974-01-01

The critical parameters of reactors are controlled by safety circuits. These circuits are controlled designed as logic modules operating by the 'n-out-of-m' selection principle. In most cases, a combination of a '1-out-of-3' circuit with a '2-out-of-3' circuit and separate indication is sufficient for a dynamic fail-safe circuit. The basic logic elements are AND and OR gate circuits, respectively, which are triggered by pulse trains and in which the failure of a pulse train is indicated as an error at the output. The module allows the design of safety circuits offering various degrees of safety. If the indication of an error is made on the modules, faulty components can be exchanged by the maintenance crew right away. (DG) [de

Comparison of modified driver circuit and capacitor-transfer circuit in longitudinally excited N2 laser.

Science.gov (United States)

Uno, Kazuyuki; Akitsu, Tetsuya; Nakamura, Kenshi; Jitsuno, Takahisa

2013-04-01

We developed a modified driver circuit composed of a capacitance and a spark gap, called a direct-drive circuit, for a longitudinally excited gas laser. The direct-drive circuit uses a large discharge impedance caused by a long discharge length of the longitudinal excitation scheme and eliminates the buffer capacitance used in the traditional capacitor-transfer circuit. We compared the direct-drive circuit and the capacitor-transfer circuit in a longitudinally excited N2 laser (wavelength: 337 nm). Producing high output energy with the capacitor-transfer circuit requires a large storage capacitance and a discharge tube with optimum dimensions (an inner diameter of 4 mm and a length of 10 cm in this work); in contrast, the direct-drive circuit requires a high breakdown voltage, achieved with a small storage capacitance and a large discharge tube. Additionally, for the same input energy of 792 mJ, the maximum output energy of the capacitor-transfer circuit was 174.2 μJ, and that of the direct-drive circuit was 344.7 μJ.

Aging evaluation of electrical circuits using the ECCAD [Electrical Circuit Characterization and Diagnostic] system

International Nuclear Information System (INIS)

Edson, J.L.

1988-01-01

As a part of the Nuclear Regulatory Commission Nuclear Plant Aging Research Program, an aging assessment of electrical circuits was conducted at the Shippingport Atomic Power Station Decommissioning Project. The objective of this work was to evaluate the effectiveness of the Electrical Circuit Characterization and Diagnostic (ECCAD) system in identifying circuit conditions, to determine the present condition of selected electrical circuits, and correlate the results with aging effects. To accomplish this task, a series of electrical tests was performed on each circuit using the ECCAD system, which is composed of commercially available electronic test equipment under computer control. Test results indicate that the ECCAD system is effective in detecting and identifying aging and service wear in selected electrical circuits. The major area of degradation in the circuits tested was at the termination/connection points, whereas the cables were in generally good condition

A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

International Nuclear Information System (INIS)

Santos, D.M.; Dow, S.F.; Flasck, J.M.; Levi, M.E.

1996-01-01

Phase-locked loops have been employed in the past to obtain sub-nanosecond time resolution in high energy physics and nuclear science applications. An alternative solution based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Mueller C-element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multichannel, time-to-digital converter (TDC) targeted for one specific frequency. The two circuits, DLL and TDC, are implemented in CMOS 1.2 microm and 0.8 microm technologies, respectively. Test results show a timing jitter of less than 30 ps for the DLL circuit and less than 190 ps integral and differential nonlinearity for the TDC circuit

Multi-Layer E-Textile Circuits

Science.gov (United States)

Dunne, Lucy E.; Bibeau, Kaila; Mulligan, Lucie; Frith, Ashton; Simon, Cory

2012-01-01

Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

Analog circuit design

CERN Document Server

Dobkin, Bob

2012-01-01

Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <

ESD analog circuits and design

CERN Document Server

Voldman, Steven H

2014-01-01

A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design.  It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres

The practical engineer-fine-tuning memory macros using variable internal delays

CERN Document Server

Gray, K

1999-01-01

Embedded memory blocks are extremely common in application-specific IC (ASIC) chips. In this era of design reuse, it is critical that these memory macros, as they are also called, should be as versatile as possible. Their $9 performance should be optimal, with adequate sense amplifier signal over the full manufacturing process range of the chip. Fortunately, several simple techniques exist for adapting memory macros to different applications running at $9 different speeds. The key is to design in delays that are variable and/or programmable. The approach is also helpful in debugging initial hardware where a memory macro is refusing to function because its timing is too fast and there $9 is insufficient internal delay for proper circuit operation. The techniques can also eliminate the process of redesigning and refabricating the initial hardware just to characterize it. A memory macro is made to function by internal $9 pulses, generated in the correct number, sequence and relationship by the internal timing ch...

'Speedy' superconducting circuits

International Nuclear Information System (INIS)

Holst, T.

1994-01-01

The most promising concept for realizing ultra-fast superconducting digital circuits is the Rapid Single Flux Quantum (RSFQ) logic. The basic physical principle behind RSFQ logic, which include the storage and transfer of individual magnetic flux quanta in Superconducting Quantum Interference Devices (SQUIDs), is explained. A Set-Reset flip-flop is used as an example of the implementation of an RSFQ based circuit. Finally, the outlook for high-temperature superconducting materials in connection with RSFQ circuits is discussed in some details. (au)

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1968-01-01

Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th

Unstable oscillators based hyperchaotic circuit

DEFF Research Database (Denmark)

Murali, K.; Tamasevicius, A.; G. Mykolaitis, A.

1999-01-01

A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations in the circ...... in the circuit. The performance of the circuit is investigated by means of numerical integration of appropriate differential equations, PSPICE simulations, and hardware experiment.......A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations...

The test of VLSI circuits

Science.gov (United States)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

Circuits and filters handbook

CERN Document Server

Chen, Wai-Kai

2003-01-01

A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi

MOS integrated circuit design

CERN Document Server

Wolfendale, E

2013-01-01

MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

Security electronics circuits manual

CERN Document Server

MARSTON, R M

1998-01-01

Security Electronics Circuits Manual is an invaluable guide for engineers and technicians in the security industry. It will also prove to be a useful guide for students and experimenters, as well as providing experienced amateurs and DIY enthusiasts with numerous ideas to protect their homes, businesses and properties.As with all Ray Marston's Circuits Manuals, the style is easy-to-read and non-mathematical, with the emphasis firmly on practical applications, circuits and design ideas. The ICs and other devices used in the practical circuits are modestly priced and readily available ty

Changes to the shuttle circuits

CERN Multimedia

GS Department

2011-01-01

To fit with passengers expectation, there will be some changes to the shuttle circuits as from Monday 10 October. See details on http://cern.ch/ShuttleService (on line on 7 October). Circuit No. 5 is cancelled as circuit No. 1 also stops at Bldg. 33. In order to guarantee shorter travel times, circuit No. 1 will circulate on Meyrin site only and circuit No. 2, with departures from Bldg. 33 and 500, on Prévessin site only. Site Services Section

Troubleshooting analog circuits

CERN Document Server

Pease, Robert A

1991-01-01

Troubleshooting Analog Circuits is a guidebook for solving product or process related problems in analog circuits. The book also provides advice in selecting equipment, preventing problems, and general tips. The coverage of the book includes the philosophy of troubleshooting; the modes of failure of various components; and preventive measures. The text also deals with the active components of analog circuits, including diodes and rectifiers, optically coupled devices, solar cells, and batteries. The book will be of great use to both students and practitioners of electronics engineering. Other

Optoelectronics circuits manual

CERN Document Server

Marston, R M

2013-01-01

Optoelectronics Circuits Manual covers the basic principles and characteristics of the best known types of optoelectronic devices, as well as the practical applications of many of these optoelectronic devices. The book describes LED display circuits and LED dot- and bar-graph circuits and discusses the applications of seven-segment displays, light-sensitive devices, optocouplers, and a variety of brightness control techniques. The text also tackles infrared light-beam alarms and multichannel remote control systems. The book provides practical user information and circuitry and illustrations.

CMOS analog circuit design

CERN Document Server

Allen, Phillip E

1987-01-01

This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

Integrated circuit and method of arbitration in a network on an integrated circuit.

NARCIS (Netherlands)

2011-01-01

The invention relates to an integrated circuit and to a method of arbitration in a network on an integrated circuit. According to the invention, a method of arbitration in a network on an integrated circuit is provided, the network comprising a router unit, the router unit comprising a first input

Electronic Circuit Analysis Language (ECAL)

Science.gov (United States)

Chenghang, C.

1983-03-01

The computer aided design technique is an important development in computer applications and it is an important component of computer science. The special language for electronic circuit analysis is the foundation of computer aided design or computer aided circuit analysis (abbreviated as CACD and CACA) of simulated circuits. Electronic circuit analysis language (ECAL) is a comparatively simple and easy to use circuit analysis special language which uses the FORTRAN language to carry out the explanatory executions. It is capable of conducting dc analysis, ac analysis, and transient analysis of a circuit. Futhermore, the results of the dc analysis can be used directly as the initial conditions for the ac and transient analyses.

The Software Reliability of Large Scale Integration Circuit and Very Large Scale Integration Circuit

OpenAIRE

Artem Ganiyev; Jan Vitasek

2010-01-01

This article describes evaluation method of faultless function of large scale integration circuits (LSI) and very large scale integration circuits (VLSI). In the article there is a comparative analysis of factors which determine faultless of integrated circuits, analysis of already existing methods and model of faultless function evaluation of LSI and VLSI. The main part describes a proposed algorithm and program for analysis of fault rate in LSI and VLSI circuits.

Regulatory heterochronies and loose temporal scaling between sea star and sea urchin regulatory circuits.

Science.gov (United States)

Gildor, Tsvia; Hinman, Veronica; Ben-Tabou-De-Leon, Smadar

2017-01-01

It has long been argued that heterochrony, a change in relative timing of a developmental process, is a major source of evolutionary innovation. Heterochronic changes of regulatory gene activation could be the underlying molecular mechanism driving heterochronic changes through evolution. Here, we compare the temporal expression profiles of key regulatory circuits between sea urchin and sea star, representative of two classes of Echinoderms that shared a common ancestor about 500 million years ago. The morphologies of the sea urchin and sea star embryos are largely comparable, yet, differences in certain mesodermal cell types and ectodermal patterning result in distinct larval body plans. We generated high resolution temporal profiles of 17 mesodermally-, endodermally- and ectodermally-expressed regulatory genes in the sea star, Patiria miniata, and compared these to their orthologs in the Mediterranean sea urchin, Paracentrotus lividus. We found that the maternal to zygotic transition is delayed in the sea star compared to the sea urchin, in agreement with the longer cleavage stage in the sea star. Interestingly, the order of gene activation shows the highest variation in the relatively diverged mesodermal circuit, while the correlations of expression dynamics are the highest in the strongly conserved endodermal circuit. We detected loose scaling of the developmental rates of these species and observed interspecies heterochronies within all studied regulatory circuits. Thus, after 500 million years of parallel evolution, mild heterochronies between the species are frequently observed and the tight temporal scaling observed for closely related species no longer holds.

Magnonic logic circuits

International Nuclear Information System (INIS)

Khitun, Alexander; Bao Mingqiang; Wang, Kang L

2010-01-01

We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

Monolithic microwave integrated circuit water vapor radiometer

Science.gov (United States)

Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

1991-01-01

A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

Electrical Circuits and Water Analogies

Science.gov (United States)

Smith, Frederick A.; Wilson, Jerry D.

1974-01-01

Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)

Optically controllable molecular logic circuits

International Nuclear Information System (INIS)

Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

2015-01-01

Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

Optimal planning of series resistor to control time constant of test circuit for high-voltage AC circuit-breakers

OpenAIRE

Yoon-Ho Kim; Jung-Hyeon Ryu; Jin-Hwan Kim; Kern-Joong Kim

2016-01-01

The equivalent test circuit that can deliver both short-circuit current and recovery voltage is used to verify the performance of high-voltage circuit breakers. Most of the parameters in this circuit can be obtained by using a simple calculation or a simulation program. The ratings of the circuit breaker include rated short-circuit breaking current, rated short-circuit making current, rated operating sequence of the circuit breaker and rated short-time current. Among these ratings, the short-...

Interface Circuit For Printer Port

Science.gov (United States)

Tucker, Jerry H.; Yadlowsky, Ann B.

1991-01-01

Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

A Two-Layer Gene Circuit for Decoupling Cell Growth from Metabolite Production.

Science.gov (United States)

Lo, Tat-Ming; Chng, Si Hui; Teo, Wei Suong; Cho, Han-Saem; Chang, Matthew Wook

2016-08-01

We present a synthetic gene circuit for decoupling cell growth from metabolite production through autonomous regulation of enzymatic pathways by integrated modules that sense nutrient and substrate. The two-layer circuit allows Escherichia coli to selectively utilize target substrates in a mixed pool; channel metabolic resources to growth by delaying enzymatic conversion until nutrient depletion; and activate, terminate, and re-activate conversion upon substrate availability. We developed two versions of controller, both of which have glucose nutrient sensors but differ in their substrate-sensing modules. One controller is specific for hydroxycinnamic acid and the other for oleic acid. Our hydroxycinnamic acid controller lowered metabolic stress 2-fold and increased the growth rate 2-fold and productivity 5-fold, whereas our oleic acid controller lowered metabolic stress 2-fold and increased the growth rate 1.3-fold and productivity 2.4-fold. These results demonstrate the potential for engineering strategies that decouple growth and production to make bio-based production more economical and sustainable. Copyright © 2016 The Authors. Published by Elsevier Inc. All rights reserved.

Maximum Acceleration Recording Circuit

Science.gov (United States)

Bozeman, Richard J., Jr.

1995-01-01

Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

Radiation-sensitive switching circuits

Energy Technology Data Exchange (ETDEWEB)

Moore, J.H.; Cockshott, C.P.

1976-03-16

A radiation-sensitive switching circuit has a light emitting diode which supplies light to a photo-transistor, the light being interrupted from time to time. When the photo-transistor is illuminated, current builds up and when this current reaches a predetermined value, a trigger circuit changes state. The peak output of the photo-transistor is measured and the trigger circuit is arranged to change state when the output of the device is a set proportion of the peak output, so as to allow for aging of the components. The circuit is designed to control the ignition system in an automobile engine.

Four-junction superconducting circuit

Science.gov (United States)

Qiu, Yueyin; Xiong, Wei; He, Xiao-Ling; Li, Tie-Fu; You, J. Q.

2016-01-01

We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit. PMID:27356619

Control circuit for transformer relay

International Nuclear Information System (INIS)

Wyatt, G.A.

1984-01-01

A control circuit for a transformer relay which will automatically momentarily control the transformer relay to a selected state upon energization of the control circuit. The control circuit has an energy storage element and a current director coupled in series and adapted to be coupled with the secondary winding of the transformer relay. A device for discharge is coupled across the energy storage element. The energy storage element and current director will momentarily allow a unidirectional flow of current in the secondary winding of the transformer relay upon application of energy to the control circuit. When energy is not applied to the control circuit the device for discharge will allow the energy storage element to discharge and be available for another operation of the control circuit

Adder design using a 5-input majority gate in a novel “multilayer gate design paradigm” for quantum dot cellular automata circuits

International Nuclear Information System (INIS)

Kumar, Rohit; Ghosh, Bahniman; Gupta, Shoubhik

2015-01-01

This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input–output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact. (paper)

Integrated coherent matter wave circuits

International Nuclear Information System (INIS)

Ryu, C.; Boshier, M. G.

2015-01-01

An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

Model Comparison Exercise Circuit Training Game and Circuit Ladder Drills to Improve Agility and Speed

Directory of Open Access Journals (Sweden)

Susilaturochman Hendrawan Koestanto

2017-11-01

Full Text Available The purpose of this study was to compare: (1 the effect of circuit training game and circuit ladder drill for the agility; (2 the effect of circuit training game and circuit ladder drill on speed; (3 the difference effect of circuit training game and circuit ladder drill for the speed (4 the difference effect of circuit training game and circuit ladder drill on agility. The type of this research was quantitative with quasi-experimental methods. The design of this research was Factorial Design, with analysing data using ANOVA. The process of data collection was done by using 30 meters sprint speed test and shuttle run test during the pretest and posttest. Furthermore, the data was analyzed by using SPSS 22.0 series. Result: The circuit training game exercise program and circuit ladder drill were significant to increase agility and speed (sig 0.000 < α = 0.005 Group I, II, III had significant differences (sig 0.000 < α = 0.005. The mean of increase in speed of group I = 0.20 seconds, group II = 0.31 seconds, and group III = 0.11 seconds. The average increase agility to group I = 0.34 seconds group II = 0.60 seconds, group III = 0.13 seconds. Based on the analysis above, it could be concluded that there was an increase in the speed and agility of each group after being given a training.

Comminution circuits for compact itabirites

Directory of Open Access Journals (Sweden)

Pedro Ferreira Pinto

Full Text Available Abstract In the beneficiation of compact Itabirites, crushing and grinding account for major operational and capital costs. As such, the study and development of comminution circuits have a fundamental importance for feasibility and optimization of compact Itabirite beneficiation. This work makes a comparison between comminution circuits for compact Itabirites from the Iron Quadrangle. The circuits developed are: a crushing and ball mill circuit (CB, a SAG mill and ball mill circuit (SAB and a single stage SAG mill circuit (SSSAG. For the SAB circuit, the use of pebble crushing is analyzed (SABC. An industrial circuit for 25 million tons of run of mine was developed for each route from tests on a pilot scale (grinding and industrial scale. The energy consumption obtained for grinding in the pilot tests was compared with that reported by Donda and Bond. The SSSAG route had the lowest energy consumption, 11.8kWh/t and the SAB route had the highest energy consumption, 15.8kWh/t. The CB and SABC routes had a similar energy consumption of 14.4 kWh/t and 14.5 kWh/t respectively.

30 CFR 77.506-1 - Electric equipment and circuits; overload and short circuit protection; minimum requirements.

Science.gov (United States)

2010-07-01

... short circuit protection; minimum requirements. 77.506-1 Section 77.506-1 Mineral Resources MINE SAFETY...-1 Electric equipment and circuits; overload and short circuit protection; minimum requirements. Devices providing either short circuit protection or protection against overload shall conform to the...

Bistability and hysteresis in the emergence of pulses in microstrip Gunn-diode circuits

Energy Technology Data Exchange (ETDEWEB)

Yurchenko, V. B., E-mail: v.yurchenko@nuim.ie [O. Ya. Usikov Institute for Radiophysics and Electronics, National Academy of Sciences of Ukraine, 12 Proskura St., Kharkiv 61085 (Ukraine); Electrical and Electronic Engineering Department, Gazi University, Celal Bayar Bulvari, Ankara 06570 (Turkey); Yurchenko, L. V. [O. Ya. Usikov Institute for Radiophysics and Electronics, National Academy of Sciences of Ukraine, 12 Proskura St., Kharkiv 61085 (Ukraine)

2014-12-15

We develop time-domain simulations of microwave and THz radiation sources built as arrays of active devices when the radiation wavelength is small as compared to spacing between electronic components. We pursue an approach when the system is represented by equations with time-delay feedback that could generate chaos and other forms of complicated dynamics. The approach simplifies simulations of ultra-wideband effects and exceeds capabilities of frequency-domain methods. As a model case, we simulated a microstrip circuit with Gunn diode and a remote resonator emitting the radiation towards infinity. We observed the emergence of either the continuous waves or the trains of high-frequency pulses depending on the bias conditions. We found bistability and hysteresis in the onset of different oscillation modes that depends on the way of driving the bias voltage into the domain of instability of the given system. The results would allow one to improve the design of THz radiation sources with time-delay coupling between components.

Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

KAUST Repository

Hanna, Amir

2015-12-04

High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

Clocking Scheme for Switched-Capacitor Circuits

DEFF Research Database (Denmark)

Steensgaard-Madsen, Jesper

1998-01-01

A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed.......A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed....

A chaotic jerk system with non-hyperbolic equilibrium: Dynamics, effect of time delay and circuit realisation

Science.gov (United States)

Rajagopal, Karthikeyan; Pham, Viet-Thanh; Tahir, Fadhil Rahma; Akgul, Akif; Abdolmohammadi, Hamid Reza; Jafari, Sajad

2018-04-01

The literature on chaos has highlighted several chaotic systems with special features. In this work, a novel chaotic jerk system with non-hyperbolic equilibrium is proposed. The dynamics of this new system is revealed through equilibrium analysis, phase portrait, bifurcation diagram and Lyapunov exponents. In addition, we investigate the time-delay effects on the proposed system. Realisation of such a system is presented to verify its feasibility.

Trapped modes in linear quantum stochastic networks with delays

Energy Technology Data Exchange (ETDEWEB)

Tabak, Gil [Stanford University, Department of Applied Physics, Stanford, CA (United States); Mabuchi, Hideo

2016-12-15

Networks of open quantum systems with feedback have become an active area of research for applications such as quantum control, quantum communication and coherent information processing. A canonical formalism for the interconnection of open quantum systems using quantum stochastic differential equations (QSDEs) has been developed by Gough, James and co-workers and has been used to develop practical modeling approaches for complex quantum optical, microwave and optomechanical circuits/networks. In this paper we fill a significant gap in existing methodology by showing how trapped modes resulting from feedback via coupled channels with finite propagation delays can be identified systematically in a given passive linear network. Our method is based on the Blaschke-Potapov multiplicative factorization theorem for inner matrix-valued functions, which has been applied in the past to analog electronic networks. Our results provide a basis for extending the Quantum Hardware Description Language (QHDL) framework for automated quantum network model construction (Tezak et al. in Philos. Trans. R. Soc. A, Math. Phys. Eng. Sci. 370(1979):5270-5290, 2012) to efficiently treat scenarios in which each interconnection of components has an associated signal propagation time delay. (orig.)

30 CFR 75.518-1 - Electric equipment and circuits; overload and short circuit protection; minimum requirements.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Electric equipment and circuits; overload and short circuit protection; minimum requirements. 75.518-1 Section 75.518-1 Mineral Resources MINE SAFETY... short circuit protection; minimum requirements. A device to provide either short circuit protection or...

Contribution to the study of time-resolution in pulse electronics for nuclear physics: phase control circuits; Contribution a l'etude de la resolution en temps de l'electronique impulsionnelle pour physique nucleaire: les circuits de mise en phase

Energy Technology Data Exchange (ETDEWEB)

Cortet, J P [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

1969-07-01

Phase control circuits make it possible to improve quite markedly the time resolution in pulse electronics. They replace a random pulse, of which the time of arrival with respect to a reference zero is being measured, by another pulse whose phase is well determined with respect to that, of a clock taken as reference. The time spectrum of the output, delayed, can always be situated inside channels of width {delta}T defined by the clock. The time statistics of the events analyzed is always correct even if the transition time for the circuits defining the channels represents a large fraction of {delta}T: the coding of the time becomes perfect, The phase control circuits, used in precision chronometry, are widely applied in Nuclear Physics since the lime spectra obtained are representative, indirectly, of certain values which are required to be measured with great accuracy. A description is given of: the constitution and operation of phase control circuits; a chain with automatic analysis and automatic reading, built for testing these circuits. Finally the measurement results are given. (author) [French] Les circuits de mise en phase permettent d'ameliorer notablement la resolution en temps de l'electronique impulsionnelle. Ils substituent a une impulsion aleatoire, dont on cherche a mesurer l'instant d'arrivee par rapport a un instant pris pour origine, une autre impulsion dont la phase est bien determinee par rapport a celle d'une horloge prise comme reference. Le spectre temporel de sortie, retarde, peut toujours etre situe a l'interieur des canaux de largeur {delta}T, definis par l'horloge. La statistique temporelle des evenements analyses est toujours correcte, meme si la duree de transition des circuits definissant les canaux represente une grande fraction de {delta}T: le codage de temps devient parfait. Les circuits de mise en phase, utilises en chronometrie fine, sont tres employes en Physique Nucleaire car les spectres temporels oblenus sont representatifs

Optimal Joint Expected Delay Forwarding in Delay Tolerant Networks

OpenAIRE

Jia Xu; Xin Feng; Wen Jun Yang; Ru Chuan Wang; Bing Qing Han

2013-01-01

Multicopy forwarding schemes have been employed in delay tolerant network (DTN) to improve the delivery delay and delivery rate. Much effort has been focused on reducing the routing cost while retaining high performance. This paper aims to provide an optimal joint expected delay forwarding (OJEDF) protocol which minimizes the expected delay while satisfying a certain constant on the number of forwardings per message. We propose a comprehensive forwarding metric called joint expected delay (JE...

Selected collection of circuit drawings

International Nuclear Information System (INIS)

1977-01-01

The many electronics circuits have been constracted in the Electronics Shop for use in nuclear experiments or other purposes of this Institute. The types of these circuits amount to about 500 items in total since 1968. This report describes the electronics circuit diagrams selected from this collection. The circuit details are not presented in this report, because these are already been published in the other technical reports. (auth.)

Circuits on Cylinders

DEFF Research Database (Denmark)

Hansen, Kristoffer Arnsfelt; Miltersen, Peter Bro; Vinay, V

2006-01-01

We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a Pi2 o MOD o AC0 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching pro...

Digital circuit boards mach 1 GHz

CERN Document Server

Morrison, Ralph

2012-01-01

A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove

Effects of neonatal inferior prefrontal and medial temporal lesions on learning the rule for delayed nonmatching-to-sample.

Science.gov (United States)

Málková, L; Bachevalier, J; Webster, M; Mishkin, M

2000-01-01

The ability of rhesus monkeys to master the rule for delayed nonmatching-to-sample (DNMS) has a protracted ontogenetic development, reaching adult levels of proficiency around 4 to 5 years of age (Bachevalier, 1990). To test the possibility that this slow development could be due, at least in part, to immaturity of the prefrontal component of a temporo-prefrontal circuit important for DNMS rule learning (Kowalska, Bachevalier, & Mishkin, 1991; Weinstein, Saunders, & Mishkin, 1988), monkeys with neonatal lesions of the inferior prefrontal convexity were compared on DNMS with both normal controls and animals given neonatal lesions of the medial temporal lobe. Consistent with our previous results (Bachevalier & Mishkin, 1994; Málková, Mishkin, & Bachevalier, 1995), the neonatal medial temporal lesions led to marked impairment in rule learning (as well as in recognition memory with long delays and list lengths) at both 3 months and 2 years of age. By contrast, the neonatal inferior convexity lesions yielded no impairment in rule-learning at 3 months and only a mild impairment at 2 years, a finding that also contrasts sharply with the marked effects of the same lesion made in adulthood. This pattern of sparing closely resembles the one found earlier after neonatal lesions to the cortical visual area TE (Bachevalier & Mishkin, 1994; Málková et al., 1995). The functional sparing at 3 months probably reflects the fact that the temporo-prefrontal circuit is nonfunctional at this early age, resulting in a total dependency on medial temporal contributions to rule learning. With further development, however, this circuit begins to provide a supplementary route for learning.

Integrated circuit cooled turbine blade

Science.gov (United States)

Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.; Holloman, Harry; Koester, Steven

2017-08-29

A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channel connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.

Advanced circuit simulation using Multisim workbench

CERN Document Server

Báez-López, David; Cervantes-Villagómez, Ofelia Delfina

2012-01-01

Multisim is now the de facto standard for circuit simulation. It is a SPICE-based circuit simulator which combines analog, discrete-time, and mixed-mode circuits. In addition, it is the only simulator which incorporates microcontroller simulation in the same environment. It also includes a tool for printed circuit board design.Advanced Circuit Simulation Using Multisim Workbench is a companion book to Circuit Analysis Using Multisim, published by Morgan & Claypool in 2011. This new book covers advanced analyses and the creation of models and subcircuits. It also includes coverage of transmissi

MOS voltage automatic tuning circuit

OpenAIRE

李, 田茂; 中田, 辰則; 松本, 寛樹

2004-01-01

Abstract ###Automatic tuning circuit adjusts frequency performance to compensate for the process variation. Phase locked ###loop (PLL) is a suitable oscillator for the integrated circuit. It is a feedback system that compares the input ###phase with the output phase. It can make the output frequency equal to the input frequency. In this paper, PLL ###fomed of MOSFET's is presented.The presented circuit consists of XOR circuit, Low-pass filter and Relaxation ###Oscillator. On PSPICE simulation...

Regenerative feedback resonant circuit

Science.gov (United States)

Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.

2014-09-02

A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.

Stochastically Estimating Modular Criticality in Large-Scale Logic Circuits Using Sparsity Regularization and Compressive Sensing

Directory of Open Access Journals (Sweden)

Mohammed Alawad

2015-03-01

Full Text Available This paper considers the problem of how to efficiently measure a large and complex information field with optimally few observations. Specifically, we investigate how to stochastically estimate modular criticality values in a large-scale digital circuit with a very limited number of measurements in order to minimize the total measurement efforts and time. We prove that, through sparsity-promoting transform domain regularization and by strategically integrating compressive sensing with Bayesian learning, more than 98% of the overall measurement accuracy can be achieved with fewer than 10% of measurements as required in a conventional approach that uses exhaustive measurements. Furthermore, we illustrate that the obtained criticality results can be utilized to selectively fortify large-scale digital circuits for operation with narrow voltage headrooms and in the presence of soft-errors rising at near threshold voltage levels, without excessive hardware overheads. Our numerical simulation results have shown that, by optimally allocating only 10% circuit redundancy, for some large-scale benchmark circuits, we can achieve more than a three-times reduction in its overall error probability, whereas if randomly distributing such 10% hardware resource, less than 2% improvements in the target circuit’s overall robustness will be observed. Finally, we conjecture that our proposed approach can be readily applied to estimate other essential properties of digital circuits that are critical to designing and analyzing them, such as the observability measure in reliability analysis and the path delay estimation in stochastic timing analysis. The only key requirement of our proposed methodology is that these global information fields exhibit a certain degree of smoothness, which is universally true for almost any physical phenomenon.

Arithmetic circuits for DSP applications

CERN Document Server

Stouraitis, Thanos

2017-01-01

Arithmetic Circuits for DSP Applications is a complete resource on arithmetic circuits for digital signal processing (DSP). It covers the key concepts, designs and developments of different types of arithmetic circuits, which can be used for improving the efficiency of implementation of a multitude of DSP applications. Each chapter includes various applications of the respective class of arithmetic circuits along with information on the future scope of research. Written for students, engineers, and researchers in electrical and computer engineering, this comprehensive text offers a clear understanding of different types of arithmetic circuits used for digital signal processing applications. The text includes contributions from noted researchers on a wide range of topics, including a review o circuits used in implementing basic operations like additions and multiplications; distributed arithmetic as a technique for the multiplier-less implementation of inner products for DSP applications; discussions on look ...

Source-circuit design overview

Science.gov (United States)

Ross, R. G., Jr.

1983-01-01

The source circuit is the fundamental electrical building block of a large central-station array; it consists of a series-parallel network of solar cells that develops full system voltage. The array field is generally made up of a large number of parallel source circuits. Source-circuit electrical configuration is driven by a number of design considerations, which must be considered simultaneously. Array fault tolerance and hot spot heating endurance are examined in detail.

PWR type reactor equipped with a primary circuit loop water level gauge

International Nuclear Information System (INIS)

Suzuki, Mitsuhiro.

1990-01-01

The time of lowering a water level to less than the position of high temperature side pipeway nozzle has been rather delayed because of the swelling of mixed water level due to heat generation of the reactor core. Further, there has been a certain restriction for the installation, maintenance and adjustment of a water level gauge since it is at a position under high radiation exposure. Then, a differential pressure type water level gauge with temperature compensation is disposed at a portion below a water level gauge of a pressurizer and between the steam generator exit plenum and the lower end of the loop seal. Further, a similar water level system is disposed to all of the loops of the primary circulation circuits. In a case that the amount of water contained in a reactor container should decreased upon occurrence of loss of coolant accidents caused by small rupture and stoppage of primary circuit pumps, lowering of the water level preceding to the lowering of the water level in the reactor core is detected to ensure the amount of water. Since they are disposed to all of the loops and ensure the excess margin, reliability for the detection of the amount of contained water can be improved by averaging time for the data of the water level and averaging the entire systems, even when there are vibrations in the fluid or pressure in the primary circuit. (N.H.)

Application of a commercial diffusion type carbon meter in a sodium circuit

International Nuclear Information System (INIS)

Bhat, N.P.; Borgstedt, H.U.; Peric, Z.; Witting, G.

1980-01-01

The exchange of carbon between structural materials and liquid sodium influences the mechanical properties of components of the cooling circuits. Therefore, the estimation of the carbon content of the alkali metal and the knowledge of its carburizing potential is of importance. Since some years the measurement of the carburizing potential of sodium is easy to perform by the application of the foil equilibration method which leads to good results in spite of the very low carbon concentrations in the liquid metal. Thin foils (0.025 to 0.125 mm) of Fe-18Cr-8Ni-C alloy (corresponding to stainless steel type AISI 304) are immersed in sodium at 550 to 700 deg. C for 200 to 400 hours. The equilibrium of the carbon distribution must be reached. Chemical analyses of the steel tabs and relation of concentration to activity of carbon lead to information on the carbon concentration in the sodium, if the saturation concentration of carbon in sodium is known. The method gives arbitrary values over a longer period of time. The time needed for equilibration and analysis causes a delay for the getting of results. Therefore, there is a need for instruments which are capable to measure carbon directly in the circuits and give continuously information on the actual carbon activities in the fluid. Until 1975 only one carbon meter was commercially available. One unit in was tested a chemical analytical sodium circuit

Analysis of the delayed afterheat removal for a pebble-bed high temperature reactor concept as a contribution to the possibility for limitation of hypothetical accidents

International Nuclear Information System (INIS)

Rehm, W.

1980-02-01

The report presents the analysis of thermodynamic transients for a pebble-bed HTR concept which occur during the delayed after-heat removal of an overheated HTR-core. The consequences of the temperature behaviour are considered for the components of the circuit and the heat exchanger. The analysis is based on a core heatup following a depressurization of the primary circuit and a hypothetical loss of all the redundant cooling systems. By means of calculations it is demonstrated that a regular core structure and a coolable circuit geometry remain. In addition, it appears that the efficiency of the first fission product barrier is not impaired. The slow temperature transients of 2 0 C/min allow the possibility to restart failed afterheat loops to limit the temperature excursion. Provided that certain design and control features are incorporated, the afterheat removal systems can be restarted successfully even after long delay periods. During corresponding emergency procedures the heat exchangers are not demaged. The problems arising from failure limits for specific concepts must be solved. The consequences of total failure of afterheat removal systems are discussed. These consequences can be limited by taking into account the characteristic features of the HTR-system together with additional counter-measures. (orig.) [de

Distortion Cancellation via Polyphase Multipath Circuits

NARCIS (Netherlands)

Mensink, E.; Klumperink, Eric A.M.; Nauta, Bram

The central question of this paper is: can we enhance the spectral purity of nonlinear circuits with the help of polyphase multipath circuits. Polyphase multipath circuits are circuits with two or more paths that exploit phase differences between the paths to cancel unwanted signals. It turns out

Software-Controlled Next Generation Optical Circuit Switching for HPC and Cloud Computing Datacenters

Directory of Open Access Journals (Sweden)

Muhammad Imran

2015-11-01

Full Text Available In this paper, we consider the performance of optical circuit switching (OCS systems designed for data center networks by using network-level simulation. Recent proposals have used OCS in data center networks but the relatively slow switching times of OCS-MEMS switches (10–100 ms and the latencies of control planes in these approaches have limited their use to the largest data center networks with workloads that last several seconds. Herein, we extend the applicability and generality of these studies by considering dynamically changing short-lived circuits in software-controlled OCS switches, using the faster switching technologies that are now available. The modelled switch architecture features fast optical switches in a single hop topology with a centralized, software-defined optical control plane. We model different workloads with various traffic aggregation parameters to investigate the performance of such designs across usage patterns. Our results show that, with suitable choices for the OCS system parameters, delay performance comparable to that of electrical data center networks can be obtained.

Variational integrators for electric circuits

International Nuclear Information System (INIS)

Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.

2013-01-01

In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator

Behavioral synthesis of asynchronous circuits

DEFF Research Database (Denmark)

Nielsen, Sune Fallgaard

2005-01-01

This thesis presents a method for behavioral synthesis of asynchronous circuits, which aims at providing a synthesis flow which uses and tranfers methods from synchronous circuits to asynchronous circuits. We move the synchronous behavioral synthesis abstraction into the asynchronous handshake...... is idle. This reduces unnecessary switching activity in the individual functional units and therefore the energy consumption of the entire circuit. A collection of behavioral synthesis algorithms have been developed allowing the designer to perform time and power constrained design space exploration...

Diode, transistor & fet circuits manual

CERN Document Server

Marston, R M

2013-01-01

Diode, Transistor and FET Circuits Manual is a handbook of circuits based on discrete semiconductor components such as diodes, transistors, and FETS. The book also includes diagrams and practical circuits. The book describes basic and special diode characteristics, heat wave-rectifier circuits, transformers, filter capacitors, and rectifier ratings. The text also presents practical applications of associated devices, for example, zeners, varicaps, photodiodes, or LEDs, as well as it describes bipolar transistor characteristics. The transistor can be used in three basic amplifier configuration

Analysis of Bernstein's factorization circuit

NARCIS (Netherlands)

Lenstra, A.K.; Shamir, A.; Tomlinson, J.; Tromer, E.; Zheng, Y.

2002-01-01

In [1], Bernstein proposed a circuit-based implementation of the matrix step of the number field sieve factorization algorithm. These circuits offer an asymptotic cost reduction under the measure "construction cost x run time". We evaluate the cost of these circuits, in agreement with [1], but argue

An electronic interface for acquisition of 12 delayed gamma-gammacoincidence spectra

International Nuclear Information System (INIS)

Domienikan, Claudio

2001-01-01

An electronic interface has been constructed to be used m conjunctionwith a Time differential Perturbed gamma-gamma Angular Correlation (TDPAC)spectrometer with four BaF 2 detectors. The routing interface is speciallydesigned to work with the Ortec model ADCAM 920-16 multichannel analyzer(MCA) having 16 multiplexed inputs, permitting the simultaneous acquisitionof 12 delayed gamma-gamma coincidence spectra. This innovation provides aconsiderable reduction in the experimental data acquisition time and as aconsequence permits an improvement in the precision of the final results ofthe hyperfine parameters deduced from the TDPAC measurements. The interfaceconsists of two distinct electronic circuits. A novel high performance analogdemultiplexer circuit is used to address the linear pulses from the time toamplitude converter (TAC) to the corresponding MCA inputs, according to thepair of detectors responsible for the given gamma-gamma coincidence.Validation of the gamma-gamma coincidence and control of the analogdemultiplexer are realized by a digital circuit, consisting basically ofmonostable multivibrators and decoders of High-Speed CMOS Logic (HCT). Theperformance of the routing interface was evaluated through several testmeasurements which included the time resolution and linearity of the system,the quadrupolar interaction in 181 Ta(Hf), 181 Ta(HfO 2 ), 111 Cd(Cd)and 111 Cd(Pd) samples, and the hyperfine magnetic field in 181 'Ta(Ni), 11 '1Cd(Ni) and 140 Ce(Gd) samples. The results of the hyperfineinteraction measurements are discussed and compared with previous results andserve to demonstrate the correct and efficient performance of the constructedinterface. (author)

Testing Solutions of the Protection Systems Provided with Delay Maximum Current Relays

Directory of Open Access Journals (Sweden)

Horia BALAN

2017-12-01

Full Text Available Relay protection is one of the main forms of automation control of electro energy systems, having as primary aims fault detection and disconnection of the faulty element in order to avoid the extent of damages and the as fast as possible recovery to the normal operation regime for the rest of the system. Faults that occur in the electro energy system can be classified considering on one hand their causes and on the other their types, but in the vast majority of cases the causes of the faults are combined. Further, considering their nature, faults are classified in faults due to the insulation’s damage, in faults due to the destruction of the integrity of the circuits and faults determined by interruptions. With respect to their nature, faults are short circuits, earthing faults and phases interruptions. At the same time, considering their type, faults are divided in transversal and longitudinal ones. The paper presents a testing solution of the delayed maximal current relays using a T3000 ISA Test measuring equipment.

Radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

Derbenwick, G.F.; Hughes, R.C.

1977-01-01

Electronic circuits that operate properly after exposure to ionizing radiation are necessary for nuclear weapon systems, satellites, and apparatus designed for use in radiation environments. The program to develop and theoretically model radiation-tolerant integrated circuit components has resulted in devices that show an improvement in hardness up to a factor of ten thousand over earlier devices. An inverter circuit produced functions properly after an exposure of 10 6 Gy (Si) which, as far as is known, is the record for an integrated circuit

Physically based arc-circuit interaction

International Nuclear Information System (INIS)

Zhong-Lie, L.

1984-01-01

An integral arc model is extended to study the interaction of the gas blast arc with the test circuit in this paper. The deformation in the waveshapes of arc current and voltage around the current zero has been formulated to first approximation by using a simple model of arc voltage based on the arc core energy conservation. By supplementing with the time scale for the radiation, the time rates of arc processes were amended. Both the contributions of various arc processes and the influence of circuit parameters to the arc-circuit interaction have been estimated by this theory. Analysis generated a new method of calculating test circuit parameters which improves the accurate simulation of arc-circuit interaction. The new method agrees with the published experimental results

Stability and delay sensitivity of neutral fractional-delay systems.

Science.gov (United States)

Xu, Qi; Shi, Min; Wang, Zaihua

2016-08-01

This paper generalizes the stability test method via integral estimation for integer-order neutral time-delay systems to neutral fractional-delay systems. The key step in stability test is the calculation of the number of unstable characteristic roots that is described by a definite integral over an interval from zero to a sufficient large upper limit. Algorithms for correctly estimating the upper limits of the integral are given in two concise ways, parameter dependent or independent. A special feature of the proposed method is that it judges the stability of fractional-delay systems simply by using rough integral estimation. Meanwhile, the paper shows that for some neutral fractional-delay systems, the stability is extremely sensitive to the change of time delays. Examples are given for demonstrating the proposed method as well as the delay sensitivity.

Integrated circuits, and design and manufacture thereof

Science.gov (United States)

Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

2006-04-18

A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

Instrumentation and test gear circuits manual

CERN Document Server

Marston, R M

2013-01-01

Instrumentation and Test Gear Circuits Manual provides diagrams, graphs, tables, and discussions of several types of practical circuits. The practical circuits covered in this book include attenuators, bridges, scope trace doublers, timebases, and digital frequency meters. Chapter 1 discusses the basic instrumentation and test gear principles. Chapter 2 deals with the design of passive attenuators, and Chapter 3 with passive and active filter circuits. The subsequent chapters tackle 'bridge' circuits, analogue and digital metering techniques and circuitry, signal and waveform generation, and p

Multi-qubit circuit quantum electrodynamics

International Nuclear Information System (INIS)

Viehmann, Oliver

2013-01-01

Circuit QED systems are macroscopic, man-made quantum systems in which superconducting artificial atoms, also called Josephson qubits, interact with a quantized electromagnetic field. These systems have been devised to mimic the physics of elementary quantum optical systems with real atoms in a scalable and more flexible framework. This opens up a variety of possible applications of circuit QED systems. For instance, they provide a promising platform for processing quantum information. Recent years have seen rapid experimental progress on these systems, and experiments with multi-component circuit QED architectures are currently starting to come within reach. In this thesis, circuit QED systems with multiple Josephson qubits are studied theoretically. We focus on simple and experimentally realistic extensions of the currently operated circuit QED setups and pursue investigations in two main directions. First, we consider the equilibrium behavior of circuit QED systems containing a large number of mutually noninteracting Josephson charge qubits. The currently accepted standard description of circuit QED predicts the possibility of superradiant phase transitions in such systems. However, a full microscopic treatment shows that a no-go theorem for superradiant phase transitions known from atomic physics applies to circuit QED systems as well. This reveals previously unknown limitations of the applicability of the standard theory of circuit QED to multi-qubit systems. Second, we explore the potential of circuit QED for quantum simulations of interacting quantum many-body systems. We propose and analyze a circuit QED architecture that implements the quantum Ising chain in a time-dependent transverse magnetic field. Our setup can be used to study quench dynamics, the propagation of localized excitations, and other non-equilibrium features in this paradigmatic model in the theory of non-equilibrium thermodynamics and quantumcritical phenomena. The setup is based on a

Multi-qubit circuit quantum electrodynamics

Energy Technology Data Exchange (ETDEWEB)

Viehmann, Oliver

2013-09-03

Circuit QED systems are macroscopic, man-made quantum systems in which superconducting artificial atoms, also called Josephson qubits, interact with a quantized electromagnetic field. These systems have been devised to mimic the physics of elementary quantum optical systems with real atoms in a scalable and more flexible framework. This opens up a variety of possible applications of circuit QED systems. For instance, they provide a promising platform for processing quantum information. Recent years have seen rapid experimental progress on these systems, and experiments with multi-component circuit QED architectures are currently starting to come within reach. In this thesis, circuit QED systems with multiple Josephson qubits are studied theoretically. We focus on simple and experimentally realistic extensions of the currently operated circuit QED setups and pursue investigations in two main directions. First, we consider the equilibrium behavior of circuit QED systems containing a large number of mutually noninteracting Josephson charge qubits. The currently accepted standard description of circuit QED predicts the possibility of superradiant phase transitions in such systems. However, a full microscopic treatment shows that a no-go theorem for superradiant phase transitions known from atomic physics applies to circuit QED systems as well. This reveals previously unknown limitations of the applicability of the standard theory of circuit QED to multi-qubit systems. Second, we explore the potential of circuit QED for quantum simulations of interacting quantum many-body systems. We propose and analyze a circuit QED architecture that implements the quantum Ising chain in a time-dependent transverse magnetic field. Our setup can be used to study quench dynamics, the propagation of localized excitations, and other non-equilibrium features in this paradigmatic model in the theory of non-equilibrium thermodynamics and quantumcritical phenomena. The setup is based on a

Experimental study on short-circuit characteristics of the new protection circuit of insulated gate bipolar transistor

International Nuclear Information System (INIS)

Ji, In-Hwan; Choi, Young-Hwan; Ha, Min-Woo; Han, Min-Koo; Choi, Yearn-Ik

2006-01-01

A new protection circuit employing the collector to emitter voltage (V CE ) sensing scheme for short-circuit withstanding capability of the insulated gate bipolar transistor (IGBT) is proposed and verified by experimental results. Because the current path between the gate and collector can be successfully eliminated in the proposed protection circuit, the power consumption can be reduced and the gate input impedance can be increased. Previous study is limited to dc characteristics. However, experimental results show that the proposed protection circuit successfully reduces the over-current of main IGBT by 80.4% under the short-circuit condition

Multifractal chaotic attractors in a system of delay-differential equations modeling road traffic.

Science.gov (United States)

Safonov, Leonid A.; Tomer, Elad; Strygin, Vadim V.; Ashkenazy, Yosef; Havlin, Shlomo

2002-12-01

We study a system of delay-differential equations modeling single-lane road traffic. The cars move in a closed circuit and the system's variables are each car's velocity and the distance to the car ahead. For low and high values of traffic density the system has a stable equilibrium solution, corresponding to the uniform flow. Gradually decreasing the density from high to intermediate values we observe a sequence of supercritical Hopf bifurcations forming multistable limit cycles, corresponding to flow regimes with periodically moving traffic jams. Using an asymptotic technique we find approximately small limit cycles born at Hopf bifurcations and numerically preform their global continuations with decreasing density. For sufficiently large delay the system passes to chaos following the Ruelle-Takens-Newhouse scenario (limit cycles-two-tori-three-tori-chaotic attractors). We find that chaotic and nonchaotic attractors coexist for the same parameter values and that chaotic attractors have a broad multifractal spectrum. (c) 2002 American Institute of Physics.

High voltage MOSFET switching circuit

Science.gov (United States)

McEwan, Thomas E.

1994-01-01

The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

Graphene radio frequency receiver integrated circuit.

Science.gov (United States)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

Apparatus and method for defect testing of integrated circuits

Science.gov (United States)

Cole, Jr., Edward I.; Soden, Jerry M.

2000-01-01

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Investigation of Equivalent Circuit for PEMFC Assessment

International Nuclear Information System (INIS)

Myong, Kwang Jae

2011-01-01

Chemical reactions occurring in a PEMFC are dominated by the physical conditions and interface properties, and the reactions are expressed in terms of impedance. The performance of a PEMFC can be simply diagnosed by examining the impedance because impedance characteristics can be expressed by an equivalent electrical circuit. In this study, the characteristics of a PEMFC are assessed using the AC impedance and various equivalent circuits such as a simple equivalent circuit, equivalent circuit with a CPE, equivalent circuit with two RCs, and equivalent circuit with two CPEs. It was found in this study that the characteristics of a PEMFC could be assessed using impedance and an equivalent circuit, and the accuracy was highest for an equivalent circuit with two CPEs

Automatic circuit analysis based on mask information

International Nuclear Information System (INIS)

Preas, B.T.; Lindsay, B.W.; Gwyn, C.W.

1976-01-01

The Circuit Mask Translator (CMAT) code has been developed which converts integrated circuit mask information into a circuit schematic. Logical operations, pattern recognition, and special functions are used to identify and interconnect diodes, transistors, capacitors, and resistances. The circuit topology provided by the translator is compatible with the input required for a circuit analysis program

Thermionic integrated circuits: electronics for hostile environments

International Nuclear Information System (INIS)

Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

1985-01-01

Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments

Modern TTL circuits manual

CERN Document Server

Marston, R M

2013-01-01

Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com

Circuit analysis with Multisim

CERN Document Server

Baez-Lopez, David

2011-01-01

This book is concerned with circuit simulation using National Instruments Multisim. It focuses on the use and comprehension of the working techniques for electrical and electronic circuit simulation. The first chapters are devoted to basic circuit analysis.It starts by describing in detail how to perform a DC analysis using only resistors and independent and controlled sources. Then, it introduces capacitors and inductors to make a transient analysis. In the case of transient analysis, it is possible to have an initial condition either in the capacitor voltage or in the inductor current, or bo

Widely Tunable On-Chip Microwave Circulator for Superconducting Quantum Circuits

Science.gov (United States)

Chapman, Benjamin J.; Rosenthal, Eric I.; Kerckhoff, Joseph; Moores, Bradley A.; Vale, Leila R.; Mates, J. A. B.; Hilton, Gene C.; Lalumière, Kevin; Blais, Alexandre; Lehnert, K. W.

2017-10-01

We report on the design and performance of an on-chip microwave circulator with a widely (GHz) tunable operation frequency. Nonreciprocity is created with a combination of frequency conversion and delay, and requires neither permanent magnets nor microwave bias tones, allowing on-chip integration with other superconducting circuits without the need for high-bandwidth control lines. Isolation in the device exceeds 20 dB over a bandwidth of tens of MHz, and its insertion loss is small, reaching as low as 0.9 dB at select operation frequencies. Furthermore, the device is linear with respect to input power for signal powers up to hundreds of fW (≈103 circulating photons), and the direction of circulation can be dynamically reconfigured. We demonstrate its operation at a selection of frequencies between 4 and 6 GHz.

Application specific integrated circuits and hybrid micro circuits for nuclear instrumentation

International Nuclear Information System (INIS)

Chandratre, V.B.; Sukhwani, Menka; Mukhopadhyay, P.K.; Shastrakar, R.S.; Sudheer, M.; Shedam, V.; Keni, Anubha

2009-01-01

Rapid development in semiconductor technology, sensors, detectors and requirements of high energy physics experiments as well as advances in commercially available nuclear instruments have lead to challenges for instrumentation. These challenges are met with development of Application Specific Integrated Circuits and Hybrid Micro Circuits. This paper discusses various activities in ASIC and HMC development in Bhabha Atomic Research Centre. (author)

A Fault Tolerant Integrated Circuit Memory

OpenAIRE

Barton, Anthony Francis

1980-01-01

Most commercially produced integrated circuits are incapable of tolerating manufacturing defects. The area and function of the circuits is thus limited by the probability of faults occurring within the circuit. This thesis examines techniques for using redundancy in memory circuits to provide fault tolerance and to increase storage capacity. A hierarchical memory architecture using multiple Hamming codes is introduced and analysed to determine its resistance to manufa...

Trip electrical circuit of the gyrotion

International Nuclear Information System (INIS)

Rossi, J.O.

1987-09-01

The electron cyclotron resonance heating system of INPE/LAP is shown and the trip electrical circuit of the gyrotron is described, together with its fundamental aspects. The trip electrical circuit consists basically of a series regulator circuit which regulates the output voltage level and controls the pulse width time. Besides that, a protection circuit for both tubes, regulator and gyrotron, against faults in the system. (author) [pt

Implementation of Chua's circuit using simulated inductance

Science.gov (United States)

Gopakumar, K.; Premlet, B.; Gopchandran, K. G.

2011-05-01

In this study we describe how to build an inductorless version of the classic Chua's circuit. A suitable inductor for Chua's circuit is often hard to procure. The required inductor for the circuit is designed using simple circuit elements such as resistors, capacitors and operational amplifiers. The complete circuit can be implemented by using off-the-shelf components, and it can readily be integrated on a single chip. This design of Chua's circuit allows the original dynamics to be slowed down to just a few hertz, enabling implementation of sophisticated control schemes without severe time restrictions. Another novel feature of the circuit is that losses associated with capacitors due to leakages can easily be compensated by providing negative resistance using the same setup. The chaotic behaviour of the circuit is verified by PSpice and Multisim simulation and also by experimental study on a circuit breadboard. The results give excellent agreement with each other and with the results of previous investigators.

CMOS circuit design, layout and simulation

CERN Document Server

Baker, R Jacob

2010-01-01

The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

Source-gated transistors for order-of-magnitude performance improvements in thin-film digital circuits

Science.gov (United States)

Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.

2014-03-01

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

Power system with an integrated lubrication circuit

Science.gov (United States)

Hoff, Brian D [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL; Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Lane, William H [Chillicothe, IL

2009-11-10

A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

Research of Driving Circuit in Coaxial Induction Coilgun

Directory of Open Access Journals (Sweden)

Yadong Zhang

2013-09-01

Full Text Available Power supply is crucial equipment in coaxial induction coil launcher.Configuration of the driving circuit influences the efficiency of the coil launcher directly.This paper gives a detailed analysis of the properties of the driving circuit construction based on the capacitor source. Three topologies of the driving circuit are compared including oscillation circuit, crowbar circuit and half-wave circuit. It is proved that which circuit has the better efficiency depends on the detailed parameters of the experiment, especially the crowbar resistance. Crowbar resistor regulates not only efficiency of the system, but also temperature rise of the coil. Electromagnetic force (EMF applied on the armature will be another question which influences service condition of the driving circuits. Oscillation circuit and crowbar circuit should apply to the asynchronous induction coil launcher and synchronous induction coil launcher, respectively. Half-wave circuit is seldom used in the experiment. Although efficiency of the half-wave circuit is very high, the speed of the armature is low. A simple independent half-wave circuit is suggested in this paper. Generally speaking, the comprehensive property of crowbar circuit is the most practical in the three typical circuits. Conclusions of the paper could provide guidelines for practice.

Four-terminal circuit element with photonic core

Science.gov (United States)

Sampayan, Stephen

2017-08-29

A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated based on electrical bias or control designs. The photonic core aspect of the four-terminal circuit element provides unique features that enable versatile circuit applications to either replace the semiconductor transistor-based circuit elements or semiconductor diode-based circuit elements.

High Q-factor tunable superconducting HF circuit

CERN Document Server

Vopilkin, E A; Pavlov, S A; Ponomarev, L I; Ganitsev, A Y; Zhukov, A S; Vladimirov, V V; Letyago, A G; Parshikov, V V

2001-01-01

Feasibility of constructing a high Q-factor (Q approx 10 sup 5) mechanically tunable in a wide range of frequencies (12-63 MHz) vibration circuit of HF range was considered. The tunable circuit integrates two single circuits made using YBaCuO films. The circuit frequency is tuned by changing distance X (capacity) between substrates. Potentiality of using substrates of lanthanum aluminate, neodymium gallate and strontium titanate for manufacture of single circuits was considered. Q-factor of the circuit amounted to 68000 at resonance frequency of 6.88 MHz

High Q-factor tunable superconducting HF circuit

International Nuclear Information System (INIS)

Vopilkin, E.A.; Parafin, A.E.; Pavlov, S.A.; Ponomarev, L.I.; Ganitsev, A.Yu.; Zhukov, A.S.; Vladimirov, V.V.; Letyago, A.G.; Parshikov, V.V.

2001-01-01

Feasibility of constructing a high Q-factor (Q ∼ 10 5 ) mechanically tunable in a wide range of frequencies (12-63 MHz) vibration circuit of HF range was considered. The tunable circuit integrates two single circuits made using YBaCuO films. The circuit frequency is tuned by changing distance X (capacity) between substrates. Potentiality of using substrates of lanthanum aluminate, neodymium gallate and strontium titanate for manufacture of single circuits was considered. Q-factor of the circuit amounted to 68000 at resonance frequency of 6.88 MHz [ru

Superconducting push-pull flux quantum logic circuits

International Nuclear Information System (INIS)

Murphy, J.H.; Daniel, M.R.; Przybysz, J.X.

1993-01-01

A superconducting digital logic circuit is described comprising: a first circuit branch including first and second Josephson junctions electrically connected in series with each other; means for applying a positive bias voltage to a first end of said circuit branch; means for applying a negative bias voltage to a second end of said circuit branch; means for applying a first dual polarity input voltage signal to a first node in said circuit branch; and means for extracting a first output voltage signal from said first node in said circuit branch

Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

Science.gov (United States)

Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2015-04-01

Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

AN ACCURATE MODELING OF DELAY AND SLEW METRICS FOR ON-CHIP VLSI RC INTERCONNECTS FOR RAMP INPUTS USING BURR’S DISTRIBUTION FUNCTION

Directory of Open Access Journals (Sweden)

Rajib Kar

2010-09-01

Full Text Available This work presents an accurate and efficient model to compute the delay and slew metric of on-chip interconnect of high speed CMOS circuits foe ramp input. Our metric assumption is based on the Burr’s Distribution function. The Burr’s distribution is used to characterize the normalized homogeneous portion of the step response. We used the PERI (Probability distribution function Extension for Ramp Inputs technique that extends delay metrics and slew metric for step inputs to the more general and realistic non-step inputs. The accuracy of our models is justified with the results compared with that of SPICE simulations.

Short-circuit impedance measurement

DEFF Research Database (Denmark)

Pedersen, Knud Ole Helgesen; Nielsen, Arne Hejde; Poulsen, Niels Kjølstad

2003-01-01

Methods for estimating the short-circuit impedance in the power grid are investigated for various voltage levels and situations. The short-circuit impedance is measured, preferably from naturally occurring load changes in the grid, and it is shown that such a measurement system faces different...

Radiation-sensitive switching circuits

Energy Technology Data Exchange (ETDEWEB)

Moore, J.H.; Cockshott, C.P.

1976-03-16

A radiation-sensitive switching circuit includes a light emitting diode which from time to time illuminates a photo-transistor, the photo-transistor serving when its output reaches a predetermined value to operate a trigger circuit. In order to allow for aging of the components, the current flow through the diode is increased when the output from the transistor falls below a known level. Conveniently, this is achieved by having a transistor in parallel with the diode, and turning the transistor off when the output from the phototransistor becomes too low. The circuit is designed to control the ignition system in an automobile engine.

What's new about generator circuit breakers

International Nuclear Information System (INIS)

Kolarik, P.L.

1979-01-01

The need for updating ANSI C37 Standards for AC high-voltage circuit breakers has become necessary because of the increased interest in power circuit breakers for generator application. These circuit breakers, which have continuous current ratings and rated short-circuit currents that are much higher than those presently covered by existing C37 Standards, take on added importance because they are being installed in critical AC power supplies at nuclear power stations

49 CFR 236.786 - Principle, closed circuit.

Science.gov (United States)

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Principle, closed circuit. 236.786 Section 236.786 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL RAILROAD ADMINISTRATION... Principle, closed circuit. The principle of circuit design where a normally energized electric circuit which...

INTEGRATED SENSOR EVALUATION CIRCUIT AND METHOD FOR OPERATING SAID CIRCUIT

OpenAIRE

Krüger, Jens; Gausa, Dominik

2015-01-01

WO15090426A1 Sensor evaluation device and method for operating said device Integrated sensor evaluation circuit for evaluating a sensor signal (14) received from a sensor (12), having a first connection (28a) for connection to the sensor and a second connection (28b) for connection to the sensor. The integrated sensor evaluation circuit comprises a configuration data memory (16) for storing configuration data which describe signal properties of a plurality of sensor control signals (26a-c). T...

Circuit card failures and industry mitigation strategy

Energy Technology Data Exchange (ETDEWEB)

Mondal, U. [Candu Owners Group, Toronto, Ontario (Canada)

2012-07-01

In recent years the nuclear industry has experienced an increase in circuit card failures due to ageing of components, inadequate Preventive Maintenance (PM), lack of effective circuit card health monitoring, etc. Circuit card failures have caused loss of critical equipment, e.g., electro hydraulic governors, Safety Systems, resulting in loss of function and in some cases loss of generation. INPO completed a root cause analysis of 40 Reactor Trips/Scrams in US reactors and has recommended several actions to mitigate Circuit Card failures. Obsolescence of discrete components has posed many challenges in conducting effective preventative maintenance on circuit cards. In many cases, repairs have resulted in installation of components that compromise performance of the circuit cards. Improper termination and worn edge connectors have caused intermittent contacts contributing to circuit card failures. Traditionally, little attention is paid to relay functions and preventative maintenance of relay. Relays contribute significantly to circuit card failures and have dominated loss of generation across the power industry. The INPO study recommended a number of actions to mitigate circuit card failures, such as; identification of critical components and single point vulnerabilities; strategic preventative maintenance; protection of circuit boards against electrostatic discharge; limiting power cycles; performing an effective burn-in prior to commissioning of the circuit cards; monitoring performance of DC power supplies; limiting cabinet temperatures; managing of component aging/degradation mechanism, etc. A subcommittee has been set up under INPO sponsorship to understand the causes of circuit card failure and to develop an effective mitigation strategy. (author)

Current-mode minimax circuit

NARCIS (Netherlands)

Wassenaar, R.F.

1992-01-01

The minimum-maximum (minimax) circuit selects the minimum and maximum of two input currents. Four transistors in matched pairs are operated in the saturation region. Because the behavior of the circuit is based on matched devices and is independent of the relationship between the drain current and

A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

Science.gov (United States)

DuMonthier, Jeffrey; Suarez, George

2013-01-01

new process specific device models. The system has been used in the design of time to digital converters for laser ranging and time-of-flight mass spectrometry to optimize analog, mixed signal and digital circuits such as charge sensitive amplifiers, comparators, delay elements, radiation tolerant dual interlocked (DICE) flip-flops and two of three voter gates.

Short circuit in deep brain stimulation.

Science.gov (United States)

Samura, Kazuhiro; Miyagi, Yasushi; Okamoto, Tsuyoshi; Hayami, Takehito; Kishimoto, Junji; Katano, Mitsuo; Kamikaseda, Kazufumi

2012-11-01

The authors undertook this study to investigate the incidence, cause, and clinical influence of short circuits in patients treated with deep brain stimulation (DBS). After the incidental identification of a short circuit during routine follow-up, the authors initiated a policy at their institution of routinely evaluating both therapeutic impedance and system impendence at every outpatient DBS follow-up visit, irrespective of the presence of symptoms suggesting possible system malfunction. This study represents a report of their findings after 1 year of this policy. Implanted DBS leads exhibiting short circuits were identified in 7 patients (8.9% of the patients seen for outpatient follow-up examinations during the 12-month study period). The mean duration from DBS lead implantation to the discovery of the short circuit was 64.7 months. The symptoms revealing short circuits included the wearing off of therapeutic effect, apraxia of eyelid opening, or dysarthria in 6 patients with Parkinson disease (PD), and dystonia deterioration in 1 patient with generalized dystonia. All DBS leads with short circuits had been anchored to the cranium using titanium miniplates. Altering electrode settings resulted in clinical improvement in the 2 PD cases in which patients had specific symptoms of short circuits (2.5%) but not in the other 4 cases. The patient with dystonia underwent repositioning and replacement of a lead because the previous lead was located too anteriorly, but did not experience symptom improvement. In contrast to the sudden loss of clinical efficacy of DBS caused by an open circuit, short circuits may arise due to a gradual decrease in impedance, causing the insidious development of neurological symptoms via limited or extended potential fields as well as shortened battery longevity. The incidence of short circuits in DBS may be higher than previously thought, especially in cases in which DBS leads are anchored with miniplates. The circuit impedance of DBS

Fuzzy delay model based fault simulator for crosstalk delay fault test ...

Indian Academy of Sciences (India)

In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design trends move towards nanometer technologies, more number of new parameters affects the delay of the component. Fuzzy delay models are ideal for modelling the uncertainty found in the design and manufacturing steps.

Spectral Purity Enhancement via Polyphase Multipath Circuits

NARCIS (Netherlands)

Mensink, E.; Klumperink, Eric A.M.; Nauta, Bram

2004-01-01

The central question of this paper is: can we enhance the spectral purity of nonlinear circuits by using polyphase multipath circuits? The basic idea behind polyphase multipath circuits is to split the nonlinear circuits into two or more paths and exploit phase differences between these paths to

IMPORTANT NOTICE: Cancellation of shuttle Circuit 3

CERN Multimedia

2013-01-01

Circuit 3 of the CERN Shuttle Service (Point 5), which has served CMS since the start of LS1, will be cancelled with effect from Tuesday 16 April. This decision has been taken in consultation with CMS, as the circuit was seldom used.   In response to increasing demand for Circuit 1 - Meyrin and feedback from passengers, the two Circuit 3 journeys will be switched to Circuit 1 – Meyrin (see new timetable below): Mornings: Four journeys instead of three. Circuit 1 now starts at 8:10 (instead of 8:19 a.m.) and runs until 9:27 a.m. (instead of 9:16 a.m.). Lunchtimes: Five journeys in place between 12:10 p.m. and 1:47 p.m. Evenings: Circuit starts at 5:23 p.m. (instead of 5:03 p.m.) and ends at 6:20 p.m. at Building 33. Please note that the circuit will depart from Building 13 instead of Building 33.  

Developing a Domain Model for Relay Circuits

DEFF Research Database (Denmark)

Haxthausen, Anne Elisabeth

2009-01-01

In this paper we stepwise develop a domain model for relay circuits as used in railway control systems. First we provide an abstract, property-oriented model of networks consisting of components that can be glued together with connectors. This model is strongly inspired by a network model...... for railways madeby Bjørner et.al., however our model is more general: the components can be of any kind and can later be refined to e.g. railway components or circuit components. Then we show how the abstract network model can be refined into an explicit model for relay circuits. The circuit model describes...... the statics as well as the dynamics of relay circuits, i.e. how a relay circuit can be composed legally from electrical components as well as how the components may change state over time. Finally the circuit model is transformed into an executable model, and we show how a concrete circuit can be defined...

Notes on basis band-pass circuits; Notes sur les circuits de base passe-bande

Energy Technology Data Exchange (ETDEWEB)

Ailloud, J [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

1959-07-01

Resistor load amplifier stages, basic band-pass RC networks, conventional single-tuned circuits, have the same transfer function. Common properties and differences because diverse magnitude of parameters with proposed problems are exposed. Next the case of several cascaded stages (or networks) is examined when there is no reaction ones to another. (author) [French] Les etages amplificateurs a resistances, les circuits passe-bande RC elementaires, le circuit resonnant classique possedent la meme fonction de transfert. On fait ressortir les proprietes communes et les differences de comportement dues aux ordres de grandeur qu'il est possible de donner aux parametres en fonction des problemes a resoudre. On examine ensuite le cas de plusieurs etages (ou de plusieurs circuits) en cascade lorsqu'ils ne reagissent pas les uns sur les autres. (auteur)

Delay dynamics of neuromorphic optoelectronic nanoscale resonators: Perspectives and applications

Science.gov (United States)

Romeira, Bruno; Figueiredo, José M. L.; Javaloyes, Julien

2017-11-01

With the recent exponential growth of applications using artificial intelligence (AI), the development of efficient and ultrafast brain-like (neuromorphic) systems is crucial for future information and communication technologies. While the implementation of AI systems using computer algorithms of neural networks is emerging rapidly, scientists are just taking the very first steps in the development of the hardware elements of an artificial brain, specifically neuromorphic microchips. In this review article, we present the current state of the art of neuromorphic photonic circuits based on solid-state optoelectronic oscillators formed by nanoscale double barrier quantum well resonant tunneling diodes. We address, both experimentally and theoretically, the key dynamic properties of recently developed artificial solid-state neuron microchips with delayed perturbations and describe their role in the study of neural activity and regenerative memory. This review covers our recent research work on excitable and delay dynamic characteristics of both single and autaptic (delayed) artificial neurons including all-or-none response, spike-based data encoding, storage, signal regeneration and signal healing. Furthermore, the neural responses of these neuromorphic microchips display all the signatures of extended spatio-temporal localized structures (LSs) of light, which are reviewed here in detail. By taking advantage of the dissipative nature of LSs, we demonstrate potential applications in optical data reconfiguration and clock and timing at high-speeds and with short transients. The results reviewed in this article are a key enabler for the development of high-performance optoelectronic devices in future high-speed brain-inspired optical memories and neuromorphic computing.

Dryout delay in loss-of-coolant incidents in nuclear power plants

International Nuclear Information System (INIS)

Belda, W.

1975-01-01

The maximum credible accident (MCA) as a result of a fault in the system is assumed to be the rupture of a pipe in the primary circuit. During the outflow process following the rupture - called blowdown - it is possible that the internals of a reactor pressure vessel are exposed to extreme mechanical and thermal stresses. The fuel rods in the core, the Zircaloy cladding tubes of which can be heated up by lack of coolant to inadmissibly high temperatures, are particularly at risk. In case of the cladding tubes being damaged, radioactive substances are released. If they escape from the outer containment, this would lead to pressures on the immediate and more distant vicinity of the nuclear pover plant. In order to eliminate the factors of uncertainty when calculating the overall blowdown process in advance, it is necessary to have a relationship valid for the instationary circumstances to work out the burnout delay which is of decisive importance for the post-incident cooling phase of the reactor. The aim of this investigation, therefore, is to develop, with the aid of a suitable model, a method of calculating the burnout delay. (orig./TK) [de

On the cost/delay tradeoff of wireless delay tolerant geographic routing

OpenAIRE

Tasiopoulos, Argyrios; Tsiaras, Christos; Toumpis, Stavros

2012-01-01

In Delay Tolerant Networks (DTNs), there is a fundamental tradeoff between the aggregate transport cost of a packet and the delay in its delivery. We study this tradeoff in the context of geographical routing in wireless DTNs.We ?rst specify the optimal cost/delay tradeoff, i.e., the tradeoff under optimal network operation, using a dynamic network construction termed the Cost/Delay Evolving Graph (C/DEG) and the Optimal Cost/Delay Curve (OC/DC), a function that gives the minimum possible agg...

Circuit for correlation spectroscopy of nuclear magnetic resonance

International Nuclear Information System (INIS)

Halamek, J.; Panek, P.

1985-01-01

The connection consists of a control circuit connected to a generator with two outputs. The first output is connected to the first keying circuit while the second output is connected to a transmitter. The transmitter output is connected via the second keying circuit, the spectrometer probe and the receiver with a mixer connected to the first keying circuit. The second keying circuit is connected via a keying control circuit to the control circuit. The resulting low-frequency signal represents the mixer output. (E.S.)

Principles of transistor circuits introduction to the design of amplifiers, receivers and digital circuits

CERN Document Server

Amos, S W

2013-01-01

Principles of Transistor Circuits: Sixth Edition discusses the principles, concepts, and practices involved integrated circuits. The current edition includes up-to-date circuits, the section on thyristors has been revised to give more information on modern types, and dated information has been eliminated. The book covers related topics such as semiconductors and junction diodes; the principles behind transistors; and common amplifiers. The book also covers bias and DC stabilization; large-signal and small-signal AF amplifiers; DC and pulse amplifiers; sinusoidal oscillators; pulse and sawtooth

IE Information Notice No. 85-64: BBC Brown Boveri low-voltage K-line circuit breakers, with deficient overcurrent trip devices models OD-4 and 5

International Nuclear Information System (INIS)

Jordan, E.L.

1992-01-01

On May 13, 1985, BBC Brown Boveri Inc. (BBC) made a 10 CFR Part 21 report to the NRC concerning a deficiency in the Models OD-4 and OD-5 overcurrent trip devices installed on K-line circuit breakers. The affected breakers were manufactured by BBC from October 1983 to March 1985 and may have incorrect short time delay band levers (links) installed in electromechanical overcurrent trip device models OD-4 and OD-5. The incorrect link could limit the travel of the short time armature and cause the short time element to be inoperative in the maximum (MAX) band. The May 13, 1985, report recommended that all K-line circuit breakers with the OD-4 and OD-5 overcurrent trip devices and any spare OD-4 and OD-5 overcurrent trip devices that were manufactured between October 1983 and March 1985, be inspected for an incorrect short time delay band link. Licensees known by BBC to have purchased K-line breakers or spare OD-4 or OD-5 overcurrent trip devices were notified of the possible defect and instructions provided for their inspection. Enclosed is a list of utilities and related facilities that were notified by BBC. However, BBC advised the NRC that there is a possibility that other utilities could be using K-line circuit breakers with the suspect OD-4 and OD-5 overcurrent trip devices. Therefore, all licensees are being notified of this possible defect

Global exponential stability and periodicity of reaction-diffusion recurrent neural networks with distributed delays and Dirichlet boundary conditions

International Nuclear Information System (INIS)

Lu Junguo; Lu Linji

2009-01-01

In this paper, global exponential stability and periodicity of a class of reaction-diffusion recurrent neural networks with distributed delays and Dirichlet boundary conditions are studied by constructing suitable Lyapunov functionals and utilizing some inequality techniques. We first prove global exponential convergence to 0 of the difference between any two solutions of the original neural networks, the existence and uniqueness of equilibrium is the direct results of this procedure. This approach is different from the usually used one where the existence, uniqueness of equilibrium and stability are proved in two separate steps. Secondly, we prove periodicity. Sufficient conditions ensuring the existence, uniqueness, and global exponential stability of the equilibrium and periodic solution are given. These conditions are easy to verify and our results play an important role in the design and application of globally exponentially stable neural circuits and periodic oscillatory neural circuits.

Leveraging delay discounting for health: Can time delays influence food choice?

Science.gov (United States)

Appelhans, Bradley M; French, Simone A; Olinger, Tamara; Bogucki, Michael; Janssen, Imke; Avery-Mamer, Elizabeth F; Powell, Lisa M

2018-03-15

Delay discounting, the tendency to choose smaller immediate rewards over larger delayed rewards, is theorized to promote consumption of immediately rewarding but unhealthy foods at the expense of long-term weight maintenance and nutritional health. An untested implication of delay discounting models of decision-making is that selectively delaying access to less healthy foods may promote selection of healthier (immediately available) alternatives, even if they may be less desirable. The current study tested this hypothesis by measuring healthy versus regular vending machine snack purchasing before and during the implementation of a 25-s time delay on the delivery of regular snacks. Purchasing was also examined under a $0.25 discount on healthy snacks, a $0.25 tax on regular snacks, and the combination of both pricing interventions with the 25-s time delay. Across 32,019 vending sales from three separate vending locations, the 25-s time delay increased healthy snack purchasing from 40.1% to 42.5%, which was comparable to the impact of a $0.25 discount (43.0%). Combining the delay and the discount had a roughly additive effect (46.0%). However, the strongest effects were seen under the $0.25 tax on regular snacks (53.7%) and the combination of the delay and the tax (50.2%). Intervention effects varied substantially between vending locations. Importantly, time delays did not harm overall vending sales or revenue, which is relevant to the real-world feasibility of this intervention. More investigation is needed to better understand how the impact of time delays on food choice varies across populations, evaluate the effects of time delays on beverage vending choices, and extend this approach to food choices in contexts other than vending machines. ClinicalTrials.gov, NCT02359916. Copyright © 2018 Elsevier Ltd. All rights reserved.

Design of analog integrated circuits and systems

CERN Document Server

Laker, Kenneth R

1994-01-01

This text is designed for senior or graduate level courses in analog integrated circuits or design of analog integrated circuits. This book combines consideration of CMOS and bipolar circuits into a unified treatment. Also included are CMOS-bipolar circuits made possible by BiCMOS technology. The text progresses from MOS and bipolar device modelling to simple one and two transistor building block circuits. The final two chapters present a unified coverage of sample-data and continuous-time signal processing systems.

Short-circuited coil in a solenoid circuit of a pulse magnetic field

International Nuclear Information System (INIS)

Kivshik, A.F.; Dubrovin, V.Yu.

1976-01-01

A short-circuited coil at the end of a long pulse solenoid attenuates the dissipation field by 3-5 times. A plug-configuration field is set up in the middle portion of the pulse solenoid incorporating the short-circuited coils. Shunting of the coils with the induction current by resistor Rsub(shunt) provides for the adjustment of the plug ratio γ

Model Order Reduction for Electronic Circuits:

DEFF Research Database (Denmark)

Hjorth, Poul G.; Shontz, Suzanne

Electronic circuits are ubiquitous; they are used in numerous industries including: the semiconductor, communication, robotics, auto, and music industries (among many others). As products become more and more complicated, their electronic circuits also grow in size and complexity. This increased...... in the semiconductor industry. Circuit simulation proceeds by using Maxwell’s equations to create a mathematical model of the circuit. The boundary element method is then used to discretize the equations, and the variational form of the equations are then solved on the graph network....

Grounding and shielding circuits and interference

CERN Document Server

Morrison, Ralph

2016-01-01

Applies basic field behavior in circuit design and demonstrates how it relates to grounding and shielding requirements and techniques in circuit design This book connects the fundamentals of electromagnetic theory to the problems of interference in all types of electronic design. The text covers power distribution in facilities, mixing of analog and digital circuitry, circuit board layout at high clock rates, and meeting radiation and susceptibility standards. The author examines the grounding and shielding requirements and techniques in circuit design and applies basic physics to circuit behavior. The sixth edition of this book has been updated with new material added throughout the chapters where appropriate. The presentation of the book has also been rearranged in order to reflect the current trends in the field.

Circuit QED lattices: Towards quantum simulation with superconducting circuits

Energy Technology Data Exchange (ETDEWEB)

Schmidt, Sebastian [Institute for Theoretical Physics, ETH Zurich, 8093, Zurich (Switzerland); Koch, Jens [Department of Physics and Astronomy, Northwestern University, Evanston, IL, 60208 (United States)

2013-06-15

The Jaynes-Cummings model describes the coupling between photons and a single two-level atom in a simplified representation of light-matter interactions. In circuit QED, this model is implemented by combining microwave resonators and superconducting qubits on a microchip with unprecedented experimental control. Arranging qubits and resonators in the form of a lattice realizes a new kind of Hubbard model, the Jaynes-Cummings-Hubbard model, in which the elementary excitations are polariton quasi-particles. Due to the genuine openness of photonic systems, circuit QED lattices offer the possibility to study the intricate interplay of collective behavior, strong correlations and non-equilibrium physics. Thus, turning circuit QED into an architecture for quantum simulation, i.e., using a well-controlled system to mimic the intricate quantum behavior of another system too daunting for a theorist to tackle head-on, is an exciting idea which has served as theorists' playground for a while and is now also starting to catch on in experiments. This review gives a summary of the most recent theoretical proposals and experimental efforts. (copyright 2013 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Compact sub-nanosecond pulse seed source with diode laser driven by a high-speed circuit

Science.gov (United States)

Wang, Xiaoqian; Wang, Bo; Wang, Junhua; Cheng, Wenyong

2018-06-01

A compact sub-nanosecond pulse seed source with 1550 nm diode laser (DL) was obtained by employing a high-speed circuit. The circuit mainly consisted of a short pulse generator and a short pulse driver. The short pulse generator, making up of a complex programmable logic device (CPLD), a level translator, two programmable delay chips and an AND gate chip, output a triggering signal to control metal-oxide-semiconductor field-effect transistor (MOSFET) switch of the short pulse driver. The MOSFET switch with fast rising time and falling time both shorter than 1 ns drove the DL to emit short optical pulses. Performances of the pulse seed source were tested. The results showed that continuously adjustable repetition frequency ranging from 500 kHz to 100 MHz and pulse duration in the range of 538 ps to 10 ns were obtained, respectively. 537 μW output was obtained at the highest repetition frequency of 100 MHz with the shortest pulse duration of 538 ps. These seed pulses were injected into an fiber amplifier, and no optical pulse distortions were found.

Logarithmic current-measuring transistor circuits

DEFF Research Database (Denmark)

Højberg, Kristian Søe

1967-01-01

Describes two transistorized circuits for the logarithmic measurement of small currents suitable for nuclear reactor instrumentation. The logarithmic element is applied in the feedback path of an amplifier, and only one dual transistor is used as logarithmic diode and temperature compensating...... transistor. A simple one-amplifier circuit is compared with a two-amplifier system. The circuits presented have been developed in connexion with an amplifier using a dual m.o.s. transistor input stage with diode-protected gates....

Automatic design of digital synthetic gene circuits.

Directory of Open Access Journals (Sweden)

Mario A Marchisio

2011-02-01

Full Text Available De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.

Representing delayed force feedback as a combination of current and delayed states.

Science.gov (United States)

Avraham, Guy; Mawase, Firas; Karniel, Amir; Shmuelof, Lior; Donchin, Opher; Mussa-Ivaldi, Ferdinando A; Nisky, Ilana

2017-10-01

To adapt to deterministic force perturbations that depend on the current state of the hand, internal representations are formed to capture the relationships between forces experienced and motion. However, information from multiple modalities travels at different rates, resulting in intermodal delays that require compensation for these internal representations to develop. To understand how these delays are represented by the brain, we presented participants with delayed velocity-dependent force fields, i.e., forces that depend on hand velocity either 70 or 100 ms beforehand. We probed the internal representation of these delayed forces by examining the forces the participants applied to cope with the perturbations. The findings showed that for both delayed forces, the best model of internal representation consisted of a delayed velocity and current position and velocity. We show that participants relied initially on the current state, but with adaptation, the contribution of the delayed representation to adaptation increased. After adaptation, when the participants were asked to make movements with a higher velocity for which they had not previously experienced with the delayed force field, they applied forces that were consistent with current position and velocity as well as delayed velocity representations. This suggests that the sensorimotor system represents delayed force feedback using current and delayed state information and that it uses this representation when generalizing to faster movements. NEW & NOTEWORTHY The brain compensates for forces in the body and the environment to control movements, but it is unclear how it does so given the inherent delays in information transmission and processing. We examined how participants cope with delayed forces that depend on their arm velocity 70 or 100 ms beforehand. After adaptation, participants applied opposing forces that revealed a partially correct representation of the perturbation using the current and the

49 CFR 236.721 - Circuit, control.

Science.gov (United States)

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Circuit, control. 236.721 Section 236.721..., MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Definitions § 236.721 Circuit, control. An electrical circuit between a source of electric energy and a device which it operates. ...

Development of high speed integrated circuit for very high resolution timing measurements

International Nuclear Information System (INIS)

Mester, Christian

2009-10-01

A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described. The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40 MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption. (orig.)

Development of high speed integrated circuit for very high resolution timing measurements

Energy Technology Data Exchange (ETDEWEB)

Mester, Christian

2009-10-15

A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described. The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40 MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption. (orig.)

Tester Detects Steady-Short Or Intermittent-Open Circuits

Science.gov (United States)

Anderson, Bobby L.

1990-01-01

Momentary open circuits or steady short circuits trigger buzzer. Simple, portable, lightweight testing circuit sounds long-duration alarm when it detects steady short circuit or momentary open circuit in coaxial cable or other two-conductor transmission line. Tester sensitive to discontinuities lasting 10 microseconds or longer. Used extensively for detecting intermittent open shorts in accelerometer and extensometer cables. Also used as ordinary buzzer-type continuity checker to detect steady short or open circuits.

Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

Directory of Open Access Journals (Sweden)

Mohammed Darmi

2017-10-01

Full Text Available As we increasingly use advanced technology nodes to design integrated circuits (ICs, physical designers and electronic design automation (EDA providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR. An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics’ physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS and total negative slack (TNS improved up to 13% and 56%, respectively, compared to the baseline flow.

Detecting short circuits during assembly

Science.gov (United States)

Deboo, G. J.

1980-01-01

Detector circuit identifies shorts between bus bars of electronic equipment being wired. Detector sounds alarm and indicates which planes are shorted. Power and ground bus bars are scanned continuously until short circuit occurs.

Asymptotic Delay Analysis for Cross-Layer Delay-Based Routing in Ad Hoc Networks

Directory of Open Access Journals (Sweden)

Philippe Jacquet

2007-01-01

Full Text Available This paper addresses the problem of the evaluation of the delay distribution via analytical means in IEEE 802.11 wireless ad hoc networks. We show that the asymptotic delay distribution can be expressed as a power law. Based on the latter result, we present a cross-layer delay estimation protocol and we derive new delay-distribution-based routing algorithms, which are well adapted to the QoS requirements of real-time multimedia applications. In fact, multimedia services are not sensitive to average delays, but rather to the asymptotic delay distributions. Indeed, video streaming applications drop frames when they are received beyond a delay threshold, determined by the buffer size. Although delay-distribution-based routing is an NP-hard problem, we show that it can be solved in polynomial time when the delay threshold is large, because of the asymptotic power law distribution of the link delays.

Radio-frequency integrated-circuit engineering

CERN Document Server

Nguyen, Cam

2015-01-01

Radio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC's using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. Provide

BR-5 primary circuit decontamination

International Nuclear Information System (INIS)

Efimov, I.A.; Nikulin, M.P.; Smirnov-Averin, A.P.; Tymosh, B.S.; Shereshkov, V.S.

1976-01-01

Results and methodology of steam-water and acid decontamination of the primary coolant circuit SBR-5 reactor in 1971 are discussed. Regeneration process in a cold trap of the primary coolant circuit is discussed

Ignition circuit for combustion engines

Energy Technology Data Exchange (ETDEWEB)

Becker, H W

1977-05-26

The invention refers to the ignition circuit for combustion engines, which are battery fed. The circuit contains a transistor and an oscillator to produce an output voltage on the secondary winding of an output transformer to supply an ignition current. The plant is controlled by an interrupter. The purpose of the invention is to form such a circuit that improved sparks for ignition are produced, on the one hand, and that on the other hand, the plant can continue to function after loss of the oscillator. The problem is solved by the battery and the secondary winding of the output transformers of the oscillator are connected via a rectifier circuit to produce a resultant total voltage with the ignition coil from the battery voltage and the rectified pulsating oscillator output.

Dynamic theory for the mesoscopic electric circuit

International Nuclear Information System (INIS)

Chen Bin; Shen Xiaojuan; Li Youquan; Sun LiLy; Yin Zhujian

2005-01-01

The quantum theory for mesoscopic electric circuit with charge discreteness is briefly described. The minibands of quasienergy in LC design mesoscopic electric circuit have been found. In the mesoscopic 'pure' inductance design circuit, just like in the mesoscopic metallic rings, the quantum dynamic characteristics have been obtained explicitly. In the 'pure' capacity design circuit, the Coulomb blockade had also been addressed

Memristor-based nanoelectronic computing circuits and architectures

CERN Document Server

Vourkas, Ioannis

2016-01-01

This book considers the design and development of nanoelectronic computing circuits, systems and architectures focusing particularly on memristors, which represent one of today’s latest technology breakthroughs in nanoelectronics. The book studies, explores, and addresses the related challenges and proposes solutions for the smooth transition from conventional circuit technologies to emerging computing memristive nanotechnologies. Its content spans from fundamental device modeling to emerging storage system architectures and novel circuit design methodologies, targeting advanced non-conventional analog/digital massively parallel computational structures. Several new results on memristor modeling, memristive interconnections, logic circuit design, memory circuit architectures, computer arithmetic systems, simulation software tools, and applications of memristors in computing are presented. High-density memristive data storage combined with memristive circuit-design paradigms and computational tools applied t...

High-precision analog circuit technology for power supply integrated circuits; Dengen IC yo koseido anarogu kairo gijutsu

Energy Technology Data Exchange (ETDEWEB)

Nakamori, A.; Suzuki, T.; Mizoe, K. [Fuji Electric Corporate Research and Development,Ltd., Kanagawa (Japan)

2000-08-10

With the recent rapid spread of portable electronic appliances, specification requirements such as compact power supply and long operation with batteries have become severer. Power supply ICs (integrated circuits) are required to reduce power consumption in the circuit and perform high-precision control. To meet these requirements, Fuji Electric develops high-precision CMOS (complementary metal-oxide semiconductor) analog technology. This paper describes three analog circuit technologies of a voltage reference, an operational amplifier and a comparator as circuit components particularly important for the precision of power supply ICs. (author)

Delayed fission

Energy Technology Data Exchange (ETDEWEB)

Hatsukawa, Yuichi [Japan Atomic Energy Research Inst., Tokai, Ibaraki (Japan). Tokai Research Establishment

1997-07-01

Delayed fission is a nuclear decay process that couples {beta} decay and fission. In the delayed fission process, a parent nucleus undergoes {beta} decay and thereby populates excited states in the daughter. If these states are of energies comparable to or greater than the fission barrier of the daughter, then fission may compete with other decay modes of the excited states in the daughter. In this paper, mechanism and some experiments of the delayed fission will be discussed. (author)

SEMICONDUCTOR INTEGRATED CIRCUITS: A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth

Science.gov (United States)

Tao, Tong; Baoyong, Chi; Ziqiang, Wang; Ying, Zhang; Hanjun, Jiang; Zhihua, Wang

2010-05-01

A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 μm CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

The LMT circuit and SPICE

DEFF Research Database (Denmark)

Lindberg, Erik; Murali, K.; Tamacevicius, Arunas

2006-01-01

The state equations of the LMT circuit are modeled as a dedicated analogue computer circuit and solved by means of PSpice. The nonlinear part of the system is studied. Problems with the PSpice program are presented....

The Maplin electronic circuits handbook

CERN Document Server

Tooley, Michael

1990-01-01

The Maplin Electronic Circuits Handbook provides pertinent data, formula, explanation, practical guidance, theory and practical guidance in the design, testing, and construction of electronic circuits. This book discusses the developments in electronics technology techniques.Organized into 11 chapters, this book begins with an overview of the common types of passive component. This text then provides the reader with sufficient information to make a correct selection of passive components for use in the circuits. Other chapters consider the various types of the most commonly used semiconductor

Hyperchaotic circuit with damped harmonic oscillators

DEFF Research Database (Denmark)

Lindberg, Erik; Murali, K.; Tamasevicius, A.

2001-01-01

A simple fourth-order hyperchaotic circuit with damped harmonic oscillators is described. ANP3 and PSpice simulations including an eigenvalue study of the linearized Jacobian are presented together with a hardware implementation. The circuit contains two inductors with series resistance, two ideal...... capacitors and one nonlinear active conductor. The Lyapunov exponents are presented to confirm the hyperchaotic nature of the oscillations of the circuit. The nonlinear conductor is realized with a diode. A negative impedance converter and a linear resistor. The performance of the circuit is investigated...... by means of numerical integration of the appropriate differential equations....

Resistor Combinations for Parallel Circuits.

Science.gov (United States)

McTernan, James P.

1978-01-01

To help simplify both teaching and learning of parallel circuits, a high school electricity/electronics teacher presents and illustrates the use of tables of values for parallel resistive circuits in which total resistances are whole numbers. (MF)

Single-event transients (SET) in analog circuits

International Nuclear Information System (INIS)

Chen Panxun; Zhou Kaiming

2006-01-01

A new phenomenon of single- event upset is introduced. The transient signal is produced in the output of analog circuits after a heavy ion strikes. The transient upset can influence the circuit connected with the output of analog circuits. For example, the output of operational amplifier can be connected with the input of a digital counter, and the pulse of sufficiently high transient output induced by an ion can increase counts of the counter. On the other hand, the transient voltage signal at the output of analog circuits can change the stage of other circuits. (authors)

On equivalent resistance of electrical circuits

Science.gov (United States)

Kagan, Mikhail

2015-01-01

While the standard (introductory physics) way of computing the equivalent resistance of nontrivial electrical circuits is based on Kirchhoff's rules, there is a mathematically and conceptually simpler approach, called the method of nodal potentials, whose basic variables are the values of the electric potential at the circuit's nodes. In this paper, we review the method of nodal potentials and illustrate it using the Wheatstone bridge as an example. We then derive a closed-form expression for the equivalent resistance of a generic circuit, which we apply to a few sample circuits. The result unveils a curious interplay between electrical circuits, matrix algebra, and graph theory and its applications to computer science. The paper is written at a level accessible by undergraduate students who are familiar with matrix arithmetic. Additional proofs and technical details are provided in appendices.

Canonical cortical circuits: current evidence and theoretical implications

Directory of Open Access Journals (Sweden)

Capone F

2016-04-01

Full Text Available Fioravante Capone,1,2 Matteo Paolucci,1,2 Federica Assenza,1,2 Nicoletta Brunelli,1,2 Lorenzo Ricci,1,2 Lucia Florio,1,2 Vincenzo Di Lazzaro1,2 1Unit of Neurology, Neurophysiology, Neurobiology, Department of Medicine, Università Campus Bio-Medico di Roma, Rome, Italy; 2Fondazione Alberto Sordi – Research Institute for Aging, Rome, ItalyAbstract: Neurophysiological and neuroanatomical studies have found that the same basic structural and functional organization of neuronal circuits exists throughout the cortex. This kind of cortical organization, termed canonical circuit, has been functionally demonstrated primarily by studies involving visual striate cortex, and then, the concept has been extended to different cortical areas. In brief, the canonical circuit is composed of superficial pyramidal neurons of layers II/III receiving different inputs and deep pyramidal neurons of layer V that are responsible for cortex output. Superficial and deep pyramidal neurons are reciprocally connected, and inhibitory interneurons participate in modulating the activity of the circuit. The main intuition of this model is that the entire cortical network could be modeled as the repetition of relatively simple modules composed of relatively few types of excitatory and inhibitory, highly interconnected neurons. We will review the origin and the application of the canonical cortical circuit model in the six sections of this paper. The first section (The origins of the concept of canonical circuit: the cat visual cortex reviews the experiments performed in the cat visual cortex, from the origin of the concept of canonical circuit to the most recent developments in the modelization of cortex. The second (The canonical circuit in neocortex and third (Toward a canonical circuit in agranular cortex sections try to extend the concept of canonical circuit to other cortical areas, providing some significant examples of circuit functioning in different cytoarchitectonic

Protection of toroidal field coils using multiple circuits

International Nuclear Information System (INIS)

Thome, R.J.; Langton, W.G.; Mann, W.R.; Pillsbury, R.D.; Tarrh, J.M.

1983-01-01

The protection of toroidal field (TF) coils using multiple circuits is described. The discharge of a single-circuit TF system is given for purposes of definition. Two-circuit TF systems are analyzed and the results presented analytically and graphically. Induced currents, maximum discharge voltages, and discharge time constants are compared to the single-circuit system. Three-circuit TF systems are analyzed. In addition to induced currents, maximum discharge voltages, and time constants, several different discharge scenarios are included. The impacts of having discharge rates versus final maximum coil temperatures as requirements are examined. The out-of-plane forces which occur in the three-circuit system are analyzed using an approximate model. The analysis of multiplecircuit TF systems is briefly described and results for a Toroidal Fusion Core Experiment (TFCX) scale device are given based on computer analysis. The advantages and disadvantages of using multiple-circuit systems are summarized and discussed. The primary disadvantages of multiple circuits are the increased circuit complexity and potential for out-of-plane forces. These are offset by the substantial reduction in maximum discharge voltages, as well as other design options which become available when using multiple circuits

Logic circuits from zero forcing.

Science.gov (United States)

Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael

We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

Discharge quenching circuit for counters

International Nuclear Information System (INIS)

Karasik, A.S.

1982-01-01

A circuit for quenching discharges in gas-discharge detectors with working voltage of 3-5 kV based on transistors operating in the avalanche mode is described. The quenching circuit consists of a coordinating emitter follower, amplifier-shaper for avalanche key cascade control which changes potential on the counter electrodes and a shaper of discharge quenching duration. The emitter follower is assembled according to a widely used flowsheet with two transistors. The circuit permits to obtain a rectangular quenching pulse with front of 100 ns and an amplitude of up to 3.2 kV at duration of 500 μm-8 ms. Application of the quenching circuit described permits to obtain countering characteristics with the slope less than or equal to 0.02%/V and plateau extent greater than or equal to 300 V [ru

Fuzzy delay model based fault simulator for crosstalk delay fault test ...

Indian Academy of Sciences (India)

In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design .... To find the quality of non-robust tests, a fuzzy delay ..... Dubois D and Prade H 1989 Processing Fuzzy temporal knowledge. IEEE Transactions ...

Delayed power analysis

International Nuclear Information System (INIS)

Adamovich, L.A.; Azarov, V.V.

1999-01-01

Time dependent core power behavior in a nuclear reactor is described with well-known neutron kinetics equations. At the same time, two portions are distinguished in energy released from uranium nuclei fission; one released directly at fission and another delayed (residual) portion produced during radioactive decay of fission products. While prompt power is definitely described with kinetics equations, the delayed power presentation still remains outstanding. Since in operation the delayed power part is relatively small (about 6%) operation, it can be neglected for small reactivity disturbances assuming that entire power obeys neutron kinetics equations. In case of a high negative reactivity rapidly inserted in core (e.g. reactor scram initiation) the prompt and delayed components can be calculated separately with practically no impact on each other, employing kinetics equations for prompt power and known approximation formulas for delayed portion, named residual in this specific case. Under substantial disturbances the prompt component in the dynamic process becomes commensurable with delayed portion, thus making necessary to take into account their cross impact. A system of differential equations to describe time-dependent behavior of delayed power is presented. Specific NPP analysis shows a way to significantly simplify the task formulation. (author)

Periodic synchronization control of discontinuous delayed networks by using extended Filippov-framework.

Science.gov (United States)

Cai, Zuowei; Huang, Lihong; Guo, Zhenyuan; Zhang, Lingling; Wan, Xuting

2015-08-01

This paper is concerned with the periodic synchronization problem for a general class of delayed neural networks (DNNs) with discontinuous neuron activation. One of the purposes is to analyze the problem of periodic orbits. To do so, we introduce new tools including inequality techniques and Kakutani's fixed point theorem of set-valued maps to derive the existence of periodic solution. Another purpose is to design a switching state-feedback control for realizing global exponential synchronization of the drive-response network system with periodic coefficients. Unlike the previous works on periodic synchronization of neural network, both the neuron activations and controllers in this paper are allowed to be discontinuous. Moreover, owing to the occurrence of delays in neuron signal, the neural network model is described by the functional differential equation. So we introduce extended Filippov-framework to deal with the basic issues of solutions for discontinuous DNNs. Finally, two examples and simulation experiments are given to illustrate the proposed method and main results which have an important instructional significance in the design of periodic synchronized DNNs circuits involving discontinuous or switching factors. Copyright © 2015 Elsevier Ltd. All rights reserved.

A programming language for composable DNA circuits.

Science.gov (United States)

Phillips, Andrew; Cardelli, Luca

2009-08-06

Recently, a range of information-processing circuits have been implemented in DNA by using strand displacement as their main computational mechanism. Examples include digital logic circuits and catalytic signal amplification circuits that function as efficient molecular detectors. As new paradigms for DNA computation emerge, the development of corresponding languages and tools for these paradigms will help to facilitate the design of DNA circuits and their automatic compilation to nucleotide sequences. We present a programming language for designing and simulating DNA circuits in which strand displacement is the main computational mechanism. The language includes basic elements of sequence domains, toeholds and branch migration, and assumes that strands do not possess any secondary structure. The language is used to model and simulate a variety of circuits, including an entropy-driven catalytic gate, a simple gate motif for synthesizing large-scale circuits and a scheme for implementing an arbitrary system of chemical reactions. The language is a first step towards the design of modelling and simulation tools for DNA strand displacement, which complements the emergence of novel implementation strategies for DNA computing.

Parallel processing using an optical delay-based reservoir computer

Science.gov (United States)

Van der Sande, Guy; Nguimdo, Romain Modeste; Verschaffelt, Guy

2016-04-01

Delay systems subject to delayed optical feedback have recently shown great potential in solving computationally hard tasks. By implementing a neuro-inspired computational scheme relying on the transient response to optical data injection, high processing speeds have been demonstrated. However, reservoir computing systems based on delay dynamics discussed in the literature are designed by coupling many different stand-alone components which lead to bulky, lack of long-term stability, non-monolithic systems. Here we numerically investigate the possibility of implementing reservoir computing schemes based on semiconductor ring lasers. Semiconductor ring lasers are semiconductor lasers where the laser cavity consists of a ring-shaped waveguide. SRLs are highly integrable and scalable, making them ideal candidates for key components in photonic integrated circuits. SRLs can generate light in two counterpropagating directions between which bistability has been demonstrated. We demonstrate that two independent machine learning tasks , even with different nature of inputs with different input data signals can be simultaneously computed using a single photonic nonlinear node relying on the parallelism offered by photonics. We illustrate the performance on simultaneous chaotic time series prediction and a classification of the Nonlinear Channel Equalization. We take advantage of different directional modes to process individual tasks. Each directional mode processes one individual task to mitigate possible crosstalk between the tasks. Our results indicate that prediction/classification with errors comparable to the state-of-the-art performance can be obtained even with noise despite the two tasks being computed simultaneously. We also find that a good performance is obtained for both tasks for a broad range of the parameters. The results are discussed in detail in [Nguimdo et al., IEEE Trans. Neural Netw. Learn. Syst. 26, pp. 3301-3307, 2015

Patient Delay, Diagnosis Delay and Treatment Delay for Breast Cancer: Comparison of the Pattern between Patients in Public and Private Health Sectors

Directory of Open Access Journals (Sweden)

Iraj Harirchi

2015-05-01

Full Text Available Background: The purpose of this study was to compare patient delay, diagnosis delay and treatment delay in breast cancer patients of selected public and private health centers in Tehran, Iran.Methods: In this cross-sectional study, female patients with newly diagnosed breast cancer in a public medical complex and a private breast clinic within one year were included. Patient delay was considered positive, if the interval between the detection of the first symptom by the patient and the first visit to a health care provider took longer than one month. Delay in diagnosis was defined as the period of more than one week between the first medical visit for the symptoms and the diagnosis of breast cancer. Following the confirmed diagnosis of breast malignancy, if the medical treatment was initiated later than one week, treatment delay had occurred. The potential reasons for patient, diagnosis and treatment delay according to the patients’ reports were also recorded.Results: Overall, 385 patients were included of whom 52.7% were recruited from the public hospitals and 47.3% from a private clinic. The prevalence of patient delay, diagnosis delay and treatment delay were 31.7%, 17.9% and 28.3%, respectively. Patient delay was significantly more common among patients with lower socio-economic status and those recruited from the public hospitals. All the patients with diagnosis delay were in the group recruited from the public hospitals.Conclusions: Gaps between women of different socio-economic levels of the society need to be addressed in order to decrease patient, diagnosis and treatment delay.

Fabric circuits and method of manufacturing fabric circuits

Science.gov (United States)

Chu, Andrew W. (Inventor); Dobbins, Justin A. (Inventor); Scully, Robert C. (Inventor); Trevino, Robert C. (Inventor); Lin, Greg Y. (Inventor); Fink, Patrick W. (Inventor)

2011-01-01

A flexible, fabric-based circuit comprises a non-conductive flexible layer of fabric and a conductive flexible layer of fabric adjacent thereto. A non-conductive thread, an adhesive, and/or other means may be used for attaching the conductive layer to the non-conductive layer. In some embodiments, the layers are attached by a computer-driven embroidery machine at pre-determined portions or locations in accordance with a pre-determined attachment layout before automated cutting. In some other embodiments, an automated milling machine or a computer-driven laser using a pre-designed circuit trace as a template cuts the conductive layer so as to separate an undesired portion of the conductive layer from a desired portion of the conductive layer. Additional layers of conductive fabric may be attached in some embodiments to form a multi-layer construct.

Speech and Language Delay

Science.gov (United States)

... OTC Relief for Diarrhea Home Diseases and Conditions Speech and Language Delay Condition Speech and Language Delay Share Print Table of Contents1. ... Treatment6. Everyday Life7. Questions8. Resources What is a speech and language delay? A speech and language delay ...

Circuit design on plastic foils

CERN Document Server

Raiteri, Daniele; Roermund, Arthur H M

2015-01-01

This book illustrates a variety of circuit designs on plastic foils and provides all the information needed to undertake successful designs in large-area electronics.  The authors demonstrate architectural, circuit, layout, and device solutions and explain the reasons and the creative process behind each. Readers will learn how to keep under control large-area technologies and achieve robust, reliable circuit designs that can face the challenges imposed by low-cost low-temperature high-throughput manufacturing.   • Discusses implications of problems associated with large-area electronics and compares them to standard silicon; • Provides the basis for understanding physics and modeling of disordered material; • Includes guidelines to quickly setup the basic CAD tools enabling efficient and reliable designs; • Illustrates practical solutions to cope with hard/soft faults, variability, mismatch, aging and bias stress at architecture, circuit, layout, and device levels.

Semiconductor integrated circuits

International Nuclear Information System (INIS)

Michel, A.E.; Schwenker, R.O.; Ziegler, J.F.

1979-01-01

An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

Switching phenomena in high-voltage circuit breakers

International Nuclear Information System (INIS)

Nakanishi, K.

1991-01-01

The topics covered in this book include: general problems concerning current interruption, the physical arc model, and miscellaneous types of modern switching apparatus, such as gas circuit breakers, gas-insulated switch-gear, vacuum circuit breakers and high-voltage direct-current circuit breakers

Fast-responding short circuit protection system with self-reset for use in circuit supplied by DC power

Science.gov (United States)

Burns, Bradley M. (Inventor); Blalock, Norman N. (Inventor)

2011-01-01

A short circuit protection system includes an inductor, a switch, a voltage sensing circuit, and a controller. The switch and inductor are electrically coupled to be in series with one another. A voltage sensing circuit is coupled across the switch and the inductor. A controller, coupled to the voltage sensing circuit and the switch, opens the switch when a voltage at the output terminal of the inductor transitions from above a threshold voltage to below the threshold voltage. The controller closes the switch when the voltage at the output terminal of the inductor transitions from below the threshold voltage to above the threshold voltage.

Realizing a supercapacitor in an electrical circuit

International Nuclear Information System (INIS)

Fukuhara, Mikio; Kuroda, Tomoyuki; Hasegawa, Fumihiko

2014-01-01

Capacitors are commonly used in electronic resonance circuits; however, capacitors have not been used for storing large amounts of electrical energy in electrical circuits. Here, we report a superior RC circuit which serves as an electrical storage system characterized by quick charging and long-term discharging of electricity. The improved energy storage characteristics in this mixed electric circuit (R 1  + R 2 C 1 ) with small resistor R 1 , large resistor R 2 , and large capacitor C 1 are derived from the damming effect by large R 2 in simple parallel R 2 C 1 circuit. However, no research work has been carried out previously on the use of capacitors as electrical energy storage devices in circuits. Combined with nanotechnology, we hope that our finding will play a remarkable role in a variety of applications such as hybrid electric vehicles and backup power supplies

30 CFR 75.800-1 - Circuit breakers; location.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Circuit breakers; location. 75.800-1 Section 75.800-1 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR COAL MINE SAFETY... § 75.800-1 Circuit breakers; location. Circuit breakers protecting high-voltage circuits entering an...

Secure integrated circuits and systems

CERN Document Server

Verbauwhede, Ingrid MR

2010-01-01

On any advanced integrated circuit or 'system-on-chip' there is a need for security. In many applications the actual implementation has become the weakest link in security rather than the algorithms or protocols. The purpose of the book is to give the integrated circuits and systems designer an insight into the basics of security and cryptography from the implementation point of view. As a designer of integrated circuits and systems it is important to know both the state-of-the-art attacks as well as the countermeasures. Optimizing for security is different from optimizations for speed, area,

Remote tuning of NMR probe circuits.

Science.gov (United States)

Kodibagkar, V D; Conradi, M S

2000-05-01

There are many circumstances in which the probe tuning adjustments cannot be located near the rf NMR coil. These may occur in high-temperature NMR, low-temperature NMR, and in the use of magnets with small diameter access bores. We address here circuitry for connecting a fixed-tuned probe circuit by a transmission line to a remotely located tuning network. In particular, the bandwidth over which the probe may be remotely tuned while keeping the losses in the transmission line acceptably low is considered. The results show that for all resonant circuit geometries (series, parallel, series-parallel), overcoupling of the line to the tuned circuit is key to obtaining a large tuning bandwidth. At equivalent extents of overcoupling, all resonant circuit geometries have nearly equal remote tuning bandwidths. Particularly for the case of low-loss transmission line, the tuning bandwidth can be many times the tuned circuit's bandwidth, f(o)/Q. Copyright 2000 Academic Press.

Advances in Analog Circuit Design 2015

CERN Document Server

Baschirotto, Andrea; Harpe, Pieter

2016-01-01

This book is based on the 18 tutorials presented during the 24th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of efficient sensor interfaces and low-power RF systems. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development. ·         Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; ·         Presents material in a tutorial-based format; ·         Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing.

Communication and Sensing Circuits on Cellulose

Directory of Open Access Journals (Sweden)

Federico Alimenti

2015-06-01

Full Text Available This paper proposes a review of several circuits for communication and wireless sensing applications implemented on cellulose-based materials. These circuits have been developed during the last years exploiting the adhesive copper laminate method. Such a technique relies on a copper adhesive tape that is shaped by a photo-lithographic process and then transferred to the hosting substrate (i.e., paper by means of a sacrificial layer. The presented circuits span from UHF oscillators to a mixer working at 24 GHz and constitute an almost complete set of building blocks that can be applied to a huge variety communication apparatuses. Each circuit is validated experimentally showing performance comparable with the state-of-the-art. This paper demonstrates that circuits on cellulose are capable of operating at record frequencies and that ultra- low cost, green i.e., recyclable and biodegradable materials can be a viable solution to realize high frequency hardware for the upcoming Internet of Things (IoT era.

Effects of smoke on functional circuits

International Nuclear Information System (INIS)

Tanaka, T.J.

1997-10-01

Nuclear power plants are converting to digital instrumentation and control systems; however, the effects of abnormal environments such as fire and smoke on such systems are not known. There are no standard tests for smoke, but previous smoke exposure tests at Sandia National Laboratories have shown that digital communications can be temporarily interrupted during a smoke exposure. Another concern is the long-term corrosion of metals exposed to the acidic gases produced by a cable fire. This report documents measurements of basic functional circuits during and up to 1 day after exposure to smoke created by burning cable insulation. Printed wiring boards were exposed to the smoke in an enclosed chamber for 1 hour. For high-resistance circuits, the smoke lowered the resistance of the surface of the board and caused the circuits to short during the exposure. These circuits recovered after the smoke was vented. For low-resistance circuits, the smoke caused their resistance to increase slightly. A polyurethane conformal coating substantially reduced the effects of smoke. A high-speed digital circuit was unaffected. A second experiment on different logic chip technologies showed that the critical shunt resistance that would cause failure was dependent on the chip technology and that the components used in the smoke exposures were some of the most smoke tolerant. The smoke densities in these tests were high enough to cause changes in high impedance (resistance) circuits during exposure, but did not affect most of the other circuits. Conformal coatings and the characteristics of chip technologies should be considered when designing circuitry for nuclear power plant safety systems, which must be highly reliable under a variety of operating and accident conditions. 10 refs., 34 figs., 18 tabs

Switchless charge-discharge circuit for electrical capacitance tomography

International Nuclear Information System (INIS)

Kryszyn, J; Smolik, W T; Radzik, B; Olszewski, T; Szabatin, R

2014-01-01

The main factor limiting the performance of electrical capacitance tomography (ECT) is an extremely low value of inter-electrode capacitances. The charge-discharge circuit is a well suited circuit for a small capacitance measurement due to its immunity to noise and stray capacitance, although it has a problem associated with a charge injected by the analogue switches, which results in a dc offset. This paper presents a new diode-based circuit for capacitance measurement in which a charge transfer method is realized without switches. The circuit was built and tested in one channel configuration with 16 multiplexed electrodes. The performance of the elaborated circuit and a comparison with a classic charge-discharge circuit are presented. The elaborated circuit can be used for sensors with inter-electrode capacitances not lower than 10 fF. The presented approach allows us to obtain a similar performance to the classic charge-discharge circuit, but has a simplified design. A lack of the need to synchronize the analogue switches in the transmitter and the receiver part of this circuit could be a desirable feature in the design of measurement systems integrated with electrodes. (paper)

A lock circuit for a multi-core processor

DEFF Research Database (Denmark)

2015-01-01

An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....

A Simple Short Circuit Analysis for Power Networks

Directory of Open Access Journals (Sweden)

Koşalay İlhan

2016-01-01

Full Text Available This study investigates the transient behavior of short circuits in power circuits. The circuit consists of two part; input part and load part. These two parts are connected with a circuit breaker switch. The circuit works in two modes; first mode is when the switch is open and second mode is when the switch is closed. This study analyses the circuit when the switch is closed. The analysis is done with different types of closing angle. The analysis is done by forming state equations and those equations are solved numerically by using Matlab. The analysis and conclusion is performed by observing the behaviors of the graphs.

Circuit-Adaptive Challenge Balancing in Racing Games

NARCIS (Netherlands)

Rietveld, A.; Bakkes, S.; Roijers, D.

2014-01-01

In this paper, we propose a novel approach to challenge balancing in racing games: circuit-adaptive challenge balancing. We propose to automatically adapt the actual racing circuit - while it is being played - such that the performed circuit adaptations intelligently balance the challenge for all

LTS and FS inhibitory interneurons, short-term synaptic plasticity, and cortical circuit dynamics.

Directory of Open Access Journals (Sweden)

Itai Hayut

2011-10-01

Full Text Available Somatostatin-expressing, low threshold-spiking (LTS cells and fast-spiking (FS cells are two common subtypes of inhibitory neocortical interneuron. Excitatory synapses from regular-spiking (RS pyramidal neurons to LTS cells strongly facilitate when activated repetitively, whereas RS-to-FS synapses depress. This suggests that LTS neurons may be especially relevant at high rate regimes and protect cortical circuits against over-excitation and seizures. However, the inhibitory synapses from LTS cells usually depress, which may reduce their effectiveness at high rates. We ask: by which mechanisms and at what firing rates do LTS neurons control the activity of cortical circuits responding to thalamic input, and how is control by LTS neurons different from that of FS neurons? We study rate models of circuits that include RS cells and LTS and FS inhibitory cells with short-term synaptic plasticity. LTS neurons shift the RS firing-rate vs. current curve to the right at high rates and reduce its slope at low rates; the LTS effect is delayed and prolonged. FS neurons always shift the curve to the right and affect RS firing transiently. In an RS-LTS-FS network, FS neurons reach a quiescent state if they receive weak input, LTS neurons are quiescent if RS neurons receive weak input, and both FS and RS populations are active if they both receive large inputs. In general, FS neurons tend to follow the spiking of RS neurons much more closely than LTS neurons. A novel type of facilitation-induced slow oscillations is observed above the LTS firing threshold with a frequency determined by the time scale of recovery from facilitation. To conclude, contrary to earlier proposals, LTS neurons affect the transient and steady state responses of cortical circuits over a range of firing rates, not only during the high rate regime; LTS neurons protect against over-activation about as well as FS neurons.

30 CFR 75.900-1 - Circuit breakers; location.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Circuit breakers; location. 75.900-1 Section 75.900-1 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR COAL MINE SAFETY... Alternating Current Circuits § 75.900-1 Circuit breakers; location. Circuit breakers used to protect low-and...

30 CFR 57.12017 - Work on power circuits.

Science.gov (United States)

2010-07-01

... shall prevent the power circuits from being energized without the knowledge of the individuals working... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Work on power circuits. 57.12017 Section 57... Surface and Underground § 57.12017 Work on power circuits. Power circuits shall be deenergized before work...

Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

Science.gov (United States)

Shin, SeungJun; Yu, YunSeop; Choi, JungBum

2008-10-01

New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

Alteration in neonatal nutrition causes perturbations in hypothalamic neural circuits controlling reproductive function.

Science.gov (United States)

Caron, Emilie; Ciofi, Philippe; Prevot, Vincent; Bouret, Sebastien G

2012-08-15

It is increasingly accepted that alterations of the early life environment may have lasting impacts on physiological functions. In particular, epidemiological and animal studies have indicated that changes in growth and nutrition during childhood and adolescence can impair reproductive function. However, the precise biological mechanisms that underlie these programming effects of neonatal nutrition on reproduction are still poorly understood. Here, we used a mouse model of divergent litter size to investigate the effects of early postnatal overnutrition and undernutrition on the maturation of hypothalamic circuits involved in reproductive function. Neonatally undernourished females display attenuated postnatal growth associated with delayed puberty and defective development of axonal projections from the arcuate nucleus to the preoptic region. These alterations persist into adulthood and specifically affect the organization of neural projections containing kisspeptin, a key neuropeptide involved in pubertal activation and fertility. Neonatal overfeeding also perturbs the development of neural projections from the arcuate nucleus to the preoptic region, but it does not result in alterations in kisspeptin projections. These studies indicate that alterations in the early nutritional environment cause lasting and deleterious effects on the organization of neural circuits involved in the control of reproduction, and that these changes are associated with lifelong functional perturbations.

The elusive memristor: properties of basic electrical circuits

Energy Technology Data Exchange (ETDEWEB)

Joglekar, Yogesh N; Wolf, Stephen J [Department of Physics, Indiana University Purdue University Indianapolis, Indianapolis, IN 46202 (United States)], E-mail: yojoglek@iupui.edu

2009-07-15

We present an introduction to and a tutorial on the properties of the recently discovered ideal circuit element, a memristor. By definition, a memristor M relates the charge q and the magnetic flux {phi} in a circuit and complements a resistor R, a capacitor C and an inductor L as an ingredient of ideal electrical circuits. The properties of these three elements and their circuits are a part of the standard curricula. The existence of the memristor as the fourth ideal circuit element was predicted in 1971 based on symmetry arguments, but was clearly experimentally demonstrated just last year. We present the properties of a single memristor, memristors in series and parallel, as well as ideal memristor-capacitor (MC), memristor-inductor (ML) and memristor-capacitor-inductor (MCL) circuits. We find that the memristor has hysteretic current-voltage characteristics. We show that the ideal MC (ML) circuit undergoes non-exponential charge (current) decay with two time scales and that by switching the polarity of the capacitor, an ideal MCL circuit can be tuned from overdamped to underdamped. We present simple models which show that these unusual properties are closely related to the memristor's internal dynamics. This tutorial complements the pedagogy of ideal circuit elements (R, C and L) and the properties of their circuits, and is aimed at undergraduate physics and electrical engineering students.

The elusive memristor: properties of basic electrical circuits

International Nuclear Information System (INIS)

Joglekar, Yogesh N; Wolf, Stephen J

2009-01-01

We present an introduction to and a tutorial on the properties of the recently discovered ideal circuit element, a memristor. By definition, a memristor M relates the charge q and the magnetic flux φ in a circuit and complements a resistor R, a capacitor C and an inductor L as an ingredient of ideal electrical circuits. The properties of these three elements and their circuits are a part of the standard curricula. The existence of the memristor as the fourth ideal circuit element was predicted in 1971 based on symmetry arguments, but was clearly experimentally demonstrated just last year. We present the properties of a single memristor, memristors in series and parallel, as well as ideal memristor-capacitor (MC), memristor-inductor (ML) and memristor-capacitor-inductor (MCL) circuits. We find that the memristor has hysteretic current-voltage characteristics. We show that the ideal MC (ML) circuit undergoes non-exponential charge (current) decay with two time scales and that by switching the polarity of the capacitor, an ideal MCL circuit can be tuned from overdamped to underdamped. We present simple models which show that these unusual properties are closely related to the memristor's internal dynamics. This tutorial complements the pedagogy of ideal circuit elements (R, C and L) and the properties of their circuits, and is aimed at undergraduate physics and electrical engineering students

Compact Circuit Preprocesses Accelerometer Output

Science.gov (United States)

Bozeman, Richard J., Jr.

1993-01-01

Compact electronic circuit transfers dc power to, and preprocesses ac output of, accelerometer and associated preamplifier. Incorporated into accelerometer case during initial fabrication or retrofit onto commercial accelerometer. Made of commercial integrated circuits and other conventional components; made smaller by use of micrologic and surface-mount technology.

Worst Asymmetrical Short-Circuit Current

DEFF Research Database (Denmark)

Arana Aristi, Iván; Holmstrøm, O; Grastrup, L

2010-01-01

In a typical power plant, the production scenario and the short-circuit time were found for the worst asymmetrical short-circuit current. Then, a sensitivity analysis on the missing generator values was realized in order to minimize the uncertainty of the results. Afterward the worst asymmetrical...

Synchronization of delayed systems in the presence of delay time modulation

International Nuclear Information System (INIS)

Kye, Won-Ho; Choi, Muhan; Kim, Myung-Woon; Lee, Soo-Young; Rim, Sunghwan; Kim, Chil-Min; Park, Young-Jai

2004-01-01

We investigate synchronization in the presence of delay time modulation for application to communication. We have observed that the robust synchronization is established by a common delay signal and its threshold is presented using Lyapunov exponents analysis. The influence of the delay time modulation in chaotic oscillators is also discussed

Circuit engineering principles for construction of bipolar large-scale integrated circuit storage devices and very large-scale main memory

Science.gov (United States)

Neklyudov, A. A.; Savenkov, V. N.; Sergeyez, A. G.

1984-06-01

Memories are improved by increasing speed or the memory volume on a single chip. The most effective means for increasing speeds in bipolar memories are current control circuits with the lowest extraction times for a specific power consumption (1/4 pJ/bit). The control current circuitry involves multistage current switches and circuits accelerating transient processes in storage elements and links. Circuit principles for the design of bipolar memories with maximum speeds for an assigned minimum of circuit topology are analyzed. Two main classes of storage with current control are considered: the ECL type and super-integrated injection type storage with data capacities of N = 1/4 and N 4/16, respectively. The circuits reduce logic voltage differentials and the volumes of lexical and discharge buses and control circuit buses. The limiting speed is determined by the antiinterference requirements of the memory in storage and extraction modes.

30 CFR 57.4011 - Abandoned electric circuits.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Abandoned electric circuits. 57.4011 Section 57.4011 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR METAL AND NONMETAL... and Control § 57.4011 Abandoned electric circuits. Abandoned electric circuits shall be deenergized...

Realizing a supercapacitor in an electrical circuit

Energy Technology Data Exchange (ETDEWEB)

Fukuhara, Mikio, E-mail: fukuhara@niche.tohoku.ac.jp; Kuroda, Tomoyuki; Hasegawa, Fumihiko [New Industry Creation Hatchery Center, Tohoku University, Sendai 980-8579 (Japan)

2014-11-17

Capacitors are commonly used in electronic resonance circuits; however, capacitors have not been used for storing large amounts of electrical energy in electrical circuits. Here, we report a superior RC circuit which serves as an electrical storage system characterized by quick charging and long-term discharging of electricity. The improved energy storage characteristics in this mixed electric circuit (R{sub 1} + R{sub 2}C{sub 1}) with small resistor R{sub 1}, large resistor R{sub 2}, and large capacitor C{sub 1} are derived from the damming effect by large R{sub 2} in simple parallel R{sub 2}C{sub 1} circuit. However, no research work has been carried out previously on the use of capacitors as electrical energy storage devices in circuits. Combined with nanotechnology, we hope that our finding will play a remarkable role in a variety of applications such as hybrid electric vehicles and backup power supplies.

Test and Diagnosis of Integrated Circuits

OpenAIRE

Bosio , Alberto

2015-01-01

The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users...

Chaos synchronization in time-delayed systems with parameter mismatches and variable delay times

International Nuclear Information System (INIS)

Shahverdiev, E.M.; Nuriev, R.A.; Hashimov, R.H.; Shore, K.A.

2004-06-01

We investigate synchronization between two undirectionally linearly coupled chaotic nonidentical time-delayed systems and show that parameter mismatches are of crucial importance to achieve synchronization. We establish that independent of the relation between the delay time in the coupled systems and the coupling delay time, only retarded synchronization with the coupling delay time is obtained. We show that with parameter mismatch or without it neither complete nor anticipating synchronization occurs. We derive existence and stability conditions for the retarded synchronization manifold. We demonstrate our approach using examples of the Ikeda and Mackey Glass models. Also for the first time we investigate chaos synchronization in time-delayed systems with variable delay time and find both existence and sufficient stability conditions for the retarded synchronization manifold with the coupling-delay lag time. (author)

21 CFR 868.5240 - Anesthesia breathing circuit.

Science.gov (United States)

2010-04-01

... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Anesthesia breathing circuit. 868.5240 Section 868...) MEDICAL DEVICES ANESTHESIOLOGY DEVICES Therapeutic Devices § 868.5240 Anesthesia breathing circuit. (a) Identification. An anesthesia breathing circuit is a device that is intended to administer medical gases to a...

Improvements in or relating to transistor circuits

International Nuclear Information System (INIS)

Richards, R.F.; Williamson, P.W.

1978-01-01

This invention relates to transistor circuits and in particular to integrated transistor circuits formed on a substrate of semi-conductor material such as silicon. The invention is concerned with providing integrated circuits in which malfunctions caused by the effects of ionising, e.g. nuclear, radiations are reduced. (author)

Development of a pulse shape discrimination circuit

International Nuclear Information System (INIS)

Ye Bangjiao; Fan Wei; Fan Yangmei; Yu Xiaoqi; Mei Wen; Wang Zhongmin; Han Rongdian; Xiao Zhenxi

1994-01-01

A pulse shape discrimination circuit was designed and used in an experiment measuring double-differential cross sections of (n, charged particle) reaction; to identify p, α and γ. The performance of the circuit was tested. With this circuit, excellent identification of p, α and γ was obtained. ((orig.))

The point of practical use for the transistor circuit

International Nuclear Information System (INIS)

1996-01-01

This is comprised of eight chapters and goes as follows; what is transistor? the first step for use of transistor such as connection between power and signal source, static characteristic of transistor and equivalent circuit of transistor, design of easy small-signal amplifier circuit, design for amplification of electric power and countermeasure for prevention of trouble, transistor concerned interface, transistor circuit around micro computer, transistor in active use of FET and power circuit and transistor. It has an appendix on transistor and design of bias of FET circuits like small signal transistor circuit and FET circuit.

Circuit design techniques for non-crystalline semiconductors

CERN Document Server

Sambandan, Sanjiv

2012-01-01

Despite significant progress in materials and fabrication technologies related to non-crystalline semiconductors, fundamental drawbacks continue to limit real-world application of these devices in electronic circuits. To help readers deal with problems such as low mobility and intrinsic time variant behavior, Circuit Design Techniques for Non-Crystalline Semiconductors outlines a systematic design approach, including circuit theory, enabling users to synthesize circuits without worrying about the details of device physics. This book: Offers examples of how self-assembly can be used as a powerf

Precise linear gating circuit on integrated microcircuits

Energy Technology Data Exchange (ETDEWEB)

Butskii, V.V.; Vetokhin, S.S.; Reznikov, I.V.

Precise linear gating circuit on four microcircuits is described. A basic flowsheet of the gating circuit is given. The gating circuit consists of two input differential cascades total load of which is two current followers possessing low input and high output resistances. Follower outlets are connected to high ohmic dynamic load formed with a current source which permits to get high amplification (>1000) at one cascade. Nonlinearity amounts to <0.1% in the range of input signal amplitudes of -10-+10 V. Front duration for an output signal with 10 V amplitude amounts to 100 ns. Attenuation of input signal with a closed gating circuit is 60 db. The gating circuits described is used in the device intended for processing of scintillation sensor signals.

Trigger circuits for the PHENIX electromagnetic calorimeter

International Nuclear Information System (INIS)

Frank, S.S.; Britton, C.L. Jr.; Winterberg, A.L.; Young, G.R.

1997-11-01

Monolithic and discrete circuits have been developed to provide trigger signals for the PHENIX electromagnetic calorimeter detector. These trigger circuits are deadtimeless and create overlapping 4 by 4 energy sums, a cosmic muon trigger, and a 144 channel energy sum. The front end electronics of the PHENIX system sample the energy and timing channels at each bunch crossing (BC) but it is not known immediately if this data is of interest. The information from the trigger circuits is used to determine if the data collected is of interest and should be digitized and stored or discarded. This paper presents details of the design, issues affecting circuit performance, characterization of prototypes fabricated in 1.2 microm Orbit CMOS, and integration of the circuits into the EMCal electronics system

Wireless transceiver circuits system perspectives and design aspects

CERN Document Server

Rhee, Woogeun

2015-01-01

This cutting-edge work contains comprehensive coverage of integrated circuit (IC) design for modern transceiver circuits and wireless systems. Ranging in scope from system perspectives to practical circuit design for emerging wireless applications, the book includes detailed discussions of transceiver architectures and system parameters, mm-wave circuits, ultra-low-power radios for biomedical and sensor applications, and the latest circuit techniques. Written by renowned international experts in IC industry and academia, the text is an ideal reference for engineers and researchers in the area

Digital signal processing in power electronics control circuits

CERN Document Server

Sozanski, Krzysztof

2013-01-01

Many digital control circuits in current literature are described using analog transmittance. This may not always be acceptable, especially if the sampling frequency and power transistor switching frequencies are close to the band of interest. Therefore, a digital circuit is considered as a digital controller rather than an analog circuit. This helps to avoid errors and instability in high frequency components. Digital Signal Processing in Power Electronics Control Circuits covers problems concerning the design and realization of digital control algorithms for power electronics circuits using

Development of 3D integrated circuits for HEP

International Nuclear Information System (INIS)

Yarema, R.; Fermilab

2006-01-01

Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented

Differential transimpedance amplifier circuit for correlated differential amplification

Science.gov (United States)

Gresham, Christopher A [Albuquerque, NM; Denton, M Bonner [Tucson, AZ; Sperline, Roger P [Tucson, AZ

2008-07-22

A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

CMOS digital integrated circuits a first course

CERN Document Server

Hawkins, Charles; Zarkesh-Ha, Payman

2016-01-01

This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

Enhancement of Linear Circuit Program

DEFF Research Database (Denmark)

Gaunholt, Hans; Dabu, Mihaela; Beldiman, Octavian

1996-01-01

In this report a preliminary user friendly interface has been added to the LCP2 program making it possible to describe an electronic circuit by actually drawing the circuit on the screen. Component values and other options and parameters can easily be set by the aid of the interface. The interface...

An analog integrated circuit design laboratory

OpenAIRE

Mondragon-Torres, A.F.; Mayhugh, Jr.; Pineda de Gyvez, J.; Silva-Martinez, J.; Sanchez-Sinencio, E.

2003-01-01

We present the structure of an analog integrated circuit design laboratory to instruct at both, senior undergraduate and entry graduate levels. The teaching material includes: a laboratory manual with analog circuit design theory, pre-laboratory exercises and circuit design specifications; a reference web page with step by step instructions and examples; the use of mathematical tools for automation and analysis; and state of the art CAD design tools in use by industry. Upon completion of the ...

Analog circuit design art, science, and personalities

CERN Document Server

Williams, Jim

1991-01-01

Analog Circuit Design: Art, Science, and Personalities discusses the many approaches and styles in the practice of analog circuit design. The book is written in an informal yet informative manner, making it easily understandable to those new in the field. The selection covers the definition, history, current practice, and future direction of analog design; the practice proper; and the styles in analog circuit design. The book also includes the problems usually encountered in analog circuit design; approach to feedback loop design; and other different techniques and applications. The text is

Intrinsic neuromodulation: altering neuronal circuits from within.

Science.gov (United States)

Katz, P S; Frost, W N

1996-02-01

There are two sources of neuromodulation for neuronal circuits: extrinsic inputs and intrinsic components of the circuits themselves. Extrinsic neuromodulation is known to be pervasive in nervous systems, but intrinsic neuromodulation is less recognized, despite the fact that it has now been demonstrated in sensory and neuromuscular circuits and in central pattern generators. By its nature, intrinsic neuromodulation produces local changes in neuronal computation, whereas extrinsic neuromodulation can cause global changes, often affecting many circuits simultaneously. Studies in a number of systems are defining the different properties of these two forms of neuromodulation.

Electric circuit theory applied electricity and electronics

CERN Document Server

Yorke, R

1981-01-01

Electric Circuit Theory provides a concise coverage of the framework of electrical engineering. Comprised of six chapters, this book emphasizes the physical process of electrical engineering rather than abstract mathematics. Chapter 1 deals with files, circuits, and parameters, while Chapter 2 covers the natural and forced response of simple circuit. Chapter 3 talks about the sinusoidal steady state, and Chapter 4 discusses the circuit analysis. The fifth chapter tackles frequency response of networks, and the last chapter covers polyphase systems. This book will be of great help to electrical

Universal programmable quantum circuit schemes to emulate an operator

Energy Technology Data Exchange (ETDEWEB)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos [Department of Computer Science, Purdue University, West Lafayette, Indiana 47907 (United States); Kais, Sabre [Department of Chemistry, Department of Physics and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907 (United States); Qatar Environment and Energy Research Institute, Doha (Qatar)

2012-12-21

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

Universal programmable quantum circuit schemes to emulate an operator

International Nuclear Information System (INIS)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos; Kais, Sabre

2012-01-01

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix–which can be non-unitary–in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e −iHt for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

Directory of Open Access Journals (Sweden)

Chao Chen

2014-01-01

Full Text Available We describe the architecture of a time-to-digital converter (TDC, specially intended to measure the delay resolution of a programmable delay line (PDL. The configuration, which consists of a ring oscillator, a frequency divider (FD, and a period measurement circuit (PMC, is implemented in a field programmable gate array (FPGA device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

Classic conditioning in aged rabbits: delay, trace, and long-delay conditioning.

Science.gov (United States)

Solomon, P R; Groccia-Ellison, M E

1996-06-01

Young (0.5 years) and aged (2+, 3+, and 4+ years) rabbits underwent acquisition of the classically conditioned nictitating membrane response in a delay (500-ms conditioned stimulus [CS], 400-ms interstimulus interval [ISI]), long-delay (1,000-ms CS, 900-ms ISI), or trace (500-ms CS, 400-ms stimulus-free period) paradigm. Collapsing across age groups, there is a general tendency for animals to acquire trace conditioning more slowly than delay conditioning. Collapsing across conditioning paradigms, there is a general tendency for aged animals to acquire more slowly than younger animals. Of greater significance, however, are the age differences in the different conditioning paradigms. In the delay and long-delay paradigms, significant conditioning deficits first appeared in the 4(+)-year-old group. In the trace conditioning paradigm, significant conditioning deficits became apparent in the 2(+)-year-old animals.

Detection Method for Soft Internal Short Circuit in Lithium-Ion Battery Pack by Extracting Open Circuit Voltage of Faulted Cell

Directory of Open Access Journals (Sweden)

Minhwan Seo

2018-06-01

Full Text Available Early detection of internal short circuit which is main cause of thermal runaway in a lithium-ion battery is necessary to ensure battery safety for users. As a promising fault index, internal short circuit resistance can directly represent degree of the fault because it describes self-discharge phenomenon caused by the internal short circuit clearly. However, when voltages of individual cells in a lithium-ion battery pack are not provided, the effect of internal short circuit in the battery pack is not readily observed in whole terminal voltage of the pack, leading to difficulty in estimating accurate internal short circuit resistance. In this paper, estimating the resistance with the whole terminal voltages and the load currents of the pack, a detection method for the soft internal short circuit in the pack is proposed. Open circuit voltage of a faulted cell in the pack is extracted to reflect the self-discharge phenomenon obviously; this process yields accurate estimates of the resistance. The proposed method is verified with various soft short conditions in both simulations and experiments. The error of estimated resistance does not exceed 31.2% in the experiment, thereby enabling the battery management system to detect the internal short circuit early.

Synthesis of logic circuits with evolutionary algorithms

Energy Technology Data Exchange (ETDEWEB)

JONES,JAKE S.; DAVIDSON,GEORGE S.

2000-01-26

In the last decade there has been interest and research in the area of designing circuits with genetic algorithms, evolutionary algorithms, and genetic programming. However, the ability to design circuits of the size and complexity required by modern engineering design problems, simply by specifying required outputs for given inputs has as yet eluded researchers. This paper describes current research in the area of designing logic circuits using an evolutionary algorithm. The goal of the research is to improve the effectiveness of this method and make it a practical aid for design engineers. A novel method of implementing the algorithm is introduced, and results are presented for various multiprocessing systems. In addition to evolving standard arithmetic circuits, work in the area of evolving circuits that perform digital signal processing tasks is described.

Micro-relay technology for energy-efficient integrated circuits

CERN Document Server

Kam, Hei

2015-01-01

This book describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers and highlights the importance of co-design across design hierarchies when optimizing system performance (in this case, energy-efficiency). This book is ideal for researchers and engineers focused on semiconductors, integrated circuits, and energy efficient electronics. This book also: ·         Covers microsystem fabrication, MEMS device design, circuit design, circuit micro-architecture, and CAD ·         Describes work previously done in the field and also lays the groundwork and criteria for future energy-efficient device and system design ·         Maximizes reader insights into the design and modeling of micro-relay, micro-relay reliability, integrated circuit design with micro-relays, and more

Synthetic Biology: A Unifying View and Review Using Analog Circuits.

Science.gov (United States)

Teo, Jonathan J Y; Woo, Sung Sik; Sarpeshkar, Rahul

2015-08-01

We review the field of synthetic biology from an analog circuits and analog computation perspective, focusing on circuits that have been built in living cells. This perspective is well suited to pictorially, symbolically, and quantitatively representing the nonlinear, dynamic, and stochastic (noisy) ordinary and partial differential equations that rigorously describe the molecular circuits of synthetic biology. This perspective enables us to construct a canonical analog circuit schematic that helps unify and review the operation of many fundamental circuits that have been built in synthetic biology at the DNA, RNA, protein, and small-molecule levels over nearly two decades. We review 17 circuits in the literature as particular examples of feedforward and feedback analog circuits that arise from special topological cases of the canonical analog circuit schematic. Digital circuit operation of these circuits represents a special case of saturated analog circuit behavior and is automatically incorporated as well. Many issues that have prevented synthetic biology from scaling are naturally represented in analog circuit schematics. Furthermore, the deep similarity between the Boltzmann thermodynamic equations that describe noisy electronic current flow in subthreshold transistors and noisy molecular flux in biochemical reactions has helped map analog circuit motifs in electronics to analog circuit motifs in cells and vice versa via a `cytomorphic' approach. Thus, a body of knowledge in analog electronic circuit design, analysis, simulation, and implementation may also be useful in the robust and efficient design of molecular circuits in synthetic biology, helping it to scale to more complex circuits in the future.

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Science.gov (United States)

Lohn, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris; Norvig, Peter (Technical Monitor)

2000-01-01

We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

Piezo pump and pressurized circuit provided therewith

NARCIS (Netherlands)

Van Es, Johannes; Wits, Wessel Willems

2015-01-01

A piezo pump for use in a pressurized circuit includes a pump chamber with an inlet provided with a one way inlet valve, for connection to a feeding line of the pressurized circuit and an outlet provided with a one way outlet valve, for connection to a discharge line of the pressurized circuit and a

Vertically integrated circuit development at Fermilab for detectors

International Nuclear Information System (INIS)

Yarema, R; Deptuch, G; Hoff, J; Khalid, F; Lipton, R; Shenai, A; Trimpl, M; Zimmerman, T

2013-01-01

Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications

International Nuclear Information System (INIS)

Zhuge, Jing; Huang, Ru; Wang, Yangyuan; Verhulst, Anne S; Vandenberghe, William G; Dehaene, Wim; Groeseneken, Guido

2011-01-01

This paper investigates the potential of tunnel field-effect transistors (TFETs), with emphasis on short-gate TFETs, by simulation for low-power digital applications having a supply voltage lower than 0.5 V. A transient study shows that the tunneling current has a negligible contribution in charging and discharging the gate capacitance of TFETs. In spite of a higher resistance region in the short-gate TFET, the gate (dis)charging speed still meets low-voltage application requirements. A circuit analysis is performed on short-gate TFETs with different materials, such as Si, Ge and heterostructures in terms of voltage overshoot, delay, static power, energy consumption and energy delay product (EDP). These results are compared to MOSFET and full-gate TFET performance. It is concluded that short-gate heterostructure TFETs (Ge–source for nTFET, In 0.6 Ga 0.4 As–source for pTFET) are promising candidates to extend the supply voltage to lower than 0.5 V because they combine the advantage of a low Miller capacitance, due to the short-gate structures, and strong drive current in TFETs, due to the narrow bandgap material in the source. At a supply voltage of 0.4 V and for an EOT and channel length of 0.6 nm and 40 nm, respectively, a three-stage inverter chain based on short-gate heterostructure TFETs saves 40% energy consumption per cycle at the same delay and shows 60%–75% improvement of EDP at the same static power, compared to its full-gate counterpart. When compared to the MOSFET, better EDP can be achieved in the heterostructure TFET especially at low static power consumption

Cell short circuit, preshort signature

Science.gov (United States)

Lurie, C.

1980-01-01

Short-circuit events observed in ground test simulations of DSCS-3 battery in-orbit operations are analyzed. Voltage signatures appearing in the data preceding the short-circuit event are evaluated. The ground test simulation is briefly described along with performance during reconditioning discharges. Results suggest that a characteristic signature develops prior to a shorting event.

Energy-efficient neuron, synapse and STDP integrated circuits.

Science.gov (United States)

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

Circuit Training.

Science.gov (United States)

Nelson, Jane B.

1998-01-01

Describes a research-based activity for high school physics students in which they build an LC circuit and find its resonant frequency of oscillation using an oscilloscope. Includes a diagram of the apparatus and an explanation of the procedures. (DDR)

Geiger-Muller (GM) counters. Associated circuits and counting techniques; Les compteurs de Geiger-Muller (GM). Les circuits associes et techniques de comptage

Energy Technology Data Exchange (ETDEWEB)

Benoit, A.; Picard, E. [Commissariat a l' Energie Atomique, Centre d' Etudes Nucleaires de Saclay (France)

1954-07-01

This article presents the Geiger-Muller counters which present the great benefit of being simple and steady in comparison with other known sensors. The authors propose an overview of problems related to the use of Geiger-Muller counters (GM counters). They first describe their operation (discharge initiation, discharge propagation, collection of positive ions and current in the counter). They discuss their limitations which are related to the migration delay of primary electrons and positive ions. They describe the operation circuit for counters with organic vapour, and for counters associated with counters using halogens. They address the main properties of GM counters, and the different factors to be taken into account when using them to count radioactive sources. The main types of GM counters are then described (they are used to measure different types of radiation). Measurement techniques are discussed for beta radiation (relationship between the number of disintegrations and the noticed counting rate, case of backscattering, absorption and diffusion in the counter window and in the air, influence of absorption and backscattering in the source), for alpha radiation, and for gamma radiation.

Delayed minocycline but not delayed mild hypothermia protects against embolic stroke

Directory of Open Access Journals (Sweden)

Noor Raza

2002-04-01

Full Text Available Abstract Background Inflammatory reactions occurring in the brain after ischemia may contribute to secondary damage. In the present study, effects of minocycline, an anti-inflammatory agent, alone or in combination with mild hypothermia on focal embolic cerebral ischemia have been examined. Methods Focal ischemic injury was induced by embolizing a preformed clot into the middle cerebral artery (MCA. Infarction volume was measured at 48 h after the injury. Mortality was also recorded. Results Delayed administration of minocycline alone or delayed minocycline plus delayed mild hypothermia reduced the infarction volume significantly. However, delayed mild hypothermia alone was not protective and delayed mild hypothermia in combination with minocycline did not show any additive effect. Conclusions These results suggest that minocycline is beneficial in focal ischemic brain injury, and the lack of the enhanced neuroprotection may be due to the brief exposure to hypothermia.

Wiring of electronic evaluation circuits

International Nuclear Information System (INIS)

Bauer, R.; Svoboda, Z.

1977-01-01

The wiring is described of electronic evaluation circuits for the automatic viewing of photographic paper strip negatives on which line tracks with an angular scatter relative to the spectrograph longitudinal axis were recorded during the oblique flight of nuclear particles during exposure in the spectrograph. In coincidence evaluation, the size of the angular scatter eventually requires that evaluation dead time be increased. The equipment consists of minimally two fixed registers and a block of logic circuits whose output is designed such as will allow connection to equipment for recording signals corresponding to the number of tracks on the film. The connection may be implemented using integrated circuits guaranteeing high operating reliability and life. (J.B.)

Hybrid Direct-Current Circuit Breaker

Science.gov (United States)

Wang, Ruxi (Inventor); Premerlani, William James (Inventor); Caiafa, Antonio (Inventor); Pan, Yan (Inventor)

2017-01-01

A circuit breaking system includes a first branch including at least one solid-state snubber; a second branch coupled in parallel to the first branch and including a superconductor and a cryogenic contactor coupled in series; and a controller operatively coupled to the at least one solid-state snubber and the cryogenic contactor and programmed to, when a fault occurs in the load circuit, activate the at least one solid-state snubber for migrating flow of the electrical current from the second branch to the first branch, and, when the fault is cleared in the load circuit, activate the cryogenic contactor for migrating the flow of the electrical current from the first branch to the second branch.

Vertically Integrated Circuits at Fermilab

International Nuclear Information System (INIS)

Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

2009-01-01

The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

Science.gov (United States)

Reagor, James A; Holt, David W

2016-03-01

Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

30 CFR 56.12065 - Short circuit and lightning protection.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Short circuit and lightning protection. 56... Electricity § 56.12065 Short circuit and lightning protection. Powerlines, including trolley wires, and telephone circuits shall be protected against short circuits and lightning. ...

Electronic circuit for control rod attracting electromagnet

International Nuclear Information System (INIS)

Ito, Koji.

1991-01-01

The present invention provides a discharging circuit for control rod attracting electromagnet used for a reactor which is highly reliable and has high performance. The resistor of the circuit comprises a non-linear resistor element and a blocking rectification element connected in series. The discharging circuit can be prevented from short-circuit by selecting a resistor having a resistance value about ten times as great as the coil resistance, even in a case where the blocking rectification element and the non-linear resistor element are failed. Accordingly, reduction of attracting force and the increase of scream releasing time can be minimized. (I.S.)

Computer-aided engineering of semiconductor integrated circuits

Science.gov (United States)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

Delayed puberty in girls

Science.gov (United States)

... sexual development - girls; Pubertal delay - girls; Constitutional delayed puberty ... In most cases of delayed puberty, growth changes just begin later than usual, sometimes called a late bloomer. Once puberty begins, it progresses normally. This pattern runs ...

Operational amplifier circuits analysis and design

CERN Document Server

Nelson, J C C

1995-01-01

This book, a revised and updated version of the author's Basic Operational Amplifiers (Butterworths 1986), enables the non-specialist to make effective use of readily available integrated circuit operational amplifiers for a range of applications, including instrumentation, signal generation and processing.It is assumed the reader has a background in the basic techniques of circuit analysis, particularly the use of j notation for reactive circuits, with a corresponding level of mathematical ability. The underlying theory is explained with sufficient but not excessive, detail. A range of compu

Delayed Puberty (For Teens)

Science.gov (United States)

... Safe Videos for Educators Search English Español Delayed Puberty KidsHealth / For Teens / Delayed Puberty What's in this ... wonder if there's anything wrong. What Is Delayed Puberty? Puberty is the time when your body grows ...

Design, Analysis and Test of Logic Circuits Under Uncertainty

CERN Document Server

Krishnaswamy, Smita; Hayes, John P

2013-01-01

Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:   • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;   • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-l...

A METHOD AND AN APPARATUS FOR PROVIDING TIMING SIGNALS TO A NUMBER OF CIRCUITS, AN INTEGRATED CIRCUIT AND A NODE

DEFF Research Database (Denmark)

2006-01-01

A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing...... signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier....

Junction and circuit fabrication

International Nuclear Information System (INIS)

Jackel, L.D.

1980-01-01

Great strides have been made in Josephson junction fabrication in the four years since the first IC SQUID meeting. Advances in lithography have allowed the production of devices with planar dimensions as small as a few hundred angstroms. Improved technology has provided ultra-high sensitivity SQUIDS, high-efficiency low-noise mixers, and complex integrated circuits. This review highlights some of the new fabrication procedures. The review consists of three parts. Part 1 is a short summary of the requirements on junctions for various applications. Part 2 reviews intergrated circuit fabrication, including tunnel junction logic circuits made at IBM and Bell Labs, and microbridge radiation sources made at SUNY at Stony Brook. Part 3 describes new junction fabrication techniques, the major emphasis of this review. This part includes a discussion of small oxide-barrier tunnel junctions, semiconductor barrier junctions, and microbridge junctions. Part 3 concludes by considering very fine lithography and limitations to miniaturization. (orig.)

30 CFR 57.12065 - Short circuit and lightning protection.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Short circuit and lightning protection. 57... MINES Electricity Surface Only § 57.12065 Short circuit and lightning protection. Powerlines, including trolley wires, and telephone circuits shall be protected against short circuits and lightning. ...

Design of An Energy Efficient Hydraulic Regenerative circuit

Science.gov (United States)

Ramesh, S.; Ashok, S. Denis; Nagaraj, Shanmukha; Adithyakumar, C. R.; Reddy, M. Lohith Kumar; Naulakha, Niranjan Kumar

2018-02-01

Increasing cost and power demand, leads to evaluation of new method to increase through productivity and help to solve the power demands. Many researchers have break through to increase the efficiency of a hydraulic power pack, one of the promising methods is the concept of regenerative. The objective of this research work is to increase the efficiency of a hydraulic circuit by introducing a concept of regenerative circuit. A Regenerative circuit is a system that is used to speed up the extension stroke of the double acting single rod hydraulic cylinder. The output is connected to the input in the directional control value. By this concept, increase in velocity of the piston and decrease the cycle time. For the research, a basic hydraulic circuit and a regenerative circuit are designated and compared both with their results. The analysis was based on their time taken for extension and retraction of the piston. From the detailed analysis of both the hydraulic circuits, it is found that the efficiency by introducing hydraulic regenerative circuit increased by is 5.3%. The obtained results conclude that, implementing hydraulic regenerative circuit in a hydraulic power pack decreases power consumption, reduces cycle time and increases productivity in a longer run.

Circuit drawings in electrical energy technology. 6. rev. ed.

International Nuclear Information System (INIS)

Weinert, J.

1991-01-01

This book contains a survey of the most important standards for graphical symbols and circuit documents for the area of electrical energy technology; it explains the circuit symbols in their construction and in their material and mental contents of terms; it contains a comparison of the circuit symbols from the DIN standards and the new DINTEC symbols taken from harmonisation, produced by arrangement in the picture column with the addition of the letters IEC; it contains a selection of circuit symbols of the IEC, USA, Canada and Great Britain; it supplements the necessary standards for producing circuit documents by extracts and references; it shows examples for the symbols of electrical equipment by using circuit symbols; it develops and explains the various kinds of representation of electrical circuits by circuit diagrams; it leads to reading and understanding the functioning of circuits by descriptions of functions; it gives examples of applications for designing and producing circuit documents, as used in practice; it contributes to arranging electrical plant according to the 'recognised rules of electrical engineering' and increasing safety by reference to the DIN-VDE regulations connected with representation, and it is a great help in designing electrical energy plant by its technical and electrical data. (orig.) [de

Microwave integrated circuits for space applications

Science.gov (United States)

Leonard, Regis F.; Romanofsky, Robert R.

1991-01-01

Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

Josephson Circuits as Vector Quantum Spins

Science.gov (United States)

Samach, Gabriel; Kerman, Andrew J.

While superconducting circuits based on Josephson junction technology can be engineered to represent spins in the quantum transverse-field Ising model, no circuit architecture to date has succeeded in emulating the vector quantum spin models of interest for next-generation quantum annealers and quantum simulators. Here, we present novel Josephson circuits which may provide these capabilities. We discuss our rigorous quantum-mechanical simulations of these circuits, as well as the larger architectures they may enable. This research was funded by the Office of the Director of National Intelligence (ODNI) and the Intelligence Advanced Research Projects Activity (IARPA) under Air Force Contract No. FA8721-05-C-0002. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of ODNI, IARPA, or the US Government.

New equivalent lumped electrical circuit for piezoelectric transformers.

Science.gov (United States)

Gonnard, Paul; Schmitt, P M; Brissaud, Michel

2006-04-01

A new equivalent circuit is proposed for a contour-vibration-mode piezoelectric transformer (PT). It is shown that the usual lumped equivalent circuit derived from the conventional Mason approach is not accurate. The proposed circuit, built on experimental measurements, makes an explicit difference between the elastic energies stored respectively on the primary and secondary parts. The experimental and theoretical resonance frequencies with the secondary in open or short circuit are in good agreement as well as the output "voltage-current" characteristic and the optimum efficiency working point. This circuit can be extended to various PT configurations and appears to be a useful tool for modeling electronic devices that integrate piezoelectric transformers.

Existence and global exponential stability of periodic solution to BAM neural networks with periodic coefficients and continuously distributed delays

International Nuclear Information System (INIS)

Zhou Tiejun; Chen Anping; Zhou Yuyuan

2005-01-01

By using the continuation theorem of coincidence degree theory and Liapunov function, we obtain some sufficient criteria to ensure the existence and global exponential stability of periodic solution to the bidirectional associative memory (BAM) neural networks with periodic coefficients and continuously distributed delays. These results improve and generalize the works of papers [J. Cao, L. Wang, Phys. Rev. E 61 (2000) 1825] and [Z. Liu, A. Chen, J. Cao, L. Huang, IEEE Trans. Circuits Systems I 50 (2003) 1162]. An example is given to illustrate that the criteria are feasible

Existence and global exponential stability of periodic solution to BAM neural networks with periodic coefficients and continuously distributed delays

Science.gov (United States)

Zhou, distributed delays [rapid communication] T.; Chen, A.; Zhou, Y.

2005-08-01

By using the continuation theorem of coincidence degree theory and Liapunov function, we obtain some sufficient criteria to ensure the existence and global exponential stability of periodic solution to the bidirectional associative memory (BAM) neural networks with periodic coefficients and continuously distributed delays. These results improve and generalize the works of papers [J. Cao, L. Wang, Phys. Rev. E 61 (2000) 1825] and [Z. Liu, A. Chen, J. Cao, L. Huang, IEEE Trans. Circuits Systems I 50 (2003) 1162]. An example is given to illustrate that the criteria are feasible.

FPGA based mixed-signal circuit novel testing techniques

International Nuclear Information System (INIS)

Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

2013-01-01

Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

A fast circuit analysis program based on microcomputer

International Nuclear Information System (INIS)

Hu Guoji

1988-01-01

A fast circuit analysis program (FCAP) is introduced. The program may be used to analyse DC operating point, frequency and transient response of fast circuit. The feature is that the model of active element is not specified. Users may choose one of many equivalent circuits. Written in FORTRAN 77, FCAP can be run on IBM PC and its compatible computers. It can be used as an assistant tool of analysis and design for fast circuits

Semiconductors integrated circuit design for manufacturability

CERN Document Server

Balasinki, Artur

2011-01-01

Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

Theory of circuit block switch-off

Directory of Open Access Journals (Sweden)

S. Henzler

2004-01-01

Full Text Available Switching-off unused circuit blocks is a promising approach to supress static leakage currents in ultra deep sub-micron CMOS digital systems. Basic performance parameters of Circuit Block Switch-Off (CBSO schemes are defined and their dependence on basic circuit parameters is estimated. Therefore the design trade-off between strong leakage suppression in idle mode and adequate dynamic performance in active mode can be supported by simple analytic investigations. Additionally, a guideline for the estimation of the minimum time for which a block deactivation is useful is derived.