WorldWideScience

Sample records for delay circuits

  1. The Limitations to Delay-Insensitivity in Asynchronous Circuits

    National Research Council Canada - National Science Library

    Martin, Alain J

    1990-01-01

    ... produced are delay-insensitive (DI). A digital circuit is DI when its correct operation is independent of the delays in operators and in the wires connecting the operators, except that the delays are finite and positive...

  2. Statistical delay estimation in digital circuits using VHDL

    Directory of Open Access Journals (Sweden)

    Milić Miljana Lj.

    2014-01-01

    Full Text Available The most important feature of modern integrated circuit is the speed. It depends on circuit's delay. For the design of high-speed digital circuits, it is necessary to evaluate delays in the earliest stages of design, thus making it easy to modify and redesign a circuit if it's too slow. This paper gives an approach for efficient delay estimation in the describing phase of the circuit design. The method can statistically estimate the minimum and maximum delay of all possible paths and signal transitions in the circuit, considering the practical implementation of circuits, and information about the parameters' tolerances. The method uses a VHDL description and is verified on ISCAS85 benchmark circuits. Matlab was used for data processing.

  3. Design of delay insensitive circuits using multi-ring structures

    DEFF Research Database (Denmark)

    Sparsø, Jens; Staunstrup, Jørgen; Dantzer-Sørensen, Michael

    1992-01-01

    The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined...

  4. Programmable delay unit incorporating a semi-custom integrated circuit

    International Nuclear Information System (INIS)

    Linstadt, E.

    1985-04-01

    The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

  5. Hopf bifurcation analysis of Chen circuit with direct time delay feedback

    International Nuclear Information System (INIS)

    Hai-Peng, Ren; Wen-Chao, Li; Ding, Liu

    2010-01-01

    Direct time delay feedback can make non-chaotic Chen circuit chaotic. The chaotic Chen circuit with direct time delay feedback possesses rich and complex dynamical behaviours. To reach a deep and clear understanding of the dynamics of such circuits described by delay differential equations, Hopf bifurcation in the circuit is analysed using the Hopf bifurcation theory and the central manifold theorem in this paper. Bifurcation points and bifurcation directions are derived in detail, which prove to be consistent with the previous bifurcation diagram. Numerical simulations and experimental results are given to verify the theoretical analysis. Hopf bifurcation analysis can explain and predict the periodical orbit (oscillation) in Chen circuit with direct time delay feedback. Bifurcation boundaries are derived using the Hopf bifurcation analysis, which will be helpful for determining the parameters in the stabilisation of the originally chaotic circuit

  6. Delay-area trade-off for MPRM circuits based on hybrid discrete particle swarm optimization

    International Nuclear Information System (INIS)

    Jiang Zhidi; Wang Zhenhai; Wang Pengjun

    2013-01-01

    Polarity optimization for mixed polarity Reed—Muller (MPRM) circuits is a combinatorial issue. Based on the study on discrete particle swarm optimization (DPSO) and mixed polarity, the corresponding relation between particle and mixed polarity is established, and the delay-area trade-off of large-scale MPRM circuits is proposed. Firstly, mutation operation and elitist strategy in genetic algorithm are incorporated into DPSO to further develop a hybrid DPSO (HDPSO). Then the best polarity for delay and area trade-off is searched for large-scale MPRM circuits by combining the HDPSO and a delay estimation model. Finally, the proposed algorithm is testified by MCNC Benchmarks. Experimental results show that HDPSO achieves a better convergence than DPSO in terms of search capability for large-scale MPRM circuits. (semiconductor integrated circuits)

  7. A programmable delay unit incorporating a semi-custom integrated circuit

    International Nuclear Information System (INIS)

    Linstadt, E.

    1985-01-01

    The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

  8. A new time-digital convert circuit based on digital delay line

    International Nuclear Information System (INIS)

    Liu Haifeng; Guo Ying; Zhang Zhi

    2004-01-01

    An introduction of a new method of time-digital convert circuit based on digital delay line is given. High precision and good reliability can be realized when it is combined with traditional counting convert method in the measurement of large scale pulse width and low frequency self-excitation oscillator. (authors)

  9. Chaos in the fractional order logistic delay system: Circuit realization and synchronization

    International Nuclear Information System (INIS)

    Baskonus, Haci Mehmet; Hammouch, Zakia; Mekkaoui, Toufik; Bulut, Hasan

    2016-01-01

    In this paper, we present a numerical study and a circuit design to prove existence of chaos in the fractional order Logistic delay system. In addition, we investigate an active control synchronization scheme in this system. Numerical and cicruit simulations show the effectiveness and feasibility of this method.

  10. Automatic test pattern generation for stuck-at and delay faults in combinational circuits

    International Nuclear Information System (INIS)

    Kim, Dae Sik

    1998-02-01

    The present studies are developed to propose the automatic test pattern generation (ATG) algorithms for combinational circuits. These ATG algorithms are realized in two ATG programs: One is the ATG program for stuck-at fault and the other one for delay faults. In order to accelerate the ATG process, these two ATG programs have a common feature (the search method based on the concept of the degree of freedom), whereas only ATG program for the delay fault utilizes the 19-valued logic, a type of composite valued logic. This difference between two ATG programs results from the difference of the target fault. Accelerating the ATG process is indispensable for improving the ATG algorithms. This acceleration is mainly achieved by reducing the number of the unnecessary backtrackings, making the earlier detection of the conflicts, and shortening the computation time between the implication. Because of this purpose, the developed ATG programs include the new search method based on the concept of the degree of freedom (DF). The DF concept, computed directly and easily from the system descriptions such as types of gates and their interconnections, is the criterion to decide which, among several alternate lines' logic values required along each path, promises to be the most effective in order to accelerate and improve the ATG process. This DF concept is utilized to develop and improve both of ATG programs for stuck-at and delay faults in combinational circuits. In addition to improving the ATG process, reducing number of test pattern is indispensable for testing the delay faults because the size of the delay faults grows rapidly as increasing the size of the circuit. In order to improve the compactness of the test set, 19-valued logic are derived. Unlike other TG logic systems, 19-valued logic is utilized to generate the robustly hazard-free test pattern. This is achieved by using the basic 5-valued logic, proposed in this work, where the transition with no hazard is

  11. On mill flow rate and fineness control in cement grinding circuits: instability and delayed measurements

    International Nuclear Information System (INIS)

    Lepore, R.; Boulvin, M.; Renotte, C.; Remy, M.

    1999-01-01

    A control structure for the mill flow rate and the product fineness is designed, with the feed flow rate and the classifier characteristic as the manipulated variables. Experimental results from a plant highlight the instability of the grinding circuit. A model previously developed by the authors stresses the major influence of the classifier nonlinearities onto this instability. A cascade control structure has been designed and implemented on site. The measurements of the product fineness, sensitive to material grindability fluctuations, are randomly time-delayed. The control structure uses a fineness estimator based on an adaptive scheme and a time delay compensator. (author)

  12. Estimation of leakage power and delay in CMOS circuits using parametric variation

    Directory of Open Access Journals (Sweden)

    Preeti Verma

    2016-09-01

    Full Text Available With the advent of deep-submicron technologies, leakage power dissipation is a major concern for scaling down portable devices that have burst-mode type integrated circuits. In this paper leakage reduction technique HTLCT (High Threshold Leakage Control Transistor is discussed. Using high threshold transistors at the place of low threshold leakage control transistors, result in more leakage power reduction as compared to LCT (leakage control transistor technique but at the scarifies of area and delay. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. It is found that the leakage power dissipation increases with increasing temperature, supply voltage and aspect ratio. However, opposite pattern is noticed for the propagation delay. Leakage power dissipation for LCT NAND gate increases up to 14.32%, 6.43% and 36.21% and delay decreases by 22.5%, 42% and 9% for variation of temperature, supply voltage and aspect ratio. Maximum peak of equivalent output noise is obtained as 127.531 nV/Sqrt(Hz at 400 mHz.

  13. Small Delay and High Performance AD/DA Converters of Lease Circuit System for AM&FM Broadcast

    Science.gov (United States)

    Takato, Kenji; Suzuki, Dai; Ishii, Takashi; Kobayashi, Masato; Yamada, Hirokazu; Amano, Shigeru

    Many AM&FM broadcasting stations in Japan are connected by the leased circuit system of NTT. Small delay and high performance AD/DA converter was developed for the system. The system was designed based on ITU-T J.41 Recommendation (384kbps), the transmission signal is 11bit-32 kHz where the Gain-frequency characteristics between 40Hz to 15kHz have to be quite flat. The ΔΣAD/DA converter LSIs for audio application in the market today realize very high performance. However the performance is not enough for the leased circuit system. We found that it is not possible to meet the delay and Gain-frequency requirements only by using ΔΣAD/DA converter LSI in normal operation, because 15kHz the highest frequency and 16kHz Nyquist frequency are too close, therefore there are aliasing around Nyquist frequency. In this paper, we designed AD/DA architecture having small delay (1msec) and sharp cut off LPF (100dB attenuation at 16kHz, and 1500dB/Oct from 15kHz to 16kHz) by operating ΔΣAD/DA converter LSIs over-sampling rate such as 128kHz and by adding custom LPF designed Infinite Impulse Response (IIR) filter. The IIR filter is a 16th order elliptic type and it is consist of eight biquad filters in series. We described how to evaluate the stability of IIR filter theoretically by calculating frequency response, Pole and Zero Layout and impulse response of each biquad filter, and experimentally by adding overflow detection circuit on each filters and input overlord signal.

  14. Structural and composition investigations at delayered locations of low k integrated circuit device by gas-assisted focused ion beam

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Dandan, E-mail: dandan.wang@globalfoundries.com; Kee Tan, Pik; Yamin Huang, Maggie; Lam, Jeffrey; Mai, Zhihong [Technology Development Department, GLOBALFOUNDRIES Singapore Pte. Ltd., 60 Woodlands Industrial Park D, Street 2, Singapore 738406 (Singapore)

    2014-05-15

    The authors report a new delayering technique – gas-assisted focused ion beam (FIB) method and its effects on the top layer materials of integrated circuit (IC) device. It demonstrates a highly efficient failure analysis with investigations on the precise location. After removing the dielectric layers under the bombardment of an ion beam, the chemical composition of the top layer was altered with the reduced oxygen content. Further energy-dispersive x-ray spectroscopy and Fourier transform infrared analysis revealed that the oxygen reduction lead to appreciable silicon suboxide formation. Our findings with structural and composition alteration of dielectric layer after FIB delayering open up a new insight avenue for the failure analysis in IC devices.

  15. A self-adjusting delay circuit for pixel read-out chips

    International Nuclear Information System (INIS)

    Raith, B.

    1997-01-01

    A simple concept for automatic adjustment of important VLSI-circuit properties was proposed in (Fischer and Joens, Nucl. Instr. and. Meth.). As an application, a self-adjusting monoflop is reviewed, and detailed measurements are discussed regarding a possible implementation in the LHC 1 read-out chip for the ATLAS experiment (ATLAS Internal Note, 1995). (orig.)

  16. Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

    Directory of Open Access Journals (Sweden)

    Mohammed Darmi

    2017-10-01

    Full Text Available As we increasingly use advanced technology nodes to design integrated circuits (ICs, physical designers and electronic design automation (EDA providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR. An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics’ physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS and total negative slack (TNS improved up to 13% and 56%, respectively, compared to the baseline flow.

  17. Analysis of the effects of time delay in clock recovery circuits based on Phase-locked loops

    DEFF Research Database (Denmark)

    Zibar, Darko; Oxenløwe, Leif Katsuo; Clausen, Anders

    2004-01-01

    Influence of time delay in a balanced optical phase-locked loops (OPLL) with a proportional integrator (Pl) filter is investigated using a delayed differential equation (DDE) is investigated. The limitations, which a time delay imposes on the Pl filter bandwidth, at increasing values of loop gain...

  18. Pulse advancement and delay in an integrated optical two-port ring-resonator circuit: direct experimental observations

    NARCIS (Netherlands)

    Uranus, H.P.; Zhuang, L.; Roeloffzen, C.G.H.; Hoekstra, Hugo

    We report experimental observations of the negative-group-velocity (v_g) phenomenon in an integrated-optical two-port ring-resonator circuit. We demonstrate that when the v_g is negative, the (main) peak of output pulse appears earlier than the peak of a reference pulse, while for a positive v_g,

  19. A chaotic jerk system with non-hyperbolic equilibrium: Dynamics, effect of time delay and circuit realisation

    Science.gov (United States)

    Rajagopal, Karthikeyan; Pham, Viet-Thanh; Tahir, Fadhil Rahma; Akgul, Akif; Abdolmohammadi, Hamid Reza; Jafari, Sajad

    2018-04-01

    The literature on chaos has highlighted several chaotic systems with special features. In this work, a novel chaotic jerk system with non-hyperbolic equilibrium is proposed. The dynamics of this new system is revealed through equilibrium analysis, phase portrait, bifurcation diagram and Lyapunov exponents. In addition, we investigate the time-delay effects on the proposed system. Realisation of such a system is presented to verify its feasibility.

  20. Peak reading detector circuit

    International Nuclear Information System (INIS)

    Courtin, E.; Grund, K.; Traub, S.; Zeeb, H.

    1975-01-01

    The peak reading detector circuit serves for picking up the instants during which peaks of a given polarity occur in sequences of signals in which the extreme values, their time intervals, and the curve shape of the signals vary. The signal sequences appear in measuring the foetal heart beat frequence from amplitude-modulated ultrasonic, electrocardiagram, and blood pressure signals. In order to prevent undesired emission of output signals from, e. g., disturbing intermediate extreme values, the circuit consists of the series connections of a circuit to simulate an ideal diode, a strong unit, a discriminator for the direction of charging current, a time-delay circuit, and an electronic switch lying in the decharging circuit of the storage unit. The time-delay circuit thereby causes storing of a preliminary maximum value being used only after a certain time delay for the emission of the output signal. If a larger extreme value occurs during the delay time the preliminary maximum value is cleared and the delay time starts running anew. (DG/PB) [de

  1. Picosecond resolution programmable delay line

    International Nuclear Information System (INIS)

    Suchenek, Mariusz

    2009-01-01

    The note presents implementation of a programmable delay line for digital signals. The tested circuit has a subnanosecond delay range programmable with a resolution of picoseconds. Implementation of the circuit was based on low-cost components, easily available on the market. (technical design note)

  2. Oscillator circuits

    CERN Document Server

    Graf, Rudolf F

    1996-01-01

    This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing

  3. Measuring circuits

    CERN Document Server

    Graf, Rudolf F

    1996-01-01

    This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings

  4. Precise delay measurement through combinatorial logic

    Science.gov (United States)

    Burke, Gary R. (Inventor); Chen, Yuan (Inventor); Sheldon, Douglas J. (Inventor)

    2010-01-01

    A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the "LUT delay chain"), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

  5. Hybdrid integral circuit for proportional chambers

    International Nuclear Information System (INIS)

    Yanik, R.; Khudy, M.; Povinets, P.; Strmen', P.; Grabachek, Z.; Feshchenko, A.A.

    1978-01-01

    Outlined briefly are a hybrid integrated circuit of the channel. One channel contains an input amplifier, delay circuit, and memory register on the base of the D-type flip-flop and controlled by the recording gate pulse. Provided at the output of the channel is a readout gating circuit. Presented are the flowsheet of the channel, the shaper amplifier and logical channel. At present the logical circuit was accepted for manufacture

  6. Estimating Delays In ASIC's

    Science.gov (United States)

    Burke, Gary; Nesheiwat, Jeffrey; Su, Ling

    1994-01-01

    Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.

  7. Resonance circuits for adiabatic circuits

    Directory of Open Access Journals (Sweden)

    C. Schlachta

    2003-01-01

    Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

  8. Programmable delay circuit for sparker signal analysis

    Digital Repository Service at National Institute of Oceanography (India)

    Pathak, D.

    The sparker echo signal had been recorded along with the EPC recorder trigger on audio cassettes in a dual channel analog recorder. The sparker signal in the analog form had to be digitised for further signal processing techniques to be performed...

  9. Development of True Time Delay Circuits

    Science.gov (United States)

    2014-06-13

    public release Distribution is unlimited DATA SHEET SKY65014-70LF: 0.1-7.0 GHz InGaP Cascadable Amplifier Applications • Wireless infrastructure: WLAN ...decoupling network out of band. For low frequency applications , R1 may be used to conveniently limit supply current on the Evaluation Board. The Evaluation...additional information, refer to the Skyworks Application Note, Solder Reflow Information, document number 200164. Care must be taken when attaching this

  10. Electronic circuit encyclopedia 2

    International Nuclear Information System (INIS)

    Park, Sun Ho

    1992-10-01

    This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

  11. Electronic circuit encyclopedia 2

    Energy Technology Data Exchange (ETDEWEB)

    Park, Sun Ho

    1992-10-15

    This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.

  12. Controllable circuit

    DEFF Research Database (Denmark)

    2010-01-01

    A switch-mode power circuit comprises a controllable element and a control unit. The controllable element is configured to control a current in response to a control signal supplied to the controllable element. The control unit is connected to the controllable element and provides the control...

  13. Circuit Training.

    Science.gov (United States)

    Nelson, Jane B.

    1998-01-01

    Describes a research-based activity for high school physics students in which they build an LC circuit and find its resonant frequency of oscillation using an oscilloscope. Includes a diagram of the apparatus and an explanation of the procedures. (DDR)

  14. Low cost design of microprocessor EDAC circuit

    International Nuclear Information System (INIS)

    Hao Li; Yu Lixin; Peng Heping; Zhuang Wei

    2015-01-01

    An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)

  15. Temperature Dependent Wire Delay Estimation in Floorplanning

    DEFF Research Database (Denmark)

    Winther, Andreas Thor; Liu, Wei; Nannarelli, Alberto

    2011-01-01

    Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability. In this w......Due to large variations in temperature in VLSI circuits and the linear relationship between metal resistance and temperature, the delay through wires of the same length can be different. Traditional thermal aware floorplanning algorithms use wirelength to estimate delay and routability....... In this work, we show that using wirelength as the evaluation metric does not always produce a floorplan with the shortest delay. We propose a temperature dependent wire delay estimation method for thermal aware floorplanning algorithms, which takes into account the thermal effect on wire delay. The experiment...

  16. Delayed fission

    Energy Technology Data Exchange (ETDEWEB)

    Hatsukawa, Yuichi [Japan Atomic Energy Research Inst., Tokai, Ibaraki (Japan). Tokai Research Establishment

    1997-07-01

    Delayed fission is a nuclear decay process that couples {beta} decay and fission. In the delayed fission process, a parent nucleus undergoes {beta} decay and thereby populates excited states in the daughter. If these states are of energies comparable to or greater than the fission barrier of the daughter, then fission may compete with other decay modes of the excited states in the daughter. In this paper, mechanism and some experiments of the delayed fission will be discussed. (author)

  17. Scan cell design for enhanced delay fault testability

    NARCIS (Netherlands)

    van Brakel, Gerrit; van Brakel, G.; Xing, Yizi; Xing, Y.; Kerkhoff, Hans G.

    1992-01-01

    Problems in testing scannable sequential circuits for delay faults are addressed. Modifications to improve circuit controllability and observability for the testing of delay faults are implemented efficiently in a scan cell design. A layout on a gate array is designed and evaluated for this scan

  18. TECHNICAL DESIGN NOTE: Picosecond resolution programmable delay line

    Science.gov (United States)

    Suchenek, Mariusz

    2009-11-01

    The note presents implementation of a programmable delay line for digital signals. The tested circuit has a subnanosecond delay range programmable with a resolution of picoseconds. Implementation of the circuit was based on low-cost components, easily available on the market.

  19. Modeling delay in genetic networks: from delay birth-death processes to delay stochastic differential equations.

    Science.gov (United States)

    Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Bennett, Matthew R; Josić, Krešimir; Ott, William

    2014-05-28

    Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay.

  20. Modeling delay in genetic networks: From delay birth-death processes to delay stochastic differential equations

    Energy Technology Data Exchange (ETDEWEB)

    Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Ott, William [Department of Mathematics, University of Houston, Houston, Texas 77004 (United States); Bennett, Matthew R. [Department of Biochemistry and Cell Biology, Rice University, Houston, Texas 77204, USA and Institute of Biosciences and Bioengineering, Rice University, Houston, Texas 77005 (United States); Josić, Krešimir [Department of Mathematics, University of Houston, Houston, Texas 77004 (United States); Department of Biology and Biochemistry, University of Houston, Houston, Texas 77204 (United States)

    2014-05-28

    Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay.

  1. Modeling delay in genetic networks: From delay birth-death processes to delay stochastic differential equations

    International Nuclear Information System (INIS)

    Gupta, Chinmaya; López, José Manuel; Azencott, Robert; Ott, William; Bennett, Matthew R.; Josić, Krešimir

    2014-01-01

    Delay is an important and ubiquitous aspect of many biochemical processes. For example, delay plays a central role in the dynamics of genetic regulatory networks as it stems from the sequential assembly of first mRNA and then protein. Genetic regulatory networks are therefore frequently modeled as stochastic birth-death processes with delay. Here, we examine the relationship between delay birth-death processes and their appropriate approximating delay chemical Langevin equations. We prove a quantitative bound on the error between the pathwise realizations of these two processes. Our results hold for both fixed delay and distributed delay. Simulations demonstrate that the delay chemical Langevin approximation is accurate even at moderate system sizes. It captures dynamical features such as the oscillatory behavior in negative feedback circuits, cross-correlations between nodes in a network, and spatial and temporal information in two commonly studied motifs of metastability in biochemical systems. Overall, these results provide a foundation for using delay stochastic differential equations to approximate the dynamics of birth-death processes with delay

  2. UWB delay and multiply receiver

    Energy Technology Data Exchange (ETDEWEB)

    Dallum, Gregory E.; Pratt, Garth C.; Haugen, Peter C.; Romero, Carlos E.

    2013-09-10

    An ultra-wideband (UWB) delay and multiply receiver is formed of a receive antenna; a variable gain attenuator connected to the receive antenna; a signal splitter connected to the variable gain attenuator; a multiplier having one input connected to an undelayed signal from the signal splitter and another input connected to a delayed signal from the signal splitter, the delay between the splitter signals being equal to the spacing between pulses from a transmitter whose pulses are being received by the receive antenna; a peak detection circuit connected to the output of the multiplier and connected to the variable gain attenuator to control the variable gain attenuator to maintain a constant amplitude output from the multiplier; and a digital output circuit connected to the output of the multiplier.

  3. LOGIC CIRCUIT

    Science.gov (United States)

    Strong, G.H.; Faught, M.L.

    1963-12-24

    A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)

  4. Short- circuit tests of circuit breakers

    OpenAIRE

    Chorovský, P.

    2015-01-01

    This paper deals with short-circuit tests of low voltage electrical devices. In the first part of this paper, there are described basic types of short- circuit tests and their principles. Direct and indirect (synthetic) tests with more details are described in the second part. Each test and principles are explained separately. Oscilogram is obtained from short-circuit tests of circuit breakers at laboratory. The aim of this research work is to propose a test circuit for performing indirect test.

  5. Dynamics of Nonlinear Time-Delay Systems

    CERN Document Server

    Lakshmanan, Muthusamy

    2010-01-01

    Synchronization of chaotic systems, a patently nonlinear phenomenon, has emerged as a highly active interdisciplinary research topic at the interface of physics, biology, applied mathematics and engineering sciences. In this connection, time-delay systems described by delay differential equations have developed as particularly suitable tools for modeling specific dynamical systems. Indeed, time-delay is ubiquitous in many physical systems, for example due to finite switching speeds of amplifiers in electronic circuits, finite lengths of vehicles in traffic flows, finite signal propagation times in biological networks and circuits, and quite generally whenever memory effects are relevant. This monograph presents the basics of chaotic time-delay systems and their synchronization with an emphasis on the effects of time-delay feedback which give rise to new collective dynamics. Special attention is devoted to scalar chaotic/hyperchaotic time-delay systems, and some higher order models, occurring in different bran...

  6. Collective of mechatronics circuit

    International Nuclear Information System (INIS)

    1987-02-01

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  7. Collective of mechatronics circuit

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1987-02-15

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  8. Topological Acoustic Delay Line

    Science.gov (United States)

    Zhang, Zhiwang; Tian, Ye; Cheng, Ying; Wei, Qi; Liu, Xiaojun; Christensen, Johan

    2018-03-01

    Topological protected wave engineering in artificially structured media is at the frontier of ongoing metamaterials research that is inspired by quantum mechanics. Acoustic analogues of electronic topological insulators have recently led to a wealth of new opportunities in manipulating sound propagation with strikingly unconventional acoustic edge modes immune to backscattering. Earlier fabrications of topological insulators are characterized by an unreconfigurable geometry and a very narrow frequency response, which severely hinders the exploration and design of useful devices. Here we establish topologically protected sound in reconfigurable phononic crystals that can be switched on and off simply by rotating its three-legged "atoms" without altering the lattice structure. In particular, we engineer robust phase delay defects that take advantage of the ultrabroadband reflection-free sound propagation. Such topological delay lines serve as a paradigm in compact acoustic devices, interconnects, and electroacoustic integrated circuits.

  9. Circuit parties.

    Science.gov (United States)

    Guzman, R

    2000-03-01

    Circuit parties are extended celebrations, lasting from a day to a week, primarily attended by gay and bisexual men in their thirties and forties. These large-scale dance parties move from city to city and draw thousands of participants. The risks for contracting HIV during these parties include recreational drug use and unsafe sex. Limited data exists on the level of risk at these parties, and participants are skeptical of outside help because of past criticism of these events. Health care and HIV advocates can promote risk-reduction strategies with the cooperation of party planners and can counsel individuals to personally reduce their own risk. To convey the message, HIV prevention workers should emphasize positive and community-centered aspects of the parties, such as taking care of friends and avoiding overdose.

  10. Inductive circuit arrangements

    International Nuclear Information System (INIS)

    Mansfield, Peter; Coxon, R.J.

    1987-01-01

    A switched coil arrangement is connected in a bridge configuration of four switches S 1 , S 2 , S 3 and S 4 which are each shunted by diodes D 1 , D 2 , D 3 and D 4 so that current can flow in either direction through a coil L depending on the setting of the switches. A capacitor C is connected across the bridge through a switch S 5 to receive the inductive energy stored in coil L on breaking the current flow path through the coil. The electrostatic energy stored in capacitor C can then be used to supply current through the coil in the reverse direction either immediately or after a time delay. Coil L may be a superconductive coil. Losses in the circuit can be made up by a trickle charge of capacitor C from a separate supply V 2 . The device may be used in nuclear magnetic resonance imaging. (author)

  11. Commutation circuit for an HVDC circuit breaker

    Science.gov (United States)

    Premerlani, William J.

    1981-01-01

    A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.

  12. Installations having pressurised fluid circuits

    International Nuclear Information System (INIS)

    Rigg, S.; Grant, J.

    1977-01-01

    Reference is made to nuclear installations having pressurised coolant flow circuits. Breaches in such circuits may quickly result in much damage to the plant. Devices such as non-return valves, orifice plates, and automatically operated shut-off valves have been provided to prevent or reduce fluid flow through a breached pipe line, but such devices have several disadvantages; they may present large restrictions to normal flow of coolant, and may depend on the operation of ancillary equipment, with consequent delay in bringing them into operation in an emergency. Other expedients that have been adopted to prevent or reduce reverse flow through an upstream breach comprise various forms of hydraulic counter flow brakes. The arrangement described has at least one variable fluid brake comprising a fluidic device connected into a duct in the pressurised circuit, the device having an inlet, an outlet, a vortex chamber between the inlet and outlet, a control jet for introducing fluid into the vortex chamber, connections communicating the inlet and the outlet into one part of the circuit and the control jet into another region at a complementary pressure so that, in the event of a breach in the circuit in one region, fluid passes from the other region to enter the vortex chamber to stimulate pressure to create a flow restricting vortex in the chamber that reduces flow through the breach. The system finds particular application to stream generating pressure tube reactors, such as the steam generating heavy water reactor at UKAEA, Winfrith. (U.K.)

  13. Delayed Ejaculation

    Science.gov (United States)

    ... cases, it is due to a combination of physical and psychological concerns. Psychological causes of delayed ejaculation include: Depression, anxiety or other mental health conditions Relationship problems due to stress, poor communication ...

  14. Delayed growth

    Science.gov (United States)

    ... Slow rate of growth; Retarded growth and development; Growth delay Images Toddler development References Cooke DW, Divall SA, Radovick S. Normal and aberrant growth in children. In: Melmed S, Polonsky KS, Larsen PR, ...

  15. Analog circuit design designing dynamic circuit response

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

  16. Trigger circuit

    International Nuclear Information System (INIS)

    Verity, P.R.; Chaplain, M.D.; Turner, G.D.J.

    1984-01-01

    A monostable trigger circuit comprises transistors TR2 and TR3 arranged with their collectors and bases interconnected. The collector of the transistor TR2 is connected to the base of transistor TR3 via a capacitor C2 the main current path of a grounded base transistor TR1 and resistive means R2,R3. The collector of transistor TR3 is connected to the base of transistor TR2 via resistive means R6, R7. In the stable state all the transistors are OFF, the capacitor C2 is charged, and the output is LOW. A positive pulse input to the base of TR2 switches it ON, which in turn lowers the voltage at points A and B and so switches TR1 ON so that C2 can discharge via R2, R3, which in turn switches TR3 ON making the output high. Thus all three transistors are latched ON. When C2 has discharged sufficiently TR1 switches OFF, followed by TR3 (making the output low again) and TR2. The components C1, C3 and R4 serve to reduce noise, and the diode D1 is optional. (author)

  17. Set of CAMAC modules on the base of large integrated circuits for an accelerator synchronization system

    International Nuclear Information System (INIS)

    Glejbman, Eh.M.; Pilyar, N.V.

    1986-01-01

    Parameters of functional moduli in the CAMAC standard developed for accelerator synchronization system are presented. They comprise BZN-8K and BZ-8K digital delay circuits, timing circuit and pulse selection circuit. In every module 3 large integral circuits of KR 580 VI53 type programmed timer, circuits of the given system bus bar interface with bus bars of crate, circuits of data recording control, 2 peripheric storage devices, circuits of initial regime setting, input and output shapers, circuits of installation and removal of blocking in channels are used

  18. Synchronization circuit for shaping electron beam picosecond pulses

    International Nuclear Information System (INIS)

    Pavlov, Yu.S.; Solov'ev, N.G.; Tomnikov, A.P.

    1985-01-01

    A fast response circuit of modulator trigger pulse synchronization of a deflector of the electron linear accelerator at 13 MeV with the given phase of HF-voltage is described. The circuit is constructed using K500 and K100 integrated emitter-coupled logics circuits. Main parameters of a synchropulse are duration of 20-50 ns, pulse rise time of 1-5 ns, pulse amplitude >=10 V, delay instability of a trigger pulse <=+-0.05 ns. A radiopulse with 3 μs duration, 5 V amplitude and 400 Hz frequency enters the circuit input. The circuit can operate at both pulsed operation and continuous modes

  19. Control circuits for the 1.3 GeV electron synchrotron

    International Nuclear Information System (INIS)

    Asaoka, S.; Shiino, K.; Yoshioka, M.; Norimura, K.

    1980-01-01

    Following control circuits for the 1.3 GeV electron synchrotron, Institute for Nuclear Study, University of Tokyo, have been designed and constructed. 1. Variable delay circuits for the timing pulse of the synchrotron. 2. An alarm circuit for sputter ion pumps. 3. A sample and hold circuit for digital display and computer control of the beam intensity. This report describes detailes of the circuits and their specificatons. (author)

  20. Timing Analysis of Genetic Logic Circuits using D-VASim

    DEFF Research Database (Denmark)

    Baig, Hasan; Madsen, Jan

    and propagation delay analysis of single as well as cascaded geneticlogic circuits can be performed. D-VASim allows user to change the circuit parameters during runtime simulation to observe its effectson circuit’s timing behavior. The results obtained from D-VASim can be used not only to characterize the timing...... delay analysis may play a very significant role in the designing of genetic logic circuits. In thisdemonstration, we present the capability of D-VASim (Dynamic Virtual Analyzer and Simulator) to perform the timing and propagationdelay analysis of genetic logic circuits. Using D-VASim, the timing...... behavior of geneticlogic circuits but also to analyze the timing constraints of cascaded genetic logic circuits....

  1. Developmental delay

    Science.gov (United States)

    Nutrition support is essential for the care of the child with developmental delay. After a thorough evaluation, an individualized intervention plan that accounts for the child’s nutrition status, feeding ability, and medical condition may be determined. Nutrition assessments may be performed at leas...

  2. An electronic implementation for Liao's chaotic delayed neuron model with non-monotonous activation function

    International Nuclear Information System (INIS)

    Duan Shukai; Liao Xiaofeng

    2007-01-01

    A new chaotic delayed neuron model with non-monotonously increasing transfer function, called as chaotic Liao's delayed neuron model, was recently reported and analyzed. An electronic implementation of this model is described in detail. At the same time, some methods in circuit design, especially for circuit with time delayed unit and non-monotonously increasing activation unit, are also considered carefully. We find that the dynamical behaviors of the designed circuits are closely similar to the results predicted by numerical experiments

  3. Solid-state circuits

    CERN Document Server

    Pridham, G J

    2013-01-01

    Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

  4. Circuit analysis for dummies

    CERN Document Server

    Santiago, John

    2013-01-01

    Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help

  5. Current limiter circuit system

    Science.gov (United States)

    Witcher, Joseph Brandon; Bredemann, Michael V.

    2017-09-05

    An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.

  6. Superconducting flux flow digital circuits

    International Nuclear Information System (INIS)

    Martens, J.S.; Zipperian, T.E.; Hietala, V.M.; Ginley, D.S.; Tigges, C.P.; Phillips, J.M.; Siegal, M.P.

    1993-01-01

    The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-μm linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps, and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic

  7. Electron commutator on integrated circuits

    International Nuclear Information System (INIS)

    Demidenko, V.V.

    1975-01-01

    The scheme and the parameters of an electron 16-channel contactless commutator based entirely on integrated circuits are described. The device consists of a unit of analog keys based on field-controlled metal-insulator-semiconductor (m.i.s.) transistors, operation amplifier comparators controlling these keys, and a level distributor. The distributor is based on a ''matrix'' scheme and comprises two ring-shaped shift registers plugged in series and a decoder base on two-input logical elements I-NE. The principal dynamical parameters of the circuit are as follows: the control signal delay in the distributor. 50 nsec; the total channel switch-over time, 500-600 nsec. The commutator transmits both constant signals and pulses whose duration reaches tens of nsec. The commutator can be used in data acquisition and processing systems, for shaping complicated signals (for example), (otherwise signals), for simultaneous oscillographing of several signals, and so forth [ru

  8. Managing contamination delay to improve Timing Speculation architectures

    Directory of Open Access Journals (Sweden)

    Naga Durga Prasad Avirneni

    2016-08-01

    Full Text Available Timing Speculation (TS is a widely known method for realizing better-than-worst-case systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that increasing the lengths of short paths of the circuit increases the effectiveness of TS, leading to performance improvement. Also, we propose an algorithm to efficiently add delay buffers to selected short paths while keeping down the area penalty. We present our algorithm results for ISCAS-85 suite and show that it is possible to increase the circuit contamination delay by up to 30% without affecting the propagation delay. We also explore the possibility of increasing short path delays further by relaxing the constraint on propagation delay and analyze the performance impact.

  9. Miniaturization of Josephson logic circuits

    International Nuclear Information System (INIS)

    Ko, H.; Van Duzer, T.

    1985-01-01

    The performances of Current Injection Logic (CIL) and Resistor Coupled Josephson Logic (RCJL) have been evaluated for minimum features sizes ranging from 5 μm to 0.2 μm. The logic delay is limited to about 10 ps for both the CIL AND gate and the RCJL OR gate biased at 70% of maximum bias current. The maximum circuit count on an 6.35 x 6.35 chip is 13,000 for CIL gates and 20,000 for RCJL gates. Some suggestions are given for further improvements

  10. Multiwire proportional counter (lecture by an electromagnetic delay line)

    International Nuclear Information System (INIS)

    Bruere-Dawson, R.

    1989-01-01

    For track localisation of ionizing particles with multiwire proportional chamber, an electronic chain including amplifying, shaping and memorizing circuits is required for each wire. In order to lower the cost of this type of detector, an electromagnetic delay line is proposed among various possibilities. In this paper, different coupling modes between chamber and delay line are studied with their respective advantages. The realization of one meter long delay line with a unit delay time of 15 ns per cm is also presented [fr

  11. Circuit, especially for digital nuclear gyroscope systems

    International Nuclear Information System (INIS)

    Lowdenslager, J.R.

    1974-01-01

    The circuit with at least one or two spin generator shows a digital phase synchronizing loop in solid-state construction without movable mechanical parts. It is stable, may be turned in one direction any number of times without saturation, and also remains phase-synchronized when input signals are turned off. For this purpose, crystal oscillators with certain resonance frequencies are used. The spin generators are coupled at the outled side with filtering, squaring, and differential connections generating control impulses synchronous to the spin generators. Step divider circuits are connected to the oscillators, which act upon flip-flop registers. This is controlled by the filtering, squaring, and differential connections. Furthermore, field proportional control circuits with registers, advancing and delay circuits are provided, the registers being connected at the outlet side with digital adders and subtractors. The digital adder serves inertial-related purposes. (DG) [de

  12. Intuitive analog circuit design

    CERN Document Server

    Thompson, Marc

    2013-01-01

    Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi

  13. The circuit designer's companion

    CERN Document Server

    Williams, Tim

    1991-01-01

    The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll

  14. Electronic devices and circuits

    CERN Document Server

    Pridham, Gordon John

    1972-01-01

    Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of

  15. Delayed Puberty

    DEFF Research Database (Denmark)

    Kolby, Nanna; Busch, Alexander Siegfried; Juul, Anders

    2017-01-01

    . The underlying reasons for the large variation in the age at pubertal onset are not fully established; however, nutritional status and socioeconomic and environmental factors are known to be influencing, and a significant amount of influencing genetic factors have also been identified. The challenges...... optimal in discriminating especially CDGP from HH. Management of the delayed puberty depends on the etiology. For boys with CDGP an observational period will often reveal imminent puberty. If puberty is not progressing spontaneously, sex steroid replacement is effective in stimulating the development...

  16. Electrical Circuits and Water Analogies

    Science.gov (United States)

    Smith, Frederick A.; Wilson, Jerry D.

    1974-01-01

    Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)

  17. Global synchronization criteria with channel time-delay for chaotic time-delay system

    International Nuclear Information System (INIS)

    Sun Jitao

    2004-01-01

    Based on the Lyapunov stabilization theory, matrix measure, and linear matrix inequality (LMIs), this paper studies the chaos synchronization of time-delay system using the unidirectional linear error feedback coupling with time-delay. Some generic conditions of chaos synchronization with time-delay in the transmission channel is established. The chaotic Chua's circuit is used for illustration, where the coupling parameters are determined according to the criteria under which the global chaos synchronization of the time-delay coupled systems is achieved

  18. Electric circuits essentials

    CERN Document Server

    REA, Editors of

    2012-01-01

    REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph

  19. Non-noise instabilities in oscilloscope trigger circuits

    International Nuclear Information System (INIS)

    Burd, Aleksander

    2011-01-01

    The paper discusses two phenomena called tremor, which result in incorrect operation of the oscilloscope trigger circuits. Both of them change delays introduced by the trigger circuit, resulting in horizontal shifts of traces on the screen, but the origins of the two phenomena are different. Both kinds of tremors in the oscilloscope trigger circuits produce images on the screen, which often are similar to those resulting from the noise jitter. Hence, limited knowledge of tremor may be a source of improper interpretation of the oscilloscope measurements. On the other hand tremor can be considered as a different approach to the problem of flip-flop circuit's metastability

  20. Piezoelectric drive circuit

    Science.gov (United States)

    Treu, C.A. Jr.

    1999-08-31

    A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.

  1. Load testing circuit

    DEFF Research Database (Denmark)

    2009-01-01

    A load testing circuit a circuit tests the load impedance of a load connected to an amplifier. The load impedance includes a first terminal and a second terminal, the load testing circuit comprising a signal generator providing a test signal of a defined bandwidth to the first terminal of the load...

  2. Short-circuit logic

    NARCIS (Netherlands)

    Bergstra, J.A.; Ponse, A.

    2010-01-01

    Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of

  3. Signal sampling circuit

    NARCIS (Netherlands)

    Louwsma, S.M.; Vertregt, Maarten

    2011-01-01

    A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

  4. Signal sampling circuit

    NARCIS (Netherlands)

    Louwsma, S.M.; Vertregt, Maarten

    2010-01-01

    A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital

  5. Refractory silicides for integrated circuits

    International Nuclear Information System (INIS)

    Murarka, S.P.

    1980-01-01

    Transition metal silicides have, in the past, attracted attention because of their usefulness as high temperature materials and in integrated circuits as Schottky barrier and ohmic contacts. More recently, with the increasing silicon integrated circuits (SIC) packing density, the line widths get narrower and the sheet resistance contribution to the RC delay increases. The possibility of using low resistivity silicides, which can be formed directly on the polysilicon, makes these silicides highly attractive. The usefulness of a silicide metallization scheme for integrated circuits depends, not only on the desired low resistivity, but also on the ease with which the silicide can be formed and patterned and on the stability of the silicides throughout device processing and during actual device usage. In this paper, various properties and the formation techniques of the silicides have been reviewed. Correlations between the various properties and the metal or silicide electronic or crystallographic structure have been made to predict the more useful silicides for SIC applications. Special reference to the silicide resistivity, stress, and oxidizability during the formation and subsequent processing has been given. Various formation and etching techniques are discussed

  6. Data readout system utilizing photonic integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

    2013-10-11

    We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

  7. Feedback in analog circuits

    CERN Document Server

    Ochoa, Agustin

    2016-01-01

    This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...

  8. Development of a non-delay-line constant-fraction discriminator

    International Nuclear Information System (INIS)

    Yang Tao; Zhao Bo; Zhang Chi

    2002-01-01

    A Non-Delay-Line Constant-Fraction Discriminator (CFD) timing circuit is introduced. The delay line in the CFD is replaced with a low pass filter in this simplified circuit. The timing resolution of the CFD is better than 150 ps

  9. A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance.

    Science.gov (United States)

    Abdulrazzaq, Bilal I; Abdul Halin, Izhal; Kawahito, Shoji; Sidek, Roslina M; Shafie, Suhaidi; Yunus, Nurul Amziah Md

    2016-01-01

    A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

  10. Multiplier less high-speed squaring circuit for binary numbers

    Science.gov (United States)

    Sethi, Kabiraj; Panda, Rutuparna

    2015-03-01

    The squaring operation is important in many applications in signal processing, cryptography etc. In general, squaring circuits reported in the literature use fast multipliers. A novel idea of a squaring circuit without using multipliers is proposed in this paper. Ancient Indian method used for squaring decimal numbers is extended here for binary numbers. The key to our success is that no multiplier is used. Instead, one squaring circuit is used. The hardware architecture of the proposed squaring circuit is presented. The design is coded in VHDL and synthesised and simulated in Xilinx ISE Design Suite 10.1 (Xilinx Inc., San Jose, CA, USA). It is implemented in Xilinx Vertex 4vls15sf363-12 device (Xilinx Inc.). The results in terms of time delay and area is compared with both modified Booth's algorithm and squaring circuit using Vedic multipliers. Our proposed squaring circuit seems to have better performance in terms of both speed and area.

  11. Electric circuits and signals

    CERN Document Server

    Sabah, Nassir H

    2007-01-01

    Circuit Variables and Elements Overview Learning Objectives Electric Current Voltage Electric Power and Energy Assigned Positive Directions Active and Passive Circuit Elements Voltage and Current Sources The Resistor The Capacitor The Inductor Concluding Remarks Summary of Main Concepts and Results Learning Outcomes Supplementary Topics on CD Problems and Exercises Basic Circuit Connections and Laws Overview Learning Objectives Circuit Terminology Kirchhoff's Laws Voltage Division and Series Connection of Resistors Current Division and Parallel Connection of Resistors D-Y Transformation Source Equivalence and Transformation Reduced-Voltage Supply Summary of Main Concepts and Results Learning Outcomes Supplementary Topics and Examples on CD Problems and Exercises Basic Analysis of Resistive Circuits Overview Learning Objectives Number of Independent Circuit Equations Node-Voltage Analysis Special Considerations in Node-Voltage Analysis Mesh-Current Analysis Special Conside...

  12. [Shunt and short circuit].

    Science.gov (United States)

    Rangel-Abundis, Alberto

    2006-01-01

    Shunt and short circuit are antonyms. In French, the term shunt has been adopted to denote the alternative pathway of blood flow. However, in French, as well as in Spanish, the word short circuit (court-circuit and cortocircuito) is synonymous with shunt, giving rise to a linguistic and scientific inconsistency. Scientific because shunt and short circuit made reference to a phenomenon that occurs in the field of the physics. Because shunt and short circuit are antonyms, it is necessary to clarify that shunt is an alternative pathway of flow from a net of high resistance to a net of low resistance, maintaining the stream. Short circuit is the interruption of the flow, because a high resistance impeaches the flood. This concept is applied to electrical and cardiovascular physiology, as well as to the metabolic pathways.

  13. Analog circuits cookbook

    CERN Document Server

    Hickman, Ian

    2013-01-01

    Analog Circuits Cookbook presents articles about advanced circuit techniques, components and concepts, useful IC for analog signal processing in the audio range, direct digital synthesis, and ingenious video op-amp. The book also includes articles about amplitude measurements on RF signals, linear optical imager, power supplies and devices, and RF circuits and techniques. Professionals and students of electrical engineering will find the book informative and useful.

  14. Analog circuit design

    CERN Document Server

    Dobkin, Bob

    2012-01-01

    Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <

  15. Regenerative feedback resonant circuit

    Science.gov (United States)

    Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.

    2014-09-02

    A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.

  16. Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits

    Directory of Open Access Journals (Sweden)

    Ruiping Cao

    2014-01-01

    Full Text Available In high-speed applications, MOS current mode logic (MCML is a good alternative. Scaling down supply voltage of the MCML circuits can achieve low power-delay product (PDP. However, the current almost all MCML circuits are realized with dual-rail scheme, where the NMOS configuration in series limits the minimum supply voltage. In this paper, single-rail MCML (SRMCML circuits are described, which can avoid the devices configuration in series, since their logic evaluation block can be realized by only using MOS devices in parallel. The relationship between the minimum supply voltage of the SRMCML circuits and the model parameters of MOS transistors is derived, so that the minimum supply voltage can be estimated before circuit designs. An MCML dynamic flop-flop based on SRMCML is also proposed. The optimization algorithm for near-threshold sequential circuits is presented. A near-threshold SRMCML mode-10 counter based on the optimization algorithm is verified. Scaling down the supply voltage of the SRMCML circuits is also investigated. The power dissipation, delay, and power-delay products of these circuits are carried out. The results show that the near-threshold SRMCML circuits can obtain low delay and small power-delay product.

  17. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  18. Timergenerator circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Timer/Generator Circuits Manual is an 11-chapter text that deals mainly with waveform generator techniques and circuits. Each chapter starts with an explanation of the basic principles of its subject followed by a wide range of practical circuit designs. This work presents a total of over 300 practical circuits, diagrams, and tables.Chapter 1 outlines the basic principles and the different types of generator. Chapters 2 to 9 deal with a specific type of waveform generator, including sine, square, triangular, sawtooth, and special waveform generators pulse. These chapters also include pulse gen

  19. Electronic devices and circuits

    CERN Document Server

    Pridham, Gordon John

    1968-01-01

    Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th

  20. Maximum Acceleration Recording Circuit

    Science.gov (United States)

    Bozeman, Richard J., Jr.

    1995-01-01

    Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

  1. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  2. Circuits and filters handbook

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi

  3. Security electronics circuits manual

    CERN Document Server

    MARSTON, R M

    1998-01-01

    Security Electronics Circuits Manual is an invaluable guide for engineers and technicians in the security industry. It will also prove to be a useful guide for students and experimenters, as well as providing experienced amateurs and DIY enthusiasts with numerous ideas to protect their homes, businesses and properties.As with all Ray Marston's Circuits Manuals, the style is easy-to-read and non-mathematical, with the emphasis firmly on practical applications, circuits and design ideas. The ICs and other devices used in the practical circuits are modestly priced and readily available ty

  4. Scaling of graphene integrated circuits.

    Science.gov (United States)

    Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

    2015-05-07

    The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

  5. Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

    Directory of Open Access Journals (Sweden)

    Michael S. Hsiao

    2002-01-01

    Full Text Available Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

  6. Circuits on Cylinders

    DEFF Research Database (Denmark)

    Hansen, Kristoffer Arnsfelt; Miltersen, Peter Bro; Vinay, V

    2006-01-01

    We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a Pi2 o MOD o AC0 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching pro...

  7. Delayed puberty in girls

    Science.gov (United States)

    ... sexual development - girls; Pubertal delay - girls; Constitutional delayed puberty ... In most cases of delayed puberty, growth changes just begin later than usual, sometimes called a late bloomer. Once puberty begins, it progresses normally. This pattern runs ...

  8. Delayed Puberty (For Teens)

    Science.gov (United States)

    ... Safe Videos for Educators Search English Español Delayed Puberty KidsHealth / For Teens / Delayed Puberty What's in this ... wonder if there's anything wrong. What Is Delayed Puberty? Puberty is the time when your body grows ...

  9. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  10. Break-before-make CMOS inverter for power-efficient delay implementation.

    Science.gov (United States)

    Puhan, Janez; Raič, Dušan; Tuma, Tadej; Bűrmen, Árpád

    2014-01-01

    A modified static CMOS inverter with two inputs and two outputs is proposed to reduce short-circuit current in order to increment delay and reduce power overhead where slow operation is required. The circuit is based on bidirectional delay element connected in series with the PMOS and NMOS switching transistors. It provides differences in the dynamic response so that the direct-path current in the next stage is reduced. The switching transistors are never ON at the same time. Characteristics of various delay element implementations are presented and verified by circuit simulations. Global optimization procedure is used to obtain the most power-efficient transistor sizing. The performance of the modified CMOS inverter chain is compared to standard implementation for various delays. The energy (charge) per delay is reduced up to 40%. The use of the proposed delay element is demonstrated by implementing a low-power delay line and a leading-edge detector cell.

  11. A Quantized Analog Delay for an ir-UWB Quadrature Downconversion Autocorrelation Receiver

    NARCIS (Netherlands)

    Bagga, S.; Zhang, L.; Serdijn, W.A.; Long, J.R.; Busking, E.B.

    2005-01-01

    A quantized analog delay is designed as a requirement for the autocorrelation function in the quadrature downconversion autocorrelation receiver (QDAR). The quantized analog delay is comprised of a quantizer, multiple binary delay lines and an adder circuit. Being the foremost element, the quantizer

  12. Approximate circuits for increased reliability

    Science.gov (United States)

    Hamlet, Jason R.; Mayo, Jackson R.

    2015-08-18

    Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.

  13. Troubleshooting analog circuits

    CERN Document Server

    Pease, Robert A

    1991-01-01

    Troubleshooting Analog Circuits is a guidebook for solving product or process related problems in analog circuits. The book also provides advice in selecting equipment, preventing problems, and general tips. The coverage of the book includes the philosophy of troubleshooting; the modes of failure of various components; and preventive measures. The text also deals with the active components of analog circuits, including diodes and rectifiers, optically coupled devices, solar cells, and batteries. The book will be of great use to both students and practitioners of electronics engineering. Other

  14. Modern TTL circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com

  15. Circuit analysis with Multisim

    CERN Document Server

    Baez-Lopez, David

    2011-01-01

    This book is concerned with circuit simulation using National Instruments Multisim. It focuses on the use and comprehension of the working techniques for electrical and electronic circuit simulation. The first chapters are devoted to basic circuit analysis.It starts by describing in detail how to perform a DC analysis using only resistors and independent and controlled sources. Then, it introduces capacitors and inductors to make a transient analysis. In the case of transient analysis, it is possible to have an initial condition either in the capacitor voltage or in the inductor current, or bo

  16. Optoelectronics circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Optoelectronics Circuits Manual covers the basic principles and characteristics of the best known types of optoelectronic devices, as well as the practical applications of many of these optoelectronic devices. The book describes LED display circuits and LED dot- and bar-graph circuits and discusses the applications of seven-segment displays, light-sensitive devices, optocouplers, and a variety of brightness control techniques. The text also tackles infrared light-beam alarms and multichannel remote control systems. The book provides practical user information and circuitry and illustrations.

  17. 'Speedy' superconducting circuits

    International Nuclear Information System (INIS)

    Holst, T.

    1994-01-01

    The most promising concept for realizing ultra-fast superconducting digital circuits is the Rapid Single Flux Quantum (RSFQ) logic. The basic physical principle behind RSFQ logic, which include the storage and transfer of individual magnetic flux quanta in Superconducting Quantum Interference Devices (SQUIDs), is explained. A Set-Reset flip-flop is used as an example of the implementation of an RSFQ based circuit. Finally, the outlook for high-temperature superconducting materials in connection with RSFQ circuits is discussed in some details. (au)

  18. 4-channel time delayed pulse generator

    International Nuclear Information System (INIS)

    Wetzel, L.F.S.; Rossi, J.O.; Del Bosco, E.

    1987-02-01

    It is described the project of a 4-channel delayed pulse generator employed to trigger the plasma centrifuge experiment of the Laboratorio Associado de Plasmas. The circuit delivers pulses with amplitude of 15V, full width at half maximum of 50μs and rise time of 0.7μs. The maximum time delay is 100ms. There are two channels with a fine adjustment of 0-1ms. The system can be manually or automatically driven. (author) [pt

  19. Speech and Language Delay

    Science.gov (United States)

    ... OTC Relief for Diarrhea Home Diseases and Conditions Speech and Language Delay Condition Speech and Language Delay Share Print Table of Contents1. ... Treatment6. Everyday Life7. Questions8. Resources What is a speech and language delay? A speech and language delay ...

  20. Analogue circuits simulation

    Energy Technology Data Exchange (ETDEWEB)

    Mendo, C

    1988-09-01

    Most analogue simulators have evolved from SPICE. The history and description of SPICE-like simulators are given. From a mathematical formulation of the electronic circuit the following analysis are possible: DC, AC, transient, noise, distortion, Worst Case and Statistical.

  1. Printed circuit for ATLAS

    CERN Multimedia

    Laurent Guiraud

    1999-01-01

    A printed circuit board made by scientists in the ATLAS collaboration for the transition radiaton tracker (TRT). This will read data produced when a high energy particle crosses the boundary between two materials with different electrical properties.

  2. Magnonic logic circuits

    International Nuclear Information System (INIS)

    Khitun, Alexander; Bao Mingqiang; Wang, Kang L

    2010-01-01

    We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

  3. Thermal Aware Floorplanning Incorporating Temperature Dependent Wire Delay Estimation

    DEFF Research Database (Denmark)

    Winther, AndreasThor; Liu, Wei; Nannarelli, Alberto

    2015-01-01

    Temperature has a negative impact on metal resistance and thus wire delay. In state-of-the-art VLSI circuits, large thermal gradients usually exist due to the uneven distribution of heat sources. The difference in wire temperature can lead to performance mismatch because wires of the same length...... can have different delay. Traditional floorplanning algorithms use wirelength to estimate wire performance. In this work, we show that this does not always produce a design with the shortest delay and we propose a floorplanning algorithm taking into account temperature dependent wire delay as one...

  4. Variable Delay Element For Jitter Control In High Speed Data Links

    Science.gov (United States)

    Livolsi, Robert R.

    2002-06-11

    A circuit and method for decreasing the amount of jitter present at the receiver input of high speed data links which uses a driver circuit for input from a high speed data link which comprises a logic circuit having a first section (1) which provides data latches, a second section (2) which provides a circuit generates a pre-destorted output and for compensating for level dependent jitter having an OR function element and a NOR function element each of which is coupled to two inputs and to a variable delay element as an input which provides a bi-modal delay for pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in the driver circuit. A fifth section is used for logic testing the driver circuit.

  5. Is the use of albumin in colloid prime solution of cardiopulmonary bypass circuit justified?

    NARCIS (Netherlands)

    Boks, RH; van Herwerden, LA; Takkenberg, JJM; van Oeveren, W; Gu, YJ; Wijers, MJ; Bogers, AJJC

    Background. Albumin in the priming solution precoats the surface of the cardiopulmonary bypass circuit, supposedly causing delayed adsorption of fibrinogen and reduced activation and adhesion of platelets. This action may result in lower transoxygenator resistance. Because our institution uses a

  6. Color Coding of Circuit Quantities in Introductory Circuit Analysis Instruction

    Science.gov (United States)

    Reisslein, Jana; Johnson, Amy M.; Reisslein, Martin

    2015-01-01

    Learning the analysis of electrical circuits represented by circuit diagrams is often challenging for novice students. An open research question in electrical circuit analysis instruction is whether color coding of the mathematical symbols (variables) that denote electrical quantities can improve circuit analysis learning. The present study…

  7. Project Circuits in a Basic Electric Circuits Course

    Science.gov (United States)

    Becker, James P.; Plumb, Carolyn; Revia, Richard A.

    2014-01-01

    The use of project circuits (a photoplethysmograph circuit and a simple audio amplifier), introduced in a sophomore-level electric circuits course utilizing active learning and inquiry-based methods, is described. The development of the project circuits was initiated to promote enhanced engagement and deeper understanding of course content among…

  8. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  9. Low latency asynchronous interface circuits

    Science.gov (United States)

    Sadowski, Greg

    2017-06-20

    In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

  10. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  11. Technology CAD for germanium CMOS circuit

    International Nuclear Information System (INIS)

    Saha, A.R.; Maiti, C.K.

    2006-01-01

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

  12. Synthesis for robust synchronization of chaotic systems under output feedback control with multiple random delays

    International Nuclear Information System (INIS)

    Wen Guilin; Wang Qingguo; Lin Chong; Han Xu; Li Guangyao

    2006-01-01

    Synchronization under output feedback control with multiple random time delays is studied, using the paradigm in nonlinear physics-Chua's circuit. Compared with other synchronization control methods, output feedback control with multiple random delay is superior for a realistic synchronization application to secure communications. Sufficient condition for global stability of delay-dependent synchronization is established based on the LMI technique. Numerical simulations fully support the analytical approach, in spite of the random delays

  13. A high-precision synchronization circuit for clock distribution

    International Nuclear Information System (INIS)

    Lu Chong; Tan Hongzhou; Duan Zhikui; Ding Yi

    2015-01-01

    In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm 2 , and the power consumption is 1.64 mW at 500 MHz. (paper)

  14. Junction and circuit fabrication

    International Nuclear Information System (INIS)

    Jackel, L.D.

    1980-01-01

    Great strides have been made in Josephson junction fabrication in the four years since the first IC SQUID meeting. Advances in lithography have allowed the production of devices with planar dimensions as small as a few hundred angstroms. Improved technology has provided ultra-high sensitivity SQUIDS, high-efficiency low-noise mixers, and complex integrated circuits. This review highlights some of the new fabrication procedures. The review consists of three parts. Part 1 is a short summary of the requirements on junctions for various applications. Part 2 reviews intergrated circuit fabrication, including tunnel junction logic circuits made at IBM and Bell Labs, and microbridge radiation sources made at SUNY at Stony Brook. Part 3 describes new junction fabrication techniques, the major emphasis of this review. This part includes a discussion of small oxide-barrier tunnel junctions, semiconductor barrier junctions, and microbridge junctions. Part 3 concludes by considering very fine lithography and limitations to miniaturization. (orig.)

  15. UAVs and Control Delays

    National Research Council Canada - National Science Library

    de Vries, S. C

    2005-01-01

    .... Delays of about 250-300 ms often lead to unacceptable airplane handling qualities. Techniques such as filtering and predictive displays may extend the range of acceptable delays up to about 400 ms...

  16. Delayed puberty in boys

    Science.gov (United States)

    ... page: //medlineplus.gov/ency/article/007695.htm Delayed puberty in boys To use the sharing features on this page, please enable JavaScript. Delayed puberty in boys is when puberty does not begin ...

  17. Small circuits for cryptography.

    Energy Technology Data Exchange (ETDEWEB)

    Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik

    2005-10-01

    This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

  18. Silicon integrated circuit process

    International Nuclear Information System (INIS)

    Lee, Jong Duck

    1985-12-01

    This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

  19. Primer printed circuit boards

    CERN Document Server

    Argyle, Andrew

    2009-01-01

    Step-by-step instructions for making your own PCBs at home. Making your own printed circuit board (PCB) might seem a daunting task, but once you master the steps, it's easy to attain professional-looking results. Printed circuit boards, which connect chips and other components, are what make almost all modern electronic devices possible. PCBs are made from sheets of fiberglass clad with copper, usually in multiplelayers. Cut a computer motherboard in two, for instance, and you'll often see five or more differently patterned layers. Making boards at home is relatively easy

  20. Silicon integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Jong Duck

    1985-12-15

    This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

  1. Circuit design for reliability

    CERN Document Server

    Cao, Yu; Wirth, Gilson

    2015-01-01

    This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units.  The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management. Provides comprehensive review on various reliability mechanisms at sub-45nm nodes; Describes practical modeling and characterization techniques for reliability; Includes thorough presentation of robust design techniques for major VLSI design units; Promotes physical understanding with first-principle simulations.

  2. Electronic circuits fundamentals & applications

    CERN Document Server

    Tooley, Mike

    2015-01-01

    Electronics explained in one volume, using both theoretical and practical applications.New chapter on Raspberry PiCompanion website contains free electronic tools to aid learning for students and a question bank for lecturersPractical investigations and questions within each chapter help reinforce learning Mike Tooley provides all the information required to get to grips with the fundamentals of electronics, detailing the underpinning knowledge necessary to appreciate the operation of a wide range of electronic circuits, including amplifiers, logic circuits, power supplies and oscillators. The

  3. Delayed Orgasm and Anorgasmia

    OpenAIRE

    Jenkins, Lawrence C.; Mulhall, John P.

    2015-01-01

    Delayed orgasm/anorgasmia defined as the persistent or recurrent difficulty, delay in, or absence of attaining orgasm after sufficient sexual stimulation, which causes personal distress. Delayed orgasm and anorgasmia are associated with significant sexual dissatisfaction. A focused medical history can shed light on the potential etiologies; which include: medications, penile sensation loss, endocrinopathies, penile hyperstimulation and psychological etiologies, amongst others. Unfortunately, ...

  4. Study of the phase delay in the amplitude-modulated harmonic oscillator

    International Nuclear Information System (INIS)

    Krupska, Aldona; Krupski, Marcin

    2003-01-01

    The delayed response of a damped harmonic oscillator (RLC circuit) to a slow periodic disturbance is presented. This communication is supplementary to the paper published recently (Krupska et al 2001 Eur. J. Phys. 22 133-8)

  5. New reactor safety circuit for low-power-level operation

    International Nuclear Information System (INIS)

    McDowell, W.P.; Keefe, D.J.; Rusch, G.K.

    1978-01-01

    In the operation of nuclear reactors at low-power levels, one of the primary instrumentation problems is that the statistical fluctuations of reactor neutron population are accentuated by conventional log-count-rate and differentiating circuits and can cause frequent spurious scrams unless long time constants are incorporated in the circuit. Excessive time constants may introduce undesirable delay in the circuit response to legitimate scram signals. The paper develops the concept of a count doubling-time monitor which generates a scram signal if the number of counts from a pulse type neutron detector doubles in a given period of time. The paper demonstrates the theoretical relation between count doubling time and asymptomatic periods. A practical circuit to implement the function is described

  6. Design and implementation of high-precision and low-jitter programmable delay circuitry

    International Nuclear Information System (INIS)

    Gao Yuan; Cui Ke; Zhang Hongfei; Luo Chunli; Yang Dongxu; Liang Hao; Wang Jian

    2011-01-01

    A programmable delay circuit design which has characteristics of high-precision, low-jitter, wide-programmable-range and low power is introduced. The delay circuitry uses the scheme which has two parts: the coarse delay and the fine delay that could be controlled separately. Using different coarse delay chip can reach different maximum programmable range. And the fine delay programmable chip has the minimum step which is down to 10 ps. The whole circuitry jitter will be less than 100 ps. The design has been successfully applied in Quantum Key Distribution experiment. (authors)

  7. ESD analog circuits and design

    CERN Document Server

    Voldman, Steven H

    2014-01-01

    A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design.  It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres

  8. Unstable oscillators based hyperchaotic circuit

    DEFF Research Database (Denmark)

    Murali, K.; Tamasevicius, A.; G. Mykolaitis, A.

    1999-01-01

    A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations in the circ...... in the circuit. The performance of the circuit is investigated by means of numerical integration of appropriate differential equations, PSPICE simulations, and hardware experiment.......A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations...

  9. The test of VLSI circuits

    Science.gov (United States)

    Baviere, Ph.

    Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

  10. Electronic Circuit Analysis Language (ECAL)

    Science.gov (United States)

    Chenghang, C.

    1983-03-01

    The computer aided design technique is an important development in computer applications and it is an important component of computer science. The special language for electronic circuit analysis is the foundation of computer aided design or computer aided circuit analysis (abbreviated as CACD and CACA) of simulated circuits. Electronic circuit analysis language (ECAL) is a comparatively simple and easy to use circuit analysis special language which uses the FORTRAN language to carry out the explanatory executions. It is capable of conducting dc analysis, ac analysis, and transient analysis of a circuit. Futhermore, the results of the dc analysis can be used directly as the initial conditions for the ac and transient analyses.

  11. An integrated circuit switch

    Science.gov (United States)

    Bonin, E. L.

    1969-01-01

    Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain.

  12. Automatic sweep circuit

    International Nuclear Information System (INIS)

    Keefe, D.J.

    1980-01-01

    An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input is described. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found

  13. Automatic sweep circuit

    Science.gov (United States)

    Keefe, Donald J.

    1980-01-01

    An automatically sweeping circuit for searching for an evoked response in an output signal in time with respect to a trigger input. Digital counters are used to activate a detector at precise intervals, and monitoring is repeated for statistical accuracy. If the response is not found then a different time window is examined until the signal is found.

  14. "Printed-circuit" rectenna

    Science.gov (United States)

    Dickinson, R. M.

    1977-01-01

    Rectifying antenna is less bulky structure for absorbing transmitted microwave power and converting it into electrical current. Printed-circuit approach, using microstrip technology and circularly polarized antenna, makes polarization orientation unimportant and allows much smaller arrays for given performance. Innovation is particularly useful with proposed electric vehicles powered by beam microwaves.

  15. Het onzichtbare circuit

    NARCIS (Netherlands)

    Nauta, Bram

    2013-01-01

    De chip, of geïntegreerde schakeling, heeft in een razend tempo ons leven ingrijpend veranderd. Het lijkt zo vanzelfsprekend dat er weer een nieuwe generatie smartphones, tablets of computers is. Maar dat is het niet. Prof.dr.ir. Bram Nauta, hoogleraar Integrated Circuit Design, laat in zijn rede

  16. Voltage regulating circuit

    NARCIS (Netherlands)

    2005-01-01

    A voltage regulating circuit comprising a rectifier (2) for receiving an AC voltage (Vmains) and for generating a rectified AC voltage (vrec), and a capacitor (3) connected in parallel with said rectified AC voltage for providing a DC voltage (VDC) over a load (5), characterized by a unidirectional

  17. Streaming Reduction Circuit

    NARCIS (Netherlands)

    Gerards, Marco Egbertus Theodorus; Kuper, Jan; Kokkeler, Andre B.J.; Molenkamp, Egbert

    2009-01-01

    Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced. We present an algorithm by which any number of consecutive rows of arbitrary lengths

  18. A Magnetic Circuit Demonstration.

    Science.gov (United States)

    Vanderkooy, John; Lowe, June

    1995-01-01

    Presents a demonstration designed to illustrate Faraday's, Ampere's, and Lenz's laws and to reinforce the concepts through the analysis of a two-loop magnetic circuit. Can be made dramatic and challenging for sophisticated students but is suitable for an introductory course in electricity and magnetism. (JRH)

  19. The LMT circuit and SPICE

    DEFF Research Database (Denmark)

    Lindberg, Erik; Murali, K.; Tamacevicius, Arunas

    2006-01-01

    The state equations of the LMT circuit are modeled as a dedicated analogue computer circuit and solved by means of PSpice. The nonlinear part of the system is studied. Problems with the PSpice program are presented....

  20. Resistor Combinations for Parallel Circuits.

    Science.gov (United States)

    McTernan, James P.

    1978-01-01

    To help simplify both teaching and learning of parallel circuits, a high school electricity/electronics teacher presents and illustrates the use of tables of values for parallel resistive circuits in which total resistances are whole numbers. (MF)

  1. Detecting short circuits during assembly

    Science.gov (United States)

    Deboo, G. J.

    1980-01-01

    Detector circuit identifies shorts between bus bars of electronic equipment being wired. Detector sounds alarm and indicates which planes are shorted. Power and ground bus bars are scanned continuously until short circuit occurs.

  2. BR-5 primary circuit decontamination

    International Nuclear Information System (INIS)

    Efimov, I.A.; Nikulin, M.P.; Smirnov-Averin, A.P.; Tymosh, B.S.; Shereshkov, V.S.

    1976-01-01

    Results and methodology of steam-water and acid decontamination of the primary coolant circuit SBR-5 reactor in 1971 are discussed. Regeneration process in a cold trap of the primary coolant circuit is discussed

  3. Basic Guidelines for Application of Performance Standards to Commissioning of DCS Digital Circuits

    Science.gov (United States)

    1992-06-01

    V6Z2J7 Canada Gustavo A. Cubas E. 1 Engineered Systems, Inc 2 Seccion De Transmission ATTN: Mr. David Gilfillan Direccion De Ingenieria Y Proyectos 14775...buffering, and and filter delay (for a voice circuit). Propagation delay is independent of data rate, while buffering delay is inversely proportional to...Complexe Des Jardins, 15th Fl. 171 N. Covington Drive 75 Rene Levesque West Bloomingdale, IL 60108 Montreal, PG H2Z Canada DISTRIBUTION LIST Department

  4. MOS voltage automatic tuning circuit

    OpenAIRE

    李, 田茂; 中田, 辰則; 松本, 寛樹

    2004-01-01

    Abstract ###Automatic tuning circuit adjusts frequency performance to compensate for the process variation. Phase locked ###loop (PLL) is a suitable oscillator for the integrated circuit. It is a feedback system that compares the input ###phase with the output phase. It can make the output frequency equal to the input frequency. In this paper, PLL ###fomed of MOSFET's is presented.The presented circuit consists of XOR circuit, Low-pass filter and Relaxation ###Oscillator. On PSPICE simulation...

  5. Behavioral synthesis of asynchronous circuits

    DEFF Research Database (Denmark)

    Nielsen, Sune Fallgaard

    2005-01-01

    This thesis presents a method for behavioral synthesis of asynchronous circuits, which aims at providing a synthesis flow which uses and tranfers methods from synchronous circuits to asynchronous circuits. We move the synchronous behavioral synthesis abstraction into the asynchronous handshake...... is idle. This reduces unnecessary switching activity in the individual functional units and therefore the energy consumption of the entire circuit. A collection of behavioral synthesis algorithms have been developed allowing the designer to perform time and power constrained design space exploration...

  6. Selected collection of circuit drawings

    International Nuclear Information System (INIS)

    1977-01-01

    The many electronics circuits have been constracted in the Electronics Shop for use in nuclear experiments or other purposes of this Institute. The types of these circuits amount to about 500 items in total since 1968. This report describes the electronics circuit diagrams selected from this collection. The circuit details are not presented in this report, because these are already been published in the other technical reports. (auth.)

  7. Diode, transistor & fet circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Diode, Transistor and FET Circuits Manual is a handbook of circuits based on discrete semiconductor components such as diodes, transistors, and FETS. The book also includes diagrams and practical circuits. The book describes basic and special diode characteristics, heat wave-rectifier circuits, transformers, filter capacitors, and rectifier ratings. The text also presents practical applications of associated devices, for example, zeners, varicaps, photodiodes, or LEDs, as well as it describes bipolar transistor characteristics. The transistor can be used in three basic amplifier configuration

  8. Global chaos synchronization with channel time-delay

    International Nuclear Information System (INIS)

    Jiang Guoping; Zheng Weixing; Chen Guanrong

    2004-01-01

    This paper addresses a practical issue in chaos synchronization where there is a time-delay in the receiver as compared with the transmitter. A new synchronization scheme and a general criterion for global chaos synchronization are proposed and developed from the approach of unidirectional linear error feedback coupling with time-delay. The chaotic Chua's circuit is used for illustration, where the coupling parameters are determined according to the criterion under which the global chaos synchronization of the time-delay coupled systems is achieved

  9. The review of radiation effects of γ total dose in CMOS circuits

    International Nuclear Information System (INIS)

    Chen Panxun; Gao Wenming; Xie Zeyuan; Mi Bang

    1992-01-01

    Radiation performances of commercial and rad-hard CMOS circuits are reviewed. Threshold voltage, static power current, V in -V out characteristic and propagation delay time related with total dose are presented for CMOS circuits from several manufacturing processes. The performance of radiation-annealing of experimental circuits had been observed for two years. The comparison has been made between the CMOS circuits made in China and the commercial RCA products. 60 Co γ source can serve as γ simulator of the nuclear explosion

  10. Analysis of Bernstein's factorization circuit

    NARCIS (Netherlands)

    Lenstra, A.K.; Shamir, A.; Tomlinson, J.; Tromer, E.; Zheng, Y.

    2002-01-01

    In [1], Bernstein proposed a circuit-based implementation of the matrix step of the number field sieve factorization algorithm. These circuits offer an asymptotic cost reduction under the measure "construction cost x run time". We evaluate the cost of these circuits, in agreement with [1], but argue

  11. High voltage MOSFET switching circuit

    Science.gov (United States)

    McEwan, Thomas E.

    1994-01-01

    The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.

  12. Neuromorphic Silicon Neuron Circuits

    Science.gov (United States)

    Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

    2011-01-01

    Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

  13. Neuromorphic silicon neuron circuits

    Directory of Open Access Journals (Sweden)

    Giacomo eIndiveri

    2011-05-01

    Full Text Available Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance based Hodgkin-Huxley models to bi-dimensional generalized adaptive Integrate and Fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

  14. High-explosive-driven delay line pulse generator

    International Nuclear Information System (INIS)

    Shearer, J.W.

    1982-01-01

    The inclusion of a delay line circuit into the design of a high-explosive-driven generator shortens the time constant of the output pulse. After a brief review of generator concepts and previously described pulse-shortening methods, a geometry is presented which incorporates delay line circuit techcniques into a coil generator. The circuit constants are adjusted to match the velocity of the generated electromagnetic wave to the detonation velocity of the high explosive. The proposed generator can be modeled by adding a variable inductance term to the telegrapher's equation. A particular solution of this equation is useful for exploring the operational parameters of the generator. The duration of the electromagnetic pulse equals the radial expansion time of the high-explosive-driven armature until it strikes the coil. Because the impedance of the generator is a constant, the current multiplication factor is limited only by nonlinear effects such as voltage breakdown, diffusion, and compression at high energies

  15. Integrated circuit structure

    International Nuclear Information System (INIS)

    1981-01-01

    The invention describes the fabrication of integrated circuit structures, such as read-only memory components of field-effect transistors, which may be fabricated and then maintained in inventory, and later selectively modified in accordance with a desired pattern. It is claimed that MOS depletion-mode devices in accordance with the invention can be fabricated at lower cost and at higher yields. (U.K.)

  16. Integrated Circuit Immunity

    Science.gov (United States)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  17. Integrated coincidence circuits

    International Nuclear Information System (INIS)

    Borejko, V.F.; Grebenyuk, V.M.; Zinov, V.G.

    1976-01-01

    The description is given of two coincidence units employing integral circuits in the VISHNYA standard. The units are distinguished for the coincidence selection element which is essentially a combination of a tunnel diode and microcircuits. The output fast response of the units is at least 90 MHz in the mode of the output signal unshaped in duration and 50 MHz minimum in the mode of the output signal shaping. The resolution time of the units is dependent upon the duration of input signals

  18. Semiconductor integrated circuits

    International Nuclear Information System (INIS)

    Michel, A.E.; Schwenker, R.O.; Ziegler, J.F.

    1979-01-01

    An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

  19. Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

    Science.gov (United States)

    Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

    2015-10-14

    We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

  20. Delayed orgasm and anorgasmia.

    Science.gov (United States)

    Jenkins, Lawrence C; Mulhall, John P

    2015-11-01

    Delayed orgasm/anorgasmia defined as the persistent or recurrent difficulty, delay in, or absence of attaining orgasm after sufficient sexual stimulation, which causes personal distress. Delayed orgasm and anorgasmia are associated with significant sexual dissatisfaction. A focused medical history can shed light on the potential etiologies, which include medications, penile sensation loss, endocrinopathies, penile hyperstimulation, and psychological etiologies. Unfortunately, there are no excellent pharmacotherapies for delayed orgasm/anorgasmia, and treatment revolves largely around addressing potential causative factors and psychotherapy. Copyright © 2015 American Society for Reproductive Medicine. Published by Elsevier Inc. All rights reserved.

  1. Interface Circuit For Printer Port

    Science.gov (United States)

    Tucker, Jerry H.; Yadlowsky, Ann B.

    1991-01-01

    Electronic circuit, called printer-port interface circuit (PPI) developed to overcome certain disadvantages of previous methods for connecting IBM PC or PC-compatible computer to other equipment. Has both reading and writing modes of operation. Very simple, requiring only six integrated circuits. Provides for moderately fast rates of transfer of data and uses existing unmodified circuit card in IBM PC. When used with appropriate software, circuit converts printer port on IBM PC, XT, AT, or compatible personal computer to general purpose, 8-bit-data, 16-bit address bus that connects to multitude of devices.

  2. Changes to the shuttle circuits

    CERN Multimedia

    GS Department

    2011-01-01

    To fit with passengers expectation, there will be some changes to the shuttle circuits as from Monday 10 October. See details on http://cern.ch/ShuttleService (on line on 7 October). Circuit No. 5 is cancelled as circuit No. 1 also stops at Bldg. 33. In order to guarantee shorter travel times, circuit No. 1 will circulate on Meyrin site only and circuit No. 2, with departures from Bldg. 33 and 500, on Prévessin site only. Site Services Section

  3. CHEETAH: circuit-switched high-speed end-to-end transport architecture

    Science.gov (United States)

    Veeraraghavan, Malathi; Zheng, Xuan; Lee, Hyuk; Gardner, M.; Feng, Wuchun

    2003-10-01

    Leveraging the dominance of Ethernet in LANs and SONET/SDH in MANs and WANs, we propose a service called CHEETAH (Circuit-switched High-speed End-to-End Transport ArcHitecture). The service concept is to provide end hosts with high-speed, end-to-end circuit connectivity on a call-by-call shared basis, where a "circuit" consists of Ethernet segments at the ends that are mapped into Ethernet-over-SONET long-distance circuits. This paper focuses on the file-transfer application for such circuits. For this application, the CHEETAH service is proposed as an add-on to the primary Internet access service already in place for enterprise hosts. This allows an end host that is sending a file to first attempt setting up an end-to-end Ethernet/EoS circuit, and if rejected, fall back to the TCP/IP path. If the circuit setup is successful, the end host will enjoy a much shorter file-transfer delay than on the TCP/IP path. To determine the conditions under which an end host with access to the CHEETAH service should attempt circuit setup, we analyze mean file-transfer delays as a function of call blocking probability in the circuit-switched network, probability of packet loss in the IP network, round-trip times, link rates, and so on.

  4. Thermionic integrated circuits: electronics for hostile environments

    International Nuclear Information System (INIS)

    Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

    1985-01-01

    Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments

  5. Power system with an integrated lubrication circuit

    Science.gov (United States)

    Hoff, Brian D [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL; Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Lane, William H [Chillicothe, IL

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  6. An electronic implementation for Liao's chaotic delayed neuron model with non-monotonous activation function

    Energy Technology Data Exchange (ETDEWEB)

    Duan Shukai [Department of Computer Science and Engineering, Chongqing University, Chongqing 400044 (China); School of Electronic and Information Engineering, Southwest University, Chongqing 400715 (China)], E-mail: duansk@swu.edu.cn; Liao Xiaofeng [Department of Computer Science and Engineering, Chongqing University, Chongqing 400044 (China)], E-mail: xfliao@cqu.edu.cn

    2007-09-10

    A new chaotic delayed neuron model with non-monotonously increasing transfer function, called as chaotic Liao's delayed neuron model, was recently reported and analyzed. An electronic implementation of this model is described in detail. At the same time, some methods in circuit design, especially for circuit with time delayed unit and non-monotonously increasing activation unit, are also considered carefully. We find that the dynamical behaviors of the designed circuits are closely similar to the results predicted by numerical experiments.

  7. Integrated coherent matter wave circuits

    International Nuclear Information System (INIS)

    Ryu, C.; Boshier, M. G.

    2015-01-01

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

  8. Delay line clipping in a scintillation camera system

    International Nuclear Information System (INIS)

    Hatch, K.F.

    1979-01-01

    The present invention provides a novel base line restoring circuit and a novel delay line clipping circuit in a scintillation camera system. Single and double delay line clipped signal waveforms are generated for increasing the operational frequency and fidelity of data detection of the camera system by base line distortion such as undershooting, overshooting, and capacitive build-up. The camera system includes a set of photomultiplier tubes and associated amplifiers which generate sequences of pulses. These pulses are pulse-height analyzed for detecting a scintillation having an energy level which falls within a predetermined energy range. Data pulses are combined to provide coordinates and energy of photopeak events. The amplifiers are biassed out of saturation over all ranges of pulse energy level and count rate. Single delay line clipping circuitry is provided for narrowing the pulse width of the decaying electrical data pulses which increase operating speed without the occurrence of data loss. (JTA)

  9. A current-mode multi-valued adder circuit for multi-operand addition

    Science.gov (United States)

    Cini, Ugur; Morgül, Avni

    2011-06-01

    Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.

  10. American Dream Delayed

    DEFF Research Database (Denmark)

    Khorunzhina, Natalia; Miller, Robert A.

    This paper investigates the delay in homeownership and a subsequent reduction in homeownership rate observed over the past decades. We focus on the delay in giving birth to children and increased labor market participation as contributing factors to homeownership dynamics for prime-age female hou...

  11. Dynamic pulse difference circuit

    International Nuclear Information System (INIS)

    Erickson, G.L.

    1978-01-01

    A digital electronic circuit of especial use for subtracting background activity pulses in gamma spectrometry is disclosed which comprises an up-down counter connected to count up with signal-channel pulses and to count down with background-channel pulses. A detector responsive to the count position of the up-down counter provides a signal when the up-down counter has completed one scaling sequence cycle of counts in the up direction. In an alternate embodiment, a detector responsive to the count position of the up-down counter provides a signal upon overflow of the counter

  12. Electronics circuits and systems

    CERN Document Server

    Bishop, Owen

    2007-01-01

    The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Each chapter ends with a set

  13. Electric circuits problem solver

    CERN Document Server

    REA, Editors of

    2012-01-01

    Each Problem Solver is an insightful and essential study and solution guide chock-full of clear, concise problem-solving gems. All your questions can be found in one convenient source from one of the most trusted names in reference solution guides. More useful, more practical, and more informative, these study aids are the best review books and textbook companions available. Nothing remotely as comprehensive or as helpful exists in their subject anywhere. Perfect for undergraduate and graduate studies.Here in this highly useful reference is the finest overview of electric circuits currently av

  14. Digital logic circuit test

    Energy Technology Data Exchange (ETDEWEB)

    Yun, Gil Jung; Yang, Hong Young

    2011-03-15

    This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.

  15. Photonic Integrated Circuits

    Science.gov (United States)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  16. Integrated circuit cell library

    Science.gov (United States)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  17. Nano integrated circuit process

    International Nuclear Information System (INIS)

    Yoon, Yung Sup

    2004-02-01

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  18. Electronic logic circuits

    CERN Document Server

    Gibson, J

    2013-01-01

    Most branches of organizing utilize digital electronic systems. This book introduces the design of such systems using basic logic elements as the components. The material is presented in a straightforward manner suitable for students of electronic engineering and computer science. The book is also of use to engineers in related disciplines who require a clear introduction to logic circuits. This third edition has been revised to encompass the most recent advances in technology as well as the latest trends in components and notation. It includes a wide coverage of application specific integrate

  19. Linear integrated circuits

    CERN Document Server

    Carr, Joseph

    1996-01-01

    The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

  20. Nano integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Yoon, Yung Sup

    2004-02-15

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  1. Electronics circuits and systems

    CERN Document Server

    Bishop, Owen

    2011-01-01

    The material in Electronics - Circuits and Systems is a truly up-to-date textbook, with coverage carefully matched to the electronics units of the 2007 BTEC National Engineering and the latest AS and A Level specifications in Electronics from AQA, OCR and WJEC. The material has been organized with a logical learning progression, making it ideal for a wide range of pre-degree courses in electronics. The approach is student-centred and includes: numerous examples and activities; web research topics; Self Test features, highlighted key facts, formulae and definitions. Ea

  2. Optoelectronics circuits manual

    CERN Document Server

    Marston, R M

    1999-01-01

    This manual is a useful single-volume guide specifically aimed at the practical design engineer, technician, and experimenter, as well as the electronics student and amateur. It deals with the subject in an easy to read, down to earth, and non-mathematical yet comprehensive manner, explaining the basic principles and characteristics of the best known devices, and presenting the reader with many practical applications and over 200 circuits. Most of the ICs and other devices used are inexpensive and readily available types, with universally recognised type numbers.The second edition

  3. Optically controllable molecular logic circuits

    International Nuclear Information System (INIS)

    Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

    2015-01-01

    Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

  4. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    Science.gov (United States)

    Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  5. Simple Cell Balance Circuit

    Science.gov (United States)

    Johnson, Steven D.; Byers, Jerry W.; Martin, James A.

    2012-01-01

    A method has been developed for continuous cell voltage balancing for rechargeable batteries (e.g. lithium ion batteries). A resistor divider chain is provided that generates a set of voltages representing the ideal cell voltage (the voltage of each cell should be as if the cells were perfectly balanced). An operational amplifier circuit with an added current buffer stage generates the ideal voltage with a very high degree of accuracy, using the concept of negative feedback. The ideal voltages are each connected to the corresponding cell through a current- limiting resistance. Over time, having the cell connected to the ideal voltage provides a balancing current that moves the cell voltage very close to that ideal level. In effect, it adjusts the current of each cell during charging, discharging, and standby periods to force the cell voltages to be equal to the ideal voltages generated by the resistor divider. The device also includes solid-state switches that disconnect the circuit from the battery so that it will not discharge the battery during storage. This solution requires relatively few parts and is, therefore, of lower cost and of increased reliability due to the fewer failure modes. Additionally, this design uses very little power. A preliminary model predicts a power usage of 0.18 W for an 8-cell battery. This approach is applicable to a wide range of battery capacities and voltages.

  6. Quantum-Circuit Refrigerator

    Science.gov (United States)

    MöTtöNen, Mikko; Tan, Kuan Y.; Masuda, Shumpei; Partanen, Matti; Lake, Russell E.; Govenius, Joonas; Silveri, Matti; Grabert, Hermann

    Quantum technology holds great potential in providing revolutionizing practical applications. However, fast and precise cooling of the functional quantum degrees of freedom on demand remains a major challenge in many solid-state implementations, such as superconducting circuits. We demonstrate direct cooling of a superconducting resonator mode using voltage-controllable quantum tunneling of electrons in a nanoscale refrigerator. In our first experiments on this type of a quantum-circuit refrigerator, we measure the drop in the mode temperature by electron thermometry at a resistor which is coupled to the resonator mode through ohmic losses. To eliminate unwanted dissipation, we remove the probe resistor and directly observe the power spectrum of the resonator output in agreement with the so-called P(E) theory. We also demonstrate in microwave reflection experiments that the internal quality factor of the resonator can be tuned by orders of magnitude. In the future, our refrigerator can be integrated with different quantum electric devices, potentially enhancing their performance. For example, it may prove useful in the initialization of superconducting quantum bits and in dissipation-assisted quantum annealing. We acknowledge European Research Council Grant SINGLEOUT (278117) and QUESS (681311) for funding.

  7. Quasi-Linear Circuit

    Science.gov (United States)

    Bradley, William; Bird, Ross; Eldred, Dennis; Zook, Jon; Knowles, Gareth

    2013-01-01

    This work involved developing spacequalifiable switch mode DC/DC power supplies that improve performance with fewer components, and result in elimination of digital components and reduction in magnetics. This design is for missions where systems may be operating under extreme conditions, especially at elevated temperature levels from 200 to 300 degC. Prior art for radiation-tolerant DC/DC converters has been accomplished utilizing classical magnetic-based switch mode converter topologies; however, this requires specific shielding and component de-rating to meet the high-reliability specifications. It requires complex measurement and feedback components, and will not enable automatic re-optimization for larger changes in voltage supply or electrical loading condition. The innovation is a switch mode DC/DC power supply that eliminates the need for processors and most magnetics. It can provide a well-regulated voltage supply with a gain of 1:100 step-up to 8:1 step down, tolerating an up to 30% fluctuation of the voltage supply parameters. The circuit incorporates a ceramic core transformer in a manner that enables it to provide a well-regulated voltage output without use of any processor components or magnetic transformers. The circuit adjusts its internal parameters to re-optimize its performance for changes in supply voltage, environmental conditions, or electrical loading at the output

  8. Delayed power analysis

    International Nuclear Information System (INIS)

    Adamovich, L.A.; Azarov, V.V.

    1999-01-01

    Time dependent core power behavior in a nuclear reactor is described with well-known neutron kinetics equations. At the same time, two portions are distinguished in energy released from uranium nuclei fission; one released directly at fission and another delayed (residual) portion produced during radioactive decay of fission products. While prompt power is definitely described with kinetics equations, the delayed power presentation still remains outstanding. Since in operation the delayed power part is relatively small (about 6%) operation, it can be neglected for small reactivity disturbances assuming that entire power obeys neutron kinetics equations. In case of a high negative reactivity rapidly inserted in core (e.g. reactor scram initiation) the prompt and delayed components can be calculated separately with practically no impact on each other, employing kinetics equations for prompt power and known approximation formulas for delayed portion, named residual in this specific case. Under substantial disturbances the prompt component in the dynamic process becomes commensurable with delayed portion, thus making necessary to take into account their cross impact. A system of differential equations to describe time-dependent behavior of delayed power is presented. Specific NPP analysis shows a way to significantly simplify the task formulation. (author)

  9. Arithmetic circuits for DSP applications

    CERN Document Server

    Stouraitis, Thanos

    2017-01-01

    Arithmetic Circuits for DSP Applications is a complete resource on arithmetic circuits for digital signal processing (DSP). It covers the key concepts, designs and developments of different types of arithmetic circuits, which can be used for improving the efficiency of implementation of a multitude of DSP applications. Each chapter includes various applications of the respective class of arithmetic circuits along with information on the future scope of research. Written for students, engineers, and researchers in electrical and computer engineering, this comprehensive text offers a clear understanding of different types of arithmetic circuits used for digital signal processing applications. The text includes contributions from noted researchers on a wide range of topics, including a review o circuits used in implementing basic operations like additions and multiplications; distributed arithmetic as a technique for the multiplier-less implementation of inner products for DSP applications; discussions on look ...

  10. Integrated circuit cooled turbine blade

    Science.gov (United States)

    Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.; Holloman, Harry; Koester, Steven

    2017-08-29

    A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channel connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.

  11. Control circuit for transformer relay

    International Nuclear Information System (INIS)

    Wyatt, G.A.

    1984-01-01

    A control circuit for a transformer relay which will automatically momentarily control the transformer relay to a selected state upon energization of the control circuit. The control circuit has an energy storage element and a current director coupled in series and adapted to be coupled with the secondary winding of the transformer relay. A device for discharge is coupled across the energy storage element. The energy storage element and current director will momentarily allow a unidirectional flow of current in the secondary winding of the transformer relay upon application of energy to the control circuit. When energy is not applied to the control circuit the device for discharge will allow the energy storage element to discharge and be available for another operation of the control circuit

  12. Source-circuit design overview

    Science.gov (United States)

    Ross, R. G., Jr.

    1983-01-01

    The source circuit is the fundamental electrical building block of a large central-station array; it consists of a series-parallel network of solar cells that develops full system voltage. The array field is generally made up of a large number of parallel source circuits. Source-circuit electrical configuration is driven by a number of design considerations, which must be considered simultaneously. Array fault tolerance and hot spot heating endurance are examined in detail.

  13. Radiation-sensitive switching circuits

    Energy Technology Data Exchange (ETDEWEB)

    Moore, J.H.; Cockshott, C.P.

    1976-03-16

    A radiation-sensitive switching circuit has a light emitting diode which supplies light to a photo-transistor, the light being interrupted from time to time. When the photo-transistor is illuminated, current builds up and when this current reaches a predetermined value, a trigger circuit changes state. The peak output of the photo-transistor is measured and the trigger circuit is arranged to change state when the output of the device is a set proportion of the peak output, so as to allow for aging of the components. The circuit is designed to control the ignition system in an automobile engine.

  14. Four-junction superconducting circuit

    Science.gov (United States)

    Qiu, Yueyin; Xiong, Wei; He, Xiao-Ling; Li, Tie-Fu; You, J. Q.

    2016-01-01

    We develop a theory for the quantum circuit consisting of a superconducting loop interrupted by four Josephson junctions and pierced by a magnetic flux (either static or time-dependent). In addition to the similarity with the typical three-junction flux qubit in the double-well regime, we demonstrate the difference of the four-junction circuit from its three-junction analogue, including its advantages over the latter. Moreover, the four-junction circuit in the single-well regime is also investigated. Our theory provides a tool to explore the physical properties of this four-junction superconducting circuit. PMID:27356619

  15. Neutron delayed choice experiments

    International Nuclear Information System (INIS)

    Bernstein, H.J.

    1986-01-01

    Delayed choice experiments for neutrons can help extend the interpretation of quantum mechanical phenomena. They may also rule out alternative explanations which static interference experiments allow. A simple example of a feasible neutron test is presented and discussed. (orig.)

  16. Quad nanosecond delay module

    International Nuclear Information System (INIS)

    McDonald, R.J.; Hunter, J.B.; Wozniak, G.J.

    1986-04-01

    Four nanosecond (ns) delay units have been designed to fit in a single-width NIM module. This module is particularly suited for use in conjunction with quad constant fraction timing discriminators (CFTDs) since it has four delay units that can be placed adjacent to the four units of the CFTD. A series of different length cables connected via DIP toggle switches provide delays of 0.60 ns in 4 ns increments. Thus, the CFTD delay can be optimized for pulses of different rise times from approx.10-100 ns. Design work for the PC board and silkscreening of the front panel were done with the MacDraw program on the Apple Mackintosh computer and printed with the Lasewriter printer. 6 refs

  17. Delayed rule following

    OpenAIRE

    Schmitt, David R.

    2001-01-01

    Although the elements of a fully stated rule (discriminative stimulus [SD], some behavior, and a consequence) can occur nearly contemporaneously with the statement of the rule, there is often a delay between the rule statement and the SD. The effects of this delay on rule following have not been studied in behavior analysis, but they have been investigated in rule-like settings in the areas of prospective memory (remembering to do something in the future) and goal pursuit. Discriminative even...

  18. Vernier Delay Unit

    International Nuclear Information System (INIS)

    Pierce, W.B.

    1984-10-01

    This module will accept differential ECL pulses from the auxiliary rear panel or NIM level pulses from the front panel. The pulses are produced at the output with a fixed delay that is software programmable in steps of 0.1 ns over the range of 0.1 to 10.5 ns. Multiple outputs are available at the front panel. Minimum delay through the module is 9 ns

  19. Quad precision delay generator

    International Nuclear Information System (INIS)

    Krishnan, Shanti; Gopalakrishnan, K.R.; Marballi, K.R.

    1997-01-01

    A Quad Precision Delay Generator delays a digital edge by a programmed amount of time, varying from nanoseconds to microseconds. The output of this generator has an amplitude of the order of tens of volts and rise time of the order of nanoseconds. This was specifically designed and developed to meet the stringent requirements of the plasma focus experiments. Plasma focus is a laboratory device for producing and studying nuclear fusion reactions in hot deuterium plasma. 3 figs

  20. Memristor Circuits and Systems

    KAUST Repository

    Zidan, Mohammed A.

    2015-05-01

    Current CMOS-based technologies are facing design challenges related to the continuous scaling down of the minimum feature size, according to Moore’s law. Moreover, conventional computing architecture is no longer an effective way of fulfilling modern applications demands, such as big data analysis, pattern recognition, and vector processing. Therefore, there is an exigent need to shift to new technologies, at both the architecture and the device levels. Recently, memristor devices and structures attracted attention for being promising candidates for this job. Memristor device adds a new dimension for designing novel circuits and systems. In addition, high-density memristor-based crossbar is widely considered to be the essential element for future memory and bio-inspired computing systems. However, numerous challenges need to be addressed before the memristor genuinely replaces current memory and computing technologies, which is the motivation behind this research effort. In order to address the technology challenges, we begin by fabricating and modeling the memristor device. The devices fabricated at our local clean room enriched our understanding of the memristive phenomenon and enabled the experimental testing for our memristor-based circuits. Moreover, our proposed mathematical modeling for memristor behavior is an essential element for the theoretical circuit design stage. Designing and addressing the challenges of memristor systems with practical complexity, however, requires an extra step, which takes the form of a reliable and modular simulation platform. We, therefore, built a new simulation platform for the resistive crossbar, which can simulate realistic size arrays filled with real memory data. In addition, this simulation platform includes various crossbar nonidealities in order to obtain accurate simulation results. Consequently, we were able to address the significant challenges facing the high density memristor crossbar, as the building block for

  1. Basic electronic circuits

    CERN Document Server

    Buckley, P M

    1980-01-01

    In the past, the teaching of electricity and electronics has more often than not been carried out from a theoretical and often highly academic standpoint. Fundamentals and basic concepts have often been presented with no indication of their practical appli­ cations, and all too frequently they have been illustrated by artificially contrived laboratory experiments bearing little relationship to the outside world. The course comes in the form of fourteen fairly open-ended constructional experiments or projects. Each experiment has associated with it a construction exercise and an explanation. The basic idea behind this dual presentation is that the student can embark on each circuit following only the briefest possible instructions and that an open-ended approach is thereby not prejudiced by an initial lengthy encounter with the theory behind the project; this being a sure way to dampen enthusiasm at the outset. As the investigation progresses, questions inevitably arise. Descriptions of the phenomena encounte...

  2. ECCS control circuit

    International Nuclear Information System (INIS)

    Sato, Takashi.

    1986-01-01

    Purpose: To afford a sufficient margin to pressure vibrations upon starting of an automatic depressurization system by dispersing pressure vibration in suppression water due to the opening action of an automatic releaf valve in the automatic depressurization system thereby reducing the dynamic load exerted to the surface of the suppression walls. Constitution: Upon occurrence of loss of coolant accidents, an automatic releaf valve for automatic depressurization is opened to deliver the steams in the pressure vessel into the suppression pool. Since a plurality of automatic releaf valves have usually been disposed, if they are opened simultaneously, excess dynamic loads are exerted due to the pressure vibrations to the wall surface of the suppression pool. In this invention, a control circuit is disposed such that the opening timing for each of the automatic releaf valves is deviated upon occurrence of a driving signal for the automatic depressurization system to thereby disperse the pressure vibrations in the suppression water. (Kamimura, M.)

  3. A dishwasher for circuits

    CERN Multimedia

    Rosaria Marraffino

    2014-01-01

    You have always been told that electronic devices fear water. However, at the Surface Mount Devices (SMD) Workshop here at CERN all the electronic assemblies are cleaned with a machine that looks like a… dishwasher.   The circuit dishwasher. Credit: Clara Nellist.  If you think the image above shows a dishwasher, you wouldn’t be completely wrong. Apart from the fact that the whole pumping system and the case itself are made entirely from stainless steel and chemical resistant materials, and the fact that it washes electrical boards instead of dishes… it works exactly like a dishwasher. It’s a professional machine (mainly used in the pharmaceutical industry) designed to clean everything that can be washed with a water-based chemical soap. This type of treatment increases the lifetime of the electronic boards and therefore the LHC's reliability by preventing corrosion problems in the severe radiation and ozone environment of the LHC tunn...

  4. Modeling cortical circuits.

    Energy Technology Data Exchange (ETDEWEB)

    Rohrer, Brandon Robinson; Rothganger, Fredrick H.; Verzi, Stephen J.; Xavier, Patrick Gordon

    2010-09-01

    The neocortex is perhaps the highest region of the human brain, where audio and visual perception takes place along with many important cognitive functions. An important research goal is to describe the mechanisms implemented by the neocortex. There is an apparent regularity in the structure of the neocortex [Brodmann 1909, Mountcastle 1957] which may help simplify this task. The work reported here addresses the problem of how to describe the putative repeated units ('cortical circuits') in a manner that is easily understood and manipulated, with the long-term goal of developing a mathematical and algorithmic description of their function. The approach is to reduce each algorithm to an enhanced perceptron-like structure and describe its computation using difference equations. We organize this algorithmic processing into larger structures based on physiological observations, and implement key modeling concepts in software which runs on parallel computing hardware.

  5. Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Shikha Panwar

    2014-01-01

    Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

  6. Modelling delays in pharmacokinetics

    International Nuclear Information System (INIS)

    Farooqi, Z.H.; Lambrecht, R.M.

    1990-01-01

    Linear system analysis has come to form the backbone of pharmacokinetics. Natural systems usually involve time delays, thus models incorporating them would be an order closer approximation to the real world compared to those that do not. Delays may be modelled in several ways. The approach considered in this study is to have a discrete-time delay dependent rate with the delay respresenting the duration between the entry of a drug into a compartment and its release in some form (may be as a metabolite) from the compartment. Such a delay may be because of one or more of several physiological reasons, like, formation of a reservoir, slow metabolism, or receptor binding. The mathematical structure this gives rise to is a system of delay-differential equations. Examples are given of simple one and two compartment systems with drugs like bumetanide, carbamazepine, and quinolone-caffeine interaction. In these examples generally a good fit is obtained and the suggested models form a good approximation. 21 refs., 6 figs

  7. Radiofrequency spark chambers and delay line resonators

    International Nuclear Information System (INIS)

    Sayag, Jacques

    1971-01-01

    According to a suggestion of A. Kastler, a spark chamber was excited by an undamped radiofrequency pulse and tracks about 1 mm wide obtained; the result was interpreted by computation of the coefficients of electronic amplification and partial ambipolar diffusion. This work led us to the construction of a new fast triggering undamped wave-train generator of very high tension (patent taken out by the C.E.A. under the no.: EN 7 134 650 the 27.9.1971). Since this apparatus uses a resonant storage line, its design implied a precise knowledge of high impedance delay lines. The experimental radiofrequency spectra of the input impedance of opened or short-circuited lines were plotted completely and analysed by the circuits theory, new measuring methods were established, dispersion relations accurately checked and the equivalence of the formulas, within the third order, with theses of Debye's Dipolar Absorption demonstrated. General properties of Hilbert's transform were also investigated. From the experimental point of view, the electromagnetic energy storage process was extended to the case of a liquid nitrogen-immersed resonant delay line. The good behavior of the cryogenic experiment, where the main difficulty of icing was overcame by the construction of special electrodes, offers great promise for extrapolation to superconductivity. (author) [fr

  8. Monolithic microwave integrated circuit water vapor radiometer

    Science.gov (United States)

    Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

    1991-01-01

    A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

  9. Compact Circuit Preprocesses Accelerometer Output

    Science.gov (United States)

    Bozeman, Richard J., Jr.

    1993-01-01

    Compact electronic circuit transfers dc power to, and preprocesses ac output of, accelerometer and associated preamplifier. Incorporated into accelerometer case during initial fabrication or retrofit onto commercial accelerometer. Made of commercial integrated circuits and other conventional components; made smaller by use of micrologic and surface-mount technology.

  10. Comminution circuits for compact itabirites

    Directory of Open Access Journals (Sweden)

    Pedro Ferreira Pinto

    Full Text Available Abstract In the beneficiation of compact Itabirites, crushing and grinding account for major operational and capital costs. As such, the study and development of comminution circuits have a fundamental importance for feasibility and optimization of compact Itabirite beneficiation. This work makes a comparison between comminution circuits for compact Itabirites from the Iron Quadrangle. The circuits developed are: a crushing and ball mill circuit (CB, a SAG mill and ball mill circuit (SAB and a single stage SAG mill circuit (SSSAG. For the SAB circuit, the use of pebble crushing is analyzed (SABC. An industrial circuit for 25 million tons of run of mine was developed for each route from tests on a pilot scale (grinding and industrial scale. The energy consumption obtained for grinding in the pilot tests was compared with that reported by Donda and Bond. The SSSAG route had the lowest energy consumption, 11.8kWh/t and the SAB route had the highest energy consumption, 15.8kWh/t. The CB and SABC routes had a similar energy consumption of 14.4 kWh/t and 14.5 kWh/t respectively.

  11. Current-mode minimax circuit

    NARCIS (Netherlands)

    Wassenaar, R.F.

    1992-01-01

    The minimum-maximum (minimax) circuit selects the minimum and maximum of two input currents. Four transistors in matched pairs are operated in the saturation region. Because the behavior of the circuit is based on matched devices and is independent of the relationship between the drain current and

  12. Short-circuit impedance measurement

    DEFF Research Database (Denmark)

    Pedersen, Knud Ole Helgesen; Nielsen, Arne Hejde; Poulsen, Niels Kjølstad

    2003-01-01

    Methods for estimating the short-circuit impedance in the power grid are investigated for various voltage levels and situations. The short-circuit impedance is measured, preferably from naturally occurring load changes in the grid, and it is shown that such a measurement system faces different...

  13. Cell short circuit, preshort signature

    Science.gov (United States)

    Lurie, C.

    1980-01-01

    Short-circuit events observed in ground test simulations of DSCS-3 battery in-orbit operations are analyzed. Voltage signatures appearing in the data preceding the short-circuit event are evaluated. The ground test simulation is briefly described along with performance during reconditioning discharges. Results suggest that a characteristic signature develops prior to a shorting event.

  14. Enhancement of Linear Circuit Program

    DEFF Research Database (Denmark)

    Gaunholt, Hans; Dabu, Mihaela; Beldiman, Octavian

    1996-01-01

    In this report a preliminary user friendly interface has been added to the LCP2 program making it possible to describe an electronic circuit by actually drawing the circuit on the screen. Component values and other options and parameters can easily be set by the aid of the interface. The interface...

  15. MOS Current Mode Logic Near Threshold Circuits

    Directory of Open Access Journals (Sweden)

    Alexander Shapiro

    2014-06-01

    Full Text Available Near threshold circuits (NTC are an attractive and promising technology that provides significant power savings with some delay penalty. The combination of NTC technology with MOS current mode logic (MCML is examined in this work. By combining MCML with NTC, the constant power consumption of MCML is reduced to leakage power levels that can be tolerated in certain modern applications. Additionally, the speed of NTC is improved due to the high speed nature of MCML technology. A 14 nm Fin field effect transistor (FinFET technology is used to evaluate these combined circuit techniques. A 32-bit Kogge Stone adder is chosen as a demonstration vehicle for feasibility analysis. MCML with NTC is shown to yield enhanced power efficiency when operated above 1 GHz with a 100% activity factor as compared to standard CMOS. MCML with NTC is more power efficient than standard CMOS beyond 9 GHz over a wide range of activity factors. MCML with NTC also exhibits significantly lower noise levels as compared to standard CMOS. The results of the analysis demonstrate that pairing NTC and MCML is efficient when operating at high frequencies and activity factors.

  16. Wavy Channel TFT-Based Digital Circuits

    KAUST Repository

    Hanna, Amir; Hussain, Aftab M.; Hussain, Aftab M.; Hussain, Aftab M.; Omran, Hesham; Alsharif, Sarah M.; Salama, Khaled N.; Hussain, Muhammad Mustafa

    2016-01-01

    We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.

  17. Wavy Channel TFT-Based Digital Circuits

    KAUST Repository

    Hanna, Amir

    2016-02-23

    We report a wavy channel (WC) architecture thin-film transistor-based digital circuitry using ZnO as a channel material. The novel architecture allows for extending device width by integrating vertical finlike substrate corrugations giving rise to 50% larger device width, without occupying extra chip area. The enhancement in the output drive current is 100%, when compared with conventional planar architecture for devices occupying the same chip area. The current increase is attributed to both the extra device width and 50% enhancement in field-effect mobility due to electrostatic gating effects. Fabricated inverters show that WC inverters can achieve two times the peak-to-peak output voltage for the same input when compared with planar devices. In addition, WC inverters show 30% faster rise and fall times, and can operate up to around two times frequency of the planar inverters for the same peak-to-peak output voltage. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts, and WC pass transistor logic multiplexer circuit has shown more than five times faster high-to-low propagation delay compared with its planar counterpart at a similar peak-to-peak output voltage.

  18. Fractional Delayer Utilizing Hermite Interpolation with Caratheodory Representation

    Directory of Open Access Journals (Sweden)

    Qiang DU

    2018-04-01

    Full Text Available Fractional delay is indispensable for many sorts of circuits and signal processing applications. Fractional delay filter (FDF utilizing Hermite interpolation with an analog differentiator is a straightforward way to delay discrete signals. This method has a low time-domain error, but a complicated sampling module than the Shannon sampling scheme. A simplified scheme, which is based on Shannon sampling and utilizing Hermite interpolation with a digital differentiator, will lead a much higher time-domain error when the signal frequency approaches the Nyquist rate. In this letter, we propose a novel fractional delayer utilizing Hermite interpolation with Caratheodory representation. The samples of differential signal are obtained by Caratheodory representation from the samples of the original signal only. So, only one sampler is needed and the sampling module is simple. Simulation results for four types of signals demonstrate that the proposed method has significantly higher interpolation accuracy than Hermite interpolation with digital differentiator.

  19. Automatic circuit analysis based on mask information

    International Nuclear Information System (INIS)

    Preas, B.T.; Lindsay, B.W.; Gwyn, C.W.

    1976-01-01

    The Circuit Mask Translator (CMAT) code has been developed which converts integrated circuit mask information into a circuit schematic. Logical operations, pattern recognition, and special functions are used to identify and interconnect diodes, transistors, capacitors, and resistances. The circuit topology provided by the translator is compatible with the input required for a circuit analysis program

  20. Novel concept of TDI readout circuit for LWIR detector

    Science.gov (United States)

    Kim, Byunghyuck; Yoon, Nanyoung; Lee, Hee Chul; Kim, Choong-Ki

    2000-07-01

    Noise property is the prime consideration in readout circuit design. The output noise caused by the photon noise, which dominates total noise in BLIP detectors, is limited by the integration time that an element looks at a specific point in the scene. Large integration time leads to a low noise performance. Time-delay integration (TDI) is used to effectively increase the integration time and reduce the photon noise. However, it increases the number of dead pixels and requires large integration capacitors and low noise output stage of the readout circuit. In this paper, to solve these problems, we propose a new concept of readout circuit, which performs background suppression, cell-to-cell background current non-uniformity compensation, and dead pixel correction using memory, ADC, DAC, and current copier cell. In simulation results, comparing with the conventional TDI readout circuit, the integration capacitor size can be reduced to 1/5 and trans-impedance gain can be increased by five times. Therefore, the new TDI readout circuit does not require large area and low noise output stage. And the error of skimming current is less than 2%, and the fixed pattern noise induced by cell-to-cell background current variation is reduced to less than 1%.

  1. Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

    International Nuclear Information System (INIS)

    Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun

    2016-01-01

    The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD

  2. Updating Procedures Can Reorganize the Neural Circuit Supporting a Fear Memory.

    Science.gov (United States)

    Kwapis, Janine L; Jarome, Timothy J; Ferrara, Nicole C; Helmstetter, Fred J

    2017-07-01

    Established memories undergo a period of vulnerability following retrieval, a process termed 'reconsolidation.' Recent work has shown that the hypothetical process of reconsolidation is only triggered when new information is presented during retrieval, suggesting that this process may allow existing memories to be modified. Reconsolidation has received increasing attention as a possible therapeutic target for treating disorders that stem from traumatic memories, yet little is known about how this process changes the original memory. In particular, it is unknown whether reconsolidation can reorganize the neural circuit supporting an existing memory after that memory is modified with new information. Here, we show that trace fear memory undergoes a protein synthesis-dependent reconsolidation process following exposure to a single updating trial of delay conditioning. Further, this reconsolidation-dependent updating process appears to reorganize the neural circuit supporting the trace-trained memory, so that it better reflects the circuit supporting delay fear. Specifically, after a trace-to-delay update session, the amygdala is now required for extinction of the updated memory but the retrosplenial cortex is no longer required for retrieval. These results suggest that updating procedures could be used to force a complex, poorly defined memory circuit to rely on a better-defined neural circuit that may be more amenable to behavioral or pharmacological manipulation. This is the first evidence that exposure to new information can fundamentally reorganize the neural circuit supporting an existing memory.

  3. Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun [KHNP CRI, Daejeon (Korea, Republic of)

    2016-10-15

    The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD.

  4. Fast 4-2 Compressor of Booth Multiplier Circuits for High-Speed RISC Processor

    Science.gov (United States)

    Yuan, S. C.

    2008-11-01

    We use different XOR circuits to optimize the XOR structure 4-2 compressor, and design the transmission gates(TG) 4-2 compressor use single to dual rail circuit configurations. The maximum propagation delay, the power consumption and the layout area of the designed 4-2 compressors are simulated with 0.35μm and 0.25μm CMOS process parameters and compared with results of the synthesized 4-2 circuits, and show that the designed 4-2 compressors are faster and area smaller than the synthesized one.

  5. Optimal Joint Expected Delay Forwarding in Delay Tolerant Networks

    OpenAIRE

    Jia Xu; Xin Feng; Wen Jun Yang; Ru Chuan Wang; Bing Qing Han

    2013-01-01

    Multicopy forwarding schemes have been employed in delay tolerant network (DTN) to improve the delivery delay and delivery rate. Much effort has been focused on reducing the routing cost while retaining high performance. This paper aims to provide an optimal joint expected delay forwarding (OJEDF) protocol which minimizes the expected delay while satisfying a certain constant on the number of forwardings per message. We propose a comprehensive forwarding metric called joint expected delay (JE...

  6. Nanofluidic Transistor Circuits

    Science.gov (United States)

    Chang, Hsueh-Chia; Cheng, Li-Jing; Yan, Yu; Slouka, Zdenek; Senapati, Satyajyoti

    2012-02-01

    Non-equilibrium ion/fluid transport physics across on-chip membranes/nanopores is used to construct rectifying, hysteretic, oscillatory, excitatory and inhibitory nanofluidic elements. Analogs to linear resistors, capacitors, inductors and constant-phase elements were reported earlier (Chang and Yossifon, BMF 2009). Nonlinear rectifier is designed by introducing intra-membrane conductivity gradient and by asymmetric external depletion with a reverse rectification (Yossifon and Chang, PRL, PRE, Europhys Lett 2009-2011). Gating phenomenon is introduced by functionalizing polyelectrolytes whose conformation is field/pH sensitive (Wang, Chang and Zhu, Macromolecules 2010). Surface ion depletion can drive Rubinstein's microvortex instability (Chang, Yossifon and Demekhin, Annual Rev of Fluid Mech, 2012) or Onsager-Wien's water dissociation phenomenon, leading to two distinct overlimiting I-V features. Bipolar membranes exhibit an S-hysteresis due to water dissociation (Cheng and Chang, BMF 2011). Coupling the hysteretic diode with some linear elements result in autonomous ion current oscillations, which undergo classical transitions to chaos. Our integrated nanofluidic circuits are used for molecular sensing, protein separation/concentration, electrospray etc.

  7. Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

    OpenAIRE

    石橋, 孝昭

    2012-01-01

    This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

  8. Variational integrators for electric circuits

    International Nuclear Information System (INIS)

    Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.

    2013-01-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator

  9. Proposal for a fast, zero suppressing circuit for the digitization of analog pulses over long memory times

    International Nuclear Information System (INIS)

    Bourgeois, F.

    1984-01-01

    This report describes the design principles of a fast (100 MHz) time and pulse height digitizer that can record up to 15 analog pulses over 10-80 μs memory times. Unlike other triggered circuits prepulse samples are recorded without the help of an analog delay line. The low power requirements of the circuit as well as its fast read-out characteristics make it very attractive for detectors with many digitizing channels. Conventional circuits are described as a reference for the evaluation of this new design. An ECL 10 K implementation of the circuit is presented in the third section. (orig.)

  10. Test and Diagnosis for Small-Delay Defects

    CERN Document Server

    Tehranipoor, Mohammad; Chakrabarty, Krishnendu

    2012-01-01

    This book introduces new techniques for detecting and diagnosing small-delay defects (SDD) in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first book to introduce effective and scalable methodologies for screening and diagnosing small-delay defects, including important parameters such as process variations, crosstalk, and power supply noise. This book presents new techniques and methodologies to improve overall SDD detection with very small pattern sets. These methods can result in pattern counts as low as a traditional 1-detect pattern set and long path sensitization and SDD detection similar to or even better than n-detect or timing-aware pattern sets. The important design parameters and pattern-induced noises such as process variations,power supply noise (PSN) and crosstalk are taken into account in the methodologies presented. A diagnostic flow is also presented to identify whether the failure is ...

  11. Integrated circuits, and design and manufacture thereof

    Science.gov (United States)

    Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

    2006-04-18

    A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

  12. Radiation-sensitive switching circuits

    Energy Technology Data Exchange (ETDEWEB)

    Moore, J.H.; Cockshott, C.P.

    1976-03-16

    A radiation-sensitive switching circuit includes a light emitting diode which from time to time illuminates a photo-transistor, the photo-transistor serving when its output reaches a predetermined value to operate a trigger circuit. In order to allow for aging of the components, the current flow through the diode is increased when the output from the transistor falls below a known level. Conveniently, this is achieved by having a transistor in parallel with the diode, and turning the transistor off when the output from the phototransistor becomes too low. The circuit is designed to control the ignition system in an automobile engine.

  13. The Maplin electronic circuits handbook

    CERN Document Server

    Tooley, Michael

    1990-01-01

    The Maplin Electronic Circuits Handbook provides pertinent data, formula, explanation, practical guidance, theory and practical guidance in the design, testing, and construction of electronic circuits. This book discusses the developments in electronics technology techniques.Organized into 11 chapters, this book begins with an overview of the common types of passive component. This text then provides the reader with sufficient information to make a correct selection of passive components for use in the circuits. Other chapters consider the various types of the most commonly used semiconductor

  14. Secure integrated circuits and systems

    CERN Document Server

    Verbauwhede, Ingrid MR

    2010-01-01

    On any advanced integrated circuit or 'system-on-chip' there is a need for security. In many applications the actual implementation has become the weakest link in security rather than the algorithms or protocols. The purpose of the book is to give the integrated circuits and systems designer an insight into the basics of security and cryptography from the implementation point of view. As a designer of integrated circuits and systems it is important to know both the state-of-the-art attacks as well as the countermeasures. Optimizing for security is different from optimizations for speed, area,

  15. INTEGRATED SENSOR EVALUATION CIRCUIT AND METHOD FOR OPERATING SAID CIRCUIT

    OpenAIRE

    Krüger, Jens; Gausa, Dominik

    2015-01-01

    WO15090426A1 Sensor evaluation device and method for operating said device Integrated sensor evaluation circuit for evaluating a sensor signal (14) received from a sensor (12), having a first connection (28a) for connection to the sensor and a second connection (28b) for connection to the sensor. The integrated sensor evaluation circuit comprises a configuration data memory (16) for storing configuration data which describe signal properties of a plurality of sensor control signals (26a-c). T...

  16. A note on exponential convergence of neural networks with unbounded distributed delays

    Energy Technology Data Exchange (ETDEWEB)

    Chu Tianguang [Intelligent Control Laboratory, Center for Systems and Control, Department of Mechanics and Engineering Science, Peking University, Beijing 100871 (China)]. E-mail: chutg@pku.edu.cn; Yang Haifeng [Intelligent Control Laboratory, Center for Systems and Control, Department of Mechanics and Engineering Science, Peking University, Beijing 100871 (China)

    2007-12-15

    This note examines issues concerning global exponential convergence of neural networks with unbounded distributed delays. Sufficient conditions are derived by exploiting exponentially fading memory property of delay kernel functions. The method is based on comparison principle of delay differential equations and does not need the construction of any Lyapunov functionals. It is simple yet effective in deriving less conservative exponential convergence conditions and more detailed componentwise decay estimates. The results of this note and [Chu T. An exponential convergence estimate for analog neural networks with delay. Phys Lett A 2001;283:113-8] suggest a class of neural networks whose globally exponentially convergent dynamics is completely insensitive to a wide range of time delays from arbitrary bounded discrete type to certain unbounded distributed type. This is of practical interest in designing fast and reliable neural circuits. Finally, an open question is raised on the nature of delay kernels for attaining exponential convergence in an unbounded distributed delayed neural network.

  17. A note on exponential convergence of neural networks with unbounded distributed delays

    International Nuclear Information System (INIS)

    Chu Tianguang; Yang Haifeng

    2007-01-01

    This note examines issues concerning global exponential convergence of neural networks with unbounded distributed delays. Sufficient conditions are derived by exploiting exponentially fading memory property of delay kernel functions. The method is based on comparison principle of delay differential equations and does not need the construction of any Lyapunov functionals. It is simple yet effective in deriving less conservative exponential convergence conditions and more detailed componentwise decay estimates. The results of this note and [Chu T. An exponential convergence estimate for analog neural networks with delay. Phys Lett A 2001;283:113-8] suggest a class of neural networks whose globally exponentially convergent dynamics is completely insensitive to a wide range of time delays from arbitrary bounded discrete type to certain unbounded distributed type. This is of practical interest in designing fast and reliable neural circuits. Finally, an open question is raised on the nature of delay kernels for attaining exponential convergence in an unbounded distributed delayed neural network

  18. Improved On-Chip Measurement of Delay in an FPGA or ASIC

    Science.gov (United States)

    Chen, Yuan; Burke, Gary; Sheldon, Douglas

    2007-01-01

    An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

  19. Assessing delay discounting in mice

    OpenAIRE

    Mitchell, Suzanne H.

    2014-01-01

    Delay discounting (also intertemporal choice or impulsive choice) is the process by which delayed outcomes, such as delayed food delivery, are valued less than the same outcomes delivered immediately or with a shorter delay. This process is of interest because many psychopathologies, including substance dependence, pathological gambling, attention deficit hyperactivity disorder and conduct disorder, are characterized by heightened levels of delay discounting. Some of these disorders are herit...

  20. Quantum circuit behaviour

    International Nuclear Information System (INIS)

    Poulton, D.

    1989-09-01

    Single electron tunnelling in multiply connected weak link systems is considered. Using a second quantised approach the tunnel current, in both normal and superconducting systems, using perturbation theory, is derived. The tunnel currents are determined as a function of an Aharanov-Bohm phase (acquired by the electrons). Using these results, the multiply connected system is then discussed when coupled to a resonant LC circuit. The resulting dynamics of this composite system are then determined. In the superconducting case the results are compared and contrasted with flux mode behaviour seen in large superconducting weak link rings. Systems in which the predicted dynamics may be seen are also discussed. In analogy to the electron tunnelling analysis, the tunnelling of magnetic flux quanta through the weak link is also considered. Here, the voltage across the weak link, due to flux tunnelling, is determined as a function of an externally applied current. This is done for both singly and multiply connected flux systems. The results are compared and contrasted with charge mode behaviour seen in superconducting weak link systems. Finally, the behaviour of simple quantum fluids is considered when subject to an external rotation. Using a microscopic analysis it is found that the microscopic quantum behaviour of the particles is manifest on a macroscopic level. Results are derived for bosonic, fermionic and BCS pair-type systems. The connection between flux quantisation in electromagnetic systems is also made. Using these results, the dynamics of such a quantum fluid is considered when coupled to a rotating torsional oscillator. The results are compared with those found in SQUID devices. A model is also presented which discusses the possible excited state dynamics of such a fluid. (author)

  1. Permissible Delay in Payments

    Directory of Open Access Journals (Sweden)

    Yung-Fu Huang

    2007-01-01

    Full Text Available The main purpose of this paper wants to investigate the optimal retailer's lot-sizing policy with two warehouses under partially permissible delay in payments within the economic order quantity (EOQ framework. In this paper, we want to extend that fully permissible delay in payments to the supplier would offer the retailer partially permissible delay in payments. That is, the retailer must make a partial payment to the supplier when the order is received. Then the retailer must pay off the remaining balance at the end of the permissible delay period. In addition, we want to add the assumption that the retailer's storage space is limited. That is, the retailer will rent the warehouse to store these exceeding items when the order quantity is larger than retailer's storage space. Under these conditions, we model the retailer's inventory system as a cost minimization problem to determine the retailer's optimal cycle time and optimal order quantity. Three theorems are developed to efficiently determine the optimal replenishment policy for the retailer. Finally, numerical examples are given to illustrate these theorems and obtained a lot of managerial insights.

  2. Delayed neutrons in ANSTO

    International Nuclear Information System (INIS)

    Wall, T.

    1988-01-01

    Delayed neutron analysis carried out at the Australian Nuclear Scientific and Technology Organization facilities, provides a fast, high sensitivity, low cost, reliable method, particularly suitable for large batches of samples, and for non destructive analysis of a range of materials. While its main use has been in uranium exploration, other applications include archeological investigations, agriculture, oceanography and biology

  3. Emergency reactor cooling circuit

    International Nuclear Information System (INIS)

    Araki, Hidefumi; Matsumoto, Tomoyuki; Kataoka, Yoshiyuki.

    1994-01-01

    Cooling water in a gravitationally dropping water reservoir is injected into a reactor pressure vessel passing through a pipeline upon occurrence of emergency. The pipeline is inclined downwardly having one end thereof being in communication with the pressure vessel. During normal operation, the cooling water in the upper portion of the inclined pipeline is heated by convection heat transfer from the communication portion with the pressure vessel. On the other hand, cooling water present at a position lower than the communication portion forms cooling water lumps. Accordingly, temperature stratification layers are formed in the inclined pipeline. Therefore, temperature rise of water in a vertical pipeline connected to the inclined pipeline is small. With such a constitution, the amount of heat lost from the pressure vessel by way of the water injection pipeline is reduced. Further, there is no worry that cooling water to be injected upon occurrence of emergency is boiled under reduced pressure in the injection pipeline to delay the depressurization of the pressure vessel. (I.N.)

  4. Transistor and integrated circuit manufacture

    International Nuclear Information System (INIS)

    Colman, D.

    1978-01-01

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

  5. Time domain analog circuit simulation

    NARCIS (Netherlands)

    Fijnvandraat, J.G.; Houben, S.H.M.J.; Maten, ter E.J.W.; Peters, J.M.F.

    2006-01-01

    Recent developments of new methods for simulating electric circuits are described. Emphasis is put on methods that fit existing datastructures for backward differentiation formulae methods. These methods can be modified to apply to hierarchically organized datastructures, which allows for efficient

  6. Circuit design on plastic foils

    CERN Document Server

    Raiteri, Daniele; Roermund, Arthur H M

    2015-01-01

    This book illustrates a variety of circuit designs on plastic foils and provides all the information needed to undertake successful designs in large-area electronics.  The authors demonstrate architectural, circuit, layout, and device solutions and explain the reasons and the creative process behind each. Readers will learn how to keep under control large-area technologies and achieve robust, reliable circuit designs that can face the challenges imposed by low-cost low-temperature high-throughput manufacturing.   • Discusses implications of problems associated with large-area electronics and compares them to standard silicon; • Provides the basis for understanding physics and modeling of disordered material; • Includes guidelines to quickly setup the basic CAD tools enabling efficient and reliable designs; • Illustrates practical solutions to cope with hard/soft faults, variability, mismatch, aging and bias stress at architecture, circuit, layout, and device levels.

  7. Discharge quenching circuit for counters

    International Nuclear Information System (INIS)

    Karasik, A.S.

    1982-01-01

    A circuit for quenching discharges in gas-discharge detectors with working voltage of 3-5 kV based on transistors operating in the avalanche mode is described. The quenching circuit consists of a coordinating emitter follower, amplifier-shaper for avalanche key cascade control which changes potential on the counter electrodes and a shaper of discharge quenching duration. The emitter follower is assembled according to a widely used flowsheet with two transistors. The circuit permits to obtain a rectangular quenching pulse with front of 100 ns and an amplitude of up to 3.2 kV at duration of 500 μm-8 ms. Application of the quenching circuit described permits to obtain countering characteristics with the slope less than or equal to 0.02%/V and plateau extent greater than or equal to 300 V [ru

  8. Transistor and integrated circuit manufacture

    Energy Technology Data Exchange (ETDEWEB)

    Colman, D

    1978-09-27

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

  9. Ignition circuit for combustion engines

    Energy Technology Data Exchange (ETDEWEB)

    Becker, H W

    1977-05-26

    The invention refers to the ignition circuit for combustion engines, which are battery fed. The circuit contains a transistor and an oscillator to produce an output voltage on the secondary winding of an output transformer to supply an ignition current. The plant is controlled by an interrupter. The purpose of the invention is to form such a circuit that improved sparks for ignition are produced, on the one hand, and that on the other hand, the plant can continue to function after loss of the oscillator. The problem is solved by the battery and the secondary winding of the output transformers of the oscillator are connected via a rectifier circuit to produce a resultant total voltage with the ignition coil from the battery voltage and the rectified pulsating oscillator output.

  10. Reverse engineering of integrated circuits

    Science.gov (United States)

    Chisholm, Gregory H.; Eckmann, Steven T.; Lain, Christopher M.; Veroff, Robert L.

    2003-01-01

    Software and a method therein to analyze circuits. The software comprises several tools, each of which perform particular functions in the Reverse Engineering process. The analyst, through a standard interface, directs each tool to the portion of the task to which it is most well suited, rendering previously intractable problems solvable. The tools are generally used iteratively to produce a successively more abstract picture of a circuit, about which incomplete a priori knowledge exists.

  11. Receiver Gain Modulation Circuit

    Science.gov (United States)

    Jones, Hollis; Racette, Paul; Walker, David; Gu, Dazhen

    2011-01-01

    A receiver gain modulation circuit (RGMC) was developed that modulates the power gain of the output of a radiometer receiver with a test signal. As the radiometer receiver switches between calibration noise references, the test signal is mixed with the calibrated noise and thus produces an ensemble set of measurements from which ensemble statistical analysis can be used to extract statistical information about the test signal. The RGMC is an enabling technology of the ensemble detector. As a key component for achieving ensemble detection and analysis, the RGMC has broad aeronautical and space applications. The RGMC can be used to test and develop new calibration algorithms, for example, to detect gain anomalies, and/or correct for slow drifts that affect climate-quality measurements over an accelerated time scale. A generalized approach to analyzing radiometer system designs yields a mathematical treatment of noise reference measurements in calibration algorithms. By treating the measurements from the different noise references as ensemble samples of the receiver state, i.e. receiver gain, a quantitative description of the non-stationary properties of the underlying receiver fluctuations can be derived. Excellent agreement has been obtained between model calculations and radiometric measurements. The mathematical formulation is equivalent to modulating the gain of a stable receiver with an externally generated signal and is the basis for ensemble detection and analysis (EDA). The concept of generating ensemble data sets using an ensemble detector is similar to the ensemble data sets generated as part of ensemble empirical mode decomposition (EEMD) with exception of a key distinguishing factor. EEMD adds noise to the signal under study whereas EDA mixes the signal with calibrated noise. It is mixing with calibrated noise that permits the measurement of temporal-functional variability of uncertainty in the underlying process. The RGMC permits the evaluation of EDA by

  12. Delayed traumatic intracranial hematoma

    International Nuclear Information System (INIS)

    Tomita, Hiroki

    1984-01-01

    CT was performed serially within 24 hours after head injury in 64 patients having Glasgow Coma Scale of 14 or less or cranial fracture shown on roentgenogram. Delayed traumatic extradural hematoma was observed within 7-12 hours after head injury in 6 cases (9.4%). This was prominent in the frontal and occipital regions (67%). Good recovery was seen in 83.3%. Delayed traumatic intracerebral hematoma was observed within 6-24 hours after head injury in 17 cases (26.6%). This higher incidence was related to contre coup injury. Conservative treatment was possible in 14 of the 17 patients (82.4%), showing good recovery in 70%. (Namekawa, K.)

  13. Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

    Science.gov (United States)

    Yuan, Shoucai; Liu, Yamei

    2016-08-01

    This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

  14. Spectral Purity Enhancement via Polyphase Multipath Circuits

    NARCIS (Netherlands)

    Mensink, E.; Klumperink, Eric A.M.; Nauta, Bram

    2004-01-01

    The central question of this paper is: can we enhance the spectral purity of nonlinear circuits by using polyphase multipath circuits? The basic idea behind polyphase multipath circuits is to split the nonlinear circuits into two or more paths and exploit phase differences between these paths to

  15. Distortion Cancellation via Polyphase Multipath Circuits

    NARCIS (Netherlands)

    Mensink, E.; Klumperink, Eric A.M.; Nauta, Bram

    The central question of this paper is: can we enhance the spectral purity of nonlinear circuits with the help of polyphase multipath circuits. Polyphase multipath circuits are circuits with two or more paths that exploit phase differences between the paths to cancel unwanted signals. It turns out

  16. Dynamic theory for the mesoscopic electric circuit

    International Nuclear Information System (INIS)

    Chen Bin; Shen Xiaojuan; Li Youquan; Sun LiLy; Yin Zhujian

    2005-01-01

    The quantum theory for mesoscopic electric circuit with charge discreteness is briefly described. The minibands of quasienergy in LC design mesoscopic electric circuit have been found. In the mesoscopic 'pure' inductance design circuit, just like in the mesoscopic metallic rings, the quantum dynamic characteristics have been obtained explicitly. In the 'pure' capacity design circuit, the Coulomb blockade had also been addressed

  17. Multi-Layer E-Textile Circuits

    Science.gov (United States)

    Dunne, Lucy E.; Bibeau, Kaila; Mulligan, Lucie; Frith, Ashton; Simon, Cory

    2012-01-01

    Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

  18. Time-Delay Interferometry

    Directory of Open Access Journals (Sweden)

    Massimo Tinto

    2014-08-01

    Full Text Available Equal-arm detectors of gravitational radiation allow phase measurements many orders of magnitude below the intrinsic phase stability of the laser injecting light into their arms. This is because the noise in the laser light is common to both arms, experiencing exactly the same delay, and thus cancels when it is differenced at the photo detector. In this situation, much lower level secondary noises then set the overall performance. If, however, the two arms have different lengths (as will necessarily be the case with space-borne interferometers, the laser noise experiences different delays in the two arms and will hence not directly cancel at the detector. In order to solve this problem, a technique involving heterodyne interferometry with unequal arm lengths and independent phase-difference readouts has been proposed. It relies on properly time-shifting and linearly combining independent Doppler measurements, and for this reason it has been called time-delay interferometry (TDI. This article provides an overview of the theory, mathematical foundations, and experimental aspects associated with the implementation of TDI. Although emphasis on the application of TDI to the Laser Interferometer Space Antenna (LISA mission appears throughout this article, TDI can be incorporated into the design of any future space-based mission aiming to search for gravitational waves via interferometric measurements. We have purposely left out all theoretical aspects that data analysts will need to account for when analyzing the TDI data combinations.

  19. Investigation of SFQ integrated circuits using Nb fabrication technology

    International Nuclear Information System (INIS)

    Numata, H.; Tanaka, M.; Kitagawa, Y.; Tahara, S.

    1999-01-01

    In NEC's standard process, the minimum junction size is 2 μm and the critical current density (J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation (σ) of the critical current (I C ) was 0.9% for the 2 μm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits. (author)

  20. Instrumentation and test gear circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Instrumentation and Test Gear Circuits Manual provides diagrams, graphs, tables, and discussions of several types of practical circuits. The practical circuits covered in this book include attenuators, bridges, scope trace doublers, timebases, and digital frequency meters. Chapter 1 discusses the basic instrumentation and test gear principles. Chapter 2 deals with the design of passive attenuators, and Chapter 3 with passive and active filter circuits. The subsequent chapters tackle 'bridge' circuits, analogue and digital metering techniques and circuitry, signal and waveform generation, and p

  1. Logic circuits from zero forcing.

    Science.gov (United States)

    Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael

    We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.

  2. 30 CFR 75.601-1 - Short circuit protection; ratings and settings of circuit breakers.

    Science.gov (United States)

    2010-07-01

    ... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Short circuit protection; ratings and settings... Trailing Cables § 75.601-1 Short circuit protection; ratings and settings of circuit breakers. Circuit breakers providing short circuit protection for trailing cables shall be set so as not to exceed the...

  3. 30 CFR 77.506 - Electric equipment and circuits; overload and short-circuit protection.

    Science.gov (United States)

    2010-07-01

    ... short-circuit protection. 77.506 Section 77.506 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... circuits; overload and short-circuit protection. Automatic circuit-breaking devices or fuses of the correct type and capacity shall be installed so as to protect all electric equipment and circuits against short...

  4. 30 CFR 75.518 - Electric equipment and circuits; overload and short circuit protection.

    Science.gov (United States)

    2010-07-01

    ... short circuit protection. 75.518 Section 75.518 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION... Equipment-General § 75.518 Electric equipment and circuits; overload and short circuit protection... installed so as to protect all electric equipment and circuits against short circuit and overloads. Three...

  5. Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

    Science.gov (United States)

    Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

    2011-07-01

    This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

  6. Delayed Dopamine Signaling of Energy Level Builds Appetitive Long-Term Memory in Drosophila

    OpenAIRE

    Pierre-Yves Musso; Paul Tchenio; Thomas Preat

    2015-01-01

    Sensory cues relevant to a food source, such as odors, can be associated with post-ingestion signals related either to food energetic value or toxicity. Despite numerous behavioral studies, a global understanding of the mechanisms underlying these long delay associations remains out of reach. Here, we demonstrate in Drosophila that the long-term association between an odor and a nutritious sugar depends on delayed post-ingestion signaling of energy level. We show at the neural circuit level t...

  7. Approaching the Processes in the Generator Circuit Breaker at Disconnection through Sustainability Concepts

    Directory of Open Access Journals (Sweden)

    Carmen A. Bulucea

    2013-03-01

    Full Text Available Nowadays, the electric connection circuits of power plants (based on fossil fuels as well as renewable sources entail generator circuit-breakers (GCBs at the generator terminals, since the presence of that electric equipment offers many advantages related to the sustainability of a power plant. In an alternating current (a.c. circuit the interruption of a short circuit is performed by the circuit-breaker at the natural passing through zero of the short-circuit current. During the current interruption, an electric arc is generated between the opened contacts of the circuit-breaker. This arc must be cooled and extinguished in a controlled way. Since the synchronous generator stator can flow via highly asymmetrical short-circuit currents, the phenomena which occur in the case of short-circuit currents interruption determine the main stresses of the generator circuit-breaker; the current interruption requirements of a GCB are significantly higher than for the distribution network circuit breakers. For shedding light on the proper moment when the generator circuit-breaker must operate, using the space phasor of the short-circuit currents, the time expression to the first zero passing of the short-circuit current is determined. Here, the manner is investigated in which various factors influence the delay of the zero passing of the short-circuit current. It is shown that the delay time is influenced by the synchronous machine parameters and by the load conditions which precede the short-circuit. Numerical simulations were conducted of the asymmetrical currents in the case of the sudden three-phase short circuit at the terminals of synchronous generators. Further in this study it is emphasized that although the phenomena produced in the electric arc at the terminals of the circuit-breaker are complicated and not completely explained, the concept of exergy is useful in understanding the physical phenomena. The article points out that just after the short-circuit

  8. Multiplication circuit for particle identification

    International Nuclear Information System (INIS)

    Gerlier, Jean

    1962-01-01

    After having commented some characteristics of the particles present in a cyclotron, and their interactions, this report addresses the development and the implementation of a method and a device for selecting and counting particles. The author presents the principle and existing techniques of selection. In comparison with an existing device, the proportional counter and the scintillator are replaced by junctions: a surface barrier type junction (a silicon N layer with a very thin oxygen layer playing the role of the P layer), and lithium-based junction (a silicon P type layer made intrinsic by migration of lithium). The author then describes the developed circuit and assembly (background of the choice of a multiplication circuit), and their operation. In the next part, he presents the performed tests and discuses the obtained results. He finally outlines the benefits of the herein presented circuit [fr

  9. Wiring of electronic evaluation circuits

    International Nuclear Information System (INIS)

    Bauer, R.; Svoboda, Z.

    1977-01-01

    The wiring is described of electronic evaluation circuits for the automatic viewing of photographic paper strip negatives on which line tracks with an angular scatter relative to the spectrograph longitudinal axis were recorded during the oblique flight of nuclear particles during exposure in the spectrograph. In coincidence evaluation, the size of the angular scatter eventually requires that evaluation dead time be increased. The equipment consists of minimally two fixed registers and a block of logic circuits whose output is designed such as will allow connection to equipment for recording signals corresponding to the number of tracks on the film. The connection may be implemented using integrated circuits guaranteeing high operating reliability and life. (J.B.)

  10. Counterpulse railgun energy recovery circuit

    International Nuclear Information System (INIS)

    Honig, E.M.

    1986-01-01

    This patent describes a counterpulse railgun energy recovery circuit for propelling a projectile along a railgun the counterpulse railgun energy recovery circuit consists of: a railgun having an effective inductance; a source inductor initially charged to an initial current; current means for initially charging the source inductor to the initial current; first current-zero type switching means; second current-zero type switching; third current-zero type switching; muzzle current-zero type switching means; transfer capacitor, the transfer capacitor is for cooperating with the first, second, third, and muzzle current-zero type switching means for providing a resonant circuit for transferring current from the source inductor to the effective inductance of the railgun during the propelling of a projectile along the railgun and for returning current from the effective inductance of the railgun to the source inductance after the projectile has exited the railgun

  11. Vertically Integrated Circuits at Fermilab

    International Nuclear Information System (INIS)

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  12. Delayed child-bearing.

    Science.gov (United States)

    Johnson, Jo-Ann; Tough, Suzanne

    2012-01-01

    To provide an overview of delayed child-bearing and to describe the implications for women and health care providers. Delayed child-bearing, which has increased greatly in recent decades, is associated with an increased risk of infertility, pregnancy complications, and adverse pregnancy outcome. This guideline provides information that will optimize the counselling and care of Canadian women with respect to their reproductive choices. Maternal age is the most important determinant of fertility, and obstetric and perinatal risks increase with maternal age. Many women are unaware of the success rates or limitations of assisted reproductive technology and of the increased medical risks of delayed child-bearing, including multiple births, preterm delivery, stillbirth, and Caesarean section. This guideline provides a framework to address these issues. Studies published between 2000 and August 2010 were retrieved through searches of PubMed and the Cochrane Library using appropriate key words (delayed child-bearing, deferred pregnancy, maternal age, assisted reproductive technology, infertility, and multiple births) and MeSH terms (maternal age, reproductive behaviour, fertility). The Internet was also searched using similar key words, and national and international medical specialty societies were searched for clinical practice guidelines and position statements. Data were extracted based on the aims, sample, authors, year, and results. The quality of evidence was rated using the criteria described in the Report of the Canadian Task Force on Preventive Health Care (Table 1). The Society of Obstetricians and Gynaecologists of Canada. RECOMMENDATIONS 1. Women who delay child-bearing are at increased risk of infertility. Prospective parents, especially women, should know that their fecundity and fertility begin to decline significantly after 32 years of age. Prospective parents should know that assisted reproductive technologies cannot guarantee a live birth or completely

  13. Cycles of self-pulsations in a photonic integrated circuit.

    Science.gov (United States)

    Karsaklian Dal Bosco, Andreas; Kanno, Kazutaka; Uchida, Atsushi; Sciamanna, Marc; Harayama, Takahisa; Yoshimura, Kazuyuki

    2015-12-01

    We report experimentally on the bifurcation cascade leading to the appearance of self-pulsation in a photonic integrated circuit in which a laser diode is subjected to delayed optical feedback. We study the evolution of the self-pulsing frequency with the increase of both the feedback strength and the injection current. Experimental observations show good qualitative accordance with numerical results carried out with the Lang-Kobayashi rate equation model. We explain the mechanism underlying the self-pulsations by a phenomenon of beating between successive pairs of external cavity modes and antimodes.

  14. Spiking neuron devices consisting of single-flux-quantum circuits

    International Nuclear Information System (INIS)

    Hirose, Tetsuya; Asai, Tetsuya; Amemiya, Yoshihito

    2006-01-01

    Single-flux-quantum (SFQ) circuits can be used for making spiking neuron devices, which are useful elements for constructing intelligent, brain-like computers. The device we propose is based on the leaky integrate-and-fire neuron (IFN) model and uses a SFQ pulse as an action signal or a spike of neurons. The operation of the neuron device is confirmed by computer simulator. It can operate with a short delay of 100 ps or less and is the highest-speed neuron device ever reported

  15. Monitoring Sodium Circuits and ACSR cables using Fiber Optic Sensors

    International Nuclear Information System (INIS)

    Kasinathan, M.; Sosamma, S.; Babu-Rao, C.; Kumar, Anish; Purna-Chandra-Rao, B.; Murali, N; Jayakumar, T.

    2013-06-01

    Raman Distributed Temperature Sensors (RDTS) are attractive for the monitoring of coolant loop systems in nuclear power plants and monitoring of overhead power transmission lines. This paper discusses deployment of RDTS on double walled pipelines of primary sodium circuits in Fast Breeder Reactors (FBR). It is demonstrated as a proof-of-concept on a test loop with water as the leaking medium. Path delay multiplexing is adopted to improve the spatial resolution from 1.02 m to 0.5 m. A second application focuses on the influence of environmental factors on the detectability of defects in the ACSR cables using RDTS. (authors)

  16. Delaying information search

    Directory of Open Access Journals (Sweden)

    Yaniv Shani

    2012-11-01

    Full Text Available In three studies, we examined factors that may temporarily attenuate information search. People are generally curious and dislike uncertainty, which typically encourages them to look for relevant information. Despite these strong forces that promote information search, people sometimes deliberately delay obtaining valuable information. We find they may do so when they are concerned that the information might interfere with future pleasurable activities. Interestingly, the decision to search or to postpone searching for information is influenced not only by the value and importance of the information itself but also by well-being maintenance goals related to possible detrimental effects that negative knowledge may have on unrelated future plans.

  17. Fermionic models with superconducting circuits

    Energy Technology Data Exchange (ETDEWEB)

    Las Heras, Urtzi; Garcia-Alvarez, Laura; Mezzacapo, Antonio; Lamata, Lucas [University of the Basque Country UPV/EHU, Department of Physical Chemistry, Bilbao (Spain); Solano, Enrique [University of the Basque Country UPV/EHU, Department of Physical Chemistry, Bilbao (Spain); IKERBASQUE, Basque Foundation for Science, Bilbao (Spain)

    2015-12-01

    We propose a method for the efficient quantum simulation of fermionic systems with superconducting circuits. It consists in the suitable use of Jordan-Wigner mapping, Trotter decomposition, and multiqubit gates, be with the use of a quantum bus or direct capacitive couplings. We apply our method to the paradigmatic cases of 1D and 2D Fermi-Hubbard models, involving couplings with nearest and next-nearest neighbours. Furthermore, we propose an optimal architecture for this model and discuss the benchmarking of the simulations in realistic circuit quantum electrodynamics setups. (orig.)

  18. Circuit modeling for electromagnetic compatibility

    CERN Document Server

    Darney, Ian B

    2013-01-01

    Very simply, electromagnetic interference (EMI) costs money, reduces profits, and generally wreaks havoc for circuit designers in all industries. This book shows how the analytic tools of circuit theory can be used to simulate the coupling of interference into, and out of, any signal link in the system being reviewed. The technique is simple, systematic and accurate. It enables the design of any equipment to be tailored to meet EMC requirements. Every electronic system consists of a number of functional modules interconnected by signal links and power supply lines. Electromagnetic interference

  19. Relative ultrasound energy measurement circuit

    OpenAIRE

    Gustafsson, E.Martin I.; Johansson, Jonny; Delsing, Jerker

    2005-01-01

    A relative ultrasound energy estimation circuit has been designed in a standard 0.35-μm CMOS process, to be a part of a thumb size internet connected wireless ultrasound measurement system. This circuit measures the relative energy between received ultrasound pulses, and presents an output signal that is linear to the received energy. Post-layout simulations indicate 7 bit linearity for 500 mV input signals, 5 μsec startup and stop times, 2.6 mW power consumption during active state. The acti...

  20. Simplified design of filter circuits

    CERN Document Server

    Lenk, John

    1999-01-01

    Simplified Design of Filter Circuits, the eighth book in this popular series, is a step-by-step guide to designing filters using off-the-shelf ICs. The book starts with the basic operating principles of filters and common applications, then moves on to describe how to design circuits by using and modifying chips available on the market today. Lenk's emphasis is on practical, simplified approaches to solving design problems.Contains practical designs using off-the-shelf ICsStraightforward, no-nonsense approachHighly illustrated with manufacturer's data sheets

  1. Programming languages for circuit design.

    Science.gov (United States)

    Pedersen, Michael; Yordanov, Boyan

    2015-01-01

    This chapter provides an overview of a programming language for Genetic Engineering of Cells (GEC). A GEC program specifies a genetic circuit at a high level of abstraction through constraints on otherwise unspecified DNA parts. The GEC compiler then selects parts which satisfy the constraints from a given parts database. GEC further provides more conventional programming language constructs for abstraction, e.g., through modularity. The GEC language and compiler is available through a Web tool which also provides functionality, e.g., for simulation of designed circuits.

  2. Endogenous money, circuits and financialization

    OpenAIRE

    Malcolm Sawyer

    2013-01-01

    This paper locates the endogenous money approach in a circuitist framework. It argues for the significance of the credit creation process for the evolution of the economy and the absence of any notion of ‘neutrality of money’. Clearing banks are distinguished from other financial institutions as the providers of initial finance in a circuit whereas other financial institutions operate in a final finance circuit. Financialization is here viewed in terms of the growth of financial assets an...

  3. Vehicle barrier with access delay

    Science.gov (United States)

    Swahlan, David J; Wilke, Jason

    2013-09-03

    An access delay vehicle barrier for stopping unauthorized entry into secure areas by a vehicle ramming attack includes access delay features for preventing and/or delaying an adversary from defeating or compromising the barrier. A horizontally deployed barrier member can include an exterior steel casing, an interior steel reinforcing member and access delay members disposed within the casing and between the casing and the interior reinforcing member. Access delay members can include wooden structural lumber, concrete and/or polymeric members that in combination with the exterior casing and interior reinforcing member act cooperatively to impair an adversarial attach by thermal, mechanical and/or explosive tools.

  4. Photonic integrated circuits unveil crisis-induced intermittency.

    Science.gov (United States)

    Karsaklian Dal Bosco, Andreas; Akizawa, Yasuhiro; Kanno, Kazutaka; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki

    2016-09-19

    We experimentally investigate an intermittent route to chaos in a photonic integrated circuit consisting of a semiconductor laser with time-delayed optical feedback from a short external cavity. The transition from a period-doubling dynamics to a fully-developed chaos reveals a stage intermittently exhibiting these two dynamics. We unveil the bifurcation mechanism underlying this route to chaos by using the Lang-Kobayashi model and demonstrate that the process is based on a phenomenon of attractor expansion initiated by a particular distribution of the local Lyapunov exponents. We emphasize on the crucial importance of the distribution of the steady-state solutions introduced by the time-delayed feedback on the existence of this intermittent dynamics.

  5. Implementation of Chua's circuit using simulated inductance

    Science.gov (United States)

    Gopakumar, K.; Premlet, B.; Gopchandran, K. G.

    2011-05-01

    In this study we describe how to build an inductorless version of the classic Chua's circuit. A suitable inductor for Chua's circuit is often hard to procure. The required inductor for the circuit is designed using simple circuit elements such as resistors, capacitors and operational amplifiers. The complete circuit can be implemented by using off-the-shelf components, and it can readily be integrated on a single chip. This design of Chua's circuit allows the original dynamics to be slowed down to just a few hertz, enabling implementation of sophisticated control schemes without severe time restrictions. Another novel feature of the circuit is that losses associated with capacitors due to leakages can easily be compensated by providing negative resistance using the same setup. The chaotic behaviour of the circuit is verified by PSpice and Multisim simulation and also by experimental study on a circuit breadboard. The results give excellent agreement with each other and with the results of previous investigators.

  6. Delayed rule following.

    Science.gov (United States)

    Schmitt, D R

    2001-01-01

    Although the elements of a fully stated rule (discriminative stimulus [S(D)], some behavior, and a consequence) can occur nearly contemporaneously with the statement of the rule, there is often a delay between the rule statement and the S(D). The effects of this delay on rule following have not been studied in behavior analysis, but they have been investigated in rule-like settings in the areas of prospective memory (remembering to do something in the future) and goal pursuit. Discriminative events for some behavior can be event based (a specific setting stimulus) or time based. The latter are more demanding with respect to intention following and show age-related deficits. Studies suggest that the specificity with which the components of a rule (termed intention) are stated has a substantial effect on intention following, with more detailed specifications increasing following. Reminders of an intention, too, are most effective when they refer specifically to both the behavior and its occasion. Covert review and written notes are two effective strategies for remembering everyday intentions, but people who use notes appear not to be able to switch quickly to covert review. By focusing on aspects of the setting and rule structure, research on prospective memory and goal pursuit expands the agenda for a more complete explanation of rule effects.

  7. Pseudotumoral delayed cerebral radionecrosis

    International Nuclear Information System (INIS)

    Ciaudo-Lacroix, C.; Lapresle, J.

    1985-01-01

    A 60 year-old woman with a scalp epithelioma underwent radiotherapy, the dose being 57 Gray. A first epileptic seizure occurred twenty months later. Neurological examination revealed signs of left hemisphere involvement. γEG, angiography, CT scans, demonstrated a pseudotumoral avascular process. On account of the localisation, the patient being right-handed, no surgical procedure was performed. In spite of corticotherapy and anticonvulsive treatment, seizures recurred and neurological signs slowly progressed. The patient died, 22 months after the first seizure, of an associated disseminated carcinoma with cachexia. Neuropathological examination showed a massive lesion presenting all the features of delayed radionecrosis in the left hemisphere: situated mainly in the white matter; numerous vascular abnormalities; wide-spread demyelination; disappearance of oligoglial cells. The Authors recall the clinical and anatomical aspects of this condition for which the only successful treatment is surgical removal when location and size of the lesion permit. Finally, the mechanisms which have been proposed to explain this delayed cerebral radionecrosis are discussed [fr

  8. Pseudotumoral delayed cerebral radionecrosis

    Energy Technology Data Exchange (ETDEWEB)

    Ciaudo-Lacroix, C; Lapresle, J [Centre Hospitalier de Bicetre, 94 - Le Kremlin-Bicetre (France)

    1985-01-01

    A 60 year-old woman with a scalp epithelioma underwent radiotherapy, the dose being 57 Gray. A first epileptic seizure occurred twenty months later. Neurological examination revealed signs of left hemisphere involvement. ..gamma..EG, angiography, CT scans, demonstrated a pseudotumoral avascular process. On account of the localisation, the patient being right-handed, no surgical procedure was performed. In spite of corticotherapy and anticonvulsive treatment, seizures recurred and neurological signs slowly progressed. The patient died, 22 months after the first seizure, of an associated disseminated carcinoma with cachexia. Neuropathological examination showed a massive lesion presenting all the features of delayed radionecrosis in the left hemisphere: situated mainly in the white matter; numerous vascular abnormalities; wide-spread demyelination; disappearance of oligoglial cells. The Authors recall the clinical and anatomical aspects of this condition for which the only successful treatment is surgical removal when location and size of the lesion permit. Finally, the mechanisms which have been proposed to explain this delayed cerebral radionecrosis are discussed.

  9. Introduction to Focus Issue: Time-delay dynamics

    Science.gov (United States)

    Erneux, Thomas; Javaloyes, Julien; Wolfrum, Matthias; Yanchuk, Serhiy

    2017-11-01

    The field of dynamical systems with time delay is an active research area that connects practically all scientific disciplines including mathematics, physics, engineering, biology, neuroscience, physiology, economics, and many others. This Focus Issue brings together contributions from both experimental and theoretical groups and emphasizes a large variety of applications. In particular, lasers and optoelectronic oscillators subject to time-delayed feedbacks have been explored by several authors for their specific dynamical output, but also because they are ideal test-beds for experimental studies of delay induced phenomena. Topics include the control of cavity solitons, as light spots in spatially extended systems, new devices for chaos communication or random number generation, higher order locking phenomena between delay and laser oscillation period, and systematic bifurcation studies of mode-locked laser systems. Moreover, two original theoretical approaches are explored for the so-called Low Frequency Fluctuations, a particular chaotical regime in laser output which has attracted a lot of interest for more than 30 years. Current hot problems such as the synchronization properties of networks of delay-coupled units, novel stabilization techniques, and the large delay limit of a delay differential equation are also addressed in this special issue. In addition, analytical and numerical tools for bifurcation problems with or without noise and two reviews on concrete questions are proposed. The first review deals with the rich dynamics of simple delay climate models for El Nino Southern Oscillations, and the second review concentrates on neuromorphic photonic circuits where optical elements are used to emulate spiking neurons. Finally, two interesting biological problems are considered in this Focus Issue, namely, multi-strain epidemic models and the interaction of glucose and insulin for more effective treatment.

  10. Advanced circuit simulation using Multisim workbench

    CERN Document Server

    Báez-López, David; Cervantes-Villagómez, Ofelia Delfina

    2012-01-01

    Multisim is now the de facto standard for circuit simulation. It is a SPICE-based circuit simulator which combines analog, discrete-time, and mixed-mode circuits. In addition, it is the only simulator which incorporates microcontroller simulation in the same environment. It also includes a tool for printed circuit board design.Advanced Circuit Simulation Using Multisim Workbench is a companion book to Circuit Analysis Using Multisim, published by Morgan & Claypool in 2011. This new book covers advanced analyses and the creation of models and subcircuits. It also includes coverage of transmissi

  11. Digital circuit boards mach 1 GHz

    CERN Document Server

    Morrison, Ralph

    2012-01-01

    A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove

  12. Clocking Scheme for Switched-Capacitor Circuits

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    1998-01-01

    A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed.......A novel clocking scheme for switched-capacitor (SC) circuits is presented. It can enhance the understanding of SC circuits and the errors caused by MOSFET (MOS) switches. Charge errors, and techniques to make SC circuits less sensitive to them are discussed....

  13. Unbalanced Neuronal Circuits in Addiction

    OpenAIRE

    Volkow, Nora D.; Wang, Gen-Jack; Tomasi, Dardo; Baler, Ruben D.

    2013-01-01

    Through sequential waves of drug-induced neurochemical stimulation, addiction co-opts the brain's neuronal circuits that mediate reward, motivation, , to behavioral inflexibility and a severe disruption of self-control and compulsive drug intake. Brain imaging technologies have allowed neuroscientists to map out the neural landscape of addiction in the human brain and to understand how drugs modify it.

  14. A Low Noise Electronic Circuit

    NARCIS (Netherlands)

    Annema, Anne J.; Leenaerts, Dominicus M.W.; de Vreede, Petrus W.H.

    2002-01-01

    An electronic circuit, which can be used as a Low Noise Amplifier (LNA), comprises two complementary Field Effect Transistors (M1, M2; M5, M6), each having a gate, a source and a drain. The gates are connected together as a common input terminal, and the drains are connected together as a

  15. Circuit design for RF transceivers

    CERN Document Server

    Leenaerts, Domine; Vaucher, Cicero S

    2007-01-01

    Second edition of this successful 2001 RF Circuit Design book, has been updated, latest technology reviews have been added as well as several actual case studies. Due to the authors being active in industry as well as academia, this should prove to be an essential guide on RF Transceiver Design for students and engineers.

  16. Integrated Circuit Stellar Magnitude Simulator

    Science.gov (United States)

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  17. Simulated annealing and circuit layout

    NARCIS (Netherlands)

    Aarts, E.H.L.; Laarhoven, van P.J.M.

    1991-01-01

    We discuss the problem of approximately sotvlng circuit layout problems by simulated annealing. For this we first summarize the theoretical concepts of the simulated annealing algorithm using Ihe theory of homogeneous and inhomogeneous Markov chains. Next we briefly review general aspects of the

  18. Delay Insensitive Ternary CMOS Logic for Secure Hardware

    Directory of Open Access Journals (Sweden)

    Ravi S. P. Nair

    2015-09-01

    Full Text Available As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI. This paper develops the Delay-Insensitive Ternary Logic (DITL asynchronous design paradigm that combines design aspects of similar dual-rail asynchronous paradigms and Boolean logic to create a single wire per bit, three voltage signaling and logic scheme. DITL is compared with other delay insensitive paradigms, such as Pre-Charge Half-Buffers (PCHB and NULL Convention Logic (NCL on which it is based. An application of DITL is discussed in designing secure digital circuits resistant to side channel attacks based on measurement of timing, power, and EMI signatures. A Secure DITL Adder circuit is designed at the transistor level, and several variance parameters are measured to validate the efficiency of DITL in resisting side channel attacks. The DITL design methodology is then applied to design a secure 8051 ALU.

  19. Stability and delay sensitivity of neutral fractional-delay systems.

    Science.gov (United States)

    Xu, Qi; Shi, Min; Wang, Zaihua

    2016-08-01

    This paper generalizes the stability test method via integral estimation for integer-order neutral time-delay systems to neutral fractional-delay systems. The key step in stability test is the calculation of the number of unstable characteristic roots that is described by a definite integral over an interval from zero to a sufficient large upper limit. Algorithms for correctly estimating the upper limits of the integral are given in two concise ways, parameter dependent or independent. A special feature of the proposed method is that it judges the stability of fractional-delay systems simply by using rough integral estimation. Meanwhile, the paper shows that for some neutral fractional-delay systems, the stability is extremely sensitive to the change of time delays. Examples are given for demonstrating the proposed method as well as the delay sensitivity.

  20. Effect of a Diagram on Primary Students' Understanding About Electric Circuits

    Science.gov (United States)

    Preston, Christine Margaret

    2017-09-01

    This article reports on the effect of using a diagram to develop primary students' conceptual understanding about electric circuits. Diagrammatic representations of electric circuits are used for teaching and assessment despite the absence of research on their pedagogical effectiveness with young learners. Individual interviews were used to closely analyse Years 3 and 5 (8-11-year-old) students' explanations about electric circuits. Data was collected from 20 students in the same school providing pre-, post- and delayed post-test dialogue. Students' thinking about electric circuits and changes in their explanations provide insights into the role of diagrams in understanding science concepts. Findings indicate that diagram interaction positively enhanced understanding, challenged non-scientific views and promoted scientific models of electric circuits. Differences in students' understanding about electric circuits were influenced by prior knowledge, meta-conceptual awareness and diagram conventions including a stylistic feature of the diagram used. A significant finding that students' conceptual models of electric circuits were energy rather than current based has implications for electricity instruction at the primary level.

  1. Delayed breast implant reconstruction

    DEFF Research Database (Denmark)

    Hvilsom, Gitte B.; Hölmich, Lisbet R.; Steding-Jessen, Marianne

    2012-01-01

    We evaluated the association between radiation therapy and severe capsular contracture or reoperation after 717 delayed breast implant reconstruction procedures (288 1- and 429 2-stage procedures) identified in the prospective database of the Danish Registry for Plastic Surgery of the Breast during...... of radiation therapy was associated with a non-significantly increased risk of reoperation after both 1-stage (HR = 1.4; 95% CI: 0.7-2.5) and 2-stage (HR = 1.6; 95% CI: 0.9-3.1) procedures. Reconstruction failure was highest (13.2%) in the 2-stage procedures with a history of radiation therapy. Breast...... reconstruction approaches other than implants should be seriously considered among women who have received radiation therapy....

  2. Delay tolerant networks

    CERN Document Server

    Gao, Longxiang; Luan, Tom H

    2015-01-01

    This brief presents emerging and promising communication methods for network reliability via delay tolerant networks (DTNs). Different from traditional networks, DTNs possess unique features, such as long latency and unstable network topology. As a result, DTNs can be widely applied to critical applications, such as space communications, disaster rescue, and battlefield communications. The brief provides a complete investigation of DTNs and their current applications, from an overview to the latest development in the area. The core issue of data forward in DTNs is tackled, including the importance of social characteristics, which is an essential feature if the mobile devices are used for human communication. Security and privacy issues in DTNs are discussed, and future work is also discussed.

  3. Global exponential stability of fuzzy cellular neural networks with delays and reaction-diffusion terms

    International Nuclear Information System (INIS)

    Wang Jian; Lu Junguo

    2008-01-01

    In this paper, we study the global exponential stability of fuzzy cellular neural networks with delays and reaction-diffusion terms. By constructing a suitable Lyapunov functional and utilizing some inequality techniques, we obtain a sufficient condition for the uniqueness and global exponential stability of the equilibrium solution for a class of fuzzy cellular neural networks with delays and reaction-diffusion terms. The result imposes constraint conditions on the network parameters independently of the delay parameter. The result is also easy to check and plays an important role in the design and application of globally exponentially stable fuzzy neural circuits

  4. Analytical and experimental study of two delay-coupled excitable units.

    Science.gov (United States)

    Weicker, Lionel; Erneux, Thomas; Keuninckx, Lars; Danckaert, Jan

    2014-01-01

    We investigate the onset of time-periodic oscillations for a system of two identical delay-coupled excitable (nonoscillatory) units. We first analyze these solutions by using asymptotic methods. The oscillations are described as relaxation oscillations exhibiting successive slow and fast changes. The analysis highlights the determinant role of the delay during the fast transition layers. We then study experimentally a system of two coupled electronic circuits that is modeled mathematically by the same delay differential equations. We obtain quantitative agreements between analytical and experimental bifurcation diagrams.

  5. Organizing of delay, input gate and memory of proportional chamber channel basing on D-trigger

    International Nuclear Information System (INIS)

    Vladimirov, S.V.; Kuzichev, V.F.; Rabin, N.V.

    1980-01-01

    Economical organization of delay, input gate and proportional chamber (PC) channel memory on the 155 TM2 D trigger basis is described. The channel consists of an amplifier; delay element permitting to synchronize PC signal and recording strobe-signal; input gate, where coincidence of the above signals occurs; memory element, where the data from a wire are recorded and stored; read gate through which the data are transmitted for further processing. Presented is one of the versions of circuit solution for delay element, input gate and momory element. Flowsheet peculiarity is the simplicity of fabrication and tuning as well as low cost of the device

  6. Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

    Directory of Open Access Journals (Sweden)

    Yoni Aizik

    2011-01-01

    Full Text Available A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.

  7. The voltage—current relationship and equivalent circuit implementation of parallel flux-controlled memristive circuits

    International Nuclear Information System (INIS)

    Bao Bo-Cheng; Feng Fei; Dong Wei; Pan Sai-Hu

    2013-01-01

    A flux-controlled memristor characterized by smooth cubic nonlinearity is taken as an example, upon which the voltage—current relationships (VCRs) between two parallel memristive circuits — a parallel memristor and capacitor circuit (the parallel MC circuit), and a parallel memristor and inductor circuit (the parallel ML circuit) — are investigated. The results indicate that the VCR between these two parallel memristive circuits is closely related to the circuit parameters, and the frequency and amplitude of the sinusoidal voltage stimulus. An equivalent circuit model of the memristor is built, upon which the circuit simulations and experimental measurements of both the parallel MC circuit and the parallel ML circuit are performed, and the results verify the theoretical analysis results

  8. Fabric circuits and method of manufacturing fabric circuits

    Science.gov (United States)

    Chu, Andrew W. (Inventor); Dobbins, Justin A. (Inventor); Scully, Robert C. (Inventor); Trevino, Robert C. (Inventor); Lin, Greg Y. (Inventor); Fink, Patrick W. (Inventor)

    2011-01-01

    A flexible, fabric-based circuit comprises a non-conductive flexible layer of fabric and a conductive flexible layer of fabric adjacent thereto. A non-conductive thread, an adhesive, and/or other means may be used for attaching the conductive layer to the non-conductive layer. In some embodiments, the layers are attached by a computer-driven embroidery machine at pre-determined portions or locations in accordance with a pre-determined attachment layout before automated cutting. In some other embodiments, an automated milling machine or a computer-driven laser using a pre-designed circuit trace as a template cuts the conductive layer so as to separate an undesired portion of the conductive layer from a desired portion of the conductive layer. Additional layers of conductive fabric may be attached in some embodiments to form a multi-layer construct.

  9. Investigation of Equivalent Circuit for PEMFC Assessment

    International Nuclear Information System (INIS)

    Myong, Kwang Jae

    2011-01-01

    Chemical reactions occurring in a PEMFC are dominated by the physical conditions and interface properties, and the reactions are expressed in terms of impedance. The performance of a PEMFC can be simply diagnosed by examining the impedance because impedance characteristics can be expressed by an equivalent electrical circuit. In this study, the characteristics of a PEMFC are assessed using the AC impedance and various equivalent circuits such as a simple equivalent circuit, equivalent circuit with a CPE, equivalent circuit with two RCs, and equivalent circuit with two CPEs. It was found in this study that the characteristics of a PEMFC could be assessed using impedance and an equivalent circuit, and the accuracy was highest for an equivalent circuit with two CPEs

  10. Sustainability issues in circuit board recycling

    DEFF Research Database (Denmark)

    Legarth, Jens Brøbech; Alting, Leo; Baldo, Gian Luca

    1995-01-01

    The resource recovery and environmental impact issues of printed circuit board recycling by secondary copper smelters are discussed. Guidelines concerning material selection for circuit board manufacture and concerning the recycling processes are given to enhance recovery efficiency and to lower...

  11. Developing a Domain Model for Relay Circuits

    DEFF Research Database (Denmark)

    Haxthausen, Anne Elisabeth

    2009-01-01

    In this paper we stepwise develop a domain model for relay circuits as used in railway control systems. First we provide an abstract, property-oriented model of networks consisting of components that can be glued together with connectors. This model is strongly inspired by a network model...... for railways madeby Bjørner et.al., however our model is more general: the components can be of any kind and can later be refined to e.g. railway components or circuit components. Then we show how the abstract network model can be refined into an explicit model for relay circuits. The circuit model describes...... the statics as well as the dynamics of relay circuits, i.e. how a relay circuit can be composed legally from electrical components as well as how the components may change state over time. Finally the circuit model is transformed into an executable model, and we show how a concrete circuit can be defined...

  12. Telecommunications Circuit Allocation Programs - Kansas City Area

    National Research Council Canada - National Science Library

    Thomas, William

    1994-01-01

    The overall objective of the audit was to determine whether DoD circuit allocation programs identified and used the most effective configurations for leased long-haul, special-purpose telecommunications circuits...

  13. Circuit QED lattices: Towards quantum simulation with superconducting circuits

    Energy Technology Data Exchange (ETDEWEB)

    Schmidt, Sebastian [Institute for Theoretical Physics, ETH Zurich, 8093, Zurich (Switzerland); Koch, Jens [Department of Physics and Astronomy, Northwestern University, Evanston, IL, 60208 (United States)

    2013-06-15

    The Jaynes-Cummings model describes the coupling between photons and a single two-level atom in a simplified representation of light-matter interactions. In circuit QED, this model is implemented by combining microwave resonators and superconducting qubits on a microchip with unprecedented experimental control. Arranging qubits and resonators in the form of a lattice realizes a new kind of Hubbard model, the Jaynes-Cummings-Hubbard model, in which the elementary excitations are polariton quasi-particles. Due to the genuine openness of photonic systems, circuit QED lattices offer the possibility to study the intricate interplay of collective behavior, strong correlations and non-equilibrium physics. Thus, turning circuit QED into an architecture for quantum simulation, i.e., using a well-controlled system to mimic the intricate quantum behavior of another system too daunting for a theorist to tackle head-on, is an exciting idea which has served as theorists' playground for a while and is now also starting to catch on in experiments. This review gives a summary of the most recent theoretical proposals and experimental efforts. (copyright 2013 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  14. QCA Gray Code Converter Circuits Using LTEx Methodology

    Science.gov (United States)

    Mukherjee, Chiradeep; Panda, Saradindu; Mukhopadhyay, Asish Kumar; Maji, Bansibadan

    2018-04-01

    The Quantum-dot Cellular Automata (QCA) is the prominent paradigm of nanotechnology considered to continue the computation at deep sub-micron regime. The QCA realizations of several multilevel circuit of arithmetic logic unit have been introduced in the recent years. However, as high fan-in Binary to Gray (B2G) and Gray to Binary (G2B) Converters exist in the processor based architecture, no attention has been paid towards the QCA instantiation of the Gray Code Converters which are anticipated to be used in 8-bit, 16-bit, 32-bit or even more bit addressable machines of Gray Code Addressing schemes. In this work the two-input Layered T module is presented to exploit the operation of an Exclusive-OR Gate (namely LTEx module) as an elemental block. The "defect-tolerant analysis" of the two-input LTEx module has been analyzed to establish the scalability and reproducibility of the LTEx module in the complex circuits. The novel formulations exploiting the operability of the LTEx module have been proposed to instantiate area-delay efficient B2G and G2B Converters which can be exclusively used in Gray Code Addressing schemes. Moreover this work formulates the QCA design metrics such as O-Cost, Effective area, Delay and Cost α for the n-bit converter layouts.

  15. What's new about generator circuit breakers

    International Nuclear Information System (INIS)

    Kolarik, P.L.

    1979-01-01

    The need for updating ANSI C37 Standards for AC high-voltage circuit breakers has become necessary because of the increased interest in power circuit breakers for generator application. These circuit breakers, which have continuous current ratings and rated short-circuit currents that are much higher than those presently covered by existing C37 Standards, take on added importance because they are being installed in critical AC power supplies at nuclear power stations

  16. Trip electrical circuit of the gyrotion

    International Nuclear Information System (INIS)

    Rossi, J.O.

    1987-09-01

    The electron cyclotron resonance heating system of INPE/LAP is shown and the trip electrical circuit of the gyrotron is described, together with its fundamental aspects. The trip electrical circuit consists basically of a series regulator circuit which regulates the output voltage level and controls the pulse width time. Besides that, a protection circuit for both tubes, regulator and gyrotron, against faults in the system. (author) [pt

  17. A Fault Tolerant Integrated Circuit Memory

    OpenAIRE

    Barton, Anthony Francis

    1980-01-01

    Most commercially produced integrated circuits are incapable of tolerating manufacturing defects. The area and function of the circuits is thus limited by the probability of faults occurring within the circuit. This thesis examines techniques for using redundancy in memory circuits to provide fault tolerance and to increase storage capacity. A hierarchical memory architecture using multiple Hamming codes is introduced and analysed to determine its resistance to manufa...

  18. Location Estimation using Delayed Measurements

    DEFF Research Database (Denmark)

    Bak, Martin; Larsen, Thomas Dall; Nørgård, Peter Magnus

    1998-01-01

    When combining data from various sensors it is vital to acknowledge possible measurement delays. Furthermore, the sensor fusion algorithm, often a Kalman filter, should be modified in order to handle the delay. The paper examines different possibilities for handling delays and applies a new techn...... technique to a sensor fusion system for estimating the location of an autonomous guided vehicle. The system fuses encoder and vision measurements in an extended Kalman filter. Results from experiments in a real environment are reported...

  19. Systematic of delayed neutron parameters

    International Nuclear Information System (INIS)

    Isaev, S.G.; Piksaikin, V.M.

    2000-01-01

    The experimental studies of the energy dependence of the delayed neutron (DN) parameters for various fission systems has shown that the behaviour of a some combination of delayed neutron parameters has a similar features. On the basis of this findings the systematics of delayed neutron experimental data for thorium, uranium, plutonium and americium isotopes have been investigated with the purpose to find a correlation of DN parameters with characteristics of fissioning system as well as a correlation between the delayed neutron parameters themselves. It was presented the preliminary results which were obtained during study the physics interpretation of the results [ru

  20. Time Delay of CGM Sensors

    Science.gov (United States)

    Schmelzeisen-Redeker, Günther; Schoemaker, Michael; Kirchsteiger, Harald; Freckmann, Guido; Heinemann, Lutz; del Re, Luigi

    2015-01-01

    Background: Continuous glucose monitoring (CGM) is a powerful tool to support the optimization of glucose control of patients with diabetes. However, CGM systems measure glucose in interstitial fluid but not in blood. Rapid changes in one compartment are not accompanied by similar changes in the other, but follow with some delay. Such time delays hamper detection of, for example, hypoglycemic events. Our aim is to discuss the causes and extent of time delays and approaches to compensate for these. Methods: CGM data were obtained in a clinical study with 37 patients with a prototype glucose sensor. The study was divided into 5 phases over 2 years. In all, 8 patients participated in 2 phases separated by 8 months. A total number of 108 CGM data sets including raw signals were used for data analysis and were processed by statistical methods to obtain estimates of the time delay. Results: Overall mean (SD) time delay of the raw signals with respect to blood glucose was 9.5 (3.7) min, median was 9 min (interquartile range 4 min). Analysis of time delays observed in the same patients separated by 8 months suggests a patient dependent delay. No significant correlation was observed between delay and anamnestic or anthropometric data. The use of a prediction algorithm reduced the delay by 4 minutes on average. Conclusions: Prediction algorithms should be used to provide real-time CGM readings more consistent with simultaneous measurements by SMBG. Patient specificity may play an important role in improving prediction quality. PMID:26243773

  1. Development of a pulse shape discrimination circuit

    International Nuclear Information System (INIS)

    Ye Bangjiao; Fan Wei; Fan Yangmei; Yu Xiaoqi; Mei Wen; Wang Zhongmin; Han Rongdian; Xiao Zhenxi

    1994-01-01

    A pulse shape discrimination circuit was designed and used in an experiment measuring double-differential cross sections of (n, charged particle) reaction; to identify p, α and γ. The performance of the circuit was tested. With this circuit, excellent identification of p, α and γ was obtained. ((orig.))

  2. Circuit card failures and industry mitigation strategy

    Energy Technology Data Exchange (ETDEWEB)

    Mondal, U. [Candu Owners Group, Toronto, Ontario (Canada)

    2012-07-01

    In recent years the nuclear industry has experienced an increase in circuit card failures due to ageing of components, inadequate Preventive Maintenance (PM), lack of effective circuit card health monitoring, etc. Circuit card failures have caused loss of critical equipment, e.g., electro hydraulic governors, Safety Systems, resulting in loss of function and in some cases loss of generation. INPO completed a root cause analysis of 40 Reactor Trips/Scrams in US reactors and has recommended several actions to mitigate Circuit Card failures. Obsolescence of discrete components has posed many challenges in conducting effective preventative maintenance on circuit cards. In many cases, repairs have resulted in installation of components that compromise performance of the circuit cards. Improper termination and worn edge connectors have caused intermittent contacts contributing to circuit card failures. Traditionally, little attention is paid to relay functions and preventative maintenance of relay. Relays contribute significantly to circuit card failures and have dominated loss of generation across the power industry. The INPO study recommended a number of actions to mitigate circuit card failures, such as; identification of critical components and single point vulnerabilities; strategic preventative maintenance; protection of circuit boards against electrostatic discharge; limiting power cycles; performing an effective burn-in prior to commissioning of the circuit cards; monitoring performance of DC power supplies; limiting cabinet temperatures; managing of component aging/degradation mechanism, etc. A subcommittee has been set up under INPO sponsorship to understand the causes of circuit card failure and to develop an effective mitigation strategy. (author)

  3. Improvements in or relating to transistor circuits

    International Nuclear Information System (INIS)

    Richards, R.F.; Williamson, P.W.

    1978-01-01

    This invention relates to transistor circuits and in particular to integrated transistor circuits formed on a substrate of semi-conductor material such as silicon. The invention is concerned with providing integrated circuits in which malfunctions caused by the effects of ionising, e.g. nuclear, radiations are reduced. (author)

  4. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  5. Piezo pump and pressurized circuit provided therewith

    NARCIS (Netherlands)

    Van Es, Johannes; Wits, Wessel Willems

    2015-01-01

    A piezo pump for use in a pressurized circuit includes a pump chamber with an inlet provided with a one way inlet valve, for connection to a feeding line of the pressurized circuit and an outlet provided with a one way outlet valve, for connection to a discharge line of the pressurized circuit and a

  6. 49 CFR 236.721 - Circuit, control.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Circuit, control. 236.721 Section 236.721..., MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Definitions § 236.721 Circuit, control. An electrical circuit between a source of electric energy and a device which it operates. ...

  7. Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

    Science.gov (United States)

    Shahrjerdi, Davood; Bedell, Stephen W

    2013-01-09

    In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

  8. Generation of optical vortices in an integrated optical circuit

    Science.gov (United States)

    Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

    2017-09-01

    In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = -1.

  9. Advanced Microwave Circuits and Systems

    DEFF Research Database (Denmark)

    This book is based on recent research work conducted by the authors dealing with the design and development of active and passive microwave components, integrated circuits and systems. It is divided into seven parts. In the first part comprising the first two chapters, alternative concepts...... amplifier architectures. In addition, distortion analysis and power combining techniques are considered. Another key element in most microwave systems is a signal generator. It forms the heart of all kinds of communication and radar systems. The fourth part of this book is dedicated to signal generators...... push currently available technologies to the limits. Some considerations to meet the growing requirements are provided in the fifth part of this book. The following part deals with circuits based on LTCC and MEMS technologies. The book concludes with chapters considering application of microwaves...

  10. Smart Circuit Breaker Communication Infrastructure

    Directory of Open Access Journals (Sweden)

    Octavian Mihai MACHIDON

    2017-11-01

    Full Text Available The expansion of the Internet of Things has fostered the development of smart technologies in fields such as power transmission and distribution systems (as is the Smart Grid and also in regard to home automation (the Smart Home concept. This paper addresses the network communication infrastructure for a Smart Circuit Breaker system, a novel application at the edge of the two afore-mentioned systems (Smart Grid and Smart Home. Such a communication interface has high requirements from functionality, performance and security point of views, given the large amount of distributed connected elements and the real-time information transmission and system management. The paper describes the design and implementation of the data server, Web interface and the embedded networking capabilities of the smart circuit breakers, underlining the protocols and communication technologies used.

  11. Foundations for microstrip circuit design

    CERN Document Server

    Edwards, Terry

    2016-01-01

    Building on the success of the previous three editions, Foundations for Microstrip Circuit Design offers extensive new, updated and revised material based upon the latest research. Strongly design-oriented, this fourth edition provides the reader with a fundamental understanding of this fast expanding field making it a definitive source for professional engineers and researchers and an indispensable reference for senior students in electronic engineering. Topics new to this edition: microwave substrates, multilayer transmission line structures, modern EM tools and techniques, microstrip and planar transmision line design, transmission line theory, substrates for planar transmission lines, Vias, wirebonds, 3D integrated interposer structures, computer-aided design, microstrip and power-dependent effects, circuit models, microwave network analysis, microstrip passive elements, and slotline design fundamentals.

  12. Unbalanced neuronal circuits in addiction.

    Science.gov (United States)

    Volkow, Nora D; Wang, Gen-Jack; Tomasi, Dardo; Baler, Ruben D

    2013-08-01

    Through sequential waves of drug-induced neurochemical stimulation, addiction co-opts the brain's neuronal circuits that mediate reward, motivation to behavioral inflexibility and a severe disruption of self-control and compulsive drug intake. Brain imaging technologies have allowed neuroscientists to map out the neural landscape of addiction in the human brain and to understand how drugs modify it. Published by Elsevier Ltd.

  13. Monolithic readout circuits for RHIC

    International Nuclear Information System (INIS)

    O'Connor, P.; Harder, J.; Sippach, W.

    1991-10-01

    Several CMOS ASICs have been developed for a proposed RHIC experiment. This paper discusses why ASIC implementation was chosen for certain functions, circuit specifications and the design techniques used to meet them, and results of simulations and early prototypes. By working closely together from an early stage in the planning process, in-house ASIC designers and detector and data acquisition experimenters can achieve optimal use of this important technology

  14. Circuit complexity of regular languages

    Czech Academy of Sciences Publication Activity Database

    Koucký, Michal

    2009-01-01

    Roč. 45, č. 4 (2009), s. 865-879 ISSN 1432-4350 R&D Projects: GA ČR GP201/07/P276; GA MŠk(CZ) 1M0545 Institutional research plan: CEZ:AV0Z10190503 Keywords : regular languages * circuit complexity * upper and lower bounds Subject RIV: BA - General Mathematics Impact factor: 0.726, year: 2009

  15. Realistic Realizations Of Threshold Circuits

    Science.gov (United States)

    Razavi, Hassan M.

    1987-08-01

    Threshold logic, in which each input is weighted, has many theoretical advantages over the standard gate realization, such as reducing the number of gates, interconnections, and power dissipation. However, because of the difficult synthesis procedure and complicated circuit implementation, their use in the design of digital systems is almost nonexistant. In this study, three methods of NMOS realizations are discussed, and their advantages and shortcomings are explored. Also, the possibility of using the methods to realize multi-valued logic is examined.

  16. Microcontroller based Integrated Circuit Tester

    OpenAIRE

    Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi

    2015-01-01

    The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...

  17. Monolithic readout circuits for RHIC

    Energy Technology Data Exchange (ETDEWEB)

    O`Connor, P.; Harder, J. [Brookhaven National Laboratory, Upton, NY (United States)

    1991-12-31

    Several CMOS ASICs have been developed for a proposed RHIC experiment. This paper discusses why ASIC implementation was chosen for certain functions, circuit specifications and the design techniques used to meet them, and results of simulations and early prototypes. By working closely together from an early stage in the planning process, in-house ASIC designers and detector and data acquisition experimenters can achieve optimal use of this important technology.

  18. Root finding with threshold circuits

    Czech Academy of Sciences Publication Activity Database

    Jeřábek, Emil

    2012-01-01

    Roč. 462, Nov 30 (2012), s. 59-69 ISSN 0304-3975 R&D Projects: GA AV ČR IAA100190902; GA MŠk(CZ) 1M0545 Institutional support: RVO:67985840 Keywords : root finding * threshold circuit * power series Subject RIV: BA - General Mathematics Impact factor: 0.489, year: 2012 http://www.sciencedirect.com/science/article/pii/S0304397512008006#

  19. Generalized synchronization-based multiparameter estimation in modulated time-delayed systems

    Science.gov (United States)

    Ghosh, Dibakar; Bhattacharyya, Bidyut K.

    2011-09-01

    We propose a nonlinear active observer based generalized synchronization scheme for multiparameter estimation in time-delayed systems with periodic time delay. A sufficient condition for parameter estimation is derived using Krasovskii-Lyapunov theory. The suggested tool proves to be globally and asymptotically stable by means of Krasovskii-Lyapunov method. With this effective method, parameter identification and generalized synchronization of modulated time-delayed systems with all the system parameters unknown, can be achieved simultaneously. We restrict our study for multiple parameter estimation in modulated time-delayed systems with single state variable only. Theoretical proof and numerical simulation demonstrate the effectiveness and feasibility of the proposed technique. The block diagram of electronic circuit for multiple time delay system shows that the method is easily applicable in practical communication problems.

  20. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  1. Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

    Science.gov (United States)

    Russinoff, David M.

    1995-01-01

    We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

  2. Damping Resonant Current in a Spark-Gap Trigger Circuit to Reduce Noise

    Science.gov (United States)

    2009-06-01

    DAMPING RESONANT CURRENT IN A SPARK- GAP TRIGGER CIRCUIT TO REDUCE NOISE E. L. Ruden Air Force Research Laboratory, Directed Energy Directorate, AFRL...REPORT TYPE N/A 3. DATES COVERED - 4. TITLE AND SUBTITLE Damping Resonant Current In A Spark- Gap Trigger Circuit To Reduce Noise 5a...thereby triggering 2 after delay 0, is 1. Each of the two rail- gaps (represented by 2) is trig- gered to close after the spark- gap (1) in the

  3. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  4. Design of analog integrated circuits and systems

    CERN Document Server

    Laker, Kenneth R

    1994-01-01

    This text is designed for senior or graduate level courses in analog integrated circuits or design of analog integrated circuits. This book combines consideration of CMOS and bipolar circuits into a unified treatment. Also included are CMOS-bipolar circuits made possible by BiCMOS technology. The text progresses from MOS and bipolar device modelling to simple one and two transistor building block circuits. The final two chapters present a unified coverage of sample-data and continuous-time signal processing systems.

  5. Delayed Auditory Feedback and Movement

    Science.gov (United States)

    Pfordresher, Peter Q.; Dalla Bella, Simone

    2011-01-01

    It is well known that timing of rhythm production is disrupted by delayed auditory feedback (DAF), and that disruption varies with delay length. We tested the hypothesis that disruption depends on the state of the movement trajectory at the onset of DAF. Participants tapped isochronous rhythms at a rate specified by a metronome while hearing DAF…

  6. #FakeNobelDelayReasons

    CERN Multimedia

    2013-01-01

    Tuesday’s hour-long delay of the Nobel Prize in Physics announcement was (and still is) quite the cause for speculation. But on the Twittersphere, it was simply the catalyst for some fantastic puns, so-bad-they're-good physics jokes and other shenanigans. Here are some of our favourite #FakeNobelDelayReasons.    

  7. Graphene radio frequency receiver integrated circuit.

    Science.gov (United States)

    Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

    2014-01-01

    Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

  8. Project delay analysis of HRSG

    Science.gov (United States)

    Silvianita; Novega, A. S.; Rosyid, D. M.; Suntoyo

    2017-08-01

    Completion of HRSG (Heat Recovery Steam Generator) fabrication project sometimes is not sufficient with the targeted time written on the contract. The delay on fabrication process can cause some disadvantages for fabricator, including forfeit payment, delay on HRSG construction process up until HRSG trials delay. In this paper, the author is using semi quantitative on HRSG pressure part fabrication delay with configuration plant 1 GT (Gas Turbine) + 1 HRSG + 1 STG (Steam Turbine Generator) using bow-tie analysis method. Bow-tie analysis method is a combination from FTA (Fault tree analysis) and ETA (Event tree analysis) to develop the risk matrix of HRSG. The result from FTA analysis is use as a threat for preventive measure. The result from ETA analysis is use as impact from fabrication delay.

  9. Delayed radiation neuropathy

    Energy Technology Data Exchange (ETDEWEB)

    Nagashima, T.; Miyamoto, K.; Beppu, H.; Hirose, K.; Yamada, K. (Tokyo Metropolitan Neurological Hospital (Japan))

    1981-07-01

    A case of cervical plexus neuropathy was reported in association with chronic radio-dermatitis, myxedema with thyroid adenoma and epiglottic tumor. A 38-year-old man has noticed muscle weakness and wasting of the right shoulder girdle since age 33. A detailed history taking revealed a previous irradiation to the neck because of the cervical lymphadenopathy at age 10 (X-ray 3,000 rads), keroid skin change at age 19, obesity and edema since 26, and hoarseness at 34. Laryngoscopic examination revealed a tumor on the right vocal cord, diagnosed as benign papilloma by histological study. In addition, there were chronic radio-dermatitis around the neck, primary hypothyroidism with a benign functioning adenoma on the right lobe of the thyroid, the right phrenic nerve palsy and the right recurrent nerve palsy. All these lesions were considered to be the late sequellae of radiation to the neck in childhood. Other neurological signs were weakness and amyotrophy of the right shoulder girdle with patchy sensory loss, and areflexia of the right arm. Gross power was fairly well preserved in the right hand. EMG showed neurogenic changes in the tested muscles, suggesting a peripheral nerve lesion. Nerve conduction velocities were normal. No abnormal findings were revealed by myelography and spinal CT. The neurological findings of the patient were compatible with the diagnosis of middle cervical plexus palsy apparently due to late radiation effect. In the literature eight cases of post-radiation neuropathy with a long latency have been reported. The present case with the longest latency after the radiation should be included in the series of the reported cases of ''delayed radiation neuropathy.'' (author).

  10. Delayed radiation neuropathy

    International Nuclear Information System (INIS)

    Nagashima, Toshiko; Miyamoto, Kazuto; Beppu, Hirokuni; Hirose, Kazuhiko; Yamada, Katsuhiro

    1981-01-01

    A case of cervical plexus neuropathy was reported in association with chronic radio-dermatitis, myxedema with thyroid adenoma and epiglottic tumor. A 38-year-old man has noticed muscle weakness and wasting of the right shoulder girdle since age 33. A detailed history taking revealed a previous irradiation to the neck because of the cervical lymphadenopathy at age 10 (X-ray 3,000 rads), keroid skin change at age 19, obesity and edema since 26, and hoarseness at 34. Laryngoscopic examination revealed a tumor on the right vocal cord, diagnosed as benign papilloma by histological study. In addition, there were chronic radio-dermatitis around the neck, primary hypothyroidism with a benign functioning adenoma on the right lobe of the thyroid, the right phrenic nerve palsy and the right recurrent nerve palsy. All these lesions were considered to be the late sequellae of radiation to the neck in childhood. Other neurological signs were weakness and amyotrophy of the right shoulder girdle with patchy sensory loss, and areflexia of the right arm. Gross power was fairly well preserved in the right hand. EMG showed neurogenic changes in the tested muscles, suggesting a peripheral nerve lesion. Nerve conduction velocities were normal. No abnormal findings were revealed by myelography and spinal CT. The neurological findings of the patient were compatible with the diagnosis of middle cervical plexus palsy apparently due to late radiation effect. In the literature eight cases of post-radiation neuropathy with a long latency have been reported. The present case with the longest latency after the radiation should be included in the series of the reported cases of ''delayed radiation neuropathy.'' (author)

  11. Mutations in KPTN Cause Macrocephaly, Neurodevelopmental Delay, and Seizures

    Science.gov (United States)

    Baple, Emma L.; Maroofian, Reza; Chioza, Barry A.; Izadi, Maryam; Cross, Harold E.; Al-Turki, Saeed; Barwick, Katy; Skrzypiec, Anna; Pawlak, Robert; Wagner, Karin; Coblentz, Roselyn; Zainy, Tala; Patton, Michael A.; Mansour, Sahar; Rich, Phillip; Qualmann, Britta; Hurles, Matt E.; Kessels, Michael M.; Crosby, Andrew H.

    2014-01-01

    The proper development of neuronal circuits during neuromorphogenesis and neuronal-network formation is critically dependent on a coordinated and intricate series of molecular and cellular cues and responses. Although the cortical actin cytoskeleton is known to play a key role in neuromorphogenesis, relatively little is known about the specific molecules important for this process. Using linkage analysis and whole-exome sequencing on samples from families from the Amish community of Ohio, we have demonstrated that mutations in KPTN, encoding kaptin, cause a syndrome typified by macrocephaly, neurodevelopmental delay, and seizures. Our immunofluorescence analyses in primary neuronal cell cultures showed that endogenous and GFP-tagged kaptin associates with dynamic actin cytoskeletal structures and that this association is lost upon introduction of the identified mutations. Taken together, our studies have identified kaptin alterations responsible for macrocephaly and neurodevelopmental delay and define kaptin as a molecule crucial for normal human neuromorphogenesis. PMID:24239382

  12. How to induce multiple delays in coupled chaotic oscillators?

    Energy Technology Data Exchange (ETDEWEB)

    Bhowmick, Sourav K. [CSIR-Indian Institute of Chemical Biology, Jadavpur, Kolkata 700032 (India); Department of Electronics, Asutosh College, Kolkata 700026 (India); Ghosh, Dibakar [Physics and Applied Mathematics Unit, Indian Statistical Institute, Kolkata 700108 (India); Roy, Prodyot K. [Department of Physics, Presidency University, Kolkata 700073 (India); Kurths, Jürgen [Potsdam Institute for Climate Impact Research, 14473 Potsdam (Germany); Institute for Physics, Humboldt University, 12489 Berlin (Germany); Dana, Syamal K. [CSIR-Indian Institute of Chemical Biology, Jadavpur, Kolkata 700032 (India)

    2013-12-15

    Lag synchronization is a basic phenomenon in mismatched coupled systems, delay coupled systems, and time-delayed systems. It is characterized by a lag configuration that identifies a unique time shift between all pairs of similar state variables of the coupled systems. In this report, an attempt is made how to induce multiple lag configurations in coupled systems when different pairs of state variables attain different time shift. A design of coupling is presented to realize this multiple lag synchronization. Numerical illustration is given using examples of the Rössler system and the slow-fast Hindmarsh-Rose neuron model. The multiple lag scenario is physically realized in an electronic circuit of two Sprott systems.

  13. Delay Estimator and Improved Proportionate Multi-Delay Adaptive Filtering Algorithm

    Directory of Open Access Journals (Sweden)

    E. Verteletskaya

    2012-04-01

    Full Text Available This paper pertains to speech and acoustic signal processing, and particularly to a determination of echo path delay and operation of echo cancellers. To cancel long echoes, the number of weights in a conventional adaptive filter must be large. The length of the adaptive filter will directly affect both the degree of accuracy and the convergence speed of the adaptation process. We present a new adaptive structure which is capable to deal with multiple dispersive echo paths. An adaptive filter according to the present invention includes means for storing an impulse response in a memory, the impulse response being indicative of the characteristics of a transmission line. It also includes a delay estimator for detecting ranges of samples within the impulse response having relatively large distribution of echo energy. These ranges of samples are being indicative of echoes on the transmission line. An adaptive filter has a plurality of weighted taps, each of the weighted taps having an associated tap weight value. A tap allocation/control circuit establishes the tap weight values in response to said detecting means so that only taps within the regions of relatively large distributions of echo energy are turned on. Thus, the convergence speed and the degree of estimation in the adaptation process can be improved.

  14. Optimal planning of series resistor to control time constant of test circuit for high-voltage AC circuit-breakers

    OpenAIRE

    Yoon-Ho Kim; Jung-Hyeon Ryu; Jin-Hwan Kim; Kern-Joong Kim

    2016-01-01

    The equivalent test circuit that can deliver both short-circuit current and recovery voltage is used to verify the performance of high-voltage circuit breakers. Most of the parameters in this circuit can be obtained by using a simple calculation or a simulation program. The ratings of the circuit breaker include rated short-circuit breaking current, rated short-circuit making current, rated operating sequence of the circuit breaker and rated short-time current. Among these ratings, the short-...

  15. Attosecond Delays in Molecular Photoionization.

    Science.gov (United States)

    Huppert, Martin; Jordan, Inga; Baykusheva, Denitsa; von Conta, Aaron; Wörner, Hans Jakob

    2016-08-26

    We report measurements of energy-dependent photoionization delays between the two outermost valence shells of N_{2}O and H_{2}O. The combination of single-shot signal referencing with the use of different metal foils to filter the attosecond pulse train enables us to extract delays from congested spectra. Remarkably large delays up to 160 as are observed in N_{2}O, whereas the delays in H_{2}O are all smaller than 50 as in the photon-energy range of 20-40 eV. These results are interpreted by developing a theory of molecular photoionization delays. The long delays measured in N_{2}O are shown to reflect the population of molecular shape resonances that trap the photoelectron for a duration of up to ∼110 as. The unstructured continua of H_{2}O result in much smaller delays at the same photon energies. Our experimental and theoretical methods make the study of molecular attosecond photoionization dynamics accessible.

  16. Circuit for Driving Piezoelectric Transducers

    Science.gov (United States)

    Randall, David P.; Chapsky, Jacob

    2009-01-01

    The figure schematically depicts an oscillator circuit for driving a piezoelectric transducer to excite vibrations in a mechanical structure. The circuit was designed and built to satisfy application-specific requirements to drive a selected one of 16 such transducers at a regulated amplitude and frequency chosen to optimize the amount of work performed by the transducer and to compensate for both (1) temporal variations of the resonance frequency and damping time of each transducer and (2) initially unknown differences among the resonance frequencies and damping times of different transducers. In other words, the circuit is designed to adjust itself to optimize the performance of whichever transducer is selected at any given time. The basic design concept may be adaptable to other applications that involve the use of piezoelectric transducers in ultrasonic cleaners and other apparatuses in which high-frequency mechanical drives are utilized. This circuit includes three resistor-capacitor networks that, together with the selected piezoelectric transducer, constitute a band-pass filter having a peak response at a frequency of about 2 kHz, which is approximately the resonance frequency of the piezoelectric transducers. Gain for generating oscillations is provided by a power hybrid operational amplifier (U1). A junction field-effect transistor (Q1) in combination with a resistor (R4) is used as a voltage-variable resistor to control the magnitude of the oscillation. The voltage-variable resistor is part of a feedback control loop: Part of the output of the oscillator is rectified and filtered for use as a slow negative feedback to the gate of Q1 to keep the output amplitude constant. The response of this control loop is much slower than 2 kHz and, therefore, does not introduce significant distortion of the oscillator output, which is a fairly clean sine wave. The positive AC feedback needed to sustain oscillations is derived from sampling the current through the

  17. Coherent defects in superconducting circuits

    International Nuclear Information System (INIS)

    Mueller, Clemens

    2011-01-01

    The interaction of superconducting circuits with additional quantum systems is a topic that has found extensive study in the recent past. In the limit where the added system are incoherent, this is the standard field of decoherence and the system dynamics can be described by a simple master equation. In the other limit however, when the additional parts are coherent, the resulting time-evolution can become more complicated. In this thesis we have investigated the interaction of superconducting circuits with coherent and incoherent two-level defects. We have shown theoretical calculations characterizing this interaction for all relevant parameter regimes. In the weak coupling limit, the interaction can be described in an effective bath picture, where the TLS act as parts of a large, decohering environment. For strong coupling, however, the coherent dynamics of the full coupled system has to be considered. We show the calculations of the coupled time-evolution and again characterize the interaction by an effective decoherence rate. We also used experimental data to characterize the microscopic origin of the defects and the details of their interaction with the circuits. The results obtained by analyzing spectroscopic data allow us to place strong constraint on several microscopic models for the observed TLS. However, these calculations are not yet fully conclusive as to the physical nature of the TLS. We propose additional experiments to fully characterize the interaction part of the Hamiltonian, thus providing the answer to the question of the physical origin of the coupling. Additionally we have developed a method to directly drive individual defect states via virtual excitation of the qubit. This method allows one to directly probe the properties of single TLS and possibly make use of their superior coherence times for quantum information purposes. The last part of this thesis provided a way for a possible implementation of geometric quantum computation in

  18. Integrated circuits for multimedia applications

    DEFF Research Database (Denmark)

    Vandi, Luca

    2007-01-01

    , and it is applied to a broad-band dual-loop receiver architecture in order to boost the linearity performances of the stage. A simplified noise- and linearity analysis of the circuit is derived, and a comparison is provided with a more traditional dual-loop topology (a broad-band stage based on shunt...... the impact of substrate-induced currents. Basic models are derived in the design phase, and the technological limits of the device are considered. Measurement results show that a very compact coil can provide ~1nH inductance up to 20GHz (physical limit for the measurement equipment), with a peak quality...

  19. Model reduction for circuit simulation

    CERN Document Server

    Hinze, Michael; Maten, E Jan W Ter

    2011-01-01

    Simulation based on mathematical models plays a major role in computer aided design of integrated circuits (ICs). Decreasing structure sizes, increasing packing densities and driving frequencies require the use of refined mathematical models, and to take into account secondary, parasitic effects. This leads to very high dimensional problems which nowadays require simulation times too large for the short time-to-market demands in industry. Modern Model Order Reduction (MOR) techniques present a way out of this dilemma in providing surrogate models which keep the main characteristics of the devi

  20. HF radio systems and circuits

    CERN Document Server

    Sabin, William

    1998-01-01

    A comprehensive reference for the design of high frequency communications systems and equipment. This revised edition is loaded with practical data, much of which cannot be found in other reference books. Its approach to the subject follows the needs of an engineer from system definition and performance requirements down to the individual circuit elements that make up radio transmitters and receivers. The accompanying disk contains updated software on filters, matching networks and receiver analysis. SciTech Publishing also provides many other products related to Communication Systems Design.

  1. Polysilicon photoconductor for integrated circuits

    Science.gov (United States)

    Hammond, R.B.; Bowman, D.R.

    1989-04-11

    A photoconductive element of polycrystalline silicon is provided with intrinsic response time which does not limit overall circuit response. An undoped polycrystalline silicon layer is deposited by LPCVD to a selected thickness on silicon dioxide. The deposited polycrystalline silicon is then annealed at a selected temperature and for a time effective to obtain crystal sizes effective to produce an enhanced current output. The annealed polycrystalline layer is subsequently exposed and damaged by ion implantation to a damage factor effective to obtain a fast photoconductive response. 6 figs.

  2. Wideband 4-diode sampling circuit

    Science.gov (United States)

    Wojtulewicz, Andrzej; Radtke, Maciej

    2016-09-01

    The objective of this work was to develop a wide-band sampling circuit. The device should have the ability to collect samples of a very fast signal applied to its input, strengthen it and prepare for further processing. The study emphasizes the method of sampling pulse shaping. The use of ultrafast pulse generator allows sampling signals with a wide frequency spectrum, reaching several gigahertzes. The device uses a pulse transformer to prepare symmetrical pulses. Their final shape is formed with the help of the step recovery diode, two coplanar strips and Schottky diode. Made device can be used in the sampling oscilloscope, as well as other measurement system.

  3. Circuit QED with transmon qubits

    Energy Technology Data Exchange (ETDEWEB)

    Wulschner, Karl Friedrich; Puertas, Javier; Baust, Alexander; Eder, Peter; Fischer, Michael; Goetz, Jan; Haeberlein, Max; Schwarz, Manuel; Xie, Edwar; Zhong, Ling; Deppe, Frank; Fedorov, Kirill; Marx, Achim; Menzel, Edwin; Gross, Rudolf [Walther-Meissner-Institut, Bayerische Akademie der Wissenschaften, Garching (Germany); Physik-Department, TU Muenchen, Garching (Germany); Nanosystems Initiative Munich (NIM), Muenchen (Germany); Huebl, Hans [Walther-Meissner-Institut, Bayerische Akademie der Wissenschaften, Garching (Germany); Nanosystems Initiative Munich (NIM), Muenchen (Germany); Weides, Martin [Karlsruhe Institute of Technology (KIT), Karlsruhe (Germany)

    2015-07-01

    Superconducting quantum bits are basic building blocks for circuit QED systems. Applications in the fields of quantum computation and quantum simulation require long coherence times. We have fabricated and characterized superconducting transmon qubits which are designed to operate at a high ratio of Josephson energy and charging energy. Due to their low sensitivity to charge noise transmon qubits show good coherence properties. We couple transmon qubits to coplanar waveguide resonators and coplanar slotline resonators and characterize the devices at mK-temperatures. From the experimental data we derive the qubit-resonator coupling strength, the qubit relaxation time and calibrate the photon number in the resonator via Stark shifts.

  4. Stochastic Mesocortical Dynamics and Robustness of Working Memory during Delay-Period.

    Directory of Open Access Journals (Sweden)

    Melissa Reneaux

    Full Text Available The role of prefronto-mesoprefrontal system in the dopaminergic modulation of working memory during delayed response tasks is well-known. Recently, a dynamical model of the closed-loop mesocortical circuit has been proposed which employs a deterministic framework to elucidate the system's behavior in a qualitative manner. Under natural conditions, noise emanating from various sources affects the circuit's functioning to a great extent. Accordingly in the present study, we reformulate the model into a stochastic framework and investigate its steady state properties in the presence of constant background noise during delay-period. From the steady state distribution, global potential landscape and signal-to-noise ratio are obtained which help in defining robustness of the circuit dynamics. This provides insight into the robustness of working memory during delay-period against its disruption due to background noise. The findings reveal that the global profile of circuit's robustness is predominantly governed by the level of D1 receptor activity and high D1 receptor stimulation favors the working memory-associated sustained-firing state over the spontaneous-activity state of the system. Moreover, the circuit's robustness is further fine-tuned by the levels of excitatory and inhibitory activities in a way such that the robustness of sustained-firing state exhibits an inverted-U shaped profile with respect to D1 receptor stimulation. It is predicted that the most robust working memory is formed possibly at a subtle ratio of the excitatory and inhibitory activities achieved at a critical level of D1 receptor stimulation. The study also paves a way to understand various cognitive deficits observed in old-age, acute stress and schizophrenia and suggests possible mechanistic routes to the working memory impairments based on the circuit's robustness profile.

  5. Stochastic Mesocortical Dynamics and Robustness of Working Memory during Delay-Period.

    Science.gov (United States)

    Reneaux, Melissa; Gupta, Rahul; Karmeshu

    2015-01-01

    The role of prefronto-mesoprefrontal system in the dopaminergic modulation of working memory during delayed response tasks is well-known. Recently, a dynamical model of the closed-loop mesocortical circuit has been proposed which employs a deterministic framework to elucidate the system's behavior in a qualitative manner. Under natural conditions, noise emanating from various sources affects the circuit's functioning to a great extent. Accordingly in the present study, we reformulate the model into a stochastic framework and investigate its steady state properties in the presence of constant background noise during delay-period. From the steady state distribution, global potential landscape and signal-to-noise ratio are obtained which help in defining robustness of the circuit dynamics. This provides insight into the robustness of working memory during delay-period against its disruption due to background noise. The findings reveal that the global profile of circuit's robustness is predominantly governed by the level of D1 receptor activity and high D1 receptor stimulation favors the working memory-associated sustained-firing state over the spontaneous-activity state of the system. Moreover, the circuit's robustness is further fine-tuned by the levels of excitatory and inhibitory activities in a way such that the robustness of sustained-firing state exhibits an inverted-U shaped profile with respect to D1 receptor stimulation. It is predicted that the most robust working memory is formed possibly at a subtle ratio of the excitatory and inhibitory activities achieved at a critical level of D1 receptor stimulation. The study also paves a way to understand various cognitive deficits observed in old-age, acute stress and schizophrenia and suggests possible mechanistic routes to the working memory impairments based on the circuit's robustness profile.

  6. Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits

    International Nuclear Information System (INIS)

    Nishigai, T.; Ito, M.; Yoshikawa, N.; Fujimaki, A.; Terai, H.; Yorozu, S.

    2005-01-01

    We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10 ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10 ps

  7. Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors

    Science.gov (United States)

    Saripalli, Vinay; Narayanan, Vijay; Datta, Suman

    Novel medical applications involving embedded sensors, require ultra low energy dissipation with low-to-moderate performance (10kHz-100MHz) driving the conventional MOSFETs into sub-threshold operation regime. In this paper, we present an alternate ultra-low power computing architecture using Binary Decision Diagram based logic circuits implemented using Single Electron Transistors (SETs) operating in the Coulomb blockade regime with very low supply voltages. We evaluate the energy - performance tradeoff metrics of such BDD circuits using time domain Monte Carlo simulations and compare them with the energy-optimized CMOS logic circuits. Simulation results show that the proposed approach achieves better energy-delay characteristics than CMOS realizations.

  8. Realizing a supercapacitor in an electrical circuit

    International Nuclear Information System (INIS)

    Fukuhara, Mikio; Kuroda, Tomoyuki; Hasegawa, Fumihiko

    2014-01-01

    Capacitors are commonly used in electronic resonance circuits; however, capacitors have not been used for storing large amounts of electrical energy in electrical circuits. Here, we report a superior RC circuit which serves as an electrical storage system characterized by quick charging and long-term discharging of electricity. The improved energy storage characteristics in this mixed electric circuit (R 1  + R 2 C 1 ) with small resistor R 1 , large resistor R 2 , and large capacitor C 1 are derived from the damming effect by large R 2 in simple parallel R 2 C 1 circuit. However, no research work has been carried out previously on the use of capacitors as electrical energy storage devices in circuits. Combined with nanotechnology, we hope that our finding will play a remarkable role in a variety of applications such as hybrid electric vehicles and backup power supplies

  9. Delays and networked control systems

    CERN Document Server

    Hetel, Laurentiu; Daafouz, Jamal; Johansson, Karl

    2016-01-01

    This edited monograph includes state-of-the-art contributions on continuous time dynamical networks with delays. The book is divided into four parts. The first part presents tools and methods for the analysis of time-delay systems with a particular attention on control problems of large scale or infinite-dimensional systems with delays. The second part of the book is dedicated to the use of time-delay models for the analysis and design of Networked Control Systems. The third part of the book focuses on the analysis and design of systems with asynchronous sampling intervals which occur in Networked Control Systems. The last part of the book exposes several contributions dealing with the design of cooperative control and observation laws for networked control systems. The target audience primarily comprises researchers and experts in the field of control theory, but the book may also be beneficial for graduate students. .

  10. Linear rotary optical delay lines

    Science.gov (United States)

    Guerboukha, Hichem; Qu, Hang; Skorobogatiy, Maksim

    2016-03-01

    We present a semi-analytical solution for the design of a high-speed rotary optical delay line that use a combination of two rotating curvilinear reflectors. We demonstrate that it is possible to design an infinite variety of the optical delay lines featuring linear dependence of the optical delay on the rotation angle. This is achieved via shape optimization of the rotating reflector surfaces. Moreover, a convenient spatial separation of the incoming and outgoing beams is possible. For the sake of example, we present blades that fit into a circle of 10cm diameter. Finally, a prototype of a rotary delay line is fabricated using CNC machining, and its optical properties are characterized.

  11. Systematics in delayed neutron yields

    Energy Technology Data Exchange (ETDEWEB)

    Ohsawa, Takaaki [Kinki Univ., Higashi-Osaka, Osaka (Japan). Atomic Energy Research Inst.

    1998-03-01

    An attempt was made to reproduce the systematic trend observed in the delayed neutron yields for actinides on the basis of the five-Gaussian representation of the fission yield together with available data sets for delayed neutron emission probability. It was found that systematic decrease in DNY for heavier actinides is mainly due to decrease of fission yields of precursors in the lighter side of the light fragment region. (author)

  12. The analysis and design of linear circuits

    CERN Document Server

    Thomas, Roland E; Toussaint, Gregory J

    2009-01-01

    The Analysis and Design of Linear Circuits, 6e gives the reader the opportunity to not only analyze, but also design and evaluate linear circuits as early as possible. The text's abundance of problems, applications, pedagogical tools, and realistic examples helps engineers develop the skills needed to solve problems, design practical alternatives, and choose the best design from several competing solutions. Engineers searching for an accessible introduction to resistance circuits will benefit from this book that emphasizes the early development of engineering judgment.

  13. Test and Diagnosis of Integrated Circuits

    OpenAIRE

    Bosio , Alberto

    2015-01-01

    The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users...

  14. An analog integrated circuit design laboratory

    OpenAIRE

    Mondragon-Torres, A.F.; Mayhugh, Jr.; Pineda de Gyvez, J.; Silva-Martinez, J.; Sanchez-Sinencio, E.

    2003-01-01

    We present the structure of an analog integrated circuit design laboratory to instruct at both, senior undergraduate and entry graduate levels. The teaching material includes: a laboratory manual with analog circuit design theory, pre-laboratory exercises and circuit design specifications; a reference web page with step by step instructions and examples; the use of mathematical tools for automation and analysis; and state of the art CAD design tools in use by industry. Upon completion of the ...

  15. Logarithmic current-measuring transistor circuits

    DEFF Research Database (Denmark)

    Højberg, Kristian Søe

    1967-01-01

    Describes two transistorized circuits for the logarithmic measurement of small currents suitable for nuclear reactor instrumentation. The logarithmic element is applied in the feedback path of an amplifier, and only one dual transistor is used as logarithmic diode and temperature compensating...... transistor. A simple one-amplifier circuit is compared with a two-amplifier system. The circuits presented have been developed in connexion with an amplifier using a dual m.o.s. transistor input stage with diode-protected gates....

  16. Electronic circuits for communications systems: A compilation

    Science.gov (United States)

    1972-01-01

    The compilation of electronic circuits for communications systems is divided into thirteen basic categories, each representing an area of circuit design and application. The compilation items are moderately complex and, as such, would appeal to the applications engineer. However, the rationale for the selection criteria was tailored so that the circuits would reflect fundamental design principles and applications, with an additional requirement for simplicity whenever possible.

  17. Analytical applications for delayed neutrons

    International Nuclear Information System (INIS)

    Eccleston, G.W.

    1983-01-01

    Analytical formulations that describe the time dependence of neutron populations in nuclear materials contain delayed-neutron dependent terms. These terms are important because the delayed neutrons, even though their yields in fission are small, permit control of the fission chain reaction process. Analytical applications that use delayed neutrons range from simple problems that can be solved with the point reactor kinetics equations to complex problems that can only be solved with large codes that couple fluid calculations with the neutron dynamics. Reactor safety codes, such as SIMMER, model transients of the entire reactor core using coupled space-time neutronics and comprehensive thermal-fluid dynamics. Nondestructive delayed-neutron assay instruments are designed and modeled using a three-dimensional continuous-energy Monte Carlo code. Calculations on high-burnup spent fuels and other materials that contain a mix of uranium and plutonium isotopes require accurate and complete information on the delayed-neutron periods, yields, and energy spectra. A continuing need exists for delayed-neutron parameters for all the fissioning isotopes

  18. Instrumentation for Sodium Circuits; Instrumentation des Circuits de Sodium

    Energy Technology Data Exchange (ETDEWEB)

    Cambillard, E. [CEA, Centre d' Etudes Nucleaires de Fontenay-aux-Roses (France); Lions, N. [CEA, Centre d' Etudes Nucleaires de Cadarache (France)

    1967-06-15

    Electromagnetic flow meters, level gauges and differential pressure gauges are among the main measurement instruments designed and tested at the Commissariat a l'Energie Atomique (CEA) for sodium reactors. The main characteristics of the flow meters used with RAPSODIE are indicated. The instruments used in this connection are of the permanent -magnet or electromagnet type (in the primary circuits). A description is given of the calibration methods employed - use is made of diaphragms or Venturi tubes as standard flow meters - and information is given on the results measured for maximum sodium flows of 400 m{sup 3}/h. Three types of continuous level gauge have been studied. Resistance gauge. Two varieties used for the 1 - and 10-MW test circuits of RAPSODIE are described. In one there is a compensation resistance along the whole height of the measuring element (the continuous gauges used with the RAPSODIE reactor are at present of this type). In the other type of gauge a device is incorporated to heat the measurement element and prevent the formation of conducting deposits (prototype sodium tests have been completed). Induction gauge. This type has two coupled coils and is fitted with a device to compensate for temperature effects. A description is given of a prototype which has been built and the results obtained in the course of sodium tests are described. Ultrasonic gauge. With this type, a transmitter is fitted on top of the outside of the sodium container; there is also a vertical wave guide, the bottom of which is immersed in the liquid metal and possesses a reflector system which returns the ultrasonic beam towards the surface. Fixed reference marks provide a permanent means of calibration and the whole apparatus is welded. This type of gauge is now being constructed. The differential pressure gauges that have been built, and used in particular with Venturi tube flow meters, are modified versions of the devices employed with the 1 - and 10-MW test circuits of

  19. Analog circuit design art, science, and personalities

    CERN Document Server

    Williams, Jim

    1991-01-01

    Analog Circuit Design: Art, Science, and Personalities discusses the many approaches and styles in the practice of analog circuit design. The book is written in an informal yet informative manner, making it easily understandable to those new in the field. The selection covers the definition, history, current practice, and future direction of analog design; the practice proper; and the styles in analog circuit design. The book also includes the problems usually encountered in analog circuit design; approach to feedback loop design; and other different techniques and applications. The text is

  20. Circuit For Control Of Electromechanical Prosthetic Hand

    Science.gov (United States)

    Bozeman, Richard J., Jr.

    1995-01-01

    Proposed circuit for control of electromechanical prosthetic hand derives electrical control signals from shoulder movements. Updated, electronic version of prosthesis, that includes two hooklike fingers actuated via cables from shoulder harness. Circuit built around favored shoulder harness, provides more dexterous movement, without incurring complexity of computer-controlled "bionic" or hydraulically actuated devices. Additional harness and potentiometer connected to similar control circuit mounted on other shoulder. Used to control stepping motor rotating hand about prosthetic wrist to one of number of angles consistent with number of digital outputs. Finger-control signals developed by circuit connected to first shoulder harness transmitted to prosthetic hand via sliprings at prosthetic wrist joint.

  1. Model Order Reduction for Electronic Circuits:

    DEFF Research Database (Denmark)

    Hjorth, Poul G.; Shontz, Suzanne

    Electronic circuits are ubiquitous; they are used in numerous industries including: the semiconductor, communication, robotics, auto, and music industries (among many others). As products become more and more complicated, their electronic circuits also grow in size and complexity. This increased...... in the semiconductor industry. Circuit simulation proceeds by using Maxwell’s equations to create a mathematical model of the circuit. The boundary element method is then used to discretize the equations, and the variational form of the equations are then solved on the graph network....

  2. Radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Hughes, R.C.

    1977-01-01

    Electronic circuits that operate properly after exposure to ionizing radiation are necessary for nuclear weapon systems, satellites, and apparatus designed for use in radiation environments. The program to develop and theoretically model radiation-tolerant integrated circuit components has resulted in devices that show an improvement in hardness up to a factor of ten thousand over earlier devices. An inverter circuit produced functions properly after an exposure of 10 6 Gy (Si) which, as far as is known, is the record for an integrated circuit

  3. Hyperchaotic circuit with damped harmonic oscillators

    DEFF Research Database (Denmark)

    Lindberg, Erik; Murali, K.; Tamasevicius, A.

    2001-01-01

    A simple fourth-order hyperchaotic circuit with damped harmonic oscillators is described. ANP3 and PSpice simulations including an eigenvalue study of the linearized Jacobian are presented together with a hardware implementation. The circuit contains two inductors with series resistance, two ideal...... capacitors and one nonlinear active conductor. The Lyapunov exponents are presented to confirm the hyperchaotic nature of the oscillations of the circuit. The nonlinear conductor is realized with a diode. A negative impedance converter and a linear resistor. The performance of the circuit is investigated...... by means of numerical integration of the appropriate differential equations....

  4. Electronic circuit for control rod attracting electromagnet

    International Nuclear Information System (INIS)

    Ito, Koji.

    1991-01-01

    The present invention provides a discharging circuit for control rod attracting electromagnet used for a reactor which is highly reliable and has high performance. The resistor of the circuit comprises a non-linear resistor element and a blocking rectification element connected in series. The discharging circuit can be prevented from short-circuit by selecting a resistor having a resistance value about ten times as great as the coil resistance, even in a case where the blocking rectification element and the non-linear resistor element are failed. Accordingly, reduction of attracting force and the increase of scream releasing time can be minimized. (I.S.)

  5. Electric circuit theory applied electricity and electronics

    CERN Document Server

    Yorke, R

    1981-01-01

    Electric Circuit Theory provides a concise coverage of the framework of electrical engineering. Comprised of six chapters, this book emphasizes the physical process of electrical engineering rather than abstract mathematics. Chapter 1 deals with files, circuits, and parameters, while Chapter 2 covers the natural and forced response of simple circuit. Chapter 3 talks about the sinusoidal steady state, and Chapter 4 discusses the circuit analysis. The fifth chapter tackles frequency response of networks, and the last chapter covers polyphase systems. This book will be of great help to electrical

  6. Intrinsic neuromodulation: altering neuronal circuits from within.

    Science.gov (United States)

    Katz, P S; Frost, W N

    1996-02-01

    There are two sources of neuromodulation for neuronal circuits: extrinsic inputs and intrinsic components of the circuits themselves. Extrinsic neuromodulation is known to be pervasive in nervous systems, but intrinsic neuromodulation is less recognized, despite the fact that it has now been demonstrated in sensory and neuromuscular circuits and in central pattern generators. By its nature, intrinsic neuromodulation produces local changes in neuronal computation, whereas extrinsic neuromodulation can cause global changes, often affecting many circuits simultaneously. Studies in a number of systems are defining the different properties of these two forms of neuromodulation.

  7. The Software Reliability of Large Scale Integration Circuit and Very Large Scale Integration Circuit

    OpenAIRE

    Artem Ganiyev; Jan Vitasek

    2010-01-01

    This article describes evaluation method of faultless function of large scale integration circuits (LSI) and very large scale integration circuits (VLSI). In the article there is a comparative analysis of factors which determine faultless of integrated circuits, analysis of already existing methods and model of faultless function evaluation of LSI and VLSI. The main part describes a proposed algorithm and program for analysis of fault rate in LSI and VLSI circuits.

  8. Electrical circuit theory and technology

    CERN Document Server

    Bird, John

    2014-01-01

    This much-loved textbook explains the principles of electrical circuit theory and technology so that students of electrical and mechanical engineering can master the subject. Real-world situations and engineering examples put the theory into context. The inclusion of worked problems with solutions help you to learn and further problems then allow you to test and confirm you have fully understood each subject. In total the book contains 800 worked problems, 1000 further problems and 14 revision tests with answers online. This an ideal text for foundation and undergraduate degree students and those on upper level vocational engineering courses, in particular electrical and mechanical. It provides a sound understanding of the knowledge required by technicians in fields such as electrical engineering, electronics and telecommunications. This edition has been updated with developments in key areas such as semiconductors, transistors, and fuel cells, along with brand new material on ABCD parameters and Fourier's An...

  9. Shapeable short circuit resistant capacitor

    Science.gov (United States)

    Taylor, Ralph S.; Myers, John D.; Baney, William J.

    2015-10-06

    A ceramic short circuit resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The capacitor that exhibits a benign failure mode in which a multitude of discrete failure events result in a gradual loss of capacitance. Each event is a localized event in which localized heating causes an adjacent portion of one or both of the electrodes to vaporize, physically cleaning away electrode material from the failure site. A first metal electrode, a second metal electrode, and a ceramic dielectric layer between the electrodes are thin enough to be formed in a serpentine-arrangement with gaps between the first electrode and the second electrode that allow venting of vaporized electrode material in the event of a benign failure.

  10. [Migratory circuits in western Mexico].

    Science.gov (United States)

    Durand, J

    1986-11-01

    The author examines patterns of internal and international migration in western Mexico. "Drawing on data from different sources and statistics, the essay demonstrates the importance of both types of migration, the changes in endogenous and exogenous factors which have affected the life and the migratory patterns of the population of this region. The migratory circuit being a flow not only of persons, but of goods and capital as well, the cities, specifically that of Guadalajara, have a strategic importance. They fulfill various functions and have become the backbone of the migratory process: they serve as centers for attracting and 'hosting' internal migrants as well as places of origin for other migrants; jumping-off points for international migrants; and the milieu in which many returning migrants of rural origin settle." (SUMMARY IN ENG AND FRE) excerpt

  11. TIME CALIBRATED OSCILLOSCOPE SWEEP CIRCUIT

    Science.gov (United States)

    Smith, V.L.; Carstensen, H.K.

    1959-11-24

    An improved time calibrated sweep circuit is presented, which extends the range of usefulness of conventional oscilloscopes as utilized for time calibrated display applications in accordance with U. S. Patent No. 2,832,002. Principal novelty resides in the provision of a pair of separate signal paths, each of which is phase and amplitude adjustable, to connect a high-frequency calibration oscillator to the output of a sawtooth generator also connected to the respective horizontal deflection plates of an oscilloscope cathode ray tube. The amplitude and phase of the calibration oscillator signals in the two signal paths are adjusted to balance out feedthrough currents capacitively coupled at high frequencies of the calibration oscillator from each horizontal deflection plate to the vertical plates of the cathode ray tube.

  12. Integrated Circuit Electromagnetic Immunity Handbook

    Science.gov (United States)

    Sketoe, J. G.

    2000-08-01

    This handbook presents the results of the Boeing Company effort for NASA under contract NAS8-98217. Immunity level data for certain integrated circuit parts are discussed herein, along with analytical techniques for applying the data to electronics systems. This handbook is built heavily on the one produced in the seventies by McDonnell Douglas Astronautics Company (MDAC, MDC Report E1929 of 1 August 1978, entitled Integrated Circuit Electromagnetic Susceptibility Handbook, known commonly as the ICES Handbook, which has served countless systems designers for over 20 years). Sections 2 and 3 supplement the device susceptibility data presented in section 4 by presenting information on related material required to use the IC susceptibility information. Section 2 concerns itself with electromagnetic susceptibility analysis and serves as a guide in using the information contained in the rest of the handbook. A suggested system hardening requirements is presented in this chapter. Section 3 briefly discusses coupling and shielding considerations. For conservatism and simplicity, a worst case approach is advocated to determine the maximum amount of RF power picked up from a given field. This handbook expands the scope of the immunity data in this Handbook is to of 10 MHz to 10 GHz. However, the analytical techniques provided are applicable to much higher frequencies as well. It is expected however, that the upper frequency limit of concern is near 10 GHz. This is due to two factors; the pickup of microwave energy on system cables and wiring falls off as the square of the wavelength, and component response falls off at a rapid rate due to the effects of parasitic shunt paths for the RF energy. It should be noted also that the pickup on wires and cables does not approach infinity as the frequency decreases (as would be expected by extrapolating the square law dependence of the high frequency roll-off to lower frequencies) but levels off due to mismatch effects.

  13. Apparatus and method for defect testing of integrated circuits

    Science.gov (United States)

    Cole, Jr., Edward I.; Soden, Jerry M.

    2000-01-01

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  14. Short circuit in deep brain stimulation.

    Science.gov (United States)

    Samura, Kazuhiro; Miyagi, Yasushi; Okamoto, Tsuyoshi; Hayami, Takehito; Kishimoto, Junji; Katano, Mitsuo; Kamikaseda, Kazufumi

    2012-11-01

    The authors undertook this study to investigate the incidence, cause, and clinical influence of short circuits in patients treated with deep brain stimulation (DBS). After the incidental identification of a short circuit during routine follow-up, the authors initiated a policy at their institution of routinely evaluating both therapeutic impedance and system impendence at every outpatient DBS follow-up visit, irrespective of the presence of symptoms suggesting possible system malfunction. This study represents a report of their findings after 1 year of this policy. Implanted DBS leads exhibiting short circuits were identified in 7 patients (8.9% of the patients seen for outpatient follow-up examinations during the 12-month study period). The mean duration from DBS lead implantation to the discovery of the short circuit was 64.7 months. The symptoms revealing short circuits included the wearing off of therapeutic effect, apraxia of eyelid opening, or dysarthria in 6 patients with Parkinson disease (PD), and dystonia deterioration in 1 patient with generalized dystonia. All DBS leads with short circuits had been anchored to the cranium using titanium miniplates. Altering electrode settings resulted in clinical improvement in the 2 PD cases in which patients had specific symptoms of short circuits (2.5%) but not in the other 4 cases. The patient with dystonia underwent repositioning and replacement of a lead because the previous lead was located too anteriorly, but did not experience symptom improvement. In contrast to the sudden loss of clinical efficacy of DBS caused by an open circuit, short circuits may arise due to a gradual decrease in impedance, causing the insidious development of neurological symptoms via limited or extended potential fields as well as shortened battery longevity. The incidence of short circuits in DBS may be higher than previously thought, especially in cases in which DBS leads are anchored with miniplates. The circuit impedance of DBS

  15. Multi-format all-optical processing based on a large-scale, hybridly integrated photonic circuit.

    Science.gov (United States)

    Bougioukos, M; Kouloumentas, Ch; Spyropoulou, M; Giannoulis, G; Kalavrouziotis, D; Maziotis, A; Bakopoulos, P; Harmon, R; Rogers, D; Harrison, J; Poustie, A; Maxwell, G; Avramopoulos, H

    2011-06-06

    We investigate through numerical studies and experiments the performance of a large scale, silica-on-silicon photonic integrated circuit for multi-format regeneration and wavelength-conversion. The circuit encompasses a monolithically integrated array of four SOAs inside two parallel Mach-Zehnder structures, four delay interferometers and a large number of silica waveguides and couplers. Exploiting phase-incoherent techniques, the circuit is capable of processing OOK signals at variable bit rates, DPSK signals at 22 or 44 Gb/s and DQPSK signals at 44 Gbaud. Simulation studies reveal the wavelength-conversion potential of the circuit with enhanced regenerative capabilities for OOK and DPSK modulation formats and acceptable quality degradation for DQPSK format. Regeneration of 22 Gb/s OOK signals with amplified spontaneous emission (ASE) noise and DPSK data signals degraded with amplitude, phase and ASE noise is experimentally validated demonstrating a power penalty improvement up to 1.5 dB.

  16. Design of an improved RCD buffer circuit for full bridge circuit

    Science.gov (United States)

    Yang, Wenyan; Wei, Xueye; Du, Yongbo; Hu, Liang; Zhang, Liwei; Zhang, Ou

    2017-05-01

    In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubber circuit with the improved RCD snubber circuit. By comparing and analyzing, it is proved that the improved buffer circuit can absorb surge voltage. Finally, experiments are demonstrated to validate that the correctness of the RC formula and the improved RCD snubber circuit.

  17. Macromodels of digital integrated circuits for program packages of circuit engineering design

    Science.gov (United States)

    Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

    1984-04-01

    Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

  18. Integrated circuit and method of arbitration in a network on an integrated circuit.

    NARCIS (Netherlands)

    2011-01-01

    The invention relates to an integrated circuit and to a method of arbitration in a network on an integrated circuit. According to the invention, a method of arbitration in a network on an integrated circuit is provided, the network comprising a router unit, the router unit comprising a first input

  19. Piezoelectric pump and pressurised circuit provided therewith

    NARCIS (Netherlands)

    Van Es, Johannes; Wits, Wessel Willems

    2015-01-01

    A piezoelectric pump for use in a pressurised circuit is provided, comprising a pump chamber (5) with an inlet (6) provided with a one way inlet valve (7), for connection to a feeding line (8) of the pressurised circuit and an outlet (9) provided with a one way outlet valve (10), for connection to a

  20. IMPORTANT NOTICE: Cancellation of shuttle Circuit 3

    CERN Multimedia

    2013-01-01

    Circuit 3 of the CERN Shuttle Service (Point 5), which has served CMS since the start of LS1, will be cancelled with effect from Tuesday 16 April. This decision has been taken in consultation with CMS, as the circuit was seldom used.   In response to increasing demand for Circuit 1 - Meyrin and feedback from passengers, the two Circuit 3 journeys will be switched to Circuit 1 – Meyrin (see new timetable below): Mornings: Four journeys instead of three. Circuit 1 now starts at 8:10 (instead of 8:19 a.m.) and runs until 9:27 a.m. (instead of 9:16 a.m.). Lunchtimes: Five journeys in place between 12:10 p.m. and 1:47 p.m. Evenings: Circuit starts at 5:23 p.m. (instead of 5:03 p.m.) and ends at 6:20 p.m. at Building 33. Please note that the circuit will depart from Building 13 instead of Building 33.  

  1. Water quality control program in experimental circuits

    International Nuclear Information System (INIS)

    Cegalla, Miriam A.

    1996-01-01

    The Water Quality Control Program of the Experimental Circuits visualizes studying the water chemistry of the cooling in the primary and secondary circuits, monitoring the corrosion of the systems and studying the mechanism of the corrosion products transport in the systems. (author)

  2. Hacking DNA copy number for circuit engineering.

    Science.gov (United States)

    Wu, Feilun; You, Lingchong

    2017-07-27

    DNA copy number represents an essential parameter in the dynamics of synthetic gene circuits but typically is not explicitly considered. A new study demonstrates how dynamic control of DNA copy number can serve as an effective strategy to program robust oscillations in gene expression circuits.

  3. The testing of generator circuit-breakers

    NARCIS (Netherlands)

    Smeets, R.P.P.; Linden, van der W.A.

    1998-01-01

    Generator circuit-breakers face much higher current and voltage stress than distribution switchgear. This has led to a special standard (ANSI C37.013). Strictly in accordance with this standard's requirements, test circuits and parameters for a 100 kA and 120 kA (25.3 kV) SF6 generator

  4. Digital Circuit Analysis Using an 8080 Processor.

    Science.gov (United States)

    Greco, John; Stern, Kenneth

    1983-01-01

    Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)

  5. Post irradiation effects (PIE) in integrated circuits

    International Nuclear Information System (INIS)

    Barnes, C.E.; Shaw, D.C.; Fleetwood, D.M.; Winokur, P.S.

    1992-01-01

    Post Irradiation Effects (PIE) ranging from normal recovery catastrophic failure have been observed in integrated circuits during the PIE period. These variations indicate that a rebound or PIE recipe used for radiation hardness assurance must be chosen with care. In this paper, the authors provide examples of PIE in a variety of integrated circuits of importance to spacecraft electronics

  6. Active components for integrated plasmonic circuits

    DEFF Research Database (Denmark)

    Krasavin, A.V.; Bolger, P.M.; Zayats, A.V.

    2009-01-01

    We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides.......We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides....

  7. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  8. Two New Families of Floating FDNR Circuits

    Directory of Open Access Journals (Sweden)

    Ahmed M. Soliman

    2010-01-01

    Full Text Available Two new configurations for realizing ideal floating frequency-dependent negative resistor elements (FDNR are introduced. The proposed circuits are symmetrical and are realizable by four CCII or ICCII or a combination of both. Each configuration is realizable by eight different circuits. Simulation results are included to support the theory.

  9. 30 CFR 56.6407 - Circuit testing.

    Science.gov (United States)

    2010-07-01

    ... series or the resistance of multiple balanced series to be connected in parallel prior to their... detonator series. (d) Total blasting circuit resistance prior to connection to the power source. Nonelectric... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Circuit testing. 56.6407 Section 56.6407...

  10. Understanding the Behaviour of Infinite Ladder Circuits

    Science.gov (United States)

    Ucak, C.; Yegin, K.

    2008-01-01

    Infinite ladder circuits are often encountered in undergraduate electrical engineering and physics curricula when dealing with series and parallel combination of impedances, as a part of filter design or wave propagation on transmission lines. The input impedance of such infinite ladder circuits is derived by assuming that the input impedance does…

  11. A new integrated microwave SQUID circuit design

    International Nuclear Information System (INIS)

    Erne, S.N.; Finnegan, T.F.

    1980-01-01

    In this paper we consider the design and operation of a planar thin-film rf-SQUID circuit which can be realized via microwave-integrated-circuit (MIC) techniques and which differs substantially from pervious microwave SQUID configurations involving either mechanical point-contact or cylindrical thin-film micro-bridge geometries. (orig.)

  12. Textbook Error: Short Circuiting on Electrochemical Cell

    Science.gov (United States)

    Bonicamp, Judith M.; Clark, Roy W.

    2007-01-01

    Short circuiting an electrochemical cell is an unreported but persistent error in the electrochemistry textbooks. It is suggested that diagrams depicting a cell delivering usable current to a load be postponed, the theory of open-circuit galvanic cells is explained, the voltages from the tables of standard reduction potentials is calculated and…

  13. The Short Circuit Model of Reading.

    Science.gov (United States)

    Lueers, Nancy M.

    The name "short circuit" has been given to this model because, in many ways, it adequately describes what happens bioelectrically in the brain. The "short-circuiting" factors include linguistic, sociocultural, attitudinal and motivational, neurological, perceptual, and cognitive factors. Research is reviewed on ways in which each one affects any…

  14. Integrated optical circuit comprising a polarization convertor

    NARCIS (Netherlands)

    1998-01-01

    An integrated optical circuit includes a first device and a second device, which devices are connected by a polarization convertor. The polarization convertor includes a curved section of a waveguide, integrated in the optical circuit. The curved section may have several differently curved

  15. Worst Asymmetrical Short-Circuit Current

    DEFF Research Database (Denmark)

    Arana Aristi, Iván; Holmstrøm, O; Grastrup, L

    2010-01-01

    In a typical power plant, the production scenario and the short-circuit time were found for the worst asymmetrical short-circuit current. Then, a sensitivity analysis on the missing generator values was realized in order to minimize the uncertainty of the results. Afterward the worst asymmetrical...

  16. DEVICES FOR COOLING ELECTRONIC CIRCUIT BOARDS

    OpenAIRE

    T. A. Ismailov; D. V. Evdulov; A. G. Mustafaev; D. K. Ramazanova

    2014-01-01

    In the work described structural variants of devices for cooling electronic circuit boards, made on the basis of thermoelectric batteries and consumable working substances, implementing uneven process of removing heat from heat-generating components. A comparison of temperature fields of electronic circuit simulator with his uniform and non-uniform cooling. 

  17. DEVICES FOR COOLING ELECTRONIC CIRCUIT BOARDS

    Directory of Open Access Journals (Sweden)

    T. A. Ismailov

    2014-01-01

    Full Text Available In the work described structural variants of devices for cooling electronic circuit boards, made on the basis of thermoelectric batteries and consumable working substances, implementing uneven process of removing heat from heat-generating components. A comparison of temperature fields of electronic circuit simulator with his uniform and non-uniform cooling. 

  18. 30 CFR 75.1323 - Blasting circuits.

    Science.gov (United States)

    2010-07-01

    ...) Blasting circuits shall be protected from sources of stray electric current. (b) Detonators made by different manufacturers shall not be combined in the same blasting circuit. (c) Detonator leg wires shall be... used between the blasting cable and detonator circuitry shall— (1) Be undamaged; (2) Be well insulated...

  19. F-Paris: integrated electronic circuits [Tender

    CERN Multimedia

    2003-01-01

    "Fourniture, montage et tests des circuits imprimes et modules multi composants pour le trajectographe central de CMS. Maximum de 12 000 circuits imprimes et modules multi-composants necessaires au trajectographe central de l'experience CMS aupres du Large Hadron Collider" (1 page).

  20. Automatic design of digital synthetic gene circuits.

    Directory of Open Access Journals (Sweden)

    Mario A Marchisio

    2011-02-01

    Full Text Available De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.

  1. Circuit II--A Conversational Graphical Interface.

    Science.gov (United States)

    Singer, Ronald A.

    1993-01-01

    Provides an overview of Circuit II, an interactive system that provides users with a graphical representation of an electronic circuit within which questions may be posed and manipulated, and discusses how mouse selections have analogous roles to certain natural language features, such as anaphora, deixis, and ellipsis. (13 references) (EA)

  2. Circuits in the Sun: Solar Panel Physics

    Science.gov (United States)

    Gfroerer, Tim

    2013-01-01

    Typical commercial solar panels consist of approximately 60 individual photovoltaic cells connected in series. Since the usual Kirchhoff rules apply, the current is uniform throughout the circuit, while the electric potential of the individual devices is cumulative. Hence, a solar panel is a good analog of a simple resistive series circuit, except…

  3. Design of arithmetic circuits in quantum dot cellular automata nanotechnology

    CERN Document Server

    Sridharan, K

    2015-01-01

    This research monograph focuses on the design of arithmetic circuits in Quantum Dot Cellular Automata (QCA). Using the fact that the 3-input majority gate is a primitive in QCA, the book sets out to discover hitherto unknown properties of majority logic in the context of arithmetic circuit designs. The pursuit for efficient adders in QCA takes two forms. One involves application of the new results in majority logic to existing adders. The second involves development of a custom adder for QCA technology. A QCA adder named as hybrid adder is proposed and it is shown that it outperforms existing multi-bit adders with respect to area and delay. The work is extended to the design of a low-complexity multiplier for signed numbers in QCA. Furthermore the book explores two aspects unique to QCA technology, namely thermal robustness and the role of interconnects. In addition, the book introduces the reader to QCA layout design and simulation using QCADesigner. Features & Benefits: This research-based book: ·  �...

  4. Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Tooraj Nikoubin

    2010-01-01

    Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

  5. A monolithic constant-fraction discriminator using distributed R-C delay-line shaping

    International Nuclear Information System (INIS)

    Simpson, M.L.; Young, G.R.; Xu, M.

    1995-01-01

    A monolithic, CMOS, constant-fraction discriminator (CFD) was fabricated in the Orbit Semiconductor, 1.2 μ N-well process. This circuit uses an on-chip, distributed, R-C delay-line to realize the constant-fraction shaping. The delay-line is constructed from a narrow, 500-μ serpentine layer of polysilicon above a wide, grounded, second layer of polysilicon. This R-C delay-line generates about 1.1 ns of delay for 5 ns risetime signals with a slope degradation of only ≅ 15% and an amplitude reduction of about 6.1%. The CFD also features an automatic walk adjustment. The entire circuit, including the delay line, has a 200 μ pitch and is 950 μ long. The walk for a 5 ns risetime signal was measured as ± 100 ps over the 100:1 dynamic range from -15 mV to -1.5 mV. to -1.5 V. The CFD consumes 15 mW

  6. A Parallel Genetic Algorithm for Automated Electronic Circuit Design

    Science.gov (United States)

    Lohn, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris; Norvig, Peter (Technical Monitor)

    2000-01-01

    We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

  7. Designing Novel Quaternary Quantum Reversible Subtractor Circuits

    Science.gov (United States)

    Haghparast, Majid; Monfared, Asma Taheri

    2018-01-01

    Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.

  8. Synthesis of logic circuits with evolutionary algorithms

    Energy Technology Data Exchange (ETDEWEB)

    JONES,JAKE S.; DAVIDSON,GEORGE S.

    2000-01-26

    In the last decade there has been interest and research in the area of designing circuits with genetic algorithms, evolutionary algorithms, and genetic programming. However, the ability to design circuits of the size and complexity required by modern engineering design problems, simply by specifying required outputs for given inputs has as yet eluded researchers. This paper describes current research in the area of designing logic circuits using an evolutionary algorithm. The goal of the research is to improve the effectiveness of this method and make it a practical aid for design engineers. A novel method of implementing the algorithm is introduced, and results are presented for various multiprocessing systems. In addition to evolving standard arithmetic circuits, work in the area of evolving circuits that perform digital signal processing tasks is described.

  9. Physically based arc-circuit interaction

    International Nuclear Information System (INIS)

    Zhong-Lie, L.

    1984-01-01

    An integral arc model is extended to study the interaction of the gas blast arc with the test circuit in this paper. The deformation in the waveshapes of arc current and voltage around the current zero has been formulated to first approximation by using a simple model of arc voltage based on the arc core energy conservation. By supplementing with the time scale for the radiation, the time rates of arc processes were amended. Both the contributions of various arc processes and the influence of circuit parameters to the arc-circuit interaction have been estimated by this theory. Analysis generated a new method of calculating test circuit parameters which improves the accurate simulation of arc-circuit interaction. The new method agrees with the published experimental results

  10. Remote tuning of NMR probe circuits.

    Science.gov (United States)

    Kodibagkar, V D; Conradi, M S

    2000-05-01

    There are many circumstances in which the probe tuning adjustments cannot be located near the rf NMR coil. These may occur in high-temperature NMR, low-temperature NMR, and in the use of magnets with small diameter access bores. We address here circuitry for connecting a fixed-tuned probe circuit by a transmission line to a remotely located tuning network. In particular, the bandwidth over which the probe may be remotely tuned while keeping the losses in the transmission line acceptably low is considered. The results show that for all resonant circuit geometries (series, parallel, series-parallel), overcoupling of the line to the tuned circuit is key to obtaining a large tuning bandwidth. At equivalent extents of overcoupling, all resonant circuit geometries have nearly equal remote tuning bandwidths. Particularly for the case of low-loss transmission line, the tuning bandwidth can be many times the tuned circuit's bandwidth, f(o)/Q. Copyright 2000 Academic Press.

  11. Precise linear gating circuit on integrated microcircuits

    Energy Technology Data Exchange (ETDEWEB)

    Butskii, V.V.; Vetokhin, S.S.; Reznikov, I.V.

    Precise linear gating circuit on four microcircuits is described. A basic flowsheet of the gating circuit is given. The gating circuit consists of two input differential cascades total load of which is two current followers possessing low input and high output resistances. Follower outlets are connected to high ohmic dynamic load formed with a current source which permits to get high amplification (>1000) at one cascade. Nonlinearity amounts to <0.1% in the range of input signal amplitudes of -10-+10 V. Front duration for an output signal with 10 V amplitude amounts to 100 ns. Attenuation of input signal with a closed gating circuit is 60 db. The gating circuits described is used in the device intended for processing of scintillation sensor signals.

  12. On equivalent resistance of electrical circuits

    Science.gov (United States)

    Kagan, Mikhail

    2015-01-01

    While the standard (introductory physics) way of computing the equivalent resistance of nontrivial electrical circuits is based on Kirchhoff's rules, there is a mathematically and conceptually simpler approach, called the method of nodal potentials, whose basic variables are the values of the electric potential at the circuit's nodes. In this paper, we review the method of nodal potentials and illustrate it using the Wheatstone bridge as an example. We then derive a closed-form expression for the equivalent resistance of a generic circuit, which we apply to a few sample circuits. The result unveils a curious interplay between electrical circuits, matrix algebra, and graph theory and its applications to computer science. The paper is written at a level accessible by undergraduate students who are familiar with matrix arithmetic. Additional proofs and technical details are provided in appendices.

  13. Trigger circuits for the PHENIX electromagnetic calorimeter

    International Nuclear Information System (INIS)

    Frank, S.S.; Britton, C.L. Jr.; Winterberg, A.L.; Young, G.R.

    1997-11-01

    Monolithic and discrete circuits have been developed to provide trigger signals for the PHENIX electromagnetic calorimeter detector. These trigger circuits are deadtimeless and create overlapping 4 by 4 energy sums, a cosmic muon trigger, and a 144 channel energy sum. The front end electronics of the PHENIX system sample the energy and timing channels at each bunch crossing (BC) but it is not known immediately if this data is of interest. The information from the trigger circuits is used to determine if the data collected is of interest and should be digitized and stored or discarded. This paper presents details of the design, issues affecting circuit performance, characterization of prototypes fabricated in 1.2 microm Orbit CMOS, and integration of the circuits into the EMCal electronics system

  14. Grounding and shielding circuits and interference

    CERN Document Server

    Morrison, Ralph

    2016-01-01

    Applies basic field behavior in circuit design and demonstrates how it relates to grounding and shielding requirements and techniques in circuit design This book connects the fundamentals of electromagnetic theory to the problems of interference in all types of electronic design. The text covers power distribution in facilities, mixing of analog and digital circuitry, circuit board layout at high clock rates, and meeting radiation and susceptibility standards. The author examines the grounding and shielding requirements and techniques in circuit design and applies basic physics to circuit behavior. The sixth edition of this book has been updated with new material added throughout the chapters where appropriate. The presentation of the book has also been rearranged in order to reflect the current trends in the field.

  15. Logic delays of 5-μm resistor coupled Josephson logic

    International Nuclear Information System (INIS)

    Sone, J.; Yoshida, T.; Tahara, S.; Abe, H.

    1982-01-01

    Logic delays of resistor coupled Josephson logic (RCJL) have been investigated. An experimental circuit with a cascade chain of ten RCJL OR gates was fabricated using Pb-alloy Josephson IC technology with 5-μm minimum linewidth. Logic delay was measured to be as low as 10.8 ps with power dissipation of 11.7 μW. This demonstrates a switching operation faster than those reported for other Josephson gate designs. Comparison with computer-simulation results is also presented

  16. Volumetric and chemical control auxiliary circuit for a PWR primary circuit

    International Nuclear Information System (INIS)

    Costes, D.

    1990-01-01

    The volumetric and chemical control circuit has an expansion tank with at least one water-steam chamber connected to the primary circuit by a sampling pipe and a reinjection pipe. The sampling pipe feeds jet pumps controlled by valves. An action on these valves and pumps regulates the volume of the water in the primary circuit. A safety pipe controlled by a flap automatically injects water from the chamber into the primary circuit in case of ruptures. The auxiliary circuit has also systems for purifying the water and controlling the boric acid and hydrogen content [fr

  17. Light Sources and Ballast Circuits

    Science.gov (United States)

    Yorifuji, Takashi; Sakai, Makoto; Yasuda, Takeo; Maehara, Akiyoshi; Okada, Atsunori; Gouriki, Takeshi; Mannami, Tomoaki

    discharge models were reported. Further, studies on ultra high-pressure mercury lamps as light sources for projectors are becoming the mainstream of HID lamp related researches. For high-pressure sodium lamps, many studies on plant growing and pest control utilizing low insect attracting aspects were also reported in 2006. Additionally, for discharge lamps, the minimum sustaining electric power for arc tubes employed in electrode-less compact fluorescent lamps was investigated. For Hg-free rare-gas fluorescent lamps, a luminance of 10,000cd/m2 was attained by a 1 meter-long external duplex spiral electrode prototype using Xe/Ne barrier discharge. As to startup circuits, the commercialization of energy saving and high value added products mainly associated with fluorescent lamps and HID lamps are becoming common. Further, the miniaturization of startup circuits for self electronic-ballasted lamps has advanced. Speaking of the overall light sources and startup circuits in 2006 and with the enforcement of RoHS in Europe in July, the momentum toward hazardous substance-free and energy saving initiatives has been enhanced from the perspective of protecting the global environment. It is anticipated that similar restrictions will be globally enforced in the future.

  18. Chaos in the delay logistic equation with discontinuous delays

    International Nuclear Information System (INIS)

    Sen, Ayan; Mukherjee, Debasis

    2009-01-01

    This paper analyzes a delay logistic equation which models a feedback control problem. Interval map associated to the system is derived. By calculating Lyapunov exponent, we indicate stable orbit and chaotic phenomenon respectively. The results are verified through computer simulation. We identify the parameter which controls the dynamics.

  19. Postraumatic delayed loss of vision

    International Nuclear Information System (INIS)

    Partington, C.R.; Graves, V.B.; Ruetenacht, D.A.; Weinstein, J.M.; Strother, C.M.

    1989-01-01

    The imaging studies and clinical findings in 10 patients who suffered delayed vision loss beginning 1 day to 13 years after head trauma have been reviewed. Two different primary lesions could be identified: pseudoaneurysm of the internal carotid artery and carotid cavernous fistula. The pathologic changes associated with pseudoaneurysm included compression of the optic nerves and/or chiasm by arterial aneurysm and intracranial hematoma. Carotid cavernous fistula caused delayed vision loss by compression of the optic nerves and chiasm by saccular dilatation of the cavernous sinus and by abnormal orbital venous drainage with retinal venous stasis, retinal edema, and glaucoma

  20. Time delayed Ensemble Nudging Method

    Science.gov (United States)

    An, Zhe; Abarbanel, Henry

    Optimal nudging method based on time delayed embedding theory has shows potentials on analyzing and data assimilation in previous literatures. To extend the application and promote the practical implementation, new nudging assimilation method based on the time delayed embedding space is presented and the connection with other standard assimilation methods are studied. Results shows the incorporating information from the time series of data can reduce the sufficient observation needed to preserve the quality of numerical prediction, making it a potential alternative in the field of data assimilation of large geophysical models.

  1. Circuit arrangement of an electronic component for the design of fail-safe protective circuits

    International Nuclear Information System (INIS)

    Centmaier, W.; Bernhard, U.; Friederich, B.; Heisecke, I.

    1974-01-01

    The critical parameters of reactors are controlled by safety circuits. These circuits are controlled designed as logic modules operating by the 'n-out-of-m' selection principle. In most cases, a combination of a '1-out-of-3' circuit with a '2-out-of-3' circuit and separate indication is sufficient for a dynamic fail-safe circuit. The basic logic elements are AND and OR gate circuits, respectively, which are triggered by pulse trains and in which the failure of a pulse train is indicated as an error at the output. The module allows the design of safety circuits offering various degrees of safety. If the indication of an error is made on the modules, faulty components can be exchanged by the maintenance crew right away. (DG) [de

  2. Aging evaluation of electrical circuits using the ECCAD [Electrical Circuit Characterization and Diagnostic] system

    International Nuclear Information System (INIS)

    Edson, J.L.

    1988-01-01

    As a part of the Nuclear Regulatory Commission Nuclear Plant Aging Research Program, an aging assessment of electrical circuits was conducted at the Shippingport Atomic Power Station Decommissioning Project. The objective of this work was to evaluate the effectiveness of the Electrical Circuit Characterization and Diagnostic (ECCAD) system in identifying circuit conditions, to determine the present condition of selected electrical circuits, and correlate the results with aging effects. To accomplish this task, a series of electrical tests was performed on each circuit using the ECCAD system, which is composed of commercially available electronic test equipment under computer control. Test results indicate that the ECCAD system is effective in detecting and identifying aging and service wear in selected electrical circuits. The major area of degradation in the circuits tested was at the termination/connection points, whereas the cables were in generally good condition

  3. 49 CFR 236.563 - Delay time.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Delay time. 236.563 Section 236.563 Transportation... Cab Signal Systems Rules and Instructions; Locomotives § 236.563 Delay time. Delay time of automatic... requirements of § 236.24 shall take into consideration the delay time. ...

  4. Quantum interference in plasmonic circuits.

    Science.gov (United States)

    Heeres, Reinier W; Kouwenhoven, Leo P; Zwiller, Valery

    2013-10-01

    Surface plasmon polaritons (plasmons) are a combination of light and a collective oscillation of the free electron plasma at metal/dielectric interfaces. This interaction allows subwavelength confinement of light beyond the diffraction limit inherent to dielectric structures. As a result, the intensity of the electromagnetic field is enhanced, with the possibility to increase the strength of the optical interactions between waveguides, light sources and detectors. Plasmons maintain non-classical photon statistics and preserve entanglement upon transmission through thin, patterned metallic films or weakly confining waveguides. For quantum applications, it is essential that plasmons behave as indistinguishable quantum particles. Here we report on a quantum interference experiment in a nanoscale plasmonic circuit consisting of an on-chip plasmon beamsplitter with integrated superconducting single-photon detectors to allow efficient single plasmon detection. We demonstrate a quantum-mechanical interaction between pairs of indistinguishable surface plasmons by observing Hong-Ou-Mandel (HOM) interference, a hallmark non-classical interference effect that is the basis of linear optics-based quantum computation. Our work shows that it is feasible to shrink quantum optical experiments to the nanoscale and offers a promising route towards subwavelength quantum optical networks.

  5. Four-deep charge-time and pulse-width scaling discriminator for delay line MWPC's

    International Nuclear Information System (INIS)

    Lee, K.L.; Kirsten, F.A.; Grigorian, A.; Guiragossian, Z.G.T.

    1976-01-01

    A discriminator has been developed for digitizing both intercepted total charge and location of electromagnetic shower and particle trajectories in multi-wire proportional chambers read by delay lines. Determination of shower trajectory is aided by video signal integration followed by centroid-locating discrimination. Calibrated run-down of the signal integrating capacitor gives the charge information above a given threshold level. The discriminator is designed to handle up to four shower-induced video signals per event by incorporating steering circuits within the module. Each video signal is examined for time over an adjustable threshold. Video pulses with separation of less than 20 nsec are treated as a single pulse. Counter-logic circuits indicate the number of video signals digitized. These signal processing circuits provide a first level of data sifting which otherwise must be carried out with additional discriminator channels and added complexity in data recognition

  6. Short circuit protection for a power distribution system

    Science.gov (United States)

    Owen, J. R., III

    1969-01-01

    Sensing circuit detects when the output from a matrix is present and when it should be present. The circuit provides short circuit protection for a power distribution system where the selection of the driven load is accomplished by digital logic.

  7. A programming language for composable DNA circuits.

    Science.gov (United States)

    Phillips, Andrew; Cardelli, Luca

    2009-08-06

    Recently, a range of information-processing circuits have been implemented in DNA by using strand displacement as their main computational mechanism. Examples include digital logic circuits and catalytic signal amplification circuits that function as efficient molecular detectors. As new paradigms for DNA computation emerge, the development of corresponding languages and tools for these paradigms will help to facilitate the design of DNA circuits and their automatic compilation to nucleotide sequences. We present a programming language for designing and simulating DNA circuits in which strand displacement is the main computational mechanism. The language includes basic elements of sequence domains, toeholds and branch migration, and assumes that strands do not possess any secondary structure. The language is used to model and simulate a variety of circuits, including an entropy-driven catalytic gate, a simple gate motif for synthesizing large-scale circuits and a scheme for implementing an arbitrary system of chemical reactions. The language is a first step towards the design of modelling and simulation tools for DNA strand displacement, which complements the emergence of novel implementation strategies for DNA computing.

  8. Pulse generator circuit triggerable by nuclear radiation

    International Nuclear Information System (INIS)

    Fredrickson, P.B.

    1980-01-01

    A pulse generator circuit triggerable by a pulse of nuclear radiation is described. The pulse generator circuit includes a pair of transistors arranged, together with other electrical components, in the topology of a standard monostable multivibrator circuit. The circuit differs most significantly from a standard monostable multivibrator circuit in that the circuit is adapted to be triggered by a pulse of nuclear radiation rather than electrically and the transistors have substantially different sensitivities to radiation, due to different physical and electrical characteristics and parameters. One of the transistors is employed principally as a radiation detector and is in a normally non-conducting state and the other transistor is normally in a conducting state. When the circuit is exposed to a pulse of nuclear radiation, currents are induced in the collector-base junctions of both transistors but, due to the different radiation sensitivities of the transistors, the current induced in the collector-base junction of the radiation-detecting transistor is substantially greater than that induced in the collector-base junction of the other transistor. The pulse of radiation causes the radiation-detecting transistor to operate in its conducting state, causing the other transistor to operate in its non-conducting state. As the radiation-detecting transistor operates in its conducting state, an output signal is produced at an output terminal connected to the radiation-detecting transistor indicating the presence of a predetermined intensity of nuclear radiation

  9. Early-delayed radiation rhombencephalopathy

    International Nuclear Information System (INIS)

    Nightingale, S.; Dawes, P.J.D.K.; Cartlidge, N.E.F.; Newcastle upon Tyne Univ.

    1982-01-01

    A 37-year-old woman developed an early-delayed rhombencephalopathy 7 weeks after completing a course of radiotherapy to a glomus jugulare tumour. The clinical features, comprising nystagmus, skew strabismus, unilateral facial weakness, dysarthria and ataxia, are compared with four previously reported patients with this syndrome. (author)

  10. Another definition for time delay

    International Nuclear Information System (INIS)

    Narnhofer, H.

    1980-01-01

    Time delay is defined by geometrical considerations which work in classical as well as in quantum mechanics, and its connection with the S-matrix and the virial is proven for potentials with V(x vector) and x vector V(x vector) vanishing as rsup(-1-epsilon) for r -> infinity. (Author)

  11. Weather delay costs to trucking.

    Science.gov (United States)

    2012-11-01

    Estimates of the nations freight sector of transportation range to upwards of $600 billion of total gross domestic product with 70 percent of total value and 60 percent of total weight moving by truck. Weather-related delays can add significantly ...

  12. Diagnostic Delay in Rheumatoid Arthritis

    DEFF Research Database (Denmark)

    Mølbaek, Karen; Hørslev-Petersen, Kim; Primdahl, Jette

    2016-01-01

    BACKGROUND: To prevent joint damage among patients with rheumatoid arthritis (RA), there is a need to minimize delays from the onset of symptoms until the initiation of appropriate therapy. The present study explored the factors that have an impact on the time it takes for Danish patients with RA...

  13. Design flaw could delay collider

    CERN Multimedia

    Cho, Adrian

    2007-01-01

    "A magnet for the Large Hadron Collider (LHC) failed during a key test at the European particle physics laboratory CERN last week. Physicists and engineers will have to repair the damaged magnet and retrofit others to correct the underlynig design flaw, which could delay the start-up of the mammouth subterranean machine." (1,5 page)

  14. Concurrent Delay in Construction Disputes

    DEFF Research Database (Denmark)

    Cavaleri, Sylvie Cécile

    the delay is contractually defined as a contractor's risk, the contractor is liable to pay liquidated damages to the employer; if it is not, the contractor can under certain circumstances claim an extension of time and in some cases also economic compensation from the employer. The situation where a given...

  15. Deconstructing delayed posttraumatic stress disorder

    NARCIS (Netherlands)

    Smid, G

    2011-01-01

    According to the Diagnostic and Statistical Manual of Mental Disorders, delayed posttraumatic stress disorder (PTSD) must be diagnosed in individuals fulfilling criteria for PTSD if the onset of symptoms is at least six months after the trauma. The purpose of this thesis was to establish the

  16. Livermore blasted for project delay

    CERN Multimedia

    1999-01-01

    In a 12 page report issued last week, a review committee set up by the University of California has concluded that mismanagement and poor planning are to blame for significant cost overruns and delays in the construction of NIF, the worlds largest laser (1 page).

  17. Providing delay guarantees in Bluetooth

    NARCIS (Netherlands)

    Ait Yaiz, R.; Heijenk, Geert; Titsworth, F.

    2003-01-01

    Bluetooth polling, also referred to as Bluetooth MAC scheduling or intra-piconet scheduling, is the mechanism that schedules the traffic between the participants in a Bluetooth network. Hence, this mechanism is highly determining with respect to the delay packets experience in a Bluetooth network.

  18. Tester Detects Steady-Short Or Intermittent-Open Circuits

    Science.gov (United States)

    Anderson, Bobby L.

    1990-01-01

    Momentary open circuits or steady short circuits trigger buzzer. Simple, portable, lightweight testing circuit sounds long-duration alarm when it detects steady short circuit or momentary open circuit in coaxial cable or other two-conductor transmission line. Tester sensitive to discontinuities lasting 10 microseconds or longer. Used extensively for detecting intermittent open shorts in accelerometer and extensometer cables. Also used as ordinary buzzer-type continuity checker to detect steady short or open circuits.

  19. Semiconductors integrated circuit design for manufacturability

    CERN Document Server

    Balasinki, Artur

    2011-01-01

    Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

  20. Silicon integrated circuits part A : supplement 2

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

  1. Multi-qubit circuit quantum electrodynamics

    International Nuclear Information System (INIS)

    Viehmann, Oliver

    2013-01-01

    Circuit QED systems are macroscopic, man-made quantum systems in which superconducting artificial atoms, also called Josephson qubits, interact with a quantized electromagnetic field. These systems have been devised to mimic the physics of elementary quantum optical systems with real atoms in a scalable and more flexible framework. This opens up a variety of possible applications of circuit QED systems. For instance, they provide a promising platform for processing quantum information. Recent years have seen rapid experimental progress on these systems, and experiments with multi-component circuit QED architectures are currently starting to come within reach. In this thesis, circuit QED systems with multiple Josephson qubits are studied theoretically. We focus on simple and experimentally realistic extensions of the currently operated circuit QED setups and pursue investigations in two main directions. First, we consider the equilibrium behavior of circuit QED systems containing a large number of mutually noninteracting Josephson charge qubits. The currently accepted standard description of circuit QED predicts the possibility of superradiant phase transitions in such systems. However, a full microscopic treatment shows that a no-go theorem for superradiant phase transitions known from atomic physics applies to circuit QED systems as well. This reveals previously unknown limitations of the applicability of the standard theory of circuit QED to multi-qubit systems. Second, we explore the potential of circuit QED for quantum simulations of interacting quantum many-body systems. We propose and analyze a circuit QED architecture that implements the quantum Ising chain in a time-dependent transverse magnetic field. Our setup can be used to study quench dynamics, the propagation of localized excitations, and other non-equilibrium features in this paradigmatic model in the theory of non-equilibrium thermodynamics and quantumcritical phenomena. The setup is based on a

  2. Controllable clock circuit design in PEM system

    International Nuclear Information System (INIS)

    Sun Yunhua; Wang Peihua; Hu Tingting; Feng Baotong; Shuai Lei; Huang Huan; Wei Shujun; Li Ke; Zhao Jingwei; Wei Long

    2011-01-01

    A high-precision synchronized clock circuit design will be presented, which can supply steady, reliable and anti-jamming clock signal for the data acquirement (DAQ) system of Positron Emission Mammography (PEM). This circuit design is based on the Single-Chip Microcomputer and high-precision clock chip, and can achieve multiple controllable clock signals. The jamming between the clock signals can be reduced greatly with the differential transmission. Meanwhile, the adoption of CAN bus control in the clock circuit can prompt the clock signals to be transmitted or masked simultaneously when needed. (authors)

  3. Controllable clock circuit design in PEM system

    International Nuclear Information System (INIS)

    Sun Yunhua; Wang Peilin; Hu Tingting; Feng Baotong; Shuai Lei; Huang Huan; Wei Shujun; Li Ke; Zhao Jingwei; Wei Long

    2010-01-01

    A high-precision synchronized clock circuit design will be presented, which can supply steady, reliable and anti-jamming clock signal for the data acquirement (DAQ) system of Positron Emission Mammography (PEM). This circuit design is based on the Single-Chip Microcomputer and high-precision clock chip, and can achieve multiple controllable clock signals. The jamming between the clock signals can be reduced greatly with the differential transmission. Meanwhile, the adoption of CAN bus control in the clock circuit can prompt the clock signals to be transmitted or masked simultaneously when needed. (authors)

  4. Equivalent circuit analysis of terahertz metamaterial filters

    KAUST Repository

    Zhang, Xueqian

    2011-01-01

    An equivalent circuit model for the analysis and design of terahertz (THz) metamaterial filters is presented. The proposed model, derived based on LMC equivalent circuits, takes into account the detailed geometrical parameters and the presence of a dielectric substrate with the existing analytic expressions for self-inductance, mutual inductance, and capacitance. The model is in good agreement with the experimental measurements and full-wave simulations. Exploiting the circuit model has made it possible to predict accurately the resonance frequency of the proposed structures and thus, quick and accurate process of designing THz device from artificial metamaterials is offered. ©2011 Chinese Optics Letters.

  5. Microelectronic circuit design for energy harvesting systems

    CERN Document Server

    Di Paolo Emilio, Maurizio

    2017-01-01

    This book describes the design of microelectronic circuits for energy harvesting, broadband energy conversion, new methods and technologies for energy conversion. The author also discusses the design of power management circuits and the implementation of voltage regulators. Coverage includes advanced methods in low and high power electronics, as well as principles of micro-scale design based on piezoelectric, electromagnetic and thermoelectric technologies with control and conditioning circuit design. Provides a single-source reference to energy harvesting and its applications; Serves as a practical guide to microelectronics design for energy harvesting, with application to mobile power supplies; Enables readers to develop energy harvesting systems for wearable/mobile electronics.

  6. Multi-qubit circuit quantum electrodynamics

    Energy Technology Data Exchange (ETDEWEB)

    Viehmann, Oliver

    2013-09-03

    Circuit QED systems are macroscopic, man-made quantum systems in which superconducting artificial atoms, also called Josephson qubits, interact with a quantized electromagnetic field. These systems have been devised to mimic the physics of elementary quantum optical systems with real atoms in a scalable and more flexible framework. This opens up a variety of possible applications of circuit QED systems. For instance, they provide a promising platform for processing quantum information. Recent years have seen rapid experimental progress on these systems, and experiments with multi-component circuit QED architectures are currently starting to come within reach. In this thesis, circuit QED systems with multiple Josephson qubits are studied theoretically. We focus on simple and experimentally realistic extensions of the currently operated circuit QED setups and pursue investigations in two main directions. First, we consider the equilibrium behavior of circuit QED systems containing a large number of mutually noninteracting Josephson charge qubits. The currently accepted standard description of circuit QED predicts the possibility of superradiant phase transitions in such systems. However, a full microscopic treatment shows that a no-go theorem for superradiant phase transitions known from atomic physics applies to circuit QED systems as well. This reveals previously unknown limitations of the applicability of the standard theory of circuit QED to multi-qubit systems. Second, we explore the potential of circuit QED for quantum simulations of interacting quantum many-body systems. We propose and analyze a circuit QED architecture that implements the quantum Ising chain in a time-dependent transverse magnetic field. Our setup can be used to study quench dynamics, the propagation of localized excitations, and other non-equilibrium features in this paradigmatic model in the theory of non-equilibrium thermodynamics and quantumcritical phenomena. The setup is based on a

  7. Newnes passive and discrete circuits pocket book

    CERN Document Server

    MARSTON, R M

    2000-01-01

    Newnes Passive and Discrete Circuits Pocket Book is aimed at all engineers, technicians, students and experimenters who can build a design directly from a circuit diagram. In a highly concise form Ray Marston presents a huge compendium of circuits that can be built as they appear, adapted or used as building blocks. The devices used have been carefully chosen for their ease of availability and reasonable price. The selection of devices has been thoroughly updated for the second edition, which has also been expanded to cover the latest ICs.The three sections of the book cover: Moder

  8. Intrinsic and extrinsic neuromodulation of motor circuits.

    Science.gov (United States)

    Katz, P S

    1995-12-01

    Neuromodulation of motor circuits by extrinsic inputs provides enormous flexibility in the production of behavior. Recent work has shown that neurons intrinsic to central pattern-generating circuits can evoke neuromodulatory effects in addition to their neurotransmitting actions. Modulatory neurons often elicit a multitude of different effects attributable to actions at different receptors and/or through the release of co-transmitters. Differences in neuromodulation between species can account for differences in behavior. Modulation of neuromodulation may provide an additional level of flexibility to motor circuits.

  9. A guide to printed circuit board design

    CERN Document Server

    Hamilton, Charles

    1984-01-01

    A Guide to Printed Circuit Board Design discusses the basic design principles of printed circuit board (PCB). The book consists of nine chapters; each chapter provides both text discussion and illustration relevant to the topic being discussed. Chapter 1 talks about understanding the circuit diagram, and Chapter 2 covers how to compile component information file. Chapter 3 deals with the design layout, while Chapter 4 talks about preparing the master artworks. The book also covers generating computer aided design (CAD) master patterns, and then discusses how to prepare the production drawing a

  10. Power electronics handbook components, circuits and applications

    CERN Document Server

    Mazda, F F

    1993-01-01

    Power Electronics Handbook: Components, Circuits, and Applications is a collection of materials about power components, circuit design, and applications. Presented in a practical form, theoretical information is given as formulae. The book is divided into three parts. Part 1 deals with the usual components found in power electronics such as semiconductor devices and power semiconductor control components, their electronic compatibility, and protection. Part 2 tackles parts and principles related to circuits such as switches; link frequency chargers; converters; and AC line control, and Part 3

  11. Method of manufacturing Josephson junction integrated circuits

    International Nuclear Information System (INIS)

    Jillie, D.W. Jr.; Smith, L.N.

    1985-01-01

    Josephson junction integrated circuits of the current injection type and magnetically controlled type utilize a superconductive layer that forms both Josephson junction electrode for the Josephson junction devices on the integrated circuit as well as a ground plane for the integrated circuit. Large area Josephson junctions are utilized for effecting contact to lower superconductive layers and islands are formed in superconductive layers to provide isolation between the groudplane function and the Josephson junction electrode function as well as to effect crossovers. A superconductor-barrier-superconductor trilayer patterned by local anodization is also utilized with additional layers formed thereover. Methods of manufacturing the embodiments of the invention are disclosed

  12. Maximum Temperature Detection System for Integrated Circuits

    Science.gov (United States)

    Frankiewicz, Maciej; Kos, Andrzej

    2015-03-01

    The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

  13. Radio-frequency integrated-circuit engineering

    CERN Document Server

    Nguyen, Cam

    2015-01-01

    Radio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC's using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. Provide

  14. Theory of circuit block switch-off

    Directory of Open Access Journals (Sweden)

    S. Henzler

    2004-01-01

    Full Text Available Switching-off unused circuit blocks is a promising approach to supress static leakage currents in ultra deep sub-micron CMOS digital systems. Basic performance parameters of Circuit Block Switch-Off (CBSO schemes are defined and their dependence on basic circuit parameters is estimated. Therefore the design trade-off between strong leakage suppression in idle mode and adequate dynamic performance in active mode can be supported by simple analytic investigations. Additionally, a guideline for the estimation of the minimum time for which a block deactivation is useful is derived.

  15. Operational amplifier circuits analysis and design

    CERN Document Server

    Nelson, J C C

    1995-01-01

    This book, a revised and updated version of the author's Basic Operational Amplifiers (Butterworths 1986), enables the non-specialist to make effective use of readily available integrated circuit operational amplifiers for a range of applications, including instrumentation, signal generation and processing.It is assumed the reader has a background in the basic techniques of circuit analysis, particularly the use of j notation for reactive circuits, with a corresponding level of mathematical ability. The underlying theory is explained with sufficient but not excessive, detail. A range of compu

  16. Efficiency of homopolar generators without ferromagnetic circuit

    International Nuclear Information System (INIS)

    Kharitonov, V.V.

    1982-01-01

    E.m.f. and weights of homopolar generators (HG) without a ferromagnetic circuit and of similar generator with a ferromagnetic circuit are compared at equal armature diameters and armature rotative speed. HG without ferromagnetic cuircuit of disk and cylinder types with hot and superconducting excitation winding are considered. Areas of the most reasonable removal of a ferromagnetic circuit in the HG layout are found. The plots of relationships between the e.m.f. and HG weight that permit to estimate the efficiency of ''nonferrite'' HG constructions are presented

  17. Comparison of modified driver circuit and capacitor-transfer circuit in longitudinally excited N2 laser.

    Science.gov (United States)

    Uno, Kazuyuki; Akitsu, Tetsuya; Nakamura, Kenshi; Jitsuno, Takahisa

    2013-04-01

    We developed a modified driver circuit composed of a capacitance and a spark gap, called a direct-drive circuit, for a longitudinally excited gas laser. The direct-drive circuit uses a large discharge impedance caused by a long discharge length of the longitudinal excitation scheme and eliminates the buffer capacitance used in the traditional capacitor-transfer circuit. We compared the direct-drive circuit and the capacitor-transfer circuit in a longitudinally excited N2 laser (wavelength: 337 nm). Producing high output energy with the capacitor-transfer circuit requires a large storage capacitance and a discharge tube with optimum dimensions (an inner diameter of 4 mm and a length of 10 cm in this work); in contrast, the direct-drive circuit requires a high breakdown voltage, achieved with a small storage capacitance and a large discharge tube. Additionally, for the same input energy of 792 mJ, the maximum output energy of the capacitor-transfer circuit was 174.2 μJ, and that of the direct-drive circuit was 344.7 μJ.

  18. Model Comparison Exercise Circuit Training Game and Circuit Ladder Drills to Improve Agility and Speed

    Directory of Open Access Journals (Sweden)

    Susilaturochman Hendrawan Koestanto

    2017-11-01

    Full Text Available The purpose of this study was to compare: (1 the effect of circuit training game and circuit ladder drill for the agility; (2 the effect of circuit training game and circuit ladder drill on speed; (3 the difference effect of circuit training game and circuit ladder drill for the speed (4 the difference effect of circuit training game and circuit ladder drill on agility. The type of this research was quantitative with quasi-experimental methods. The design of this research was Factorial Design, with analysing data using ANOVA. The process of data collection was done by using 30 meters sprint speed test and shuttle run test during the pretest and posttest. Furthermore, the data was analyzed by using SPSS 22.0 series. Result: The circuit training game exercise program and circuit ladder drill were significant to increase agility and speed (sig 0.000 < α = 0.005 Group I, II, III had significant differences (sig 0.000 < α = 0.005. The mean of increase in speed of group I = 0.20 seconds, group II = 0.31 seconds, and group III = 0.11 seconds. The average increase agility to group I = 0.34 seconds group II = 0.60 seconds, group III = 0.13 seconds. Based on the analysis above, it could be concluded that there was an increase in the speed and agility of each group after being given a training.

  19. State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

    Science.gov (United States)

    Breuer, M. A.; Carlan, A. J.

    1982-10-01

    Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

  20. Power ion beam production in a magnetic-insulated diode placed in a circuit with an inductive storage with a plasmoerosion circuit breaker

    International Nuclear Information System (INIS)

    Anan'in, P.S.; Karpov, V.B.; Krasik, Ya.E.; Paul', E.A.

    1991-01-01

    Consideration is given to results of experimental studies of modes of operation of plasma current breaker and magnetic insulated diode, placed parallel in a circuit with inductive storage and microsecond generator, as well as parameters of high-power ion beam, generated in gas-filled diode. Magnetic field of mirror configuration, which enabled to locate the gas-filled diode dose to breaking region was used for decrease of electrodynamic plasma transfer. It is shown that time delay (of the order of ten and more) of power maximum in gas-filled diode with respect to power maximum in plasma breaker is observed when using passive plasma source on anode