Recent Developments in p-Type Oxide Semiconductor Materials and Devices

KAUST Repository

Wang, Zhenwei

2016-02-16

The development of transparent p-type oxide semiconductors with good performance may be a true enabler for a variety of applications where transparency, power efficiency, and greater circuit complexity are needed. Such applications include transparent electronics, displays, sensors, photovoltaics, memristors, and electrochromics. Hence, here, recent developments in materials and devices based on p-type oxide semiconductors are reviewed, including ternary Cu-bearing oxides, binary copper oxides, tin monoxide, spinel oxides, and nickel oxides. The crystal and electronic structures of these materials are discussed, along with approaches to enhance valence-band dispersion to reduce effective mass and increase mobility. Strategies to reduce interfacial defects, off-state current, and material instability are suggested. Furthermore, it is shown that promising progress has been made in the performance of various types of devices based on p-type oxides. Several innovative approaches exist to fabricate transparent complementary metal oxide semiconductor (CMOS) devices, including novel device fabrication schemes and utilization of surface chemistry effects, resulting in good inverter gains. However, despite recent developments, p-type oxides still lag in performance behind their n-type counterparts, which have entered volume production in the display market. Recent successes along with the hurdles that stand in the way of commercial success of p-type oxide semiconductors are presented.

Recent Developments in p-Type Oxide Semiconductor Materials and Devices

KAUST Repository

Wang, Zhenwei; Nayak, Pradipta K.; Caraveo-Frescas, Jesus Alfonso; Alshareef, Husam N.

2016-01-01

The development of transparent p-type oxide semiconductors with good performance may be a true enabler for a variety of applications where transparency, power efficiency, and greater circuit complexity are needed. Such applications include transparent electronics, displays, sensors, photovoltaics, memristors, and electrochromics. Hence, here, recent developments in materials and devices based on p-type oxide semiconductors are reviewed, including ternary Cu-bearing oxides, binary copper oxides, tin monoxide, spinel oxides, and nickel oxides. The crystal and electronic structures of these materials are discussed, along with approaches to enhance valence-band dispersion to reduce effective mass and increase mobility. Strategies to reduce interfacial defects, off-state current, and material instability are suggested. Furthermore, it is shown that promising progress has been made in the performance of various types of devices based on p-type oxides. Several innovative approaches exist to fabricate transparent complementary metal oxide semiconductor (CMOS) devices, including novel device fabrication schemes and utilization of surface chemistry effects, resulting in good inverter gains. However, despite recent developments, p-type oxides still lag in performance behind their n-type counterparts, which have entered volume production in the display market. Recent successes along with the hurdles that stand in the way of commercial success of p-type oxide semiconductors are presented.

Resistor Extends Life Of Battery In Clocked CMOS Circuit

Science.gov (United States)

Wells, George H., Jr.

1991-01-01

Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

Synthesis, Characterization, and Ultrafast Dynamics of Metal, Metal Oxide, and Semiconductor Nanomaterials

OpenAIRE

Wheeler, Damon Andreas

2013-01-01

SYNTHESIS, CHARACTERIZATION, AND ULTRAFAST DYNAMICS OF METAL, METAL OXIDE, AND SEMICONDUCTOR NANOMATERIALSABSTRACTThe optical properties of each of the three main classes of inorganic nanomaterials, metals, metal oxides, and semiconductors differ greatly due to the intrinsically different nature of the materials. These optical properties are among the most fascinating and useful aspects of nanomaterials with applications spanning cancer treatment, sensors, lasers, and solar cells. One techn...

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Science.gov (United States)

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Recent Advances of Solution-Processed Metal Oxide Thin-Film Transistors.

Science.gov (United States)

Xu, Wangying; Li, Hao; Xu, Jian-Bin; Wang, Lei

2018-03-06

Solution-processed metal oxide thin-film transistors (TFTs) are considered as one of the most promising transistor technologies for future large-area flexible electronics. This review surveys the recent advances in solution-based oxide TFTs, including n-type oxide semiconductors, oxide dielectrics and p-type oxide semiconductors. Firstly, we provide an introduction on oxide TFTs and the TFT configurations and operating principles. Secondly, we present the recent progress in solution-processed n-type transistors, with a special focus on low-temperature and large-area solution processed approaches as well as novel non-display applications. Thirdly, we give a detailed analysis of the state-of-the-art solution-processed oxide dielectrics for low-voltage electronics. Fourthly, we discuss the recent progress in solution-based p-type oxide semiconductors, which will enable the highly desirable future low-cost large-area complementary circuits. Finally, we draw the conclusions and outline the perspectives over the research field.

Exploring SiSn as a performance enhancing semiconductor: A theoretical and experimental approach

KAUST Repository

Hussain, Aftab M.; Singh, Nirpendra; Fahad, Hossain M.; Rader, Kelly; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

2014-01-01

We present a novel semiconducting alloy, silicon-tin (SiSn), as channel material for complementary metal oxide semiconductor (CMOS) circuit applications. The material has been studied theoretically using first principles analysis as well

Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

Science.gov (United States)

McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

2017-03-28

Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

Directory of Open Access Journals (Sweden)

Chyan-Chyi Wu

2011-11-01

Full Text Available A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

Progress in complementary metal–oxide–semiconductor silicon photonics and optoelectronic integrated circuits

International Nuclear Information System (INIS)

Chen Hongda; Zhang Zan; Huang Beiju; Mao Luhong; Zhang Zanyun

2015-01-01

Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits (OEICs) based on a complementary metal–oxide–semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems. (review)

High-precision analog circuit technology for power supply integrated circuits; Dengen IC yo koseido anarogu kairo gijutsu

Energy Technology Data Exchange (ETDEWEB)

Nakamori, A.; Suzuki, T.; Mizoe, K. [Fuji Electric Corporate Research and Development,Ltd., Kanagawa (Japan)

2000-08-10

With the recent rapid spread of portable electronic appliances, specification requirements such as compact power supply and long operation with batteries have become severer. Power supply ICs (integrated circuits) are required to reduce power consumption in the circuit and perform high-precision control. To meet these requirements, Fuji Electric develops high-precision CMOS (complementary metal-oxide semiconductor) analog technology. This paper describes three analog circuit technologies of a voltage reference, an operational amplifier and a comparator as circuit components particularly important for the precision of power supply ICs. (author)

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

Science.gov (United States)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Note: A disposable x-ray camera based on mass produced complementary metal-oxide-semiconductor sensors and single-board computers

Energy Technology Data Exchange (ETDEWEB)

Hoidn, Oliver R.; Seidler, Gerald T., E-mail: seidler@uw.edu [Physics Department, University of Washington, Seattle, Washington 98195 (United States)

2015-08-15

We have integrated mass-produced commercial complementary metal-oxide-semiconductor (CMOS) image sensors and off-the-shelf single-board computers into an x-ray camera platform optimized for acquisition of x-ray spectra and radiographs at energies of 2–6 keV. The CMOS sensor and single-board computer are complemented by custom mounting and interface hardware that can be easily acquired from rapid prototyping services. For single-pixel detection events, i.e., events where the deposited energy from one photon is substantially localized in a single pixel, we establish ∼20% quantum efficiency at 2.6 keV with ∼190 eV resolution and a 100 kHz maximum detection rate. The detector platform’s useful intrinsic energy resolution, 5-μm pixel size, ease of use, and obvious potential for parallelization make it a promising candidate for many applications at synchrotron facilities, in laser-heating plasma physics studies, and in laboratory-based x-ray spectrometry.

Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

Science.gov (United States)

Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

2014-10-28

The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

CMOS circuit design, layout and simulation

CERN Document Server

Baker, R Jacob

2010-01-01

The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

Semiconductor

International Nuclear Information System (INIS)

2000-01-01

This book deals with process and measurement of semiconductor. It contains 20 chapters, which goes as follows; semiconductor industry, introduction of semiconductor manufacturing, yield of semiconductor process, materials, crystal growth and a wafer forming, PN, control pollution, oxidation, photomasking photoresist chemistry, photomasking technologies, diffusion and ion injection, chemical vapor deposition, metallization, wafer test and way of evaluation, semiconductor elements, integrated circuit and semiconductor circuit technology.

A high-performance complementary inverter based on transition metal dichalcogenide field-effect transistors.

Science.gov (United States)

Cho, Ah-Jin; Park, Kee Chan; Kwon, Jang-Yeon

2015-01-01

For several years, graphene has been the focus of much attention due to its peculiar characteristics, and it is now considered to be a representative 2-dimensional (2D) material. Even though many research groups have studied on the graphene, its intrinsic nature of a zero band-gap, limits its use in practical applications, particularly in logic circuits. Recently, transition metal dichalcogenides (TMDs), which are another type of 2D material, have drawn attention due to the advantage of having a sizable band-gap and a high mobility. Here, we report on the design of a complementary inverter, one of the most basic logic elements, which is based on a MoS2 n-type transistor and a WSe2 p-type transistor. The advantages provided by the complementary metal-oxide-semiconductor (CMOS) configuration and the high-performance TMD channels allow us to fabricate a TMD complementary inverter that has a high-gain of 13.7. This work demonstrates the operation of the MoS2 n-FET and WSe2 p-FET on the same substrate, and the electrical performance of the CMOS inverter, which is based on a different driving current, is also measured.

Sol-Gel Zinc Oxide Humidity Sensors Integrated with a Ring Oscillator Circuit On-a-Chip

Directory of Open Access Journals (Sweden)

Ming-Zhi Yang

2014-10-01

Full Text Available The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

A molybdenum disulfide/carbon nanotube heterogeneous complementary inverter.

Science.gov (United States)

Huang, Jun; Somu, Sivasubramanian; Busnaina, Ahmed

2012-08-24

We report a simple, bottom-up/top-down approach for integrating drastically different nanoscale building blocks to form a heterogeneous complementary inverter circuit based on layered molybdenum disulfide and carbon nanotube (CNT) bundles. The fabricated CNT/MoS(2) inverter is composed of n-type molybdenum disulfide (MOS(2)) and p-type CNT transistors, with a high voltage gain of 1.3. The CNT channels are fabricated using directed assembly while the layered molybdenum disulfide channels are fabricated by mechanical exfoliation. This bottom-up fabrication approach for integrating various nanoscale elements with unique characteristics provides an alternative cost-effective methodology to complementary metal-oxide-semiconductors, laying the foundation for the realization of high performance logic circuits.

Metal semiconductor contacts and devices

CERN Document Server

Cohen, Simon S; Einspruch, Norman G

1986-01-01

VLSI Electronics Microstructure Science, Volume 13: Metal-Semiconductor Contacts and Devices presents the physics, technology, and applications of metal-semiconductor barriers in digital integrated circuits. The emphasis is placed on the interplay among the theory, processing, and characterization techniques in the development of practical metal-semiconductor contacts and devices.This volume contains chapters that are devoted to the discussion of the physics of metal-semiconductor interfaces and its basic phenomena; fabrication procedures; and interface characterization techniques, particularl

High Performance Complementary Circuits Based on p-SnO and n-IGZO Thin-Film Transistors

Directory of Open Access Journals (Sweden)

Jiawei Zhang

2017-03-01

Full Text Available Oxide semiconductors are regarded as promising materials for large-area and/or flexible electronics. In this work, a ring oscillator based on n-type indium-gallium-zinc-oxide (IGZO and p-type tin monoxide (SnO is presented. The IGZO thin-film transistor (TFT shows a linear mobility of 11.9 cm2/(V∙s and a threshold voltage of 12.2 V. The SnO TFT exhibits a mobility of 0.51 cm2/(V∙s and a threshold voltage of 20.1 V which is suitable for use with IGZO TFTs to form complementary circuits. At a supply voltage of 40 V, the complementary inverter shows a full output voltage swing and a gain of 24 with both TFTs having the same channel length/channel width ratio. The three-stage ring oscillator based on IGZO and SnO is able to operate at 2.63 kHz and the peak-to-peak oscillation amplitude reaches 36.1 V at a supply voltage of 40 V. The oxide-based complementary circuits, after further optimization of the operation voltage, may have wide applications in practical large-area flexible electronics.

High Performance Complementary Circuits Based on p-SnO and n-IGZO Thin-Film Transistors.

Science.gov (United States)

Zhang, Jiawei; Yang, Jia; Li, Yunpeng; Wilson, Joshua; Ma, Xiaochen; Xin, Qian; Song, Aimin

2017-03-21

Oxide semiconductors are regarded as promising materials for large-area and/or flexible electronics. In this work, a ring oscillator based on n-type indium-gallium-zinc-oxide (IGZO) and p-type tin monoxide (SnO) is presented. The IGZO thin-film transistor (TFT) shows a linear mobility of 11.9 cm²/(V∙s) and a threshold voltage of 12.2 V. The SnO TFT exhibits a mobility of 0.51 cm²/(V∙s) and a threshold voltage of 20.1 V which is suitable for use with IGZO TFTs to form complementary circuits. At a supply voltage of 40 V, the complementary inverter shows a full output voltage swing and a gain of 24 with both TFTs having the same channel length/channel width ratio. The three-stage ring oscillator based on IGZO and SnO is able to operate at 2.63 kHz and the peak-to-peak oscillation amplitude reaches 36.1 V at a supply voltage of 40 V. The oxide-based complementary circuits, after further optimization of the operation voltage, may have wide applications in practical large-area flexible electronics.

CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

Energy Technology Data Exchange (ETDEWEB)

Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

2000-08-10

In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

Highly stable and imperceptible electronics utilizing photoactivated heterogeneous sol-gel metal-oxide dielectrics and semiconductors.

Science.gov (United States)

Jo, Jeong-Wan; Kim, Jaekyun; Kim, Kyung-Tae; Kang, Jin-Gu; Kim, Myung-Gil; Kim, Kwang-Ho; Ko, Hyungduk; Kim, Jiwan; Kim, Yong-Hoon; Park, Sung Kyu

2015-02-18

Incorporation of Zr into an AlOx matrix generates an intrinsically activated ZAO surface enabling the formation of a stable semiconducting IGZO film and good interfacial properties. Photochemically annealed metal-oxide devices and circuits with the optimized sol-gel ZAO dielectric and IGZO semiconductor layers demonstrate the high performance and electrically/mechanically stable operation of flexible electronics fabricated via a low-temperature solution process. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A complementary MOS process

International Nuclear Information System (INIS)

Jhabvala, M.D.

1977-03-01

The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated circuits is described. The fixed-gate array concept is presented as a means of obtaining CMOS integrated circuits in a fast and reliable fashion. Examples of CMOS circuits fabricated by both the conventional method and the fixed-gate array method are included. The electrical parameter specifications and characteristics are given along with typical values used to produce CMOS circuits. Temperature-bias stressing data illustrating the thermal stability of devices manufactured by this process are presented. Results of a preliminary study on the radiation sensitivity of circuits manufactured by this process are discussed. Some process modifications are given which have improved the radiation hardness of our CMOS devices. A formula description of the chemicals and gases along with the gas flow rates is also included

Ultrasonic fingerprint sensor using a piezoelectric micromachined ultrasonic transducer array integrated with complementary metal oxide semiconductor electronics

Energy Technology Data Exchange (ETDEWEB)

Lu, Y.; Fung, S.; Wang, Q.; Horsley, D. A. [Berkeley Sensor and Actuator Center, University of California, Davis, 1 Shields Avenue, Davis, California 95616 (United States); Tang, H.; Boser, B. E. [Berkeley Sensor and Actuator Center, University of California, Berkeley, California 94720 (United States); Tsai, J. M.; Daneman, M. [InvenSense, Inc., 1745 Technology Drive, San Jose, California 95110 (United States)

2015-06-29

This paper presents an ultrasonic fingerprint sensor based on a 24 × 8 array of 22 MHz piezoelectric micromachined ultrasonic transducers (PMUTs) with 100 μm pitch, fully integrated with 180 nm complementary metal oxide semiconductor (CMOS) circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. The array frequency response and vibration mode-shape were characterized using laser Doppler vibrometry and verified via finite element method simulation. The array's acoustic output was measured using a hydrophone to be ∼14 kPa with a 28 V input, in reasonable agreement with predication from analytical calculation. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20 × 8 sub-array, resulting in 300 mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D polydimethylsiloxane fingerprint phantom (10 mm × 8 mm) at a 1.2 mm distance from the array.

Oxide bipolar electronics: materials, devices and circuits

International Nuclear Information System (INIS)

Grundmann, Marius; Klüpfel, Fabian; Karsthof, Robert; Schlupp, Peter; Schein, Friedrich-Leonhard; Splith, Daniel; Yang, Chang; Bitter, Sofie; Von Wenckstern, Holger

2016-01-01

We present the history of, and the latest progress in, the field of bipolar oxide thin film devices. As such we consider primarily pn-junctions in which at least one of the materials is a metal oxide semiconductor. A wide range of n-type and p-type oxides has been explored for the formation of such bipolar diodes. Since most oxide semiconductors are unipolar, challenges and opportunities exist with regard to the formation of heterojunction diodes and band lineups. Recently, various approaches have led to devices with high rectification, namely p-type ZnCo 2 O 4 and NiO on n-type ZnO and amorphous zinc-tin-oxide. Subsequent bipolar devices and applications such as photodetectors, solar cells, junction field-effect transistors and integrated circuits like inverters and ring oscillators are discussed. The tremendous progress shows that bipolar oxide electronics has evolved from the exploration of various materials and heterostructures to the demonstration of functioning integrated circuits. Therefore a viable, facile and high performance technology is ready for further exploitation and performance optimization. (topical review)

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

Science.gov (United States)

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

Science.gov (United States)

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Design of nanophotonic, hot-electron solar-blind ultraviolet detectors with a metal-oxide-semiconductor structure

International Nuclear Information System (INIS)

Wang, Zhiyuan; Wang, Xiaoxin; Liu, Jifeng

2014-01-01

Solar-blind ultraviolet (UV) detection refers to photon detection specifically in the wavelength range of 200 nm–320 nm. Without background noises from solar radiation, it has broad applications from homeland security to environmental monitoring. The most commonly used solid state devices for this application are wide band gap (WBG) semiconductor photodetectors (Eg > 3.5 eV). However, WBG semiconductors are difficult to grow and integrate with Si readout integrated circuits (ROICs). In this paper, we design a nanophotonic metal-oxide-semiconductor structure on Si for solar-blind UV detectors. Instead of using semiconductors as the active absorber, we use Sn nano-grating structures to absorb UV photons and generate hot electrons for internal photoemission across the Sn/SiO 2 interfacial barrier, thereby generating photocurrent between the metal and the n-type Si region upon UV excitation. Moreover, the transported hot electron has an excess kinetic energy >3 eV, large enough to induce impact ionization and generate another free electron in the conduction band of n-Si. This process doubles the quantum efficiency. On the other hand, the large metal/oxide interfacial energy barrier (>3.5 eV) also enables solar-blind UV detection by blocking the less energetic electrons excited by visible photons. With optimized design, ∼75% UV absorption and hot electron excitation can be achieved within the mean free path of ∼20 nm from the metal/oxide interface. This feature greatly enhances hot electron transport across the interfacial barrier to generate photocurrent. The simple geometry of the Sn nano-gratings and the MOS structure make it easy to fabricate and integrate with Si ROICs compared to existing solar-blind UV detection schemes. The presented device structure also breaks through the conventional notion that photon absorption by metal is always a loss in solid-state photodetectors, and it can potentially be extended to other active metal photonic devices. (paper)

Training and operation of an integrated neuromorphic network based on metal-oxide memristors

Science.gov (United States)

Prezioso, M.; Merrikh-Bayat, F.; Hoskins, B. D.; Adam, G. C.; Likharev, K. K.; Strukov, D. B.

2015-05-01

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 1014 synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Metal-oxide-semiconductor devices based on epitaxial germanium-carbon layers grown directly on silicon substrates by ultra-high-vacuum chemical vapor deposition

Science.gov (United States)

Kelly, David Quest

After the integrated circuit was invented in 1959, complementary metal-oxide-semiconductor (CMOS) technology soon became the mainstay of the semiconductor industry. Silicon-based CMOS has dominated logic technologies for decades. During this time, chip performance has grown at an exponential rate at the cost of higher power consumption and increased process complexity. The performance gains have been made possible through scaling down circuit dimensions by improvements in lithography capabilities. Since scaling cannot continue forever, researchers have vigorously pursued new ways of improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) without having to shrink gate lengths and reduce the gate insulator thickness. Strained silicon, with its ability to boost transistor current by improving the channel mobility, is one of the methods that has already found its way into production. Although not yet in production, high-kappa dielectrics have also drawn wide interest in industry since they allow for the reduction of the electrical oxide thickness of the gate stack without having to reduce the physical thickness of the dielectric. Further out on the horizon is the incorporation of high-mobility materials such as germanium (Ge), silicon-germanium (Si1-xGe x), and the III-V semiconductors. Among the high-mobility materials, Ge has drawn the most attention because it has been shown to be compatible with high-kappa dielectrics and to produce high drive currents compared to Si. Among the most difficult challenges for integrating Ge on Si is finding a suitable method for reducing the number of crystal defects. The use of strain-relaxed Si1- xGex buffers has proven successful for reducing the threading dislocation density in Ge epitaxial layers, but questions remain as to the viability of this method in terms of cost and process complexity. This dissertation presents research on thin germanium-carbon (Ge 1-yCy layers on Si for the fabrication

Ultra-low power circuits based on tunnel FETs for energy harvesting applications

OpenAIRE

Cavalheiro, David

2017-01-01

There has been a tremendous evolution in integrated circuit technology in the past decades. With the scaling of complementary metal-oxide-semiconductor (CMOS) transistors, faster, less power consuming and more complex chips per unit area have made possible electronic gadgets to evolve to what we see today. The increasing demand in electronic portability imposes low power consumption as a key metric to analog and digital circuit design. While dynamic power consumption decreases quadraticall...

Positron studies of metal-oxide-semiconductor structures

Science.gov (United States)

Au, H. L.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

1993-03-01

Positron annihilation spectroscopy provides a new probe to study the properties of interface traps in metal-oxide semiconductors (MOS). Using positrons, we have examined the behavior of the interface traps as a function of gate bias. We propose a simple model to explain the positron annihilation spectra from the interface region of a MOS capacitor.

Plasmonic finite-thickness metal-semiconductor-metal waveguide as ultra-compact modulator

DEFF Research Database (Denmark)

Babicheva, Viktoriia; Malureanu, Radu; Lavrinenko, Andrei

2013-01-01

We propose a plasmonic waveguide with semiconductor gain material for optoelectronic integrated circuits. We analyze properties of a finite-thickness metal-semiconductor-metal (F-MSM) waveguide to be utilized as an ultra-compact and fast plasmonic modulator. The InP-based semiconductor core allows...

Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

Directory of Open Access Journals (Sweden)

Ching-Liang Dai

2010-03-01

Full Text Available The study presents a micro carbon monoxide (CO sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively.

Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

KAUST Repository

Wang, Zhenwei

2015-04-20

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

International Nuclear Information System (INIS)

Spathis, C.; Birbas, A.; Georgakopoulou, K.

2015-01-01

Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices

Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Spathis, C., E-mail: cspathis@ece.upatras.gr; Birbas, A.; Georgakopoulou, K. [Department of Electrical and Computer Engineering, University of Patras, Patras 26500 (Greece)

2015-08-15

Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

Directory of Open Access Journals (Sweden)

Paul C. McIntyre

2012-07-01

Full Text Available The literature on polar Gallium Nitride (GaN surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Feigenbaum scenario in the dynamics of a metal-oxide semiconductor heterostructure under harmonic perturbation. Golden mean criticality

International Nuclear Information System (INIS)

Cristescu, C.P.; Mereu, B.; Stan, Cristina; Agop, M.

2009-01-01

Experimental investigations and theoretical analysis on the dynamics of a metal-oxide semiconductor heterostructure used as nonlinear capacity in a series RLC electric circuit are presented. A harmonic voltage perturbation can induce various nonlinear behaviours, particularly evolution to chaos by period doubling and torus destabilization. In this work we focus on the change in dynamics induced by a sinusoidal driving with constant frequency and variable amplitude. Theoretical treatment based on the microscopic mechanisms involved led us to a dynamic system with a piecewise behaviour. Consequently, a model consisting of a nonlinear oscillator described by a piecewise second order ordinary differential equation is proposed. This kind of treatment is required by the asymmetry in the behaviour of the metal-oxide semiconductor with respect to the polarization of the perturbing voltage. The dynamics of the theoretical model is in good agreement with the experimental results. A connection with El Naschie's E-infinity space-time is established based on the interpretation of our experimental results as evidence of the importance of the golden mean criticality in the microscopic world.

Metal/oxide/semiconductor interface investigated by monoenergetic positrons

Science.gov (United States)

Uedono, A.; Tanigawa, S.; Ohji, Y.

1988-10-01

Variable-energy positron-beam studies have been carried out for the first time on a metal/oxide/semiconductor (MOS) structure of polycrystalline Si/SiO 2/Si-substrate. We were successful in collecting injected positrons at the SiO 2/Si interface by the application of an electric field between the MOS electrodes.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

Science.gov (United States)

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Triple inverter pierce oscillator circuit suitable for CMOS

Science.gov (United States)

Wessendorf,; Kurt, O [Albuquerque, NM

2007-02-27

An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

Graphene radio frequency receiver integrated circuit.

Science.gov (United States)

Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

2014-01-01

Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

A Wide-Range Tunable Level-Keeper Using Vertical Metal-Oxide-Semiconductor Field-Effect Transistors for Current-Reuse Systems

Science.gov (United States)

Tanoi, Satoru; Endoh, Tetsuo

2012-04-01

A wide-range tunable level-keeper using vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed for current-reuse analog systems. The design keys for widening tunable range of the operation are a two-path feed-back and a vertical MOSFET with back-bias-effect free. The proposed circuit with the vertical MOSFETs shows the 1.23-V tunable-range of the input level with the 2.4-V internal-supply voltage (VDD) in the simulation. This tunable-range of the proposed circuit is 4.7 times wider than that of the conventional. The achieved current efficiency of the proposed level-keeper is 66% at the 1.2-V output with the 2.4-V VDD. This efficiency of the proposed circuit is twice higher than that of the traditional voltage down converter.

Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon assisted tunneling

OpenAIRE

Koswatta, Siyuranga O.; Lundstrom, Mark S.; Nikonov, Dmitri E.

2007-01-01

Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the non-equilibrium Green's functions formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (Y. Lu et al, J. Am. Chem. Soc.,...

Reduction of Charge Traps and Stability Enhancement in Solution-Processed Organic Field-Effect Transistors Based on a Blended n-Type Semiconductor.

Science.gov (United States)

Campos, Antonio; Riera-Galindo, Sergi; Puigdollers, Joaquim; Mas-Torrent, Marta

2018-05-09

Solution-processed n-type organic field-effect transistors (OFETs) are essential elements for developing large-area, low-cost, and all organic logic/complementary circuits. Nonetheless, the development of air-stable n-type organic semiconductors (OSCs) lags behind their p-type counterparts. The trapping of electrons at the semiconductor-dielectric interface leads to a lower performance and operational stability. Herein, we report printed small-molecule n-type OFETs based on a blend with a binder polymer, which enhances the device stability due to the improvement of the semiconductor-dielectric interface quality and a self-encapsulation. Both combined effects prevent the fast deterioration of the OSC. Additionally, a complementary metal-oxide semiconductor-like inverter is fabricated depositing p-type and n-type OSCs simultaneously.

SEM evaluation of metallization on semiconductors. [Scanning Electron Microscope

Science.gov (United States)

Fresh, D. L.; Adolphsen, J. W.

1974-01-01

A test method for the evaluation of metallization on semiconductors is presented and discussed. The method has been prepared in MIL-STD format for submittal as a proposed addition to MIL-STD-883. It is applicable to discrete devices and to integrated circuits and specifically addresses batch-process oriented defects. Quantitative accept/reject criteria are given for contact windows, other oxide steps, and general interconnecting metallization. Figures are provided that illustrate typical types of defects. Apparatus specifications, sampling plans, and specimen preparation and examination requirements are described. Procedures for glassivated devices and for multi-metal interconnection systems are included.

Ultralow power complementary inverter circuits using axially doped p- and n-channel Si nanowire field effect transistors.

Science.gov (United States)

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2016-06-09

We have successfully synthesized axially doped p- and n-type regions on a single Si nanowire (NW). Diodes and complementary metal-oxide-semiconductor (CMOS) inverter devices using single axial p- and n-channel Si NW field-effect transistors (FETs) were fabricated. We show that the threshold voltages of both p- and n-channel Si NW FETs can be lowered to nearly zero by effectively controlling the doping concentration. Because of the high performance of the p- and n-type Si NW channel FETs, especially with regard to the low threshold voltage, the fabricated NW CMOS inverters have a low operating voltage (<3 V) while maintaining a high voltage gain (∼6) and ultralow static power dissipation (≤0.3 pW) at an input voltage of ±3 V. This result offers a viable way for the fabrication of a high-performance high-density logic circuit using a low-temperature fabrication process, which makes it suitable for flexible electronics.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

Science.gov (United States)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

Science.gov (United States)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Fabrication of integrated metallic MEMS devices

DEFF Research Database (Denmark)

Yalcinkaya, Arda Deniz; Ravnkilde, Jan Tue; Hansen, Ole

2002-01-01

A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators are characteri......A simple and complementary metal oxide semiconductor (CMOS) compatible fabrication technique for microelectromechanical (MEMS) devices is presented. The fabrication technology makes use of electroplated metal layers. Among the fabricated devices, high quality factor microresonators...

n-Channel semiconductor materials design for organic complementary circuits.

Science.gov (United States)

Usta, Hakan; Facchetti, Antonio; Marks, Tobin J

2011-07-19

emphasis on structure-property relationships. We then examine the synthesis and properties of carbonyl-functionalized oligomers, which constitute second-generation n-channel oligothiophenes, in both vacuum- and solution-processed FETs. These materials have high carrier mobilities and good air stability. In parallel, exceptionally electron-deficient cyano-functionalized arylenediimide derivatives are discussed as early examples of thermodynamically air-stable, high-performance n-channel semiconductors; they exhibit record electron mobilities of up to 0.64 cm(2)/V·s. Furthermore, we provide an overview of highly soluble ladder-type macromolecular semiconductors as OFET components, which combine ambient stability with solution processibility. A high electron mobility of 0.16 cm(2)/V·s is obtained under ambient conditions for solution-processed films. Finally, examples of polymeric n-channel semiconductors with electron mobilities as high as 0.85 cm(2)/V·s are discussed; these constitute an important advance toward fully printed polymeric electronic circuitry. Density functional theory (DFT) computations reveal important trends in molecular physicochemical and semiconducting properties, which, when combined with experimental data, shed new light on molecular charge transport characteristics. Our data provide the basis for a fundamental understanding of charge transport in high-performance n-channel organic semiconductors. Moreover, our results provide a road map for developing functional, complementary organic circuitry, which requires combining p- and n-channel transistors.

Determination of Insulator-to-Semiconductor Transition in Sol-Gel Oxide Semiconductors Using Derivative Spectroscopy.

Science.gov (United States)

Lee, Woobin; Choi, Seungbeom; Kim, Kyung Tae; Kang, Jingu; Park, Sung Kyu; Kim, Yong-Hoon

2015-12-23

We report a derivative spectroscopic method for determining insulator-to-semiconductor transition during sol-gel metal-oxide semiconductor formation. When an as-spun sol-gel precursor film is photochemically activated and changes to semiconducting state, the light absorption characteristics of the metal-oxide film is considerable changed particularly in the ultraviolet region. As a result, a peak is generated in the first-order derivatives of light absorption ( A' ) vs. wavelength (λ) plots, and by tracing the peak center shift and peak intensity, transition from insulating-to-semiconducting state of the film can be monitored. The peak generation and peak center shift are described based on photon-energy-dependent absorption coefficient of metal-oxide films. We discuss detailed analysis method for metal-oxide semiconductor films and its application in thin-film transistor fabrication. We believe this derivative spectroscopy based determination can be beneficial for a non-destructive and a rapid monitoring of the insulator-to-semiconductor transition in sol-gel oxide semiconductor formation.

Non-Stoichiometric SixN Metal-Oxide-Semiconductor Field-Effect Transistor for Compact Random Number Generator with 0.3 Mbit/s Generation Rate

Science.gov (United States)

Matsumoto, Mari; Ohba, Ryuji; Yasuda, Shin-ichi; Uchida, Ken; Tanamoto, Tetsufumi; Fujita, Shinobu

2008-08-01

The demand for random numbers for security applications is increasing. A conventional random number generator using thermal noise can generate unpredictable high-quality random numbers, but the circuit is extremely large because of large amplifier circuit for a small thermal signal. On the other hand, a pseudo-random number generator is small but the quality of randomness is bad. For a small circuit and a high quality of randomness, we purpose a non-stoichiometric SixN metal-oxide-semiconductor field-effect transistor (MOSFET) noise source device. This device generates a very large noise signal without an amplifier circuit. As a result, it is shown that, utilizing a SiN MOSFET, we can attain a compact random number generator with a high generation rate near 1 Mbit/s, which is suitable for almost all security applications.

Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

International Nuclear Information System (INIS)

Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

2016-01-01

This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

Potential of carbon nanotube field effect transistors for analogue circuits

KAUST Repository

Hayat, Khizar; Cheema, Hammad; Shamim, Atif

2013-01-01

This Letter presents a detailed comparison of carbon nanotube field effect transistors (CNFETs) and metal oxide semiconductor field effect transistors (MOSFETs) with special focus on carbon nanotube FET's potential for implementing analogue circuits in the mm-wave and sub-terahertz range. The latest CNFET lithographic dimensions place it at-par with complementary metal oxide semiconductor in terms of current handling capability, whereas the forecasted improvement in the lithography enables the CNFETs to handle more than twice the current of MOSFETs. The comparison of RF parameters shows superior performance of CNFETs with a g m , f T and f max of 2.7, 2.6 and 4.5 times higher, respectively. MOSFET- and CNFET-based inverter, three-stage ring oscillator and LC oscillator have been designed and compared as well. The CNFET-based inverters are found to be ten times faster, the ring oscillator demonstrates three times higher oscillation frequency and CNFET-based LC oscillator also shows improved performance than its MOSFET counterpart.

Potential of carbon nanotube field effect transistors for analogue circuits

KAUST Repository

Hayat, Khizar

2013-05-11

This Letter presents a detailed comparison of carbon nanotube field effect transistors (CNFETs) and metal oxide semiconductor field effect transistors (MOSFETs) with special focus on carbon nanotube FET\\'s potential for implementing analogue circuits in the mm-wave and sub-terahertz range. The latest CNFET lithographic dimensions place it at-par with complementary metal oxide semiconductor in terms of current handling capability, whereas the forecasted improvement in the lithography enables the CNFETs to handle more than twice the current of MOSFETs. The comparison of RF parameters shows superior performance of CNFETs with a g m , f T and f max of 2.7, 2.6 and 4.5 times higher, respectively. MOSFET- and CNFET-based inverter, three-stage ring oscillator and LC oscillator have been designed and compared as well. The CNFET-based inverters are found to be ten times faster, the ring oscillator demonstrates three times higher oscillation frequency and CNFET-based LC oscillator also shows improved performance than its MOSFET counterpart.

Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

KAUST Repository

Almuslem, A. S.; Hanna, Amir; Yapici, Tahir; Wehbe, N.; Diallo, Elhadj; Kutbee, Arwa T.; Bahabry, Rabab R.; Hussain, Muhammad Mustafa

2017-01-01

, in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured

All-semiconductor metamaterial-based optical circuit board at the microscale

International Nuclear Information System (INIS)

Min, Li; Huang, Lirong

2015-01-01

The newly introduced metamaterial-based optical circuit, an analogue of electronic circuit, is becoming a forefront topic in the fields of electronics, optics, plasmonics, and metamaterials. However, metals, as the commonly used plasmonic elements in an optical circuit, suffer from large losses at the visible and infrared wavelengths. We propose here a low-loss, all-semiconductor metamaterial-based optical circuit board at the microscale by using interleaved intrinsic GaAs and doped GaAs, and present the detailed design process for various lumped optical circuit elements, including lumped optical inductors, optical capacitors, optical conductors, and optical insulators. By properly combining these optical circuit elements and arranging anisotropic optical connectors, we obtain a subwavelength optical filter, which can always hold band-stop filtering function for various polarization states of the incident electromagnetic wave. All-semiconductor optical circuits may provide a new opportunity in developing low-power and ultrafast components and devices for optical information processing

Characterization of Interface State in Silicon Carbide Metal Oxide Semiconductor Capacitors

Science.gov (United States)

Kao, Wei-Chieh

Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system.

Mechanical anomaly impact on metal-oxide-semiconductor capacitors on flexible silicon fabric

KAUST Repository

Ghoneim, Mohamed T.; Kutbee, Arwa T.; Ghodsi Nasseri, Seyed Faizelldin; Bersuker, G.; Hussain, Muhammad Mustafa

2014-01-01

We report the impact of mechanical anomaly on high-κ/metal-oxide-semiconductor capacitors built on flexible silicon (100) fabric. The mechanical tests include studying the effect of bending radius up to 5 mm minimum bending radius with respect

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

International Nuclear Information System (INIS)

Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

2015-01-01

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

Energy Technology Data Exchange (ETDEWEB)

Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu [Department of Materials Science and Engineering, Beckman Institute for Advanced Science and Technology, and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 S Goodwin Ave., Urbana, Illinois 61801 (United States); Bozler, Carl [Lincoln Laboratory, Massachusetts Institute of Technology, 244 Wood Street, Lexington, Massachusetts 02420 (United States); Omenetto, Fiorenzo [Department of Biomedical Engineering, Department of Physics, Tufts University, 4 Colby St., Medford, Massachusetts 02155 (United States)

2015-01-05

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

Science.gov (United States)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Bipolar resistive switching in metal-insulator-semiconductor nanostructures based on silicon nitride and silicon oxide

Science.gov (United States)

Koryazhkina, M. N.; Tikhov, S. V.; Mikhaylov, A. N.; Belov, A. I.; Korolev, D. S.; Antonov, I. N.; Karzanov, V. V.; Gorshkov, O. N.; Tetelbaum, D. I.; Karakolis, P.; Dimitrakis, P.

2018-03-01

Bipolar resistive switching in metal-insulator-semiconductor (MIS) capacitor-like structures with an inert Au top electrode and a Si3N4 insulator nanolayer (6 nm thick) has been observed. The effect of a highly doped n +-Si substrate and a SiO2 interlayer (2 nm) is revealed in the changes in the semiconductor space charge region and small-signal parameters of parallel and serial equivalent circuit models measured in the high- and low-resistive capacitor states, as well as under laser illumination. The increase in conductivity of the semiconductor capacitor plate significantly reduces the charging and discharging times of capacitor-like structures.

Laser Doppler perfusion imaging with a complimentary metal oxide semiconductor image sensor

NARCIS (Netherlands)

Serov, Alexander; Steenbergen, Wiendelt; de Mul, F.F.M.

2002-01-01

We utilized a complimentary metal oxide semiconductor video camera for fast f low imaging with the laser Doppler technique. A single sensor is used for both observation of the area of interest and measurements of the interference signal caused by dynamic light scattering from moving particles inside

Active pixel sensor with intra-pixel charge transfer

Science.gov (United States)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2004-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Long-term research in Japan: amorphous metals, metal oxide varistors, high-power semiconductors and superconducting generators

Energy Technology Data Exchange (ETDEWEB)

Hane, G.J.; Yorozu, M.; Sogabe, T.; Suzuki, S.

1985-04-01

The review revealed that significant activity is under way in the research of amorphous metals, but that little fundamental work is being pursued on metal oxide varistors and high-power semiconductors. Also, the investigation of long-term research program plans for superconducting generators reveals that activity is at a low level, pending the recommendations of a study currently being conducted through Japan's Central Electric Power Council.

Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon

International Nuclear Information System (INIS)

Bory, Benjamin F.; Meskers, Stefan C. J.; Rocha, Paulo R. F.; Gomes, Henrique L.; Leeuw, Dago M. de

2015-01-01

Diodes incorporating a bilayer of an organic semiconductor and a wide bandgap metal oxide can show unipolar, non-volatile memory behavior after electroforming. The prolonged bias voltage stress induces defects in the metal oxide with an areal density exceeding 10 17  m −2 . We explain the electrical bistability by the coexistence of two thermodynamically stable phases at the interface between an organic semiconductor and metal oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with a low work function constitute current filaments. The phase composition and critical temperature are derived from a 2D Ising model as a function of chemical potential. The model predicts filamentary conduction exhibiting a negative differential resistance and nonvolatile memory behavior. The model is expected to be generally applicable to any bilayer system that shows unipolar resistive switching

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

2015-01-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles

Energy Technology Data Exchange (ETDEWEB)

Phelps, Tommy J.; Lauf, Robert J.; Moon, Ji-Won; Rondinone, Adam Justin; Love, Lonnie J.; Duty, Chad Edward; Madden, Andrew Stephen; Li, Yiliang; Ivanov, Ilia N.; Rawn, Claudia Jeanette

2017-09-19

The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction components to conditions conducive to microbially-mediated formation of non-oxide semiconductor nanoparticles, wherein said combination of reaction components comprises i) anaerobic microbes, ii) a culture medium suitable for sustaining said anaerobic microbes, iii) a metal component comprising at least one type of metal ion, iv) a non-metal component comprising at least one non-metal selected from the group consisting of S, Se, Te, and As, and v) one or more electron donors that provide donatable electrons to said anaerobic microbes during consumption of the electron donor by said anaerobic microbes; and (b) isolating said non-oxide semiconductor nanoparticles, which contain at least one of said metal ions and at least one of said non-metals. The invention is also directed to non-oxide semiconductor nanoparticle compositions produced as above and having distinctive properties.

Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles

Science.gov (United States)

Phelps, Tommy J.; Lauf, Robert J.; Moon, Ji Won; Rondinone, Adam J.; Love, Lonnie J.; Duty, Chad Edward; Madden, Andrew Stephen; Li, Yiliang; Ivanov, Ilia N.; Rawn, Claudia Jeanette

2014-06-24

The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction components to conditions conducive to microbially-mediated formation of non-oxide semiconductor nanoparticles, wherein said combination of reaction components comprises i) anaerobic microbes, ii) a culture medium suitable for sustaining said anaerobic microbes, iii) a metal component comprising at least one type of metal ion, iv) a non-metal component containing at least one non-metal selected from the group consisting of S, Se, Te, and As, and v) one or more electron donors that provide donatable electrons to said anaerobic microbes during consumption of the electron donor by said anaerobic microbes; and (b) isolating said non-oxide semiconductor nanoparticles, which contain at least one of said metal ions and at least one of said non-metals. The invention is also directed to non-oxide semiconductor nanoparticle compositions produced as above and having distinctive properties.

Average output polarization dataset for signifying the temperature influence for QCA designed reversible logic circuits.

Science.gov (United States)

Abdullah-Al-Shafi, Md; Bahar, Ali Newaz; Bhuiyan, Mohammad Maksudur Rahman; Shamim, S M; Ahmed, Kawser

2018-08-01

Quantum-dot cellular automata (QCA) as nanotechnology is a pledging contestant that has incredible prospective to substitute complementary metal-oxide-semiconductor (CMOS) because of its superior structures such as intensely high device thickness, minimal power depletion with rapid operation momentum. In this study, the dataset of average output polarization (AOP) for fundamental reversible logic circuits is organized as presented in (Abdullah-Al-Shafi and Bahar, 2017; Bahar et al., 2016; Abdullah-Al-Shafi et al., 2015; Abdullah-Al-Shafi, 2016) [1-4]. QCADesigner version 2.0.3 has been utilized to survey the AOP of reversible circuits at separate temperature point in Kelvin (K) unit.

Nano integrated circuit process

International Nuclear Information System (INIS)

Yoon, Yung Sup

2004-02-01

This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

Nano integrated circuit process

Energy Technology Data Exchange (ETDEWEB)

Yoon, Yung Sup

2004-02-15

This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

KAUST Repository

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, Mohamed N.; Wang, Q. X.; Alshareef, Husam N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling

An integrated semiconductor device enabling non-optical genome sequencing.

Science.gov (United States)

Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

2011-07-20

The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

Science.gov (United States)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Charge injection engineering of ambipolar field-effect transistors for high-performance organic complementary circuits.

Science.gov (United States)

Baeg, Kang-Jun; Kim, Juhwan; Khim, Dongyoon; Caironi, Mario; Kim, Dong-Yu; You, In-Kyu; Quinn, Jordan R; Facchetti, Antonio; Noh, Yong-Young

2011-08-01

Ambipolar π-conjugated polymers may provide inexpensive large-area manufacturing of complementary integrated circuits (CICs) without requiring micro-patterning of the individual p- and n-channel semiconductors. However, current-generation ambipolar semiconductor-based CICs suffer from higher static power consumption, low operation frequencies, and degraded noise margins compared to complementary logics based on unipolar p- and n-channel organic field-effect transistors (OFETs). Here, we demonstrate a simple methodology to control charge injection and transport in ambipolar OFETs via engineering of the electrical contacts. Solution-processed caesium (Cs) salts, as electron-injection and hole-blocking layers at the interface between semiconductors and charge injection electrodes, significantly decrease the gold (Au) work function (∼4.1 eV) compared to that of a pristine Au electrode (∼4.7 eV). By controlling the electrode surface chemistry, excellent p-channel (hole mobility ∼0.1-0.6 cm(2)/(Vs)) and n-channel (electron mobility ∼0.1-0.3 cm(2)/(Vs)) OFET characteristics with the same semiconductor are demonstrated. Most importantly, in these OFETs the counterpart charge carrier currents are highly suppressed for depletion mode operation (I(off) 0.1-0.2 mA). Thus, high-performance, truly complementary inverters (high gain >50 and high noise margin >75% of ideal value) and ring oscillators (oscillation frequency ∼12 kHz) based on a solution-processed ambipolar polymer are demonstrated.

Ionic behavior of organic-inorganic metal halide perovskite based metal-oxide-semiconductor capacitors.

Science.gov (United States)

Wang, Yucheng; Zhang, Yuming; Pang, Tiqiang; Xu, Jie; Hu, Ziyang; Zhu, Yuejin; Tang, Xiaoyan; Luan, Suzhen; Jia, Renxu

2017-05-24

Organic-inorganic metal halide perovskites are promising semiconductors for optoelectronic applications. Despite the achievements in device performance, the electrical properties of perovskites have stagnated. Ion migration is speculated to be the main contributing factor for the many unusual electrical phenomena in perovskite-based devices. Here, to understand the intrinsic electrical behavior of perovskites, we constructed metal-oxide-semiconductor (MOS) capacitors based on perovskite films and performed capacitance-voltage (C-V) and current-voltage (I-V) measurements of the capacitors. The results provide direct evidence for the mixed ionic-electronic transport behavior within perovskite films. In the dark, there is electrical hysteresis in both the C-V and I-V curves because the mobile negative ions take part in charge transport despite frequency modulation. However, under illumination, the large amount of photoexcited free carriers screens the influence of the mobile ions with a low concentration, which is responsible for the normal C-V properties. Validation of ion migration for the gate-control ability of MOS capacitors is also helpful for the investigation of perovskite MOS transistors and other gate-control photovoltaic devices.

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal oxide semiconductor molecular circuits

Science.gov (United States)

Masoumi, Massoud; Raissi, Farshid; Ahmadian, Mahmoud; Keshavarzi, Parviz

2006-01-01

We are proposing that the recently proposed semiconductor-nanowire-molecular architecture (CMOL) is an optimum platform to realize encryption algorithms. The basic modules for the advanced encryption standard algorithm (Rijndael) have been designed using CMOL architecture. The performance of this design has been evaluated with respect to chip area and speed. It is observed that CMOL provides considerable improvement over implementation with regular CMOS architecture even with a 20% defect rate. Pseudo-optimum gate placement and routing are provided for Rijndael building blocks and the possibility of designing high speed, attack tolerant and long key encryptions are discussed.

CMOS/SOS processing

Science.gov (United States)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto

2013-02-12

In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.

2013-01-01

In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

A Distance Detector with a Strip Magnetic MOSFET and Readout Circuit.

Science.gov (United States)

Sung, Guo-Ming; Lin, Wen-Sheng; Wang, Hsing-Kuang

2017-01-10

This paper presents a distance detector composed of two separated metal-oxide semiconductor field-effect transistors (MOSFETs), a differential polysilicon cross-shaped Hall plate (CSHP), and a readout circuit. The distance detector was fabricated using 0.18 μm 1P6M Complementary Metal-Oxide Semiconductor (CMOS) technology to sense the magnetic induction perpendicular to the chip surface. The differential polysilicon CSHP enabled the magnetic device to not only increase the magnetosensitivity but also eliminate the offset voltage generated because of device mismatch and Lorentz force. Two MOSFETs generated two drain currents with a quadratic function of the differential Hall voltages at CSHP. A readout circuit-composed of a current-to-voltage converter, a low-pass filter, and a difference amplifier-was designed to amplify the current difference between two drains of MOSFETs. Measurements revealed that the electrostatic discharge (ESD) could be eliminated from the distance sensor by grounding it to earth; however, the sensor could be desensitized by ESD in the absence of grounding. The magnetic influence can be ignored if the magnetic body (human) stays far from the magnetic sensor, and the measuring system is grounded to earth by using the ESD wrist strap (Strap E-GND). Both 'no grounding' and 'grounding to power supply' conditions were unsuitable for measuring the induced Hall voltage.

Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling.

Science.gov (United States)

Koswatta, Siyuranga O; Lundstrom, Mark S; Nikonov, Dmitri E

2007-05-01

Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the nonequilibrium Green's function formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (J. Am. Chem. Soc. 2006, 128, 3518-3519), we have obtained strong evidence that BTBT in CNT-MOSFETs is dominated by optical phonon assisted inelastic transport, which can have important implications on the transistor characteristics. It is shown that, under large biasing conditions, two-phonon scattering may also become important.

VLSI scaling methods and low power CMOS buffer circuit

International Nuclear Information System (INIS)

Sharma Vijay Kumar; Pattanaik Manisha

2013-01-01

Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

Simulation of pulsed-ionizing-radiation-induced errors in CMOS memory circuits

International Nuclear Information System (INIS)

Massengill, L.W.

1987-01-01

Effects of transient ionizing radiation on complementary metal-oxide-semiconductor (CMOS) memory circuits was studied by computer simulation. Simulation results have uncovered the dominant mechanism leading to information loss (upset) in dense (CMOS) circuits: rail span collapse. This effect is the catastrophic reduction in the local power supply at a RAM cell location due to the conglomerate radiation-induced photocurrents from all other RAM cells flowing through the power-supply-interconnect distribution. Rail-span collapse leads to reduced RAM cell-noise margins and can predicate upset. Results show that rail-span collapse in the dominant pulsed radiation effect in many memory circuits, preempting local circuit responses to the radiation. Several techniques to model power-supply noise, such as that arising from rail span collapse, are presented in this work. These include an analytical model for design optimization against these effects, a hierarchical computer-analysis technique for efficient power bus noise simulation in arrayed circuits, such as memories, and a complete circuit-simulation tool for noise margin analysis of circuits with arbitrary topologies

Circuit design techniques for non-crystalline semiconductors

CERN Document Server

Sambandan, Sanjiv

2012-01-01

Despite significant progress in materials and fabrication technologies related to non-crystalline semiconductors, fundamental drawbacks continue to limit real-world application of these devices in electronic circuits. To help readers deal with problems such as low mobility and intrinsic time variant behavior, Circuit Design Techniques for Non-Crystalline Semiconductors outlines a systematic design approach, including circuit theory, enabling users to synthesize circuits without worrying about the details of device physics. This book: Offers examples of how self-assembly can be used as a powerf

Mechanical anomaly impact on metal-oxide-semiconductor capacitors on flexible silicon fabric

KAUST Repository

Ghoneim, Mohamed T.

2014-06-09

We report the impact of mechanical anomaly on high-κ/metal-oxide-semiconductor capacitors built on flexible silicon (100) fabric. The mechanical tests include studying the effect of bending radius up to 5 mm minimum bending radius with respect to breakdown voltage and leakage current of the devices. We also report the effect of continuous mechanical stress on the breakdown voltage over extended periods of times.

Computer-aided engineering of semiconductor integrated circuits

Science.gov (United States)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

Basic mechanisms of radiation effects on electronic materials and devices

International Nuclear Information System (INIS)

Winokur, P.S.

1989-01-01

Many defense and nuclear reactor systems require complementary metal-oxide semiconductor integrated circuits that are tolerant to high levels of radiation. This radiation can result from space, hostile environments or nuclear reactor and accelerator beam environments. In addition, many techniques used to fabricate today's complex very-large-scale integration circuits expose the circuits to ionizing radiation during the process sequence. Whatever its origin, radiation can cause significant damage to integrated-circuit materials. This damage can lead to circuit performance degradation, logic upset, and even catastrophic circuit failure. This paper provides a brief overview of the basic mechanisms for radiation damage to silicon-based integrated circuits. Primary emphasis is on the effects of total-dose ionizing radiation on metal-oxide-semiconductor (MOS) structures

Reconfigurable Complementary Monolayer MoTe2 Field-Effect Transistors for Integrated Circuits.

Science.gov (United States)

Larentis, Stefano; Fallahazad, Babak; Movva, Hema C P; Kim, Kyounghwan; Rai, Amritesh; Taniguchi, Takashi; Watanabe, Kenji; Banerjee, Sanjay K; Tutuc, Emanuel

2017-05-23

Transition metal dichalcogenides are of interest for next generation switches, but the lack of low resistance electron and hole contacts in the same material has hindered the development of complementary field-effect transistors and circuits. We demonstrate an air-stable, reconfigurable, complementary monolayer MoTe 2 field-effect transistor encapsulated in hexagonal boron nitride, using electrostatically doped contacts. The introduction of a multigate design with prepatterned bottom contacts allows us to independently achieve low contact resistance and threshold voltage tuning, while also decoupling the Schottky contacts and channel gating. We illustrate a complementary inverter and a p-i-n diode as potential applications.

MOSFET analog memory circuit achieves long duration signal storage

Science.gov (United States)

1966-01-01

Memory circuit maintains the signal voltage at the output of an analog signal amplifier when the input signal is interrupted or removed. The circuit uses MOSFET /Metal Oxide Semiconductor Field Effect Transistor/ devices as voltage-controlled switches, triggered by an external voltage-sensing device.

Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations

Directory of Open Access Journals (Sweden)

Marco Lanuzza

2011-04-01

Full Text Available Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits. Five well known adder circuits were designed exploiting an industrial 45 nm static complementary metal-oxide semiconductor (CMOS standard cell library. The designed adders were comparatively evaluated under different energy constraints. As a main result, the performed analysis demonstrates that, for a given energy budget, simpler circuits (which are conventionally identified as low-energy slow architectures operating at higher power supply voltages can achieve a timing yield significantly better than more complex faster adders when used in low-power design with supply voltages lower than nominal.

Amphoteric oxide semiconductors for energy conversion devices: a tutorial review.

Science.gov (United States)

Singh, Kalpana; Nowotny, Janusz; Thangadurai, Venkataraman

2013-03-07

In this tutorial review, we discuss the defect chemistry of selected amphoteric oxide semiconductors in conjunction with their significant impact on the development of renewable and sustainable solid state energy conversion devices. The effect of electronic defect disorders in semiconductors appears to control the overall performance of several solid-state ionic devices that include oxide ion conducting solid oxide fuel cells (O-SOFCs), proton conducting solid oxide fuel cells (H-SOFCs), batteries, solar cells, and chemical (gas) sensors. Thus, the present study aims to assess the advances made in typical n- and p-type metal oxide semiconductors with respect to their use in ionic devices. The present paper briefly outlines the key challenges in the development of n- and p-type materials for various applications and also tries to present the state-of-the-art of defect disorders in technologically related semiconductors such as TiO(2), and perovskite-like and fluorite-type structure metal oxides.

Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

KAUST Repository

Nayak, Pradipta K.

2014-04-14

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

Design of organic complementary circuits and systems on foil

CERN Document Server

Abdinia, Sahel; Cantatore, Eugenio

2015-01-01

This book describes new approaches to fabricate complementary organic electronics, and focuses on the design of circuits and practical systems created using these manufacturing approaches. The authors describe two state-of-the-art, complementary organic technologies, characteristics and modeling of their transistors and their capability to implement circuits and systems on foil. Readers will benefit from the valuable overview of the challenges and opportunities that these extremely innovative technologies provide. ·         Demonstrates first circuits implemented using specific complementary organic technologies, including first printed analog to digital converter, first dynamic logic on foil and largest complementary organic circuit ·         Includes step-by-step design from single transistor level to complete systems on foil ·         Provides a platform for comparing state-of-the-art complementary organic technologies and for comparing these with other similar technologies, spec...

Dual passivation of intrinsic defects at the compound semiconductor/oxide interface using an oxidant and a reductant.

Science.gov (United States)

Kent, Tyler; Chagarov, Evgeniy; Edmonds, Mary; Droopad, Ravi; Kummel, Andrew C

2015-05-26

Studies have shown that metal oxide semiconductor field-effect transistors fabricated utilizing compound semiconductors as the channel are limited in their electrical performance. This is attributed to imperfections at the semiconductor/oxide interface which cause electronic trap states, resulting in inefficient modulation of the Fermi level. The physical origin of these states is still debated mainly because of the difficulty in assigning a particular electronic state to a specific physical defect. To gain insight into the exact source of the electronic trap states, density functional theory was employed to model the intrinsic physical defects on the InGaAs (2 × 4) surface and to model the effective passivation of these defects by utilizing both an oxidant and a reductant to eliminate metallic bonds and dangling-bond-induced strain at the interface. Scanning tunneling microscopy and spectroscopy were employed to experimentally determine the physical and electronic defects and to verify the effectiveness of dual passivation with an oxidant and a reductant. While subsurface chemisorption of oxidants on compound semiconductor substrates can be detrimental, it has been shown theoretically and experimentally that oxidants are critical to removing metallic defects at oxide/compound semiconductor interfaces present in nanoscale channels, oxides, and other nanostructures.

High Performance Electronics on Flexible Silicon

KAUST Repository

Sevilla, Galo T.

2016-09-01

Over the last few years, flexible electronic systems have gained increased attention from researchers around the world because of their potential to create new applications such as flexible displays, flexible energy harvesters, artificial skin, and health monitoring systems that cannot be integrated with conventional wafer based complementary metal oxide semiconductor processes. Most of the current efforts to create flexible high performance devices are based on the use of organic semiconductors. However, inherent material\\'s limitations make them unsuitable for big data processing and high speed communications. The objective of my doctoral dissertation is to develop integration processes that allow the transformation of rigid high performance electronics into flexible ones while maintaining their performance and cost. In this work, two different techniques to transform inorganic complementary metal-oxide-semiconductor electronics into flexible ones have been developed using industry compatible processes. Furthermore, these techniques were used to realize flexible discrete devices and circuits which include metal-oxide-semiconductor field-effect-transistors, the first demonstration of flexible Fin-field-effect-transistors, and metal-oxide-semiconductors-based circuits. Finally, this thesis presents a new technique to package, integrate, and interconnect flexible high performance electronics using low cost additive manufacturing techniques such as 3D printing and inkjet printing. This thesis contains in depth studies on electrical, mechanical, and thermal properties of the fabricated devices.

An acetone microsensor with a ring oscillator circuit fabricated using the commercial 0.18 μm CMOS process.

Science.gov (United States)

Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

2014-07-17

This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm.

Signatures of Quantized Energy States in Solution-Processed Ultrathin Layers of Metal-Oxide Semiconductors and Their Devices

KAUST Repository

Labram, John G.; Lin, Yenhung; Zhao, Kui; Li, Ruipeng; Thomas, Stuart R.; Semple, James; Androulidaki, Maria; Sygellou, Lamprini; McLachlan, Martyn A.; Stratakis, Emmanuel; Amassian, Aram; Anthopoulos, Thomas D.

2015-01-01

reports of the growth of uniform, ultrathin (<5 nm) metal-oxide semiconductors from solution, however, have potentially opened the door to such phenomena manifesting themselves. Here, a theoretical framework is developed for energy quantization

Adjusting the Parameters of Metal Oxide Gapless Surge Arresters’ Equivalent Circuits Using the Harmony Search Method

Directory of Open Access Journals (Sweden)

Christos A. Christodoulou

2017-12-01

Full Text Available The appropriate circuit modeling of metal oxide gapless surge arresters is critical for insulation coordination studies. Metal oxide arresters present a dynamic behavior for fast front surges; namely, their residual voltage is dependent on the peak value, as well as the duration of the injected impulse current, and should therefore not only be represented by non-linear elements. The aim of the current work is to adjust the parameters of the most frequently used surge arresters’ circuit models by considering the magnitude of the residual voltage, as well as the dissipated energy for given pulses. In this aim, the harmony search method is implemented to adjust parameter values of the arrester equivalent circuit models. This functions by minimizing a defined objective function that compares the simulation outcomes with the manufacturer’s data and the results obtained from previous methodologies.

Lithography for enabling advances in integrated circuits and devices.

Science.gov (United States)

Garner, C Michael

2012-08-28

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

Science.gov (United States)

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

Science.gov (United States)

Nakazato, Kazuo

2014-03-28

By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

Molecular-beam-deposited yttrium-oxide dielectrics in aluminum-gated metal - oxide - semiconductor field-effect transistors: Effective electron mobility

International Nuclear Information System (INIS)

Ragnarsson, L.-A degree.; Guha, S.; Copel, M.; Cartier, E.; Bojarczuk, N. A.; Karasinski, J.

2001-01-01

We report on high effective mobilities in yttrium-oxide-based n-channel metal - oxide - semiconductor field-effect transistors (MOSFETs) with aluminum gates. The yttrium oxide was grown in ultrahigh vacuum using a reactive atomic-beam-deposition system. Medium-energy ion-scattering studies indicate an oxide with an approximate composition of Y 2 O 3 on top of a thin layer of interfacial SiO 2 . The thickness of this interfacial oxide as well as the effective mobility are found to be dependent on the postgrowth anneal conditions. Optimum conditions result in mobilities approaching that of SiO 2 -based MOSFETs at higher fields with peak mobilities at approximately 210 cm 2 /Vs. [copyright] 2001 American Institute of Physics

Wafer-scale laser pantography: Fabrication of n-metal-oxide-semiconductor transistors and small-scale integrated circuits by direct-write laser-induced pyrolytic reactions

International Nuclear Information System (INIS)

McWilliams, B.M.; Herman, I.P.; Mitlitsky, F.; Hyde, R.A.; Wood, L.L.

1983-01-01

A complete set of processes sufficient for manufacture of n-metal-oxide-semiconductor (n-MOS) transistors by a laser-induced direct-write process has been demonstrated separately, and integrated to yield functional transistors. Gates and interconnects were fabricated of various combinations of n-doped and intrinsic polysilicon, tungsten, and tungsten silicide compounds. Both 0.1-μm and 1-μm-thick gate oxides were micromachined with and without etchant gas, and the exposed p-Si [100] substrate was cleaned and, at times, etched. Diffusion regions were doped by laser-induced pyrolytic decomposition of phosphine followed by laser annealing. Along with the successful manufacture of working n-MOS transistors and a set of elementary digital logic gates, this letter reports the successful use of several laser-induced surface reactions that have not been reported previously

Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

International Nuclear Information System (INIS)

Kim, Y; Pham, C; Chang, J P

2015-01-01

This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal–oxide–semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the

Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

Science.gov (United States)

Fossum, Eric R. (Inventor); Nakamura, Junichi (Inventor); Kemeny, Sabrina E. (Inventor)

2005-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Direct observation of both contact and remote oxygen scavenging of GeO2 in a metal-oxide-semiconductor stack

International Nuclear Information System (INIS)

Fadida, S.; Shekhter, P.; Eizenberg, M.; Cvetko, D.; Floreano, L.; Verdini, A.; Nyns, L.; Van Elshocht, S.; Kymissis, I.

2014-01-01

In the path to incorporating Ge based metal-oxide-semiconductor into modern nano-electronics, one of the main issues is the oxide-semiconductor interface quality. Here, the reactivity of Ti on Ge stacks and the scavenging effect of Ti were studied using synchrotron X-ray photoelectron spectroscopy measurements, with an in-situ metal deposition and high resolution transmission electron microscopy imaging. Oxygen removal from the Ge surface was observed both in direct contact as well as remotely through an Al 2 O 3 layer. The scavenging effect was studied in situ at room temperature and after annealing. We find that the reactivity of Ti can be utilized for improved scaling of Ge based devices.

A metallic metal oxide (Ti5O9)-metal oxide (TiO2) nanocomposite as the heterojunction to enhance visible-light photocatalytic activity.

Science.gov (United States)

Li, L H; Deng, Z X; Xiao, J X; Yang, G W

2015-01-26

Coupling titanium dioxide (TiO2) with other semiconductors is a popular method to extend the optical response range of TiO2 and improve its photon quantum efficiency, as coupled semiconductors can increase the separation rate of photoinduced charge carriers in photocatalysts. Differing from normal semiconductors, metallic oxides have no energy gap separating occupied and unoccupied levels, but they can excite electrons between bands to create a high carrier mobility to facilitate kinetic charge separation. Here, we propose the first metallic metal oxide-metal oxide (Ti5O9-TiO2) nanocomposite as a heterojunction for enhancing the visible-light photocatalytic activity of TiO2 nanoparticles and we demonstrate that this hybridized TiO2-Ti5O9 nanostructure possesses an excellent visible-light photocatalytic performance in the process of photodegrading dyes. The TiO2-Ti5O9 nanocomposites are synthesized in one step using laser ablation in liquid under ambient conditions. The as-synthesized nanocomposites show strong visible-light absorption in the range of 300-800 nm and high visible-light photocatalytic activity in the oxidation of rhodamine B. They also exhibit excellent cycling stability in the photodegrading process. A working mechanism for the metallic metal oxide-metal oxide nanocomposite in the visible-light photocatalytic process is proposed based on first-principle calculations of Ti5O9. This study suggests that metallic metal oxides can be regarded as partners for metal oxide photocatalysts in the construction of heterojunctions to improve photocatalytic activity.

Driver Circuit For High-Power MOSFET's

Science.gov (United States)

Letzer, Kevin A.

1991-01-01

Driver circuit generates rapid-voltage-transition pulses needed to switch high-power metal oxide/semiconductor field-effect transistor (MOSFET) modules rapidly between full "on" and full "off". Rapid switching reduces time of overlap between appreciable current through and appreciable voltage across such modules, thereby increasing power efficiency.

Hysteresis phenomena at metal-semiconductor phase transformation in vanadium oxides

International Nuclear Information System (INIS)

Lanskaya, T.G.; Merkulov, I.A.; Chudnovski , F.A.

1978-01-01

The hysteresis phenomena during the metal-semiconductor phase transformation (MSPT) in vanadium oxides are investigated. It is shown experimentally that the hysteresis effects during MSPT in vanadium oxides are associated not only with the martensite nature of the transformation, but also with activation processes. It is shown that the hysteresis phenomena during MSPT may be described by the distribution function of microregions of the crystal in the phase transformation temperature T 0 and the coercive temperature Tsub(c). An experimental method for constructing this distribution function was worked out. An analysis of the experimental data shows that finely dispersed films are characterized by a wide range of values of T 0 and Tsub(c) (55 deg C 0 <65 deg C, 6 deg C< Tsub(c)<12 deg C). The peculiarities of the optical recording of information on monocrystal and finely dispersed films are considered

Modelling of Leakage Current Through Double Dielectric Gate Stack in Metal Oxide Semiconductor Capacitor

International Nuclear Information System (INIS)

Fatimah A Noor; Mikrajuddin Abdullah; Sukirno; Khairurrijal

2008-01-01

In this paper, we have derived analytical expression of leakage current through double barriers in Metal Oxide Semiconductor (MOS) capacitor. Initially, electron transmittance through the MOS capacitor was derived by including the coupling between the transverse and longitudinal energies. The transmittance was then employed to obtain leakage current through the double barrier. In this model, we observed the effect of electron velocity due to the coupling effect and the oxide thickness to the leakage current. The calculated results showed that the leakage current decreases as the electron velocity increases. (author)

A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

CERN Multimedia

2002-01-01

% RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

A memristor-based nonvolatile latch circuit

International Nuclear Information System (INIS)

Robinett, Warren; Pickett, Matthew; Borghetti, Julien; Xia Qiangfei; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2010-01-01

Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.

Characteristics of Superjunction Lateral-Double-Diffusion Metal Oxide Semiconductor Field Effect Transistor and Degradation after Electrical Stress

Science.gov (United States)

Lin, Jyh‑Ling; Lin, Ming‑Jang; Lin, Li‑Jheng

2006-04-01

The superjunction lateral double diffusion metal oxide semiconductor field effect has recently received considerable attention. Introducing heavily doped p-type strips to the n-type drift region increases the horizontal depletion capability. Consequently, the doping concentration of the drift region is higher and the conduction resistance is lower than those of conventional lateral-double-diffusion metal oxide semiconductor field effect transistors (LDMOSFETs). These characteristics may increase breakdown voltage (\\mathit{BV}) and reduce specific on-resistance (Ron,sp). In this study, we focus on the electrical characteristics of conventional LDMOSFETs on silicon bulk, silicon-on-insulator (SOI) LDMOSFETs and superjunction LDMOSFETs after bias stress. Additionally, the \\mathit{BV} and Ron,sp of superjunction LDMOSFETs with different N/P drift region widths and different dosages are discussed. Simulation tools, including two-dimensional (2-D) TSPREM-4/MEDICI and three-dimensional (3-D) DAVINCI, were employed to determine the device characteristics.

Air-stable complementary-like circuits based on organic ambipolar transistors

NARCIS (Netherlands)

Anthopoulos, Thomas D.; Setayesh, Sepas; Smits, Edsger; Cantatore, Eugenio; Boer ,de Bert; Blom, Paul W. M.; de Leeuw, Dago M.; Cölle, Michael

2006-01-01

Air stable complementary-like circuits, such as voltage inverters (see figure) and ring oscillators, are fabricated using ambipolar organic transistors based on a nickel dithiolene derivative. In addition to the complementary-like character of the circuits, the technology is very simple and fully

A power management system for energy harvesting and wireless sensor networks application based on a novel charge pump circuit

Science.gov (United States)

Aloulou, R.; De Peslouan, P.-O. Lucas; Mnif, H.; Alicalapa, F.; Luk, J. D. Lan Sun; Loulou, M.

2016-05-01

Energy Harvesting circuits are developed as an alternative solution to supply energy to autonomous sensor nodes in Wireless Sensor Networks. In this context, this paper presents a micro-power management system for multi energy sources based on a novel design of charge pump circuit to allow the total autonomy of self-powered sensors. This work proposes a low-voltage and high performance charge pump (CP) suitable for implementation in standard complementary metal oxide semiconductor (CMOS) technologies. The CP design was implemented using Cadence Virtuoso with AMS 0.35μm CMOS technology parameters. Its active area is 0.112 mm2. Consistent results were obtained between the measured findings of the chip testing and the simulation results. The circuit can operate with an 800 mV supply and generate a boosted output voltage of 2.835 V with 1 MHz as frequency.

Solar hydrogen production with semiconductor metal oxides: new directions in experiment and theory

DEFF Research Database (Denmark)

Valdes, Alvaro; Brillet, Jeremie; Graetzel, Michael

2012-01-01

An overview of a collaborative experimental and theoretical effort toward efficient hydrogen production via photoelectrochemical splitting of water into di-hydrogen and di-oxygen is presented here. We present state-of-the-art experimental studies using hematite and TiO2 functionalized with gold n...... nanoparticles as photoanode materials, and theoretical studies on electro and photo-catalysis of water on a range of metal oxide semiconductor materials, including recently developed implementation of self-interaction corrected energy functionals....

Semiconductor Metal-Organic Frameworks: Future Low-Bandgap Materials.

Science.gov (United States)

Usman, Muhammad; Mendiratta, Shruti; Lu, Kuang-Lieh

2017-02-01

Metal-organic frameworks (MOFs) with low density, high porosity, and easy tunability of functionality and structural properties, represent potential candidates for use as semiconductor materials. The rapid development of the semiconductor industry and the continuous miniaturization of feature sizes of integrated circuits toward the nanometer (nm) scale require novel semiconductor materials instead of traditional materials like silicon, germanium, and gallium arsenide etc. MOFs with advantageous properties of both the inorganic and the organic components promise to serve as the next generation of semiconductor materials for the microelectronics industry with the potential to be extremely stable, cheap, and mechanically flexible. Here, a perspective of recent research is provided, regarding the semiconducting properties of MOFs, bandgap studies, and their potential in microelectronic devices. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Low-Power Photoplethysmogram Acquisition Integrated Circuit with Robust Light Interference Compensation.

Science.gov (United States)

Kim, Jongpal; Kim, Jihoon; Ko, Hyoungho

2015-12-31

To overcome light interference, including a large DC offset and ambient light variation, a robust photoplethysmogram (PPG) readout chip is fabricated using a 0.13-μm complementary metal-oxide-semiconductor (CMOS) process. Against the large DC offset, a saturation detection and current feedback circuit is proposed to compensate for an offset current of up to 30 μA. For robustness against optical path variation, an automatic emitted light compensation method is adopted. To prevent ambient light interference, an alternating sampling and charge redistribution technique is also proposed. In the proposed technique, no additional power is consumed, and only three differential switches and one capacitor are required. The PPG readout channel consumes 26.4 μW and has an input referred current noise of 260 pArms.

Nonvolatile memory characteristics in metal-oxide-semiconductors containing metal nanoparticles fabricated by using a unique laser irradiation method

International Nuclear Information System (INIS)

Yang, JungYup; Yoon, KapSoo; Kim, JuHyung; Choi, WonJun; Do, YoungHo; Kim, ChaeOk; Hong, JinPyo

2006-01-01

Metal-oxide-semiconductor (MOS) capacitors with metal nanoparticles (Co NP) were successfully fabricated by utilizing an external laser exposure technique for application of non-volatile memories. Images of high-resolution transmission electron microscopy reveal that the spherically shaped Co NP are clearly embedded in the gate oxide layer. Capacitance-voltage measurements exhibit typical charging and discharging effects with a large flat-band shift. The effects of the tunnel oxide thickness and the different tunnel materials are analyzed using capacitance-voltage and retention characteristics. In addition, the memory characteristics of the NP embedded in a high-permittivity material are investigated because the thickness of conventionally available SiO 2 gates is approaching the quantum tunneling limit as devices are scaled down. Finally, the suitability of NP memory devices for nonvolatile memory applications is also discussed. The present results suggest that our unique laser exposure technique holds promise for the NP formation as floating gate elements in nonvolatile NP memories and that the quality of the tunnel oxide is very important for enhancing the retention properties of nonvolatile memory.

Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

KAUST Repository

Almuslem, A. S.

2017-02-14

In the recent past, with the advent of transient electronics for mostly implantable and secured electronic applications, the whole field effect transistor structure has been dissolved in a variety of chemicals. Here, we show simple water soluble nano-scale (sub-10 nm) germanium oxide (GeO) as the dissolvable component to remove the functional structures of metal oxide semiconductor devices and then reuse the expensive germanium substrate again for functional device fabrication. This way, in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured and billions are disposed, which extend the harmful impact to our environment. Therefore, this is a key study to show a pragmatic approach for water soluble high performance electronics for environmentally friendly manufacturing and bioresorbable electronic applications.

Silicon carbide: A unique platform for metal-oxide-semiconductor physics

Energy Technology Data Exchange (ETDEWEB)

Liu, Gang [Institute for Advanced Materials, Devices and Nanotechnology, Rutgers University, Piscataway, New Jersey 08854 (United States); Tuttle, Blair R. [Department of Physics and Astronomy, Vanderbilt University, Nashville, Tennessee 37235 (United States); Dhar, Sarit [Department of Physics, Auburn University, Auburn, Alabama 36849 (United States)

2015-06-15

A sustainable energy future requires power electronics that can enable significantly higher efficiencies in the generation, distribution, and usage of electrical energy. Silicon carbide (4H-SiC) is one of the most technologically advanced wide bandgap semiconductor that can outperform conventional silicon in terms of power handling, maximum operating temperature, and power conversion efficiency in power modules. While SiC Schottky diode is a mature technology, SiC power Metal Oxide Semiconductor Field Effect Transistors are relatively novel and there is large room for performance improvement. Specifically, major initiatives are under way to improve the inversion channel mobility and gate oxide stability in order to further reduce the on-resistance and enhance the gate reliability. Both problems relate to the defects near the SiO{sub 2}/SiC interface, which have been the focus of intensive studies for more than a decade. Here we review research on the SiC MOS physics and technology, including its brief history, the state-of-art, and the latest progress in this field. We focus on the two main scientific problems, namely, low channel mobility and bias temperature instability. The possible mechanisms behind these issues are discussed at the device physics level as well as the atomic scale, with the support of published physical analysis and theoretical studies results. Some of the most exciting recent progress in interface engineering for improving the channel mobility and fundamental understanding of channel transport is reviewed.

A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

Institute of Scientific and Technical Information of China (English)

Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

2011-01-01

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (Ron,sp),whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region,is proposed.The theoretical limit of its Ron,sp is deduced,the influence of structure parameters on the breakdown voltage (BV) and Ron,sp are investigated,and the optimized results with BV of 83 V and Ron,sp of 54 mΩ.mm2 are obtained.Simulations show that the inhomogencous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET)has a superior “Ron,sp/BV” trade-off to the conventional VDMOS (a 38％ reduction of Ron,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10％ reduction of Ron,sp with the same BV).The inhomogeneous-floatingislands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET.Its reverse recovery peak current,reverse recovery time and reverse recovery charge are about 50,80 and 40％ of those of the superjunction MOSFET,respectively.

Electrical memory features of ferromagnetic CoFeAlSi nano-particles embedded in metal-oxide-semiconductor matrix

International Nuclear Information System (INIS)

Lee, Ja Bin; Kim, Ki Woong; Lee, Jun Seok; An, Gwang Guk; Hong, Jin Pyo

2011-01-01

Half-metallic Heusler material Co 2 FeAl 0.5 Si 0.5 (CFAS) nano-particles (NPs) embedded in metal-oxide-semiconductor (MOS) structures with thin HfO 2 tunneling and MgO control oxides were investigated. The CFAS NPs were prepared by rapid thermal annealing. The formation of well-controlled CFAS NPs on thin HfO 2 tunneling oxide was confirmed by atomic force microscopy (AFM). Memory characteristics of CFAS NPs in MOS devices exhibited a large memory window of 4.65 V, as well as good retention and endurance times of 10 5 cycles and 10 9 s, respectively, demonstrating the potential of CFAS NPs as promising candidates for use in charge storage.

Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

NARCIS (Netherlands)

Dutta, Satadal

2017-01-01

Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

Robust parameter design for integrated circuit fabrication procedure with respect to categorical characteristic

International Nuclear Information System (INIS)

Sohn, S.Y.

1999-01-01

We consider a robust parameter design of the process for forming contact windows in complementary metal-oxide semiconductor circuits. Robust design is often used to find the optimal levels of process conditions which would provide the output of consistent quality as close to a target value. In this paper, we analyze the results of the fractional factorial design of nine factors: mask dimension, viscosity, bake temperature, spin speed, bake time, aperture, exposure time, developing time, etch time, where the outcome of the experiment is measured in terms of a categorized window size with five categories. Random effect analysis is employed to model both the mean and variance of categorized window size as functions of some controllable factors as well as random errors. Empirical Bayes' procedures are then utilized to fit both the models, and to eventually find the robust design of CMOS circuit process by means of a Bootstrap resampling approach

Electrosprayed Metal Oxide Semiconductor Films for Sensitive and Selective Detection of Hydrogen Sulfide

Directory of Open Access Journals (Sweden)

Maryam Siadat

2009-11-01

Full Text Available Semiconductor metal oxide films of copper-doped tin oxide (Cu-SnO2, tungsten oxide (WO3 and indium oxide (In2O3 were deposited on a platinum coated alumina substrate employing the electrostatic spray deposition technique (ESD. The morphology studied with scanning electron microscopy (SEM and atomic force microscopy (AFM shows porous homogeneous films comprising uniformly distributed aggregates of nano particles. The X-ray diffraction technique (XRD proves the formation of crystalline phases with no impurities. Besides, the Raman cartographies provided information about the structural homogeneity. Some of the films are highly sensitive to low concentrations of H2S (10 ppm at low operating temperatures (100 and 200 °C and the best response in terms of Rair/Rgas is given by Cu-SnO2 films (2500 followed by WO3 (1200 and In2O3 (75. Moreover, all the films exhibit no cross-sensitivity to other reducing (SO2 or oxidizing (NO2 gases.

A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

Directory of Open Access Journals (Sweden)

Ming-Zhi Yang

2013-03-01

Full Text Available The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

A complementary and synergistic effect of Fe-Zn binary metal oxide in the process of high-temperature fuel gas desulfurization

Institute of Scientific and Technical Information of China (English)

翁斯灏; 吴幼青

1996-01-01

57Fe Mossbauer spectroscopy was used to investigate the evolution of Fe-Zn binary metal oxide sorbent in the process of high-temperature fuel gas desulfurization. The results of phase analyses show that Fe-Zn binary metal oxide sorbent is rapidly reduced in hot fuel gas and decomposed to new phases of highly dispersed microcrystalline elemental iron and zinc oxide, both of which become the active desulfurization constituents. A complementary and synergistic effect between active iron acting as a high sulfur capacity constituent and active zinc oxide acting as a deep refining desulfurization constituent exists in this type of sorbent for hot fuel gas desulfurization.

Hybrid complementary circuits based on p-channel organic and n-channel metal oxide transistors with balanced carrier mobilities of up to 10 cm2/Vs

KAUST Repository

Isakov, Ivan

2016-12-29

We report the development of hybrid complementary inverters based on p-channel organic and n-channel metal oxide thin-film transistors (TFTs) both processed from solution at <200 °C. For the organic TFTs, a ternary blend consisting of the small-molecule 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene, the polymer indacenodithiophene-benzothiadiazole (CIDT-BT) and the p-type dopant CF was employed, whereas the isotype InO/ZnO heterojunction was used for the n-channel TFTs. When integrated on the same substrate, p- and n-channel devices exhibited balanced carrier mobilities up to 10 cm/Vs. Hybrid complementary inverters based on these devices show high signal gain (>30 V/V) and wide noise margins (70%). The moderate processing temperatures employed and the achieved level of device performance highlight the tremendous potential of the technology for application in the emerging sector of large-area microelectronics.

Hybrid complementary circuits based on p-channel organic and n-channel metal oxide transistors with balanced carrier mobilities of up to 10 cm2/Vs

KAUST Repository

Isakov, Ivan; Paterson, Alexandra F.; Solomeshch, Olga; Tessler, Nir; Zhang, Qiang; Li, Jun; Zhang, Xixiang; Fei, Zhuping; Heeney, Martin; Anthopoulos, Thomas D.

2016-01-01

We report the development of hybrid complementary inverters based on p-channel organic and n-channel metal oxide thin-film transistors (TFTs) both processed from solution at <200 °C. For the organic TFTs, a ternary blend consisting of the small-molecule 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene, the polymer indacenodithiophene-benzothiadiazole (CIDT-BT) and the p-type dopant CF was employed, whereas the isotype InO/ZnO heterojunction was used for the n-channel TFTs. When integrated on the same substrate, p- and n-channel devices exhibited balanced carrier mobilities up to 10 cm/Vs. Hybrid complementary inverters based on these devices show high signal gain (>30 V/V) and wide noise margins (70%). The moderate processing temperatures employed and the achieved level of device performance highlight the tremendous potential of the technology for application in the emerging sector of large-area microelectronics.

Optically induced bistable states in metal/tunnel-oxide/semiconductor /MTOS/ junctions

Science.gov (United States)

Lai, S. K.; Dressendorfer, P. V.; Ma, T. P.; Barker, R. C.

1981-01-01

A new switching phenomenon in metal-oxide semiconductor tunnel junction has been discovered. With a sufficiently large negative bias applied to the electrode, incident visible light of intensity greater than about 1 microW/sq cm causes the reverse-biased junction to switch from a low-current to a high-current state. It is believed that hot-electron-induced impact ionization provides the positive feedback necessary for switching, and causes the junction to remain in its high-current state after the optical excitation is removed. The junction may be switched back to the low-current state electrically. The basic junction characteristics have been measured, and a simple model for the switching phenomenon has been developed.

Semiconductor integrated circuits

International Nuclear Information System (INIS)

Michel, A.E.; Schwenker, R.O.; Ziegler, J.F.

1979-01-01

An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

Science.gov (United States)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

Directory of Open Access Journals (Sweden)

Kyeonghwan Park

2017-04-01

Full Text Available This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

Science.gov (United States)

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

Semiconductors integrated circuit design for manufacturability

CERN Document Server

Balasinki, Artur

2011-01-01

Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

Signatures of Quantized Energy States in Solution-Processed Ultrathin Layers of Metal-Oxide Semiconductors and Their Devices

KAUST Repository

Labram, John G.

2015-02-13

Physical phenomena such as energy quantization have to-date been overlooked in solution-processed inorganic semiconducting layers, owing to heterogeneity in layer thickness uniformity unlike some of their vacuum-deposited counterparts. Recent reports of the growth of uniform, ultrathin (<5 nm) metal-oxide semiconductors from solution, however, have potentially opened the door to such phenomena manifesting themselves. Here, a theoretical framework is developed for energy quantization in inorganic semiconductor layers with appreciable surface roughness, as compared to the mean layer thickness, and present experimental evidence of the existence of quantized energy states in spin-cast layers of zinc oxide (ZnO). As-grown ZnO layers are found to be remarkably continuous and uniform with controllable thicknesses in the range 2-24 nm and exhibit a characteristic widening of the energy bandgap with reducing thickness in agreement with theoretical predictions. Using sequentially spin-cast layers of ZnO as the bulk semiconductor and quantum well materials, and gallium oxide or organic self-assembled monolayers as the barrier materials, two terminal electronic devices are demonstrated, the current-voltage characteristics of which resemble closely those of double-barrier resonant-tunneling diodes. As-fabricated all-oxide/hybrid devices exhibit a characteristic negative-differential conductance region with peak-to-valley ratios in the range 2-7.

A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

International Nuclear Information System (INIS)

Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

2011-01-01

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (R on,sp ), whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its R on,sp is deduced, the influence of structure parameters on the breakdown voltage (BV) and R on,sp are investigated, and the optimized results with BV of 83 V and R on,sp of 54 mΩ·mm 2 are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET) has a superior 'R on,sp /BV' trade-off to the conventional VDMOS (a 38% reduction of R on,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of R on,sp with the same BV). The inhomogeneous-floating-islands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively. (interdisciplinary physics and related areas of science and technology)

Spintronic effects in metallic, semiconductor, metal-oxide and metal-semiconductor heterostructures

Energy Technology Data Exchange (ETDEWEB)

Bratkovsky, A M [Hewlett-Packard Laboratories, 1501 Page Mill Road, MS 1123, Palo Alto, CA 94304 (United States)

2008-02-15

Spintronics is a rapidly growing field focusing on phenomena and related devices essentially dependent on spin transport. Some of them are already an established part of microelectronics. We review recent theoretical and experimental advances in achieving large spin injection efficiency (polarization of current) and accumulated spin polarization. These include tunnel and giant magnetoresistance, spin-torque and spin-orbit effects on electron transport in various heterostructures. We give a microscopic description of spin tunneling through oxide and modified Schottky barriers between a ferromagnet (FM) and a semiconductor (S). It is shown that in such FM-S junctions electrons with a certain spin projection can be efficiently injected into (or extracted from) S, while electrons with the opposite spin can accumulate in S near the interface. The criterion for efficient injection is opposite to a known Rashba criterion, since the barrier should be rather transparent. In degenerate semiconductors, extraction of spin can proceed at low temperatures. We mention a few novel spin-valve ultrafast devices with small dissipated power: a magnetic sensor, a spin transistor, an amplifier, a frequency multiplier, a square-law detector and a source of polarized radiation. We also discuss effects related to spin-orbital interactions, such as the spin Hall effect (SHE) and a recently predicted positive magnetoresistance accompanying SHE. Some esoteric devices such as 'spinFET', interacting spin logic and spin-based quantum computing are discussed and problems with their realization are highlighted. We demonstrate that the so-called 'ferroelectric tunnel junctions' are unlikely to provide additional functionality because in all realistic situations the ferroelectric barrier would be split into domains by the depolarizing field.

Spintronic effects in metallic, semiconductor, metal-oxide and metal-semiconductor heterostructures

International Nuclear Information System (INIS)

Bratkovsky, A M

2008-01-01

Spintronics is a rapidly growing field focusing on phenomena and related devices essentially dependent on spin transport. Some of them are already an established part of microelectronics. We review recent theoretical and experimental advances in achieving large spin injection efficiency (polarization of current) and accumulated spin polarization. These include tunnel and giant magnetoresistance, spin-torque and spin-orbit effects on electron transport in various heterostructures. We give a microscopic description of spin tunneling through oxide and modified Schottky barriers between a ferromagnet (FM) and a semiconductor (S). It is shown that in such FM-S junctions electrons with a certain spin projection can be efficiently injected into (or extracted from) S, while electrons with the opposite spin can accumulate in S near the interface. The criterion for efficient injection is opposite to a known Rashba criterion, since the barrier should be rather transparent. In degenerate semiconductors, extraction of spin can proceed at low temperatures. We mention a few novel spin-valve ultrafast devices with small dissipated power: a magnetic sensor, a spin transistor, an amplifier, a frequency multiplier, a square-law detector and a source of polarized radiation. We also discuss effects related to spin-orbital interactions, such as the spin Hall effect (SHE) and a recently predicted positive magnetoresistance accompanying SHE. Some esoteric devices such as 'spinFET', interacting spin logic and spin-based quantum computing are discussed and problems with their realization are highlighted. We demonstrate that the so-called 'ferroelectric tunnel junctions' are unlikely to provide additional functionality because in all realistic situations the ferroelectric barrier would be split into domains by the depolarizing field

Spintronic effects in metallic, semiconductor, metal oxide and metal semiconductor heterostructures

Science.gov (United States)

Bratkovsky, A. M.

2008-02-01

Spintronics is a rapidly growing field focusing on phenomena and related devices essentially dependent on spin transport. Some of them are already an established part of microelectronics. We review recent theoretical and experimental advances in achieving large spin injection efficiency (polarization of current) and accumulated spin polarization. These include tunnel and giant magnetoresistance, spin-torque and spin-orbit effects on electron transport in various heterostructures. We give a microscopic description of spin tunneling through oxide and modified Schottky barriers between a ferromagnet (FM) and a semiconductor (S). It is shown that in such FM-S junctions electrons with a certain spin projection can be efficiently injected into (or extracted from) S, while electrons with the opposite spin can accumulate in S near the interface. The criterion for efficient injection is opposite to a known Rashba criterion, since the barrier should be rather transparent. In degenerate semiconductors, extraction of spin can proceed at low temperatures. We mention a few novel spin-valve ultrafast devices with small dissipated power: a magnetic sensor, a spin transistor, an amplifier, a frequency multiplier, a square-law detector and a source of polarized radiation. We also discuss effects related to spin-orbital interactions, such as the spin Hall effect (SHE) and a recently predicted positive magnetoresistance accompanying SHE. Some esoteric devices such as 'spinFET', interacting spin logic and spin-based quantum computing are discussed and problems with their realization are highlighted. We demonstrate that the so-called 'ferroelectric tunnel junctions' are unlikely to provide additional functionality because in all realistic situations the ferroelectric barrier would be split into domains by the depolarizing field.

Physicochemical and Electrophysical Properties of Metal/Semiconductor Containing Nanostructured Composites

Science.gov (United States)

Gerasimov, G. N.; Gromov, V. F.; Trakhtenberg, L. I.

2018-06-01

The properties of nanostructured composites based on metal oxides and metal-polymer materials are analyzed, along with ways of preparing them. The effect the interaction between metal and semiconductor nanoparticles has on the conductivity, photoconductivity, catalytic activity, and magnetic, dielectric, and sensor properties of nanocomposites is discussed. It is shown that as a result of this interaction, a material can acquire properties that do not exist in systems of isolated particles. The transfer of electrons between metal particles of different sizes in polymeric matrices leads to specific dielectric losses, and to an increase in the rate and a change in the direction of chemical reactions catalyzed by these particles. The interaction between metal-oxide semiconductor particles results in the electronic and chemical sensitization of sensor effects in nanostructured composite materials. Studies on creating molecular machines (Brownian motors), devices for magnetic recording of information, and high-temperature superconductors based on nanostructured systems are reviewed.

Electronic structure of semiconductor interfaces

Energy Technology Data Exchange (ETDEWEB)

Herman, F

1983-02-01

The study of semiconductor interfaces is one of the most active and exciting areas of current semiconductor research. Because interfaces play a vital role in modern semiconductor technology (integrated circuits, heterojunction lasers, solar cells, infrared detectors, etc.), there is a strong incentive to understand interface properties at a fundamental level and advance existing technology thereby. At the same time, technological advances such as molecular beam epitaxy have paved the way for the fabrication of semiconductor heterojunctions and superlattices of novel design which exhibit unusual electronic, optical, and magnetic properties and offer unique opportunities for fundamental scientific research. A general perspective on this subject is offered treating such topics as the atomic and electronic structure of semiconductor surfaces and interfaces; oxidation and oxide layers; semiconductor heterojunctions and superlattices; rectifying metal-semiconductor contacts; and interface reactions. Recent progress is emphasized and some future directions are indicated. In addition, the role that large-scale scientific computation has played in furthering our theoretical understanding of semiconductor surfaces and interfaces is discussed. Finally, the nature of theoretical models, and the role they play in describing the physical world is considered.

Electronic structure of semiconductor interfaces

International Nuclear Information System (INIS)

Herman, F.

1983-01-01

The study of semiconductor interfaces is one of the most active and exciting areas of current semiconductor research. Because interfaces play a vital role in modern semiconductor technology (integrated circuits, heterojunction lasers, solar cells, infrared detectors, etc.), there is a strong incentive to understand interface properties at a fundamental level and advance existing technology thereby. At the same time, technological advances such as molecular beam epitaxy have paved the way for the fabrication of semiconductor heterojunctions and superlattices of novel design which exhibit unusual electronic, optical, and magnetic properties and offer unique opportunities for fundamental scientific research. A general perspective on this subject is offered treating such topics as the atomic and electronic structure of semiconductor surfaces and interfaces; oxidation and oxide layers; semiconductor heterojunctions and superlattices; rectifying metal-semiconductor contacts; and interface reactions. Recent progress is emphasized and some future directions are indicated. In addition, the role that large-scale scientific computation has played in furthering our theoretical understanding of semiconductor surfaces and interfaces is discussed. Finally, the nature of theoretical models, and the role they play in describing the physical world is considered. (Author) [pt

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.

2015-06-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

Robust parameter design for integrated circuit fabrication procedure with respect to categorical characteristic

Energy Technology Data Exchange (ETDEWEB)

Sohn, S.Y

1999-12-01

We consider a robust parameter design of the process for forming contact windows in complementary metal-oxide semiconductor circuits. Robust design is often used to find the optimal levels of process conditions which would provide the output of consistent quality as close to a target value. In this paper, we analyze the results of the fractional factorial design of nine factors: mask dimension, viscosity, bake temperature, spin speed, bake time, aperture, exposure time, developing time, etch time, where the outcome of the experiment is measured in terms of a categorized window size with five categories. Random effect analysis is employed to model both the mean and variance of categorized window size as functions of some controllable factors as well as random errors. Empirical Bayes' procedures are then utilized to fit both the models, and to eventually find the robust design of CMOS circuit process by means of a Bootstrap resampling approach.

Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal-oxide-semiconductor capacitor

Energy Technology Data Exchange (ETDEWEB)

Liu, Li Ning; Choi, Hoi Wai; Lai, Pui To [Department of Electrical and Electronic Engineering, The University of Hong Kong (China); Xu, Jing Ping [School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan (China)

2016-09-15

In this study, GaAs metal-oxide-semiconductor (MOS) capacitors using Y-incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 x 10{sup 11} cm{sup -2} eV{sup -1}), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 x 10{sup -5}A/cm{sup 2} at V{sub fb} + 1 V). These merits should be attributed to the complementary properties of Y{sub 2}O{sub 3} and Ta{sub 2}O{sub 5}:Y can effectively passivate the large amount of oxygen vacancies in Ta{sub 2}O{sub 5}, while the positively-charged oxygen vacancies in Ta{sub 2}O{sub 5} are capable of neutralizing the effects of the negative oxide charges in Y{sub 2}O{sub 3}. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Metal-insulator-semiconductor photodetectors.

Science.gov (United States)

Lin, Chu-Hsuan; Liu, Chee Wee

2010-01-01

The major radiation of the sun can be roughly divided into three regions: ultraviolet, visible, and infrared light. Detection in these three regions is important to human beings. The metal-insulator-semiconductor photodetector, with a simpler process than the pn-junction photodetector and a lower dark current than the MSM photodetector, has been developed for light detection in these three regions. Ideal UV photodetectors with high UV-to-visible rejection ratio could be demonstrated with III-V metal-insulator-semiconductor UV photodetectors. The visible-light detection and near-infrared optical communications have been implemented with Si and Ge metal-insulator-semiconductor photodetectors. For mid- and long-wavelength infrared detection, metal-insulator-semiconductor SiGe/Si quantum dot infrared photodetectors have been developed, and the detection spectrum covers atmospheric transmission windows.

Metal-Insulator-Semiconductor Photodetectors

Directory of Open Access Journals (Sweden)

Chu-Hsuan Lin

2010-09-01

Full Text Available The major radiation of the Sun can be roughly divided into three regions: ultraviolet, visible, and infrared light. Detection in these three regions is important to human beings. The metal-insulator-semiconductor photodetector, with a simpler process than the pn-junction photodetector and a lower dark current than the MSM photodetector, has been developed for light detection in these three regions. Ideal UV photodetectors with high UV-to-visible rejection ratio could be demonstrated with III-V metal-insulator-semiconductor UV photodetectors. The visible-light detection and near-infrared optical communications have been implemented with Si and Ge metal-insulator-semiconductor photodetectors. For mid- and long-wavelength infrared detection, metal-insulator-semiconductor SiGe/Si quantum dot infrared photodetectors have been developed, and the detection spectrum covers atmospheric transmission windows.

A novel charge pump drive circuit for power MOSFETs

International Nuclear Information System (INIS)

Wang Songlin; Zhou Bo; Wang Hui; Guo Wangrui; Ye Qiang

2010-01-01

Novel improved power metal oxide semiconductor field effect transistor (MOSFET) drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6 μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW. (semiconductor integrated circuits)

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

International Nuclear Information System (INIS)

Ni Henan; Wu Liangcai; Song Zhitang; Hui Chun

2009-01-01

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO 2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time. (semiconductor devices)

Controlling the interface charge density in GaN-based metal-oxide-semiconductor heterostructures by plasma oxidation of metal layers

International Nuclear Information System (INIS)

Hahn, Herwig; Kalisch, Holger; Vescan, Andrei; Pécz, Béla; Kovács, András; Heuken, Michael

2015-01-01

In recent years, investigating and engineering the oxide-semiconductor interface in GaN-based devices has come into focus. This has been driven by a large effort to increase the gate robustness and to obtain enhancement mode transistors. Since it has been shown that deep interface states act as fixed interface charge in the typical transistor operating regime, it appears desirable to intentionally incorporate negative interface charge, and thus, to allow for a positive shift in threshold voltage of transistors to realise enhancement mode behaviour. A rather new approach to obtain such negative charge is the plasma-oxidation of thin metal layers. In this study, we present transmission electron microscopy and energy dispersive X-ray spectroscopy analysis as well as electrical data for Al-, Ti-, and Zr-based thin oxide films on a GaN-based heterostructure. It is shown that the plasma-oxidised layers have a polycrystalline morphology. An interfacial amorphous oxide layer is only detectable in the case of Zr. In addition, all films exhibit net negative charge with varying densities. The Zr layer is providing a negative interface charge density of more than 1 × 10 13  cm –2 allowing to considerably shift the threshold voltage to more positive values

Scheme for the fabrication of ultrashort channel metal-oxide-semiconductor field-effect transistors

International Nuclear Information System (INIS)

Appenzeller, J.; Martel, R.; Solomon, P.; Chan, K.; Avouris, Ph.; Knoch, J.; Benedict, J.; Tanner, M.; Thomas, S.; Wang, K. L.

2000-01-01

We present a scheme for the fabrication of ultrashort channel length metal-oxide-semiconductor field-effect transistors (MOSFETs) involving nanolithography and molecular-beam epitaxy. The active channel is undoped and is defined by a combination of nanometer-scale patterning and anisotropic etching of an n ++ layer grown on a silicon on insulator wafer. The method is self-limiting and can produce MOSFET devices with channel lengths of less than 10 nm. Measurements on the first batch of n-MOSFET devices fabricated with this approach show very good output characteristics and good control of short-channel effects. (c) 2000 American Institute of Physics

Multifunctional Organic-Semiconductor Interfacial Layers for Solution-Processed Oxide-Semiconductor Thin-Film Transistor.

Science.gov (United States)

Kwon, Guhyun; Kim, Keetae; Choi, Byung Doo; Roh, Jeongkyun; Lee, Changhee; Noh, Yong-Young; Seo, SungYong; Kim, Myung-Gil; Kim, Choongik

2017-06-01

The stabilization and control of the electrical properties in solution-processed amorphous-oxide semiconductors (AOSs) is crucial for the realization of cost-effective, high-performance, large-area electronics. In particular, impurity diffusion, electrical instability, and the lack of a general substitutional doping strategy for the active layer hinder the industrial implementation of copper electrodes and the fine tuning of the electrical parameters of AOS-based thin-film transistors (TFTs). In this study, the authors employ a multifunctional organic-semiconductor (OSC) interlayer as a solution-processed thin-film passivation layer and a charge-transfer dopant. As an electrically active impurity blocking layer, the OSC interlayer enhances the electrical stability of AOS TFTs by suppressing the adsorption of environmental gas species and copper-ion diffusion. Moreover, charge transfer between the organic interlayer and the AOS allows the fine tuning of the electrical properties and the passivation of the electrical defects in the AOS TFTs. The development of a multifunctional solution-processed organic interlayer enables the production of low-cost, high-performance oxide semiconductor-based circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Accuracy of dielectric-dependent hybrid functionals in the prediction of optoelectronic properties of metal oxide semiconductors: a comprehensive comparison with many-body GW and experiments

Science.gov (United States)

Gerosa, M.; E Bottani, C.; Di Valentin, C.; Onida, G.; Pacchioni, G.

2018-01-01

Understanding the electronic structure of metal oxide semiconductors is crucial to their numerous technological applications, such as photoelectrochemical water splitting and solar cells. The needed experimental and theoretical knowledge goes beyond that of pristine bulk crystals, and must include the effects of surfaces and interfaces, as well as those due to the presence of intrinsic defects (e.g. oxygen vacancies), or dopants for band engineering. In this review, we present an account of the recent efforts in predicting and understanding the optoelectronic properties of oxides using ab initio theoretical methods. In particular, we discuss the performance of recently developed dielectric-dependent hybrid functionals, providing a comparison against the results of many-body GW calculations, including G 0 W 0 as well as more refined approaches, such as quasiparticle self-consistent GW. We summarize results in the recent literature for the band gap, the band level alignment at surfaces, and optical transition energies in defective oxides, including wide gap oxide semiconductors and transition metal oxides. Correlated transition metal oxides are also discussed. For each method, we describe successes and drawbacks, emphasizing the challenges faced by the development of improved theoretical approaches. The theoretical section is preceded by a critical overview of the main experimental techniques needed to characterize the optoelectronic properties of semiconductors, including absorption and reflection spectroscopy, photoemission, and scanning tunneling spectroscopy (STS).

Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.

Science.gov (United States)

Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

2008-12-02

Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

Self-aligned metallization on organic semiconductor through 3D dual-layer thermal nanoimprint

International Nuclear Information System (INIS)

Jung, Y; Cheng, X

2014-01-01

High-resolution patterning of metal structures on organic semiconductors is important to the realization of high-performance organic transistors for organic integrated circuit applications. The traditional shadow mask technique has a limited resolution, precluding sub-micron metal structures on organic semiconductors. Thus organic transistors cannot benefit from scaling into the deep sub-micron region to improve their dc and ac performances. In this work, we report an efficient multiple-level metallization on poly (3-hexylthiophene) (P3HT) with a deep sub-micron lateral gap. By using a 3D nanoimprint mold in a dual-layer thermal nanoimprint process, we achieved self-aligned two-level metallization on P3HT. The 3D dual-layer thermal nanoimprint enables the first metal patterns to have suspending side-wings that can clearly define a distance from the second metal patterns. Isotropic and anisotropic side-wing structures can be fabricated through two different schemes. The process based on isotropic side-wings achieves a lateral-gap in the order of 100 nm (scheme 1). A gap of 60 nm can be achieved from the process with anisotropic side-wings (scheme 2). Because of the capability of nanoscale metal patterning on organic semiconductors with high overlay accuracy, this self-aligned metallization technique can be utilized to fabricate high-performance organic metal semiconductor field-effect transistor. (paper)

Fabrication of smooth patterned structures of refractory metals, semiconductors, and oxides via template stripping.

Science.gov (United States)

Park, Jong Hyuk; Nagpal, Prashant; McPeak, Kevin M; Lindquist, Nathan C; Oh, Sang-Hyun; Norris, David J

2013-10-09

The template-stripping method can yield smooth patterned films without surface contamination. However, the process is typically limited to coinage metals such as silver and gold because other materials cannot be readily stripped from silicon templates due to strong adhesion. Herein, we report a more general template-stripping method that is applicable to a larger variety of materials, including refractory metals, semiconductors, and oxides. To address the adhesion issue, we introduce a thin gold layer between the template and the deposited materials. After peeling off the combined film from the template, the gold layer can be selectively removed via wet etching to reveal a smooth patterned structure of the desired material. Further, we demonstrate template-stripped multilayer structures that have potential applications for photovoltaics and solar absorbers. An entire patterned device, which can include a transparent conductor, semiconductor absorber, and back contact, can be fabricated. Since our approach can also produce many copies of the patterned structure with high fidelity by reusing the template, a low-cost and high-throughput process in micro- and nanofabrication is provided that is useful for electronics, plasmonics, and nanophotonics.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

Science.gov (United States)

Geier, Michael

symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

Empirical study of the metal-nitride-oxide-semiconductor device characteristics deduced from a microscopic model of memory traps

International Nuclear Information System (INIS)

Ngai, K.L.; Hsia, Y.

1982-01-01

A graded-nitride gate dielectric metal-nitride-oxide-semiconductor (MNOS) memory transistor exhibiting superior device characteristics is presented and analyzed based on a qualitative microscopic model of the memory traps. The model is further reviewed to interpret some generic properties of the MNOS memory transistors including memory window, erase-write speed, and the retention-endurance characteristic features

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

Science.gov (United States)

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

Plasma-assisted atomic layer deposition of TiN/Al2O3 stacks for metal-oxide-semiconductor capacitor applications

NARCIS (Netherlands)

Hoogeland, D.; Jinesh, K.B.; Roozeboom, F.; Besling, W.F.A.; Sanden, van de M.C.M.; Kessels, W.M.M.

2009-01-01

By employing plasma-assisted atomic layer deposition, thin films of Al2O3 and TiN are subsequently deposited in a single reactor at a single substrate temperature with the objective of fabricating high-quality TiN/Al2O3 / p-Si metal-oxide-semiconductor capacitors. Transmission electron microscopy

Metabolomics on integrated circuit

OpenAIRE

Cheah, Boon Chong; MacDonald, Alasdair I.; Barrett, Michael P.; Cumming, David R.S.

2017-01-01

We have demonstrated a chip-based diagnostics tool for the quantification of metabolites, using specific enzymes, to study enzyme kinetics and calculate the Michaelis-Menten constant. An array of 256×256 ion-sensitive field effect transistors (ISFETs) fabricated in a complementary metal oxide semiconductor (CMOS) process is used for this prototype. We have used hexokinase enzyme reaction on the ISFET CMOS chip with glucose concentration in the physiological range of 0.05 mM – 231 mM and succe...

Metal/Semiconductor and Transparent Conductor/Semiconductor Heterojunctions in High Efficient Photoelectric Devices: Progress and Features

Directory of Open Access Journals (Sweden)

M. Melvin David Kumar

2014-01-01

Full Text Available Metal/semiconductor and transparent conductive oxide (TCO/semiconductor heterojunctions have emerged as an effective modality in the fabrication of photoelectric devices. This review is following a recent shift toward the engineering of TCO layers and structured Si substrates, incorporating metal nanoparticles for the development of next-generation photoelectric devices. Beneficial progress which helps to increase the efficiency and reduce the cost, has been sequenced based on efficient technologies involved in making novel substrates, TCO layers, and electrodes. The electrical and optical properties of indium tin oxide (ITO and aluminum doped zinc oxide (AZO thin films can be enhanced by structuring the surface of TCO layers. The TCO layers embedded with Ag nanoparticles are used to enhance the plasmonic light trapping effect in order to increase the energy harvesting nature of photoelectric devices. Si nanopillar structures which are fabricated by photolithography-free technique are used to increase light-active surface region. The importance of the structure and area of front electrodes and the effect of temperature at the junction are the value added discussions in this review.

Nanoscale Metal Oxide Semiconductors for Gas Sensing

Science.gov (United States)

Hunter, Gary W.; Evans, Laura; Xu, Jennifer C.; VanderWal, Randy L.; Berger, Gordon M.; Kulis, Michael J.

2011-01-01

A report describes the fabrication and testing of nanoscale metal oxide semiconductors (MOSs) for gas and chemical sensing. This document examines the relationship between processing approaches and resulting sensor behavior. This is a core question related to a range of applications of nanotechnology and a number of different synthesis methods are discussed: thermal evaporation- condensation (TEC), controlled oxidation, and electrospinning. Advantages and limitations of each technique are listed, providing a processing overview to developers of nanotechnology- based systems. The results of a significant amount of testing and comparison are also described. A comparison is made between SnO2, ZnO, and TiO2 single-crystal nanowires and SnO2 polycrystalline nanofibers for gas sensing. The TECsynthesized single-crystal nanowires offer uniform crystal surfaces, resistance to sintering, and their synthesis may be done apart from the substrate. The TECproduced nanowire response is very low, even at the operating temperature of 200 C. In contrast, the electrospun polycrystalline nanofiber response is high, suggesting that junction potentials are superior to a continuous surface depletion layer as a transduction mechanism for chemisorption. Using a catalyst deposited upon the surface in the form of nanoparticles yields dramatic gains in sensitivity for both nanostructured, one-dimensional forms. For the nanowire materials, the response magnitude and response rate uniformly increase with increasing operating temperature. Such changes are interpreted in terms of accelerated surface diffusional processes, yielding greater access to chemisorbed oxygen species and faster dissociative chemisorption, respectively. Regardless of operating temperature, sensitivity of the nanofibers is a factor of 10 to 100 greater than that of nanowires with the same catalyst for the same test condition. In summary, nanostructure appears critical to governing the reactivity, as measured by electrical

Instrumentation for characterizing materials and composed semiconductors for ionizing radiation detectors

International Nuclear Information System (INIS)

Paschoal, Arquimedes J.A.; Leite, Adolfo M.B.; Nazzre, Fabio V.B.; Santos, Luiz A.P.

2007-01-01

The purpose of this work is the development of instrumentation for characterizing some type of ionizing radiation detectors. Those detectors are being manufactured by the Nuclear Instrumentation Laboratory at CRCN/Recife and can be used both on photon beam and with particles. Such detectors consist of semiconductor material in the form of films generated by oxide growing or by means of semiconductor material deposition in a substrate. Those materials can be made of metals, semi-metals, composites or semiconductor polymers. Prior to expose those detectors to ionizing radiation, it must be physically and electrically characterized. In this intention it was developed an electromechanical system. An electrical circuit was built to measure the signal from the detector and another circuit to control the movement of four probes (4-points technique) by using a stepper motor and the micro stepping technique avoiding damage to the detector. This system can be of interest to researchers that work with a sort of semiconductor materials in the form of thin film and in nanotechnological processes aiming the design of radiation ionizing detectors. (author)

Power management circuits for self-powered systems based on micro-scale solar energy harvesting

Science.gov (United States)

Yoon, Eun-Jung; Yu, Chong-Gun

2016-03-01

In this paper, two types of power management circuits for self-powered systems based on micro-scale solar energy harvesting are proposed. First, if a solar cell outputs a very low voltage, less than 0.5 V, as in miniature solar cells or monolithic integrated solar cells, such that it cannot directly power the load, a voltage booster is employed to step up the solar cell's output voltage, and then a power management unit (PMU) delivers the boosted voltage to the load. Second, if the output voltage of a solar cell is enough to drive the load, the PMU directly supplies the load with solar energy. The proposed power management systems are designed and fabricated in a 0.18-μm complementary metal-oxide-semiconductor process, and their performances are compared and analysed through measurements.

Review of recent developments in amorphous oxide semiconductor thin-film transistor devices

International Nuclear Information System (INIS)

Park, Joon Seok; Maeng, Wan-Joo; Kim, Hyun-Suk; Park, Jin-Seong

2012-01-01

The present article is a review of the recent progress and major trends in the field of thin-film transistor (TFT) research involving the use of amorphous oxide semiconductors (AOS). First, an overview is provided on how electrical performance may be enhanced by the adoption of specific device structures and process schemes, the combination of various oxide semiconductor materials, and the appropriate selection of gate dielectrics and electrode metals in contact with the semiconductor. As metal oxide TFT devices are excellent candidates for switching or driving transistors in next generation active matrix liquid crystal displays (AMLCD) or active matrix organic light emitting diode (AMOLED) displays, the major parameters of interest in the electrical characteristics involve the field effect mobility (μ FE ), threshold voltage (V th ), and subthreshold swing (SS). A study of the stability of amorphous oxide TFT devices is presented next. Switching or driving transistors in AMLCD or AMOLED displays inevitably involves voltage bias or constant current stress upon prolonged operation, and in this regard many research groups have examined and proposed device degradation mechanisms under various stress conditions. The most recent studies involve stress experiments in the presence of visible light irradiating the semiconductor, and different degradation mechanisms have been proposed with respect to photon radiation. The last part of this review consists of a description of methods other than conventional vacuum deposition techniques regarding the formation of oxide semiconductor films, along with some potential application fields including flexible displays and information storage.

Chemoelectronic circuits based on metal nanoparticles

Science.gov (United States)

Yan, Yong; Warren, Scott C.; Fuller, Patrick; Grzybowski, Bartosz A.

2016-07-01

To develop electronic devices with novel functionalities and applications, various non-silicon-based materials are currently being explored. Nanoparticles have unique characteristics due to their small size, which can impart functions that are distinct from those of their bulk counterparts. The use of semiconductor nanoparticles has already led to improvements in the efficiency of solar cells, the processability of transistors and the sensitivity of photodetectors, and the optical and catalytic properties of metal nanoparticles have led to similar advances in plasmonics and energy conversion. However, metals screen electric fields and this has, so far, prevented their use in the design of all-metal nanoparticle circuitry. Here, we show that simple electronic circuits can be made exclusively from metal nanoparticles functionalized with charged organic ligands. In these materials, electronic currents are controlled by the ionic gradients of mobile counterions surrounding the ‘jammed’ nanoparticles. The nanoparticle-based electronic elements of the circuitry can be interfaced with metal nanoparticles capable of sensing various environmental changes (humidity, gas, the presence of various cations), creating electronic devices in which metal nanoparticles sense, process and ultimately report chemical signals. Because the constituent nanoparticles combine electronic and chemical sensing functions, we term these systems ‘chemoelectronic’. The circuits have switching times comparable to those of polymer electronics, selectively transduce parts-per-trillion chemical changes into electrical signals, perform logic operations, consume little power (on the scale of microwatts), and are mechanically flexible. They are also ‘green’, in the sense that they comprise non-toxic nanoparticles cast at room temperature from alcohol solutions.

Monitoring Apnea in the Elderly by an Electromechanical System with a Carbon Nanotube-based Sensor

Directory of Open Access Journals (Sweden)

Hung-Chang Liu

2013-09-01

Conclusion: Our results showed that a new device composed of an NEMS by combining an MWCNT sensor and complementary metal-oxide semiconductor (CMOS circuits could be integrated to effectively detect apnea in the elderly. This novel device may improve the pattern of safe respiratory care for the elderly in the future.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

Energy Technology Data Exchange (ETDEWEB)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany); Miehler, Dominik [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Zaumseil, Jana, E-mail: zaumseil@uni-heidelberg.de [Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany)

2015-08-24

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.

Exploring SiSn as a performance enhancing semiconductor: A theoretical and experimental approach

KAUST Repository

Hussain, Aftab M.

2014-12-14

We present a novel semiconducting alloy, silicon-tin (SiSn), as channel material for complementary metal oxide semiconductor (CMOS) circuit applications. The material has been studied theoretically using first principles analysis as well as experimentally by fabricating MOSFETs. Our study suggests that the alloy offers interesting possibilities in the realm of silicon band gap tuning. We have explored diffusion of tin (Sn) into the industry\\'s most widely used substrate, silicon (100), as it is the most cost effective, scalable and CMOS compatible way of obtaining SiSn. Our theoretical model predicts a higher mobility for p-channel SiSn MOSFETs, due to a lower effective mass of the holes, which has been experimentally validated using the fabricated MOSFETs. We report an increase of 13.6% in the average field effect hole mobility for SiSn devices compared to silicon control devices.

Where science fiction meets reality? With oxide semiconductors.

Energy Technology Data Exchange (ETDEWEB)

Fortunato, E.; Martins, R. [CENIMAT/I3N, Departamento de Ciencia dos Materiais, Faculdade de Ciencias e Tecnologia, FCT, Universidade Nova de Lisboa, CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

2011-09-15

Transparent electronics is today one of the most advanced topics for a wide range of device applications, where the key components are wide band gap semiconductors, where oxides of different origin play an important role, not only as passive components but also as active components similar to what we observe in conventional semiconductors. As passive components they include the use of these materials as dielectrics for a wide range of electronic devices and also as transparent electrical conductors for use in several optoelectronic applications, such as liquid crystal displays, organic light emitting diodes, solar cells, optical sensors etc. As active materials, they exploit the use of truly electronic semiconductors where the main emphasis is being put on transparent thin film transistors, light emitting diodes, lasers, ultraviolet sensors and integrated circuits among others. (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

Directory of Open Access Journals (Sweden)

Chyan-Chyi Wu

2009-02-01

Full Text Available This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature

Review of mixer design for low voltage - low power applications

Science.gov (United States)

Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

2017-09-01

A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

Science.gov (United States)

Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

1996-01-01

Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

Effective dose assessment in the maxillofacial region using thermoluminescent (TLD) and metal oxide semiconductor field-effect transistor (MOSFET) dosemeters: a comparative study

NARCIS (Netherlands)

Koivisto, J.; Schulze, D.; Wolff, J.E.H.; Rottke, D.

2014-01-01

Objectives: The objective of this study was to compare the performance of metal oxide semiconductor field-effect transistor (MOSFET) technology dosemeters with thermoluminescent dosemeters (TLDs) (TLD 100; Thermo Fisher Scientific, Waltham, MA) in the maxillofacial area. Methods: Organ and effective

Damage free Ar ion plasma surface treatment on In{sub 0.53}Ga{sub 0.47}As-on-silicon metal-oxide-semiconductor device

Energy Technology Data Exchange (ETDEWEB)

Koh, Donghyi; Shin, Seung Heon; Ahn, Jaehyun; Sonde, Sushant; Banerjee, Sanjay K. [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, 10100 Burnet Road, Austin, Texas 78758 (United States); Kwon, Hyuk-Min [SK Hynix, Icheon, 2091, Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do 136-1 (Korea, Republic of); Orzali, Tommaso; Kim, Tae-Woo, E-mail: twkim78@gmail.com [SEMATECH Inc., 257 Fuller Rd #2200, Albany, New York 12203 (United States); Kim, Dae-Hyun [Kyungpook National University, 80, Daehak-ro, Buk-gu, Daegu 702-701 (Korea, Republic of)

2015-11-02

In this paper, we investigated the effect of in-situ Ar ion plasma surface pre-treatment in order to improve the interface properties of In{sub 0.53}Ga{sub 0.47}As for high-κ top-gate oxide deposition. X-ray photoelectron spectroscopy (XPS) and metal-oxide-semiconductor capacitors (MOSCAPs) demonstrate that Ar ion treatment removes the native oxide on In{sub 0.53}Ga{sub 0.47}As. The XPS spectra of Ar treated In{sub 0.53}Ga{sub 0.47}As show a decrease in the AsO{sub x} and GaO{sub x} signal intensities, and the MOSCAPs show higher accumulation capacitance (C{sub acc}), along with reduced frequency dispersion. In addition, Ar treatment is found to suppress the interface trap density (D{sub it}), which thereby led to a reduction in the threshold voltage (V{sub th}) degradation during constant voltage stress and relaxation. These results outline the potential of surface treatment for III-V channel metal-oxide-semiconductor devices and application to non-planar device process.

Functional integrity of flexible n-channel metal-oxide-semiconductor field-effect transistors on a reversibly bistable platform

Science.gov (United States)

Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan P.; Aljedaani, Abdulrahman B.; Hussain, Muhammad M.

2015-10-01

Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal-oxide-semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

High-performance hybrid complementary logic inverter through monolithic integration of a MEMS switch and an oxide TFT.

Science.gov (United States)

Song, Yong-Ha; Ahn, Sang-Joon Kenny; Kim, Min-Wu; Lee, Jeong-Oen; Hwang, Chi-Sun; Pi, Jae-Eun; Ko, Seung-Deok; Choi, Kwang-Wook; Park, Sang-Hee Ko; Yoon, Jun-Bo

2015-03-25

A hybrid complementary logic inverter consisting of a microelectromechanical system switch as a promising alternative for the p-type oxide thin film transistor (TFT) and an n-type oxide TFT is presented for ultralow power integrated circuits. These heterogeneous microdevices are monolithically integrated. The resulting logic device shows a distinctive voltage transfer characteristic curve, very low static leakage, zero-short circuit current, and exceedingly high voltage gain. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Single photon sources in 4H-SiC metal-oxide-semiconductor field-effect transistors

Science.gov (United States)

Abe, Y.; Umeda, T.; Okamoto, M.; Kosugi, R.; Harada, S.; Haruyama, M.; Kada, W.; Hanaizumi, O.; Onoda, S.; Ohshima, T.

2018-01-01

We present single photon sources (SPSs) embedded in 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). They are formed in the SiC/SiO2 interface regions of wet-oxidation C-face 4H-SiC MOSFETs and were not found in other C-face and Si-face MOSFETs. Their bright room-temperature photoluminescence (PL) was observed in the range from 550 to 750 nm and revealed variable multi-peak structures as well as variable peak shifts. We characterized a wide variety of their PL spectra as the inevitable variation of local atomic structures at the interface. Their polarization dependence indicates that they are formed at the SiC side of the interface. We also demonstrate that it is possible to switch on/off the SPSs by a bias voltage of the MOSFET.

Positron annihilation studies in the field induced depletion regions of metal-oxide-semiconductor structures

Science.gov (United States)

Asoka-Kumar, P.; Leung, T. C.; Lynn, K. G.; Nielsen, B.; Forcier, M. P.; Weinberg, Z. A.; Rubloff, G. W.

1992-06-01

The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions.

Positron annihilation studies in the field induced depletion regions of metal-oxide-semiconductor structures

International Nuclear Information System (INIS)

Asoka-Kumar, P.; Leung, T.C.; Lynn, K.G.; Nielsen, B.; Forcier, M.P.; Weinberg, Z.A.; Rubloff, G.W.

1992-01-01

The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions

Effects of oxide traps, interface traps, and ''border traps'' on metal-oxide-semiconductor devices

International Nuclear Information System (INIS)

Fleetwood, D.M.; Winokur, P.S.; Reber, R.A. Jr.; Meisenheimer, T.L.; Schwank, J.R.; Shaneyfelt, M.R.; Riewe, L.C.

1993-01-01

We have identified several features of the 1/f noise and radiation response of metal-oxide-semiconductor (MOS) devices that are difficult to explain with standard defect models. To address this issue, and in response to ambiguities in the literature, we have developed a revised nomenclature for defects in MOS devices that clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. In this nomenclature, ''oxide traps'' are simply defects in the SiO 2 layer of the MOS structure, and ''interface traps'' are defects at the Si/SiO 2 interface. Nothing is presumed about how either type of defect communicates with the underlying Si. Electrically, ''fixed states'' are defined as trap levels that do not communicate with the Si on the time scale of the measurements, but ''switching states'' can exchange charge with the Si. Fixed states presumably are oxide traps in most types of measurements, but switching states can either be interface traps or near-interfacial oxide traps that can communicate with the Si, i.e., ''border traps'' [D. M. Fleetwood, IEEE Trans. Nucl. Sci. NS-39, 269 (1992)]. The effective density of border traps depends on the time scale and bias conditions of the measurements. We show the revised nomenclature can provide focus to discussions of the buildup and annealing of radiation-induced charge in non-radiation-hardened MOS transistors, and to changes in the 1/f noise of MOS devices through irradiation and elevated-temperature annealing

Fully Integrated Solar Energy Harvester and Sensor Interface Circuits for Energy-Efficient Wireless Sensing Applications

Directory of Open Access Journals (Sweden)

Maher Kayal

2013-02-01

Full Text Available This paper presents an energy-efficient solar energy harvesting and sensing microsystem that harvests solar energy from a micro-power photovoltaic module for autonomous operation of a gas sensor. A fully integrated solar energy harvester stores the harvested energy in a rechargeable NiMH microbattery. Hydrogen concentration and temperature are measured and converted to a digital value with 12-bit resolution using a fully integrated sensor interface circuit, and a wireless transceiver is used to transmit the measurement results to a base station. As the harvested solar energy varies considerably in different lighting conditions, in order to guarantee autonomous operation of the sensor, the proposed area- and energy-efficient circuit scales the power consumption and performance of the sensor. The power management circuit dynamically decreases the operating frequency of digital circuits and bias currents of analog circuits in the sensor interface circuit and increases the idle time of the transceiver under reduced light intensity. The proposed microsystem has been implemented in a 0.18 µm complementary metal-oxide-semiconductor (CMOS process and occupies a core area of only 0.25 mm2. This circuit features a low power consumption of 2.1 µW when operating at its highest performance. It operates with low power supply voltage in the 0.8V to 1.6 V range.

Metal-semiconductor, composite radiation detectors

International Nuclear Information System (INIS)

Orvis, W.J.; Yee, J.H.; Fuess, D.A.

1991-12-01

In 1989, Naruse and Hatayama of Toshiba published a design for an increased efficiency x-ray detector. The design increased the efficiency of a semiconductor detector by interspersing layers of high-z metal within it. Semiconductors such as silicon make good, high-resolution radiation detectors, but they have low efficiency because they are low-z materials (z = 14). High-z metals, on the other hand, are good absorbers of high-energy photons. By interspersing high-z metal layers with semiconductor layers, Naruse and Hatayama combined the high absorption efficiency of the high-z metals with good detection capabilities of a semiconductor. This project is an attempt to use the same design to produce a high- efficiency gamma ray detector. By their nature, gamma rays require thicker metal layers to efficiently absorb them. These thicker layers change the behavior of the detector by reducing the resolution, compared to a solid state detector, and shifting the photopeak by a predictable amount. During the last year, we have modeled parts of the detector and have nearly completed a prototype device. 2 refs

Pr-O-Al-N dielectrics for metal insulator semiconductor stacks

Energy Technology Data Exchange (ETDEWEB)

Henkel, Karsten; Torche, Mohamed; Sohal, Rakesh; Karavaev, Konstantin; Burkov, Yevgen; Schwiertz, Carola; Schmeisser, Dieter [Brandenburg University of Technology, Chair of Applied Physics and Sensors, K.-Wachsmann-Allee 1, 03046 Cottbus (Germany)

2011-02-15

This work focuses on praseodymium oxide films as a high-k material on silicon and silicon carbide (SiC) in metal insulator semiconductor samples. The electrical results are correlated to spectroscopic findings on this material system. Strong interfacial reactions between the praseodymium oxide and the semiconductor as well as silicon inter-diffusion into the high-k material are observed. The importance of a buffer layer is discussed and its optimisation is addressed, too. In particular the improvement of the performance by the introduction of an aluminium oxynitride buffer layer, which acts as an inter-diffusion barrier and reduces the leakage current, the interface state density and the equivalent oxide thickness is demonstrated. (Copyright copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

A complementary metal oxide semiconductor—integrable conditioning circuit for resistive chemical sensor management

International Nuclear Information System (INIS)

Depari, Alessandro; Flammini, Alessandra; De Marcellis, Andrea; Ferri, Giuseppe

2011-01-01

This paper presents a new interface circuit (for MOX-based resistive chemical sensors) capable of overcoming the main limit of the circuits based on the resistance-to-time approach, i.e. the long measuring time with high-value resistances. The system is designed to operate with a single supply of 3.3 V, thus facilitating an ASIC implementation together with digital electronics for a first data analysis and transmission. This is particularly advantageous when the elaboration process requires a large computational load and a data pre-elaboration is advisable. Simulations of the integrable solution of the system have shown the feasibility of the proposed approach. A prototype with discrete components has been furthermore fabricated and experimentally tested, showing good performance in the range 0.5 MΩ to 10 GΩ with a maximum measuring time of 60 ms

Infrared rectification in a nanoantenna-coupled metal-oxide-semiconductor tunnel diode.

Science.gov (United States)

Davids, Paul S; Jarecki, Robert L; Starbuck, Andrew; Burckel, D Bruce; Kadlec, Emil A; Ribaudo, Troy; Shaner, Eric A; Peters, David W

2015-12-01

Direct rectification of electromagnetic radiation is a well-established method for wireless power conversion in the microwave region of the spectrum, for which conversion efficiencies in excess of 84% have been demonstrated. Scaling to the infrared or optical part of the spectrum requires ultrafast rectification that can only be obtained by direct tunnelling. Many research groups have looked to plasmonics to overcome antenna-scaling limits and to increase the confinement. Recently, surface plasmons on heavily doped Si surfaces were investigated as a way of extending surface-mode confinement to the thermal infrared region. Here we combine a nanostructured metallic surface with a heavily doped Si infrared-reflective ground plane designed to confine infrared radiation in an active electronic direct-conversion device. The interplay of strong infrared photon-phonon coupling and electromagnetic confinement in nanoscale devices is demonstrated to have a large impact on ultrafast electronic tunnelling in metal-oxide-semiconductor (MOS) structures. Infrared dispersion of SiO2 near a longitudinal optical (LO) phonon mode gives large transverse-field confinement in a nanometre-scale oxide-tunnel gap as the wavelength-dependent permittivity changes from 1 to 0, which leads to enhanced electromagnetic fields at material interfaces and a rectified displacement current that provides a direct conversion of infrared radiation into electric current. The spectral and electrical signatures of the nanoantenna-coupled tunnel diodes are examined under broadband blackbody and quantum-cascade laser (QCL) illumination. In the region near the LO phonon resonance, we obtained a measured photoresponsivity of 2.7 mA W(-1) cm(-2) at -0.1 V.

Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

Science.gov (United States)

Shin, SeungJun; Yu, YunSeop; Choi, JungBum

2008-10-01

New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

Absorbed dose by a CMOS in radiotherapy

International Nuclear Information System (INIS)

Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

2011-10-01

Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

Homostructured ZnO-based metal-oxide-semiconductor field-effect transistors deposited at low temperature by vapor cooling condensation system

Energy Technology Data Exchange (ETDEWEB)

Lin, Tzu-Shun [Institute of Nanotechnology and Microsystems Engineering, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China); Lee, Ching-Ting, E-mail: ctlee@ee.ncku.edu.tw [Institute of Nanotechnology and Microsystems Engineering, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China); Institute of Microelectronics, Department of Electrical Engineering, Advanced Optoelectronic Technology Center, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China)

2015-11-01

Highlights: • The vapor cooling condensation system was designed and used to deposit homostructured ZnO-based metal-oxide-semiconductor field-effect transistors. • The resulting homostructured ZnO-based MOSFETs operated at a reverse voltage of −6 V had a very low gate leakage current of 24 nA. • The associated I{sub DSS} and the g{sub m(max)} were 5.64 mA/mm and 1.31 mS/mm, respectively. - Abstract: The vapor cooling condensation system was designed and used to deposit homostructured ZnO-based metal-oxide-semiconductor field-effect transistors (MOSFETs) on sapphire substrates. Owing to the high quality of the deposited, various ZnO films and interfaces, the resulting MOSFETs manifested attractive characteristics, such as the low gate leakage current of 24 nA, the low average interface state density of 2.92 × 10{sup 11} cm{sup −2} eV{sup −1}, and the complete pinch-off performance. The saturation drain–source current, the maximum transconductance, and the gate voltage swing of the resulting homostructured ZnO-based MOSFETs were 5.64 mA/mm, 1.31 mS/mm, and 3.2 V, respectively.

H+-type and OH- -type biological protonic semiconductors and complementary devices.

Science.gov (United States)

Deng, Yingxin; Josberger, Erik; Jin, Jungho; Roudsari, Anita Fadavi; Rousdari, Anita Fadavi; Helms, Brett A; Zhong, Chao; Anantram, M P; Rolandi, Marco

2013-10-03

Proton conduction is essential in biological systems. Oxidative phosphorylation in mitochondria, proton pumping in bacteriorhodopsin, and uncoupling membrane potentials by the antibiotic Gramicidin are examples. In these systems, H(+) hop along chains of hydrogen bonds between water molecules and hydrophilic residues - proton wires. These wires also support the transport of OH(-) as proton holes. Discriminating between H(+) and OH(-) transport has been elusive. Here, H(+) and OH(-) transport is achieved in polysaccharide- based proton wires and devices. A H(+)- OH(-) junction with rectifying behaviour and H(+)-type and OH(-)-type complementary field effect transistors are demonstrated. We describe these devices with a model that relates H(+) and OH(-) to electron and hole transport in semiconductors. In turn, the model developed for these devices may provide additional insights into proton conduction in biological systems.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

Science.gov (United States)

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

KAUST Repository

Sevilla, Galo T.; Almuslem, A. S.; Gumus, Abdurrahman; Hussain, Aftab M.; Hussain, Aftab M.; Cruz, Melvin; Hussain, Muhammad Mustafa

2016-01-01

shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

Energy Technology Data Exchange (ETDEWEB)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kawarada, Hiroshi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishiwaseda, Shinjuku, Tokyo 169-0051 (Japan)

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

Method to induce a conductivity type in a semiconductor

International Nuclear Information System (INIS)

Aboaf, J.A.; Sedgwick, T.O.

1977-01-01

The invention deals with a method in which one can produce a region of a desired type of conductivity in a semiconductor as is required for, e.g., field effect transistors. A metal oxide layer combination consisting of several metal oxides is thus deposited on the semiconductor. This is carried out according to the invention in a non-oxidizing atmosphere at temperatures at which the metal oxides do not diffuse into the semiconductor. The sign and degree of the induced conductivity type is adjusted by dosed depositing of the individual metal oxides related to one another. The gaseous metal oxides due to heating, mixed with a non-oxidizing gas are added in compounds to the semiconductor heated to depositing temperature. These compounds decompose at the depositing temperature into the metal oxide and a gaseous residual component. The semiconductor consists of silicon, and nitrogen is used as carrier gas; when depositing aluminium oxide, gaseous aluminium isopropoxide is added; when depositing silicon dioxide, gaseous tetra-ethyl orthosilicate. (ORU) [de

Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

International Nuclear Information System (INIS)

Chakraborty, Gargi; Sarkar, C K; Lu, X B; Dai, J Y

2008-01-01

The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

Science.gov (United States)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

Science.gov (United States)

2012-05-01

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit... States after importation of certain semiconductor integrated circuit devices and products containing same... No. 6,847,904 (``the '904 patent''). The complaint further alleges that an industry in the United...

The role of metallic impurities in oxide semiconductors: first-principles calculations and PAC experiments

Energy Technology Data Exchange (ETDEWEB)

Errico, L.A.; Fabricius, G.; Renteria, M. [Departamento de Fisica, Facultad de Ciencias Exactas, Universidad Nacional de La Plata, CC 67, 1900 La Plata (Argentina)

2004-08-01

We report an ab-initio comparative study of the electric-field-gradient tensor (EFG) and structural relaxations introduced by acceptor (Cd) and donor (Ta) impurities when they replace cations in a series of binary oxides: TiO{sub 2}, SnO{sub 2}, and In{sub 2}O{sub 3}. Calculations were performed with the Full-Potential Linearized-Augmented Plane Waves method that allows us to treat the electronic structure and the atomic relaxations in a fully self-consistent way. We considered different charge states for each impurity and studied the dependence on these charge states of the electronic properties and the structural relaxations. Our results are compared with available data coming from PAC experiments and previous calculations, allowing us to obtain a new insight on the role that metal impurities play in oxide semiconductors. It is clear from our results that simple models can not describe the measured EFGs at impurities in oxides even approximately. (copyright 2004 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

G(sup 4)FET Implementations of Some Logic Circuits

Science.gov (United States)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

Development of analog watch with minute repeater

Science.gov (United States)

Okigami, Tomio; Aoyama, Shigeru; Osa, Takashi; Igarashi, Kiyotaka; Ikegami, Tomomi

A complementary metal oxide semiconductor with large scale integration was developed for an electronic minute repeater. It is equipped with the synthetic struck sound circuit to generate natural struck sound necessary for the minute repeater. This circuit consists of an envelope curve drawing circuit, frequency mixer, polyphonic mixer, and booster circuit made by using analog circuit technology. This large scale integration is a single chip microcomputer with motor drivers and input ports in addition to the synthetic struck sound circuit, and it is possible to make an electronic system of minute repeater at a very low cost in comparison with the conventional type.

75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

Science.gov (United States)

2010-02-04

... Semiconductor Integrated Circuits and Products Containing Same; Notice of Commission Determination To Review in... importation of certain semiconductor integrated circuits and products containing same by reason of... (collectively ``Seagate''). Qimonda accuses of infringement certain LSI integrated circuits, as well as certain...

Radiation effects and soft errors in integrated circuits and electronic devices

CERN Document Server

Fleetwood, D M

2004-01-01

This book provides a detailed treatment of radiation effects in electronic devices, including effects at the material, device, and circuit levels. The emphasis is on transient effects caused by single ionizing particles (single-event effects and soft errors) and effects produced by the cumulative energy deposited by the radiation (total ionizing dose effects). Bipolar (Si and SiGe), metal-oxide-semiconductor (MOS), and compound semiconductor technologies are discussed. In addition to considering the specific issues associated with high-performance devices and technologies, the book includes th

Fundamental energy limits of SET-based Brownian NAND and half-adder circuits. Preliminary findings from a physical-information-theoretic methodology

Science.gov (United States)

Ercan, İlke; Suyabatmaz, Enes

2018-06-01

The saturation in the efficiency and performance scaling of conventional electronic technologies brings about the development of novel computational paradigms. Brownian circuits are among the promising alternatives that can exploit fluctuations to increase the efficiency of information processing in nanocomputing. A Brownian cellular automaton, where signals propagate randomly and are driven by local transition rules, can be made computationally universal by embedding arbitrary asynchronous circuits on it. One of the potential realizations of such circuits is via single electron tunneling (SET) devices since SET technology enable simulation of noise and fluctuations in a fashion similar to Brownian search. In this paper, we perform a physical-information-theoretic analysis on the efficiency limitations in a Brownian NAND and half-adder circuits implemented using SET technology. The method we employed here establishes a solid ground that enables studying computational and physical features of this emerging technology on an equal footing, and yield fundamental lower bounds that provide valuable insights into how far its efficiency can be improved in principle. In order to provide a basis for comparison, we also analyze a NAND gate and half-adder circuit implemented in complementary metal oxide semiconductor technology to show how the fundamental bound of the Brownian circuit compares against a conventional paradigm.

Oxide Thin-Film Electronics using All-MXene Electrical Contacts

KAUST Repository

Wang, Zhenwei; Kim, Hyunho; Alshareef, Husam N.

2018-01-01

show balanced performance, including field-effect mobilities of 2.61 and 2.01 cm2 V−1 s−1 and switching ratios of 3.6 × 106 and 1.1 × 103, respectively. Further, complementary metal oxide semiconductor (CMOS) inverters are demonstrated. The CMOS

Absorbed dose by a CMOS in radiotherapy

Energy Technology Data Exchange (ETDEWEB)

Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

2011-10-15

Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

Science.gov (United States)

Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

2013-08-21

transport properties. Among this class of materials, various polymers can show well balanced electrons and holes mobility, therefore being indicated as ambipolar semiconductors, good environmental stability, and a small band-gap, which simplifies the tuning of charge injection. This opened up the possibility of taking advantage of the superior performances offered by complementary "CMOS-like" logic for the design of digital ICs, easing the scaling down of critical geometrical features, and achieving higher complexity from robust single gates (e.g., inverters) and test circuits (e.g., ring oscillators) to more complete circuits. Here, we review the recent progress in the development of printed ICs based on polymeric semiconductors suitable for large-volume micro- and nano-electronics applications. Particular attention is paid to the strategies proposed in the literature to design and synthesize high mobility polymers and to develop suitable printing tools and techniques to allow for improved patterning capability required for the down-scaling of devices in order to achieve the operation frequencies needed for applications, such as flexible radio-frequency identification (RFID) tags, near-field communication (NFC) devices, ambient electronics, and portable flexible displays. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Magnetotransport investigations of the two-dimensional metallic state in silicon metal-oxid-semiconductor structures

International Nuclear Information System (INIS)

Prinz, A.

2002-03-01

For more than two decades it was the predominant view among the physical community that the every two-dimensional (2D) disordered electron system becomes insulating as the temperature approaches the absolute zero temperature (0 Kelvin or -273.15 o C). Two-dimensional means that the movement of the charge carriers is confined in one direction by a potential so that the carriers can move freely only perpendicular to the confinement. The most famous physical realization of a 2D system is the silicon metal-oxide-semiconductor field effect transistor (Si-MOSFET). It is one of the basic elements of most electronic devices in our daily life. The working principle is very simple. Charges are attracted to the semiconductor-oxide interface by an electric field applied between the metallic gate and the semiconductor, so that a 2D conductive channel is formed. The charge density can be adjusted by the voltage from zero up to 10 13 cm -2 . In 1994 Kravchenko and coworkers made a very important discovery. They studied high mobility Si-MOSFETs and found that for densities below a certain critical value, nc, the resistivity increases as the temperature is decreased below 2 K, whereas for densities above $n c $ the resistivity decreases unexpectedly. The transition from insulating to metallic behavior, known as metal-insulator transition (MIT), was obviously a contradiction to the commonly accepted theories which predict insulating behavior for any density. The insulating behavior is a consequence of the wave properties of electrons which leads to interference in disordered media and thus to enhanced backscattering. In the subsequent years, experimental studies were performed on a variety of 2D systems, which qualitatively showed a similar behavior. All the investigated samples had one thing in common. The interaction energy between the carriers was considerable higher than their mean kinetic energy due to their movement in the 2D plane. Since the electron-electron interaction was

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

Science.gov (United States)

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

H+-type and OH−-type biological protonic semiconductors and complementary devices

Science.gov (United States)

Deng, Yingxin; Josberger, Erik; Jin, Jungho; Rousdari, Anita Fadavi; Helms, Brett A.; Zhong, Chao; Anantram, M. P.; Rolandi, Marco

2013-01-01

Proton conduction is essential in biological systems. Oxidative phosphorylation in mitochondria, proton pumping in bacteriorhodopsin, and uncoupling membrane potentials by the antibiotic Gramicidin are examples. In these systems, H+ hop along chains of hydrogen bonds between water molecules and hydrophilic residues – proton wires. These wires also support the transport of OH− as proton holes. Discriminating between H+ and OH− transport has been elusive. Here, H+ and OH− transport is achieved in polysaccharide- based proton wires and devices. A H+- OH− junction with rectifying behaviour and H+-type and OH−-type complementary field effect transistors are demonstrated. We describe these devices with a model that relates H+ and OH− to electron and hole transport in semiconductors. In turn, the model developed for these devices may provide additional insights into proton conduction in biological systems. PMID:24089083

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

Directory of Open Access Journals (Sweden)

Chris R. Bowen

2011-05-01

Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

Semiconductor-metal transition of Se in Ru-Se Catalyst Nanoparticles

Science.gov (United States)

Babu, P. K.; Lewera, Adam; Oldfield, Eric; Wieckowski, Andrzej

2009-03-01

Ru-Se composite nanoparticles are promising catalysts for the oxygen reduction reaction (ORR) in fuel cells. Though the role of Se in enhancing the chemical stability of Ru nanoparticles is well established, the microscopic nature of Ru-Se interaction was not clearly understood. We carried out a combined investigation of ^77Se NMR and XPS on Ru-Se nanoparticles and our results indicate that Se, a semiconductor in elemental form, becomes metallic when interacting with Ru. ^77Se spin-lattice relaxation rates are found to be proportional to T, the well-known Korringa behavior characteristic of metals. The NMR results are supported by the XPS binding energy shifts which suggest that a possible Ru->Se charge transfer could be responsible for the semiconductor->metal transition of Se which also makes Ru less susceptible to oxidation during ORR.

Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom

Directory of Open Access Journals (Sweden)

Hang Song

2017-01-01

Full Text Available A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

Charge-flow structures as polymeric early-warning fire alarm devices. M.S. Thesis; [metal oxide semiconductors

Science.gov (United States)

Sechen, C. M.; Senturia, S. D.

1977-01-01

The charge-flow transistor (CFT) and its applications for fire detection and gas sensing were investigated. The utility of various thin film polymers as possible sensing materials was determined. One polymer, PAPA, showed promise as a relative humidity sensor; two others, PFI and PSB, were found to be particularly suitable for fire detection. The behavior of the charge-flow capacitor, which is basically a parallel-plate capacitor with a polymer-filled gap in the metallic tip electrode, was successfully modeled as an RC transmission line. Prototype charge-flow transistors were fabricated and tested. The effective threshold voltage of this metal oxide semiconductor was found to be dependent on whether surface or bulk conduction in the thin film was dominant. Fire tests with a PFI-coated CFT indicate good sensitivity to smouldering fires.

Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

International Nuclear Information System (INIS)

Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

2014-01-01

This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO 2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

Mathematical Modelling and Simulation of Electrical Circuits and Semiconductor Devices

CERN Document Server

Merten, K; Bulirsch, R

1990-01-01

Numerical simulation and modelling of electric circuits and semiconductor devices are of primal interest in today's high technology industries. At the Oberwolfach Conference more than forty scientists from around the world, in­ cluding applied mathematicians and electrical engineers from industry and universities, presented new results in this area of growing importance. The contributions to this conference are presented in these proceedings. They include contributions on special topics of current interest in circuit and device simulation, as well as contributions that present an overview of the field. In the semiconductor area special lectures were given on mixed finite element methods and iterative procedures for the solution of large linear systems. For three dimensional models new discretization procedures including software packages were presented. Con­ nections between semiconductor equations and the Boltzmann equation were shown as well as relations to the quantum transport equation. Other issues dis...

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

Directory of Open Access Journals (Sweden)

Cheng-Yang Liu

2009-12-01

Full Text Available The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa.

Metal-core@metal oxide-shell nanomaterials for gas-sensing applications: a review

Energy Technology Data Exchange (ETDEWEB)

Mirzaei, A.; Janghorban, K.; Hashemi, B. [Shiraz University, Department of Materials Science and Engineering (Iran, Islamic Republic of); Neri, G., E-mail: gneri@unime.it [University of Messina, Department of Electronic Engineering, Chemistry and Industrial Engineering (Italy)

2015-09-15

With an ever-increasing number of applications in many advanced fields, gas sensors are becoming indispensable devices in our daily life. Among different types of gas sensors, conductometric metal oxide semiconductor (MOS) gas sensors are found to be the most appealing for advanced applications in the automotive, biomedical, environmental, and safety sectors because of the their high sensitivity, reduced size, and low cost. To improve their sensing characteristics, new metal oxide-based nanostructures have thus been proposed in recent years as sensing materials. In this review, we extensively review gas-sensing properties of core@ shell nanocomposites in which metals as the core and metal oxides as the shell structure, both of nanometer sizes, are assembled into a single metal@metal oxide core–shell. These nanostructures not only combine the properties of both noble metals and metal oxides, but also bring unique synergetic functions in comparison with single-component materials. Up-dated achievements in the synthesis and characterization of metal@metal oxide core–shell nanostructures as well as their use in MOS sensors are here reported with the main objective of providing an overview about their gas-sensing properties.

Mechanisms of current flow in metal-semiconductor ohmic contacts

International Nuclear Information System (INIS)

Blank, T. V.; Gol'dberg, Yu. A.

2007-01-01

Published data on the properties of metal-semiconductor ohmic contacts and mechanisms of current flow in these contacts (thermionic emission, field emission, thermal-field emission, and also current flow through metal shunts) are reviewed. Theoretical dependences of the resistance of an ohmic contact on temperature and the charge-carrier concentration in a semiconductor were compared with experimental data on ohmic contacts to II-VI semiconductors (ZnSe, ZnO), III-V semiconductors (GaN, AlN, InN, GaAs, GaP, InP), Group IV semiconductors (SiC, diamond), and alloys of these semiconductors. In ohmic contacts based on lightly doped semiconductors, the main mechanism of current flow is thermionic emission with the metal-semiconductor potential barrier height equal to 0.1-0.2 eV. In ohmic contacts based on heavily doped semiconductors, the current flow is effected owing to the field emission, while the metal-semiconductor potential barrier height is equal to 0.3-0.5 eV. In alloyed In contacts to GaP and GaN, a mechanism of current flow that is not characteristic of Schottky diodes (current flow through metal shunts formed by deposition of metal atoms onto dislocations or other imperfections in semiconductors) is observed

P-type Oxide Semiconductors for Transparent & Energy Efficient Electronics

KAUST Repository

Wang, Zhenwei

2018-03-11

Emerging transparent semiconducting oxide (TSO) materials have achieved their initial commercial success in the display industry. Due to the advanced electrical performance, TSOs have been adopted either to improve the performance of traditional displays or to demonstrate the novel transparent and flexible displays. However, due to the lack of feasible p-type TSOs, the applications of TSOs is limited to unipolar (n-type TSOs) based devices. Compared with the prosperous n-type TSOs, the performance of p-type counterparts is lag behind. However, after years of discovery, several p-type TSOs are confirmed with promising performance, for example, tin monoxide (SnO). By using p-type SnO, excellent transistor field-effect mobility of 6.7 cm2 V-1 s-1 has been achieved. Motivated by this encouraging performance, this dissertation is devoted to further evaluate the feasibility of integrating p-type SnO in p-n junctions and complementary metal oxide semiconductor (CMOS) devices. CMOS inverters are fabricated using p-type SnO and in-situ formed n-type tin dioxide (SnO2). The semiconductors are simultaneously sputtered, which simplifies the process of CMOS inverters. The in-situ formation of SnO2 phase is achieved by selectively sputtering additional capping layer, which serves as oxygen source and helps to balance the process temperature for both types of semiconductors. Oxides based p-n junctions are demonstrated between p-type SnO and n-type SnO2 by magnetron sputtering method. Diode operating ideality factor of 3.4 and rectification ratio of 103 are achieved. A large temperature induced knee voltage shift of 20 mV oC-1 is observed, and explained by the large band gap and shallow states in SnO, which allows minor adjustment of band structure in response to the temperature change. Finally, p-type SnO is used to demonstrating the hybrid van der Waals heterojunctions (vdWHs) with two-dimensional molybdenum disulfide (2D MoS2) by mechanical exfoliation. The hybrid vdWHs show

Positron annihilation in a metal-oxide semiconductor studied by using a pulsed monoenergetic positron beam

Science.gov (United States)

Uedono, A.; Wei, L.; Tanigawa, S.; Suzuki, R.; Ohgaki, H.; Mikado, T.; Ohji, Y.

1993-12-01

The positron annihilation in a metal-oxide semiconductor was studied by using a pulsed monoenergetic positron beam. Lifetime spectra of positrons were measured as a function of incident positron energy for a polycrystalline Si(100 nm)/SiO2(400 nm)/Si specimen. Applying a gate voltage between the polycrystalline Si film and the Si substrate, positrons implanted into the specimen were accumulated at the SiO2/Si interface. From the measurements, it was found that the annihilation probability of ortho-positronium (ortho-Ps) drastically decreased at the SiO2/Si interface. The observed inhibition of the Ps formation was attributed to an interaction between positrons and defects at the SiO2/Si interface.

Fundamentals of semiconductor devices

CERN Document Server

Lindmayer, Joseph

1965-01-01

Semiconductor properties ; semiconductor junctions or diodes ; transistor fundamentals ; inhomogeneous impurity distributions, drift or graded-base transistors ; high-frequency properties of transistors ; band structure of semiconductors ; high current densities and mechanisms of carrier transport ; transistor transient response and recombination processes ; surfaces, field-effect transistors, and composite junctions ; additional semiconductor characteristics ; additional semiconductor devices and microcircuits ; more metal, insulator, and semiconductor combinations for devices ; four-pole parameters and configuration rotation ; four-poles of combined networks and devices ; equivalent circuits ; the error function and its properties ; Fermi-Dirac statistics ; useful physical constants.

Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

KAUST Repository

Lechuga Aranda, Jesus Javier

2016-05-01

Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

Fermi level dependent native defect formation: Consequences for metal-semiconductor and semiconductor-semiconductor interfaces

International Nuclear Information System (INIS)

Walukiewicz, W.

1988-02-01

The amphoteric native defect model of the Schottky barrier formation is used to analyze the Fermi level pinning at metal/semiconductor interfaces for submonolayer metal coverages. It is assumed that the energy required for defect generation is released in the process of surface back-relaxation. Model calculations for metal/GaAs interfaces show a weak dependence of the Fermi level pinning on the thickness of metal deposited at room temperature. This weak dependence indicates a strong dependence of the defect formation energy on the Fermi level, a unique feature of amphoteric native defects. This result is in very good agreement with experimental data. It is shown that a very distinct asymmetry in the Fermi level pinning on p- and n-type GaAs observed at liquid nitrogen temperatures can be understood in terms of much different recombination rates for amphoteric native defects in those two types of materials. Also, it is demonstrated that the Fermi level stabilization energy, a central concept of the amphoteric defect system, plays a fundamental role in other phenomena in semiconductors such as semiconductor/semiconductor heterointerface intermixing and saturation of free carrier concentration. 33 refs., 6 figs

Group IIB-VIA semiconductor oxide cluster ions

Science.gov (United States)

Jayasekharan, Thankan

2018-05-01

Metal oxide cluster ions, MnOm± (M = Zn, Cd) and HgnOm- of various stoichiometry have been generated from solid IIB-VIA semiconductor oxides targets, (ZnO(s), CdO(s), and HgO(s)) by using pulse laser desorption ionization time of flight mass spectrometry with a laser of λ = 355 nm. Analysis of mass spectral data indicates the formation of stoichiometric cluster ions viz., (ZnO)n=1-30+ and (CdO)n=1-40+ along with -O bound anions, (ZnO)n=1-30O-, (CdO)n=1-40O- and (HgO)n=1-36O- from their respective solids. Further, metal oxoanions such as ZnOn=2,3-, CdOn=2,3,6-, and HgOn=2,3,6,7- have also been noted signifying the higher coordination ability of both Cd and Hg with O/O2/O3 species.

Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors with sulfur passivation

International Nuclear Information System (INIS)

Tan Zhen; Zhao Lian-Feng; Wang Jing; Xu Jun

2014-01-01

Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors (MOSCAPs) with sulfur passivation were investigated and the chemical mechanisms of the sulfur passivation process were carefully studied. It was shown that the sulfur passivation treatment could reduce the interface trap density D it of the HfAlO/GaSb interface by 35% and reduce the equivalent oxide thickness (EOT) from 8 nm to 4 nm. The improved properties are due to the removal of the native oxide layer, as was proven by x-ray photoelectron spectroscopy measurements and high-resolution cross-sectional transmission electron microscopy (HRXTEM) results. It was also found that GaSb-based MOSCAPs with HfAlO gate dielectrics have interfacial properties superior to those using HfO 2 or Al 2 O 3 dielectric layers. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Metal-semiconductor interface in extreme temperature conditions

International Nuclear Information System (INIS)

Bulat, L.P.; Erofeeva, I.A.; Vorobiev, Yu.V.; Gonzalez-Hernandez, J.

2008-01-01

We present an investigation of electrons' and phonons' temperatures in the volume of a semiconductor (or metal) sample and at the interface between metal and semiconductor. Two types of mismatch between electrons' and phonons' temperatures take place: at metal-semiconductor interfaces and in the volume of the sample. The temperature mismatch leads to nonlinear terms in expressions for heat and electricity transport. The nonlinear effects should be taken into consideration in the study of electrical and heat transport in composites and in electronic chips

Metal-semiconductor, composite radiation detectors

International Nuclear Information System (INIS)

Orvis, W.J.; Yee, J.H.; Fuess, D.

1992-12-01

In 1989, Naruse and Hatayama of Toshiba published a design for an increased efficiency x-ray detector. The design increased the efficiency of a semiconductor detector by interspersing layers of high-z metal within it. Semiconductors such as silicon make good, high-resolution radiation detectors, but they have low efficiency because they are low-z materials (z = 14). High-z metals, on the other hand, are good absorbers of high-energy photons. By interspersing high-z metal layers with semiconductor layers, Naruse and Hatayama combined the high absorption efficiency of the high-z metals with the good detection capabilities of a semiconductor. This project is an attempt to use the same design to produce a high-efficiency, room temperature gamma ray detector. By their nature, gamma rays require thicker metal layers to efficiently absorb them. These thicker layers change the behavior of the detector by reducing the resolution, compared to a solid state detector, and shifting the photopeak by a predictable amount. During the last year, the authors have procured and tested a commercial device with operating characteristics similar to those of a single layer of the composite device. They have modeled the radiation transport in a multi-layered device, to verify the initial calculations of layer thickness and composition. They have modeled the electrostatic field in different device designs to locate and remove high-field regions that can cause device breakdown. They have fabricated 14 single layer prototypes

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

Science.gov (United States)

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Study of CMOS micromachined self-oscillating loop utilizing a phase-locked loop-driving circuit

International Nuclear Information System (INIS)

Li, Hsin-Chih; Tseng, Sheng-Hsiang; Lu, Michael S.-C.; Huang, Po-Chiun

2012-01-01

This work describes the design and characterization of integrated CMOS (complementary metal oxide semiconductor) oscillators comprising a capacitively transduced micromechanical resonator and a phase-locked loop (PLL) driving circuit. Three oscillator schemes are studied and compared, including direct feedback, direct feedback containing a PLL and hybrid direct feedback plus a PLL. PLL is known for its capability in automatic tuning and tracking of a reference signal. Inclusion of a PLL is beneficial for sustaining oscillations at resonant frequencies within its capture range. The micromechanical resonator has a measured resonant frequency of 117.3 kHz. The CMOS PLL circuit has a closed-loop bandwidth of 1.8 kHz with a capture range between 111 kHz and 118.4 kHz. The start-up times for oscillation are shortened in the two schemes utilizing a PLL, since it provides an initial driving signal at its free-running frequency. The lock-in time is also reduced by increasing the proportion of PLL drive in the hybrid scheme. The measured noises for the three oscillator schemes are similar with a value of −75 dB below the resonant peak at a 10 Hz offset. (paper)

Electron Band Alignment at Interfaces of Semiconductors with Insulating Oxides: An Internal Photoemission Study

Directory of Open Access Journals (Sweden)

Valeri V. Afanas'ev

2014-01-01

Full Text Available Evolution of the electron energy band alignment at interfaces between different semiconductors and wide-gap oxide insulators is examined using the internal photoemission spectroscopy, which is based on observations of optically-induced electron (or hole transitions across the semiconductor/insulator barrier. Interfaces of various semiconductors ranging from the conventional silicon to the high-mobility Ge-based (Ge, Si1-xGex, Ge1-xSnx and AIIIBV group (GaAs, InxGa1-xAs, InAs, GaP, InP, GaSb, InSb materials were studied revealing several general trends in the evolution of band offsets. It is found that in the oxides of metals with cation radii larger than ≈0.7 Å, the oxide valence band top remains nearly at the same energy (±0.2 eV irrespective of the cation sort. Using this result, it becomes possible to predict the interface band alignment between oxides and semiconductors as well as between dissimilar insulating oxides on the basis of the oxide bandgap width which are also affected by crystallization. By contrast, oxides of light elements, for example, Be, Mg, Al, Si, and Sc exhibit significant shifts of the valence band top. General trends in band lineup variations caused by a change in the composition of semiconductor photoemission material are also revealed.

The competing oxide and sub-oxide formation in metal-oxide molecular beam epitaxy

International Nuclear Information System (INIS)

Vogt, Patrick; Bierwagen, Oliver

2015-01-01

The hetero-epitaxial growth of the n-type semiconducting oxides β-Ga 2 O 3 , In 2 O 3 , and SnO 2 on c- and r-plane sapphire was performed by plasma-assisted molecular beam epitaxy. The growth-rate and desorbing flux from the substrate were measured in-situ under various oxygen to metal ratios by laser reflectometry and quadrupole mass spectrometry, respectively. These measurements clarified the role of volatile sub-oxide formation (Ga 2 O, In 2 O, and SnO) during growth, the sub-oxide stoichiometry, and the efficiency of oxide formation for the three oxides. As a result, the formation of the sub-oxides decreased the growth-rate under metal-rich growth conditions and resulted in etching of the oxide film by supplying only metal flux. The flux ratio for the exclusive formation of the sub-oxide (e.g., the p-type semiconductor SnO) was determined, and the efficiency of oxide formation was found to be the highest for SnO 2 , somewhat lower for In 2 O 3 , and the lowest for Ga 2 O 3 . Our findings can be generalized to further oxides that possess related sub-oxides

A Customized Metal Oxide Semiconductor-Based Gas Sensor Array for Onion Quality Evaluation: System Development and Characterization

Directory of Open Access Journals (Sweden)

Tharun Konduru

2015-01-01

Full Text Available A gas sensor array, consisting of seven Metal Oxide Semiconductor (MOS sensors that are sensitive to a wide range of organic volatile compounds was developed to detect rotten onions during storage. These MOS sensors were enclosed in a specially designed Teflon chamber equipped with a gas delivery system to pump volatiles from the onion samples into the chamber. The electronic circuit mainly comprised a microcontroller, non-volatile memory chip, and trickle-charge real time clock chip, serial communication chip, and parallel LCD panel. User preferences are communicated with the on-board microcontroller through a graphical user interface developed using LabVIEW. The developed gas sensor array was characterized and the discrimination potential was tested by exposing it to three different concentrations of acetone (ketone, acetonitrile (nitrile, ethyl acetate (ester, and ethanol (alcohol. The gas sensor array could differentiate the four chemicals of same concentrations and different concentrations within the chemical with significant difference. Experiment results also showed that the system was able to discriminate two concentrations (196 and 1964 ppm of methlypropyl sulfide and two concentrations (145 and 1452 ppm of 2-nonanone, two key volatile compounds emitted by rotten onions. As a proof of concept, the gas sensor array was able to achieve 89% correct classification of sour skin infected onions. The customized low-cost gas sensor array could be a useful tool to detect onion postharvest diseases in storage.

Electronic properties of semiconductor surfaces and metal/semiconductor interfaces

Energy Technology Data Exchange (ETDEWEB)

Tallarida, M.

2005-05-15

This thesis reports investigations of the electronic properties of a semiconductor surface (silicon carbide), a reactive metal/semiconductor interface (manganese/silicon) and a non-reactive metal/semiconductor interface (aluminum-magnesium alloy/silicon). The (2 x 1) reconstruction of the 6H-SiC(0001) surface has been obtained by cleaving the sample along the (0001) direction. This reconstruction has not been observed up to now for this compound, and has been compared with those of similar elemental semiconductors of the fourth group of the periodic table. This comparison has been carried out by making use of photoemission spectroscopy, analyzing the core level shifts of both Si 2p and C 1s core levels in terms of charge transfer between atoms of both elements and in different chemical environments. From this comparison, a difference between the reconstruction on the Si-terminated and the C-terminated surface was established, due to the ionic nature of the Si-C bond. The growth of manganese films on Si(111) in the 1-5 ML thickness range has been studied by means of LEED, STM and photoemission spectroscopy. By the complementary use of these surface science techniques, two different phases have been observed for two thickness regimes (<1 ML and >1 ML), which exhibit a different electronic character. The two reconstructions, the (1 x 1)-phase and the ({radical}3 x {radical}3)R30 -phase, are due to silicide formation, as observed in core level spectroscopy. The growth proceeds via island formation in the monolayer regime, while the thicker films show flat layers interrupted by deep holes. On the basis of STM investigations, this growth mode has been attributed to strain due to lattice mismatch between the substrate and the silicide. Co-deposition of Al and Mg onto a Si(111) substrate at low temperature (100K) resulted in the formation of thin alloy films. By varying the relative content of both elements, the thin films exhibited different electronic properties

Memory characteristics of Au nanocrystals embedded in metal-oxide-semiconductor structure by using atomic-layer-deposited Al2O3 as control oxide

International Nuclear Information System (INIS)

Wang, C.-C.; Chiou, Y.-K.; Chang, C.-H.; Tseng, J.-Y.; Wu, L.-J.; Chen, C.-Y.; Wu, T.-B.

2007-01-01

The nonvolatile memory characteristics of metal-oxide-semiconductor (MOS) structures containing Au nanocrystals in the Al 2 O 3 /SiO 2 matrix were studied. In this work, we have demonstrated that the use of Al 2 O 3 as control oxide prepared by atomic-layer-deposition enhances the erase speed of the MOS capacitors. A giant capacitance-voltage hysteresis loop and a very short erase time which is lower than 1 ms can be obtained. Compared with the conventional floating-gate electrically erasable programmable read-only memories, the erase speed was promoted drastically. In addition, very low leakage current and large turn-around voltage resulting from electrons or holes stored in the Au nanocrystals were found in the current-voltage relation of the MOS capacitors

Metal oxide nanostructures as gas sensing devices

CERN Document Server

Eranna, G

2016-01-01

Metal Oxide Nanostructures as Gas Sensing Devices explores the development of an integrated micro gas sensor that is based on advanced metal oxide nanostructures and is compatible with modern semiconductor fabrication technology. This sensor can then be used to create a compact, low-power, handheld device for analyzing air ambience. The book first covers current gas sensing tools and discusses the necessity for miniaturized sensors. It then focuses on the materials, devices, and techniques used for gas sensing applications, such as resistance and capacitance variations. The author addresses the issues of sensitivity, concentration, and temperature dependency as well as the response and recovery times crucial for sensors. He also presents techniques for synthesizing different metal oxides, particularly those with nanodimensional structures. The text goes on to highlight the gas sensing properties of many nanostructured metal oxides, from aluminum and cerium to iron and titanium to zinc and zirconium. The final...

An area and power-efficient analog li-ion battery charger circuit.

Science.gov (United States)

Do Valle, Bruno; Wentz, Christian T; Sarpeshkar, Rahul

2011-04-01

The demand for greater battery life in low-power consumer electronics and implantable medical devices presents a need for improved energy efficiency in the management of small rechargeable cells. This paper describes an ultra-compact analog lithium-ion (Li-ion) battery charger with high energy efficiency. The charger presented here utilizes the tanh basis function of a subthreshold operational transconductance amplifier to smoothly transition between constant-current and constant-voltage charging regimes without the need for additional area- and power-consuming control circuitry. Current-domain circuitry for end-of-charge detection negates the need for precision-sense resistors in either the charging path or control loop. We show theoretically and experimentally that the low-frequency pole-zero nature of most battery impedances leads to inherent stability of the analog control loop. The circuit was fabricated in an AMI 0.5-μm complementary metal-oxide semiconductor process, and achieves 89.7% average power efficiency and an end voltage accuracy of 99.9% relative to the desired target 4.2 V, while consuming 0.16 mm(2) of chip area. To date and to the best of our knowledge, this design represents the most area-efficient and most energy-efficient battery charger circuit reported in the literature.

Positive and negative gain exceeding unity magnitude in silicon quantum well metal-oxide-semiconductor transistors

Science.gov (United States)

Hu, Gangyi; Wijesinghe, Udumbara; Naquin, Clint; Maggio, Ken; Edwards, H. L.; Lee, Mark

2017-10-01

Intrinsic gain (AV) measurements on Si quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors show that these devices can have |AV| > 1 in quantum transport negative transconductance (NTC) operation at room temperature. QW NMOS devices were fabricated using an industrial 45 nm technology node process incorporating ion implanted potential barriers to define a lateral QW in the conduction channel under the gate. While NTC at room temperature arising from transport through gate-controlled QW bound states has been previously established, it was unknown whether the quantum NTC mechanism could support gain magnitude exceeding unity. Bias conditions were found giving both positive and negative AV with |AV| > 1 at room temperature. This result means that QW NMOS devices could be useful in amplifier and oscillator applications.

Radiation-hardened gate-around n-MOSFET structure for radiation-tolerant application-specific integrated circuits

International Nuclear Information System (INIS)

Lee, Min Su; Lee, Hee Chul

2012-01-01

To overcome the total ionizing dose effect on an n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET), we designed a radiation-hardened gate-around n-MOSFET structure and evaluated it through a radiation-exposure experiment. Each test device was fabricated in a commercial 0.35-micron complementary metal-oxide-semiconductor (CMOS) process. The fabricated devices were evaluated under a total dose of 1 Mrad (Si) at a dose rate of 250 krad/h to obtain very high reliability for space electronics. The experimental results showed that the gate-around n-MOSFET structure had very good performance against 1 Mrad (Si) of gamma radiation, while the conventional n-MOSFET experienced a considerable amount of radiation-induced leakage current. Furthermore, a source follower designed with the gate-around transistor worked properly at 1 Mrad (Si) of gamma radiation while a source follower designed with the conventional n-MOSFET lost its functionality.

Ultrawide band gap amorphous oxide semiconductor, Ga–Zn–O

Energy Technology Data Exchange (ETDEWEB)

Kim, Junghwan, E-mail: JH.KIM@lucid.msl.titech.ac.jp [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Miyokawa, Norihiko; Sekiya, Takumi; Ide, Keisuke [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Toda, Yoshitake [Materials Research Center for Element Strategy, Tokyo Institute of Technology, Mailbox SE-6, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Hiramatsu, Hidenori; Hosono, Hideo; Kamiya, Toshio [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Mailbox SE-6, 4259 Nagatsuta, Midori-ku, Yokohama (Japan)

2016-09-01

We fabricated amorphous oxide semiconductor films, a-(Ga{sub 1–x}Zn{sub x})O{sub y}, at room temperature on glass, which have widely tunable band gaps (E{sub g}) ranging from 3.47–4.12 eV. The highest electron Hall mobility ~ 7 cm{sup 2} V{sup −1} s{sup −1} was obtained for E{sub g} = ~ 3.8 eV. Ultraviolet photoemission spectroscopy revealed that the increase in E{sub g} with increasing the Ga content comes mostly from the deepening of the valence band maximum level while the conduction band minimum level remains almost unchanged. These characteristics are explained by their electronic structures. As these films can be fabricated at room temperature on plastic, this achievement extends the applications of flexible electronics to opto-electronic integrated circuits associated with deep ultraviolet region. - Highlights: • Incorporation of H/H{sub 2}O stabilizes the amorphous phase. • Ultrawide band gap (~ 3.8 eV) amorphous oxide semiconductor was fabricated. • The increase in band gap comes mostly from the deepening of the valence band maximum level. • Donor level is more likely aligned to the valence band maximum level.

Design of 5.8 GHz Integrated Antenna on 180nm Complementary Metal Oxide Semiconductor (CMOS) Technology

Science.gov (United States)

Razak, A. H. A.; Shamsuddin, M. I. A.; Idros, M. F. M.; Halim, A. K.; Ahmad, A.; Junid, S. A. M. Al

2018-03-01

This project discusses the design and simulation performances of integrated loop antenna. Antenna is one of the main parts in any wireless radio frequency integrated circuit (RFIC). Naturally, antenna is the bulk in any RFIC design. Thus, this project aims to implement an integrated antenna on a single chip making the end product more compact. This project targets 5.8 GHz as the operating frequency of the integrated antenna for a transceiver module based on Silterra CMOS 180nm technology. The simulation of the antenna was done by using High Frequency Structure Simulator (HFSS). This software is industrial standard software that been used to simulate all electromagnetic effect including antenna simulation. This software has ability to simulate frequency at range of 100 MHz to 4 THz. The simulation set up in 3 dimension structure with driven terminal. The designed antenna has 1400um of diameter and placed on top metal layer. Loop configuration of the antenna has been chosen as the antenna design. From the configuration, it is able to make the chip more compact. The simulation shows that the antenna has single frequency band at center frequency 5.8 GHz with -48.93dB. The antenna radiation patterns shows, the antenna radiate at omnidirectional. From the simulation result, it could be concluded that the antenna have a good radiation pattern and propagation for wireless communication.

Deep electron traps in HfO_2-based metal-oxide-semiconductor capacitors

International Nuclear Information System (INIS)

Salomone, L. Sambuco; Lipovetzky, J.; Carbonetto, S.H.; García Inza, M.A.; Redin, E.G.; Campabadal, F.

2016-01-01

Hafnium oxide (HfO_2) is currently considered to be a good candidate to take part as a component in charge-trapping nonvolatile memories. In this work, the electric field and time dependences of the electron trapping/detrapping processes are studied through a constant capacitance voltage transient technique on metal-oxide-semiconductor capacitors with atomic layer deposited HfO_2 as insulating layer. A tunneling-based model is proposed to reproduce the experimental results, obtaining fair agreement between experiments and simulations. From the fitting procedure, a band of defects is identified, located in the first 1.7 nm from the Si/HfO_2 interface at an energy level E_t = 1.59 eV below the HfO_2 conduction band edge with density N_t = 1.36 × 10"1"9 cm"−"3. A simplified analytical version of the model is proposed in order to ease the fitting procedure for the low applied voltage case considered in this work. - Highlights: • We characterized deep electron trapping/detrapping in HfO_2 structures. • We modeled the experimental results through a tunneling-based model. • We obtained an electron trap energy level of 1.59 eV below conduction band edge. • We obtained a spatial trap distribution extending 1.7 nm within the insulator. • A simplified tunneling front model is able to reproduce the experimental results.

Development of semiconductor electronics

International Nuclear Information System (INIS)

Bardeen, John.

1977-01-01

In 1931, Wilson applied Block's theory about the energy bands for the motion of electrons in a crystal lattice to semiconductors and showed that conduction can take place in two different ways, by electrons and by holes. Not long afterwards Frenkel showed that these carriers can flow by diffusion in a concentration gradient as well as under the influence of an electric field and wrote down equations for the current flow. The third major contribution, in the late 1930's was the explanation of rectification at a metalsemiconductor contact by Mott and more completely by Schottky. In late 1947 the first transistor of the point contact type was invented by Brattin, Shockley and Bardeen. Then after single crystals of Ge were grown, the junction transistor was developed by the same group. The first silicon transistors appeared in 1954. Then an important step was discovery of the planar transistor by Hoenri in 1960 which led to development of integrated circuits by 1962. Many transistors are produced by batch processing on a slice of silicon. Then in 1965 Mos (Metal-Oxide Semiconductor) transistor and in 1968 LSI (Large Scale Intergration circuits) were developed. Aside from electronic circuits, there are many other applications of semiconductors, including junction power rectifiers, junction luminescence (including lasers), solar batteries, radiation detectors, microwave oscillators and charged-coupled devices for computer memories and devices. One of the latest developments is a microprocessor with thousands of transistors and associated circuitry on a single small chip of silicon. It can be programmed to provide a variety of circuit functions, thus it is not necessary to go through the great expense of LSI's for each desired function, but to use standard microprocessors and program to do the job

A unique metal-semiconductor interface and resultant electron transfer phenomenon

OpenAIRE

Taft, S. L.

2012-01-01

An unusual electron transfer phenomenon has been identified from an n-type semiconductor to Schottky metal particles, the result of a unique metal semiconductor interface that results when the metal particles are grown from the semiconductor substrate. The unique interface acts as a one-way (rectifying) open gateway and was first identified in reduced rutile polycrystalline titanium dioxide (an n-type semiconductor) to Group VIII (noble) metal particles. The interface significantly affects th...

On-chip single photon filtering and multiplexing in hybrid quantum photonic circuits.

Science.gov (United States)

Elshaari, Ali W; Zadeh, Iman Esmaeil; Fognini, Andreas; Reimer, Michael E; Dalacu, Dan; Poole, Philip J; Zwiller, Val; Jöns, Klaus D

2017-08-30

Quantum light plays a pivotal role in modern science and future photonic applications. Since the advent of integrated quantum nanophotonics different material platforms based on III-V nanostructures-, colour centers-, and nonlinear waveguides as on-chip light sources have been investigated. Each platform has unique advantages and limitations; however, all implementations face major challenges with filtering of individual quantum states, scalable integration, deterministic multiplexing of selected quantum emitters, and on-chip excitation suppression. Here we overcome all of these challenges with a hybrid and scalable approach, where single III-V quantum emitters are positioned and deterministically integrated in a complementary metal-oxide-semiconductor-compatible photonic circuit. We demonstrate reconfigurable on-chip single-photon filtering and wavelength division multiplexing with a foot print one million times smaller than similar table-top approaches, while offering excitation suppression of more than 95 dB and efficient routing of single photons over a bandwidth of 40 nm. Our work marks an important step to harvest quantum optical technologies' full potential.Combining different integration platforms on the same chip is currently one of the main challenges for quantum technologies. Here, Elshaari et al. show III-V Quantum Dots embedded in nanowires operating in a CMOS compatible circuit, with controlled on-chip filtering and tunable routing.

ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

Science.gov (United States)

Vasile, Stefan; Lipson, Jerold

2012-01-01

The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

Spin-dependent transport properties of a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor structure

Energy Technology Data Exchange (ETDEWEB)

Kanaki, Toshiki, E-mail: kanaki@cryst.t.u-tokyo.ac.jp; Asahara, Hirokatsu; Ohya, Shinobu, E-mail: ohya@cryst.t.u-tokyo.ac.jp; Tanaka, Masaaki, E-mail: masaaki@ee.t.u-tokyo.ac.jp [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan)

2015-12-14

We fabricate a vertical spin metal-oxide-semiconductor field-effect transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current I{sub DS} by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate I{sub DS} by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale.

Spin-dependent transport properties of a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor structure

International Nuclear Information System (INIS)

Kanaki, Toshiki; Asahara, Hirokatsu; Ohya, Shinobu; Tanaka, Masaaki

2015-01-01

We fabricate a vertical spin metal-oxide-semiconductor field-effect transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current I DS by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate I DS by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale

Theoretical calculations of positron lifetimes for metal oxides

International Nuclear Information System (INIS)

Mizuno, Masataka; Araki, Hideki; Shirai, Yasuharu

2004-01-01

Our recent positron lifetime measurements for metal oxides suggest that positron lifetimes of bulk state in metal oxides are shorter than previously reported values. We have performed theoretical calculations of positron lifetimes for bulk and vacancy states in MgO and ZnO using first-principles electronic structure calculations and discuss the validity of positron lifetime calculations for insulators. By comparing the calculated positron lifetimes to the experimental values, it wa found that the semiconductor model well reproduces the experimental positron lifetime. The longer positron lifetime previously reported can be considered to arise from not only the bulk but also from the vacancy induced by impurities. In the case of cation vacancy, the calculated positron lifetime based on semiconductor model is shorter than the experimental value, which suggests that the inward relaxation occurs around the cation vacancy trapping the positron. (author)

Absorption properties of metal-semiconductor hybrid nanoparticles.

Science.gov (United States)

Shaviv, Ehud; Schubert, Olaf; Alves-Santos, Marcelo; Goldoni, Guido; Di Felice, Rosa; Vallée, Fabrice; Del Fatti, Natalia; Banin, Uri; Sönnichsen, Carsten

2011-06-28

The optical response of hybrid metal-semiconductor nanoparticles exhibits different behaviors due to the proximity between the disparate materials. For some hybrid systems, such as CdS-Au matchstick-shaped hybrids, the particles essentially retain the optical properties of their original components, with minor changes. Other systems, such as CdSe-Au dumbbell-shaped nanoparticles, exhibit significant change in the optical properties due to strong coupling between the two materials. Here, we study the absorption of these hybrids by comparing experimental results with simulations using the discrete dipole approximation method (DDA) employing dielectric functions of the bare components as inputs. For CdS-Au nanoparticles, the DDA simulation provides insights on the gold tip shape and its interface with the semiconductor, information that is difficult to acquire by experimental means alone. Furthermore, the qualitative agreement between DDA simulations and experimental data for CdS-Au implies that most effects influencing the absorption of this hybrid system are well described by local dielectric functions obtained separately for bare gold and CdS nanoparticles. For dumbbell shaped CdSe-Au, we find a shortcoming of the electrodynamic model, as it does not predict the "washing out" of the optical features of the semiconductor and the metal observed experimentally. The difference between experiment and theory is ascribed to strong interaction of the metal and semiconductor excitations, which spectrally overlap in the CdSe case. The present study exemplifies the employment of theoretical approaches used to describe the optical properties of semiconductors and metal nanoparticles, to achieve better understanding of the behavior of metal-semiconductor hybrid nanoparticles.

Ultraviolet-visible electroluminescence from metal-oxide-semiconductor devices with CeO2 films on silicon

International Nuclear Information System (INIS)

Lv, Chunyan; Zhu, Chen; Wang, Canxing; Li, Dongsheng; Ma, Xiangyang; Yang, Deren

2015-01-01

We report on ultraviolet-visible (UV-Vis) electroluminescence (EL) from metal-oxide-semiconductor (MOS) devices with the CeO 2 films annealed at low temperatures. At the same injection current, the UV-Vis EL from the MOS device with the 550 °C-annealed CeO 2 film is much stronger than that from the counterpart with the 450 °C-annealed CeO 2 film. This is due to that the 550 °C-annealed CeO 2 film contains more Ce 3+ ions and oxygen vacancies. It is tentatively proposed that the recombination of the electrons in multiple oxygen-vacancy–related energy levels with the holes in Ce 4f 1 energy band pertaining to Ce 3+ ions leads to the UV-Vis EL

Properties of InGaAs/GaAs metal-oxide-semiconductor heterostructure field-effect transistors modified by surface treatment

Energy Technology Data Exchange (ETDEWEB)

Gregušová, D., E-mail: Dagmar.Gregusova@savba.sk [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Gucmann, F.; Kúdela, R. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Mičušík, M. [Polymer Institute of Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84541 (Slovakia); Stoklas, R.; Válik, L. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Greguš, J. [Faculty of Mathematics, Physics and Informatics, Comenius University, Mlynská dolina, Bratislava SK-84248 (Slovakia); Blaho, M. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Kordoš, P. [Institute of Electronics and Photonics, Faculty of Electrical Engineering and Information Technology STU, Ilkovičova 3, Bratislava SK-81219 (Slovakia)

2017-02-15

Highlights: • AlGaAs/InGaAs/GaAs-based metal oxide semiconductor transistors-MOSHFET. • Thin Al-layer deposited in-situ and oxidize in air – gate insulator. • MOSHFET vs HFET transistor properties, density of traps evaluated. - Abstract: GaAs-based heterostructures exhibit excellent carrier transport properties, mainly the high carrier velocity. An AlGaAs-GaAs heterostructure field-effect transistor (HFET) with an InGaAs channel was prepared using metal-organic chemical vapor deposition (MOVPE). An AlOx layer was formed on the AlGaAs barrier layer by the air-assisted oxidation of a thin Al layer deposited in-situ in an MOVPE reactor immediately after AlGaAs/InGaAs growth. The HFETs and MOSHFETs exhibited a very low trap state density in the order of 10{sup 11} cm{sup −2} eV{sup −1}. Capacitance measurement yielded no significant difference between the HFET and MOSHFET structures. The formation of an AlOx layer modified the surface by partially eliminating surface states that arise from Ga-and As-based native oxides. The presence of an AlOx layer reflected in a reduced gate leakage current, which was evidenced by the two-terminal transistor measurement. Presented preparation procedure and device properties show great potential of AlGaAs/InGaAs-based MOSHFETs.

Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

KAUST Repository

Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, Mohamed N.; Alshareef, Husam N.

2015-01-01

, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin

Radiation effects in metal-oxide-semiconductor capacitors

International Nuclear Information System (INIS)

Collins, J.L.

1987-01-01

The effects of various radiations on commercially made Al-SiO 2 -Si Capacitors (MOSCs) have been investigated. Intrinsic dielectric breakdown in MOSCs has been shown to be a two-stage process dominated by charge injection in a pre-breakdown stage; this is associated with localised high-field injection of carriers from the semiconductor substrate to interfacial and bulk charge traps which, it is proposed, leads to the formation of conducting channels through the dielectric with breakdown occurring as a result of the dissipation of the conduction band energy. A study of radiation-induced dielectric breakdown has revealed the possibility of anomalous hot-electron injection to an excess of bulk oxide traps in the ionization channel produced by very heavily ionizing radiation, which leads to intrinsic breakdown in high-field stressed devices. This is interpreted in terms of a modified model for radiation-induced dielectric breakdown based upon the primary dependence of breakdown on charge injection rather than high-field mechanisms. A detailed investigation of charge trapping and interface state generation due to various radiations has revealed evidence of neutron induced interface states, and the generation of positive oxide charge in devices due to all the radiations tested. The greater the linear energy transfer of the radiation, the greater the magnitude of charge trapped in the oxide and the number of interface states generated. This is interpreted in terms of Si-H and Si-OH bond-breaking at the Si-SiO 2 interface which is enhanced by charge carrier transfer to the interface and by anomalous charge injection to compensate for the excess of charge carriers created by the radiation. (author)

Anisotropy-based crystalline oxide-on-semiconductor material

Science.gov (United States)

McKee, Rodney Allen; Walker, Frederick Joseph

2000-01-01

A semiconductor structure and device for use in a semiconductor application utilizes a substrate of semiconductor-based material, such as silicon, and a thin film of a crystalline oxide whose unit cells are capable of exhibiting anisotropic behavior overlying the substrate surface. Within the structure, the unit cells of the crystalline oxide are exposed to an in-plane stain which influences the geometric shape of the unit cells and thereby arranges a directional-dependent quality of the unit cells in a predisposed orientation relative to the substrate. This predisposition of the directional-dependent quality of the unit cells enables the device to take beneficial advantage of characteristics of the structure during operation. For example, in the instance in which the crystalline oxide of the structure is a perovskite, a spinel or an oxide of similarly-related cubic structure, the structure can, within an appropriate semiconductor device, exhibit ferroelectric, piezoelectric, pyroelectric, electro-optic, ferromagnetic, antiferromagnetic, magneto-optic or large dielectric properties that synergistically couple to the underlying semiconductor substrate.

Driver circuit for pulse modulation of a semiconductor laser

International Nuclear Information System (INIS)

Ueki, A.

1975-01-01

A pulse modulation driver circuit for a semiconductor laser is disclosed which discriminates among input pulse signals composed of binary codes to detect the occurrence of a pulse having a code of ''I'' following a pulse having a code of ''0''. Detection of this pattern is used to control the driver to increase either or both the width or peak value of the pulse having a code of 1. The effect of this is to eliminate a pattern effect in the light emitted by the semiconductor laser caused by an attenuation of the population inversion in the laser. (U.S.)

Effect of Water Vapor and Surface Morphology on the Low Temperature Response of Metal Oxide Semiconductor Gas Sensors

Directory of Open Access Journals (Sweden)

Konrad Maier

2015-09-01

Full Text Available In this work the low temperature response of metal oxide semiconductor gas sensors is analyzed. Important characteristics of this low-temperature response are a pronounced selectivity to acid- and base-forming gases and a large disparity of response and recovery time constants which often leads to an integrator-type of gas response. We show that this kind of sensor performance is related to the trend of semiconductor gas sensors to adsorb water vapor in multi-layer form and that this ability is sensitively influenced by the surface morphology. In particular we show that surface roughness in the nanometer range enhances desorption of water from multi-layer adsorbates, enabling them to respond more swiftly to changes in the ambient humidity. Further experiments reveal that reactive gases, such as NO2 and NH3, which are easily absorbed in the water adsorbate layers, are more easily exchanged across the liquid/air interface when the humidity in the ambient air is high.

Controlled fabrication of semiconductor-metal hybrid nano-heterostructures via site-selective metal photodeposition

Science.gov (United States)

Vela Becerra, Javier; Ruberu, T. Purnima A.

2017-12-05

A method of synthesizing colloidal semiconductor-metal hybrid heterostructures is disclosed. The method includes dissolving semiconductor nanorods in a solvent to form a nanorod solution, and adding a precursor solution to the nanorod solution. The precursor solution contains a metal. The method further includes illuminating the combined precursor and nanorod solutions with light of a specific wavelength. The illumination causes the deposition of the metal in the precursor solution onto the surface of the semiconductor nanorods.

An Overview of High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Capacitors and Field-Effect Transistors

Directory of Open Access Journals (Sweden)

Jiangwei Liu

2018-06-01

Full Text Available Thanks to its excellent intrinsic properties, diamond is promising for applications of high-power electronic devices, ultraviolet detectors, biosensors, high-temperature tolerant gas sensors, etc. Here, an overview of high-k oxides on hydrogenated-diamond (H-diamond for metal-oxide-semiconductor (MOS capacitors and MOS field-effect transistors (MOSFETs is demonstrated. Fabrication routines for the H-diamond MOS capacitors and MOSFETs, band configurations of oxide/H-diamond heterointerfaces, and electrical properties of the MOS and MOSFETs are summarized and discussed. High-k oxide insulators are deposited using atomic layer deposition (ALD and sputtering deposition (SD techniques. Electrical properties of the H-diamond MOS capacitors with high-k oxides of ALD-Al2O3, ALD-HfO2, ALD-HfO2/ALD-Al2O3 multilayer, SD-HfO2/ALD-HfO2 bilayer, SD-TiO2/ALD-Al2O3 bilayer, and ALD-TiO2/ALD-Al2O3 bilayer are discussed. Analyses for capacitance-voltage characteristics of them show that there are low fixed and trapped charge densities for the ALD-Al2O3/H-diamond and SD-HfO2/ALD-HfO2/H-diamond MOS capacitors. The k value of 27.2 for the ALD-TiO2/ALD-Al2O3 bilayer is larger than those of the other oxide insulators. Drain-source current versus voltage curves show distinct pitch-off and p-type channel characteristics for the ALD-Al2O3/H-diamond, SD-HfO2/ALD-HfO2/H-diamond, and ALD-TiO2/ALD-Al2O3/H-diamond MOSFETs. Understanding of fabrication routines and electrical properties for the high-k oxide/H-diamond MOS electronic devices is meaningful for the fabrication of high-performance H-diamond MOS capacitor and MOSFET gas sensors.

Epitaxial heterojunctions of oxide semiconductors and metals on high temperature superconductors

Science.gov (United States)

Vasquez, Richard P. (Inventor); Hunt, Brian D. (Inventor); Foote, Marc C. (Inventor)

1994-01-01

Epitaxial heterojunctions formed between high temperature superconductors and metallic or semiconducting oxide barrier layers are provided. Metallic perovskites such as LaTiO3, CaVO3, and SrVO3 are grown on electron-type high temperature superconductors such as Nd(1.85)Ce(0.15)CuO(4-x). Alternatively, transition metal bronzes of the form A(x)MO(3) are epitaxially grown on electron-type high temperature superconductors. Also, semiconducting oxides of perovskite-related crystal structures such as WO3 are grown on either hole-type or electron-type high temperature superconductors.

Thin film transistors for flexible electronics: Contacts, dielectrics and semiconductors

KAUST Repository

Quevedo-López, Manuel Angel Quevedo

2011-06-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed. Copyright © 2011 American Scientific Publishers.

Thin film transistors for flexible electronics: Contacts, dielectrics and semiconductors

KAUST Repository

Quevedo-Ló pez, Manuel Angel Quevedo; Wondmagegn, Wudyalew T.; Alshareef, Husam N.; Ramí rez-Bon, Rafael; Gnade, Bruce E.

2011-01-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed. Copyright © 2011 American Scientific Publishers.

Radiation effects in semiconductors: technologies for hardened integrated circuits

International Nuclear Information System (INIS)

Charlot, J.M.

1983-09-01

Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technologie or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented

Radiation effects in semiconductors: technologies for hardened integrated circuits

International Nuclear Information System (INIS)

Charlot, J.M.

1984-01-01

Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technology or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented. (author)

MeV He microbeam analysis of a semiconductor integrated circuit

International Nuclear Information System (INIS)

Zhu Peiran; Liu Jiarui; Zhang Jinping; Yin Shiduan

1989-01-01

An MeV He + microbeam has been used to analyse a microscale semiconductor structure. The 2 MeV He + ion beam is limited to 25 μm diameter by a set of diaphragms and is further focused by a quadrupole quadruplet to 3μm diameter. The incident beam current on the sample is about 0.3 nA. The Rutherford backscattering (RBS) technique is applied to the measurement of the composition and depth profile in the near-surface region of a semiconductor integrated circuit. (author)

MeV He microbeam analysis of a semiconductor integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Zhu Peiran; Liu Jiarui; Zhang Jinping; Yin Shiduan

1989-01-01

An MeV He/sup +/ microbeam has been used to analyse a microscale semiconductor structure. The 2 MeV He/sup +/ ion beam is limited to 25 /mu/m diameter by a set of diaphragms and is further focused by a quadrupole quadruplet to 3/mu/m diameter. The incident beam current on the sample is about 0.3 nA. The Rutherford backscattering (RBS) technique is applied to the measurement of the composition and depth profile in the near-surface region of a semiconductor integrated circuit.

Synthesis of self-detached nanoporous titanium-based metal oxide

International Nuclear Information System (INIS)

Hu, F.; Wen, Y.; Chan, K.C.; Yue, T.M.; Zhou, Y.Z.; Zhu, S.L.; Yang, X.J.

2015-01-01

In this study, self-detached nanoporous titanium-based metal oxide was synthesized for the first time by ultrafast anodization in a fluoride-free electrolyte containing 10% HNO 3 . The nanoporous oxide has through-holes with diameters ranging from 10 to 60 nm. The as-formed oxides are amorphous, and were transformed to crystalline structures by annealing. The performance of a dye sensitized solar cell using nanoporpous Ti–10Zr oxide (TZ10) was further studied. It was found that the TZ10 film could increase both the short-circuit current and the open-circuit photovoltage of the solar cell. The overall efficiency of the solar cell was 6.99%, an increase of 20.7% as compared to that using a pure TiO 2 (P25) film. - Graphical abstract: The nanoporous Ti–xZr(x=10, 30) oxide layers are fabricated by anodizing in a dilute nitric acid solvent. The power conversion efficiency of the DSSC by a covering of a Ti–10Zr thin film is increased by 20.7%, with an η of 7.69% , a short circuit current of 12.4 mA/cm 2 , a open circuit voltage of 0.833 V, and a fill factor of 0.679. - Highlights: • Self-detached nanoporous titanium-based metal (TiZr) oxide was synthesized. • The TiZr oxides have through-hole nanopores with diameters ranging from 10 to 60 nm. • The nanoporous Ti–10Zr oxide can improve the power conversion efficiency of a DSSC

Synthesis of self-detached nanoporous titanium-based metal oxide

Energy Technology Data Exchange (ETDEWEB)

Hu, F. [Advanced Manufacturing Technology Research Center, Department of Industrial and Systems Engineering, The Hong Kong Polytechnic University (Hong Kong); Jiangxi Key Laboratory of Advanced Ceramic Materials, School of Materials Science and Engineering, Jingdezhen Ceramic Institute, Jiangxi 343001 (China); Wen, Y. [Jiangxi Key Laboratory of Advanced Ceramic Materials, School of Materials Science and Engineering, Jingdezhen Ceramic Institute, Jiangxi 343001 (China); Chan, K.C., E-mail: mfkcchan@inet.polyu.edu.hk [Advanced Manufacturing Technology Research Center, Department of Industrial and Systems Engineering, The Hong Kong Polytechnic University (Hong Kong); Yue, T.M. [Advanced Manufacturing Technology Research Center, Department of Industrial and Systems Engineering, The Hong Kong Polytechnic University (Hong Kong); Zhou, Y.Z. [Jiangxi Key Laboratory of Advanced Ceramic Materials, School of Materials Science and Engineering, Jingdezhen Ceramic Institute, Jiangxi 343001 (China); Zhu, S.L.; Yang, X.J. [School of Materials Science and Engineering, Tianjin University, Tianjin 300072 (China)

2015-09-15

In this study, self-detached nanoporous titanium-based metal oxide was synthesized for the first time by ultrafast anodization in a fluoride-free electrolyte containing 10% HNO{sub 3}. The nanoporous oxide has through-holes with diameters ranging from 10 to 60 nm. The as-formed oxides are amorphous, and were transformed to crystalline structures by annealing. The performance of a dye sensitized solar cell using nanoporpous Ti–10Zr oxide (TZ10) was further studied. It was found that the TZ10 film could increase both the short-circuit current and the open-circuit photovoltage of the solar cell. The overall efficiency of the solar cell was 6.99%, an increase of 20.7% as compared to that using a pure TiO{sub 2} (P25) film. - Graphical abstract: The nanoporous Ti–xZr(x=10, 30) oxide layers are fabricated by anodizing in a dilute nitric acid solvent. The power conversion efficiency of the DSSC by a covering of a Ti–10Zr thin film is increased by 20.7%, with an η of 7.69% , a short circuit current of 12.4 mA/cm{sup 2}, a open circuit voltage of 0.833 V, and a fill factor of 0.679. - Highlights: • Self-detached nanoporous titanium-based metal (TiZr) oxide was synthesized. • The TiZr oxides have through-hole nanopores with diameters ranging from 10 to 60 nm. • The nanoporous Ti–10Zr oxide can improve the power conversion efficiency of a DSSC.

High-temperature complementary metal oxide semiconductors (CMOS)

International Nuclear Information System (INIS)

McBrayer, J.D.

1979-10-01

Silicon CMOS devices were studied, tested, and evaluated at high temperatures to determine processing, geometric, operating characteristics, and stability parameters. After more than 1000 hours at 300 0 C, most devices showed good stability, reliability, and operating characteristics. Processing and geometric parameters were evaluated and optimization steps discussed

Effects of quantum coupling on the performance of metal-oxide ...

Indian Academy of Sciences (India)

LING-FENG MAO. School of Electronics & Information Engineering, Soochow University, ... Quantum coupling; metal-oxide-semiconductor field transistors. ... effects of the barrier height reduction caused by the channel electron velocity due to.

Electrostatic analysis of n-doped SrTiO3 metal-insulator-semiconductor systems

International Nuclear Information System (INIS)

Kamerbeek, A. M.; Banerjee, T.; Hueting, R. J. E.

2015-01-01

Electron doped SrTiO 3 , a complex-oxide semiconductor, possesses novel electronic properties due to its strong temperature and electric-field dependent permittivity. Due to the high permittivity, metal/n-SrTiO 3 systems show reasonably strong rectification even when SrTiO 3 is degenerately doped. Our experiments show that the insertion of a sub nanometer layer of AlO x in between the metal and n-SrTiO 3 interface leads to a dramatic reduction of the Schottky barrier height (from around 0.90 V to 0.25 V). This reduces the interface resistivity by 4 orders of magnitude. The derived electrostatic analysis of the metal-insulator-semiconductor (n-SrTiO 3 ) system is consistent with this trend. When compared with a Si based MIS system, the change is much larger and mainly governed by the high permittivity of SrTiO 3 . The non-linear permittivity of n-SrTiO 3 leads to unconventional properties such as a temperature dependent surface potential non-existent for semiconductors with linear permittivity such as Si. This allows tuning of the interfacial band alignment, and consequently the Schottky barrier height, in a much more drastic way than in conventional semiconductors

Study of surface modifications for improved selected metal (II-VI) semiconductor based devices

Science.gov (United States)

Blomfield, Christopher James

Metal-semiconductor contacts are of fundamental importance to the operation of all semiconductor devices. There are many competing theories of Schottky barrier formation but as yet no quantitative predictive model exists to adequately explain metal-semiconductor interfaces. The II-VI compound semiconductors CdTe, CdS and ZnSe have recently come to the fore with the advent of high efficiency photovoltaic cells and short wavelength light emitters. Major problems still exist however in forming metal contacts to these materials with the desired properties. This work presents results which make a significant contribution to the theory of metal/II-VI interface behaviour in terms of Schottky barriers to n-type CdTe, CdS and ZnSe.Predominantly aqueous based wet chemical etchants were applied to the surfaces of CdTe, CdS and ZnSe which were subsequently characterised by X-ray photoelectron spectroscopy. The ionic nature of these II-VI compounds meant that they behaved as insoluble salts of strong bases and weak acids. Acid etchants induced a stoichiometric excess of semiconductor anion at the surface which appeared to be predominantly in the elemental or hydrogenated state. Alkaline etchants conversely induced a stoichiometric excess of semiconductor cation at the surface which appeared to be in an oxidised state.Metal contacts were vacuum-evaporated onto these etched surfaces and characterised by current-voltage and capacitance-voltage techniques. The surface preparation was found to have a clear influence upon the electrical properties of Schottky barriers formed to etched surfaces. Reducing the native surface oxide produced near ideal Schottky diodes. An extended study of Au, Ag and Sb contacts to [mathematical formula] substrates again revealed the formation of several discrete Schottky barriers largely independent of the metal used; for [mathematical formula]. Deep levels measured within this study and those reported in the literature led to the conclusion that Fermi

Asymmetric split-gate ambipolar transistor and its circuit application to complementary inverter

NARCIS (Netherlands)

Yoo, H.; Smits, E.C.P.; van Breemen, A.J.J.M.; van der Steen, J.L.; Torricelli, F.; Ghittorelli, M.; Lee, J.; Gelinck, G.; Kim, J.-J.

2016-01-01

Using a concept of asymmetric side gate and main gate, it is shown that it is possible to realize unipolar transport (both p-type and n-type) in a thin-film transistor with a high-performance ambipolar polymer semiconductor. In a complementary inverter, this results in higher noise margin and DC

77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

Science.gov (United States)

2012-10-04

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-840] Certain Semiconductor Integrated... certain semiconductor integrated circuit devices and products containing same by reason of infringement of...,783; and 6,847,904. The complaint further alleges the existence of a domestic industry. The Commission...

GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

Energy Technology Data Exchange (ETDEWEB)

Islam, Sk Masiul, E-mail: masiulelt@gmail.com; Chowdhury, Sisir; Sarkar, Krishnendu; Nagabhushan, B.; Banerji, P. [Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302 (India); Chakraborty, S. [Applied Materials Science Division, Saha Institute of Nuclear Physics, 1/AF Bidhannagar, Sector-I, Kolkata 700 064 (India); Mukherjee, Rabibrata [Department of Chemical Engineering, Indian Institute of Technology, Kharagpur 721302 (India)

2015-06-24

Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. The device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.

Impact of process temperature on GaSb metal-oxide-semiconductor interface properties fabricated by ex-situ process

Energy Technology Data Exchange (ETDEWEB)

Yokoyama, Masafumi, E-mail: yokoyama@mosfet.t.u-tokyo.ac.jp; Takenaka, Mitsuru; Takagi, Shinichi [Department of Electrical Engineering and Information Systems, The University of Tokyo, Yayoi 2-11-16, Bunkyo, Tokyo 113-0032 (Japan); JST-CREST, Yayoi 2-11-16, Bunkyo, Tokyo 113-0032 (Japan); Asakura, Yuji [Department of Electrical Engineering and Information Systems, The University of Tokyo, Yayoi 2-11-16, Bunkyo, Tokyo 113-0032 (Japan); Yokoyama, Haruki [NTT Photonics Laboratories, NTT Corporation, Atsugi 243-0198 (Japan)

2014-06-30

We have studied the impact of process temperature on interface properties of GaSb metal-oxide-semiconductor (MOS) structures fabricated by an ex-situ atomic-layer-deposition (ALD) process. We have found that the ALD temperature strongly affects the Al{sub 2}O{sub 3}/GaSb MOS interface properties. The Al{sub 2}O{sub 3}/GaSb MOS interfaces fabricated at the low ALD temperature of 150 °C have the minimum interface-trap density (D{sub it}) of ∼4.5 × 10{sup 13 }cm{sup −2} eV{sup −1}. We have also found that the post-metalization annealing at temperature higher than 200 °C degrades the Al{sub 2}O{sub 3}/GaSb MOS interface properties. The low-temperature process is preferable in fabricating GaSb MOS interfaces in the ex-situ ALD process to avoid the high-temperature-induced degradations.

Using a Semiconductor-to-Metal Transition to Control Optical Transmission through Subwavelength Hole Arrays

Directory of Open Access Journals (Sweden)

E. U. Donev

2008-01-01

Full Text Available We describe a simple configuration in which the extraordinary optical transmission effect through subwavelength hole arrays in noble-metal films can be switched by the semiconductor-to-metal transition in an underlying thin film of vanadium dioxide. In these experiments, the transition is brought about by thermal heating of the bilayer film. The surprising reverse hysteretic behavior of the transmission through the subwavelength holes in the vanadium oxide suggest that this modulation is accomplished by a dielectric-matching condition rather than plasmon coupling through the bilayer film. The results of this switching, including the wavelength dependence, are qualitatively reproduced by a transfer matrix model. The prospects for effecting a similar modulation on a much faster time scale by using ultrafast laser pulses to trigger the semiconductor-to-metal transition are also discussed.

Study of SiO2-Si and metal-oxide-semiconductor structures using positrons

Science.gov (United States)

Leung, T. C.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

1993-01-01

Studies of SiO2-Si and metal-oxide-semiconductor (MOS) structures using positrons are summarized and a concise picture of the present understanding of positrons in these systems is provided. Positron annihilation line-shape S data are presented as a function of the positron incident energy, gate voltage, and annealing, and are described with a diffusion-annihilation equation for positrons. The data are compared with electrical measurements. Distinct annihilation characteristics were observed at the SiO2-Si interface and have been studied as a function of bias voltage and annealing conditions. The shift of the centroid (peak) of γ-ray energy distributions in the depletion region of the MOS structures was studied as a function of positron energy and gate voltage, and the shifts are explained by the corresponding variations in the strength of the electric field and thickness of the depletion layer. The potential role of the positron annihilation technique as a noncontact, nondestructive, and depth-sensitive characterization tool for the technologically important, deeply buried interface is shown.

Study of SiO2-Si and metal-oxide-semiconductor structures using positrons

International Nuclear Information System (INIS)

Leung, T.C.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K.G.

1993-01-01

Studies of SiO 2 -Si and metal-oxide-semiconductor (MOS) structures using positrons are summarized and a concise picture of the present understanding of positrons in these systems is provided. Positron annihilation line-shape S data are presented as a function of the positron incident energy, gate voltage, and annealing, and are described with a diffusion-annihilation equation for positrons. The data are compared with electrical measurements. Distinct annihilation characteristics were observed at the SiO 2 -Si interface and have been studied as a function of bias voltage and annealing conditions. The shift of the centroid (peak) of γ-ray energy distributions in the depletion region of the MOS structures was studied as a function of positron energy and gate voltage, and the shifts are explained by the corresponding variations in the strength of the electric field and thickness of the depletion layer. The potential role of the positron annihilation technique as a noncontact, nondestructive, and depth-sensitive characterization tool for the technologically important, deeply buried interface is shown

Hydrogen Sensors Using Nitride-Based Semiconductor Diodes: The Role of Metal/Semiconductor Interfaces

Directory of Open Access Journals (Sweden)

Yoshihiro Irokawa

2011-01-01

Full Text Available In this paper, I review my recent results in investigating hydrogen sensors using nitride-based semiconductor diodes, focusing on the interaction mechanism of hydrogen with the devices. Firstly, effects of interfacial modification in the devices on hydrogen detection sensitivity are discussed. Surface defects of GaN under Schottky electrodes do not play a critical role in hydrogen sensing characteristics. However, dielectric layers inserted in metal/semiconductor interfaces are found to cause dramatic changes in hydrogen sensing performance, implying that chemical selectivity to hydrogen could be realized. The capacitance-voltage (C-V characteristics reveal that the work function change in the Schottky metal is not responsible mechanism for hydrogen sensitivity. The interface between the metal and the semiconductor plays a critical role in the interaction of hydrogen with semiconductor devises. Secondly, low-frequency C-V characterization is employed to investigate the interaction mechanism of hydrogen with diodes. As a result, it is suggested that the formation of a metal/semiconductor interfacial polarization could be attributed to hydrogen-related dipoles. In addition, using low-frequency C-V characterization leads to clear detection of 100 ppm hydrogen even at room temperature where it is hard to detect hydrogen by using conventional current-voltage (I-V characterization, suggesting that low-frequency C-V method would be effective in detecting very low hydrogen concentrations.

Metal Contacts to Gallium Arsenide.

Science.gov (United States)

Ren, Fan

1991-07-01

While various high performance devices fabricated from the gallium arsenide (GaAs) and related materials have generated considerable interest, metallization are fundamental components to all semiconductor devices and integrated circuits. The essential roles of metallization systems are providing the desired electrical paths between the active region of the semiconductor and the external circuits through the metal interconnections and contacts. In this work, in-situ clean of native oxide, high temperature n-type, low temperature n-type and low temperature p-type ohmic metal systems have been studied. Argon ion mill was used to remove the native oxide prior to metal deposition. For high temperature process n-type GaAs ohmic contacts, Tungsten (W) and Tungsten Silicide (WSi) were used with an epitaxial grown graded Indium Gallium Arsenide (InGaAs) layer (0.2 eV) on GaAs. In addition, refractory metals, Molybdenum (Mo), was incorporated in the Gold-Germanium (AuGe) based on n-type GaAs ohmic contacts to replace conventional silver as barrier to prevent the reaction between ohmic metal and chlorine based plasma as well as the ohmic metallization intermixing which degrades the device performance. Finally, Indium/Gold-Beryllium (In/Au-Be) alloy has been developed as an ohmic contact for p-type GaAs to reduce the contact resistance. The Fermi-level pinning of GaAs has been dominated by the surface states. The Schottky barrier height of metal contacts are about 0.8 V regardless of the metal systems. By using p-n junction approach, barrier height of pulsed C-doped layers was achieved as high as 1.4 V. Arsenic implantation into GaAs method was also used to enhance the barrier height of 1.6 V.

Thermal stability of atomic layer deposited WCxNy electrodes for metal oxide semiconductor devices

Science.gov (United States)

Zonensain, Oren; Fadida, Sivan; Fisher, Ilanit; Gao, Juwen; Danek, Michal; Eizenberg, Moshe

2018-01-01

This study is a thorough investigation of the chemical, structural, and electrical stability of W based organo-metallic films, grown by atomic layer deposition, for future use as gate electrodes in advanced metal oxide semiconductor structures. In an earlier work, we have shown that high effective work-function (4.7 eV) was produced by nitrogen enriched films (WCxNy) dominated by W-N chemical bonding, and low effective work-function (4.2 eV) was produced by hydrogen plasma resulting in WCx films dominated by W-C chemical bonding. In the current work, we observe, using x-ray diffraction analysis, phase transformation of the tungsten carbide and tungsten nitride phases after 900 °C annealing to the cubic tungsten phase. Nitrogen diffusion is also observed and is analyzed with time-of-flight secondary ion mass spectroscopy. After this 900 °C anneal, WCxNy effective work function tunability is lost and effective work-function values of 4.7-4.8 eV are measured, similar to stable effective work function values measured for PVD TiN up to 900 °C anneal. All the observed changes after annealing are discussed and correlated to the observed change in the effective work function.

Preparation and dielectric investigation of organic metal insulator semiconductor (MIS) structures with a ferroelectric polymer

Energy Technology Data Exchange (ETDEWEB)

Kalbitz, Rene; Fruebing, Peter; Gerhard, Reimund [Department of Physics and Astronomy, University of Potsdam (Germany); Taylor, Martin [School of Electronic Engineering, Bangor University (United Kingdom)

2010-07-01

Ferroelectric field effect transistors (FeFETs) offer the prospect of an organic-based memory device. Since the charge transport in the semiconductor is confined to the interface region between the insulator and the semiconductor, the focus of the present study was on the investigation of this region in metal-insulator-semiconductor (MIS) capacitors using dielectric spectroscopy. Capacitance-Voltage (C-V) measurements at different frequencies as well as capacitance-frequency (C-f) measurements after applying different poling voltages were carried out. The C-V measurements yielded information about the frequency dependence of the depletion layer width as well as the number of charges stored at the semiconductor/ insulator interface. The results are compared to numerical calculations based on a model introduced by S. L. Miller (JAP, 72(12), 1992). The C-f measurements revealed three main relaxation processes. An equivalent circuit has been developed to model the frequency response of the MIS capacitor. With this model the origin of the three relaxations may be deduced.

Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

Science.gov (United States)

Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

2005-04-01

We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

Synthesis of a nano-silver metal ink for use in thick conductive film fabrication applied on a semiconductor package.

Directory of Open Access Journals (Sweden)

Lai Chin Yung

Full Text Available The success of printing technology in the electronics industry primarily depends on the availability of metal printing ink. Various types of commercially available metal ink are widely used in different industries such as the solar cell, radio frequency identification (RFID and light emitting diode (LED industries, with limited usage in semiconductor packaging. The use of printed ink in semiconductor IC packaging is limited by several factors such as poor electrical performance and mechanical strength. Poor adhesion of the printed metal track to the epoxy molding compound is another critical factor that has caused a decline in interest in the application of printing technology to the semiconductor industry. In this study, two different groups of adhesion promoters, based on metal and polymer groups, were used to promote adhesion between the printed ink and the epoxy molding substrate. The experimental data show that silver ink with a metal oxide adhesion promoter adheres better than silver ink with a polymer adhesion promoter. This result can be explained by the hydroxyl bonding between the metal oxide promoter and the silane grouping agent on the epoxy substrate, which contributes a greater adhesion strength compared to the polymer adhesion promoter. Hypotheses of the physical and chemical functions of both adhesion promoters are described in detail.

Carrier scattering in metals and semiconductors

CERN Document Server

Gantmakher, VF

1987-01-01

The transport properties of solids, as well as the many optical phenomena in them are determined by the scattering of current carriers. ``Carrier Scattering in Metals and Semiconductors'' elucidates the state of the art in the research on the scattering mechanisms for current carriers in metals and semiconductors and describes experiments in which these mechanisms are most dramatically manifested.The selection and organization of the material is in a form to prepare the reader to reason independently and to deal just as independently with available theoretical results and experimental

Cu2O-based solar cells using oxide semiconductors

International Nuclear Information System (INIS)

Minami, Tadatsugu; Nishi, Yuki; Miyata, Toshihiro

2016-01-01

We describe significant improvements of the photovoltaic properties that were achieved in Al-doped ZnO (AZO)/n-type oxide semiconductor/p-type Cu 2 O heterojunction solar cells fabricated using p-type Cu 2 O sheets prepared by thermally oxidizing Cu sheets. The multicomponent oxide thin film used as the n-type semiconductor layer was prepared with various chemical compositions on non-intentionally heated Cu 2 O sheets under various deposition conditions using a pulsed laser deposition method. In Cu 2 O-based heterojunction solar cells fabricated using various ternary compounds as the n-type oxide thin-film layer, the best photovoltaic performance was obtained with an n-ZnGa 2 O 4 thin-film layer. In most of the Cu 2 O-based heterojunction solar cells using multicomponent oxides composed of combinations of various binary compounds, the obtained photovoltaic properties changed gradually as the chemical composition was varied. However, with the ZnO-MgO and Ga 2 O 3 -Al 2 O 3 systems, higher conversion efficiencies (η) as well as a high open circuit voltage (V oc ) were obtained by using a relatively small amount of MgO or Al 2 O 3 , e.g., (ZnO) 0.91 –(MgO) 0.09 and (Ga 2 O 3 ) 0.975 –(Al 2 O 3 ) 0.025 , respectively. When Cu 2 O-based heterojunction solar cells were fabricated using Al 2 O 3 –Ga 2 O 3 –MgO–ZnO (AGMZO) multicomponent oxide thin films deposited with metal atomic ratios of 10, 60, 10 and 20 at.% for the Al, Ga, Mg and Zn, respectively, a high V oc of 0.98 V and an η of 4.82% were obtained. In addition, an enhanced η and an improved fill factor could be achieved in AZO/n-type multicomponent oxide/p-type Cu 2 O heterojunction solar cells fabricated using Na-doped Cu 2 O (Cu 2 O:Na) sheets that featured a resistivity controlled by optimizing the post-annealing temperature and duration. Consequently, an η of 6.25% and a V oc of 0.84 V were obtained in a MgF 2 /AZO/n-(Ga 2 O 3 –Al 2 O 3 )/p-Cu 2 O:Na heterojunction solar cell fabricated using

Cu2O-based solar cells using oxide semiconductors

Science.gov (United States)

Minami, Tadatsugu; Nishi, Yuki; Miyata, Toshihiro

2016-01-01

We describe significant improvements of the photovoltaic properties that were achieved in Al-doped ZnO (AZO)/n-type oxide semiconductor/p-type Cu2O heterojunction solar cells fabricated using p-type Cu2O sheets prepared by thermally oxidizing Cu sheets. The multicomponent oxide thin film used as the n-type semiconductor layer was prepared with various chemical compositions on non-intentionally heated Cu2O sheets under various deposition conditions using a pulsed laser deposition method. In Cu2O-based heterojunction solar cells fabricated using various ternary compounds as the n-type oxide thin-film layer, the best photovoltaic performance was obtained with an n-ZnGa2O4 thin-film layer. In most of the Cu2O-based heterojunction solar cells using multicomponent oxides composed of combinations of various binary compounds, the obtained photovoltaic properties changed gradually as the chemical composition was varied. However, with the ZnO-MgO and Ga2O3-Al2O3 systems, higher conversion efficiencies (η) as well as a high open circuit voltage (Voc) were obtained by using a relatively small amount of MgO or Al2O3, e.g., (ZnO)0.91-(MgO)0.09 and (Ga2O3)0.975-(Al2O3)0.025, respectively. When Cu2O-based heterojunction solar cells were fabricated using Al2O3-Ga2O3-MgO-ZnO (AGMZO) multicomponent oxide thin films deposited with metal atomic ratios of 10, 60, 10 and 20 at.% for the Al, Ga, Mg and Zn, respectively, a high Voc of 0.98 V and an η of 4.82% were obtained. In addition, an enhanced η and an improved fill factor could be achieved in AZO/n-type multicomponent oxide/p-type Cu2O heterojunction solar cells fabricated using Na-doped Cu2O (Cu2O:Na) sheets that featured a resistivity controlled by optimizing the post-annealing temperature and duration. Consequently, an η of 6.25% and a Voc of 0.84 V were obtained in a MgF2/AZO/n-(Ga2O3-Al2O3)/p-Cu2O:Na heterojunction solar cell fabricated using a Cu2O:Na sheet with a resistivity of approximately 10 Ω·cm and a (Ga0.975Al0

Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

Science.gov (United States)

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-Il Dan; Ko, Hyoungho

2015-10-14

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

Directory of Open Access Journals (Sweden)

Haryong Song

2015-10-01

Full Text Available Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

Effective carrier sweepout in a silicon waveguide by a metal-semiconductor-metal structure

DEFF Research Database (Denmark)

Ding, Yunhong; Hu, Hao; Ou, Haiyan

2015-01-01

We demonstrate effective carrier depletion by metal-semiconductor-metal junctions for a silicon waveguide. Photo-generated carriers are efficiently swept out by applying bias voltages, and a shortest carrier lifetime of only 55 ps is demonstrated.......We demonstrate effective carrier depletion by metal-semiconductor-metal junctions for a silicon waveguide. Photo-generated carriers are efficiently swept out by applying bias voltages, and a shortest carrier lifetime of only 55 ps is demonstrated....

Charge transport in metal oxide nanocrystal-based materials

Science.gov (United States)

Runnerstrom, Evan Lars

structure. Charge transport can obviously be taken to mean the conduction of electrons, but it also refers to the motion of ions, such as lithium ions and protons. In many cases, the transport of ions is married to the motion of electrons as well, either through an external electrical circuit, or within the same material in the case of mixed ionic electronic conductors. The collective motion of electrons over short length scales, that is, within single nanocrystals, is also a subject of study as it pertains to plasmonic nanocrystals. Finally, charge transport can also be coupled to or result from the formation of defects in metal oxides. All of these modes of charge transport in metal oxides gain further complexity when considered in nanocrystalline systems, where the introduction of numerous surfaces can change the character of charge transport relative to bulk systems, providing opportunities to exploit new physical phenomena. Part I of this dissertation explores the combination of electronic and ionic transport in electrochromic devices based on nanocrystals. Colloidal chemistry and solution processing are used to fabricate nanocomposites based on electrochromic tin-doped indium oxide (ITO) nanocrystals. The nanocomposites, which are completely synthesized using solution processing, consist of ITO nanocrystals and lithium bis(trifluoromethylsulfonyl)amide (LiTFSI) salt dispersed in a lithium ion-conducting polymer matrix of either poly(ethylene oxide) (PEO) or poly(methyl methacrylate) (PMMA). ITO nanocrystals are prepared by colloidal synthetic methods and the nanocrystal surface chemistry is modified to achieve favorable nanocrystal-polymer interactions. Homogeneous solutions containing polymer, ITO nanocrystals, and lithium salt are thus prepared and deposited by spin casting. Characterization by DC electronic measurements, microscopy, and x-ray scattering techniques show that the ITO nanocrystals form a complete, connected electrode within a polymer electrolyte

Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

Science.gov (United States)

Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

2013-12-13

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

Science.gov (United States)

Liu, Yuanda; Ang, Kah-Wee

2017-07-25

Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10 3 . Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

Semiconductors for plasmonics and metamaterials

DEFF Research Database (Denmark)

Naik, G.V.; Boltasseva, Alexandra

2010-01-01

Plasmonics has conventionally been in the realm of metal-optics. However, conventional metals as plasmonic elements in the near-infrared (NIR) and visible spectral ranges suffer from problems such as large losses and incompatibility with semiconductor technology. Replacing metals with semiconduct......Plasmonics has conventionally been in the realm of metal-optics. However, conventional metals as plasmonic elements in the near-infrared (NIR) and visible spectral ranges suffer from problems such as large losses and incompatibility with semiconductor technology. Replacing metals...... with semiconductors can alleviate these problems if only semiconductors could exhibit negative real permittivity. Aluminum doped zinc oxide (AZO) is a low loss semiconductor that can show negative real permittivity in the NIR. A comparative assessment of AZO-based plasmonic devices such as superlens and hyperlens...... with their metal-based counterparts shows that AZO-based devices significantly outperform at a wavelength of 1.55 µm. This provides a strong stimulus in turning to semiconductor plasmonics at the telecommunication wavelengths. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)....

Broadband image sensor array based on graphene-CMOS integration

Science.gov (United States)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Structure and magnetism of transition-metal implanted dilute magnetic semiconductors

CERN Document Server

Pereira, Lino; Temst, K; Araújo, JP; Wahl, U

The discovery of a dilute magnetic semiconductor (DMS) in which ferromagnetism is carrier-mediated and persists above room temperature is a critical step towards the development of semiconductor-based spintronics. Among the many types of DMS materials which have been investigated, the current research interest can be narrowed down to two main classes of materials: (1) narrow-gap III-V semiconductors, mostly GaAs and InAs, doped with Mn; (2) wide-gap oxides and nitrides doped with 3d transition metals, mostly Mn- and Co-doped ZnO and Mn-doped GaN. With a number of interesting functionalities deriving from the carrier-mediated ferromagnetism and demonstrated in various proof-of-concept devices, Mn-doped GaAs has become, among DMS materials, one of the best candidates for technological application. However, despite major developments over the last 15 years, the maximum Curie temperature (185 K) remains well below room temperature. On the other hand, wide-gap DMS materials appear to exhibit ferromagnetic behavior...

Semiconductor electrolyte photovoltaic energy converter

Science.gov (United States)

Anderson, W. W.; Anderson, L. B.

1975-01-01

Feasibility and practicality of a solar cell consisting of a semiconductor surface in contact with an electrolyte are evaluated. Basic components and processes are detailed for photovoltaic energy conversion at the surface of an n-type semiconductor in contact with an electrolyte which is oxidizing to conduction band electrons. Characteristics of single crystal CdS, GaAs, CdSe, CdTe and thin film CdS in contact with aqueous and methanol based electrolytes are studied and open circuit voltages are measured from Mott-Schottky plots and open circuit photo voltages. Quantum efficiencies for short circuit photo currents of a CdS crystal and a 20 micrometer film are shown together with electrical and photovoltaic properties. Highest photon irradiances are observed with the GaAs cell.

Influence of quantizing magnetic field and Rashba effect on indium arsenide metal-oxide-semiconductor structure accumulation capacitance

Science.gov (United States)

Kovchavtsev, A. P.; Aksenov, M. S.; Tsarenko, A. V.; Nastovjak, A. E.; Pogosov, A. G.; Pokhabov, D. A.; Tereshchenko, O. E.; Valisheva, N. A.

2018-05-01

The accumulation capacitance oscillations behavior in the n-InAs metal-oxide-semiconductor structures with different densities of the built-in charge (Dbc) and the interface traps (Dit) at temperature 4.2 K in the magnetic field (B) 2-10 T, directed perpendicular to the semiconductor-dielectric interface, is studied. A decrease in the oscillation frequency and an increase in the capacitance oscillation amplitude are observed with the increase in B. At the same time, for a certain surface accumulation band bending, the influence of the Rashba effect, which is expressed in the oscillations decay and breakdown, is traced. The experimental capacitance-voltage curves are in a good agreement with the numeric simulation results of the self-consistent solution of Schrödinger and Poisson equations in the magnetic field, taking into account the quantization, nonparabolicity of dispersion law, and Fermi-Dirac electron statistics, with the allowance for the Rashba effect. The Landau quantum level broadening in a two-dimensional electron gas (Lorentzian-shaped density of states), due to the electron scattering mechanism, linearly depends on the magnetic field. The correlation between the interface electronic properties and the characteristic scattering times was established.

Electric Circuit Model Analogy for Equilibrium Lattice Relaxation in Semiconductor Heterostructures

Science.gov (United States)

Kujofsa, Tedi; Ayers, John E.

2018-01-01

The design and analysis of semiconductor strained-layer device structures require an understanding of the equilibrium profiles of strain and dislocations associated with mismatched epitaxy. Although it has been shown that the equilibrium configuration for a general semiconductor strained-layer structure may be found numerically by energy minimization using an appropriate partitioning of the structure into sublayers, such an approach is computationally intense and non-intuitive. We have therefore developed a simple electric circuit model approach for the equilibrium analysis of these structures. In it, each sublayer of an epitaxial stack may be represented by an analogous circuit configuration involving an independent current source, a resistor, an independent voltage source, and an ideal diode. A multilayered structure may be built up by the connection of the appropriate number of these building blocks, and the node voltages in the analogous electric circuit correspond to the equilibrium strains in the original epitaxial structure. This enables analysis using widely accessible circuit simulators, and an intuitive understanding of electric circuits can easily be extended to the relaxation of strained-layer structures. Furthermore, the electrical circuit model may be extended to continuously-graded epitaxial layers by considering the limit as the individual sublayer thicknesses are diminished to zero. In this paper, we describe the mathematical foundation of the electrical circuit model, demonstrate its application to several representative structures involving In x Ga1- x As strained layers on GaAs (001) substrates, and develop its extension to continuously-graded layers. This extension allows the development of analytical expressions for the strain, misfit dislocation density, critical layer thickness and widths of misfit dislocation free zones for a continuously-graded layer having an arbitrary compositional profile. It is similar to the transition from circuit

Indium tin oxide films prepared by atmospheric plasma annealing and their semiconductor-metal conductivity transition around room temperature

International Nuclear Information System (INIS)

Li Yali; Li Chunyang; He Deyan; Li Junshuai

2009-01-01

We report the synthesis of indium tin oxide (ITO) films using the atmospheric plasma annealing (APA) technique combined with the spin-coating method. The ITO film with a low resistivity of ∼4.6 x 10 -4 Ω cm and a high visible light transmittance, above 85%, was achieved. Hall measurement indicates that compared with the optimized ITO films deposited by magnetron sputtering, the above-mentioned ITO film has a higher carrier concentration of ∼1.21 x 10 21 cm -3 and a lower mobility of ∼11.4 cm 2 V -1 s -1 . More interestingly, these electrical characteristics result in the semiconductor-metal conductivity transition around room temperature for the ITO films prepared by APA.

Radiation hardness of β-Ga2O3 metal-oxide-semiconductor field-effect transistors against gamma-ray irradiation

Science.gov (United States)

Wong, Man Hoi; Takeyama, Akinori; Makino, Takahiro; Ohshima, Takeshi; Sasaki, Kohei; Kuramata, Akito; Yamakoshi, Shigenobu; Higashiwaki, Masataka

2018-01-01

The effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. A gamma-ray tolerance as high as 1.6 MGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on the MOSFETs' output current and threshold voltage. The MOSFETs remained functional with insignificant hysteresis in their transfer characteristics after exposure to the maximum cumulative dose. Despite the intrinsic radiation hardness of Ga2O3, radiation-induced gate leakage and drain current dispersion ascribed respectively to dielectric damage and interface charge trapping were found to limit the overall radiation hardness of these devices.

Fully-Coupled Thermo-Electrical Modeling and Simulation of Transition Metal Oxide Memristors

Energy Technology Data Exchange (ETDEWEB)

Mamaluy, Denis [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Gao, Xujiao [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Tierney, Brian David [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Marinella, Matthew [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Mickel, Patrick [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Tierney, Brian D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2016-11-01

Transition metal oxide (TMO) memristors have recently attracted special attention from the semiconductor industry and academia. Memristors are one of the strongest candidates to replace flash memory, and possibly DRAM and SRAM in the near future. Moreover, memristors have a high potential to enable beyond-CMOS technology advances in novel architectures for high performance computing (HPC). The utility of memristors has been demonstrated in reprogrammable logic (cross-bar switches), brain-inspired computing and in non-CMOS complementary logic. Indeed, the potential use of memristors as logic devices is especially important considering the inevitable end of CMOS technology scaling that is anticipated by 2025. In order to aid the on-going Sandia memristor fabrication effort with a memristor design tool and establish a clear physical picture of resistance switching in TMO memristors, we have created and validated with experimental data a simulation tool we name the Memristor Charge Transport (MCT) Simulator.

Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

International Nuclear Information System (INIS)

Liu, Siyang; Zhang, Chunwei; Sun, Weifeng; Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu

2014-01-01

Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic

Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

Energy Technology Data Exchange (ETDEWEB)

Liu, Siyang; Zhang, Chunwei; Sun, Weifeng, E-mail: swffrog@seu.edu.cn [National ASIC System Engineering Research Center, Southeast University, Nanjing 210096 (China); Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu [CSMC Technologies Corporation, Wuxi 214061 (China)

2014-04-14

Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic.

Reagent-Free Electrophoretic Synthesis of Few-Atom-Thick Metal Oxide Nanosheets

DEFF Research Database (Denmark)

Hou, Chengyi; Zhang, Minwei; Zhang, Lili

2017-01-01

Engineering traditional materials into the new form of atomic and free-standing two-dimensional structures is of both fundamental interest and practical significance, but it is in general facing challenges especially for metal oxide semiconductors. We herein report an ultragreen method for the cost......-effective and fast preparation of atomic metal oxide nanosheets that can be further transformed into nanofilms. The method combines top-down building block synthesis and bottom-up electrophoretic assembly in water under ambient conditions, using only bulk metal and Milli-Q water without involving any additional...

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

Science.gov (United States)

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Current-voltage characteristics of the semiconductor nanowires under the metal-semiconductor-metal structure

Science.gov (United States)

Wen, Jing; Zhang, Xitian; Gao, Hong; Wang, Mingjiao

2013-12-01

We present a method to calculate the I-V characteristics of semiconductor nanowires under the metal-semiconductor-metal (MSM) structure. The carrier concentration as an important parameter is introduced into the expression of the current. The subband structure of the nanowire has been considered for associating it with the position of the Fermi level and circumventing the uncertainties of the contact areas in the contacts. The tunneling and thermionic emission currents in the two Schottky barriers at the two metal-semiconductor contacts are discussed. We find that the two barriers have different influences on the I-V characteristics of the MSM structure, one of which under the forward bias plays the role of threshold voltage if its barrier height is large and the applied voltage is small, and the other under the reverse bias controls the shapes of I-V curves. Our calculations show that the shapes of the I-V curves for the MSM structure are mainly determined by the barrier heights of the contacts and the carrier concentration. The nearly identical I-V characteristics can be obtained by using different values of the barrier heights and carrier concentration, which means that the contact type conversion can be ascribed not only to the changes of the barrier heights but also that of the carrier concentration. We also discuss the mechanisms of the ohmic-Schottky conversions and clarify the ambiguity in the literature. The possibility about the variation of the carrier concentration under the applied fields has been confirmed by experimental results.

Nanoscale semiconductor-insulator-metal core/shell heterostructures: facile synthesis and light emission

Science.gov (United States)

Li, Gong Ping; Chen, Rui; Guo, Dong Lai; Wong, Lai Mun; Wang, Shi Jie; Sun, Han Dong; Wu, Tom

2011-08-01

Controllably constructing hierarchical nanostructures with distinct components and designed architectures is an important theme of research in nanoscience, entailing novel but reliable approaches of bottom-up synthesis. Here, we report a facile method to reproducibly create semiconductor-insulator-metal core/shell nanostructures, which involves first coating uniform MgO shells onto metal oxide nanostructures in solution and then decorating them with Au nanoparticles. The semiconductor nanowire core can be almost any material and, herein, ZnO, SnO2 and In2O3 are used as examples. We also show that linear chains of short ZnO nanorods embedded in MgO nanotubes and porous MgO nanotubes can be obtained by taking advantage of the reduced thermal stability of the ZnO core. Furthermore, after MgO shell-coating and the appropriate annealing treatment, the intensity of the ZnO near-band-edge UV emission becomes much stronger, showing a 25-fold enhancement. The intensity ratio of the UV/visible emission can be increased further by decorating the surface of the ZnO/MgO nanowires with high-density plasmonic Au nanoparticles. These heterostructured semiconductor-insulator-metal nanowires with tailored morphologies and enhanced functionalities have great potential for use as nanoscale building blocks in photonic and electronic applications.Controllably constructing hierarchical nanostructures with distinct components and designed architectures is an important theme of research in nanoscience, entailing novel but reliable approaches of bottom-up synthesis. Here, we report a facile method to reproducibly create semiconductor-insulator-metal core/shell nanostructures, which involves first coating uniform MgO shells onto metal oxide nanostructures in solution and then decorating them with Au nanoparticles. The semiconductor nanowire core can be almost any material and, herein, ZnO, SnO2 and In2O3 are used as examples. We also show that linear chains of short ZnO nanorods embedded in

Ultrafast photoinduced charge separation in metal-semiconductor nanohybrids.

Science.gov (United States)

Mongin, Denis; Shaviv, Ehud; Maioli, Paolo; Crut, Aurélien; Banin, Uri; Del Fatti, Natalia; Vallée, Fabrice

2012-08-28

Hybrid nano-objects formed by two or more disparate materials are among the most promising and versatile nanosystems. A key parameter in their properties is interaction between their components. In this context we have investigated ultrafast charge separation in semiconductor-metal nanohybrids using a model system of gold-tipped CdS nanorods in a matchstick architecture. Experiments are performed using an optical time-resolved pump-probe technique, exciting either the semiconductor or the metal component of the particles, and probing the light-induced change of their optical response. Electron-hole pairs photoexcited in the semiconductor part of the nanohybrids are shown to undergo rapid charge separation with the electron transferred to the metal part on a sub-20 fs time scale. This ultrafast gold charging leads to a transient red-shift and broadening of the metal surface plasmon resonance, in agreement with results for free clusters but in contrast to observation for static charging of gold nanoparticles in liquid environments. Quantitative comparison with a theoretical model is in excellent agreement with the experimental results, confirming photoexcitation of one electron-hole pair per nanohybrid followed by ultrafast charge separation. The results also point to the utilization of such metal-semiconductor nanohybrids in light-harvesting applications and in photocatalysis.

Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

Directory of Open Access Journals (Sweden)

Kwang-Jow Gan

2016-06-01

Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

Extraordinary Magnetoresistance in Semiconductor/Metal Hybrids: A Review

Science.gov (United States)

Sun, Jian; Kosel, Jürgen

2013-01-01

The Extraordinary Magnetoresistance (EMR) effect is a change in the resistance of a device upon the application of a magnetic field in hybrid structures, consisting of a semiconductor and a metal. The underlying principle of this phenomenon is a change of the current path in the hybrid structure upon application of a magnetic field, due to the Lorentz force. Specifically, the ratio of current, flowing through the highly conducting metal and the poorly conducting semiconductor, changes. The main factors for the device’s performance are: the device geometry, the conductivity of the metal and semiconductor, and the mobility of carriers in the semiconductor. Since the discovery of the EMR effect, much effort has been devoted to utilize its promising potential. In this review, a comprehensive overview of the research on the EMR effect and EMR devices is provided. Different geometries of EMR devices are compared with respect to MR ratio and output sensitivity, and the criteria of material selection for high-performance devices are discussed. PMID:28809321

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

Science.gov (United States)

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal−oxide−semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

Energy Technology Data Exchange (ETDEWEB)

Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel

2017-07-01

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

Device reliability challenges for modern semiconductor circuit design – a review

Directory of Open Access Journals (Sweden)

C. Schlünder

2009-05-01

Full Text Available Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1. Degradation mechanisms like Negative Bias Temperature Instability (NBTI or Hot Carrier Injection (HCI lead to parameter drifts during operation adding on top of the process variations.

The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs.

An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.

Durability-enhanced two-dimensional hole gas of C-H diamond surface for complementary power inverter applications.

Science.gov (United States)

Kawarada, Hiroshi; Yamada, Tetsuya; Xu, Dechen; Tsuboi, Hidetoshi; Kitabayashi, Yuya; Matsumura, Daisuke; Shibata, Masanobu; Kudo, Takuya; Inaba, Masafumi; Hiraiwa, Atsushi

2017-02-20

Complementary power field effect transistors (FETs) based on wide bandgap materials not only provide high-voltage switching capability with the reduction of on-resistance and switching losses, but also enable a smart inverter system by the dramatic simplification of external circuits. However, p-channel power FETs with equivalent performance to those of n-channel FETs are not obtained in any wide bandgap material other than diamond. Here we show that a breakdown voltage of more than 1600 V has been obtained in a diamond metal-oxide-semiconductor (MOS) FET with a p-channel based on a two-dimensional hole gas (2DHG). Atomic layer deposited (ALD) Al 2 O 3 induces the 2DHG ubiquitously on a hydrogen-terminated (C-H) diamond surface and also acts as both gate insulator and passivation layer. The high voltage performance is equivalent to that of state-of-the-art SiC planar n-channel FETs and AlGaN/GaN FETs. The drain current density in the on-state is also comparable to that of these two FETs with similar device size and V B .

Binary copper oxide semiconductors: From materials towards devices

Energy Technology Data Exchange (ETDEWEB)

Meyer, B.K.; Polity, A.; Reppin, D.; Becker, M.; Hering, P.; Klar, P.J.; Sander, T.; Reindl, C.; Benz, J.; Eickhoff, M.; Heiliger, C.; Heinemann, M. [1. Physics Institute, Justus-Liebig University of Giessen (Germany); Blaesing, J.; Krost, A. [Institute of Experimental Physics (IEP), Otto-von-Guericke University Magdeburg (Germany); Shokovets, S. [Institute of Physics, Ilmenau University of Technology (Germany); Mueller, C.; Ronning, C. [Institute of Solid State Physics, Friedrich Schiller University Jena (Germany)

2012-08-15

Copper-oxide compound semiconductors provide a unique possibility to tune the optical and electronic properties from insulating to metallic conduction, from bandgap energies of 2.1 eV to the infrared at 1.40 eV, i.e., right into the middle of the efficiency maximum for solar-cell applications. Three distinctly different phases, Cu{sub 2}O, Cu{sub 4}O{sub 3}, and CuO, of this binary semiconductor can be prepared by thin-film deposition techniques, which differ in the oxidation state of copper. Their material properties as far as they are known by experiment or predicted by theory are reviewed. They are supplemented by new experimental results from thin-film growth and characterization, both will be critically discussed and summarized. With respect to devices the focus is on solar-cell performances based on Cu{sub 2}O. It is demonstrated by photoelectron spectroscopy (XPS) that the heterojunction system p-Cu{sub 2}O/n-AlGaN is much more promising for the application as efficient solar cells than that of p-Cu{sub 2}O/n-ZnO heterojunction devices that have been favored up to now. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Comparison of modification strategies towards enhanced charge carrier separation and photocatalytic degradation activity of metal oxide semiconductors (TiO{sub 2}, WO{sub 3} and ZnO)

Energy Technology Data Exchange (ETDEWEB)

Kumar, S. Girish [Department of Physics, Indian Institute of Science, Bengaluru, 560012 Karnataka (India); Department of Chemistry, School of Engineering and Technology, CMR University, Bengaluru, 562149, Karnataka (India); Rao, K.S.R. Koteswara, E-mail: raoksrk@gmail.com [Department of Physics, Indian Institute of Science, Bengaluru, 560012 Karnataka (India)

2017-01-01

Graphical abstract: Semiconductor metal oxides: Modifications, charge carrier dynamics and photocatalysis. - Highlights: • TiO{sub 2}, WO{sub 3} and ZnO based photocatalysis is reviewed. • Advances to improve the efficiency are emphasized. • Differences and similarities in the modifications are highlighted. • Charge carrier dynamics for each strategy are discussed. - Abstract: Metal oxide semiconductors (TiO{sub 2}, WO{sub 3} and ZnO) finds unparalleled opportunity in wastewater purification under UV/visible light, largely encouraged by their divergent admirable features like stability, non-toxicity, ease of preparation, suitable band edge positions and facile generation of active oxygen species in the aqueous medium. However, the perennial failings of these photocatalysts emanates from the stumbling blocks like rapid charge carrier recombination and meager visible light response. In this review, tailoring the surface-bulk electronic structure through the calibrated and veritable approaches such as impurity doping, deposition with noble metals, sensitizing with other compounds (dyes, polymers, inorganic complexes and simple chelating ligands), hydrogenation process (annealing under hydrogen atmosphere), electronic integration with other semiconductors, modifying with carbon nanostructures, designing with exposed facets and tailoring with hierarchical morphologies to overcome their critical drawbacks are summarized. Taking into account the materials intrinsic properties, the pros and cons together with similarities and striking differences for each strategy in specific to TiO{sub 2}, WO{sub 3} & ZnO are highlighted. These subtlety enunciates the primacy for improving the structure-electronic properties of metal oxides and credence to its fore in the practical applications. Future research must focus on comparing the performances of ZnO, TiO{sub 2} and WO{sub 3} in parallel to get insight into their photocatalytic behaviors. Such comparisons not only reveal

Characterization of metal-functionalized flax orbitide as a new candidate for light-emitting semiconductor

International Nuclear Information System (INIS)

Bauer, Robert; Bazylewski, Paul; Chang, Gap Soo; Jadhav, Pramodkumar; Shen, Jianheng; Okinyo-Owiti, Denis Paskal; Reaney, Martin; Yang, Jian; Sammynaiken, Ramaswami

2015-01-01

Organic materials display promise in numerous electronic applications, complimentary to traditional semi-conducting materials. Cyclolinopeptides show promise in light-emitting applications as an organic semiconductor. Photoluminescence measurements indicate charge transfer between the peptide and the metal, resulting in an increase in intensity of the emission from around the metal in the Cyclolinopeptide complex. Complementary X-ray absorption near-edge spectroscopy (XANES) shows a change in occupation of energy states in the peptide when complexed with the metal, indicating charge transfer, but peak positions show the peptide is not chemically changed by the metal. Combining X-ray emission and XANES provides element specific partial density of states, to estimate the element specific energy gap which is the proposed emission range for the peptide material. Organic light emitting diode devices have been fabricated, although no measurable emission has been seen as of yet. The devices have diode like current-voltage characteristics showing the peptide is semi-conducting with a threshold voltage of approximately 2.5 V. (paper)

An analog memory integrated circuit for waveform sampling up to 900 MHz

International Nuclear Information System (INIS)

Haller, G.M.; Wooley, B.A.

1994-01-01

The potential of switched-capacitor technology for acquiring analog signals in high-energy physics (HEP) applications has been demonstrated in a number of analog memory designs. The design and implementation of a switched-capacitor memory suitable for capturing high-speed analog waveforms is described. Highlights of the presented circuit are a 900 MHz sampling frequency (generated on chip), input signal independent cell pedestal and sampling instances, and cell gains that are insensitive to component sizes. A two-channel version of the memory with 32 cells for each channel has been integrate in a 2-μm complementary metal oxide semiconductor (CMOS) process with polysilicon-to-polysilicon capacitors. The measured rms cell response variation in a channel after cell pedestal subtraction is less than 0.3 mV across the full input signal range. The cell-to-cell gain matching is better than 0.01% rms, and the nonlinearity is less than 0.03% for a 2.5-V input range. The dynamic range of the memory exceeds 13 bits, and the peak signal-to-(noise + distortion) ratio for a 21.4 MHz sine wave sampled at 900 MHz is 59 dB

Biomedical implementation of liquid metal ink as drawable ECG electrode and skin circuit.

Directory of Open Access Journals (Sweden)

Yang Yu

Full Text Available BACKGROUND: Conventional ways of making bio-electrodes are generally complicated, expensive and unconformable. Here we describe for the first time the method of applying Ga-based liquid metal ink as drawable electrocardiogram (ECG electrodes. Such material owns unique merits in both liquid phase conformability and high electrical conductivity, which provides flexible ways for making electrical circuits on skin surface and a prospective substitution of conventional rigid printed circuit boards (PCBs. METHODS: Fundamental measurements of impedance and polarization voltage of the liquid metal ink were carried out to evaluate its basic electrical properties. Conceptual experiments were performed to draw the alloy as bio-electrodes to acquire ECG signals from both rabbit and human via a wireless module developed on the mobile phone. Further, a typical electrical circuit was drawn in the palm with the ink to demonstrate its potential of implementing more sophisticated skin circuits. RESULTS: With an oxide concentration of 0.34%, the resistivity of the liquid metal ink was measured as 44.1 µΩ·cm with quite low reactance in the form of straight line. Its peak polarization voltage with the physiological saline was detected as -0.73 V. The quality of ECG wave detected from the liquid metal electrodes was found as good as that of conventional electrodes, from both rabbit and human experiments. In addition, the circuit drawn with the liquid metal ink in the palm also runs efficiently. When the loop was switched on, all the light emitting diodes (LEDs were lit and emitted colorful lights. CONCLUSIONS: The liquid metal ink promises unique printable electrical properties as both bio-electrodes and electrical wires. The implemented ECG measurement on biological surface and the successfully run skin circuit demonstrated the conformability and attachment of the liquid metal. The present method is expected to innovate future physiological measurement and

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

Science.gov (United States)

Rotta, Davide; Sebastiano, Fabio; Charbon, Edoardo; Prati, Enrico

2017-06-01

Even the quantum simulation of an apparently simple molecule such as Fe2S2 requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore's law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault-tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal-oxide-semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency

Extraordinary magnetoresistance in semiconductor/metal hybrids: A review

KAUST Repository

Sun, J.

2013-02-13

The Extraordinary Magnetoresistance (EMR) effect is a change in the resistance of a device upon the application of a magnetic field in hybrid structures, consisting of a semiconductor and a metal. The underlying principle of this phenomenon is a change of the current path in the hybrid structure upon application of a magnetic field, due to the Lorentz force. Specifically, the ratio of current, flowing through the highly conducting metal and the poorly conducting semiconductor, changes. The main factors for the device\\'s performance are: the device geometry, the conductivity of the metal and semiconductor, and the mobility of carriers in the semiconductor. Since the discovery of the EMR effect, much effort has been devoted to utilize its promising potential. In this review, a comprehensive overview of the research on the EMR effect and EMR devices is provided. Different geometries of EMR devices are compared with respect to MR ratio and output sensitivity, and the criteria of material selection for high-performance devices are discussed. 2013 by the authors.

Extraordinary Magnetoresistance in Semiconductor/Metal Hybrids: A Review

Directory of Open Access Journals (Sweden)

Jürgen Kosel

2013-02-01

Full Text Available The Extraordinary Magnetoresistance (EMR effect is a change in the resistance of a device upon the application of a magnetic field in hybrid structures, consisting of a semiconductor and a metal. The underlying principle of this phenomenon is a change of the current path in the hybrid structure upon application of a magnetic field, due to the Lorentz force. Specifically, the ratio of current, flowing through the highly conducting metal and the poorly conducting semiconductor, changes. The main factors for the device’s performance are: the device geometry, the conductivity of the metal and semiconductor, and the mobility of carriers in the semiconductor. Since the discovery of the EMR effect, much effort has been devoted to utilize its promising potential. In this review, a comprehensive overview of the research on the EMR effect and EMR devices is provided. Different geometries of EMR devices are compared with respect to MR ratio and output sensitivity, and the criteria of material selection for high-performance devices are discussed.

Failure of the integrated circuits involving complementary MOS transistors under thermal and ionizing radiation stresses

International Nuclear Information System (INIS)

Sarrabayrouse, G.; Rossel, P.; Buxo, J.; Vialaret, G.

Some criteria for reliability and sorting of complementary MOS transistor integrated circuits are proposed, that take account for special environmental stresses near plane reactors or nuclear reactor cores. An analysis of the damaging causes for these circuits at high and low temperatures is proposed, results obtained on the evolution of these devices under irradiation and irradiation behaviors are discussed. The whole set of experiments has been carried out on CD 4007 AD(K) circuits [fr

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector.

Science.gov (United States)

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2014-01-13

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

Near-IR Spectral Imaging of Semiconductor Absorption Sites in Integrated Circuits

Directory of Open Access Journals (Sweden)

E. C. Samson

2004-12-01

Full Text Available We derive spectral maps of absorption sites in integrated circuits (ICs by varying the wavelength of the optical probe within the near-IR range. This method has allowed us to improve the contrast of the acquired images by revealing structures that have a different optical absorption from neighboring sites. A false color composite image from those acquired at different wavelengths is generated from which the response of each semiconductor structure can be deduced. With the aid of the spectral maps, nonuniform absorption was also observed in a semiconductor structure located near an electrical overstress defect. This method may prove important in failure analysis of ICs by uncovering areas exhibiting anomalous absorption, which could improve localization of defective edifices in the semiconductor parts of the microchip

Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er2O3 as a gate dielectric

International Nuclear Information System (INIS)

Lin, Ray-Ming; Chu, Fu-Chuan; Das, Atanu; Liao, Sheng-Yu; Chou, Shu-Tsun; Chang, Liann-Be

2013-01-01

In this study, the rare earth erbium oxide (Er 2 O 3 ) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N t ) of the MOS–HEMT were 125 mV/decade and 4.3 × 10 12 cm −2 , respectively. The dielectric constant of the Er 2 O 3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166 V for the conventional HEMT to –196 V for the Er 2 O 3 MOS–HEMT. - Highlights: ► GaN/AlGaN/Er 2 O 3 metal-oxide semiconductor high electron mobility transistor ► Physical and electrical characteristics are presented. ► Electron beam evaporated Er 2 O 3 with excellent surface roughness ► Device exhibits reduced gate leakage current and improved I ON /I OFF ratio

Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

Energy Technology Data Exchange (ETDEWEB)

Chubenko, E. B., E-mail: eugene.chubenko@gmail.com; Redko, S. V.; Sherstnyov, A. I.; Petrovich, V. A.; Kotov, D. A.; Bondarenko, V. P. [Belarusian State University of Information and RadioElectronics (Belarus)

2016-03-15

The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materials on the basis of porous silicon and nanostructures with a high aspect ratio.

Influence of the Surface Layer on the Electrochemical Deposition of Metals and Semiconductors into Mesoporous Silicon

International Nuclear Information System (INIS)

Chubenko, E. B.; Redko, S. V.; Sherstnyov, A. I.; Petrovich, V. A.; Kotov, D. A.; Bondarenko, V. P.

2016-01-01

The influence of the surface layer on the process of the electrochemical deposition of metals and semiconductors into porous silicon is studied. It is shown that the surface layer differs in structure and electrical characteristics from the host porous silicon bulk. It is established that a decrease in the conductivity of silicon crystallites that form the surface layer of porous silicon has a positive effect on the process of the filling of porous silicon with metals and semiconductors. This is demonstrated by the example of nickel and zinc oxide. The effect can be used for the formation of nanocomposite materials on the basis of porous silicon and nanostructures with a high aspect ratio.

Electronic Properties of Metallic Nanoclusters on Semiconductor Surfaces: Implications for Nanoelectronic Device Applications

International Nuclear Information System (INIS)

Lee, Takhee; Liu Jia; Chen, N.-P.; Andres, R.P.; Janes, D.B.; Reifenberger, R.

2000-01-01

We review current research on the electronic properties of nanoscale metallic islands and clusters deposited on semiconductor substrates. Reported results for a number of nanoscale metal-semiconductor systems are summarized in terms of their fabrication and characterization. In addition to the issues faced in large-area metal-semiconductor systems, nano-systems present unique challenges in both the realization of well-controlled interfaces at the nanoscale and the ability to adequately characterize their electrical properties. Imaging by scanning tunneling microscopy as well as electrical characterization by current-voltage spectroscopy enable the study of the electrical properties of nanoclusters/semiconductor systems at the nanoscale. As an example of the low-resistance interfaces that can be realized, low-resistance nanocontacts consisting of metal nanoclusters deposited on specially designed ohmic contact structures are described. To illustrate a possible path to employing metal/semiconductor nanostructures in nanoelectronic applications, we also describe the fabrication and performance of uniform 2-D arrays of such metallic clusters on semiconductor substrates. Using self-assembly techniques involving conjugated organic tether molecules, arrays of nanoclusters have been formed in both unpatterned and patterned regions on semiconductor surfaces. Imaging and electrical characterization via scanning tunneling microscopy/spectroscopy indicate that high quality local ordering has been achieved within the arrays and that the clusters are electronically coupled to the semiconductor substrate via the low-resistance metal/semiconductor interface

Effect of the tunnelling oxide growth by H{sub 2}O{sub 2} oxidation on the performance of a-Si:H MIS photodiodes

Energy Technology Data Exchange (ETDEWEB)

Aguas, H.; Perreira, L.; Silva, R.J.C.; Fortunato, E.; Martins, R

2004-06-15

In this work metal-insulator-semiconductor (MIS) photodiodes with a structure: Cr/a-Si:H(n{sup +})/a-Si:H(i)/oxide/Au were studied, where the main objective was to determine the influence of the oxide layer on the performance of the devices. The results achieved show that their performance is a function of both oxide thickness and oxide density. The a-Si:H oxidation method used was the immersion in H{sub 2}O{sub 2} solution. By knowledge of the oxide growth process it was possible to fabricate photodiodes exhibiting an open circuit voltage of 0.65 V and short circuit current density under AM1.5 illumination of 11 mA/cm{sup 2}, with a response times less than 1 {mu}s for load resistance <400 {omega}, and a signal to noise ratio of 1x10{sup 7}.

First-principles simulations of the leakage current in metal-oxide-semiconductor structures caused by oxygen vacancies in HfO2 high-K gate dielectric

International Nuclear Information System (INIS)

Mao, L.F.; Wang, Z.O.

2008-01-01

HfO 2 high-K gate dielectric has been used as a new gate dielectric in metal-oxide-semiconductor structures. First-principles simulations are used to study the effects of oxygen vacancies on the tunneling current through the oxide. A level which is nearly 1.25 eV from the bottom of the conduction band is introduced into the bandgap due to the oxygen vacancies. The tunneling current calculations show that the tunneling currents through the gate oxide with different defect density possess the typical characteristic of stress-induced leakage current. Further analysis shows that the location of oxygen vacancies will have a marked effect on the tunneling current. The largest increase in the tunneling current caused by oxygen vacancies comes about at the middle oxide field when defects are located at the middle of the oxide. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Flexible Electronics Powered by Mixed Metal Oxide Thin Film Transistors

Science.gov (United States)

Marrs, Michael

A low temperature amorphous oxide thin film transistor (TFT) and amorphous silicon PIN diode backplane technology for large area flexible digital x-ray detectors has been developed to create 7.9-in. diagonal backplanes. The critical steps in the evolution of the backplane process include the qualification and optimization of the low temperature (200 °C) metal oxide TFT and a-Si PIN photodiode process, the stability of the devices under forward and reverse bias stress, the transfer of the process to flexible plastic substrates, and the fabrication and assembly of the flexible detectors. Mixed oxide semiconductor TFTs on flexible plastic substrates suffer from performance and stability issues related to the maximum processing temperature limitation of the polymer. A novel device architecture based upon a dual active layer improves both the performance and stability. Devices are directly fabricated below 200 ºC on a polyethylene naphthalate (PEN) substrate using mixed metal oxides of either zinc indium oxide (ZIO) or indium gallium zinc oxide (IGZO) as the active semiconductor. The dual active layer architecture allows for adjustment to the saturation mobility and threshold voltage stability without the requirement of high temperature annealing, which is not compatible with flexible plastic substrates like PEN. The device performance and stability is strongly dependent upon the composition of the mixed metal oxide; this dependency provides a simple route to improving the threshold voltage stability and drive performance. By switching from a single to a dual active layer, the saturation mobility increases from 1.2 cm2/V-s to 18.0 cm2/V-s, while the rate of the threshold voltage shift decreases by an order of magnitude. This approach could assist in enabling the production of devices on flexible substrates using amorphous oxide semiconductors. Low temperature (200°C) processed amorphous silicon photodiodes were developed successfully by balancing the tradeoffs

Nitrogen doped nanocrystalline semiconductor metal oxide: An efficient UV active photocatalyst for the oxidation of an organic dye using slurry Photoreactor.

Science.gov (United States)

Ramachandran, Saranya; Sivasamy, A; Kumar, B Dinesh

2016-12-01

Water pollution is a cause for serious concern in today's world. A major contributor to water pollution is industrial effluents containing dyes and other organic molecules. Waste water treatment has become a priority area in today's applied scientific research as it seeks to minimize the toxicity of the effluents being discharged and increase the possibility of water recycling. An efficient and eco-friendly way of degrading toxic molecules is to use nano metal-oxide photocatalysts. The present study aims at enhancing the photocatalytic activity of a semiconductor metal oxide by doping it with nitrogen. A sol-gel cum combustion method was employed to synthesize the catalyst. The prepared catalyst was characterized by FT-IR, XRD, UV-DRS, FESEM and AFM techniques. UV-DRS result showed the catalyst to possess band gap energy of 2.97eV, thus making it active in the UV region of the spectrum. Its photocatalytic activity was evaluated by the degradation of a model pollutant-Orange G dye, under UV light irradiation. Preliminary experiments were carried out to study the effects of pH, catalyst dosage and initial dye concentration on the extent of dye degradation. Kinetic studies revealed that the reaction followed pseudo first order kinetics. The effect of electrolytes on catalyst efficiency was also studied. The progress of the reaction was monitored by absorption studies and measuring the reduction in COD. The catalyst thus prepared was seen to have a high photocatalytic efficiency. The use of this catalyst is a promising means of waste water treatment. Copyright © 2016 Elsevier Inc. All rights reserved.

Localization and Imaging of Integrated Circuit Defect Using Simple Optical Feedback Detection

Directory of Open Access Journals (Sweden)

Vernon Julius Cemine

2004-12-01

Full Text Available High-contrast microscopy of semiconductor and metal edifices in integrated circuits is demonstrated by combining laser-scanning confocal reflectance microscopy, one-photon optical-beam-induced current (1P-OBIC imaging, and optical feedback detection via a commercially available semiconductor laser that also serves as the excitation source. The confocal microscope has a compact in-line arrangement with no external photodetector. Confocal and 1P-OBIC images are obtained simultaneously from the same focused beam that is scanned across the sample plane. Image pairs are processed to generate exclusive high-contrast distributions of the semiconductor, metal, and dielectric sites in a GaAs photodiode array sample. The method is then utilized to demonstrate defect localization and imaging in an integrated circuit.

Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

Science.gov (United States)

Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

2017-08-01

The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Transparent Oxide Semiconductors for Emerging Electronics

KAUST Repository

Caraveo-Frescas, Jesus Alfonso

2013-11-01

Transparent oxide electronics have emerged as promising materials to shape the future of electronics. While several n-type oxides have been already studied and demonstrated feasibility to be used as active materials in thin film transistors, high performance p-type oxides have remained elusive. This dissertation is devoted to the study of transparent p-type oxide semiconductor tin monoxide and its use in the fabrication of field effect devices. A complete study on the deposition of tin monoxide thin films by direct current reactive magnetron sputtering is performed. Carrier density, carrier mobility and conductivity are studied over a set of deposition conditions where p-type conduction is observed. Density functional theory simulations are performed in order to elucidate the effect of native defects on carrier mobility. The findings on the electrical properties of SnO thin films are then translated to the fabrication of thin films transistors. The low processing temperature of tin monoxide thin films below 200 oC is shown advantageous for the fabrication of fully transparent and flexible thin film transistors. After careful device engineering, including post deposition annealing temperature, gate dielectric material, semiconductor thickness and source and drain electrodes material, thin film transistors with record device performance are demonstrated, achieving a field effect mobility >6.7 cm2V-1s-1. Device performance is further improved to reach a field effect mobility of 10.8 cm2V-1s-1 in SnO nanowire field effect transistors fabricated from the sputtered SnO thin films and patterned by electron beam lithography. Downscaling device dimension to nano scale is shown beneficial for SnO field effect devices not only by achieving a higher hole mobility but enhancing the overall device performance including better threshold voltage, subthreshold swing and lower number of interfacial defects. Use of p-type semiconductors in nonvolatile memory applications is then

Fabricating an organic complementary inverter by integrating two transistors on a single substrate

International Nuclear Information System (INIS)

Wang Jun; Wei Bin; Zhang Jianhua

2008-01-01

Organic complementary inverters were fabricated by integrating two transistors of different electric type on a single substrate. One is a p-type organic heterojunction transistor with a depletion–accumulation mode that acts as a load element. The other is an n-type transistor with an accumulation mode that acts as a drive element. Typical inverter characteristics with a voltage gain of 12 were obtained. Compared with conventional devices, our organic complementary inverter used only one-step patterning of an organic semiconductor, and simultaneously suppressed the leakage current between supply voltage and ground. Therefore, current studies provide a simpler path to fabrication of organic complementary circuits

Transparent megahertz circuits from solution-processed composite thin films.

Science.gov (United States)

Liu, Xingqiang; Wan, Da; Wu, Yun; Xiao, Xiangheng; Guo, Shishang; Jiang, Changzhong; Li, Jinchai; Chen, Tangsheng; Duan, Xiangfeng; Fan, Zhiyong; Liao, Lei

2016-04-21

Solution-processed amorphous oxide semiconductors have attracted considerable interest in large-area transparent electronics. However, due to its relative low carrier mobility (∼10 cm(2) V(-1) s(-1)), the demonstrated circuit performance has been limited to 800 kHz or less. Herein, we report solution-processed high-speed thin-film transistors (TFTs) and integrated circuits with an operation frequency beyond the megahertz region on 4 inch glass. The TFTs can be fabricated from an amorphous indium gallium zinc oxide/single-walled carbon nanotube (a-IGZO/SWNT) composite thin film with high yield and high carrier mobility of >70 cm(2) V(-1) s(-1). On-chip microwave measurements demonstrate that these TFTs can deliver an unprecedented operation frequency in solution-processed semiconductors, including an extrinsic cut-off frequency (f(T) = 102 MHz) and a maximum oscillation frequency (f(max) = 122 MHz). Ring oscillators further demonstrated an oscillation frequency of 4.13 MHz, for the first time, realizing megahertz circuit operation from solution-processed semiconductors. Our studies represent an important step toward high-speed solution-processed thin film electronics.

Temperature induced complementary switching in titanium oxide resistive random access memory

Energy Technology Data Exchange (ETDEWEB)

Panda, D., E-mail: dpanda@nist.edu [Department of Electronics Engineering, National Institute of Science and Technology, Berhampur, Odisha 761008 (India); Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Simanjuntak, F. M.; Tseng, T.-Y. [Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan (China)

2016-07-15

On the way towards high memory density and computer performance, a considerable development in energy efficiency represents the foremost aspiration in future information technology. Complementary resistive switch consists of two antiserial resistive switching memory (RRAM) elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption. Here we present a titanium oxide based complementary RRAM (CRRAM) device with Pt top and TiN bottom electrode. A subsequent post metal annealing at 400°C induces CRRAM. Forming voltage of 4.3 V is required for this device to initiate switching process. The same device also exhibiting bipolar switching at lower compliance current, Ic <50 μA. The CRRAM device have high reliabilities. Formation of intermediate titanium oxi-nitride layer is confirmed from the cross-sectional HRTEM analysis. The origin of complementary switching mechanism have been discussed with AES, HRTEM analysis and schematic diagram. This paper provides valuable data along with analysis on the origin of CRRAM for the application in nanoscale devices.

On-chip growth of semiconductor metal oxide nanowires for gas sensors: A review

Directory of Open Access Journals (Sweden)

Chu Manh Hung

2017-09-01

Full Text Available Semiconductor metal oxide nanowires (SMO-NWs show great potential for novel gas sensor applications because of their distinct properties, such as a high surface area to volume aspect ratio, high crystallinity and perfect pathway for electron transfer (length of NW. SMO-NW sensors can be configured as resistors or field-effect transistors for gas detection and different configurations, such as a single NW, multiple NWs, and networked NW films, have been established. Surface-functionalizing NWs with catalyst elements and self-heating NWs provide additional advantages for highly selective and low-power consumption gas sensors. However, an appropriate design of SMO-NWs is of practical importance in enhancing the gas-sensing performance of SMO-NW sensors. The on-chip growth of SMO-NWs possesses many advantages which can thus be effectively used for the large-scale fabrication of SMO-NW sensors with improved gas response and stability. This review aims to provide up-to-date information on the on-chip fabrication of SnO2, ZnO, WO3, CuO, and other SMO-NW sensors. It also discusses a variety of promising approaches that help advance the on-chip fabrication of SMO-NW-based gas sensors and other NW-based devices.

NASA Space Engineering Research Center for VLSI systems design

Science.gov (United States)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

A comparative study of semiconductor-based plasmonic metamaterials

DEFF Research Database (Denmark)

Naik, Gururaj V.; Boltasseva, Alexandra

2011-01-01

and very large negative real permittivity values, and in addition, their optical properties cannot be tuned. These issues that put severe constraints on the device applications of MMs could be overcome if semiconductors are used as plasmonic materials instead of metals. Heavily doped, wide bandgap oxide...... semiconductors could exhibit both a small negative real permittivity and relatively small losses in the NIR. Heavily doped oxides of zinc and indium were already reported to be good, low loss alternatives to metals in the NIR range. Here, we consider these transparent conducting oxides (TCOs) as alternative...

Influence of semiconductor barrier tunneling on the current-voltage characteristics of tunnel metal-oxide-semiconductor diodes

DEFF Research Database (Denmark)

Nielsen, Otto M.

1983-01-01

of multistep tunneling recombination current and injected minority carrier diffusion current. This can explain the observed values of the diode quality factor n. The results also show that the voltage drop across the oxide Vox is increased with increased NA, with the result that the lowering of the minority...... carrier diode current Jmin is greater than in the usual theory. The conclusion drawn is that the increase in Vox and lowering of Jmin is due to multistep tunneling of majority carriers through the semiconductor barrier. Journal of Applied Physics is copyrighted by The American Institute of Physics.......Current–voltage characteristics have been examined for Al–SiO2–pSi diodes with an interfacial oxide thickness of delta[approximately-equal-to]20 Å. The diodes were fabricated on and oriented substrates with an impurity concentration in the range of NA=1014–1016 cm−3. The results show that for low...

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

Science.gov (United States)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process.

Science.gov (United States)

Swain, Basudev; Mishra, Chinmayee; Lee, Chan Gi; Park, Kyung-Soo; Lee, Kun-Jae

2015-07-01

Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga0.97N0.9O0.09 is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga0.97N0.9O0.09 of the MOCVD dust is leached at the optimum condition. Subsequently, the leach residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4M HCl, 100°C and pulp density of 100 kg/m(3,) respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. Copyright © 2015 Elsevier Inc. All rights reserved.

Study of Si/Si, Si/SiO2, and metal-oxide-semiconductor (MOS) using positrons

International Nuclear Information System (INIS)

Leung, To Chi.

1991-01-01

A variable-energy positron beam is used to study Si/Si, Si/SiO 2 , and metal-oxide-semiconductor (MOS) structures. The capability of depth resolution and the remarkable sensitivity to defects have made the positron annihilation technique a unique tool in detecting open-volume defects in the newly innovated low temperature (300C) molecular-beam-epitaxy (MBE) Si/Si. These two features of the positron beam have further shown its potential role in the study of the Si/SiO 2 . Distinct annihilation characteristics has been observed at the interface and has been studied as a function of the sample growth conditions, annealing (in vacuum), and hydrogen exposure. The MOS structure provides an effective way to study the electrical properties of the Si/SiO 2 interface as a function of applied bias voltage. The annihilation characteristics show a large change as the device condition is changed from accumulation to inversion. The effect of forming gas (FG) anneal is studied using positron annihilation and the result is compared with capacitance-voltage (C-V) measurements. The reduction in the number of interface states is found correlated with the changes in the positron spectra. The present study shows the importance of the positron annihilation technique as a non-contact, non-destructive, and depth-sensitive characterization tool to study the Si-related systems, in particular, the Si/SiO 2 interface which is of crucial importance in semiconductor technology, and fundamental understanding of the defects responsible for degradation of the electrical properties

Stress Characterization of 4H-SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) using Raman Spectroscopy and the Finite Element Method.

Science.gov (United States)

Yoshikawa, Masanobu; Kosaka, Kenichi; Seki, Hirohumi; Kimoto, Tsunenobu

2016-07-01

We measured the depolarized and polarized Raman spectra of a 4H-SiC metal-oxide-semiconductor field-effect transistor (MOSFET) and found that compressive stress of approximately 20 MPa occurs under the source and gate electrodes and tensile stress of approximately 10 MPa occurs between the source and gate electrodes. The experimental result was in close agreement with the result obtained by calculation using the finite element method (FEM). A combination of Raman spectroscopy and FEM provides much data on the stresses in 4H-SiC MOSFET. © The Author(s) 2016.

Surface Passivation of CIGS Solar Cells Using Gallium Oxide

KAUST Repository

Garud, Siddhartha

2018-02-27

This work proposes gallium oxide grown by plasma-enhanced atomic layer deposition, as a surface passivation material at the CdS buffer interface of Cu(In,Ga)Se2 (CIGS) solar cells. In preliminary experiments, a metal-insulator-semiconductor (MIS) structure is used to compare aluminium oxide, gallium oxide, and hafnium oxide as passivation layers at the CIGS-CdS interface. The findings suggest that gallium oxide on CIGS may show a density of positive charges and qualitatively, the least interface trap density. Subsequent solar cell results with an estimated 0.5 nm passivation layer show an substantial absolute improvement of 56 mV in open-circuit voltage (VOC), 1 mA cm−2 in short-circuit current density (JSC), and 2.6% in overall efficiency as compared to a reference (with the reference showing 8.5% under AM 1.5G).

1/f Fluctuations in ion implanted metal semiconductor contacts

International Nuclear Information System (INIS)

Stojanovic, M.; Marjanovic, N.; Radojevic, B.

1998-01-01

Ion implanted Metal-Semiconductor contacts is the most widely used structures in electrical devices. Weather complete devices or some parts are of interest, properties of metal-semiconductor junction strongly influence the quality and external characteristic of electronic devices. That is the reason why special attention is paid to the investigation of factor (noise for example) that could influence given junction. Low frequency 1/f fluctuations (noise) are constantly present in metal-semiconductor junction, so measurement of their level as well as the dependence on factors such as temperature must be taken into account in detailed analysis of electrical characteristics of devices such as contact, nuclear detector with surface barrier etc. In this paper we present the results of low frequency noise level measurements on TiN-Ti-Si structures produced by As + ion implantation. (author)

Promotion effect of monovalent metals (K and Cs) on the GaAs (110) surface oxidation

International Nuclear Information System (INIS)

Valeri, S.; Sberveglieri, P.; Angeli, E.

1987-01-01

The effect of thin (∼ 1 monolayer) overlayers of low electronegativity metals (Cs and K) on the RT oxidation behaviour of GaAs(110) cleavage surface is studied. This study was with Auger and Photoemission spectroscopies. Attention has been focused on the core-valence-valence and Auger lineshapes on the Ga and As 3d peaks. Presence of the alkali metal enhances the GaAs (110) oxidation rate several orders of magnitude above the clean surface value has been found. The range 0-100 Langmuir is investigated in detail. The oxidation process of the GaAs(110) surface in the presence of both K and Cs overlayer follows a multi-step kinetic and reaches a saturation at exposure lower than 100 Langmuir. Both Ga and As atoms are involved in the oxygen bonding. The metal enhanced semiconductor oxidation is generally reported to be a process involving predominantly the semiconductor surface atoms. However in the Cs - and K - GaAs case, an involvement of the alkali metal atoms too, reflected in the shape modification of their Auger line has been found. The promotion effect of K and Cs is discussed in terms of their low electronegativity and in comparison with the results recently reported in the literature for the other low electronegativity metals

A review of cobalt adsorption on transition metal oxides

International Nuclear Information System (INIS)

Walker, S.M.

1987-04-01

This report reviews studies of cobalt adsorption on transition metal oxides, in the context of corrosion product and radioactivity transport in PWR primary circuits. In general, uptake of cobalt increases with pH, with temperature and with decreasing ionic strength. Very little data are available under PWR primary circuit conditions, but the limited data available suggest that cobalt uptake by the zirconium oxide corrosion product layer on fuel pins may be significant compared to that deposited on fuel crud. If fuel crud levels can be reduced in future by coolant chemistry control then uptake by the zirconia will assume a greater relative role. It is planned to use an autoclave to study uptake of cobalt on oxidised Zircaloy surfaces at temperatures up to 593K under PWR primary circuit chemistry conditions. (author)

Rocksalt nitride metal/semiconductor superlattices: A new class of artificially structured materials

Science.gov (United States)

Saha, Bivas; Shakouri, Ali; Sands, Timothy D.

2018-06-01

Artificially structured materials in the form of superlattice heterostructures enable the search for exotic new physics and novel device functionalities, and serve as tools to push the fundamentals of scientific and engineering knowledge. Semiconductor heterostructures are the most celebrated and widely studied artificially structured materials, having led to the development of quantum well lasers, quantum cascade lasers, measurements of the fractional quantum Hall effect, and numerous other scientific concepts and practical device technologies. However, combining metals with semiconductors at the atomic scale to develop metal/semiconductor superlattices and heterostructures has remained a profoundly difficult scientific and engineering challenge. Though the potential applications of metal/semiconductor heterostructures could range from energy conversion to photonic computing to high-temperature electronics, materials challenges primarily had severely limited progress in this pursuit until very recently. In this article, we detail the progress that has taken place over the last decade to overcome the materials engineering challenges to grow high quality epitaxial, nominally single crystalline metal/semiconductor superlattices based on transition metal nitrides (TMN). The epitaxial rocksalt TiN/(Al,Sc)N metamaterials are the first pseudomorphic metal/semiconductor superlattices to the best of our knowledge, and their physical properties promise a new era in superlattice physics and device engineering.

Comparative analysis of oxide phase formation and its effects on electrical properties of SiO{sub 2}/InSb metal-oxide-semiconductor structures

Energy Technology Data Exchange (ETDEWEB)

Lee, Jaeyel [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Park, Sehun [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); WCU Hybrid Materials Program, Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Kim, Jungsub; Yang, Changjae; Kim, Sujin; Seok, Chulkyun [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Park, Jinsub [Department of Electronic Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Yoon, Euijoon, E-mail: eyoon@snu.ac.kr [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); WCU Hybrid Materials Program, Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Department of Nano Science and Technology, Graduate School of Convergence Science and Technology, Seoul National University, Suwon 443-270 (Korea, Republic of); Energy Semiconductor Research Center, Advanced Institutes of Convergence Technology, Seoul National University, Suwon 443-270 (Korea, Republic of)

2012-06-01

We report on the changes in the interfacial phases between SiO{sub 2} and InSb caused by various deposition temperatures and heat treatments. X-ray photoelectron spectroscopy (XPS) and Raman spectroscopy were used to evaluate the relative amount of each phase present at the interface. The effect of interfacial phases on the electrical properties of SiO{sub 2}/InSb metal-oxide-semiconductor (MOS) structures was investigated by capacitance-voltage (C-V) measurements. The amount of both In and Sb oxides increased with the deposition temperature. The amount of interfacial In oxide was larger for all samples, regardless of the deposition and annealing temperatures and times. In particular, the annealed samples contained less than half the amount of Sb oxide compared with the as-deposited samples, indicating a strong interfacial reaction between Sb oxide and the InSb substrate during annealing. The interface trap density sharply increased for deposition temperatures above 240 Degree-Sign C. The C-V measurements and Raman spectroscopy indicated that elemental Sb accumulation due to the interfacial reaction of Sb oxide with InSb substrate was responsible for the increased interfacial trap densities in these SiO{sub 2}/InSb MOS structures. - Highlights: Black-Right-Pointing-Pointer We report the quantitative analysis of interfacial oxides at the SiO{sub 2}/InSb interface. Black-Right-Pointing-Pointer Interfacial oxides were measured quantitatively by X-ray Photoelectron Spectroscopy. Black-Right-Pointing-Pointer As-grown and annealed samples showed different compositions of oxide phases. Black-Right-Pointing-Pointer Considerable reduction of antimony oxide phases was observed during annealing. Black-Right-Pointing-Pointer Interface trap densities at the SiO{sub 2}/InSb interface were calculated.

Integration of near infrared and visible organic photodiodes on a complementary metal–oxide–semiconductor compatible backplane

Energy Technology Data Exchange (ETDEWEB)

Jahnel, M.; Thomschke, M.; Fehse, K.; Vogel, U. [Fraunhofer-Institute for Organische Elektronik, Elektronenstrahl-und Plasmatechnik FEP, 01199 Dresden (Germany); An, J.D.; Park, H. [Konkuk University-Fraunhofer Next Generation Solar Cell Research Center (KFnSC), Konkuk University, 120 Neungdong-ro, Gwangjin-gu, Seoul 143-701 (Korea, Republic of); Leo, K. [Fraunhofer-Institute for Organische Elektronik, Elektronenstrahl-und Plasmatechnik FEP, 01199 Dresden (Germany); Institut für Angewandte Photophysik, Technische Universität Dresden (TUD), 01062 Dresden (Germany); Im, C. [Konkuk University-Fraunhofer Next Generation Solar Cell Research Center (KFnSC), Konkuk University, 120 Neungdong-ro, Gwangjin-gu, Seoul 143-701 (Korea, Republic of)

2015-10-01

This paper reports about the integration of polymer-based bulk heterojunction organic photo diodes (OPDs) onto complementary metal–oxide–semiconductor (CMOS) compatible electrode materials. The fabrication and performance of four absorber systems in indium tin oxide-free OPDs for sensing applications have been studied. These are based on the following polymer–fullerene blends: Poly(3-hexylthiophene-2,5-diyl):[6,6]Phenyl C{sub 61} Butyric Acid Methyl Ester and Poly(3-hexylthiophene-2,5 diyl):Di[1,4] methanonaphthaleno [1,2:2′,3′;56,60:2″,3″] [5,6]fullerene-C60-Ih, 1′,1″,4′,4″-tetrahydro-, indene-C60 bisadduct to detect light in the visible range and Poly[[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b′]dithiophene-2,6-diyl] [3-fluoro-2-[(2-ethylhexyl)carbonyl] thieno[3,4-b]thiophenediyl

Integration of near infrared and visible organic photodiodes on a complementary metal–oxide–semiconductor compatible backplane

International Nuclear Information System (INIS)

Jahnel, M.; Thomschke, M.; Fehse, K.; Vogel, U.; An, J.D.; Park, H.; Leo, K.; Im, C.

2015-01-01

This paper reports about the integration of polymer-based bulk heterojunction organic photo diodes (OPDs) onto complementary metal–oxide–semiconductor (CMOS) compatible electrode materials. The fabrication and performance of four absorber systems in indium tin oxide-free OPDs for sensing applications have been studied. These are based on the following polymer–fullerene blends: Poly(3-hexylthiophene-2,5-diyl):[6,6]Phenyl C_6_1 Butyric Acid Methyl Ester and Poly(3-hexylthiophene-2,5 diyl):Di[1,4] methanonaphthaleno [1,2:2′,3′;56,60:2″,3″] [5,6]fullerene-C60-Ih, 1′,1″,4′,4″-tetrahydro-, indene-C60 bisadduct to detect light in the visible range and Poly[[4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b′]dithiophene-2,6-diyl] [3-fluoro-2-[(2-ethylhexyl)carbonyl] thieno[3,4-b]thiophenediyl

Comparison of modification strategies towards enhanced charge carrier separation and photocatalytic degradation activity of metal oxide semiconductors (TiO2, WO3 and ZnO)

Science.gov (United States)

Kumar, S. Girish; Rao, K. S. R. Koteswara

2017-01-01

Metal oxide semiconductors (TiO2, WO3 and ZnO) finds unparalleled opportunity in wastewater purification under UV/visible light, largely encouraged by their divergent admirable features like stability, non-toxicity, ease of preparation, suitable band edge positions and facile generation of active oxygen species in the aqueous medium. However, the perennial failings of these photocatalysts emanates from the stumbling blocks like rapid charge carrier recombination and meager visible light response. In this review, tailoring the surface-bulk electronic structure through the calibrated and veritable approaches such as impurity doping, deposition with noble metals, sensitizing with other compounds (dyes, polymers, inorganic complexes and simple chelating ligands), hydrogenation process (annealing under hydrogen atmosphere), electronic integration with other semiconductors, modifying with carbon nanostructures, designing with exposed facets and tailoring with hierarchical morphologies to overcome their critical drawbacks are summarized. Taking into account the materials intrinsic properties, the pros and cons together with similarities and striking differences for each strategy in specific to TiO2, WO3 & ZnO are highlighted. These subtlety enunciates the primacy for improving the structure-electronic properties of metal oxides and credence to its fore in the practical applications. Future research must focus on comparing the performances of ZnO, TiO2 and WO3 in parallel to get insight into their photocatalytic behaviors. Such comparisons not only reveal the changed surface-electronic structure upon various modifications, but also shed light on charge carrier dynamics, free radical generation, structural stability and compatibility for photocatalytic reactions. It is envisioned that these cardinal tactics have profound implications and can be replicated to other semiconductor photocatalysts like CeO2, In2O3, Bi2O3, Fe2O3, BiVO4, AgX, BiOX (X = Cl, Br & I), Bi2WO6, Bi2MoO6

Influence of semiconductor/metal interface geometry in an EMR sensor

KAUST Repository

Sun, Jian

2013-02-01

The extraordinary magnetoresistance (EMR) is well known to be strongly dependent on geometric parameters. While the influence of the aspect ratios of the metal and semiconductor areas has been thoroughly investigated, the geometry of the semiconductor/metal interface has been neglected so far. However, from a fabrication point of view, this part plays a crucial role. In this paper, the performance of a bar-type hybrid EMR sensor is investigated by means of finite element method and experiments with respect to the hybrid interface geometry. A 3-D model has been developed, which simulates the EMR effect in case of fields in different directions. The semiconductor/metal interface has been investigated in terms of different layer thicknesses and overlaps. The results show that those parameters can cause a change in the output sensitivity of 2%-10%. In order to maintain a high sensitivity and keep the fabrication relatively simple and at low cost, a device with a thin metal shunt having a large overlap on the top of the semiconductor bar would provide the best solution. © 2001-2012 IEEE.

Modeling the dark current histogram induced by gold contamination in complementary-metal-oxide-semiconductor image sensors

Energy Technology Data Exchange (ETDEWEB)

Domengie, F., E-mail: florian.domengie@st.com; Morin, P. [STMicroelectronics Crolles 2 (SAS), 850 Rue Jean Monnet, 38926 Crolles Cedex (France); Bauza, D. [CNRS, IMEP-LAHC - Grenoble INP, Minatec: 3, rue Parvis Louis Néel, CS 50257, 38016 Grenoble Cedex 1 (France)

2015-07-14

We propose a model for dark current induced by metallic contamination in a CMOS image sensor. Based on Shockley-Read-Hall kinetics, the expression of dark current proposed accounts for the electric field enhanced emission factor due to the Poole-Frenkel barrier lowering and phonon-assisted tunneling mechanisms. To that aim, we considered the distribution of the electric field magnitude and metal atoms in the depth of the pixel. Poisson statistics were used to estimate the random distribution of metal atoms in each pixel for a given contamination dose. Then, we performed a Monte-Carlo-based simulation for each pixel to set the number of metal atoms the pixel contained and the enhancement factor each atom underwent, and obtained a histogram of the number of pixels versus dark current for the full sensor. Excellent agreement with the dark current histogram measured on an ion-implanted gold-contaminated imager has been achieved, in particular, for the description of the distribution tails due to the pixel regions in which the contaminant atoms undergo a large electric field. The agreement remains very good when increasing the temperature by 15 °C. We demonstrated that the amplification of the dark current generated for the typical electric fields encountered in the CMOS image sensors, which depends on the nature of the metal contaminant, may become very large at high electric field. The electron and hole emissions and the resulting enhancement factor are described as a function of the trap characteristics, electric field, and temperature.

Method of producing homogeneous mixed metal oxides and metal-metal oxide mixtures

International Nuclear Information System (INIS)

Quinby, T.C.

1980-01-01

A method for preparing particulate metal or metal oxide of controlled partile size comprises contacting an an aqueous solution containing dissolved metal values with excess urea at a temperature sufficient to cause urea to react with water to provide a molten urea solution containing the metal values; heating the molten urea solution to cause the metal values to precipitate, forming a mixture containing precipitated metal values; heating the mixture containing precipitated metal values to evaporate volatile material leaving a dry powder containing said metal values. The dry powder can be calcined to provide particulate metal oxide or reduced to provide particulate metal. Oxide mixtures are provided when the aqueous solution contains values of more than one metal. Homogeneousmetal-metal oxide mistures for preparing cermets can be prepared by selectively reducing at least one of the metal oxides. (auth)

Method of producing homogeneous mixed metal oxides and metal--metal oxide mixtures

International Nuclear Information System (INIS)

Quinby, T.C.

1978-01-01

Metal powders, metal oxide powders, and mixtures thereof of controlled particle size are provided by reacting an aqueous solution containing dissolved metal values with excess urea. Upon heating, urea reacts with water from the solution to leave a molten urea solution containing the metal values. The molten urea solution is heated to above about 180 0 C, whereupon metal values precipitate homogeneously as a powder. The powder is reduced to metal or calcined to form oxide particles. One or more metal oxides in a mixture can be selectively reduced to produce metal particles or a mixture of metal and metal oxide particles

Parasitic resistive switching uncovered from complementary resistive switching in single active-layer oxide memory device

Science.gov (United States)

Zhu, Lisha; Hu, Wei; Gao, Chao; Guo, Yongcai

2017-12-01

This paper reports the reversible transition processes between the bipolar and complementary resistive switching (CRS) characteristics on the binary metal-oxide resistive memory devices of Pt/HfO x /TiN and Pt/TaO x /TiN by applying the appropriate bias voltages. More interestingly, by controlling the amplitude of the negative bias, the parasitic resistive switching effect exhibiting repeatable switching behavior is uncovered from the CRS behavior. The electrical observation of the parasitic resistive switching effect can be explained by the controlled size of the conductive filament. This work confirms the transformation and interrelationship among the bipolar, parasitic, and CRS effects, and thus provides new insight into the understanding of the physical mechanism of the binary metal-oxide resistive switching memory devices.

Load Insensitive, Low Voltage Quadrature Oscillator Using Single Active Element

Directory of Open Access Journals (Sweden)

Jitendra Mohan

2017-01-01

Full Text Available In this paper, a load insensitive quadrature oscillator using single differential voltage dual-X second generation current conveyor operated at low voltage is proposed. The proposed circuit employs single active element, three grounded resistors and two grounded capacitors. The proposed oscillator offers two load insensitive quadrature current outputs and three quadrature voltage outputs simultaneously. Effects of non-idealities along with the effects of parasitic are further studied. The proposed circuit enjoys the feature of low active and passive sensitivities. Additionally, a resistorless realization of the proposed quadrature oscillator is also explored. Simulation results using PSPICE program on cadence tool using 90 nm Complementary Metal Oxide Semiconductor (CMOS process parameters confirm the validity and practical utility of the proposed circuit.

Photo-assisted local oxidation of GaN using an atomic force microscope

International Nuclear Information System (INIS)

Hwang, J S; Hu, Z S; Lu, T Y; Chen, L W; Chen, S W; Lin, T Y; Hsiao, C-L; Chen, K-H; Chen, L-C

2006-01-01

This paper introduces a photo-assisted atomic force microscope (AFM) local oxidation technique which is capable of producing highly smooth oxide patterns with heights reaching several tens of nanometres on both n- and p-types of GaN (and in principle on most semiconductors) without the use of chemicals. The novel methodology relies on UV illumination of the surface of the substrate during conventional AFM local oxidation. A low 1.2 V threshold voltage for n-type GaN was obtained, which can be explained by UV photo-generation of excess electron-hole pairs in the substrate near the junction, thereby reducing the electric field required to drive carrier flow through the tip-sample Schottky barrier. It was demonstrated that the presence or absence of light alone was sufficient to switch the growth of the oxide on or off. The photo-assisted AFM oxidation technique is of immediate interest to the semiconductor industry for the fabrication of GaN-based complementary metal-oxide-semiconductor devices and nanodevices, improves chances for AFM-type data storage, and presents new degrees of freedom for process control technique

Flexible ambipolar organic field-effect transistors with reverse-offset-printed silver electrodes for a complementary inverter.

Science.gov (United States)

Park, Junsu; Kim, Minseok; Yeom, Seung-Won; Ha, Hyeon Jun; Song, Hyenggun; Min Jhon, Young; Kim, Yun-Hi; Ju, Byeong-Kwon

2016-06-03

We report ambipolar organic field-effect transistors and complementary inverter circuits with reverse-offset-printed (ROP) Ag electrodes fabricated on a flexible substrate. A diketopyrrolopyrrole-based co-polymer (PDPP-TAT) was used as the semiconductor and poly(methyl methacrylate) was used as the gate insulator. Considerable improvement is observed in the n-channel electrical characteristics by inserting a cesium carbonate (Cs2CO3) as the electron-injection/hole-blocking layer at the interface between the semiconductors and the electrodes. The saturation mobility values are 0.35 cm(2) V(-1) s(-1) for the p-channel and 0.027 cm(2) V(-1) s(-1) for the n-channel. A complementary inverter is demonstrated based on the ROP process, and it is selectively controlled by the insertion of Cs2CO3 onto the n-channel region via thermal evaporation. Moreover, the devices show stable operation during the mechanical bending test using tensile strains ranging from 0.05% to 0.5%. The results confirm that these devices have great potential for use in flexible and inexpensive integrated circuits over a large area.

Generic process for preparing a crystalline oxide upon a group IV semiconductor substrate

Science.gov (United States)

McKee, Rodney A.; Walker, Frederick J.; Chisholm, Matthew F.

2000-01-01

A process for growing a crystalline oxide epitaxially upon the surface of a Group IV semiconductor, as well as a structure constructed by the process, is described. The semiconductor can be germanium or silicon, and the crystalline oxide can generally be represented by the formula (AO).sub.n (A'BO.sub.3).sub.m in which "n" and "m" are non-negative integer repeats of planes of the alkaline earth oxides or the alkaline earth-containing perovskite oxides. With atomic level control of interfacial thermodynamics in a multicomponent semiconductor/oxide system, a highly perfect interface between a semiconductor and a crystalline oxide can be obtained.

Covalent functionalization of carbon nanotube forests grown in situ on a metal-silicon chip

KAUST Repository

Johansson, Johan R.

2012-03-12

We report on the successful covalent functionalization of carbon nanotube (CNT) forests, in situ grown on a silicon chip with thin metal contact film as the buffer layer between the CNT forests and the substrate. The CNT forests were successfully functionalized with active amine and azide groups, which can be used for further chemical reactions. The morphology of the CNT forests was maintained after the functionalization. We thus provide a promising foundation for a miniaturized biosensor arrays system that can be easily integrated with Complementary Metal-Oxide Semiconductor (CMOS) technology.

Covalent functionalization of carbon nanotube forests grown in situ on a metal-silicon chip

KAUST Repository

Johansson, Johan R.; Bosaeus, Niklas; Kann, Nina; Å kerman, Bjö rn; Nordé n, Bengt; Khalid, Waqas

2012-01-01

We report on the successful covalent functionalization of carbon nanotube (CNT) forests, in situ grown on a silicon chip with thin metal contact film as the buffer layer between the CNT forests and the substrate. The CNT forests were successfully functionalized with active amine and azide groups, which can be used for further chemical reactions. The morphology of the CNT forests was maintained after the functionalization. We thus provide a promising foundation for a miniaturized biosensor arrays system that can be easily integrated with Complementary Metal-Oxide Semiconductor (CMOS) technology.

Emerging Applications for High K Materials in VLSI Technology

Science.gov (United States)

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

Emerging Applications for High K Materials in VLSI Technology

Directory of Open Access Journals (Sweden)

Robert D. Clark

2014-04-01

Full Text Available The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI manufacturing for leading edge Dynamic Random Access Memory (DRAM and Complementary Metal Oxide Semiconductor (CMOS applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

Si micro photonics for optical interconnection

International Nuclear Information System (INIS)

Wada, K.; Ahn, D.H.; Lim, D.R.; Michel, J.; Kimerling, L.C.

2006-01-01

This paper reviews current status of silicon microphotonics and the recent prototype of on-chip optical interconnection. Si microphotonics pursues complementary metal oxide semiconductor (CMOS)-compatibility of photonic devices to reduce the materials diversity eventually to integrate on Si chips. Fractal optical H-trees have been implemented on a chip and found to be a technology breakthrough beyond metal interconnection. It has shown that large RC time constants associated with metal can be eliminated at least long distant data communication on a chip, and eventually improve yield and power issues. This has become the world's first electronic and photonic integrated circuits (EPICs) and the possibility of at least 10 GHz clocking for personal computers has been demonstrated

Perspective: The future of quantum dot photonic integrated circuits

Directory of Open Access Journals (Sweden)

Justin C. Norman

2018-03-01

Full Text Available Direct epitaxial integration of III-V materials on Si offers substantial manufacturing cost and scalability advantages over heterogeneous integration. The challenge is that epitaxial growth introduces high densities of crystalline defects that limit device performance and lifetime. Quantum dot lasers, amplifiers, modulators, and photodetectors epitaxially grown on Si are showing promise for achieving low-cost, scalable integration with silicon photonics. The unique electrical confinement properties of quantum dots provide reduced sensitivity to the crystalline defects that result from III-V/Si growth, while their unique gain dynamics show promise for improved performance and new functionalities relative to their quantum well counterparts in many devices. Clear advantages for using quantum dot active layers for lasers and amplifiers on and off Si have already been demonstrated, and results for quantum dot based photodetectors and modulators look promising. Laser performance on Si is improving rapidly with continuous-wave threshold currents below 1 mA, injection efficiencies of 87%, and output powers of 175 mW at 20 °C. 1500-h reliability tests at 35 °C showed an extrapolated mean-time-to-failure of more than ten million hours. This represents a significant stride toward efficient, scalable, and reliable III-V lasers on on-axis Si substrates for photonic integrate circuits that are fully compatible with complementary metal-oxide-semiconductor (CMOS foundries.

Perspective: The future of quantum dot photonic integrated circuits

Science.gov (United States)

Norman, Justin C.; Jung, Daehwan; Wan, Yating; Bowers, John E.

2018-03-01

Direct epitaxial integration of III-V materials on Si offers substantial manufacturing cost and scalability advantages over heterogeneous integration. The challenge is that epitaxial growth introduces high densities of crystalline defects that limit device performance and lifetime. Quantum dot lasers, amplifiers, modulators, and photodetectors epitaxially grown on Si are showing promise for achieving low-cost, scalable integration with silicon photonics. The unique electrical confinement properties of quantum dots provide reduced sensitivity to the crystalline defects that result from III-V/Si growth, while their unique gain dynamics show promise for improved performance and new functionalities relative to their quantum well counterparts in many devices. Clear advantages for using quantum dot active layers for lasers and amplifiers on and off Si have already been demonstrated, and results for quantum dot based photodetectors and modulators look promising. Laser performance on Si is improving rapidly with continuous-wave threshold currents below 1 mA, injection efficiencies of 87%, and output powers of 175 mW at 20 °C. 1500-h reliability tests at 35 °C showed an extrapolated mean-time-to-failure of more than ten million hours. This represents a significant stride toward efficient, scalable, and reliable III-V lasers on on-axis Si substrates for photonic integrate circuits that are fully compatible with complementary metal-oxide-semiconductor (CMOS) foundries.

Injection of holes at indium tin oxide/dendrimer interface: An explanation with new theory of thermionic emission at metal/organic interfaces

International Nuclear Information System (INIS)

Peng Yingquan; Lu Feiping

2006-01-01

The traditional theory of thermionic emission at metal/inorganic crystalline semiconductor interfaces is no longer applicable for the interface between a metal and an organic semiconductor. Under the assumption of thermalization of hot carriers in the organic semiconductor near the interface, a theory for thermionic emission of charge carriers at metal/organic semiconductor interfaces is developed. This theory is used to explain the experimental result from Samuel group [J.P.J. Markham, D.W. Samuel, S.-C. Lo, P.L. Burn, M. Weiter, H. Baessler, J. Appl. Phys. 95 (2004) 438] for the injection of holes from indium tin oxide into the dendrimer based on fac-tris(2-phenylpyridyl) iridium(III)

Atomic switches: atomic-movement-controlled nanodevices for new types of computing

International Nuclear Information System (INIS)

Hino, Takami; Hasegawa, Tsuyoshi; Terabe, Kazuya; Tsuruoka, Tohru; Nayak, Alpana; Ohno, Takeo; Aono, Masakazu

2011-01-01

Atomic switches are nanoionic devices that control the diffusion of metal cations and their reduction/oxidation processes in the switching operation to form/annihilate a metal atomic bridge, which is a conductive path between two electrodes in the on-state. In contrast to conventional semiconductor devices, atomic switches can provide a highly conductive channel even if their size is of nanometer order. In addition to their small size and low on-resistance, their nonvolatility has enabled the development of new types of programmable devices, which may achieve all the required functions on a single chip. Three-terminal atomic switches have also been developed, in which the formation and annihilation of a metal atomic bridge between a source electrode and a drain electrode are controlled by a third (gate) electrode. Three-terminal atomic switches are expected to enhance the development of new types of logic circuits, such as nonvolatile logic. The recent development of atomic switches that use a metal oxide as the ionic conductive material has enabled the integration of atomic switches with complementary metal-oxide-semiconductor (CMOS) devices, which will facilitate the commercialization of atomic switches. The novel characteristics of atomic switches, such as their learning and photosensing abilities, are also introduced in the latter part of this review. (topical review)

Investigation of structural and electrical properties on substrate material for high frequency metal-oxide-semiconductor (MOS) devices

Science.gov (United States)

Kumar, M.; Yang, Sung-Hyun; Janardhan Reddy, K.; JagadeeshChandra, S. V.

2017-04-01

Hafnium oxide (HfO2) thin films were grown on cleaned P-type Ge and Si substrates by using atomic layer deposition technique (ALD) with thickness of 8 nm. The composition analysis of as-deposited and annealed HfO2 films was characterized by XPS, further electrical measurements; we fabricated the metal-oxide-semiconductor (MOS) devices with Pt electrode. Post deposition annealing in O2 ambient at 500 °C for 30 min was carried out on both Ge and Si devices. Capacitance-voltage (C-V) and conductance-voltage (G-V) curves measured at 1 MHz. The Ge MOS devices showed improved interfacial and electrical properties, high dielectric constant (~19), smaller EOT value (0.7 nm), and smaller D it value as Si MOS devices. The C-V curves shown significantly high accumulation capacitance values from Ge devices, relatively when compare with the Si MOS devices before and after annealing. It could be due to the presence of very thin interfacial layer at HfO2/Ge stacks than HfO2/Si stacks conformed by the HRTEM images. Besides, from current-voltage (I-V) curves of the Ge devices exhibited similar leakage current as Si devices. Therefore, Ge might be a reliable substrate material for structural, electrical and high frequency applications.

Semiconductor photocatalysts for water oxidation: current status and challenges.

Science.gov (United States)

Yang, Lingling; Zhou, Han; Fan, Tongxiang; Zhang, Di

2014-04-21

Artificial photosynthesis is a highly-promising strategy to convert solar energy into hydrogen energy for the relief of the global energy crisis. Water oxidation is the bottleneck for its kinetic and energetic complexity in the further enhancement of the overall efficiency of the artificial photosystem. Developing efficient and cost-effective photocatalysts for water oxidation is a growing desire, and semiconductor photocatalysts have recently attracted more attention due to their stability and simplicity. This article reviews the recent advancement of semiconductor photocatalysts with a focus on the relationship between material optimization and water oxidation efficiency. A brief introduction to artificial photosynthesis and water oxidation is given first, followed by an explanation of the basic rules and mechanisms of semiconductor particulate photocatalysts for water oxidation as theoretical references for discussions of componential, surface structure, and crystal structure modification. O2-evolving photocatalysts in Z-scheme systems are also introduced to demonstrate practical applications of water oxidation photocatalysts in artificial photosystems. The final part proposes some challenges based on the dynamics and energetics of photoholes which are fundamental to the enhancement of water oxidation efficiency, as well as on the simulation of natural water oxidation that will be a trend in future research.

Single-electron regime and Pauli spin blockade in a silicon metal-oxide-semiconductor double quantum dot

Science.gov (United States)

Rochette, Sophie; Ten Eyck, Gregory A.; Pluym, Tammy; Lilly, Michael P.; Carroll, Malcolm S.; Pioro-Ladrière, Michel

2015-03-01

Silicon quantum dots are promising candidates for quantum information processing as spin qubits with long coherence time. We present electrical transport measurements on a silicon metal-oxide-semiconductor (MOS) double quantum dot (DQD). First, Coulomb diamonds measurements demonstrate the one-electron regime at a relatively high temperature of 1.5 K. Then, the 8 mK stability diagram shows Pauli spin blockade with a large singlet-triplet separation of approximatively 0.40 meV, pointing towards a strong lifting of the valley degeneracy. Finally, numerical simulations indicate that by integrating a micro-magnet to those devices, we could achieve fast spin rotations of the order of 30 ns. Those results are part of the recent body of work demonstrating the potential of Si MOS DQD as reliable and long-lived spin qubits that could be ultimately integrated into modern electronic facilities. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. DOE's National Nuclear Security Administration under Contract DE-AC04-94AL85000.

Temperature Modulation with Specified Detection Point on Metal Oxide Semiconductor Gas Sensors for E-Nose Application

Directory of Open Access Journals (Sweden)

Arief SUDARMAJI

2015-03-01

Full Text Available Temperature modulation technique, some called dynamic measurement mode, on Metal-Oxide Semiconductor (MOS/MOX gas sensor has been widely observed and employed in many fields. We present its development, a Specified Detection Point (SDP on modulated sensing element of MOS sensor is applied which associated to its temperature modulation, temperature modulation-SDP so-named. We configured the rectangular modulation signal for MOS gas sensors (TGSs and FISs using PSOC CY8C28445-24PVXI (Programmable System on Chip which also functioned as acquisition unit and interface to a computer. Initial responses and selectivity evaluations were performed using statistical tool and Principal Component Analysis (PCA to differ sample gases (Toluene, Ethanol and Ammonia on dynamic chamber measurement under various frequencies (0.25 Hz, 1 Hz, 4 Hz and duty-cycles (25 %, 50 %, 75 %. We found that at lower frequency the response waveform of the sensors becomes more sloping and distinct, and selected modulations successfully increased the selectivity either on singular or array sensors rather than static temperature measurement.

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

International Nuclear Information System (INIS)

Takano, H.; Hosogi, K.; Kato, T.

1995-01-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs

Large-area processing of solution type metal-oxide in TFT backplanes and integration in highly stable OLED displays

NARCIS (Netherlands)

Marinkovic, Marko; Takata, Ryo; Neumann, Anita; Pham, Duy Vu; Anselmann, Ralf; Maas, Joris; Van Der Steen, Jan Laurens; Gelinck, Gerwin; Katsouras, Ilias

2017-01-01

Solution type metal-oxide semiconductor was processed on mass-production ready equipment and integrated in a backplane with ESL architecture TFTs. Excellent thickness uniformity of the semiconductor layer was obtained over the complete Gen I glass substrate (320 mm ×00D7; 352 mm), resulting in

Bioleaching of metals from printed circuit boards supported with surfactant-producing bacteria

International Nuclear Information System (INIS)

Karwowska, Ewa; Andrzejewska-Morzuch, Dorota; Łebkowska, Maria; Tabernacka, Agnieszka; Wojtkowska, Małgorzata; Telepko, Alicja; Konarzewska, Agnieszka

2014-01-01

Highlights: • Bioleaching of metals from printed circuit boards by BSAC-producing bacteria was estimated. • Aeration increased the release of all metals in medium with sulphur and biosurfactant. • Increase in Cu, Pb, Ni and Cr removal rate was observed at 37 °C in acidic medium. -- Abstract: This study has evaluated the possibility of bioleaching zinc, copper, lead, nickel, cadmium and chromium from printed circuit boards by applying a culture of sulphur-oxidising bacteria and a mixed culture of biosurfactant-producing bacteria and sulphur-oxidising bacteria. It was revealed that zinc was removed effectively both in a traditional solution acidified by a way of microbial oxidation of sulphur and when using a microbial culture containing sulphur-oxidising and biosurfactant-producing bacteria. The average process efficiency was 48% for Zn dissolution. Cadmium removal was similar in both media, with a highest metal release of 93%. For nickel and copper, a better effect was obtained in the acidic medium, with a process effectiveness of 48.5% and 53%, respectively. Chromium was the only metal that was removed more effectively in the bioleaching medium containing both sulphur-oxidising and biosurfactant-producing bacteria. Lead was removed from the printed circuit boards with very low effectiveness (below 0.5%). Aerating the culture medium with compressed air increased the release of all metals in the medium with sulphur and biosurfactant, and of Ni, Cu, Zn and Cr in the acidic medium. Increasing the temperature of the medium (to 37 °C) had a more significant impact in the acidic environment than in the neutral environment

Bioleaching of metals from printed circuit boards supported with surfactant-producing bacteria

Energy Technology Data Exchange (ETDEWEB)

Karwowska, Ewa, E-mail: ewa.karwowska@is.pw.edu.pl [Warsaw University of Technology, Faculty of Environmental Engineering, Biology Division, Nowowiejska 20, 00-653 Warsaw (Poland); Andrzejewska-Morzuch, Dorota; Łebkowska, Maria [Warsaw University of Technology, Faculty of Environmental Engineering, Biology Division, Nowowiejska 20, 00-653 Warsaw (Poland); Tabernacka, Agnieszka, E-mail: agnieszka.tabernacka@is.pw.edu.pl [Warsaw University of Technology, Faculty of Environmental Engineering, Biology Division, Nowowiejska 20, 00-653 Warsaw (Poland); Wojtkowska, Małgorzata; Telepko, Alicja; Konarzewska, Agnieszka [Warsaw University of Technology, Faculty of Environmental Engineering, Nowowiejska 20, 00-653 Warsaw (Poland)

2014-01-15

Highlights: • Bioleaching of metals from printed circuit boards by BSAC-producing bacteria was estimated. • Aeration increased the release of all metals in medium with sulphur and biosurfactant. • Increase in Cu, Pb, Ni and Cr removal rate was observed at 37 °C in acidic medium. -- Abstract: This study has evaluated the possibility of bioleaching zinc, copper, lead, nickel, cadmium and chromium from printed circuit boards by applying a culture of sulphur-oxidising bacteria and a mixed culture of biosurfactant-producing bacteria and sulphur-oxidising bacteria. It was revealed that zinc was removed effectively both in a traditional solution acidified by a way of microbial oxidation of sulphur and when using a microbial culture containing sulphur-oxidising and biosurfactant-producing bacteria. The average process efficiency was 48% for Zn dissolution. Cadmium removal was similar in both media, with a highest metal release of 93%. For nickel and copper, a better effect was obtained in the acidic medium, with a process effectiveness of 48.5% and 53%, respectively. Chromium was the only metal that was removed more effectively in the bioleaching medium containing both sulphur-oxidising and biosurfactant-producing bacteria. Lead was removed from the printed circuit boards with very low effectiveness (below 0.5%). Aerating the culture medium with compressed air increased the release of all metals in the medium with sulphur and biosurfactant, and of Ni, Cu, Zn and Cr in the acidic medium. Increasing the temperature of the medium (to 37 °C) had a more significant impact in the acidic environment than in the neutral environment.

Optical properties of hybrid semiconductor-metal structures

Energy Technology Data Exchange (ETDEWEB)

Kreilkamp, L.E.; Pohl, M.; Akimov, I.A.; Yakovlev, D.R.; Bayer, M. [Experimentelle Physik 2, Technische Universitaet Dortmund, 44221 Dortmund (Germany); Belotelov, V.I.; Zvezdin, A.K. [A.M. Prokhorov General Physics Institute, Russian Academy of Sciences, 119992 Moscow (Russian Federation); Karczewski, G.; Wojtowicz, T. [Institute of Physics, Polish Academy of Sciences, 02668 Warsaw (Poland); Rudzinski, A.; Kahl, M. [Raith GmbH, Konrad-Adenauer-Allee 8, 44263 Dortmund (Germany)

2012-07-01

We study the optical properties of hybrid nanostructures comprising a semiconductor CdTe quantum well (QW) separated by a thin CdMgTe cap layer of 40 nm from a patterned gold film. The CdTe/CdMgTe QW structure with a well width of 10nm was grown by molecular beam epitaxy. The one-dimensional periodic gold films on top were made using e-beam lithography and lift-off process. The investigated structures can be considered as plasmonic crystals because the metal films attached to the semiconductor are patterned with a period in the range from 475 to 600 nm, which is comparable to the surface plasmon-polariton (SPP) wavelength. Angle dependent reflection spectra at room temperature clearly show plasmonic resonances. PL spectra taken at low temperatures of about 10 K under below- and above-barrier illumination show significant modifications compared to the unstructured QW sample. The number of emission lines and their position shift change depending on the excitation energy. The role of exciton-SPP coupling and Schottky barrier at the semiconductor-metal interface are discussed.

Surface chemistry of metals and their oxides in high temperature water

International Nuclear Information System (INIS)

Tomlinson, M.

1975-01-01

Examination of oxide and metal surfaces in water at high temperature by a broad spectrum of techniques is bringing understanding of corrosion product movement and alleviation of activity transport in CANDU-type reactor primary coolant circuits. (Author)

Emission channeling with short-lived isotopes lattice location of impurities in semiconductors and oxides

CERN Multimedia

We propose to perform emission channeling lattice location experiments in a number of semiconductor and oxide systems of technological relevance: \\\\- The lattice location of the transition metal probes $^{56}$Mn ($\\textit{t}_{1/2}$=2.6 h), $^{59}$Fe (45 d), $^{61}$Co (1.6 h) and $^{65}$Ni (2.5 h) is to be investigated in materials of interest as dilute magnetic semiconductors, such as GaMnAs, GaMnN, GaFeN, AlGaN, SiC, and in a number of oxides that are candidates for “single ion ferromagnetism”, in particular SrTiO$_3$ and LiNbO$_3$.\\\\- The topic of $\\textit{p}$-type doping of nitride semiconductors shall be addressed by studying the lattice sites of the acceptor dopants Mg and Be in GaN and AlN using the short-lived probes $^{27}$Mg (9.5 min) and $^{11}$Be (13.8 s). The aim is to reach a lattice location precision around 0.05 Å in order to provide critical tests for recent theoretical models which e.g. have predicted displacements of the Mg atom from the ideal substitutional Ga and Al sites of the order...

Plasmonic doped semiconductor nanocrystals: Properties, fabrication, applications and perspectives

Science.gov (United States)

Kriegel, Ilka; Scotognella, Francesco; Manna, Liberato

2017-02-01

Degenerately doped semiconductor nanocrystals (NCs) are of recent interest to the NC community due to their tunable localized surface plasmon resonances (LSPRs) in the near infrared (NIR). The high level of doping in such materials with carrier densities in the range of 1021cm-3 leads to degeneracy of the doping levels and intense plasmonic absorption in the NIR. The lower carrier density in degenerately doped semiconductor NCs compared to noble metals enables LSPR tuning over a wide spectral range, since even a minor change of the carrier density strongly affects the spectral position of the LSPR. Two classes of degenerate semiconductors are most relevant in this respect: impurity doped semiconductors, such as metal oxides, and vacancy doped semiconductors, such as copper chalcogenides. In the latter it is the density of copper vacancies that controls the carrier concentration, while in the former the introduction of impurity atoms adds carriers to the system. LSPR tuning in vacancy doped semiconductor NCs such as copper chalcogenides occurs by chemically controlling the copper vacancy density. This goes in hand with complex structural modifications of the copper chalcogenide crystal lattice. In contrast the LSPR of degenerately doped metal oxide NCs is modified by varying the doping concentration or by the choice of host and dopant atoms, but also through the addition of capacitive charge carriers to the conduction band of the metal oxide upon post-synthetic treatments, such as by electrochemical- or photodoping. The NIR LSPRs and the option of their spectral fine-tuning make accessible important new features, such as the controlled coupling of the LSPR to other physical signatures or the enhancement of optical signals in the NIR, sensing application by LSPR tracking, energy production from the NIR plasmon resonance or bio-medical applications in the biological window. In this review we highlight the recent advances in the synthesis of various different plasmonic

Impact of GaN cap on charges in Al₂O₃/(GaN/)AlGaN/GaN metal-oxide-semiconductor heterostructures analyzed by means of capacitance measurements and simulations

Energy Technology Data Exchange (ETDEWEB)

Ťapajna, M., E-mail: milan.tapajna@savba.sk; Jurkovič, M.; Válik, L.; Haščík, Š.; Gregušová, D.; Kuzmík, J. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, 841 04 Bratislava (Slovakia); Brunner, F.; Cho, E.-M. [Ferdinand-Braun-Institut, Leibniz Institut für Höchstfrequenztechnik, Gustav-Kirchhoff-Strasse 4, 12489 Berlin (Germany); Hashizume, T. [Research Center for Integrated Quantum Electronics (RCIQE), Hokkaido University, 060-0814 Sapporo, Japan and JST-CREST, 102-0075 Tokyo (Japan)

2014-09-14

Oxide/semiconductor interface trap density (D{sub it}) and net charge of Al₂O₃/(GaN)/AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor (MOS-HEMT) structures with and without GaN cap were comparatively analyzed using comprehensive capacitance measurements and simulations. D{sub it} distribution was determined in full band gap of the barrier using combination of three complementary capacitance techniques. A remarkably higher D{sub it} (∼5–8 × 10¹²eV⁻¹ cm⁻²) was found at trap energies ranging from E_C-0.5 to 1 eV for structure with GaN cap compared to that (D{sub it} ∼ 2–3 × 10¹²eV⁻¹ cm⁻²) where the GaN cap was selectively etched away. D{sub it} distributions were then used for simulation of capacitance-voltage characteristics. A good agreement between experimental and simulated capacitance-voltage characteristics affected by interface traps suggests (i) that very high D{sub it} (>10¹³eV⁻¹ cm⁻²) close to the barrier conduction band edge hampers accumulation of free electron in the barrier layer and (ii) the higher D{sub it} centered about E_C-0.6 eV can solely account for the increased C-V hysteresis observed for MOS-HEMT structure with GaN cap. Analysis of the threshold voltage dependence on Al₂O₃ thickness for both MOS-HEMT structures suggests that (i) positive charge, which compensates the surface polarization, is not necessarily formed during the growth of III-N heterostructure, and (ii) its density is similar to the total surface polarization charge of the GaN/AlGaN barrier, rather than surface polarization of the top GaN layer only. Some constraints for the positive surface compensating charge are discussed.

Dry etching technology for semiconductors

CERN Document Server

Nojiri, Kazuo

2015-01-01

This book is a must-have reference to dry etching technology for semiconductors, which will enable engineers to develop new etching processes for further miniaturization and integration of semiconductor integrated circuits.  The author describes the device manufacturing flow, and explains in which part of the flow dry etching is actually used. The content is designed as a practical guide for engineers working at chip makers, equipment suppliers and materials suppliers, and university students studying plasma, focusing on the topics they need most, such as detailed etching processes for each material (Si, SiO2, Metal etc) used in semiconductor devices, etching equipment used in manufacturing fabs, explanation of why a particular plasma source and gas chemistry are used for the etching of each material, and how to develop etching processes.  The latest, key technologies are also described, such as 3D IC Etching, Dual Damascene Etching, Low-k Etching, Hi-k/Metal Gate Etching, FinFET Etching, Double Patterning ...

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors

Directory of Open Access Journals (Sweden)

Xiaoliang Ge

2018-02-01

Full Text Available This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.

Semiconductor-metal transition induced by giant Stark effect in blue phosphorene nanoribbons

Energy Technology Data Exchange (ETDEWEB)

Xiong, Peng-Yu; Chen, Shi-Zhang; Zhou, Wu-Xing; Chen, Ke-Qiu, E-mail: keqiuchen@hnu.edu.cn

2017-06-28

The electronic structures and transport properties in monolayer blue phosphorene nanoribbons (BPNRs) with transverse electric field have been studied by using density functional theory and nonequilibrium Green's functions method. The results show that the band gaps of BPNRs with both armchair and zigzag edges are linearly decreased with the increasing of the strength of transverse electric field. A semiconductor-metal transition occurs when the electric field strength reaches to 5 V/nm. The Stark coefficient presents a linear dependency on BPNRs widths, and the slopes of both zBPNRs and aBPNRs are 0.41 and 0.54, respectively, which shows a giant Stark effect occurs. Our studies show that the semiconductor-metal transition originates from the giant Stark effect. - Highlights: • The electronic transport in blue phosphorene nanoribbons. • Semiconductor-metal transition can be observed. • The semiconductor-metal transition originates from the giant Stark effect.

Review on analog/radio frequency performance of advanced silicon MOSFETs

Science.gov (United States)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Contribution to the study of rectification at the metal-semiconductor contact: analysis of aging in silicon Schottky diodes

International Nuclear Information System (INIS)

Ponpon, J.-P.

1979-01-01

The formation of the barrier height and the aging of metal-semiconductor contacts during exposure to air have been studied. The evolution of the electrical characteristics, especially the barrier height, of silicon Schottky diodes results from the diffusion of oxygen through the electrode and its accumulation at the interface. The diffusion coefficient of oxygen has been deduced for each metal used. In a first step the oxygen neutralize a fixed positive charge which remains at the semiconductor surface after etching; then, as silicon is oxidized, a MIS device is formed. Similar results have been obtained in the case of germanium, while no aging appears with cadmium telluride. In this case the barrier height seems to be determined by chemical reactions at the interface [fr

Current-Voltage Characteristics of the Metal / Organic Semiconductor / Metal Structures: Top and Bottom Contact Configuration Case

Directory of Open Access Journals (Sweden)

Šarūnas MEŠKINIS

2013-03-01

Full Text Available In present study five synthesized organic semiconductor compounds have been used for fabrication of the planar metal / organic semiconductor / metal structures. Both top electrode and bottom electrode configurations were used. Current-voltage (I-V characteristics of the samples were investigated. Effect of the hysteresis of the I-V characteristics was observed for all the investigated samples. However, strength of the hysteresis was dependent on the organic semiconductor used. Study of I-V characteristics of the top contact Al/AT-RB-1/Al structures revealed, that in (0 – 500 V voltages range average current of the samples measured in air is only slightly higher than current measured in nitrogen ambient. Deposition of the ultra-thin diamond like carbon interlayer resulted in both decrease of the hysteresis of I-V characteristics of top contact Al/AT-RB-1/Al samples. However, decreased current and decreased slope of the I-V characteristics of the samples with diamond like carbon interlayer was observed as well. I-V characteristic hysteresis effect was less pronounced in the case of the bottom contact metal/organic semiconductor/metal samples. I-V characteristics of the bottom contact samples were dependent on electrode metal used.DOI: http://dx.doi.org/10.5755/j01.ms.19.1.3816

Fabrication and operation methods of a one-time programmable (OTP) nonvolatile memory (NVM) based on a metal-oxide-semiconductor structure

International Nuclear Information System (INIS)

Cho, Seongjae; Lee, Junghoon; Jung, Sunghun; Park, Sehwan; Park, Byunggook

2011-01-01

In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array based on a metal-insulator-semiconductor (MIS) structure is proposed. The Iindividual memory device has a vertical channel of a silicon diode. Historically, OTP memories were widely used for read-only-memories (ROMs), in which the most basic system architecture model was to store central processing unit (CPU) instructions. By grafting the nanoscale fabrication technology and novel structuring onto the concept of the OTP memory, innovative high-density NVM appliances for mobile storage media may be possible. The program operation is performed by breaking down the thin oxide layer between the pn diode structure and the wordline (WL). The programmed state can be identified by an operation that reads the leakage currents through the broken oxide. Since the proposed OTP NVM is based on neither a transistor structure nor a charge storing mechanism, it is highly reliable and functional for realizing the ultra-large scale integration. The operation physics and the fabrication processes are also explained in detail.

Low Power Operation of Temperature-Modulated Metal Oxide Semiconductor Gas Sensors.

Science.gov (United States)

Burgués, Javier; Marco, Santiago

2018-01-25

Mobile applications based on gas sensing present new opportunities for low-cost air quality monitoring, safety, and healthcare. Metal oxide semiconductor (MOX) gas sensors represent the most prominent technology for integration into portable devices, such as smartphones and wearables. Traditionally, MOX sensors have been continuously powered to increase the stability of the sensing layer. However, continuous power is not feasible in many battery-operated applications due to power consumption limitations or the intended intermittent device operation. This work benchmarks two low-power, duty-cycling, and on-demand modes against the continuous power one. The duty-cycling mode periodically turns the sensors on and off and represents a trade-off between power consumption and stability. On-demand operation achieves the lowest power consumption by powering the sensors only while taking a measurement. Twelve thermally modulated SB-500-12 (FIS Inc. Jacksonville, FL, USA) sensors were exposed to low concentrations of carbon monoxide (0-9 ppm) with environmental conditions, such as ambient humidity (15-75% relative humidity) and temperature (21-27 °C), varying within the indicated ranges. Partial Least Squares (PLS) models were built using calibration data, and the prediction error in external validation samples was evaluated during the two weeks following calibration. We found that on-demand operation produced a deformation of the sensor conductance patterns, which led to an increase in the prediction error by almost a factor of 5 as compared to continuous operation (2.2 versus 0.45 ppm). Applying a 10% duty-cycling operation of 10-min periods reduced this prediction error to a factor of 2 (0.9 versus 0.45 ppm). The proposed duty-cycling powering scheme saved up to 90% energy as compared to the continuous operating mode. This low-power mode may be advantageous for applications that do not require continuous and periodic measurements, and which can tolerate slightly higher

Electrical characterization of Ω-gated uniaxial tensile strained Si nanowire-array metal-oxide-semiconductor field effect transistors with - and channel orientations

International Nuclear Information System (INIS)

Habicht, Stefan; Feste, Sebastian; Zhao, Qing-Tai; Buca, Dan; Mantl, Siegfried

2012-01-01

Nanowire-array metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated along and crystal directions on (001) un-/strained silicon-on-insulator substrates. Lateral strain relaxation through patterning was employed to transform biaxial tensile strain into uniaxial tensile strain along the nanowire. Devices feature ideal subthreshold swings and maximum on-current/off-current ratios of 10 11 for n and p-type transistors on both substrates. Electron and hole mobilities were extracted by split C–V method. For p-MOSFETs an increased mobility is observed for channel direction devices compared to devices. The n-MOSFETs showed a 45% increased electron mobility compared to devices. The comparison of strained and unstrained n-MOSFETs along and clearly demonstrates improved electron mobilities for strained channels of both channel orientations.

Effect of 1MeV electron beam on transistors and circuits