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Sample records for cmos sp chip

  1. Packaging commercial CMOS chips for lab on a chip integration.

    Science.gov (United States)

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems.

  2. A Modular Programmable CMOS Analog Fuzzy Controller Chip

    OpenAIRE

    1999-01-01

    We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area a...

  3. Single-chip RF communications systems in CMOS

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  4. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  5. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    NARCIS (Netherlands)

    Lu, Jiwu; Liu, Wei; Kovalgin, Alexey Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  6. Seamless integration of CMOS and microfluidics using flip chip bonding

    Science.gov (United States)

    Welch, David; Blain Christen, Jennifer

    2013-03-01

    We demonstrate the microassembly of PDMS (polydimethylsiloxane) microfluidics with integrated circuits made in complementary metal-oxide-semiconductor (CMOS) processes. CMOS-sized chips are flip chip bonded to a flexible polyimide printed circuit board (PCB) with commercially available solder paste patterned using a SU-8 epoxy. The average resistance of each flip chip bond is negligible and all connections are electrically isolated. PDMS is attached to the flexible polyimide PCB using a combination of oxygen plasma treatment and chemical bonding with 3-aminopropyltriethoxysilane. The total device has a burst pressure of 175 kPA which is limited by the strength of the flip chip attachment. This technique allows the sensor area of the die to act as the bottom of the microfluidic channel. The SU-8 provides a barrier between the pad ring (electrical interface) and the fluids; post-processing is not required on the CMOS die. This assembly method shows great promise for developing analytic systems which combine the strengths of microelectronics and microfluidics into one device.

  7. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  8. CMOS realization of a 2-layer CNN universal machine chip.

    Science.gov (United States)

    Carmona, R; Jiménez-Garrido, F; Domínguez-Castro, R; Espejo, S; Rodríguez-Vázquez, A

    2003-12-01

    Some features of the biological retina can be modelled by a 2-layer cellular neural network (CNN) composed of locally connected elementary nonlinear processors. In order to explore these complex spatiotemporal dynamics for image processing, a prototype chip has been designed and fabricated in a 0.5 microm CMOS technology. Design challenges, trade-offs, the building blocks and the tests results for this system with 0.5 x 10(6) transistors, most of them operating in analog mode, are presented in this paper.

  9. An analog CMOS chip set for neural networks with arbitrary topologies

    DEFF Research Database (Denmark)

    Lansner, John; Lehmann, Torsten

    1993-01-01

    An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus...... implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4×4 matrix-vector multiplier with variable, 10-b...

  10. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  11. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    NARCIS (Netherlands)

    Lu, Jiwu; Kovalgin, Alexey Y.; Werf, van der Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  12. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  13. Indium bump array fabrication on small CMOS circuit for flip-chip bonding

    Institute of Scientific and Technical Information of China (English)

    Huang Yuyang; Zhang Yuxiang; Yin Zhizhen; Cui Guoxin; Liu H C; Bian Lifeng; Yang Hui; Zhang Yaohui

    2011-01-01

    We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator.A chip holder with a via hole is used to coat the photoresist for indium bump lift-off.The 1000 μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500μm,which ensures the integrity of the indium bump array.64 × 64 indium arrays with 20 μm-high,30 μm-diameter bumps are successfully formed on a 5 × 6.5 mm2 CMOS chip.

  14. A CMOS detection chip for amperometric sensors with chopper stabilized incremental ΔΣ ADC

    Science.gov (United States)

    Min, Chen; Yuntao, Liu; Jingbo, Xiao; Jie, Chen

    2016-06-01

    This paper presents a low noise complimentary metal-oxide-semiconductor (CMOS) detection chip for amperometric electrochemical sensors. In order to effectively remove the input offset of the cascaded integrators and the low frequency noise in the modulator, a novel offset cancellation chopping scheme was proposed in the Incremental ΔΣ analog to digital converter (IADC). A novel low power potentiostat was employed in this chip to provide the biasing voltage for the sensor while mirroring the sensor current out for detection. The chip communicates with FPGA through standard built in I2C interface and SPI bus. Fabricated in 0.18-μm CMOS process, this chip detects current signal with high accuracy and high linearity. A prototype microsystem was produced to verify the detection chip performance with current input as well as micro-sensors. Project supported by the State Key Development Program for Basic Research of China (No. 2015CB352100).

  15. Design of a CMOS-based multichannel integrated biosensor chip for bioelectronic interface with neurons.

    Science.gov (United States)

    Zhang, Xin; Wong, Wai Man; Zhang, Yulong; Zhang, Yandong; Gao, Fei; Nelson, Richard D; Larue, John C

    2009-01-01

    In this paper we present the design and prototyping of a 24-channel mixed signal full-customized CMOS integrated biosensor chip for in vitro extracellular recording of neural signals. Design and implementation of hierarchical modules including microelectrode electrophysiological sensors, analog signal buffers, high gain amplifier and control/interface units are presented in detail. The prototype chip was fabricated by MOSIS with AMI C5 0.5 microm, double poly, triple metal layer CMOS technology. The electroless gold plating process is used to replace the aluminum material obtained from the standard CMOS process with biocompatible metal gold in the planner microelectrode array sensors to prevent cell poisoning and undesirable electrochemical corrosion. The biosensor chip provides a satisfactory signal-to-noise ratio for neural signals with amplitudes and frequencies within the range of 600microV - 2mV and 100 Hz to 10KHz, respectively.

  16. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  17. A 1 GHz sample rate, 256-channel, 1-bit quantization, CMOS, digital correlator chip

    Science.gov (United States)

    Timoc, C.; Tran, T.; Wongso, J.

    1992-01-01

    This paper describes the development of a digital correlator chip with the following features: 1 Giga-sample/second; 256 channels; 1-bit quantization; 32-bit counters providing up to 4 seconds integration time at 1 GHz; and very low power dissipation per channel. The improvements in the performance-to-cost ratio of the digital correlator chip are achieved with a combination of systolic architecture, novel pipelined differential logic circuits, and standard 1.0 micron CMOS process.

  18. CMOS current-mode neural associative memory design with on-chip learning.

    Science.gov (United States)

    Wu, C Y; Lan, J F

    1996-01-01

    Based on the Grossberg mathematical model called the outstar, a modular neural net with on-chip learning and memory is designed and analyzed. The outstar is the minimal anatomy that can interpret the classical conditioning or associative memory. It can also be served as a general-purpose pattern learning device. To realize the outstar, CMOS (complimentary metal-oxide semiconductor) current-mode analog dividers are developed to implement the special memory called the ratio-type memory. Furthermore, a CMOS current-mode analog multiplier is used to implement the correlation. The implemented CMOS outstar can on-chip store the relative ratio values of the trained weights for a long time. It can also be modularized to construct general neural nets. HSPICE (a circuit simulator of Meta Software, Inc.) simulation results of the CMOS outstar circuits as associative memory and pattern learner have successfully verified their functions. The measured results of the fabricated CMOS outstar circuits have also successfully confirmed the ratio memory and on-chip learning capability of the circuits. Furthermore, it has been shown that the storage time of the ratio memory can be as long as five minutes without refreshment. Also the outstar can enhance the contrast of the stored pattern within a long period. This makes the outstar circuits quite feasible in many applications.

  19. Design and Fabrication of a Monolithic Optoelectronic Integrated Circuit Chip Based on CMOS Compatible Technology

    Institute of Scientific and Technical Information of China (English)

    GUO Wei-Feng; ZHAO Yong; WANG Wan-Jun; SHAO Hai-Feng; YANG Jian-Yi; JIANG Xiao-Qing

    2012-01-01

    A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology.The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function.Test results show that the extinction ratio of the MZM is close to 20dB and the small-signal gain of the CMOS driving circuit is about 26.9dB.A 50m V 10 MHz sine wave signal is amplified by the driving circuit,and then drives the MZM successfully.%A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology. The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function. Test results show that the extinction ratio of the MZM is close to 20 dB and the small-signal gain of the CMOS driving circuit is about 26.9dB. A 50mV 10MHz sine wave signal is amplified by the driving circuit, and then drives the MZM successfully.

  20. Experimental verification of on-chip CMOS fractional-order capacitor emulators

    KAUST Repository

    Tsirimokou, G.

    2016-06-13

    The experimental results from a fabricated integrated circuit of fractional-order capacitor emulators are reported. The chip contains emulators of capacitors of orders 0.3, 0.4, 0.5, 0.6 and 0.7 with nano-Farad pseudo-capacitances that can be adjusted through a bias current. Two off-chip capacitors are used to set the bandwidth of each emulator independently. The chip was designed in Austria microsystems (AMS) 0.35μ CMOS. © 2016 The Institution of Engineering and Technology.

  1. MuPix7 - A fast monolithic HV-CMOS pixel chip for Mu3e

    CERN Document Server

    Augustin, H; Dittmeier, S; Hammerich, J; Hartenstein, U; Huang, Q; Huth, L; Immig, D; Kozlinskiy, A; Aeschbacher, F Meier; Perić, I; Perrevoort, A -K; Schöning, A; Shrestha, S; Sorokin, I; Tyukin, A; Bruch, D vom; Wauters, F; Wiedner, D; Zimmermann, M

    2016-01-01

    The MuPix7 chip is a monolithic HV-CMOS pixel chip, thinned down to 50 \\mu m. It provides continuous self-triggered, non-shuttered readout at rates up to 30 Mhits/chip of 3x3 mm^2 active area and a pixel size of 103x80 \\mu m^2. The hit efficiency depends on the chosen working point. Settings with a power consumption of 300 mW/cm^2 allow for a hit efficiency >99.5%. A time resolution of 14.2 ns (Gaussian sigma) is achieved. Latest results from 2016 test beam campaigns are shown.

  2. Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

    CERN Document Server

    Kremastiotis, Iraklis; Campbell, Michael; Dannheim, Dominik; Fiergolski, Adrian; Hynds, Daniel; Kulis, Szymon; Peric, Ivan

    2017-01-01

    The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128 × 128 square pixels with 25 μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼ 20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼ 20 ns for a power consumption of 5 μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼ 20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using...

  3. A CMOS analog front-end chip for amperometric electrochemical sensors

    Science.gov (United States)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (Σ-Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  4. CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics

    Science.gov (United States)

    Sawadsaringkarn, Y.; Kimura, H.; Maezawa, Y.; Nakajima, A.; Kobayashi, T.; Sasagawa, K.; Noda, T.; Tokuda, T.; Ohta, J.

    2012-03-01

    A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

  5. CMOS Ultrasound Transceiver Chip for High-Resolution Ultrasonic Imaging Systems.

    Science.gov (United States)

    Insoo Kim; Hyunsoo Kim; Griggio, F; Tutwiler, R L; Jackson, T N; Trolier-McKinstry, S; Kyusun Choi

    2009-10-01

    The proposed CMOS ultrasound transceiver chip will enable the development of portable high resolution, high-frequency ultrasonic imaging systems. The transceiver chip is designed for close-coupled MEMS transducer arrays which operate with a 3.3-V power supply. In addition, a transmit digital beamforming system architecture is supported in this work. A prototype chip containing 16 receive and transmit channels with preamplifiers, time-gain compensation amplifiers, a multiplexed analog-to-digital converter with 3 kB of on-chip SRAM, and 50-MHz resolution time delayed excitation pulse generators has been fabricated. By utilizing a shared A/D converter architecture, the number of A/D converter and SRAM is cut down to one, unlike typical digital beamforming systems which need 16 A/D converters for 16 receive channels. The chip was fabricated in a 0.35-mum standard CMOS process. The chip size is 10 mm(2), and its average power consumption in receive mode is approximately 270 mW with a 3.3-V power supply. The transceiver chip specifications and designs are described, as well as measured results of each transceiver component and initial pulse-echo experimental results are presented.

  6. Photon imaging using post-processed CMOS chips

    NARCIS (Netherlands)

    Melai, Joost

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic s

  7. Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

    Science.gov (United States)

    Feller, A.; Lombardi, T.

    1978-01-01

    Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

  8. A 24 GHz CMOS oscillator transmitter with an inkjet printed on-chip antenna

    KAUST Repository

    Ghaffar, Farhan A.

    2016-08-15

    CMOS based RF circuits have demonstrated efficient performance over the decades. However, one bottle neck with this technology is its lossy nature for passive components such as inductors, antennas etc. Due to this drawback, passives are either implemented off chip or the designers work with the inefficient passives. This problem can be alleviated by using inkjet printing as a post process on CMOS chip. In this work, we demonstrate inkjet printing of a patterned polymer (SU8) layer on a 24 GHz oscillator chip to isolate the lossy Si substrate from the passives which are inkjet printed on top of the SU8 layer. As a proof of concept, a monopole antenna is printed on top of the SU8 layer integrating it with the oscillator through the exposed RF pads to realize an oscillator transmitter. The proposed hybrid fabrication technique can be extended to multiple dielectric and conductive printed layers to demonstrate complete RF systems on CMOS chips which are efficient, cost-effective and above all small in size. © 2016 IEEE.

  9. Design and Experimental Evaluation of a 3rd Generation Addressable CMOS Piezoresistive Stress Sensing Test Chip

    Energy Technology Data Exchange (ETDEWEB)

    Sweet, J.N.; Peterson, D.W.; Hsia, A.H.

    1999-04-13

    Piezoresistive stress sensing chips have been used extensively for measurement of assembly related die surface stresses. Although many experiments can be performed with resistive structures which are directly bonded, for extensive stress mapping it is necessary to have a large number of sensor cells which can be addressed using CMOS logic circuitry. Our previous test chip, the ATC04, has 100 cells, each approximately 0.012 in. on a side, on a chip with a side dimension of 0.45 in. When a cell resistor is addressed, it is connected to a four terminal measurement bus through CMOS transmission gates. In theory, the gate resistances do not affect the measurement. In practice, there may be subtle effects which appear when very high accuracy is required. At high temperatures, gate leakage can increase to a point at which the resistor measurement becomes inaccurate. For ATC04 this occurred at or above 50 C. Here, we report on the first measurements obtained with a new prototype test chip, the ATC06. This prototype was fabricated in a 0.5 micron feature size silicided CMOS process using the MOSIS prototyping facility. The cell size was approximately 0.004 in. on a side. In order to achieve piezoresistive behavior for the implanted resistors it was necessary to employ a non-standard silicide ''blocking'' process. The stress sensitivity of both implanted and polysilicon blocked resistors is discussed. Using a new design strategy for the CMOS logic, it was possible to achieve a design in which only 5 signals had to be routed to a cell for addressing vs. 9 for ATC04. With our new design, the resistor under test is more effectively electrically isolated from other resistors on the chip, thereby improving high temperature performance. We present data showing operation up to 140 C.

  10. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    Science.gov (United States)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×1012 1 MeV neq/cm2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  11. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    Energy Technology Data Exchange (ETDEWEB)

    Andreotti, M.; Baldini, W.; Calabrese, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Carniti, P.; Cassina, L. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Cotta Ramusino, A. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Fiorini, M., E-mail: fiorini@fe.infn.it [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Giachero, A.; Gotti, C. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Luppi, E. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Maino, M. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Malaguti, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Pessina, G. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Tomassetti, L. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy)

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×10{sup 12} 1 MeV n{sub eq}/cm{sup 2} and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  12. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-11-04

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)(-0.1) in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

  13. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications

    Directory of Open Access Journals (Sweden)

    Mohtashim Mansoor

    2016-11-01

    Full Text Available An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors, a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

  14. Radiation hardness studies of AMS HV-CMOS 350 nm prototype chip HVStripV1

    Science.gov (United States)

    Kanisauskas, K.; Affolder, A.; Arndt, K.; Bates, R.; Benoit, M.; Di Bello, F.; Blue, A.; Bortoletto, D.; Buckland, M.; Buttar, C.; Caragiulo, P.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hiti, B.; Hoeferkamp, M.; Hommels, L. B. A.; Huffman, B. T.; John, J.; Kenney, C.; Kramberger, J.; Liang, Z.; Mandic, I.; Maneuski, D.; Martinez-Mckinney, F.; MacMahon, S.; Meng, L.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Peric, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seidel, S.; Seiden, A.; Shipsey, I.; Song, W.; Staniztki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zhang, J.; Zhu, H.

    2017-02-01

    CMOS active pixel sensors are being investigated for their potential use in the ATLAS inner tracker upgrade at the HL-LHC. The new inner tracker will have to handle a significant increase in luminosity while maintaining a sufficient signal-to-noise ratio and pulse shaping times. This paper focuses on the prototype chip "HVStripV1" (manufactured in the AMS HV-CMOS 350nm process) characterization before and after irradiation up to fluence levels expected for the strip region in the HL-LHC environment. The results indicate an increase of depletion region after irradiation for the same bias voltage by a factor of ≈2.4 and ≈2.8 for two active pixels on the test chip. There was also a notable increase in noise levels from 85 e‑ to 386 e‑ and from 75 e‑ to 277 e‑ for the corresponding pixels.

  15. In vitro and in vivo on-chip biofluorescence imaging using a CMOS image sensor

    Science.gov (United States)

    Ng, David C.; Matsuo, Masamichi; Tokuda, Takashi; Kagawa, Keiichiro; Nunoshita, Masahiro; Ohta, Jun

    2006-02-01

    We have designed and fabricated a 176×144-pixels (QCIF) CMOS image sensor for on-chip bio-fluorescence imaging of the mouse brain. In our approach, a single CMOS image sensor chip without additional optics is used. This enables imaging at arbitrary depths into the brain; a clear advantage compared to existing optical microscopy methods. Packaging of the chip represents a challenge for in vivo imaging. We developed a novel packaging process whereby an excitation filter is applied onto the sensor. This eliminates the use of a filter cube found in conventional fluorescence microscopes. The fully packaged chip is about 350 μm thick. Using the device, we demonstrated in vitro on-chip fluorescence imaging of a 400 μm thick mouse brain slice detailing the hippocampus. The image obtained compares favorably to the image captured by conventional microscopes in terms of image resolution. In order to study imaging in vivo, we also developed a phantom media. In situ fluorophore measurement shows that detection through the turbid medium of up to 1 mm thickness is possible. We have successfully demonstrated imaging deep into the hippocampal region of the mouse brain where quantitative fluorometric measurements was made. This work is expected to lead to a promising new tool for imaging the brain in vivo.

  16. A power efficient 2Gb/s transceiver in 90nm CMOS for 10mm On-Chip interconnect

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, D.; Klumperink, E.A.M.; Tuijl, van A.J.M.; Nauta, B.

    2007-01-01

    Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper a low-swing transceiver for 10mm long 0.54μm wide on-chip interconnect is presented, which achieves a similar data rate as previou

  17. CMOS active pixel sensor type imaging system on a chip

    Science.gov (United States)

    Fossum, Eric R. (Inventor); Nixon, Robert (Inventor)

    2011-01-01

    A single chip camera which includes an .[.intergrated.]. .Iadd.integrated .Iaddend.image acquisition portion and control portion and which has double sampling/noise reduction capabilities thereon. Part of the .[.intergrated.]. .Iadd.integrated .Iaddend.structure reduces the noise that is picked up during imaging.

  18. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS

    Science.gov (United States)

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-01-01

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology. PMID:27444782

  19. Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

    Science.gov (United States)

    López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

  20. On-chip sub-terahertz surface plasmon polariton transmission lines in CMOS.

    Science.gov (United States)

    Liang, Yuan; Yu, Hao; Zhang, Hao Chi; Yang, Chang; Cui, Tie Jun

    2015-10-08

    A low-loss and low-crosstalk surface-wave transmission line (T-line) is demonstrated at sub-THz in CMOS. By introducing periodical sub-wavelength structures onto the metal transmission line, surface plasmon polaritons (SPP) are excited and propagate signals via a strongly localized surface wave. Two coupled SPP T-lines and two quasi-TEM T-lines are both fabricated on-chip, each with a separation distance of 2.4 μm using standard 65 nm CMOS technology. Measurement results show that the SPP T-lines achieve wideband reflection coefficient lower than -14 dB and crosstalk ratio better than -24 dB, which is 19 dB lower on average than the traditional T-lines from 220 GHz to 325 GHz. The demonstrated compact and wideband SPP T-lines have shown great potential for future realization of highly dense on-chip sub-THz communications in CMOS.

  1. Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

    Science.gov (United States)

    López-Huerta, Francisco; Herrera-May, Agustín L; Estrada-López, Johan J; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

  2. On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS.

    Science.gov (United States)

    Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

    2016-07-21

    An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (CMOS technology.

  3. A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

    Directory of Open Access Journals (Sweden)

    Chang-Hung Lee

    2014-05-01

    Full Text Available A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

  4. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2015-03-01

    Full Text Available This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  5. A CMOS pressure sensor tag chip for passive wireless applications.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-03-23

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  6. On-Chip Hotplate for Temperature Control of Cmos Saw Resonators

    CERN Document Server

    Nordin, Anis; Zaghloul, Mona

    2008-01-01

    Due to the sensitivity of the piezoelectric layer in surface acoustic wave (SAW) resonators to temperature, a method of achieving device stability as a function of temperature is required. This work presents the design, modeling and characterization of integrated dual-serpentine polysilicon resistors as a method for temperature control of CMOS SAW resonators. The design employs the oven control temperature stabilization scheme where the device's temperature is elevated to higher than Tmax to maintain constant device temperature. The efficiency of the polysilicon resistor as a heating element was verified through a 1-D partial differential equation model, 3-D CoventorWare finite element simulations and measurements using Compix thermal camera. To verify that the on-chip hotplate is effective as a temperature control method, both DC and RF measurements of the heater together with the resonator were conducted. Experimental results have indicated that the TCF of the CMOS SAW resonator of -97.2 ppm/deg C has been ...

  7. Design of a Tunable All-Digital UWB Pulse Generator CMOS Chip for Wireless Endoscope.

    Science.gov (United States)

    Chul Kim; Nooshabadi, S

    2010-04-01

    A novel tunable all-digital, ultrawideband pulse generator (PG) has been implemented in a standard 0.18-¿ m complementary metal-oxide semiconductor (CMOS) process for implantable medical applications. The chip shows that an ultra-low dynamic energy consumption of 27 pJ per pulse without static current flow at a 200-MHz pulse repetition frequency (PRF) with a 1.8-V power supply and low area of 90 × 50 ¿m(2). The PG generates tunable pulsewidth, amplitude, and transmit (Tx) power by using simple circuitry, through precise timing control of the H-bridge output stage. The all-digital architecture allows easy integration into a standard CMOS process, thus making it the most suitable candidate for in-vivo biotelemetry applications.

  8. CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

    Directory of Open Access Journals (Sweden)

    Milin Zhang

    2010-01-01

    Full Text Available Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end.

  9. A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

    Science.gov (United States)

    Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

    2007-06-01

    waveform frequency is about 200 Hz; and standard 5-V CMOS logic data communication rate is variable up to 250 kHz. This HV demonstration chip is fabricated in a 130-V 1.0-mum SOI CMOS fabrication technology, dissipates a maximum of 1.87 W, and is about 10.4 mm x 8.2 mm.

  10. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Science.gov (United States)

    Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

    2017-05-01

    Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  11. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  12. Development of a CMOS-compatible PCR chip: comparison of design and system strategies

    Science.gov (United States)

    Erill, Ivan; Campoy, Susana; Rus, José; Fonseca, Luis; Ivorra, Antoni; Navarro, Zenón; Plaza, José A.; Aguiló, Jordi; Barbé, Jordi

    2004-11-01

    In the last decade research in chips for DNA amplification through the polymerase chain reaction (PCR) has been relatively abundant, but has taken very diverse approaches, leaving little common ground for a straightforward comparison of results. Here we report the development of a line of PCR chips that is fully compatible with complementary-metal-oxide-semiconductor (CMOS) technology and its revealing use as a general platform to test and compare a wide range of experimental parameters involved in PCR-chip design and operation. Peltier-heated and polysilicon thin-film driven PCR chips have been produced and directly compared in terms of efficiency, speed and power consumption, showing that thin-film systems run faster and more efficiently than Peltier-based ones, but yield inferior PCR products. Serpentine-like chamber designs have also been compared with standard rectangular designs and with the here reported rhomboidal chamber shape, showing that serpentine-like chambers do not have detrimental effects in PCR efficiency when using non-flow-through schemes, and that chamber design has a strong impact on sample insertion/extraction yields. With an accurate temperature control (±0.2 °C) we have optimized reaction kinetics to yield sound PCR amplifications of 25 µl mixtures in 20 min and with 24.4 s cycle times, confirming that a titrated amount of bovine albumin serum (BSA, 2.5 µg µl-1) is essential to counteract polymerase adsorption at chip walls. The reported use of a CMOS-compatible technological process paves the way for an easy adaption to foundry requirements and for a scalable integration of electro-optic detection and control circuitry.

  13. Robust thermal control for CMOS-based lab-on-chip systems

    Science.gov (United States)

    Martinez-Quijada, Jose; Ma, Tianchi; Hall, Gordon H.; Reynolds, Matt; Sloan, David; Caverhill-Godkewitsch, Saul; Glerum, D. Moira; Sameoto, Dan; Elliott, Duncan G.; Backhouse, Christopher J.

    2015-07-01

    The need for precise temperature control at small scales has provided a formidable challenge to the lab-on-chip community. It requires, at once, good thermal conductivity for high speed operation, good thermal isolation for low power consumption and the ability to have small (mm-scale) thermally independent regions on the same substrate. Most importantly, and, in addition to these conflicting requirements, there is a need to accurately measure the temperature of the active region without the need for device-to-device calibrations. We have developed and tested a design that enables thermal control of lab-on-chip devices atop silicon substrates in a way that could be integrated with the standard methods of mass-manufacture used in the electronics industry (i.e. CMOS). This is a significant step towards a single-chip lab-on-chip solution, one in which the microfluidics, high voltage electronics, optoelectronics, instrumentation electronics, and the world-chip interface are all integrated on a single substrate with multiple, independent, thermally-controlled regions based on active heating and passive cooling.

  14. A novel compact model for on-chip stacked transformers in RF-CMOS technology

    Institute of Scientific and Technical Information of China (English)

    Liu Jun; Wen Jincai; Zhao Qian; Sun Lingling

    2013-01-01

    A novel compact model for on-chip stacked transformers is presented.The proposed model topology gives a clear distinction to the eddy current,resistive and capacitive losses of the primary and secondary coils in the substrate.A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided.The model is further verified by the excellent match between the measured and simulated S-parameters on the extracted parameters for a 1 ∶ 1 stacked transformer manufactured in a commercial RF-CMOS technology.

  15. CMOS biosensor system for on-chip cell culture with read-out circuitry and microfluidic packaging.

    Science.gov (United States)

    Welch, David; Christen, Jennifer Blain

    2012-01-01

    A 1.5 mm × 3 mm CMOS chip with sensors for monitoring on-chip cell cultures has been designed. The chip is designed in a 0.5 µm CMOS process which has 3 metal layers and 2 poly layers and is a 5 volt process. The chip contains ion sensitive field effect transistors (ISFETs), as well as ISFETs with read-out circuitry, for monitoring the pH of solutions placed on top of the chip. Interdigitated electrode structures (IDESs) are made using the top metal of the process to be used for sensing cellular attachment and proliferation via impendence. IDES read-out circuits and IDES test structures are included. The chip also contains test amplifiers, bandgap reference test structures, and connections for post-processing. We designed the chip to accommodate packaging into an environment where it will be directly exposed to a cell culture environment. Specifically we designed the chip to have the incorporated sensors near the center of the chip allowing for connections made around the edge of the chip to be sealed off using an epoxy or similar material to prevent shorting. Preliminary electrical characterization results for our amplifier indicate a gain of 48 dB, a bandwidth of 1.65 kHz, and a common mode rejection ratio (CMRR) of 72 dB. We also present a packaging technique using a flexible pcb substrate.

  16. A CMOS frontend chip for implantable neural recording with wide voltage supply range

    Science.gov (United States)

    Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

    2015-10-01

    A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

  17. One-chip electronic detection of DNA hybridization using precision impedance-based CMOS array sensor.

    Science.gov (United States)

    Lee, Kang-Ho; Lee, Jeong-Oen; Sohn, Mi-Jin; Lee, Byunghun; Choi, Suk-Hwan; Kim, Sang Kyu; Yoon, Jun-Bo; Cho, Gyu-Hyeong

    2010-12-15

    This paper describes a label-free and fully electronic detection method of DNA hybridization, which is achieved through the use of a 16×8 microarray sensor in conjunction with a new type of impedance spectroscopy constructed with standard complementary metal-oxide-semiconductor (CMOS) technology. The impedance-based method is based on changes in the reactive capacitance and the charge-transfer resistance after hybridization with complementary DNA targets. In previously published label-free techniques, the measured capacitance presented unstable capacitive properties due to the parallel resistance that is not infinite and can cause a leakage by discharging the charge on the capacitor. This paper presents an impedance extraction method that uses excitation by triangular wave voltage, which enables a reliable measurement of both C and R producing a highly sensitive sensor with a stable operation independent of external variables. The system was fabricated in an industrial 0.35-μm 4-metal 2-poly CMOS process, integrating working electrodes and readout electronics into one chip. The integrated readout, which uses a parasitic insensitive integrator, achieves an enlarged detection range and improved noise performance. The maximum average relative variations of C and R are 31.5% and 68.6%, respectively, after hybridization with a 1 μM target DNA. The proposed sensor allows quantitative evaluation of the molecule densities on the chip with distinguishable variation in the impedance. This fully electronic microsystem has great potential for use with bioanalytical tools and point-of-care diagnosis.

  18. A CMOS One-chip Wireless Camera with Digital Image Transmission Function for Capsule Endoscopes

    Science.gov (United States)

    Itoh, Shinya; Kawahito, Shoji; Terakawa, Susumu

    This paper presents the design and implementation of a one-chip camera device for capsule endoscopes. This experimental chip integrates functional circuits required for capsule endoscopes and digital image transmission function. The integrated functional blocks include an image array, a timing generator, a clock generator, a voltage regulator, a 10b cyclic A/D converter, and a BPSK modulator. It can be operated autonomously with 3 pins (VDD, GND, and DATAOUT). A prototype image sensor chip which has 320x240 effective pixels was fabricated using 0.25μm CMOS image sensor process and the autonomous imaging was demonstrated. The chip size is 4.84mmx4.34mm. With a 2.0 V power supply, the analog part consumes 950μW and the total power consumption at 2 frames per second (fps) is 2.6mW. Error-free image transmission over a distance of 48cm at 2.5Mbps corresponding to 2fps has been succeeded with inductive coupling.

  19. CMOS多通道芯片%CMOS Multi-Channel Chips

    Institute of Scientific and Technical Information of China (English)

    康凯; 高宗智

    2016-01-01

    In order to overcome a number of challenges in CMOS millimeter-wave integrated circuit design, the millimeter-wave device modeling, antenna design, circuit block, and multi-channel transceiver system are introduced in this paper. The equivalent-circuit models of millimeter-wave on-chip interconnected lines, multiple-coupled inductors, six-portM:N transformers, and the model of terahertz active device are studied and proposed, respectively. Moreover, a low noise amplifier with noise canceling and a power amplifier with a fully symmetrical distributed active transformer are introduced in this paper. Furthermore, the CMOS 60 GHz receiver with on-chip antenna and the multi-channel phase array transceiver are described, respectively.%针对互补金属氧化物半导体(CMOS)工艺在毫米波集成电路设计中存在的诸多挑战,分别从毫米波器件建模和天线设计,毫米波电路模块设计和多通道收发系统设计方面进行介绍,以克服相应挑战。该文研究和建立了毫米波频段片上互连线,耦合电感和六端口M:N变压器的等效模型和太赫兹有源器件模型,并对毫米波片上天线进行设计;介绍了基于噪声抵消的低噪声放大器电路和基于全对称平衡分布式有源变压器的功率放大器电路、毫米波移相器电路以及集成片上天线的CMOS 60 GHz接收机和多通道相控阵收发系统。

  20. Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing

    Directory of Open Access Journals (Sweden)

    Cally Gill

    2013-09-01

    Full Text Available The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

  1. Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

    Science.gov (United States)

    He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

    2013-09-18

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

  2. Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing

    Science.gov (United States)

    He, Diwei; Nguyen, Hoang C.; Hayes-Gill, Barrie R.; Zhu, Yiqun; Crowe, John A.; Gill, Cally; Clough, Geraldine F.; Morgan, Stephen P.

    2013-01-01

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

  3. SEMICONDUCTOR INTEGRATED CIRCUITS: A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

    Science.gov (United States)

    Leisheng, Gao; Yumei, Zhou; Bin, Wu; Jianhua, Jiang

    2010-08-01

    A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 μm CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 × 270 μm2. Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA.

  4. CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

    Energy Technology Data Exchange (ETDEWEB)

    Fu Jian; Mei Niansong; Huang Yumei; Hong Zhiliang, E-mail: yumeihuang@fudan.edu.cn [ASIC and System State Key Laboratory, Fudan University, Shanghai 201203 (China)

    2011-09-15

    A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-{mu}m CMOS process for W-CDMA application is presented. The transformer not only accomplishes output impedance matching, but also acts as a balun for converting differential signals to single-ended ones. Under a supply voltage of 3.3 V, the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%. The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB, respectively. The die size is 0.91 x 1.12 mm{sup 2}. (semiconductor integrated circuits)

  5. CMOS high linearity PA driver with an on-chip transformer for W-CDMA application

    Institute of Scientific and Technical Information of China (English)

    Fu Jian; Mei Niansong; Huang Yumei; Hong Zhiliang

    2011-01-01

    A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μm CMOS process for W-CDMA application is presented.The transformer not only accomplishes output impedance matching,but also acts as a balun for converting differential signals to single-ended ones.Under a supply voltage of 3.3 V,the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%.The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB,respectively.The die size is 0.91 × 1.12 mm2.

  6. Flexible multi-electrode array with integrated bendable CMOS-chip for implantable systems.

    Science.gov (United States)

    Winkin, N; Mokwa, W

    2012-01-01

    Micro-electrodes and micro-electrode arrays (MEAs) for stimulating neurons or recording action potentials are widely used in medical applications or biological research. For medical implants in many applications like brain implants or retinal implants there is a need for flexible MEAs with a large area and a large number of stimulation electrodes. In this work a flexible MEA with an embedded flexible silicon dummy CMOS-chip facing these challenges has been designed, manufactured and characterized. This approach offers the possibility by connecting and addressing several of these MEAs via a bus system, to increase the number and the density of electrodes significantly. This paper describes the design and fabrication process. Results on the mechanical and electrical behavior will be given and possible improvements for medical applications by this novel approach will be discussed.

  7. An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

    Science.gov (United States)

    Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

    2015-03-06

    An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

  8. A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface

    Science.gov (United States)

    Yoshida, Hiroshi; Toyoda, Takehiko; Tsurumi, Hiroshi; Itoh, Nobuyuki

    In this paper, a single-chip dual-mode 8-band 130nm CMOS transceiver including A/D/A converters and digital filters with 312MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.

  9. Programmable retinal dynamics in a CMOS mixed-signal array processor chip

    Science.gov (United States)

    Carmona, Ricardo A.; Jimenez-Garrido, Francisco J.; Dominguez-Castro, Rafael; Espejo, Servando; Rodriguez-Vazquez, Angel

    2003-04-01

    The retina is responsible of the treatment of visual information at early stages. Visual stimuli generate patterns of activity that are transmitted through its layered structure up to the ganglion cells that interface it to the optical nerve. In this trip of micrometers, information is sustained by continuous signals that interact in excitatory and inhibitory ways. This low-level processing compresses the relevant information of the images to a manageable size. The behavior of the more external layers of the biological retina has been successfully modelled within the Cellular Neural Network framework. Interactions between cells are realized on a local basic. Each cell interacts with its nearest neighbors and every cell in the same layer follows the same interconnection pattern. Intra- and inter-layer interactions are continuous in magnitude and time. The evolution of the network can be described by a set of coupled nonlinear differential equations. A mixed-signal VLSI implementation of focal-plane low-level image processing based upon this biological model constitutes a feasible and cost effective alternative to conventional digital processing in real-time applications. A CMOS Programmable Array Processor prototype chip has been designed and fabricated in a standard technology. It has been successfully tested, validating the proposed design techniques. The integrated system consists of a network of 2 coupled layers, containing 32×32 elementary processors, running at different time constants. Involved image processing algorithms can be programmed on this chip by tuning the appropriate interconnection weights, internally coded as analog but programmed via a digital interface. Propagative, active wave phenomena and retina-lake effects can be observed in this chip. Low-level image processing tasks for early vision applications can be developed based on these high-order dynamics.

  10. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

    Directory of Open Access Journals (Sweden)

    Chun-Chi Chen

    2016-01-01

    Full Text Available This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs. Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI system.

  11. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    Science.gov (United States)

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-30

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

  12. A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

    Institute of Scientific and Technical Information of China (English)

    Zhitang Song; YiPeng Zhan; Daolin Cai; Bo Liu; Yifeng Chen; Jiadong Ren

    2015-01-01

    In this letter, a phase change random access memory (PCRAM) chip based on Ti0.4Sb2Te3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor (CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 mA, 100 and 10 ns, respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications.

  13. Design and experimental verification of CMOS magnetic-based microbead detection using an asynchronous intra-chip inductive-coupling transceiver

    Science.gov (United States)

    Niitsu, Kiichi; Kobayashi, Atsuki; Yoshida, Kohei; Nakazato, Kazuo

    2017-01-01

    In this study, an asynchronous intra-chip inductive-coupling transceiver was used to design and experimentally verify a CMOS magnetic-based microbeads detection system. Magnetic microbeads were employed for the surrounding living cells. These microbeads increased the magnetic flux and enabled the operation of an intra-chip inductive-coupling transceiver with a low transmitter supply voltage. Thus, by sensing the change in transmitter supply voltage, the system detected the living cells surrounded by microbeads. To verify the effectiveness of the proposed approach, a test chip was fabricated using 0.25 µm CMOS technology. The measured results successfully demonstrated the detection of microbeads.

  14. System on chip thermal vacuum sensor based on standard CMOS process

    Institute of Scientific and Technical Information of China (English)

    Li Jinfeng; Tang Zhen'an; Wang Jiaqi

    2009-01-01

    An on-chip microelectromechanical system was fabricated in a 0.5μm standard CMOS process for gas pressure detection. The sensor was based on a micro-hotplate (MHP) and had been integrated with a rail to rail operational amplifier and an 8-bit successive approximation register (SAR) A/D converter. A tungsten resistor was manufactured on the MHP as the sensing element, and the sacrificial layer of the sensor was made from polysilicon and etched by surface-micromachining technology. The operational amplifier was configured to make the sensor operate in constant current mode. A digital bit stream was provided as the system output. The measurement results demonstrate that the gas pressure sensitive range of the vacuum sensor extends from 1 to 105 Pa. In the gas pressure range from 1 to 100 Pa, the sensitivity of the sensor is 0.23 mV/Pa, the linearity is 4.95%, and the hysteresis is 8.69%. The operational amplifier can drive 200 Ω resistors distortionlessly, and the SAR A/D converter achieves a resolution of 7.4 bit with 100 kHz sample rate. The performance of the operational amplifier and the SAR A/D converter meets the requirements of the sensor system.

  15. CMOS-compatible silicon nitride spectrometers for lab-on-a-chip spectral sensing

    Science.gov (United States)

    Ryckeboer, Eva; Nie, Xiaomin; Subramanian, Ananth Z.; Martens, Daan; Bienstman, Peter; Clemmen, Stephane; Severi, Simone; Jansen, Roelof; Roelkens, Gunther; Baets, Roel

    2016-05-01

    We report on miniaturized optical spectrometers integrated on a photonic integrated circuit (PIC) platform based on silicon nitride waveguides and fabricated in a CMOS-compatible approach. As compared to a silicon- on-insulator PIC-platform, the usage of silicon nitride allows for operation in the visible and near infrared. Furthermore, the moderately high refractive index contrast in silicon-nitride photonic wire waveguides provides a valuable compromise between compactness, optical loss and sensitivity to phase error. Three generic types of on-chip spectrometers are discussed: the arrayed waveguide grating (AWG) spectrometer, the echelle grating or planar concave grating (PCG) spectrometer and the stationary Fourier transform spectrometer (FTS) spectrometer. Both the design as well as experimental results are presented and discussed. For the FTS spectrometer a specific design is described in detail leading to an ultra-small (0.1 mm2) footprint device with a resolution of 1 nm and a spectral range of 100nm. Examples are given of the usage of these spectrometers in refractive index biosensing, absorption spectroscopy and Raman spectroscopy.

  16. A New Method for Optimizing Layout Parameter of an Integrated On-Chip Inductor in CMOS RF IC's

    Institute of Scientific and Technical Information of China (English)

    李力南; 钱鹤

    2000-01-01

    Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on-chip integrated inductor, a concise method to increase the Q factor has been ob tained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5 % compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC's.

  17. An integrated CMOS quantitative-polymerase-chain-reaction lab-on-chip for point-of-care diagnostics.

    Science.gov (United States)

    Norian, Haig; Field, Ryan M; Kymissis, Ioannis; Shepard, Kenneth L

    2014-10-21

    Considerable effort has recently been directed toward the miniaturization of quantitative-polymerase-chain-reaction (qPCR) instrumentation in an effort to reduce both cost and form factor for point-of-care applications. Considerable gains have been made in shrinking the required volumes of PCR reagents, but resultant prototypes retain their bench-top form factor either due to heavy heating plates or cumbersome optical sensing instrumentation. In this paper, we describe the use of complementary-metal-oxide semiconductor (CMOS) integrated circuit (IC) technology to produce a fully integrated qPCR lab-on-chip. Exploiting a 0.35 μm high-voltage CMOS process, the IC contains all of the key components for performing qPCR. Integrated resistive heaters and temperature sensors regulate the surface temperature of the chip to an accuracy of 0.45 °C. Electrowetting-on-dielectric microfluidics are actively driven from the chip surface, allowing for droplet generation and transport down to volumes less than 1.2 nanoliter. Integrated single-photon avalanche diodes (SPADs) are used for fluorescent monitoring of the reaction, allowing for the quantification of target DNA with more than four-orders-of-magnitude of dynamic range and sensitivities down to a single copy per droplet. Using this device, reliable and sensitive real-time proof-of-concept detection of Staphylococcus aureus (S. aureus) is demonstrated.

  18. Development of a small-scale protope of the GOSSIPO-2 chip in 0.13 um CMOS technology

    CERN Document Server

    Kluit, R; Gromov, V

    2007-01-01

    The GOSSIP (Gas On Slimmed Silicon Pixel) detector is a proposed alternative for silicon based pixel detectors. The Gossip Prototype (GOSSIPO) chip is being developed to serve as a prototype read-out chip for such a gas-filled detector. Thanks to the very low capacitance at the preamplifier input, the front-end of the chip demonstrates low-noise performance in combination with a fast peaking time and low analog power dissipation. Measurement of the drift time of every primary electron in the gas volume enables 3D reconstruction of the particle tracks. For this purpose a Time-to- Digital converter must be placed in each pixel. A small-scale prototype of the GOSSIP chip has been developed in the 0.13 μm CMOS technology. The prototype includes a 16 by 16 pixel array where each pixel is equipped with a front-end circuit, threshold DAC, and a 4-bit TDC. The chip is available for testing in May 2007 and after initial tests it will be postprocessed to build a prototype detector. This paper describes the detector de...

  19. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Directory of Open Access Journals (Sweden)

    M. Elsobky

    2017-09-01

    Full Text Available Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI substrate to form a Hybrid System-in-Foil (HySiF, which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC. The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC, a differential difference amplifier (DDA, and a 10-bit successive approximation register (SAR ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  20. Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

    Science.gov (United States)

    Elsobky, Mourad; Mahsereci, Yigit; Keck, Jürgen; Richter, Harald; Burghartz, Joachim N.

    2017-09-01

    Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI) substrate to form a Hybrid System-in-Foil (HySiF), which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing) of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA) in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC). The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC), a differential difference amplifier (DDA), and a 10-bit successive approximation register (SAR) ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

  1. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

    Science.gov (United States)

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

    2014-02-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

  2. Heterogeneous integration of GaAs pHEMT and Si CMOS on the same chip

    Science.gov (United States)

    Li-Shu, Wu; Yan, Zhao; Hong-Chang, Shen; You-Tao, Zhang; Tang-Sheng, Chen

    2016-06-01

    In this work, we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of GaAs pseudomorphic high electron mobility transistors (pHEMTs) and Si complementary metal-oxide semiconductor (CMOS) on the same Silicon substrate. GaAs pHEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique, and the best alignment accuracy of 5 μm is obtained. As a circuit example, a wide band GaAs digital controlled switch is fabricated, which features the technologies of a digital control circuit in Si CMOS and a switch circuit in GaAs pHEMT, 15% smaller than the area of normal GaAs and Si CMOS circuits.

  3. Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability

    OpenAIRE

    2001-01-01

    Silicon-hydrogen bonds passivate the interface defects at the silicon-silicon dioxide interface of CMOS transistors. The activation of these bonds and subsequent creation of interface traps is an important source of transistor degradation at current operating conditions. There is now evidence for a distribution in the activation energies of these bonds instead of a single threshold value. We show that conventional CMOS scaling rules are substantially affected by this energy dis...

  4. Integrated on-chip 0.35 μm BiCMOS current-mode DC-DC buck converter

    Science.gov (United States)

    Lee, Chan-Soo; Kim, Nam-Soo; Gendensuren, Munkhsuld; Choi, Jae-Ho; Choi, Joong-Ho

    2012-12-01

    A current-mode DC-DC buck converter with a fully integrated power module is presented in this article. The converter is implemented using BiCMOS technology in amplifier and power MOSFET in a current sensor. The current sensor is realised by the power lateral double-diffused MOSFET with the aspect ratio much larger than that of a matched p-MOSFET. In addition, BiCMOS technology is applied in the error amplifier for an accurate current sensing and a fast transient response. The DC-DC converter is fabricated with 0.35 µm BiCMOS process. Experimental results show that the fully integrated converter operates at 1.3 MHz switching frequency with a supply voltage of 5 V. The output DC voltage is obtained as expected and the output ripple is controlled to be within 2% with a 30 µH off-chip inductor and 100 µF off-chip capacitor.

  5. A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS

    Science.gov (United States)

    Xiangyu, Meng; Baoyong, Chi; Haikun, Jia; Lixue, Kuang; Wen, Jia; Zhihua, Wang

    2013-10-01

    A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS with a low-resistivity (10 Ω·bm) silicon substrate is presented. The wideband is achieved by reducing the Q factor and exciting the high-order radiation modes with size optimization. The antenna uses an on-chip top layer metal as the patch and a probe station as the ground plane. The on-chip ground plane is connected to the probe station using the inner connection structure of the probe station for better performance. The simulated S11 is less than -10 dB over 46-95 GHz, which is well matched with the measured results over the available 40-67 GHz frequency range from our measurement equipment. A maximum gain of -5.55 dBi with 4% radiation efficiency at a 60 GHz point is also achieved based on Ansoft HFSS simulation. Compared with the current state-of-the-art devices, the presented antenna achieves a wider bandwidth and could be used in wideband millimeter-wave communication and image applications.

  6. Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Testsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany); Havranek, Miroslav [University of Bonn, Bonn (Germany); Institute of Physics of the Academy of Sciences, Prague (Czech Republic)

    2015-07-01

    The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges coming from the higher hit rate will have to be solved by designing faster and more complex circuits, while at the same time keeping in mind very high radiation hardness requirements. Therefore matching the specification set by the high luminosity upgrade requires a large R and D effort. Our group is participating in such a joint development * namely the RD53 collaboration * which goal is to design a new pixel chip using an advanced 65 nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology will be shown together with a comparison with older technologies (130 nm, 250 nm). Most of the talk is allocated to presenting some of the circuits designed by our group, along with their performance measurement results.

  7. A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer*

    Institute of Scientific and Technical Information of China (English)

    Chen Qihui; Qin Yajie; Lu Bo; Hong Zhiliang

    2011-01-01

    A 12-bit 30 MSPS pipeline analog-to-digital converter (ADC) implemented in 0.13-μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.

  8. A CMOS wideband front-end chip using direct RF sampling mixer with embedded discrete-time filtering

    Science.gov (United States)

    Jiangtao, Xu; Saavedra, Carlos E.; Guican, Chen

    2011-08-01

    A CMOS wideband front-end IC is demonstrated in this paper. It consists of a low noise transconductance amplifier (LNTA) and a direct RF sampling mixer (DSM) with embedded programmable discrete-time filtering. The LNTA has the features of 0.5-6 GHz wideband, wideband input matching and low noise. The embedded filter following the DSM operates in discrete-time charge domain, filtering the aliasing signals and interferences while controlling the IF bandwidth according to the clock frequency. The measured NF of the front-end was below 7 dB throughout the whole band from 0.5 to 6 GHz. It shows a conversion gain of 12.6 dB and IP1dB of -7.5 dBm at 2.4 GHz. It occupies a chip area of 0.23 mm2 and consumes 14 mA DC current.

  9. Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany)

    2016-07-01

    The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges arising from the increased hit rate will have to be solved by designing faster and more complex readout electronics that will also have to withstand unprecedented radiation doses. Developing such integrated circuit requires a significant R and D effort and resources, therefore a joint development project between several institutes (including ours) was started. This collaboration, named RD53, aims to develop a pixel readout chip suitable for ATLAS' and CMS' upgrades using a 65nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology are discussed. Most of the talk is allocated to presenting some of the circuits designed by our group (focusing on developments connected to RD53 collaboration), along with their performance measurement results.

  10. A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

    Science.gov (United States)

    Sheng, Duo; Hong, Min-Rong

    2016-10-14

    This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

  11. Easy simulation and design of on-chip inductors in standard CMOS processes

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Jørgensen, Allan

    1998-01-01

    This paper presents an approach to CMOS inductor modelling, that allow easy simulation in SPICE-like simulators. A number of test results are presented concerning optimal center hole, inductor area, wire spacing and self-inductance. Finally a comprehensive design guide is provided on how to design...

  12. A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18μm standard CMOS process

    Institute of Scientific and Technical Information of China (English)

    Feng Peng; Zhang Qi; Wu Nanjian

    2011-01-01

    This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor.The chip tag integrates a temperature sensor,an RF/analog front-end circuit,an NVM memory and a digital baseband in a standard CMOS process.The sensor with a low power sigma-delta (Σ△) ADC is designed to operate in low and high resolution modes.It can not only achieve the target accuracy but also reduce the power consumption and the sensing time.A CMOS-only RF rectifier and a single-poly non-volatile memory (NVM) are designed to realize a low cost tag chip.The 192-bit-NVM tag chip with an area of 1 mm2 is implemented in a 0.18-μm standard CMOS process.The sensitivity of the tag is -10.7 dBm/-8.4 dBm when the sensor is disabled/enabled.It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP.The inaccuracy of the sensor is -0.6 ℃/0.5 ℃ (-1.0 ℃/1.2 ℃) in the operating range from 5 to 15 ℃ in high resolution mode (-30 to 50 ℃ in low resolution mode).The resolution of the sensor achieves 0.02 ℃ (0.18 ℃) in high (low) resolution mode.

  13. A 130 nm CMOS mixed mode front end readout chip for silicon strip tracking at the future linear collider

    Energy Technology Data Exchange (ETDEWEB)

    Pham, T.H., E-mail: pham@lpnhe.in2p3.f [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France); Charpy, A.; Ciobanu, C. [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France); Comerma, A. [Universitat de Barcelona, Dept E.C.M/Dept. Electronica/ICC-Diagonal 647, planta 6, 08028 Barcelona (Spain); David, J.; Dhellot, M. [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France); Dieguez, A.; Gascon, D. [Universitat de Barcelona, Dept E.C.M/Dept. Electronica/ICC-Diagonal 647, planta 6, 08028 Barcelona (Spain); Genat, J.F.; Savoy Navarro, A.; Sefri, R. [LPNHE-Universite Pierre et Marie Curie/IN2P3-CNRS-4, Place Jussieu, 75252 Paris Cedex 05 (France)

    2010-11-01

    A 130 nm mixed (analog and digital) CMOS chip intended to read silicon strip detectors for future linear collider experiments was developed. Currently under testing, this chip has been optimized for a silicon micro-strip tracking device. It includes 88 channels of a full analog signal processing chain with the corresponding digital control and readout. Every analog channel includes (i) a low noise charge amplifier and integration with long pulse shaping, (ii) an eight by eight positions analog sampler for both storing successive events and reconstructing the full pulse shape, and (iii) a sparsifier performing analog sum of three adjacent inputs to decide whether there is signal or not. The whole system is controlled by the digital part, which allows configuring all the reference currents and voltages, drives the control signals to the analog memories, records the timing and channel information and subsequently performs the conversion to digital values of samples. The total surface of the circuit is 10x5 mm{sup 2}, with each analog channel occupying an area of 105x3500 {mu}m{sup 2}, and the remaining space of about 9000x700 {mu}m{sup 2} being filled by the analog channels on the silicon.

  14. Design of the low area monotonic trim DAC in 40 nm CMOS technology for pixel readout chips

    Science.gov (United States)

    Drozd, A.; Szczygiel, R.; Maj, P.; Satlawa, T.; Grybos, P.

    2014-12-01

    The recent research in hybrid pixel detectors working in single photon counting mode focuses on nanometer or 3D technologies which allow making pixels smaller and implementing more complex solutions in each of the pixels. Usually single pixel in readout electronics for X-ray detection comprises of charge amplifier, shaper and discriminator that allow classification of events occurring at the detector as true or false hits by comparing amplitude of the signal obtained with threshold voltage, which minimizes the influence of noise effects. However, making the pixel size smaller often causes problems with pixel to pixel uniformity and additional effects like charge sharing become more visible. To improve channel-to-channel uniformity or implement an algorithm for charge sharing effect minimization, small area trimming DACs working in each pixel independently are necessary. However, meeting the requirement of small area often results in poor linearity and even non-monotonicity. In this paper we present a novel low-area thermometer coded 6-bit DAC implemented in 40 nm CMOS technology. Monte Carlo simulations were performed on the described design proving that under all conditions designed DAC is inherently monotonic. Presented DAC was implemented in the prototype readout chip with 432 pixels working in single photon counting mode, with two trimming DACs in each pixel. Each DAC occupies the area of 8 μm × 18.5 μm. Measurements and chips' tests were performed to obtain reliable statistical results.

  15. A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects

    Energy Technology Data Exchange (ETDEWEB)

    Maj, Piotr; Grybos, P.; Szczgiel, R.; Kmon, P.; Drozd, A.; Deptuch, G.

    2013-11-07

    We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 m. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.

  16. TOT01, a time-over-threshold based readout chip in 180nm CMOS technology for silicon strip detectors

    Science.gov (United States)

    Kasinski, K.; Szczygiel, R.; Gryboś, P.

    2011-01-01

    This work is focused on the development of the TOT01 prototype front-end ASIC for the readout of long silicon strip detectors in the STS (Silicon Tracking System) of the CBM experiment at FAIR - GSI. The deposited charge measurement is based on the Time-over-Threshold method which allows integration of a low-power ADC into each channel. The TOT01 chip comprises 30 identical channels and 1 test channel which is supplied with additional test pads. The major blocks of each channel are the CSA (charge sensitive amplifier) with two switchable constant-current discharge circuits and additional test features. The architecture of the CSA core is based on the folded cascode. The input p-channel MOSFET device, biased at a drain current 500 μA, was optimized for 30 pF detector capacitance while keeping in mind the area constraints — W/L = 1800 μm / 0.180 μm. The main advantage of this solution is high gain (GBW = 1.2 GHz) and low power consumption at the same time. The amplifier is followed by the discriminator circuit. The discriminator allows for a global (multi-channel) differential threshold setting and independent compensation for the CSA output DC-level deviations in each channel by means of a 6-bit digital to analog converter (DAC). The output pulse of this processing chain is fed through a 31:1 multiplexer structure to the output of the chip for further processing. The TOT01 chip has been fabricated in the UMC 0.18 μm CMOS process (Europractice mini@sic). It has 78 pads, measures approximately 1.5x3.2 mm2 and dissipates 33 mW. The channels have 50 μm pitch and each consumes 1.05 mW of power. The chip has been successfully tested. Charge sensitivity parameters, noise performance and first X-ray acquisitions are presented.

  17. Analysis list: SP2 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available SP2 Blood,Liver,Pluripotent stem cell + hg19 http://dbarchive.biosciencedbc.jp/kyus...hu-u/hg19/target/SP2.1.tsv http://dbarchive.biosciencedbc.jp/kyushu-u/hg19/target/SP2.5.tsv http://dbarchive.bioscience...dbc.jp/kyushu-u/hg19/target/SP2.10.tsv http://dbarchive.biosciencedbc.jp/kyushu-u/hg19/colo/SP2.B...lood.tsv,http://dbarchive.biosciencedbc.jp/kyushu-u/hg19/colo/SP2.Liver.tsv,http://dbarchive.bioscience...dbc.jp/kyushu-u/hg19/colo/SP2.Pluripotent_stem_cell.tsv http://dbarchive.biosciencedbc

  18. Low temperature co-fired ceramic packaging of CMOS capacitive sensor chip towards cell viability monitoring

    Directory of Open Access Journals (Sweden)

    Niina Halonen

    2016-11-01

    Full Text Available Cell viability monitoring is an important part of biosafety evaluation for the detection of toxic effects on cells caused by nanomaterials, preferably by label-free, noninvasive, fast, and cost effective methods. These requirements can be met by monitoring cell viability with a capacitance-sensing integrated circuit (IC microchip. The capacitance provides a measurement of the surface attachment of adherent cells as an indication of their health status. However, the moist, warm, and corrosive biological environment requires reliable packaging of the sensor chip. In this work, a second generation of low temperature co-fired ceramic (LTCC technology was combined with flip-chip bonding to provide a durable package compatible with cell culture. The LTCC-packaged sensor chip was integrated with a printed circuit board, data acquisition device, and measurement-controlling software. The packaged sensor chip functioned well in the presence of cell medium and cells, with output voltages depending on the medium above the capacitors. Moreover, the manufacturing of microfluidic channels in the LTCC package was demonstrated.

  19. A CMOS vision chip for a contrast-enhanced image using a logarithmic APS and a switch-selective resistive network

    Science.gov (United States)

    Kong, Jae-Sung; Kim, Sang-Heon; Sung, Dong-Kyu; Seo, Sang-Ho; Shin, Jang-Kyoo

    2007-02-01

    In this paper, a vision chip for a contrast-enhanced image based on a structure of a biological retina is introduced. The key advantage of this structure is high speed of signal processing. In a conventional active pixel sensor (APS), the charge accumulation time limits its operation speed. In order to enhance the speed, a logarithmic APS was applied to the vision chip. By applying a MOS-type photodetector to the logarithmic APS, we could achieve sufficient output swing for the vision chip in natural illumination condition. In addition, a CMOS buffer circuit, a common drain amplifier, is commonly used for both raw and smoothed images by using additional switches. By using the switch-selective resistive network, the total number of MOSFETs for a unit pixel and the fixed-pattern noise were reduced. A vision chip with a 160×120 pixel array was fabricated using a 0.35 μm double-poly four-metal CMOS technology, and its operation was experimentally investigated.

  20. A 94 GHz CMOS based oscillator transmitter with an on-chip meandered dipole antenna

    KAUST Repository

    Cheema, Hammad M.

    2015-10-26

    A miniaturized 94 GHz oscillator transmitter in 65nm CMOS is presented. An extremely small silicon foot-print of 0.25mm2 is achieved through meandering of the top-metal dipole antenna, conjugate matching between the oscillator and the antenna without impedance matching elements and efficient placement of the oscillator circuit within the antenna. The antenna demonstrates bandwidth of 90 to 99 GHz (10%) and a gain of -6dBi. The use of parasitic aware antenna-circuit code-sign strategy results in an accurate measured oscillation frequency of 94.1 GHz. The oscillator exhibits a measured output power of -25 dBm, phase noise of -88 dBc/Hz at 1 MHz offset and consumes 8.4mW from a 1V supply. © 2015 IEEE.

  1. New Programmable CMOS Fuzzifier and C2V Circuits Applicable in FLC Chip for Signal Processing of MEMS Glucose Sensors

    Directory of Open Access Journals (Sweden)

    Ghader Yosefi

    2015-08-01

    Full Text Available This paper presents the design and simulation of improved circuits of Fuzzifier and capacitance to voltage (C2V converter. The Fuzzifier circuit is designed based on analog advantages such as low die area, high accuracy, and simplicity which are added to the fuzzy system advantages. For implementing this idea, a programmable Membership Function Generator (MFG including differential pair circuit as a Fuzzifier is proposed. The MFG generates arbitrary forms of Gaussian, Trapezoidal, and Triangular shapes. The shape types are achieved using control switches and different reference voltages. This structure is also general purpose in tuning the slope of Membership Functions (MFs using scaled transistors with different W/L ratios. With a specific purpose in mind, we used it here to generate fuzzy language terms from sensed classic data of a blood glucose microsensor. Thus we proposed a C2V circuit to convert capacitance variations (from MEMS glucose microsensor to voltage values as classic data. The proposed mentioned circuits can be applicable in design of Fuzzy Logic Controller (FLC chips to detect blood glucose, process its data in Fuzzy environment, and control insulin injection of diabetic patients by MEMS micropumps. The simulation results are achieved by MATLAB and Hspice software in 0.35 μm CMOS standard technology.

  2. A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18 μm standard CMOS process

    Science.gov (United States)

    Peng, Feng; Qi, Zhang; Nanjian, Wu

    2011-11-01

    This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor, an RF/analog front-end circuit, an NVM memory and a digital baseband in a standard CMOS process. The sensor with a low power sigma—delta (ΣΔ) ADC is designed to operate in low and high resolution modes. It can not only achieve the target accuracy but also reduce the power consumption and the sensing time. A CMOS-only RF rectifier and a single-poly non-volatile memory (NVM) are designed to realize a low cost tag chip. The 192-bit-NVM tag chip with an area of 1 mm2 is implemented in a 0.18-μm standard CMOS process. The sensitivity of the tag is -10.7 dBm/-8.4 dBm when the sensor is disabled/enabled. It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP. The inaccuracy of the sensor is -0.6 °C/0.5 °C (-1.0 °C/1.2 °C) in the operating range from 5 to 15 °C in high resolution mode (-30 to 50 °C in low resolution mode). The resolution of the sensor achieves 0.02 °C (0.18 °C) in high (low) resolution mode.

  3. High-speed polymerase chain reaction in CMOS-compatible chips

    OpenAIRE

    Erill Sagalés, Ivan

    2003-01-01

    Consultable des del TDX Títol obtingut de la portada digitalitzada En la última década del siglo XX, el campo de los microsistemas para análisis total (µ-TAS) y, más concretamente, el de los DNA-chips ha adquirido una importancia preponderante en el ámbito de los microsistemas. En gran parte, el creciente interés por estos dispositivos se debe a las substanciales mejoras que prometen: análisis más rápidos, baratos y automatizados, pero también es debido a la posibilidad de implementar t...

  4. Characterization of on-chip balun with patterned floating shield in 65 nm CMOS

    Institute of Scientific and Technical Information of China (English)

    Wei Jiaju; Wang Zhigong

    2011-01-01

    A simple method ofbalun synthesis is proposed to estimate the balun structure in the operating frequency band.Then,a careful optimization is implemented to evaluate the estimated structure by a series of EM simulations.In order to investigate the impact of the patterned floating shield (PFS),the optimized baluns with and without PFS are fabricated in a 65 nm 1 P6M CMOS process.The measurement results demonstrate that the PFS obviously improves the insertion loss (IL) in the frequency range and a linear improving trend appears smoothly.It is also found that the PFS gradually improves the phase balance as the frequency increases,while it has a very slight influence on the magnitude balance.To characterize the device's intrinsic power transfer ability,we propose a method to obtain the baluns' maximum available gain directly from the measured 3-port S-parameters and find that IL-comparison may not be very objective when evaluating the shielding effect.We also use the resistive coupling efficiency to characterize the shielding effect,and an imbalanced shielding efficiency is found though the PFS is perfectly symmetric in the measurement.It can be demonstrated that this phenomenon comes from the intrinsic imbalance of our balun layout.

  5. Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Li, Bing; Zhang, Lihua; Wu, Xiang; Fu, Zhihui; Zuo, Lei

    2015-05-18

    This paper presents an ultra-low embedded power temperature sensor for passive RFID tags. The temperature sensor converts the temperature variation to a PTAT current, which is then transformed into a temperature-controlled frequency. A phase locked loop (PLL)-based sensor interface is employed to directly convert this temperature-controlled frequency into a corresponding digital output without an external reference clock. The fabricated sensor occupies an area of 0.021 mm2 using the TSMC 0.18 1P6M mixed-signal CMOS process. Measurement results of the embedded sensor within the tag system shows a 92 nW power dissipation under 1.0 V supply voltage at room temperature, with a sensing resolution of 0.15 °C/LSB and a sensing accuracy of -0.7/0.6 °C from -30 °C to 70 °C after 1-point calibration at 30 °C.

  6. Hybrid Spintronic-CMOS Spiking Neural Network with On-Chip Learning: Devices, Circuits, and Systems

    Science.gov (United States)

    Sengupta, Abhronil; Banerjee, Aparajita; Roy, Kaushik

    2016-12-01

    Over the past decade, spiking neural networks (SNNs) have emerged as one of the popular architectures to emulate the brain. In SNNs, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing-dependent plasticity mechanisms require the online programing of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike-transmission and programing-current paths. The spintronic synapse consists of a ferromagnet-heavy-metal heterostructure where the programing current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programing energy and fast programing times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in the transistor subthreshold region to form a network of spiking neurons that can be utilized for pattern-recognition problems.

  7. Iterative current mode per pixel ADC for 3D SoftChip implementation in CMOS

    Science.gov (United States)

    Lachowicz, Stefan W.; Rassau, Alexander; Lee, Seung-Minh; Eshraghian, Kamran; Lee, Mike M.

    2003-04-01

    Mobile multimedia communication has rapidly become a significant area of research and development constantly challenging boundaries on a variety of technological fronts. The processing requirements for the capture, conversion, compression, decompression, enhancement, display, etc. of increasingly higher quality multimedia content places heavy demands even on current ULSI (ultra large scale integration) systems, particularly for mobile applications where area and power are primary considerations. The ADC presented in this paper is designed for a vertically integrated (3D) system comprising two distinct layers bonded together using Indium bump technology. The top layer is a CMOS imaging array containing analogue-to-digital converters, and a buffer memory. The bottom layer takes the form of a configurable array processor (CAP), a highly parallel array of soft programmable processors capable of carrying out complex processing tasks directly on data stored in the top plane. This paper presents a ADC scheme for the image capture plane. The analogue photocurrent or sampled voltage is transferred to the ADC via a column or a column/row bus. In the proposed system, an array of analogue-to-digital converters is distributed, so that a one-bit cell is associated with one sensor. The analogue-to-digital converters are algorithmic current-mode converters. Eight such cells are cascaded to form an 8-bit converter. Additionally, each photo-sensor is equipped with a current memory cell, and multiple conversions are performed with scaled values of the photocurrent for colour processing.

  8. Fully Integrated On-Chip Coil in 0.13 μm CMOS for Wireless Power Transfer Through Biological Media.

    Science.gov (United States)

    Zargham, Meysam; Gulak, P Glenn

    2015-04-01

    Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits.

  9. Single-Chip Fully Integrated Direct-Modulation CMOS RF Transmitters for Short-Range Wireless Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2013-08-01

    Full Text Available Ultra-low power radio frequency (RF transceivers used in short-range application such as wireless sensor networks (WSNs require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs in addition to a 2.0 GHz phase-locked loop (PLL based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of −122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of −120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

  10. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  11. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  12. A new equivalent circuit model for on-chip spiral transformers in CMOS RFICs

    Institute of Scientific and Technical Information of China (English)

    Wei Jiaju; Wang Zhigong; Li Zhiqun; Tang Lu

    2012-01-01

    A new compact model has been introduced to model on-chip spiral transformers.Unlike conventional models,which are often a compound of two spiral inductor models (i.e.,the combination of two coupled Π or 2-Π sub-circuits),our new model only uses 12 elements to model the whole structure in the form ofT topology.The new model is based on the physical meaning,and the process of model derivation is also presented.In addition,a simple parameter extraction procedure is proposed to get the elements' values without any fitting and optimization.In this procedure,a new method has been developed for the parameter extraction of the ladder circuit,which is commonly used to represent the skin effect.In order to verify the model's validity and accuracy,we have compared the simulated and measured self-inductance,quality factor,coupling coefficient and insertion loss,and an excellent agreement has been found over a broad frequency range up to the resonant frequency.

  13. Noise minimization via deep submicron system-on-chip integration in megapixel CMOS imaging sensors

    Science.gov (United States)

    Kozlowski, L. J.

    2006-03-01

    Infrared sensor designers have long maximized S/N ratio by employing pixel-based amplification in conjunction with supplemental noise suppression. Instead, we suppress photodiode noise using novel SoC implementation with simple three transistor pixel; supporting SoC components include a feedback amplifier having elements distributed amongst the pixel and column buffer, a tapered reset clock waveform, and reset timing generator. The tapered reset method does not swell pixel area, compel processing of the correlated reset and signal values, or require additional memory. Integrated in a 2.1 M pixel imager developed for generating high definition television, random noise is ˜8e-at video rates to 225 MHz. Random noise of ˜30e-would otherwise he predicted for the 5 μm 5 μm pixels having 5.5 fF detector capacitance with negligible image lag. Minimum sensor S/N ratio is 52 dB with 1920 by 1080 progressive readout at 60 Hz, 72 Hz and 90 Hz. Fixed pattern noise is <2 DN via on-chip signal processing.

  14. A fully on-chip three-terminal switched-capacitor DC-DC converter for low-voltage CMOS LSIs

    Science.gov (United States)

    Kojima, Yuta; Hirose, Tetsuya; Tsubaki, Keishi; Ozaki, Toshihiro; Asano, Hiroki; Kuroki, Nobutaka; Numa, Masahiro

    2016-04-01

    In this paper, we present a fully on-chip switched-capacitor DC-DC converter for low-voltage CMOS LSIs. The converter has three terminals of input, ground, and output, by developing control circuits with fully on-chip configuration. We employ an ultra low-power nanoampere bias current and voltage reference circuit to achieve ultra low-power dissipation of control circuits. It enables us to realize a highly efficient power conversion circuit at light-load-current applications. The converter achieves highly efficient and robust voltage conversion using a pulse frequency modulation control circuit and a start-up/fail-safe circuit. Measurement results demonstrated that the converter can convert a 3.0 V input into 1.2 V output successfully. The start-up and fail-safe operations were confirmed through the measurement. The efficiency was more than 50% in the range of 2-6 µA load current.

  15. Area-Efficient 60 GHz +18.9 dBm Power Amplifier with On-Chip Four-Way Parallel Power Combiner in 65-nm CMOS

    Science.gov (United States)

    Farahabadi, Payam Masoumi; Basaligheh, Ali; Saffari, Parvaneh; Moez, Kambiz

    2017-02-01

    This paper presents a compact 60-GHz power amplifier utilizing a four-way on-chip parallel power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.19-mm2 power amplifier at 60 GHz is 18.8 and 15 dB utilizing 1.4 and 1.0 V supply. Three-decibel band width of 4 GHz and P1dB of 16.9 dBm is measured while consuming 424 mW from a 1.4-V supply. A maximum saturated output power of 18.3 dBm is measured with the 15.9% peak power added efficiency at 60 GHz. The measured insertion loss is 1.9 dB at 60 GHz. The proposed power amplifier achieves the highest power density (power/area) compared to the reported 60-GHz CMOS power amplifiers in 65 nm or older CMOS technologies.

  16. CMOS图像传感器芯片的自动白平衡算法%Auto White Balance Algorithm for CMOS Image Sensor Chip

    Institute of Scientific and Technical Information of China (English)

    甘波; 魏廷存; 郑然

    2011-01-01

    针对CMOS图像传感器芯片中的自动白平衡图像处理电路,提出了一种便于硬件实现的增益计算方法,并在此基础上实现了一个用于CMOS图像传感器芯片的自动白平衡算法.该算法将增益计算的计算法与迭代法结合使用,并用比较器和移位寄存器来取代复杂的组合逻辑单元,在不增加硬件开销的基础上提高了计算精度与处理速度.%A method of gain calculation for auto white balance is proposed which is suitable for hardware implement in CMOS image sensors chip.Based on the method, an auto white balance algorithm used in CMOS image sensors chip is completed.Iterative method and calculation method are combined in this algorithm, and comparator and shift registers are used instead of complex combination logic cells.The computation accuracy and processing speed are improved without hardware expenses.

  17. A device design of an integrated CMOS poly-silicon biosensor-on-chip to enhance performance of biomolecular analytes in serum samples.

    Science.gov (United States)

    Pei-Wen, Yen; Che-Wei, Huang; Yu-Jie, Huang; Min-Cheng, Chen; Hsin-Hao, Liao; Shey-Shi, Lu; Chih-Ting, Lin

    2014-11-15

    For on-site clinical diagnosis of biomolecules, the detection performances of most point-of-care (POC) biosensor devices are limited by undesired cross-detection of other non-analyte proteins in patient serum samples and other complex samples. To conquer this obstacle, this work presents a fully integrated bottom-gate poly-silcion nanowire (polySi NW) biosensor system-on-chip (SoC) to enhance the detection performance of cardiac-specific troponin-I (cTnI) concentration levels in serum samples. By applying proper electrical potential at the bottom gate under polySi NW biosensor, the biosensor response to cTnI biomarker can be improved by at least 16 fold in 50% phantom serum samples. The experimental result shows its detection range is from 3.2 × 10(-13)M(mol l(-1)) to 3.2 × 10(-10)M. This enhancement can be attributed to the electrostatic interactions between target biomolecules and voltage-applied bottom gate electrodes. This is the first time that a polySi NW CMOS biosensor chip has shown feasibilities to detect specific biomarkers in serum samples. Therefore, the developed technology paves the way toward on-field applications of CMOS compatible SiNW biosensing technologies and it can be employed for future biomolecular analysis in on-site serum diagnosis applications.

  18. CMOS-Based Biosensor Arrays

    CERN Document Server

    Thewes, R; Schienle, M; Hofmann, F; Frey, A; Brederlow, R; Augustyniak, M; Jenkner, M; Eversmann, B; Schindler-Bauer, P; Atzesberger, M; Holzapfl, B; Beer, G; Haneder, T; Hanke, H -C

    2011-01-01

    CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

  19. CMOS array design automation techniques

    Science.gov (United States)

    Lombardi, T.; Feller, A.

    1976-01-01

    The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

  20. A high resolution, high frame rate detector based on a microchannel plate read out with the Medipix2 counting CMOS pixel chip.

    CERN Document Server

    Mikulec, Bettina; McPhate, J B; Tremsin, A S; Siegmund, O H W; Clark, Allan G; CERN. Geneva

    2005-01-01

    The future of ground-based optical astronomy lies with advancements in adaptive optics (AO) to overcome the limitations that the atmosphere places on high resolution imaging. A key technology for AO systems on future very large telescopes are the wavefront sensors (WFS) which detect the optical phase error and send corrections to deformable mirrors. Telescopes with >30 m diameters will require WFS detectors that have large pixel formats (512x512), low noise (<3 e-/pixel) and very high frame rates (~1 kHz). These requirements have led to the idea of a bare CMOS active pixel device (the Medipix2 chip) functioning in counting mode as an anode with noiseless readout for a microchannel plate (MCP) detector and at 1 kHz continuous frame rate. First measurement results obtained with this novel detector are presented both for UV photons and beta particles.

  1. Noiseless, kilohertz-frame-rate, imaging detector based on micro-channel plates readout with the Medipix2 CMOS pixel chip

    CERN Document Server

    McPhate, J; Tremsin, A; Siegmund, O; Mikulec, Bettina; Clark, Allan G; CERN. Geneva

    2005-01-01

    A new hybrid imaging detector is described that is being developed for the next generation adaptive optics (AO) wavefront sensors. The detector consists of proximity focused microchannel plates (MCPs) read out by pixelated CMOS application specific integrated circuit (ASIC) chips developed at CERN ("Medipix2"). Each Medipix2 pixel has an amplifier, lower and upper charge discriminators, and a 14-bit chounter. The 256x256 array can be read out noiselessly (photon counting) in 286 us. The Medipix2 is buttable on 3 sides to produce 512x(n*256) pixel devices. The readout can be electronically shuttered down to a terporal window of a few microseconds with an accuracy of 10 ns. Good quantum efficiencies can be achieved from the x-ray (open faced with opaque photocathodes) to the optical (sealed tube with multialkali or GaAs photocathode).

  2. A CMOS-compatible poly-Si nanowire device with hybrid sensor/memory characteristics for System-on-Chip applications.

    Science.gov (United States)

    Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

    2012-01-01

    This paper reports a versatile nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically V(th)-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady V(th) adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.

  3. A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

    Directory of Open Access Journals (Sweden)

    Chia-Hua Ho

    2012-03-01

    Full Text Available This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs in the conventional Complementary Metal-Oxide Semiconductor (CMOS-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH and sensitive deoxyribonucleic acid (DNA detection ability (100 pM at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window. The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording.

  4. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  5. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS

    Science.gov (United States)

    Zhixiong, Ren; Kefeng, Zhang; Lanqi, Liu; Cong, Li; Xiaofei, Chen; Dongsheng, Liu; Zhenglin, Liu; Xuecheng, Zou

    2015-09-01

    Three linear CMOS power amplifiers (PAs) with high output power (more than watt-level output power) for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer (PCT) and one 1.95 GHz PA using an on-chip series combining transformer (SCT) to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors (MGTR) and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE. Project supported by the National Natural Science Foundation of China (No. 61076030).

  6. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    Science.gov (United States)

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-12-16

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  7. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  8. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  9. MicroCMOS design

    CERN Document Server

    Song, Bang-Sup

    2011-01-01

    MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge. As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and tran

  10. IRRADIATION MEASUREMENTS ON THE 0.25 micro m CMOS PIXEL READOUT TEST CHIP BY A 14 MEV NEUTRON FACILITY

    CERN Document Server

    Barbera, R; CERN. Geneva; Palmeri, A; Pappalardo, G S; Riggi, F; Di Liberto, S; Meddi, F; Sestito, S; Loi, D; Angelone, M; Badalà, A; Pillon, M

    2000-01-01

    ALICE-ITS-2000-24   Abstract   A test facility station with 14 MeV neutrons was arranged at the FNG-ENEA Laboratory in Frascati (Italy) for the characterization with respect to radiation tolerance of the prototype pixel readout chips in 0.25 m m IBM technology done in edgeless design. This facility could allow to test both the readout chips and the pilot chips for the pixel readout system. In fact, both ASICs will have to survive at the same radiation level foreseen for the innermost layer (r = 4 cm) of the Inner Tracker System (ITS) in the LHC-ALICE experiment. Two test chips were exposed to an overall flux of 1.3 x 1012 14 MeV neutrons/cm2, which is larger than the expected neutron flux in ALICE during 10 years data taking. No variation in the parameters defining the chip functionality (analog and digital currents, linearity, shapes of the signal, efficiency) was observed.

  11. CMOS Nonlinear Signal Processing Circuits

    OpenAIRE

    2010-01-01

    The chapter describes various nonlinear signal processing CMOS circuits, including a high reliable WTA/LTA, simple MED cell, and low-voltage arbitrary order extractor. We focus the discussion on CMOS analog circuit design with reliable, programmable capability, and low voltage operation. It is a practical problem when the multiple identical cells are required to match and realized within a single chip using a conventional process. Thus, the design of high-reliable circuit is indeed needed. Th...

  12. On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS)

    CERN Document Server

    Sun, Q; Valin, I; Claus, G; Hu-Guo, Ch; Hu, Yu

    2009-01-01

    In a detector system, clock distribution to sensors must be controlled at a level allowing proper synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), we have proposed to distribute a low frequency clock at 10 MHz which will be multiplied to 160 MHz in each sensor by a PLL. A PLL has been designed for period jitter less than 20 ps rms, low power consumption and manufactured in a 0.35 μm CMOS process.

  13. Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

    Directory of Open Access Journals (Sweden)

    Al Al

    2015-01-01

    Full Text Available Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ-comparator, the encoder and the parallel input serial output (PISO register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 µm2 and the power dissipation is 0.162 µW with 1.6 V supply voltage.

  14. CMOS-compatible LVOF-based visible microspectrometer

    NARCIS (Netherlands)

    Emadi, A.; Wu, H.; De Graaf, G.; Wolffenbuttel, R.F.

    2010-01-01

    This paper reports on a CMOS-Compatible Linear Variable Optical Filter (LVOF) visible micro-spectrometer. The CMOS-compatible post process for fabrication of the LVOF has been used for integration of the LVOF with a CMOS chip containing a 128-element photodiode array and readout circuitry. Fabricati

  15. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  16. Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

    2015-01-01

    Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

  17. CMOS-array design-automation techniques

    Science.gov (United States)

    Feller, A.; Lombardt, T.

    1979-01-01

    Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

  18. A noiseless kilohertz frame rate imaging detector based on microchannel plates read out with the Medipix2 CMOS pixel chip

    CERN Document Server

    Mikulec, Bettina; Ferrère, Didier; La Marra, Daniel; McPhate, J B; Tremsin, A S; Siegmund, O H W; Vallerga, J V; Clement, J; Ponchut, C; Rigal, J M; CERN. Geneva

    2006-01-01

    A new hybrid optical imaging detector is described that is being developed for the next generation adaptive optics (AO) wavefront sensors (WFS) for ground-based telescopes. The detector consists of a photocathode and proximity focused microchannel plates (MCPs) read out by the Medipix2 CMOS pixel ASIC. Each pixel of the Medipix2 device measures 55x55 um2 and comprises pre-amplifier, a window discriminator and a 14-bit counter. The 256x256 Medipix2 array can be read out noiselessly in 287 us. The readout can be electronically shuttered down to a temporal window of a few us. The Medipix2 is buttable on 3 sides to produce 512x(n*256) pixel devices. Measurements with ultraviolet light yield a spatial resolution of the detector at the Nyquist limit. Sub-pixel resolution can be achieved using centroiding algorithms. For the AO application, very high continuous frame rates of the order of 1 kHz are required for a matrix of 512x512 pixels. The design concepts of a parallel readout board are presented that will allow ...

  19. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  20. Integrated RF MEMS/CMOS Devices

    CERN Document Server

    Mansour, R R; Bakeri-Kassem, M

    2008-01-01

    A maskless post-processing technique for CMOS chips is developed that enables the fabrication of RF MEMS parallel-plate capacitors with a high quality factor and a very compact size. Simulations and measured results are presented for several MEMS/CMOS capacitors. A 2-pole coupled line tunable bandpass filter with a center frequency of 9.5 GHz is designed, fabricated and tested. A tuning range of 17% is achieved using integrated variable MEMS/CMOS capacitors with a quality factor exceeding 20. The tunable filter occupies a chip area of 1.2 x 2.1 mm2.

  1. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    OpenAIRE

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal a...

  2. A CMOS floating point multiplier

    Science.gov (United States)

    Uya, M.; Kaneko, K.; Yasui, J.

    1984-10-01

    This paper describes a 32-bit CMOS floating point multiplier. The chip can perform 32-bit floating point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed point multiplication (two's complement format) in less than 78.7 and 71.1 ns, respectively, and the typical power dissipation is 195 mW at 10 million operations per second. High-speed multiplication techniques - a modified Booth's allgorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder - are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2 micron n-well CMOS technology; it contains about 23000 transistors of 5.75 x 5.67 sq mm in size.

  3. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis descri...

  4. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  5. Fluoroscopic x-ray demonstrator using a CdTe polycrystalline layer coupled to a CMOS readout chip

    Science.gov (United States)

    Arques, M.; Renet, S.; Brambilla, A.; Feuillet, G.; Gasse, A.; Billon-Pierron, N.; Jolliot, M.; Mathieu, L.; Rohr, P.

    2010-04-01

    Dynamic X-ray imagers require large surface, fast and highly sensitive X-ray absorbers and dedicated readout electronics. Monocrystalline photoconductors offer the sensitivity, speed, and MTF performances. Polycristalline photoconductors offer the large surface at a moderate cost. The challenge for them is to maintain the first performances at a compatible level with the medical applications requirements. This work has been focused on polycristalline CdTe grown by Close Space Sublimation (CSS) technique. This technique offers the possibility to grow large layers with a high material evaporation yield. This paper presents the results obtained with an image demonstrator using 350μm thick CdTe_css layers coupled to a CMOS readout circuit with Indium bumping. The present demonstrator has 200 x 200 pixels, with a pixel pitch of 75μm ×75μm. A total image surface of 15mm × 15mm has then been obtained. The ASIC works in an integration mode, i.e. each pixel accumulates the charges coming from the CdTe layer on a capacitor, converting them to a voltage. Single images as well as video sequences have been obtained. X-ray performance at 16 frames per second rate is measured. In particular a readout noise of 0.5 X ray, an MTF of 50% at 4 lp/mm and a DQE of 20% at 4lp/mm and 600 nGy are obtained. Although present demonstrator surface is moderate, it demonstrates that high performance can be expected from this assembly concept and its interest for medical applications.

  6. Design of a 10-bit segmented current-steering digital-to-analog converter in CMOS 65 nm technology for the bias of new generation readout chips in high radiation environment

    Science.gov (United States)

    De Robertis, G.; Loddo, F.; Mattiazzo, S.; Pacher, L.; Pantano, D.; Tamma, C.

    2016-01-01

    A new pixel front end chip for HL-LHC experiments in CMOS 65nm technology is under development by the CERN RD53 collaboration together with the Chipix65 INFN project. This work describes the design of a 10-bit segmented current-steering Digital-to-Analog Converter (DAC) to provide a programmable bias current to the analog blocks of the circuit. The main requirements are monotonicity, good linearity, limited area consumption and radiation hardness up to 10 MGy. The DAC was prototyped and electrically tested, while irradiation tests will be performed in Autumn 2015.

  7. Nano CMOS

    Directory of Open Access Journals (Sweden)

    Malay Ranjan Tripathy

    2009-05-01

    Full Text Available Complementary metal-oxide-semiconductor (CMOS has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discussed in this article. The challenges and opportunities of nano CMOS technology are outlined here.

  8. Graphene/Si CMOS hybrid hall integrated circuits.

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-07

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  9. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  10. Nano CMOS

    OpenAIRE

    2009-01-01

    Complementary metal-oxide-semiconductor (CMOS) has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discu...

  11. A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

    Science.gov (United States)

    Lattuca, A.; Mazza, G.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Mager, M.; Sielewicz, K. Marek; Marin Tobon, C. Augusto; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

    2016-01-01

    This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

  12. CMOS Image Sensors for High Speed Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2009-01-01

    Full Text Available Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps.

  13. CMOS Image Sensors for High Speed Applications.

    Science.gov (United States)

    El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

  14. Carbon Nanotube Integration with a CMOS Process

    OpenAIRE

    Perez, Maximiliano S.; Betiana Lerner; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Pedro M. Julian; Pablo S. Mandolesi; Fabian A. Buffa; Alfredo Boselli; Alberto Lamagna

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new rout...

  15. Carbon nanotube integration with a CMOS process.

    Science.gov (United States)

    Perez, Maximiliano S; Lerner, Betiana; Resasco, Daniel E; Pareja Obregon, Pablo D; Julian, Pedro M; Mandolesi, Pablo S; Buffa, Fabian A; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture.

  16. Carbon Nanotube Integration with a CMOS Process

    Directory of Open Access Journals (Sweden)

    Maximiliano S. Perez

    2010-04-01

    Full Text Available This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture.

  17. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  18. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... these issues and presents the development leading to applicable technological solutions. The via technology developed in this work enable effective utilization of the available surface area on both sides of the amplifier chip for redistribution as well as placement of passive components and external...... connections. A process for wafer level packaging and assembly of chips with vias is presented in this thesis. Discrete components, capacitors and resistors, are assembled on the backside of the amplifier chips by screen printing of solder paste, pick and place of components, and reflow soldering. Since...

  19. Label-free CMOS bio sensor with on-chip noise reduction scheme for real-time quantitative monitoring of biomolecules.

    Science.gov (United States)

    Seong-Jin Kim; Euisik Yoon

    2012-06-01

    We present a label-free CMOS field-effect transistor sensing array to detect the surface potential change affected by the negative charge in DNA molecules for real-time monitoring and quantification. The proposed CMOS bio sensor includes a new sensing pixel architecture implemented with correlated double sampling for reducing offset fixed pattern noise and 1/f noise of the sensing devices. We incorporated non-surface binding detection which allows real-time continuous monitoring of DNA concentrations without immobilizing them on the sensing surface. Various concentrations of 19-bp oligonucleotides solution can be discriminated using the prototype device fabricated in 1- μm double-poly double-metal standard CMOS process. The detection limit was measured as 1.1 ng/μl with a dynamic range of 40 dB and the transient response time was measured less than 20 seconds.

  20. Lab-on-CMOS integration of microfluidics and electrochemical sensors.

    Science.gov (United States)

    Huang, Yue; Mason, Andrew J

    2013-10-07

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

  1. A High-Speed CMOS Image Sensor for Real-Time Vision Chip%面向实时视觉芯片的高速CMOS图像传感器

    Institute of Scientific and Technical Information of China (English)

    付秋瑜; 林清宇; 张万成; 吴南健

    2011-01-01

    A high-speed CMOS image sensor for real-time vision chip is proposed. The high-speed CMOS image sensor consists of CMOS photodiode array, correlated double sampling (CDS) array, programmable gain amplifier (PGA) array, area-efficient single-slope analog-to-digital converter (ADC) array and controller circuit. It can perform the image capturing and row-parallel signal processing. It outputs digital signal or digital image at a frame rate of over 1000 frame/s. It can reduce the fixed pattern noise (FPN) and amplify (or shrink) the output signals of the photodiode array to maintain the amplitude of the signal in row-parallel fashion. It can continuously perform 8-bit ADC conversion in row-parallel. A 128 pixel × 128 pixel image sensor with 128 rows of CDS, PGA and single-slope ADC is fabricated by using 0.18 μm 1P6M CMOS process. The chip size is 2. 2 mm× 2. 6 mm. The measured results demonstrate that the designed chip can perform high-speed real-time optical signal capturing and processing. It can be applied to the real-time vision chip system.%提出了一种面向实时视觉芯片的高速CMOS图像传感器.该高速图像传感器主要包括CMOS像素单元阵列、相关双采样(CDS)阵列、可编程增益放大(PGA)阵列、单次比较模数转换(ADC)阵列和控制模块.该传感器集成了光信号采集和行并行信号处理等功能,以大于1000 frame/s的速度输出数字信号或数字图像,同时实现了行并行方式的固定模式噪声消除、编程控制输出信号动态范围调节、连续8位行并行模数信号转换的功能.采用0.18 μm 1P6M CMOS工艺实现了高速图像传感器,芯片面积为2.2 mm×2.6 mm,测试结果表明,该芯片可以完成实时高速光信号采集及处理,适用于集成高速实时视觉芯片系统.

  2. Effect of Chipping and Solarization on Emergence and Boring Activity of a Recently Introduced Ambrosia Beetle (Euwallacea sp., Coleoptera: Curculionidae: Scolytinae) in Southern California.

    Science.gov (United States)

    Eatough Jones, Michele; Paine, Timothy D

    2015-08-01

    Polyphagous shot hole borer (Euwallacea sp., Coleoptera: Curculionidae: Scolytinae) has recently invaded southern California. The beetle, along with its associated fungi, Fusarium euwallaceae, Graphium sp., and Acremonium sp., causes branch dieback and tree mortality in a large variety of tree species including avocado (Persea americana Mill.) and box elder (Acer negundo L.). With the spread of the beetle through Los Angeles, Orange, and San Diego Counties in California, there is increasing concern that felled trees and pruned branches infested with polyphagous shot hole borer should receive sanitation treatment to reduce the potential spread of the beetle from the movement of untreated wood. We tested two sanitation methods to reduce beetle populations, chipping with a commercial chipper and solarization by covering logs with clear or black plastic in full sun. Both chipping and solarization decreased beetle emergence and boring activity compared to untreated control logs. Chipping was most effective for chip sizes <5 cm. Solarization was most effective using clear polyethylene sheeting during hot summer months, particularly August, when daily maximum temperatures were ≥35°C. Beetles persisted for 2 mo or more when solarization was applied during the spring or fall.

  3. Fuzzy Logic Control ASIC Chip

    Institute of Scientific and Technical Information of China (English)

    沈理

    1997-01-01

    A fuzzy logic control VLSI chip,F100,for industry process real-time control has been designed and fabricated with 0.8μm CMOS technology.The chip has the features of simplicity,felexibility and generality.This paper presents the Fuzzy control inrerence method of the chip,its VLSI implementation,and testing esign consideration.

  4. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  5. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  6. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  7. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  8. DESIGN AND IMPLEMETTATION OF CMOS IMAGE SENSOR

    Institute of Scientific and Technical Information of China (English)

    Liu Yu; Wang Guoyu

    2007-01-01

    A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.

  9. Spatio-temporal simulation in subthreshold CMOS

    Science.gov (United States)

    Neeley, John; Harris, John G.

    1997-05-01

    This paper reports on the design and chip measurements from a CMOS chaotic oscillator operating by itself and connected in a ring of four similar oscillators. The oscillator is autonomous and generates signals with three state variables analogous to Chua's circuit. For commensurate bandwidth, this design utilizes currents and capacitors over 200 times smaller than above threshold CMOS realizations. Also, all circuit elements are on chip. The resulting voltage-controlled bifurcation parameters simplify exploration of the circuit's dynamics, alleviating the need to interchange physical components. This combination of reduced size and variable parameters make the design suitable for single-chip VLSI synthesis of higher dimensional chaotic circuits, including coupled maps generating spatio-temporal chaos and systems exploiting chaos synchronization.

  10. A 5.8nW, 45ppm/°C On-Chip CMOS Wake-up Timer Using a Constant Charge Subtraction Scheme.

    Science.gov (United States)

    Jeong, Seokhyeon; Lee, Inhee; Blaauw, David; Sylvester, Dennis

    2014-09-01

    This work presents an ultra-low power oscillator designed for wake-up timers in compact wireless sensors. A constant charge subtraction scheme removes continuous comparator delay from the oscillation period, which is the source of temperature dependence in conventional RC relaxation oscillators. This relaxes comparator design constraints, enabling low power operation. In 0.18µm CMOS, the oscillator consumes 5.8nW at room temperature with temperature stability of 45ppm/°C (-10°C to 90°C) and 1%V line sensitivity.

  11. Design and realization of CMOS image sensor

    Science.gov (United States)

    Xu, Jian; Xiao, Zexin

    2008-02-01

    A project was presented that instrumental design of an economical CMOS microscope image sensor. A high performance, low price, black-white camera chip OV5116P was used as the core of the sensor circuit; Designing and realizing peripheral control circuit of sensor; Through the control on dial switch to realize different functions of the sensor chip in the system. For example: auto brightness level descending function on or off; gamma correction function on or off; auto and manual backlight compensation mode conversion and so on. The optical interface of sensor is designed for commercialization and standardization. The images of sample were respectively gathered with CCD and CMOS. Result of the experiment indicates that both performances were identical in several aspects as follows: image definition, contrast control, heating degree and the function can be adjusted according to the demand of user etc. The imperfection was that the CMOS with smaller field and higher noise than CCD; nevertheless, the maximal advantage of choosing the CMOS chip is its low cost. And its imaging quality conformed to requirement of the economical microscope image sensor.

  12. Modeling of Amperometric Immunosensor for CMOS Integration

    Institute of Scientific and Technical Information of China (English)

    Ce Li; Haigang Yang; Shanhong Xia; Chao Bian

    2006-01-01

    A circuit model of the Amperometric immunosensor for use in the biosensor system-on-chip simulation is proposed in this paper. The model parameters are extracted with several methods and verified by MATLAB and SPICE simulation. A CMOS potentiostat circuit required for conditioning the Amperometric immunosensor is also included in the circuit model. The mean square error norm of the simulated curve against the measured one is 8.65 × 10-17. The whole circuit has been fabricated in a 0.35am CMOS process.

  13. Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13 μm CMOS technology

    CERN Document Server

    Gromov, V; van der Graaf, H

    2007-01-01

    The new GOSSIP detector, capable to detect single electrons in gas, has certain advantages with respect silicon (pixel) detectors. It does not require a Si sensor; it has a very low detector parasitic capacitance and a zero bias current at the pixel input. These are attractive features to design a compact, low-noise and low-power integrated input circuit. A prototype of the integrated circuit has been developed in 0.13 μm CMOS technology. It includes a few channels equipped with preamplifier, discriminator and the digital circuit to study the feasibility of the TDC-perpixel concept. The design demonstrates very low input referred noise (60e- RMS) in combination with a fast peaking time (40 ns) and an analog power dissipation as low as 2 μW per channel. Switching activity on the clock bus (up to 100 MHz) in the close vicinity of the pixel input pads does not cause noticeable extra noise.

  14. Analog floating-point BiCMOS sampling chip and architecture of the BaBar CsI calorimeter front-end electronics system at the SLAC B-Factory

    Energy Technology Data Exchange (ETDEWEB)

    Haller, G.M.; Freytag, D.R. [Stanford Univ., CA (United States). Stanford Linear Accelerator Center

    1996-06-01

    The design and implementation of an analog floating-point sampling integrated circuit for the BaBar detector at the SLAC B-Factory is described. The CARE (Custom Auto-Range Encoding) circuit is part of an 18-bit dynamic range sampling system with a 4-MHz waveform digitization rate for the CsI calorimeter. The architecture and methodology of the system are described. The CARE integrated circuit receives dual-range (gain of 1 and 32) 13-bit signals from the 18-bit range preamplifiers mounted directly on the CsI crystals and converts the input at a rate of 4 MHz to an auto-range floating-point format with a 10-bit analog mantissa and 2 digital range bits (for 4 ranges). Additional functions integrated on the chip are averaging and selection circuitry for signals originating from two independent diodes per crystal and range-selection overwrite circuitry. The circuit will be mounted within the detector structure and thus low power dissipation is essential. The circuit has been fabricated in a 1.2 {micro}m BiCMOS process with polysilicon-to-polysilicon capacitors and polysilicon resistors. Measurement results are presented. One complete CARE channel dissipates 25 mW.

  15. Compact 0.3-to-1.125 GHz self-biased phase-locked loop for system-on-chip clock generation in 0.18 µm CMOS

    Science.gov (United States)

    Zhang, Zhao; Liu, Liyuan; Feng, Peng; Liu, Jian; Wu, Nanjian

    2016-04-01

    In this paper, we propose a compact ring-oscillator-based self-biased phase-locked loop (SBPLL) for system-on-chip (SoC) clock generation. It adopts the proposed triple-well NMOS source degeneration voltage-to-current (V-I) converter instead of the operational amplifier (OPAMP) based V-I converter and a proposed simple start-up circuit with a negligible area to save power and area. The SBPLL is implemented in the 0.18 µm CMOS process, and it occupies 0.048 mm2 active core. The measurement results show the SBPLL can generate output frequency in a wide range from 300 MHz to 1.125 GHz with a constant loop bandwidth that is around 5 MHz and a relatively low jitter performance that is less than 4.9 mUI over the entire covered frequency range. From -20 to 70 °C the rms jitter variation and loop bandwidth variation at 1.125 GHz are 0.2 ps and 350 kHz, respectively. The rms jitter performance variation of all covered frequency points is less than 10% in the supply range from 1.5 to 1.7 V. Such SBPLL shows robustness over environmental variation. The maximum power consumption is 5.6 mW with 1.6 V supply at an output frequency of 1.125 GHz.

  16. 一种CMOS集成MEMS片上螺旋电感设计与仿真%Design and Simulation of a CMOS Integrated MEMS On-chip Spiral Inductor

    Institute of Scientific and Technical Information of China (English)

    卢冲赢; 徐立新; 王婷

    2012-01-01

    A CMOS-compatible MEMS integrated on-chip inductor is designed. The square planar spiral coil program is utilized. The coils are made of copper with a higher conductivity than aluminum. In order to improve the quality factor (Q) of the inductor, thick metal coils and cavities etched in the CMOS -grade silicon substrate are designed by the MEMS technology, which can reduce the serial resistance of metal square planar spiral coils and the losses in the low resistance silicon substrate, respectively. A fully CMOS -compatible low temperature MEMS process is presented and a lnH inductor model with thick metal coils and low-loss MEMS substrate is simulated by using HFSS software. Simulation results show that the inductor obtained by this CMOS-compatible low temperature MEMS process enjoys a high peak quality factor of 22.37 and 20.74 at 6.6GHz and lOGHz with a self-resonant frequency over 20GHz, respectively. The influences of metal coils' thickness on the quality factor and the inductance are also analyzed. When the thickness ofthe inductor is increased, the quality factor is increased while the inductance is decreased. The fluctuation of the inductance is less than5.5% in the simulation frequency range.%设计了一种与CMOS工艺兼容的MEMS片上螺旋电感.电感为矩形平面螺旋线圈结构,并采用电导率较高的铜代替铝制作线圈.利用MEMS技术设计了厚金属线圈,同时在CMOS级低阻硅衬底中刻蚀空腔,减小了线圈的串联电阻和衬底损耗,提高了电感的Q值.设计了与CMOS工艺相兼容的低温MEMS工艺和基于该工艺的1niH电感模型.使用HFSS软件对该电感模型进行仿真,结果表明,该电感在仿真频率为6.6GHz和10GHz时Q值分别达到了22.37和20.74,且自谐振频率大于20GHz,较传统的CMOS片上集成电感有明显改善;同时随着电感线圈厚度的增加,电感的Q值增加,而电感值(L值)则减小,且在仿真频段内电感值的变化小于5.5%.

  17. Design of 2.1 GHz CMOS Low Noise Amplifier

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    This paper discusses the design of a fully differential 2.1 GHz CMOS low noise amplifier using the TSMC0.25 μm CMOS process. Intended for use in 3G, the low noise amplifier is fully integrated and without off-chip components. The design uses an LC tank to replace a large inductor to achieve a smaller die area, and uses shielded pad capacitances to improve the noise performance. This paper also presents evaluation results of the design.

  18. Hybrid CMOS / Microfluidic Systems for Cell Manipulation with Dielectrophoresis

    Science.gov (United States)

    Hunt, Tom; Issadore, David; Westervelt, Robert M.

    2007-03-01

    A hybrid CMOS/microfluidic chip combines the biocompatibility of microfluidics with the built-in logic, programmability, and sensitivity of CMOS integrated circuits (ICs)^1 We have designed a CMOS IC for moving individual cells using dielectrophoresis (DEP). The IC was built in a commercial foundry and we subsequently fabricated a microfluidic chamber on the top surface. The chip consists of a 1.4 by 2.8mm array of over 32,000 individually addressable 11x11 micron pixels. An RF voltage of 5V at 10MHz can be applied to each pixel with respect to the conductive lid of the microfluidic chamber, producing a localized electric field that can trap a cell. By shifting the location of energized pixels, the array can trap and move cells along programmable paths through the microfluidic chamber. We show the design, fabrication, and testing of the hybrid chip. Bringing together the biocompatibility of microfluidics and the power of CMOS chips, hybrid CMOS / microfluidic systems are an exciting technology for biomedical research. Thanks to NSEC NSF grant PHY-0117795 and the NCI MIT-Harvard CCNE. [1] H Lee, Y Liu, RM Westervelt, D Ham, IEEE JSSC 41, 6, pp. 1471-1480, 2006

  19. Cantilever-Based Biosensors in CMOS Technology

    CERN Document Server

    Kirstein, K -U; Zimmermann, M; Vancura, C; Volden, T; Song, W H; Lichtenberg, J; Hierlemannn, A

    2011-01-01

    Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integrated Wheatstone bridge. The monolithic integrated readout allows for a high signal-to-noise ratio, lowers the sensitivity to external interference and enables autonomous device operation.

  20. On-chip data communication

    NARCIS (Netherlands)

    Schinkel, Daniel

    2011-01-01

    On-chip data communication is an active research area, as interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Especially for global interconnects that have to span large parts of a chip, there is an increasing gap between transistor speed and interc

  1. On-chip data communication

    NARCIS (Netherlands)

    Schinkel, Daniel

    2011-01-01

    On-chip data communication is an active research area, as interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Especially for global interconnects that have to span large parts of a chip, there is an increasing gap between transistor speed and

  2. POWER DRIVEN SYNTHESIS OF COMBINATIONAL CIRCUITS ON THE BASE OF CMOS VLSI LIBRARY ELEMENTS

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2013-01-01

    Full Text Available A problem of synthesis of multi-level logical networks using CMOS VLSI cell library is considered. The networks are optimized with respect to the die size and average dissipated power by CMOS-circuit implemented on a VLSI chip. The suggested approach is based on covering multilevel gate network and on taking into account specific features of the CMOS cell basis.

  3. Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

    Science.gov (United States)

    Duong, Tuan A. (Inventor)

    2015-01-01

    A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

  4. Reliability engineering in RF CMOS

    OpenAIRE

    2008-01-01

    In this thesis new developments are presented for reliability engineering in RF CMOS. Given the increase in use of CMOS technology in applications for mobile communication, also the reliability of CMOS for such applications becomes increasingly important. When applied in these applications, CMOS is typically referred to as RF CMOS, where RF stands for radio frequencies.

  5. Design of CMOS Digital Thermal Vacuum Sensor Chip%CMOS数字热真空传感器芯片设计

    Institute of Scientific and Technical Information of China (English)

    李金凤; 刘沁; 张治国; 曹顺

    2012-01-01

    基于标准CMOS工艺设计了一款集成热真空传感器、运算放大器、逐次逼近型模数转换器(SAR ADC)、数字信号处理电路的传感器系统.工作在恒电流模式的传感器,气压敏感区间为1~105 Pa.运算放大器(OPAMP)的输入级采用互补差分对获得轨至轨的共模输入范围.为满足精度要求,对SAR ADC中数模转换器电容阵列进行优化设计,并采用输出失调存储技术消除比较器的失调电压.数字电路采用查表法将电压信号变换为气压值.结果表明:运算放大器能无失真地驱动200 Q电阻,模数转换器的有效位为9.5 bit.运算放大器、模数转换器、数字信号处理电路性能良好,满足传感器系统要求.%A sensor system was designed based on the standard CMOS process. The thermal vacuum sensor, operational amplifier (OPAMP), successive approximation register analog to digital converter (SAR ADC ) and digital signal processing circuit were integrated in it. The vacuum sensor worked in the constant-current mode whose gas pressure sensitive range extended from 1 Pa to 10 Pa. The OPAMP adopted the complementary differential pairs to obtain the rail to rail common-mode input range. The capacitor array of the DAC in the SAR ADC was optimized, and the offset voltage of the comparator was eliminated using the output offset storage technique. The digital circuit transformed voltage signal into gas pressure value by the look-up table. The results show that the OPAMP can drive 200 ft resistors distortion lessly, and the ADC achieves a resolution of 9. 5 bit. The OPAMP, SAR ADC and digital circuit have good performances, and meet the requirements of the sensor system.

  6. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  7. Analog CMOS contrastive Hebbian networks

    Science.gov (United States)

    Schneider, Christian; Card, Howard

    1992-09-01

    CMOS VLSI circuits implementing an analog neural network with on-chip contrastive Hebbian learning and capacitive synaptic weight storage have been designed and fabricated. Weights are refreshed by periodic repetition of the training data. To evaluate circuit performance in a medium-sized system, these circuits were used to build a 132 synapse neural network. An adaptive neural system, such as the one described in this paper, can compensate for imperfections in the components from which it is constructed, and thus it is possible to build this type of system using simple, silicon area-efficient analog circuits. Because these analog VLSI circuits are far more compact than their digital counterparts, analog VLSI neural network implementations are potentially more efficient than digital ones.

  8. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  9. CAOS-CMOS camera.

    Science.gov (United States)

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

  10. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the

  11. Thermal-Diffusivity-Based Frequency References in Standard CMOS

    NARCIS (Netherlands)

    Kashmiri, S.M.

    2012-01-01

    In recent years, a lot of research has been devoted to the realization of accurate integrated frequency references. A thermal-diffusivity-based (TD) frequency reference provides an alternative method of on-chip frequency generation in standard CMOS technology. A frequency-locked loop locks the outpu

  12. A Single-Transistor Active Pixel CMOS Image Sensor Architecture

    Institute of Scientific and Technical Information of China (English)

    ZHANG Guo-An; ZHANG Dong-Wei; HE Jin; SU Yan-Mei; WANG Cheng; CHEN Qin; LIANG Hai-Lang; YE Yun

    2012-01-01

    A single-transistor CMOS active pixel image sensor (1T CMOS APS) architecture is proposed,By switching the photosensing pinned diode,resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus,the reset and selected transistors can be removed. In addition,the reset and selected signal lines can be shared to reduce the metal signal line,leading to a very high fill factor.The pixel design and operation principles are discussed in detail.The functionality of the proposed 1 T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology.

  13. A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array

    Institute of Scientific and Technical Information of China (English)

    唐志敏; 夏培肃

    1995-01-01

    This paper describes a maximum time difference pipelined arithmetic chip,the 36-bit adder and subtractor based on 1.5μm CMOS gate array.The chip can operate at 60MHz,and consumes less than 0.5Watt.The results are also studied,and a more precise model of delay time difference is proposed.

  14. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    Science.gov (United States)

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

  15. A Full CMOS Integration Including ISFET Microsensors and Interface Circuit for Biochemical Applications

    Institute of Scientific and Technical Information of China (English)

    Jinbao Wei; Haigang Yang; Hongguang Sun; Zengjin Lin; Shanhong Xia

    2006-01-01

    One of today's challenges is the integration of ISFETs in chemical and biochemical Microsystems. This article presents a full integration of ISFET chip containing the ISFET/REFET (reference FET) pair, ISFET/REFET amplifiers, bias current generator, as well as a reference electrode structure, all integrated on the same chip based on CMOS technology. The sensor chip was fabricated in a standard 0.35 μm CMOS process (Chartered Semiconductor, Singapore). The extra post processing steps have been developed and added for depositing membranes. Finally, the pH response of the integrated sensor was measured with the interface circuit.

  16. CMOS MEMS capacitive absolute pressure sensor

    Science.gov (United States)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  17. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  18. Improved Space Object Observation Techniques Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  19. A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro

    OpenAIRE

    Tateno, Takashi; Nishikawa, Jun

    2014-01-01

    In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) w...

  20. A CMOS IC–based multisite measuring system for stimulation and recording in neural preparations in vitro

    OpenAIRE

    Takashi eTateno; Jun eNishikawa

    2014-01-01

    In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 mm × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs...

  1. NSC 800, 8-bit CMOS microprocessor

    Science.gov (United States)

    Suszko, S. F.

    1984-01-01

    The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

  2. A Neuron- and a Synapse Chip for Artificial Neural Networks

    DEFF Research Database (Denmark)

    Lansner, John; Lehmann, Torsten

    1992-01-01

    A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where...

  3. Packetizing OCP Transactions in the MANGO Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    The scaling of CMOS technology causes a widening gap between the performance of on-chip communication and computation. This calls for a communication-centric design flow. The MANGO network-on-chip architecture enables globally asynchronous locally synchronous (GALS) system-on-chip design, while...

  4. CMOS-compatible photonic devices for single-photon generation

    Directory of Open Access Journals (Sweden)

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  5. CMOS-compatible photonic devices for single-photon generation

    Science.gov (United States)

    Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

    2016-09-01

    Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  6. CMOS imager for pointing and tracking applications

    Science.gov (United States)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  7. A Multipurpose CMOS Platform for Nanosensing

    Directory of Open Access Journals (Sweden)

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  8. CMOS biosensors for in vitro diagnosis - transducing mechanisms and applications.

    Science.gov (United States)

    Lei, Ka-Meng; Mak, Pui-In; Law, Man-Kay; Martins, Rui P

    2016-09-21

    Complementary metal oxide semiconductor (CMOS) technology enables low-cost and large-scale integration of transistors and physical sensing materials on tiny chips (e.g., key functions of biosensors: transducing and signal processing. Recent CMOS biosensors unified different transducing mechanisms (impedance, fluorescence, and nuclear spin) and readout electronics have demonstrated competitive sensitivity for in vitro diagnosis, such as detection of DNA (down to 10 aM), protein (down to 10 fM), or bacteria/cells (single cell). Herein, we detail the recent advances in CMOS biosensors, centering on their key principles, requisites, and applications. Together, these may contribute to the advancement of our healthcare system, which should be decentralized by broadly utilizing point-of-care diagnostic tools.

  9. Piezoresistive Sensors Development Using Monolithic CMOS MEMS Technology

    Directory of Open Access Journals (Sweden)

    A. Chaehoi

    2011-04-01

    Full Text Available This paper presents the development of a monolithic CMOS-MEMS platform under the iDesign and SemeMEMS projects with the aim of jointly providing an open access “one-stop-shop” design and prototyping facility for integrated CMOS-MEMS. This work addresses the implementation of a 3-axis accelerometer and a pressure sensor using Semefab’s in-house 2-poly 1-metal CMOS process on a 380/4/15 μm SOI wafer; the membrane and the proof mass being micromachined using double-sided Deep Reactive Ion Etching (DRIE. This monolithic approach promises, in high volume production and using low complexity processes, a dramatic cost reduction over hybrid sensors. Furthermore, the embedded signal conditioning and the low-noise level in polysilicon gauges enables high performance to be achieved by implementing dedicated on-chip amplification and filtering circuitry.

  10. Silicon pixel detector prototyping in SOI CMOS technology

    Science.gov (United States)

    Dasgupta, Roma; Bugiel, Szymon; Idzik, Marek; Kapusta, Piotr; Kucewicz, Wojciech; Turala, Michal

    2016-12-01

    The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.

  11. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  12. Low-Frequency-Noise Reduction Technique for Linear Analog CMOS IC's

    OpenAIRE

    Koh, Jeongwook

    2007-01-01

    For AMS (analog-mixed signal) and RF (radio frequency) implementations CMOS (Complementary Metal Oxide Semiconductor) technology platforms are the mainstream today. These platforms provide great density and power savings on digital parts on the same chip and, in addition, a good mix of components for analog design. The analog performance of CMOS technology is worse compared to other technology options (e.g. bipolar technology), and its major advantage is the lower total cost of system. Severa...

  13. A Linearity-Enhanced Time-Domain CMOS Thermostat with Process-Variation Calibration

    OpenAIRE

    Chun-Chi Chen; Yi Lin

    2014-01-01

    This study proposes a linearity-enhanced time-domain complementary metal-oxide semiconductor (CMOS) thermostat with process-variation calibration for improving the accuracy, expanding the operating temperature range, and reducing test costs. For sensing temperatures in the time domain, the large characteristic curve of a CMOS inverter markedly affects the accuracy, particularly when the operating temperature range is increased. To enhance the on-chip linearity, this study proposes a novel tem...

  14. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Fadeyev, V., E-mail: fadeyev@ucsc.edu [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Galloway, Z.; Grabas, H.; Grillo, A.A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz, CA 95064 (United States); Affolder, A.; Buckland, M.; Meng, L. [Department of Physics, University of Liverpool, O. Lodge Laboratory, Oxford Street, Liverpool L69 7ZE (United Kingdom); Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I. [Department of Physics, Oxford University, Oxford (United Kingdom); and others

    2016-09-21

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  15. Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

    Science.gov (United States)

    Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

    2016-09-01

    ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

  16. Capacitor-Free, Low Drop-Out Linear Regulator in a 180 nm CMOS for Hearing Aids

    DEFF Research Database (Denmark)

    Yosef-Hay, Yoni; Llimos Muntal, Pere; Larsen, Dennis Øland;

    2016-01-01

    . The proposed design works without the need of an off-chip discrete capacitor connected at the output and operates with 0-100 pF capacitive load. The design has been implemented in a 0.18 µm CMOS process. The proposed regulator has a low component count and is suitable for system-on-chip integration...

  17. Integrated CMOS sensor technologies for the CLIC tracker

    CERN Document Server

    AUTHOR|(SzGeCERN)754303

    2017-01-01

    Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear e+e- collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.

  18. Chip, Chip, Hooray!

    Science.gov (United States)

    Kelly, Susan

    2001-01-01

    Presents a science laboratory using different brands of potato chips in which students test their oiliness, size, thickness, saltiness, quality, and cost, then analyze the results to determine the best chip. Gives a brief history of potato chips. (YDS)

  19. CMOS Conductometric System for Growth Monitoring and Sensing of Bacteria.

    Science.gov (United States)

    Lei Yao; Lamarche, P; Tawil, N; Khan, R; Aliakbar, A M; Hassan, M H; Chodavarapu, V P; Mandeville, R

    2011-06-01

    We present the design and implementation of a prototype complementary metal-oxide semiconductor (CMOS) conductometric integrated circuit (IC) for colony growth monitoring and specific sensing of Escherichia coli (E. coli) bacteria. The detection of E. coli is done by employing T4 bacteriophages as receptor organisms. The conductometric system operates by measuring the resistance of the test sample between the electrodes of a two-electrode electrochemical system (reference electrode and working electrode). The CMOS IC is fabricated in a TSMC 0.35-μm process and uses a current-to-frequency (I to F) conversion circuit to convert the test sample resistance into a digital output modulated in frequency. Pulsewidth control (one-shot circuit) is implemented on-chip to control the pulsewidth of the output digital signal. The novelty in the current work lies in the ability of the CMOS sensor system to monitor very low initial concentrations of bacteria (4×10(2) to 4×10(4) colony forming unit (CFU)/mL). The CMOS system is also used to record the interaction between E. coli and its specific receptor T4 bacteriophage. The prototype CMOS IC consumes an average power of 1.85 mW with a 3.3-V dc power supply.

  20. Design and fabrication of vertically-integrated CMOS image sensors.

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

  1. Building strong partnerships with CMOs.

    Science.gov (United States)

    Dye, Carson F

    2014-07-01

    CFOs and chief medical officers (CMOs) can build on common traits to form productive partnerships in guiding healthcare organizations through the changes affecting the industry. CFOs can strengthen bonds with CMOs by taking steps to engage physicians on their own turf--by visiting clinical locations and attending medical-executive committee meetings, for example. Steps CFOs can take to help CMOs become more acquainted with the financial operations of health systems include demonstrating the impact of clinical decisions on costs and inviting CMOs to attend finance-related meetings.

  2. 40.4fJ/bit/mm Low-Swing On-Chip Signaling with Self-Resetting Logic Repeaters Embedded within a Mesh NoC in 45nm SOI CMOS

    OpenAIRE

    Park, Sunghyun; Qazi, Masood; Peh, Li-Shiuan; Chandrakasan, Anantha P.

    2013-01-01

    Mesh NoCs are the most widely-used fabric in high-performance many-core chips today. They are, however, becoming increasingly power-constrained with the higher on-chip bandwidth requirements of high-performance SoCs. In particular, the physical datapath of a mesh NoC consumes significant energy. Low-swing signaling circuit techniques can substantially reduce the NoC datapath energy, but existing low-swing circuits involve huge area footprints, unreliable signaling or considerable system overh...

  3. A CMOS Imager with Focal Plane Compression using Predictive Coding

    Science.gov (United States)

    Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

    2007-01-01

    This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

  4. Fermilab silicon strip readout chip for BTev

    Energy Technology Data Exchange (ETDEWEB)

    Yarema, Raymond; Hoff, Jim; Mekkaoui, Abderrezak; Manghisoni, Massimo; Re, Valerio; Angeleri, Valentina; Manfredi, Pier Francesco; Ratti, Lodovico; Speziali, Valeria; /Fermilab /Bergamo U. /INFN, Pavia /Pavia U.

    2005-05-01

    A chip has been developed for reading out the silicon strip detectors in the new BTeV colliding beam experiment at Fermilab. The chip has been designed in a 0.25 {micro}m CMOS technology for high radiation tolerance. Numerous programmable features have been added to the chip, such as setup for operation at different beam crossing intervals. A full size chip has been fabricated and successfully tested. The design philosophy, circuit features, and test results are presented in this paper.

  5. Planar pixel sensors in commercial CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

    2015-07-01

    For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

  6. Interconnects and On-Chip Data Communication Techniques

    NARCIS (Netherlands)

    Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria

    Global on-chip communication is rapidly becoming a speed and power bottleneck in CMOS circuits. In this paper, a ‘mixed-signal’ approach is taken to analyze on-chip interconnects and it is investigated how data-rates can be improved. It is shown that complex signaling schemes such as OFDM and CDMA

  7. Design of Antenna-on-Chip, Antenna-on-Package and Detectors from RF, Microwave to THz Frequency Range in SiGe-C Technology

    NARCIS (Netherlands)

    Wane, S; Bardy, S.; Heijster, R.M.E.M. van; Goulet, F.; Gamand, P.

    2011-01-01

    Design solutions for on-chip signal detectors, Antenna-on- Chip and Antenna-on-Package (with Bond Wire elements), from RF, Microwave to THz frequency range, using state-of-theart SiGe BiCMOS technology are presented. Both CML and CMOS detectors are designed, fabricated and compared in terms of their

  8. RF Calibration of On-Chip DfT Chain by DC Stimuli and Statistical Multivariate Regression Technique

    OpenAIRE

    Ramzan, Rashad; Dabrowski, Jerzy

    2015-01-01

    The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to archite...

  9. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  10. High-Voltage-Input Level Translator Using Standard CMOS

    Science.gov (United States)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  11. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Institute of Scientific and Technical Information of China (English)

    Gao Tongqiang; Zhang Chun; Chi Baoyong; Wang Zhihua

    2009-01-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  12. 2D and 3D CMOS MAPS with high performance pixel-level signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Traversi, Gianluca, E-mail: gianluca.traversi@unibg.i [University of Bergamo and INFN Pavia, Via Marconi 5, Dalmine 24044 (Italy); Gaioni, Luigi; Manghisoni, Massimo [University of Bergamo and INFN Pavia, Via Marconi 5, Dalmine 24044 (Italy); Ratti, Lodovico [University of Pavia and INFN Pavia (Italy); Re, Valerio [University of Bergamo and INFN Pavia, Via Marconi 5, Dalmine 24044 (Italy)

    2011-02-01

    Deep N-well (DNW) MAPS have been developed in the last few years with the aim of building monolithic sensors with similar functionalities as hybrid pixels systems. These devices have been fabricated in a planar (2D) 130 nm CMOS technology. The triple-well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. This paper intends to discuss the design features and measurement results of the last prototype (Apsel5T chip) recently fabricated in a 2D 130 nm CMOS technology. Recent advances in microelectronics industry have made 3D integrated circuits an option for High Energy Physics experiments. A 3D version of the Apsel5T chip has been designed in a 130 nm CMOS, two-layer, vertically integrated technology. The main features of this new 3D monolithic detector are presented in this paper.

  13. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Energy Technology Data Exchange (ETDEWEB)

    Gao Tongqiang [Department of Electronics, Tsinghua University, Beijing 100084 (China); Zhang Chun; Chi Baoyong; Wang Zhihua, E-mail: gtq03@mails.tsinghua.edu.c [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2009-06-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-mum CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  14. A Capacitor-Free, Fast Transient Response Linear Voltage Regulator In a 180nm CMOS

    DEFF Research Database (Denmark)

    Deleuran, Alexander N.; Lindbjerg, Nicklas; Pedersen, Martin K.;

    2015-01-01

    A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 µm CMOS process. The design has a low component count and is tailored for system-on-chip integration...

  15. Structured Analog CMOS Design

    CERN Document Server

    Stefanovic, Danica

    2008-01-01

    Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

  16. Development of radiation hard CMOS active pixel sensors for HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Pernegger, Heinz, E-mail: heinz.pernegger@cern.ch

    2016-07-11

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  17. Planar CMOS analog SiPMs: design, modeling, and characterization

    Science.gov (United States)

    Zou, Yu; Villa, Federica; Bronzi, Danilo; Tisa, Simone; Tosi, Alberto; Zappa, Franco

    2015-11-01

    Silicon photomultipliers (SiPMs) are large area detectors consisting of an array of single-photon-sensitive microcells, which make SiPMs extremely attractive to substitute the photomultiplier tubes in many applications. We present the design, fabrication, and characterization of analog SiPMs in standard planar 0.35 μm CMOS technology, with about 1 mm × 1 mm total area and different kinds of microcells, based on single-photon avalanche diodes with 30 μm diameter reaching 21.0% fill-factor (FF), 50 μm diameter (FF = 58.3%) or 50 μm square active area with rounded corner of 5 μm radius (FF = 73.7%). We also developed the electrical SPICE model for CMOS SiPMs. Our CMOS SiPMs have 25 V breakdown voltage, in line with most commercial SiPMs and higher gain (8.8 × 106, 13.2 × 106, and 15.0 × 106, respectively). Although dark count rate density is slightly higher than state-of-the-art analog SiPMs, the proposed standard CMOS processing opens the feasibility of integration with active electronics, for switching hot pixels off, drastically reducing the overall dark count rate, or for further on-chip processing.

  18. CMOS image sensors as an efficient platform for glucose monitoring.

    Science.gov (United States)

    Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

    2013-10-07

    Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications.

  19. An Evolutionary Transition of conventional n MOS VLSI to CMOS considering Scaling, Low Power and Higher Mobility

    Directory of Open Access Journals (Sweden)

    Md Mobarok Hossain Rubel

    2016-07-01

    Full Text Available This paper emphasizes on the gradual revolution of CMOS scaling by delivering the modern concepts of newly explored device structures and new materials. After analyzing the improvements in sources, performance of CMOS technology regarding conventional semiconductor devices has been thoroughly discussed. This has been done by considering the significant semiconductor evolution devices like metal gate electrode, double gate FET, FinFET, high dielectric constant (high k and strained silicon FET. Considering the power level while scaling, the paper showed how nMOS VLSI chips have been gradually replaced by CMOS aiming for the reduction in the growing power of VLSI systems.

  20. Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

    Science.gov (United States)

    Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.; Ackland, B.; Dickinson, A.; Eid, E.; Inglis, D.

    1994-01-01

    This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.

  1. Micromachined high-performance RF passives in CMOS substrate

    Science.gov (United States)

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-11-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications.

  2. Electrothermal frequency references in standard CMOS

    CERN Document Server

    Kashmiri, S Mahdi

    2013-01-01

    This book describes an alternative method of accurate on-chip frequency generation in standard CMOS IC processes. This method exploits the thermal-diffusivity of silicon, the rate at which heat diffuses through a silicon substrate.  This is the first book describing thermal-diffusivity-based frequency references, including the complete theoretical methodology supported by practical realizations that prove the feasibility of the method.  Coverage also includes several circuit and system-level solutions for the analog electronic circuit design challenges faced.   ·         Surveys the state-of-the-art in all-silicon frequency references; ·         Examines the thermal properties of silicon as a solution for the challenge of on-chip accurate frequency generation; ·         Uses simplified modeling approaches that allow an electronics engineer easily to simulate the electrothermal elements; ·         Follows a top-down methodology in circuit design, in which system-level des...

  3. Application of CMOS charge-sensitive preamplifier in triple-GEM detector

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    Among the various micro-pattern gas detectors (MPGD) that are available, the gas electron multiplier (GEM) detector is an attractive gas detector that has been used in particle physics experiments. However the GEM detector usually needs thousands of preamplifier units for its large number of micro-pattern readout strips or pads,which leads to considerable difficulties and complexities for front end electronics (FEE). Nowadays, by making use of complementary metal-oxide semiconductor (CMOS)-based application specific integrated circuit (ASIC), it is feasible to integrate hundreds of preamplifier units and other signal process circuits in a small-sized chip, which can be bound to the readout strips or pads of a micro-pattern particle detector (MPPD). Therefore, CMOS ASIC may provide an ideal solution to the readout problem of MPPD. In this article, a triple GEM detector is constructed and one of its readout strips is connected to a CMOS charge-sensitive preamplifier chip. The chip was exposed to an 55Fe source of 5.9 keV X-ray, and the amplitude spectrum of the chip was tested, and it was found that the energy resolution was approximately 27%, which indicates that the chip can be used in triple GEM detectors.

  4. A CMOS Morlet Wavelet Generator

    Directory of Open Access Journals (Sweden)

    A. I. Bautista-Castillo

    2017-04-01

    Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

  5. Non-invasive monitoring and control in silicon photonics by CMOS integrated electronics

    CERN Document Server

    Grillanda, Stefano; Morichetti, Francesco; Ciccarella, Pietro; Annoni, Andrea; Ferrari, Giorgio; Strain, Michael; Sorel, Marc; Sampietro, Marco; Melloni, Andrea

    2014-01-01

    As photonics breaks away from today's device level toward large scale of integration and complex systems-on-a-chip, concepts like monitoring, control and stabilization of photonic integrated circuits emerge as new paradigms. Here, we show non-invasive monitoring and feedback control of high quality factor silicon photonics resonators assisted by a transparent light detector directly integrated inside the cavity. Control operations are entirely managed by a CMOS microelectronic circuit, hosting many parallel electronic read-out channels, that is bridged to the silicon photonics chip. Advanced functionalities, such as wavelength tuning, locking, labeling and swapping are demonstrated. The non-invasive nature of the transparent monitor and the scalability of the CMOS read-out system offer a viable solution for the control of arbitrarily reconfigurable photonic integrated circuits aggregating many components on a single chip.

  6. A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

    Science.gov (United States)

    Smith, Edwyn D.

    1991-01-01

    Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

  7. Beyond CMOS: heterogeneous integration of III-V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems.

    Science.gov (United States)

    Kazior, Thomas E

    2014-03-28

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III-V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III-V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III-V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications.

  8. Beyond CMOS: heterogeneous integration of III–V devices, RF MEMS and other dissimilar materials/devices with Si CMOS to create intelligent microsystems

    Science.gov (United States)

    Kazior, Thomas E.

    2014-01-01

    Advances in silicon technology continue to revolutionize micro-/nano-electronics. However, Si cannot do everything, and devices/components based on other materials systems are required. What is the best way to integrate these dissimilar materials and to enhance the capabilities of Si, thereby continuing the micro-/nano-electronics revolution? In this paper, I review different approaches to heterogeneously integrate dissimilar materials with Si complementary metal oxide semiconductor (CMOS) technology. In particular, I summarize results on the successful integration of III–V electronic devices (InP heterojunction bipolar transistors (HBTs) and GaN high-electron-mobility transistors (HEMTs)) with Si CMOS on a common silicon-based wafer using an integration/fabrication process similar to a SiGe BiCMOS process (BiCMOS integrates bipolar junction and CMOS transistors). Our III–V BiCMOS process has been scaled to 200 mm diameter wafers for integration with scaled CMOS and used to fabricate radio-frequency (RF) and mixed signals circuits with on-chip digital control/calibration. I also show that RF microelectromechanical systems (MEMS) can be integrated onto this platform to create tunable or reconfigurable circuits. Thus, heterogeneous integration of III–V devices, MEMS and other dissimilar materials with Si CMOS enables a new class of high-performance integrated circuits that enhance the capabilities of existing systems, enable new circuit architectures and facilitate the continued proliferation of low-cost micro-/nano-electronics for a wide range of applications. PMID:24567473

  9. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  10. Comparators in nanometer CMOS technology

    CERN Document Server

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  11. Contact CMOS imaging of gaseous oxygen sensor array.

    Science.gov (United States)

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3](2+)) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  12. Low Power CMOS Analog Multiplier

    Directory of Open Access Journals (Sweden)

    Shipra Sachan

    2015-12-01

    Full Text Available In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it consumes only 31.8µW quiescent power and 110MHZ bandwidth.

  13. Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

    Science.gov (United States)

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-04-19

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

  14. Label free sensing of creatinine using a 6 GHz CMOS near-field dielectric immunosensor.

    Science.gov (United States)

    Guha, S; Warsinke, A; Tientcheu, Ch M; Schmalz, K; Meliani, C; Wenger, Ch

    2015-05-07

    In this work we present a CMOS high frequency direct immunosensor operating at 6 GHz (C-band) for label free determination of creatinine. The sensor is fabricated in standard 0.13 μm SiGe:C BiCMOS process. The report also demonstrates the ability to immobilize creatinine molecules on a Si3N4 passivation layer of the standard BiCMOS/CMOS process, therefore, evading any further need of cumbersome post processing of the fabricated sensor chip. The sensor is based on capacitive detection of the amount of non-creatinine bound antibodies binding to an immobilized creatinine layer on the passivated sensor. The chip bound antibody amount in turn corresponds indirectly to the creatinine concentration used in the incubation phase. The determination of creatinine in the concentration range of 0.88-880 μM is successfully demonstrated in this work. A sensitivity of 35 MHz/10 fold increase in creatinine concentration (during incubation) at the centre frequency of 6 GHz is gained by the immunosensor. The results are compared with a standard optical measurement technique and the dynamic range and sensitivity is of the order of the established optical indication technique. The C-band immunosensor chip comprising an area of 0.3 mm(2) reduces the sensing area considerably, therefore, requiring a sample volume as low as 2 μl. The small analyte sample volume and label free approach also reduce the experimental costs in addition to the low fabrication costs offered by the batch fabrication technique of CMOS/BiCMOS process.

  15. Dielectrophoretic lab-on-CMOS platform for trapping and manipulation of cells.

    Science.gov (United States)

    Park, Kyoungchul; Kabiri, Shideh; Sonkusale, Sameer

    2016-02-01

    Trapping and manipulation of cells are essential operations in numerous studies in biology and life sciences. We discuss the realization of a Lab-on-a-Chip platform for dielectrophoretic trapping and repositioning of cells and microorganisms on a complementary metal oxide semiconductor (CMOS) technology, which we define here as Lab-on-CMOS (LoC). The LoC platform is based on dielectrophoresis (DEP) which is the force experienced by any dielectric particle including biological entities in non-uniform AC electrical field. DEP force depends on the permittivity of the cells, its size and shape and also on the permittivity of the medium and therefore it enables selective targeting of cells based on their phenotype. In this paper, we address an important matter that of electrode design for DEP for which we propose a three-dimensional (3D) octapole geometry to create highly confined electric fields for trapping and manipulation of cells. Conventional DEP-based platforms are implemented stand-alone on glass, silicon or polymers connected to external infrastructure for electronics and optics, making it bulky and expensive. In this paper, the use of CMOS as a platform provides a pathway to truly miniaturized lab-on-CMOS or LoC platform, where DEP electrodes are designed using built-in multiple metal layers of the CMOS process for effective trapping of cells, with built-in electronics for in-situ impedance monitoring of the cell position. We present electromagnetic simulation results of DEP force for this unique 3D octapole geometry on CMOS. Experimental results with yeast cells validate the design. These preliminary results indicate the promise of using CMOS technology for truly compact miniaturized lab-on-chip platform for cell biotechnology applications.

  16. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  17. A photovoltaic-driven and energy-autonomous CMOS implantable sensor.

    Science.gov (United States)

    Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

    2012-08-01

    An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest μW's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-μW integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes.

  18. Direct detection in Transmission Electron Microscopy with a 5{mu}m pitch CMOS pixel sensor

    Energy Technology Data Exchange (ETDEWEB)

    Contarato, Devis, E-mail: DContarato@lbl.go [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Denes, Peter; Doering, Dionisio; Joseph, John; Krieger, Brad [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States)

    2011-04-11

    This paper presents the characterization of a CMOS monolithic pixel sensor prototype optimized for direct detection in Transmission Electron Microscopy (TEM). The sensor was manufactured in a deep-submicron commercial CMOS process and features pixels of 5{mu}m pitch. Different pixel architectures have been implemented in the test chip, and the best performing architecture has been selected from a series of tests performed with 300 keV electrons. Irradiation tests to high electron doses have also been performed in order to estimate device lifetime.

  19. Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

    OpenAIRE

    2016-01-01

    We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency) CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to redu...

  20. CMOS image sensor with contour enhancement

    Science.gov (United States)

    Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

    2010-10-01

    Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

  1. Single event effects in 0.18μm CMOS image sensors

    Science.gov (United States)

    Rushton, Joseph E.; Stefanov, Konstantin D.; Holland, Andrew D.; Bugnet, Henri; Mayer, Frederic; Cordrey-Gale, Matthew; Endicott, James

    2016-08-01

    CMOS image sensors are widely used on Earth and are becoming increasingly favourable for use in space. Advantages, such as low power consumption, and ever-improving imaging peformance make CMOS an attractive option. The ability to integrate camera functions on-chip, such as biasing and sequencing, simplifies designing with CMOS sensors and can improve system reliability. One potential disadvantage to the use of CMOS is the possibility of single event effects, such as single event latchup (SEL), which can cause malfunctions or even permanent destruction of the sensor. These single event effects occur in the space environment due to the high levels of radiation incident on the sensor. This work investigates the ocurrence of SEL in CMOS image sensors subjected to heavy-ion irradiation. Three devices are investigated, two of which have triple-well doping implants. The resulting latchup cross-sections are presented. It is shown that using a deep p well on 18 μm epitaxial silicon increases the radiation hardness of the sensor against latchup. The linear energy transfer (LET) threshold for latchup is increased when using this configuration. Our findings suggest deep p wells can be used to increase the radiation tolerance of CMOS image sensors for use in future space missions.

  2. Design and Fabrication of Complementary Metal-Oxide-Semiconductor Sensor Chip for Electrochemical Measurement

    Science.gov (United States)

    Yamazaki, Tomoyuki; Ikeda, Takaaki; Kano, Yoshiko; Takao, Hidekuni; Ishida, Makoto; Sawada, Kazuaki

    2010-04-01

    An electrochemical sensor has been developed on a single chip in which potentiostat and sensor electrodes are integrated. Sensor chips were fabricated using 5.0 µm complementary metal-oxide-semiconductor (CMOS) technology. All processes including the CMOS process, postprocessing for fabricating sensor electrodes and passivation layers, and packaging were performed at Toyohashi University of Technology. The integration makes it possible to measure electrochemical signals without having to use a bulky external electrochemical system. The potential between the working electrode and the reference electrode was controlled using an on-chip potentiostat composed of CMOS transistors. The chip characteristics were verified by electrochemical measurement, namely, by cyclic voltammetry. Potassium ferricyanide solution was measured to obtain results that fit well to the theoretical formula. A clear proportional relationship between peak height and the concentration of the sample solution was obtained using the proposed sensor chip, and the dynamic range obtained was 0.10 to 8.0 mM.

  3. Low-power high-accuracy micro-digital sun sensor by means of a CMOS image sensor

    NARCIS (Netherlands)

    Xie, N.; Theuwissen, A.J.P.

    2013-01-01

    A micro-digital sun sensor (μDSS) is a sun detector which senses a satellite’s instant attitude angle with respect to the sun. The core of this sensor is a system-on-chip imaging chip which is referred to as APS+. The APS+ integrates a CMOS active pixel sensor (APS) array of 368×368  pixels , a 12-b

  4. Measurements of Si Hybrid CMOS X-Ray Detector Characteristics

    CERN Document Server

    Bongiorno, Stephen D; Burrows, David N; Cook, Robert; Bai, Yibin; Farris, Mark

    2009-01-01

    The development of Hybrid CMOS Detectors (HCDs) for X-Ray telescope focal planes will place them in con- tention with CCDs on future satellite missions due to their faster frame rates, flexible readout scenarios, lower power consumption, and inherent radiation hardness. CCDs have been used with great success on the current generation of X-Ray telescopes (e.g. Chandra, XMM, Suzaku, and Swift). However their bucket-brigade read-out architecture, which transfers charge across the chip with discrete component readout electronics, results in clockrate limited readout speeds that cause pileup (saturation) of bright sources and an inherent susceptibility to radiation induced displacement damage that limits mission lifetime. In contrast, HCDs read pixels with low power, on-chip multiplexer electronics in a random access fashion. Faster frame rates achieved with multi-output readout design will allow the next generation's larger effective area telescopes to observe bright sources free of pileup. Radiation damaged latt...

  5. New CMOS Compatible Platforms for Integrated Nonlinear Optical Signal Processing

    CERN Document Server

    Moss, D J

    2014-01-01

    Nonlinear photonic chips have succeeded in generating and processing signals all-optically with performance far superior to that possible electronically - particularly with respect to speed. Although silicon-on-insulator has been the leading platform for nonlinear optics, its high two-photon absorption at telecommunications wavelengths poses a fundamental limitation. This paper reviews some of the recent achievements in CMOS-compatible platforms for nonlinear optics, focusing on amorphous silicon and Hydex glass, highlighting their potential future impact as well as the challenges to achieving practical solutions for many key applications. These material systems have opened up many new capabilities such as on-chip optical frequency comb generation and ultrafast optical pulse generation and measurement.

  6. CMOS capacitive biosensors for highly sensitive biosensing applications.

    Science.gov (United States)

    Chang, An-Yu; Lu, Michael S-C

    2013-01-01

    Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

  7. A CMOS frequency generation module for 60-GHz applications

    Institute of Scientific and Technical Information of China (English)

    Zhou Chunyuan; Zhang Lei; Wang Hongrui; Qian He

    2012-01-01

    A frequency generation module for 60-GHz transceivers and phased array systems is presented in this paper.It is composed of a divide-by-2 current mode logic divider (CM L) and a doubler in push-push configuration.Benefiting from the CML structure and push-push configuration,the proposed frequency generation module has a wide operating frequency range to cover process,voltage,and temperature variation.It is implemented in a 90-nm CMOS process,and occupies a chip area of 0.64 × 0.65 mm2 including pads.The measurement results show that the designed frequency generation module functions properly with input frequency over 15 GHz to 25 GHz.The whole chip dissipates 12.1 mW from a 1.2-V supply excluding the output buffers.

  8. Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor

    Directory of Open Access Journals (Sweden)

    Fang Tang

    2014-01-01

    Full Text Available Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μm CMOS technology. The chip area of the proposed ADC is 7 μm × 500 μm. The measurement results show that the energy efficiency figure-of-merit (FOM of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μm2·cycles/sample.

  9. Two-step single slope/SAR ADC with error correction for CMOS image sensor.

    Science.gov (United States)

    Tang, Fang; Bermak, Amine; Amira, Abbes; Amor Benammar, Mohieddine; He, Debiao; Zhao, Xiaojin

    2014-01-01

    Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μ m CMOS technology. The chip area of the proposed ADC is 7 μ m × 500 μ m. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k  μ m(2) · cycles/sample.

  10. Low noise CMOS readout for CdZnTe detector arrays

    Energy Technology Data Exchange (ETDEWEB)

    Jakobson, C.G.; Asa, G.; Lev, S. Bar; Nemirovsky, Y. E-mail: nemirov@ee.technion.ac.il

    1999-06-01

    A low noise CMOS readout for CdTe and CdZnTe X- and gamma-ray detector arrays has been designed and implemented in the CMOS 2 {mu}m low noise analog process provided by the multi-chip program of Metal Oxide Semiconductor Implementation Service. The readout includes CMOS low noise charge sensitive preamplifier and a multiplexed semi-Gaussian pulse shaper. Thus, each detector has a dedicated charge sensitive preamplifier that integrates its signal, while a single shaping amplifier shapes the pulses after the multiplexer. Low noise and low-power operation are achieved by optimizing the input transistor of the charge sensitive preamplifier. Two optimization criteria are used to reduce noise. The first criterion is based on capacitance matching between the input transistor and the detector. The second criterion is based on bandwidth optimization, which is obtained by tailoring the shaper parameters to the particular noise mechanisms of the MOS transistor and the CdZnTe detector. Furthermore, the multiplexing function incorporated in the shaper provides low power and reduces chip area. The system is partitioned into a chip containing the charge amplifiers and a chip containing the semi-Gaussian pulse shaper and multiplexer. This architecture minimizes coupling from multiplexer switches as well as shaper output to the input of the charge sensitive preamplifiers.

  11. Multiband CMOS sensor simplify FPA design

    Science.gov (United States)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  12. Large area CMOS image sensors

    Science.gov (United States)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  13. CMOS bulk-metal design handbook

    Science.gov (United States)

    Edge, T. M.

    1978-01-01

    User's guide describes techniques for generating precision mask artwork for complex CMOS integrated circuits, starting from logic diagram. Techniques are based on standard-cell approach. Guide also includes user guidelines for designing efficient CMOS arrays.

  14. Noise sources and noise suppression in CMOS imagers

    Science.gov (United States)

    Pain, Bedabrata; Cunningham, Thomas J.; Hancock, Bruce R.

    2004-01-01

    Mechanisms for noise coupling in CMOS imagers are complex, since unlike a CCD, a CMOS imager has to be considered as a full digital-system-on-a-chip, with a highly sensitive front-end. In this paper, we analyze the noise sources in a photodiode CMOS imager, and model their propagation through the signal chain to determine the nature and magnitude of noise coupling. We present methods for reduction of noise, and present measured data to show their viability. For temporal read noise reduction, we present pixel signal chain design techniques to achieve near 2 electrons read noise. We model the front-end reset noise both for conventional photodiode and CTIA type of pixels. For the suppression of reset noise, we present a column feedback-reset method to reduce reset noise below 6 electrons. For spatial noise reduction, we present the design of column signal chain that suppresses both spatial noise and power supply coupling noise. We conclude by identifying problems in low-noise design caused by dark current spatial distribution.

  15. Low voltage electron multiplying CCD in a CMOS process

    Science.gov (United States)

    Dunford, Alice; Stefanov, Konstantin; Holland, Andrew

    2016-07-01

    Low light level and high-speed image sensors as required for space applications can suffer from a decrease in the signal to noise ratio (SNR) due to the photon-starved environment and limitations of the sensor's readout noise. The SNR can be increased by the implementation of Time Delay Integration (TDI) as it allows photoelectrons from multiple exposures to be summed in the charge domain with no added noise. Electron Multiplication (EM) can further improve the SNR and lead to an increase in device performance. However, both techniques have traditionally been confined to Charge Coupled Devices (CCD) due to the efficient charge transfer required. With the increase in demand for CMOS sensors with equivalent or superior functionality and performance, this paper presents findings from the characterisation of a low voltage EMCCD in a CMOS process using advanced design features to increase the electron multiplying gain. By using the CMOS process, it is possible to increase chip integration and functionality and achieve higher readout speeds and reduced pixel size. The presented characterisation results include analysis of the photon transfer curve, the dark current, the electron multiplying gain and analysis of the parameters' dependence on temperature and operating voltage.

  16. Custom CMOS Reed Solomon coder for the Hubble Space Telescope

    Science.gov (United States)

    Whitaker, S.; Cameron, K.; Owsley, P.; Maki, G.

    1990-01-01

    A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.

  17. HV-CMOS detectors in BCD8 technology

    Science.gov (United States)

    Andreazza, A.; Castoldi, A.; Ceriale, V.; Chiodini, G.; Citterio, M.; Darbo, G.; Gariano, G.; Gaudiello, A.; Guazzoni, C.; Joshi, A.; Liberali, V.; Passadore, S.; Ragusa, F.; Ruscino, E.; Sbarra, C.; Shrimali, H.; Sidoti, A.; Stabile, A.; Yadav, I.; Zaffaroni, E.

    2016-11-01

    This paper presents the first pixel detector realized using the BCD8 technology of STMicroelectronics. The BCD8 is a 160 nm process with bipolar, CMOS and DMOS devices; mainly targeted for an automotive application. The silicon particle detector is realized as a pixel sensor diode with a dimension of 250 × 50 μm2. To support the signal sensitivity of pixel diode, the circuit simulations have been performed with a substrate voltage of 50 V. The analog signal processing circuitry and the digital operation of the circuit is designed with the supply voltage of 1.8 V. Moreover, an analog processing part of the pixel detector circuit is confined in a unit pixel (diode sensor) to achieve 100 % fill factor. As a first phase of the design, an array of 8 pixels and 4 passive diodes have been designed and measured experimentally. The entire analog circuitry including passive diodes is implemented in a single chip. This chip has been tested experimentally with 70 V voltage capability, to evaluate its suitability. The sensor on a 125 Ωcm resistivity substrate has been characterized in the laboratory. The CMOS sensor realizes a depleted region of several tens of micrometer. The characterization shows a uniform breakdown at 70 V before irradiation and an approximate capacitance of 80 fF at 50 V of reverse bias voltage. The response to ionizing radiation is tested using radioactive sources and an X-ray tube.

  18. An arrayed accelerometer device of a wide range of detection for integrated CMOS-MEMS technology

    Science.gov (United States)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-02-01

    This paper reports the design and experimental results of an arrayed accelerometer device in 3 × 3 format that can detect wide range of acceleration between 1G and 20G (1G = 9.8 m/s2). Implemented in a single chip has been performed by gold electroplating for integrated complementary metal oxide semiconductor-microelectromechanical systems (CMOS-MEMS) technology. An equivalent circuit of a MEMS accelerometer has been developed with an electrical circuit simulator to demonstrate the mixed-behavior of the arrayed sensor device and sensing CMOS circuits. Mechanical and electrical crosstalk between the arrayed elements is analyzed on the electrical field distributions. Experimental results show that the resonant frequency and readout capacitance as a function of applied acceleration have been well explained by the results of the multi-physics simulation. As a result, it is confirmed that the proposed device is applicable to an integrated CMOS-MEMS arrayed accelerometer.

  19. A novel monolithic ultraviolet image sensor based on a standard CMOS process

    Institute of Scientific and Technical Information of China (English)

    Li Guike; Feng Peng; Wu Nanjian

    2011-01-01

    We present a monolithic ultraviolet (UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists ofa CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16 × 16 image sensor prototype chip is implemented in a 0.18 μm standard CMOS logic process.The pixel and image sensor were measured.Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.

  20. Design of Transmission Gate VCO and Dynamic PFD for Low Power CMOS PLL

    Science.gov (United States)

    Yuan, S. C.

    2008-11-01

    To realize the high speed and low power CMOS PLL(Phase Locked Loop), the new circuits of VCO and PFD is designed in transistor level. In the VCO, the high speed and low power is realized using transmission-gate(TG) with an adaptive delay cell and low supply sensitivity. This delay cell has a built-in compensation circuit that senses and corrects the delay variation caused by supply fluctuation. And in the PFD, low power and small chip area is realized with the dynamic inverter. A fully CMOS PLL using these components has been designed based 0.6μm CMOS technology and its SPICE model. SPICE simulation results show that at 2.5V supply voltage, the designed PLL can operate over 1000MHz and dissipate power less than 50mW.

  1. Design and Implementation of Area Optimized, Low Complexity CMOS 32nm Technology Based NCO

    Directory of Open Access Journals (Sweden)

    Miss. Amruta Upase

    2017-05-01

    Full Text Available A numerically controlled oscillator (NCO is a digital signal generator which is a very important block in many Digital Communication Systems such as Software Defined Radios, Digital Radio set and Modems, Down/Up converters for Cellular and PCS base stations etc. NCO creates a synchronous, discrete-time, discrete-valued representation of a sinusoidal waveform. This paper implements the development and design of CMOS look up Table based numerically controlled oscillator which improves the performance, reduces the power & area requirement. The design is implemented with CMOS 32 nm Technology with Microwind 3.8 software tool. In addition, it can be used for analog circuit also enables the integration of complete system on chip. This paper also describes the design of a NCO which is of contemporary nature with reasonable speed, resolution and linearity with lower power, low area. For all about Pre Layout simulation has been realized using 32nm CMOS process Technology.

  2. A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

    Science.gov (United States)

    Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

    2016-08-01

    This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

  3. Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology Using SPICE

    Directory of Open Access Journals (Sweden)

    Mugdha Sathe

    2014-07-01

    Full Text Available According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.

  4. Real time image processing with an analog vision chip system.

    Science.gov (United States)

    Kameda, S; Honda, A; Yagi, T

    1999-10-01

    A linear analog network model is proposed to characterize the function of the outer retinal circuit in terms of the standard regularization theory. Inspired by the function and the architecture of the model, a vision chip has been designed using analog CMOS Very Large Scale Integrated circuit technology. In the chip, sample/hold amplifier circuits are incorporated to compensate for statistic transistor mismatches. Accordingly, extremely low noise outputs were obtained from the chip. Using the chip and a zero-crossing detector, edges of given images were effectively extracted in indoor illumination.

  5. A CMOS image sensor with draining only modulation pixels for fluorescence lifetime imaging

    Science.gov (United States)

    Li, Zhuo; Yasutomi, Keita; Takasawa, Taishi; Itoh, Shinya; Kawahito, Shoji

    2011-03-01

    Fluorescence lifetime imaging is becoming a powerful tool in biology. A charge-domain CMOS Fluorescence Lifetime Imaging Microscopy (FLIM) chip using a pinned photo diode (PPD) and the pinned storage diode (PSD) with different depth of potential wells has been previously developed by the authors. However, a transfer gate between PPD and PSD causes charge transfer noise due to traps at the channel surface. This paper presents a time-resolved CMOS image sensor with draining only modulation pixels for fluorescence lifetime imaging, which removes the transfer gate between PPD and PSD. The time windowing is done by draining with a draining gate only, which is attached along the carrier path from PPD to PSD. This allows us to realize a trapping less charge transfer between PPD and PSD, leading to a very low-noise time-resolved signal detection. A video-rate CMOS FLIM chip has been fabricated using 0.18μm standard CMOS pinned diode image sensor process. The pixel consists of a PPD, a PSD, a charge draining gate (TD), a readout transfer gate (TX) between the PSD and the floating diffusion (FD), a reset transistor and a source follower amplifier transistor. The pixel array has 200(Row) x 256(Column) pixels and the pixel pitch is 7.5μm. Fundamental characteristics of the implemented CMOS FLIM chip are measured. The signal intensity of the PSD as a function of the TD gate voltage is also measured. The ratio of the signal for the TD off to the signal for the TD on is 212 : 1.

  6. Rapid detection of aflatoxigenic Aspergillus sp. in herbal specimens by a simple, bendable, paper-based lab-on-a-chip.

    Science.gov (United States)

    Chaumpluk, Piyasak; Plubcharoensook, Pattra; Prasongsuk, Sehanat

    2016-06-01

    Postharvest herbal product contamination with mycotoxins and mycotoxin-producing fungi represents a potentially carcinogenic hazard. Aspergillus flavus is a major cause of this issue. Available mold detection methods are PCR-based and rely heavily on laboratories; thus, they are unsuitable for on-site monitoring. In this study, a bendable, paper-based lab-on-a-chip platform was developed to rapidly detect toxigenic Aspergillus spp. DNA. The 3.0-4.0 cm(2) chip is fabricated using Whatman™ filter paper, fishing line and a simple plastic lamination process and has nucleic acid amplification and signal detection components. The Aspergillus assay specifically amplifies the aflatoxin biosynthesis gene, aflR, using loop-mediated isothermal amplification (LAMP); hybridization between target DNA and probes on blue silvernanoplates (AgNPls) yields colorimetric results. Positive results are indicated by the detection pad appearing blue due to dispersed blue AgNPls; negative results are indicated by the detection pad appearing colorless or pale yellow due to probe/target DNA hybridization and AgNPls aggregation. Assay completion requires less than 40 min, has a limit of detection (LOD) of 100 aflR copies, and has high specificity (94.47%)and sensitivity (100%). Contamination was identified in 14 of 32 herbal samples tested (43.75%). This work demonstrates the fabrication of a simple, low-cost, paper-based lab-on-a-chip platform suitable for rapid-detection applications.

  7. Fast Hopping Frequency Generation in Digital CMOS

    CERN Document Server

    Farazian, Mohammad; Gudem, Prasad S

    2013-01-01

    Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.   Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power s...

  8. 一种基于CMOS工艺的高稳定片内振荡器的设计%Design of a on-chip CMOS Oscillator with High Precision

    Institute of Scientific and Technical Information of China (English)

    陈崴; 施隆照

    2011-01-01

    A kind of on-chip oscillator with simple structure and is easy to integrate was designed usingconstant current source charge-discharge and temperature compensation technologies .The key element of the circuit is a temperature independent bandgap current source generated from the superposition of PTA-T and NTAT currents .A capacitance was charged and discharged accurately by the current source whil-e the difference between the High threshold and Low threshold of comparator was designed to be NTA-T to compensate the PTAT of capacitance in order to weaken the impact of temperature to the period of oscillation, generating precious rectangle wave oscillation with duty ratio adjustable. This design is i-mplemented in HHNEC 0.35 μm process. Spectre simulation shows up that in standard situation this mod-ule offers A 6.321MHz clock signal, and it' s temperature coefficient is only 42ppm/℃ from-20℃ to 100℃.%采用恒流源充放电及温度补偿技术设计了一款结构简单、易于集成的片内振荡器。该模块的核心为利用带隙基准电流源产生一路零温度系数电流,并用该电流源对电容进行充放电;设置比较器的高低阈值电压的差值为负温度系数与电容的正温度系数相互补偿,尽可能减弱温度对振荡周期的影响,产生高稳定且占空比可调的矩形波。采用华虹NEC0.35μmCZ6H工艺设计,经CadenceSpectre软件仿真表明标准状况下该模块振荡频率为6.321MHz,在-20到100℃的温度区间内其温度系数仅为42ppm/℃。

  9. Readout circuit design of the retina-like CMOS image sensor

    Science.gov (United States)

    Cao, Fengmei; Song, Shengyu; Bai, Tingzhu; Cao, Nan

    2015-02-01

    Readout circuit is designed for a special retina-like CMOS image sensor. To realize the pixels timing drive and readout of the sensor, the Altera's Cyclone II FPGA is used as a control chip. The voltage of the sensor is supported by a voltage chip initialized by SPI with AVR MCU system. The analog image signal outputted by the sensor is converted to digital image data by 12-bits A/D converter ADS807 and the digital data is memorized in the SRAM. Using the Camera-link image grabber, the data stored in SRAM is transformed to image shown on PC. Experimental results show the circuit works well on retina-like CMOS timing drive and image readout and images can be displayed properly on the PC.

  10. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  11. A CMOS Switched Transconductor Mixer

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Louwsma, S.M.; Wienk, Gerhardus J.M.; Nauta, Bram

    A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled

  12. A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor

    Energy Technology Data Exchange (ETDEWEB)

    Benschneider, B.J.; Bowhill, W.J.; Cooper, E.M.; Gronowski, P.E.; Peng, V.; Pickholtz, J.D.; Samudrala, S. (Digital Equipment Corp., Hudson, MA (US)); Gavrielov, M.N. (LSI Logic Corp., Milpitas, CA (US)); Maheshwari, V.K. (AT and T Bell Labs., Allentown, PA (US))

    1989-10-01

    A 135 K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition (ADD) and subtraction (SUB) operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm ar used.

  13. Fully Integrated, Low Drop-Out Linear Voltage Regulator in 180 nm CMOS

    DEFF Research Database (Denmark)

    Yosef-Hay, Yoni; Larsen, Dennis Øland; Llimos Muntal, Pere

    2017-01-01

    . The proposed design works without the need of a decoupling capacitor connected at the output and operates with a 0-100 pF capacitive load. The design has been taped out in a 0.18 µm CMOS process. The proposed regulator has a low component count, area of 0.012 mm2 and is suitable for system-on-chip integration...

  14. A CMOS Neural Interface for a Multichannel Vestibular Prosthesis.

    Science.gov (United States)

    Hageman, Kristin N; Kalayjian, Zaven K; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A; Fridman, Gene Y; Dai, Chenkai; Pouliquen, Philippe O; Georgiou, Julio; Della Santina, Charles C; Andreou, Andreas G

    2016-04-01

    We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45±0.06 mA with durations as short as 10 μs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68-130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9-16.7 °/s for the MVP2 and 2.0-14.2 °/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference ( t-test, p=0.34), suggesting that the MVP2A achieves performance at least as good as the larger MVP2.

  15. Characterization of 4 K CMOS devices and circuits for hybrid Josephson-CMOS systems

    OpenAIRE

    Yoshikawa, Nobuyuki; Tomida, T.; Tokuda, A.; Liu, Q.; Meng, X.(Institute of High Energy Physics, Beijing, China); Whiteley, SR.; VanDuzer, T.

    2005-01-01

    Characterization and modeling of CMOS devices at 4.2 K are carried out in order to simulate low-temperature operation of CMOS circuits for Josephson-CMOS hybrid systems. CMOS devices examined in this study have been fabricated by using 0.18 mu m, 0.25 mu m, and 0.35 mu m commercial CMOS processes. Their static IN characteristics and capacitances are measured at 4.2 K to establish the low-temperature device model based on the BSIM3 SPICE model. The propagation delays of CMOS inverters measured...

  16. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Fiorini, M., E-mail: fiorini@fe.infn.it [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Andreotti, M.; Baldini, W.; Calabrese, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Carniti, P.; Cassina, L. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Cotta Ramusino, A. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Giachero, A.; Gotti, C. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Luppi, E. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Maino, M. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Malaguti, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Pessina, G. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Tomassetti, L. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy)

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10{sup 12} 1 MeV n{sub eq}/cm{sup 2} and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 10{sup 14} cm{sup −2} and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step. - Highlights: • CLARO chip capable of single-photon counting with 5 ns peaking time. • Chip irradiated up to very high neutron, proton and X-rays fluences, as expected for upgraded LHCb RICH detectors. • No significant performance degradation is observed after irradiation.

  17. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    Science.gov (United States)

    Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×1012 1 MeV neq /cm2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 1014 cm-2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  18. Towards third generation pixel readout chips

    Energy Technology Data Exchange (ETDEWEB)

    Garcia-Sciveres, M., E-mail: mgarcia-sciveres@lbl.gov; Mekkaoui, A.; Ganani, D.

    2013-12-11

    We present concepts and prototyping results towards a third generation pixel readout chip. We consider the 130 nm feature size FE-I4 chip, in production for the ATLAS IBL upgrade, to be a second generation chip. A third generation chip would have to go significantly further. A possible direction is to make the IC design generic so that different experiments can configure it to meet significantly different requirements, without the need for everybody to develop their own ASIC from the ground up. In terms of target technology, a demonstrator 500-pixel matrix containing analog front ends only (no complex functionality), was designed and fabricated in 65 nm CMOS and irradiated with protons in December 2011 and May 2012.

  19. IC chip stress during plastic package molding

    Energy Technology Data Exchange (ETDEWEB)

    Palmer, D.W.; Benson, D.A.; Peterson, D.W.; Sweet, J.N.

    1998-02-01

    Approximately 95% of the world`s integrated chips are packaged using a hot, high pressure transfer molding process. The stress created by the flow of silica powder loaded epoxy can displace the fine bonding wires and can even distort the metalization patterns under the protective chip passivation layer. In this study the authors developed a technique to measure the mechanical stress over the surface of an integrated circuit during the molding process. A CMOS test chip with 25 diffused resistor stress sensors was applied to a commercial lead frame. Both compression and shear stresses were measured at all 25 locations on the surface of the chip every 50 milliseconds during molding. These measurements have a fine time and stress resolution which should allow comparison with computer simulation of the molding process, thus allowing optimization of both the manufacturing process and mold geometry.

  20. High-performance VGA-resolution digital color CMOS imager

    Science.gov (United States)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  1. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  2. Portable design rules for bulk CMOS

    Science.gov (United States)

    Griswold, T. W.

    1982-01-01

    It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

  3. Batch Processing of CMOS Compatible Feedthroughs

    DEFF Research Database (Denmark)

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    This paper presents a technique for batch fabrication of electrical feedthroughs in CMOS wafers. The presented process is designed with specific attention on industrial applicability. The electrical feedthroughs are processed entirely by low temperature, CMOS compatible processes. Hence, the proc......This paper presents a technique for batch fabrication of electrical feedthroughs in CMOS wafers. The presented process is designed with specific attention on industrial applicability. The electrical feedthroughs are processed entirely by low temperature, CMOS compatible processes. Hence....... The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...

  4. CMOS Image Sensor with a Built-in Lane Detector.

    Science.gov (United States)

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

  5. CMOS Image Sensor with a Built-in Lane Detector

    Directory of Open Access Journals (Sweden)

    Li-Chen Fu

    2009-03-01

    Full Text Available This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC or Digital Signal Processor (DSP, the proposed imager, without extra Analog to Digital Converter (ADC circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 x 2,389.8 mm, and the package uses 40 pin Dual-In-Package (DIP. The pixel cell size is 18.45 x 21.8 mm and the core size of photodiode is 12.45 x 9.6 mm; the resulting fill factor is 29.7%.

  6. Design of A 0.5V Op-Amp Based on CMOS Inverter Using Floating Voltage Sources

    OpenAIRE

    Wang, Jun; Lee, Tuck-Yang; Kim, Dong-Gyou; Matsuoka, Toshimasa; Taniguchi, Kenji

    2008-01-01

    This letter presents a 0.5 V low-voltage op-amp in a standard 0.18 µm CMOS process for switched-capacitor circuits. Unlike other two-stage 0.5 V op-amp architectures, this op-amp consists of CMOS inverters that utilize floating voltage sources and forward body bias for obtaining high-speed operation. And two improved common-mode rejection circuits are well combined to achieve low power and chip area reduction. Simulation results indicate that the op-amp has an open-loop gain of 62 dB, and a h...

  7. Application of Ferrite Nanomaterial in RF On-Chip Inductors

    Directory of Open Access Journals (Sweden)

    Hua-Lin Cai

    2013-01-01

    Full Text Available Several kinds of ferrite-integrated on-chip inductors are presented. Ferrite nanomaterial applied in RF on-chip inductors is prepared and analyzed to show the properties of high permeability, high ferromagnetic resonance frequency, high resistivity, and low loss, which has the potential that will improve the performance of RF on-chip inductors. Simulations of different coil and ferrite nanomaterial parameters, inductor structures, and surrounding structures are also conducted to achieve the trend of gains of inductance and quality factor of on-chip inductors. By integrating the prepared ferrite magnetic nanomaterial to the on-chip inductors with different structures, the measurement performances show an obvious improvement even in GHz frequency range. In addition, the studies of CMOS compatible process to integrate the nanomaterial promote the widespread application of magnetic nanomaterial in RF on-chip inductors.

  8. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  9. CMOS Law-jitter Clock Driver Design

    OpenAIRE

    2012-01-01

    [ANGLÈS] Design of a low-jitter, low-phase noise clock driver in 40 nm CMOS technology. The work is in the field of analog integrated circuit (IC) design in nanometer CMOS technologies. [CASTELLÀ] Diseño de un circuito integrado "clock driver" de bajo jitter y bajo ruido de fase en tecnología CMOS 40 nm. El trabajo se contextualiza en el campo del diseño de circuitos integrados analógicos en tecnologías CMOS nanométricas. [CATALÀ] Disseny d'un circuit "clock driver" de baix jitter i bai...

  10. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  11. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  12. Electroabsorption modulators for CMOS compatible optical interconnects in III-V and group IV materials

    Science.gov (United States)

    Roth, Jonathan Edgar

    While electrical systems excel at information processing, photonics is useful in systems for high-bandwidth, low-loss signal transmission. As photonics technology has become increasingly widespread and has been deployed at shorter distance scales than traditional long-haul networks, it has become important to efficiently integrate photonics components with electrical integrated circuits. Optoelectronic modulators used as transmitters are an important class of device for use in optical interconnects. Many optoelectronic modulator designs use waveguides. Coupling light into waveguides requires a difficult alignment step. This dissertation will describe a number of optoelectronic modulators that do not have the tight alignment constraints associated with waveguide-based modulators. The eased alignment constraints may be important for the practical manufacturing and packaging of systems using optical interconnects. Most currently deployed photonics technologies also use substrates other than silicon and materials incompatible with CMOS manufacturing. Recently we discovered a strong quantum-confined Stark effect in Ge/SiGe quantum well structures that can be used to create efficient optoelectronic modulators on silicon substrates. Optoelectronic modulators using this technology can be fabricated with conventional CMOS foundry processes, possibly on the same chips as CMOS circuits. In this dissertation, an optical interconnect operating in the C-band will be presented. We believe this is the first such device employing an optical transmitter flip-chip bonded to silicon CMOS. A number of novel modulators will be presented, which are fabricated on silicon substrates, and employ Ge/SiGe quantum well structures. These modulators include a novel architecture known as the side-entry modulator, which is designed for monolithic integration with electronics. One side-entry modulator achieved over 3 dB of contrast in the telecommunications C-band for a voltage swing of 1V. Such a

  13. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

  14. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    Science.gov (United States)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  15. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    Science.gov (United States)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  16. A time-domain CMOS oscillator-based thermostat with digital set-point programming.

    Science.gov (United States)

    Chen, Chun-Chi; Lin, Shih-Hao

    2013-01-29

    This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC) or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs) was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-mm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 µW at a sample rate of 10 samples/s.

  17. Capacitive micropressure sensors with underneath readout circuit using a standard CMOS process

    Science.gov (United States)

    Chang, Shihchen; Dai, Chingliang; Chiou, Jinghung; Chang, Peizen

    2001-08-01

    A capacitive micropressure sensor with readout circuits on a single chip is fabricated using commercial 0.35micrometers CMOS process technology and post-processing. The main break through feature of the chip is the positioning of its readout circuits under the pressure sensor, allowing the chip to be smaller. Post-processing included anisotropic dry etching and wet etching to remove the sacrificial layer, and the use of PECVD nitride to seal the etching holes of the pressure sensor. The sacrificial layer was the metal 3 layer of the standard 0.35 micrometers CMOS process. In addition, the readout circuit is divided into analog and digital parts, with the digital part being an alternate coupled RS flip- flop with four inverters that sharpened the output wave. Moreover, the analog part is employed switched capacitor methodology. The pressure sensor contained an 8 X 8 sensing cells array, and the total area of the pressure sensor chip is 2mmx2 mm. In addition to illustrating the design and fabrication of the capacitive pressure sensor, this investigation demonstrates the simulation and testing results of the readout circuit.

  18. A Time-Domain CMOS Oscillator-Based Thermostat with Digital Set-Point Programming

    Directory of Open Access Journals (Sweden)

    Shih-Hao Lin

    2013-01-01

    Full Text Available This paper presents a time-domain CMOS oscillator-based thermostat with digital set-point programming [without a digital-to-analog converter (DAC or external resistor] to achieve on-chip thermal management of modern VLSI systems. A time-domain delay-line-based thermostat with multiplexers (MUXs was used to substantially reduce the power consumption and chip size, and can benefit from the performance enhancement due to the scaling down of fabrication processes. For further cost reduction and accuracy enhancement, this paper proposes a thermostat using two oscillators that are suitable for time-domain curvature compensation instead of longer linear delay lines. The final time comparison was achieved using a time comparator with a built-in custom hysteresis to generate the corresponding temperature alarm and control. The chip size of the circuit was reduced to 0.12 mm2 in a 0.35-mm TSMC CMOS process. The thermostat operates from 0 to 90 °C, and achieved a fine resolution better than 0.05 °C and an improved inaccuracy of ± 0.6 °C after two-point calibration for eight packaged chips. The power consumption was 30 µW at a sample rate of 10 samples/s.

  19. Reliability Considerations of ULP Scaled CMOS in Spacecraft Systems

    Science.gov (United States)

    White, Mark; MacNeal, Kristen; Cooper, Mark

    2012-01-01

    NASA, the aerospace community, and other high reliability (hi-rel) users of advanced microelectronic products face many challenges as technology continues to scale into the deep sub-micron region. Decreasing the feature size of CMOS devices not only allows more components to be placed on a single chip, but it increases performance by allowing faster switching (or clock) speeds with reduced power compared to larger scaled devices. Higher performance, and lower operating and stand-by power characteristics of Ultra-Low Power (ULP) microelectronics are not only desirable, but also necessary to meet low power consumption design goals of critical spacecraft systems. The integration of these components in such systems, however, must be balanced with the overall risk tolerance of the project.

  20. An integrated CMOS high data rate transceiver for video applications

    Science.gov (United States)

    Yaping, Liang; Dazhi, Che; Cheng, Liang; Lingling, Sun

    2012-07-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology by using a proprietary protocol, which combines the new IEEE 802.11n features such as multiple-in multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment. The RF frequencies cover from 4.9 to 5.9 GHz: the industrial, scientific and medical (ISM) band. Each RF channel bandwidth is 20 MHz. The transceiver utilizes a direct up transmitter and low-IF receiver architecture. A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration. The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

  1. CMOS-TDI detector technology for reconnaissance application

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Jung, Melanie; Sengebusch, Karsten

    2014-10-01

    The Institute of Optical Sensor Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the institute's scientific results of the leading-edge detector design CMOS in a TDI (Time Delay and Integration) architecture. This project includes the technological design of future high or multi-spectral resolution spaceborne instruments and the possibility of higher integration. DLR OS and the Fraunhofer Institute for Microelectronic Circuits and Systems (IMS) in Duisburg were driving the technology of new detectors and the FPA design for future projects, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generation of space borne sensor systems is focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large-swath and high-spectral resolution with intelligent synchronization control, fast-readout ADC (analog digital converter) chains and new focal-plane concepts opens the door to new remote-sensing and smart deep-space instruments. The paper gives an overview of the detector development status and verification program at DLR, as well as of new control possibilities for CMOS-TDI detectors in synchronization control mode.

  2. An integrated CMOS high data rate transceiver for video applications

    Institute of Scientific and Technical Information of China (English)

    Liang Yaping; Che Dazhi; Liang Cheng; Sun Lingling

    2012-01-01

    This paper presents a 5 GHz CMOS radio frequency (RF) transceiver built with 0.18 μm RF-CMOS technology hy using a proprietary protocol,which combines the new IEEE 802.11n features such as multiplein multiple-out (MIMO) technology with other wireless technologies to provide high data rate robust real-time high definition television (HDTV) distribution within a home environment.The RF frequencies cover from 4.9 to 5.9 GHz:the industrial,scientific and medical (ISM) band.Each RF channel bandwidth is 20 MHz.The transceiver utilizes a direct up transmitter and low-IF receiver architecture.A dual-quadrature direct up conversion mixer is used that achieves better than 35 dB image rejection without any on chip calibration.The measurement shows a 6 dB typical receiver noise figure and a better than 33 dB transmitter error vector magnitude (EVM) at -3 dBm output power.

  3. A Low-Cost CMOS Programmable Temperature Switch.

    Science.gov (United States)

    Li, Yunlong; Wu, Nanjian

    2008-05-15

    A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45-120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm² and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

  4. A Low-Cost CMOS Programmable Temperature Switch

    Directory of Open Access Journals (Sweden)

    Nanjian Wu

    2008-05-01

    Full Text Available A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45-120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

  5. NV-CMOS HD camera for day/night imaging

    Science.gov (United States)

    Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

    2014-06-01

    SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

  6. Solar cells on CMOS chips as energy harvesters - integration and CMOS compatibility

    NARCIS (Netherlands)

    Lu, Jiwu

    2011-01-01

    Energy harvesting is an interesting topic in the 21st century for electrical engineers from both industry and academia. It will be a core technology for autonomous wireless networks, which is the essential component of the long-lived ubiquitous computing world. There are different ways to achieve th

  7. Analysis of Leakages and Leakage Reduction Methods in UDSM CMOS VLSI Circuits.

    Directory of Open Access Journals (Sweden)

    Sagar Ekade

    2014-04-01

    Full Text Available This is the era of portable devices which need to be powered by battery. Due to scarcity of space and leakages in chips, battery life is a serious concern. As technology advances, scaling of transistor feature size and supply voltage has improved the performance, increased the transistor density and reduced the power required by the chip. The maximum power consumed by the chip is the function of its technology along with its implementation. As technology is scaling down and CMOS circuits are supplied with lower supply voltages, the static power i.e. standby leakage current becomes very crucial. In Ultra Deep-submicron regime scaling has reduced the threshold voltage and that has led to increase in leakage current in sub-threshold region and hence rise in static power dissipation. This paper presents a critical analysis of leakages and leakage reduction techniques.

  8. Pixel architectures in a HV-CMOS process for the ATLAS inner detector upgrade

    Science.gov (United States)

    Degerli, Y.; Godiot, S.; Guilloux, F.; Hemperek, T.; Krüger, H.; Lachkar, M.; Liu, J.; Orsini, F.; Pangaud, P.; Rymaszewski, P.; Wang, T.

    2016-12-01

    In this paper, design details and simulation results of new pixel architectures designed in LFoundry 150 nm high voltage CMOS process in the framework of the ATLAS high luminosity inner detector upgrade are presented. These pixels can be connected to the FE-I4 readout chip via bump bonding or glue and some of them can also be tested without a readout chip. Negative high voltage is applied to the high resistivity (> 2 kΩ .cm) substrate in order to deplete the deep n-well charge collection diode, ensuring good charge collection and radiation tolerance. In these pixels, the front-end has been implemented inside the diode using both NMOS and PMOS transistors. The pixel pitch is 50 μm × 250 μm for all pixels. These pixels have been implemented in a demonstrator chip called LFCPIX.

  9. A fully integrated 3.5 GHz CMOS differential power amplifier driver

    Science.gov (United States)

    Xiaodong, Xu; Haigang, Yang; Tongqiang, Gao; Hongfeng, Zhang

    2013-07-01

    A fully integrated CMOS differential power amplifier driver (PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements, a transmission line transformer is used as the output matching network. A differential inductance constitutes an inter-stage matching network. Meanwhile, an on chip balun realizes input matching as well as single-end to differential conversion. The PAD is fabricated in a 0.13 μm RFCMOS process. The chip size is 1.1 × 1.1 mm2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.

  10. CMOS circuits for analog signal processing

    NARCIS (Netherlands)

    Wallinga, Hans

    1988-01-01

    Design choices in CMOS analog signal processing circuits are presented. Special attention is focussed on continuous-time filter technologies. The basics of MOSFET-C continuous-time filters and CMOS Square Law Circuits are explained at the hand of a graphical MOST characteristics representation.

  11. Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

    Science.gov (United States)

    Liang, Z.; Affolder, A.; Arndt, K.; Bates, R.; Benoit, M.; Di Bello, F.; Blue, A.; Bortoletto, D.; Buckland, M.; Buttar, C.; Caragiulo, P.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hoeferkamp, M.; Hommels, L. B. A.; Huffman, B. T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, J.; Mandić, I.; Maneuski, D.; Martinez-Mckinney, F.; McMahon, S.; Meng, L.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Peric, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seidel, S.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zhang, J.; Zhu, H.

    2016-09-01

    This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

  12. Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Liang, Z., E-mail: zhijun.liang@cern.ch [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Institute of High Energy Physics, Beijing (China); Affolder, A. [University of Liverpool (United Kingdom); Arndt, K. [University of Oxford (United Kingdom); Bates, R. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Benoit, M.; Di Bello, F. [University of Geneva (Switzerland); Blue, A. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Bortoletto, D. [University of Oxford (United Kingdom); Buckland, M. [University of Liverpool (United Kingdom); CERN, European Center for Nuclear Research (Switzerland); Buttar, C. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Caragiulo, P. [SLAC National Accelerator Laboratory (United States); Das, D.; Dopke, J. [Rutherford Appleton Laboratory, Didcot (United Kingdom); Dragone, A. [SLAC National Accelerator Laboratory (United States); Ehrler, F. [Karlsruhe Institute of Technology (Germany); Fadeyev, V.; Galloway, Z.; Grabas, H. [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Gregor, I.M. [Deutsches Elektronen-Synchrotron (Germany); Grenier, P. [SLAC National Accelerator Laboratory (United States); and others

    2016-09-21

    This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

  13. Nanosecond monolithic CMOS readout cell

    Science.gov (United States)

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  14. Drop casting of stiffness gradients for chip integration into stretchable substrates

    Science.gov (United States)

    Naserifar, Naser; LeDuc, Philip R.; Fedder, Gary K.

    2017-04-01

    Stretchable electronics have demonstrated promise within unobtrusive wearable systems in areas such as health monitoring and medical therapy. One significant question is whether it is more advantageous to develop holistic stretchable electronics or to integrate mature CMOS into stretchable electronic substrates where the CMOS process is separated from the mechanical processing steps. A major limitation with integrating CMOS is the dissimilar interface between the soft stretchable and hard CMOS materials. To address this, we developed an approach to pattern an elastomeric polymer layer with spatially varying mechanical properties around CMOS electronics to create a controllable material stiffness gradient. Our experimental approach reveals that modifying the interfaces can increase the strain failure threshold up to 30% and subsequently decreases delamination. The stiffness gradient in the polymer layer provides a safe region for electronic chips to function under a substrate tensile strain up to 150%. These results will have impacts in diverse applications including skin sensors and wearable health monitoring systems.

  15. A low-noise current preamplifier in 120 nm CMOS technology

    Directory of Open Access Journals (Sweden)

    H. Uhrmann

    2008-05-01

    Full Text Available In this paper we examine the impact of deep sub-micron CMOS technology on analog circuit design with a special focus on the noise performance and the ability to design low-noise preamplifiers. To point out, why CMOS technology can grow to a key technology in low-noise and high-speed applications, various amplifier stages, applied in literature, are compared. One, that fits as a current preamplifier for low-noise applications, is the current mirror. Starting from the basic current mirror, an enhanced current preamplifier is developed, that offers low-noise and high-speed operation. The suggested chip is realized in 0.12 μm CMOS technology and needs a chip area of 100 μm×280 μm. It consumes about 15 mW at a supply voltage of 1.5 V. The presented current preamplifier has a bandwidth of 750 MHz and a gain of 36 dB. The fields of application for current preamplifiers are, for instance, charge amplifiers, amplifiers for low-voltage differential signaling (LVDS based point-to-point data links or preamplifiers for photodetectors.

  16. Development of a prototype of the Tomo-e Gozen wide-field CMOS camera

    Science.gov (United States)

    Sako, Shigeyuki; Osawa, Ryou; Takahashi, Hidenori; Kikuchi, Yuki; Doi, Mamoru; Kobayashi, Naoto; Aoki, Tsutomu; Arimatsu, Ko; Ichiki, Makoto; Ikeda, Shiro; Ita, Yoshifusa; Kasuga, Toshihiro; Kawakita, Hideyo; Kokubo, Mitsuru; Maehara, Hiroyuki; Matsunaga, Noriyuki; Mito, Hiroyuki; Mitsuda, Kazuma; Miyata, Takashi; Mori, Kiyoshi; Mori, Yuki; Morii, Mikio; Morokuma, Tomoki; Motohara, Kentaro; Nakada, Yoshikazu; Osawa, Kentaro; Okumura, Shin-ichiro; Onozato, Hiroki; Sarugaku, Yuki; Sato, Mikiya; Shigeyama, Toshikazu; Soyano, Takao; Tanaka, Masaomi; Taniguchi, Yuki; Tanikawa, Ataru; Tarusawa, Ken'ichi; Tominaga, Nozomu; Totani, Tomonori; Urakawa, Seitaro; Usui, Fumihiko; Watanabe, Junichi; Yamaguchi, Jumpei; Yoshikawa, Makoto

    2016-08-01

    The Tomo-e Gozen is an extremely wide-field optical camera for the Kiso 1.0-m Schmidt telescope. It is capable of taking consecutive frames with a field-of-view of 20 deg2 and a sub-second time-resolution, which are achieved by 84 chips of 2k×1k CMOS sensor. This camera adopts unconventional designs including a lightweight structure, a nonvacuumed and naturally-air cooled system, front-side-illuminated CMOS sensors with microlens arrays, a sensor alignment along a spherical focal plane of the telescope, and massive readout electronics. To develop technical components necessary for the Tomo-e Gozen and confirm a feasibility of its basic design, we have developed a prototype-model (PM) of the Tomo-e Gozen prior to the final-model (FM). The Tomo-e PM is equipped with eight chips of the CMOS sensor arranged in a line along the RA direction, covering a sky area of 2.0 deg2. The maximum frame rate is 2 fps. The total data production rate is 80 MByte sec-1 at 2 fps, corresponding to approximately 3 TByte night-1. After laboratory testing, we have successfully obtained consecutive movie data at 2 fps with the Tomo-e PM in the first commissioning run conducted in the end of 2015.

  17. Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

    Directory of Open Access Journals (Sweden)

    Min Yoon

    2016-01-01

    Full Text Available We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency CMOS (fT/fmax=120/140 GHz technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to reduce parasitic capacitance at the band of 24 GHz. The proposed sensor has low cost and low power dissipation since it is realized using CMOS process. The proposed sensor showed the lowest noise figure of 2.9 dB and the highest conversion gain of 40.2 dB as compared to recently reported research results. It also showed small chip size of 0.56 mm2, low power dissipation of 39.5 mW, and wide operating temperature range of −40 to +125°C.

  18. 10×10-pixel 606kS/s multi-point fluorescence correlation spectroscopy CMOS image sensor

    Science.gov (United States)

    Kagawa, Keiichiro; Takasawa, Taishi; Bo, Zhang; Seo, Min-Woong; Imai, Kaita; Yamamoto, Jotaro; Kinjo, Masataka; Terakawa, Susumu; Yasutomi, Keita; Kawahito, Shoji

    2014-03-01

    To observe molecular transport in a living cell, a high-speed CMOS image sensor for multi-point fluorescence correlation spectroscopy is developed. To achieve low-noise and high-speed simultaneously, a prototype CMOS image sensor is designed based on a complete pixel-parallel architecture and multi-channel pipelined pixel readout. The prototype chip with 10×10 effective pixels is fabricated in 0.18-μm CMOS image sensor technology. The pixel pitch and the photosensitive area are 56μm and 10μm in diameter without a microlens, respectively. In the experiment, the total sampling rate of 606kS/s is achieved. The measured average random noise is 24.9LSB, which is equivalent to about 2.5 electrons in average.

  19. 0.8 /spl mu/m CMOS implementation of weighted-order statistic image filter based on cellular neural network architecture.

    Science.gov (United States)

    Kowalski, J

    2003-01-01

    In this paper, a very large scale integration chip of an analog image weighted-order statistic (WOS) filter based on cellular neural network (CNN) architecture for real-time applications is described. The chip has been implemented in CMOS AMS 0.8 /spl mu/m technology. CNN-based filter consists of feedforward nonlinear template B operating within the window of 3 /spl times/ 3 pixels around the central pixel being filtered. The feedforward nonlinear CNN coefficients have been realized using programmable nonlinear coupler circuits. The WOS filter chip allows for processing of images with 300 pixels horizontal resolution. The resolution can be increased by cascading of the chips. Experimental results of basic circuit building blocks measurements are presented. Functional tests of the chip have been performed using a special test setup for PAL composite video signal processing. Using the setup real images have been filtered by WOS filter chip under test.

  20. CMOS integrated switching power converters

    CERN Document Server

    Villar-Pique, Gerard

    2011-01-01

    This book describes the structured design and optimization of efficient, energy processing integrated circuits. The approach is multidisciplinary, covering the monolithic integration of IC design techniques, power electronics and control theory. In particular, this book enables readers to conceive, synthesize, design and implement integrated circuits with high-density high-efficiency on-chip switching power regulators. Topics covered encompass the structured design of the on-chip power supply, efficiency optimization, IC-compatible power inductors and capacitors, power MOSFET switches and effi

  1. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  2. Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

    Science.gov (United States)

    Kim, Jong-Wan; Takao, Hidekuni; Sawada, Kazuaki; Ishida, Makoto

    2007-01-01

    This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensor systems that have been developed to monitor the motion and vital signs of humans in various environments. Integration of radio frequency transmitter (RF) technology with complementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. The essential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiral inductors for an LC resonator and an integrated antenna have been fabricated and evaluated experimentally. The fabricated RF transmitter and integrated antenna were packaged with subminiature series A (SMA) connectors, respectively. For the impedance (50 Ω) matching, a bonding wire type inductor was developed. In this paper, the design and fabrication of the bonding wire inductor for impedance matching is described. Integrated techniques for the RF transmitter by CMOS compatible processes have been successfully developed. After matching by inserting the bonding wire inductor between the on-chip integrated antenna and the VCO output, the measured emission power at distance of 5 m from RF transmitter was -37 dBm (0.2 μW).

  3. Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

    Directory of Open Access Journals (Sweden)

    Makoto Ishida

    2007-07-01

    Full Text Available This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS compatible processes for integrated smart microsensorsystems that have been developed to monitor the motion and vital signs of humans invarious environments. Integration of radio frequency transmitter (RF technology withcomplementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS microsensors is required to realize the wireless smart microsensors system. Theessential RF components such as a voltage controlled RF-CMOS oscillator (VCO, spiralinductors for an LC resonator and an integrated antenna have been fabricated and evaluatedexperimentally. The fabricated RF transmitter and integrated antenna were packaged withsubminiature series A (SMA connectors, respectively. For the impedance (50 matching,a bonding wire type inductor was developed. In this paper, the design and fabrication of thebonding wire inductor for impedance matching is described. Integrated techniques for theRF transmitter by CMOS compatible processes have been successfully developed. Aftermatching by inserting the bonding wire inductor between the on-chip integrated antennaand the VCO output, the measured emission power at distance of 5 m from RF transmitterwas -37 dBm (0.2 μW.

  4. On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

    Science.gov (United States)

    Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

    2008-01-01

    The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

  5. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    Science.gov (United States)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  6. Development of a novel pixel-level signal processing chain for fast readout 3D integrated CMOS pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Y.; Torheim, O.; Hu-Guo, C. [Institut Pluridisciplinaire Hubert Curien (IPHC), 23 rue du loess, BP 28, 67037 Strasbourg (France); Degerli, Y. [CEA Saclay, IRFU/SEDI, 91191 Gif-sur-Yvette Cedex (France); Hu, Y., E-mail: yann.hu@iphc.cnrs.fr [Institut Pluridisciplinaire Hubert Curien (IPHC), 23 rue du loess, BP 28, 67037 Strasbourg (France)

    2013-03-11

    In order to resolve the inherent readout speed limitation of traditional 2D CMOS pixel sensors, operated in rolling shutter readout, a parallel readout architecture has been developed by taking advantage of 3D integration technologies. Since the rows of the pixel array are zero-suppressed simultaneously instead of sequentially, a frame readout time of a few microseconds is expected for coping with high hit rates foreseen in future collider experiments. In order to demonstrate the pixel readout functionality of such a pixel sensor, a 2D proof-of-concept chip including a novel pixel-level signal processing chain was designed and fabricated in a 0.13μm CMOS technology. The functionalities of this chip have been verified through experimental characterization.

  7. A Nordic Project Project on High Speed Low Power Design in Sub-micron CMOS Technology for Mobile

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    of including good off-chip components in the design by use of innovative, inexpensive package technology.To achieve a higher level of integration, the project will use a novel codesign approach to the design strategy. Rather than making specifications based on a purely architectural approach, the work uses...... a concurrent approach, where circuit designers and architecture designers co-operate on the design and specifications. This allows more circuit issues to be included in the overall architecture, hopefully resulting in an architecture with circuit blocks suited for full integration....... digital base-band processing on the same chip. Presently, only few examples of CMOS used for RF front-end circuits have been presented by academia, and so far no commercial products exist. The approach has been to do a CMOS block by block replacement of the blocks in traditional transceiver architectures...

  8. Development of cryogenic CMOS Readout ASICs for the Point-Contact HPGe Detectors for Dark Matter Search and Neutrino Experiments

    Science.gov (United States)

    Deng, Zhi; He, Li; Liu, Feng; Liu, Yinong; Xue, Tao; Li, Yulan; Yue, Qian

    2017-05-01

    The paper presents the developments of two cryogenic readout ASICs for the point-contact HPGe detectors for dark matter search and neutrino experiments. Extremely low noise readout electronics were demanded and the capability of working at cryogenic temperatures may bring great advantages. The first ASIC was a monolithic CMOS charge sensitive preamplifier with its noise optimized for ∼1 pF input capacitance. The second ASIC was a waveform recorder based on switched capacitor array. These two ASICs were fabricated in CMOS 350 nm and 180 nm processes respectively. The prototype chips were tested and showed promising results. Both ASICs worked well at low temperature. The preamplifier had achieved ENC of 10.3 electrons with 0.7 pF input capacitance and the SCA chip could run at 9 bit effective resolution and 25 MSPS sampling rate.

  9. Design of a Parallel Sampling Encoder for Analog to Information (A2I Converters: Theory, Architecture and CMOS Implementation

    Directory of Open Access Journals (Sweden)

    Andreas G. Andreou

    2013-03-01

    Full Text Available We discuss the architecture and design of parallel sampling front ends for analog to information (A2I converters. As a way of example, we detail the design of a custom 0.5 µm CMOS implementation of a mixed signal parallel sampling encoder architecture. The system consists of configurable parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs. The analog front-end modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. An FPGA is employed to generate the chipping sequences and process the digitized samples.

  10. Capacitor-Free, Low Drop-Out Linear Regulator in a 180 nm CMOS for Hearing Aids

    DEFF Research Database (Denmark)

    Yosef-Hay, Yoni; Llimos Muntal, Pere; Larsen, Dennis Øland;

    2016-01-01

    This paper presents a capacitor-free low dropout (LDO) linear regulator based on a new dual loop topology. The regulator utilizes the feedback loops to satisfy the challenges for hearing aid devices, which include fast transient performance and small voltage spikes under rapid load-current changes....... The proposed design works without the need of an off-chip discrete capacitor connected at the output and operates with 0-100 pF capacitive load. The design has been implemented in a 0.18 µm CMOS process. The proposed regulator has a low component count and is suitable for system-on-chip integration...

  11. LC-Oscillator for 94 GHz Automotive Radar System Fabricated in SiGe:C BiCMOS Technology

    OpenAIRE

    2004-01-01

    This paper presents the design and measurement of a voltage-controlled oscillator (VCO) for the use in a 94 GHz automotive radar system and other applications. The oscillator has been fabricated in a 200 GHz SiGe:C BiCMOS technology with 0.25 µm minimum feature size. The oscillator is fully integrated on a single chip with a chip area of only 0.25 mm2. The fabricated oscillator has a tuning range of 2.2 GHz and a supply voltage of -3 Volt.

  12. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhou Feng; Gao Ting; Lan Fei; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-11-15

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 {mu}m RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  13. Modeling and Design Guidelines for P⁺ Guard Rings in Lightly Doped CMOS Substrates

    DEFF Research Database (Denmark)

    Shen, Ming; Mikkelsen, Jan H.; Zhang, Ke;

    2013-01-01

    This paper presents a compact model for ${rm P}^{+}$ guard rings in lightly doped CMOS substrates featuring a P-well layer. Simple expressions for the impedances in the model are derived based on a conformal mapping approach. The model can be used to predict the noise suppression performance...... of ${rm P}^{+}$ guard rings in terms of S-parameters, which is useful for substrate noise mitigation in mixed-signal system-on-chips. Validation of the model has been done by both electromagnetic simulation and experimental results from guard rings implemented using a standard 0.18-$mu{rm m}$ CMOS process....... In addition, design guidelines have been drawn for minimizing the guard ring size while maintaining the noise suppression performance....

  14. 320×240 Pixels CMOS Digital Image Sensor with Wide Dynamic Range

    Institute of Scientific and Technical Information of China (English)

    FANG Jie; WANG Jing-guang; HONG Zhi-liang

    2004-01-01

    A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.

  15. Characterization of zeolite-trench-embedded microcantilevers with CMOS strain gauge for integrated gas sensor applications

    Science.gov (United States)

    Inoue, Shu; Denoual, Matthieu; Awala, Hussein; Grand, Julien; Mintova, Sveltana; Tixier-Mita, Agnès; Mita, Yoshio

    2016-04-01

    Custom-synthesized zeolite is coated and fixed into microcantilevers with microtrenches of 1 to 5 µm width. Zeolite is a porous material that absorbs chemical substances; thus, it is expected to work as a sensitive chemical-sensing head. The total mass increases with gas absorption, and the cantilever resonance frequency decreases accordingly. In this paper, a thick zeolite cantilever sensor array system for high sensitivity and selectivity is proposed. The system is composed of an array of microcantilevers with silicon deep trenches. The cantilevers are integrated with CMOS-made polysilicon strain gauges for frequency response electrical measurement. The post-process fabrication of such an integrated array out of a foundry-made CMOS chip is successful. On the cantilevers, three types of custom zeolite (FAU-X, LTL, and MFI) are integrated by dip and heating methods. The preliminary measurement has shown a clear shift of resonance frequency by the chemical absorbance of ethanol gas.

  16. A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering

    Science.gov (United States)

    Lioe, DeXing; Mars, Kamel; Takasawa, Taishi; Yasutomi, Keita; Kagawa, Keiichiro; Hashimoto, Mamoru; Kawahito, Shoji

    2016-03-01

    A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering (SRS) spectroscopy is presented in this paper. The effective SRS signal from the stimulated emission of SRS mechanism is very small in contrast to the offset of a probing laser source, which is in the ratio of 10-4 to 10-5. In order to extract this signal, the common offset component is removed, and the small difference component is sampled using switched-capacitor integrator with a fully differential amplifier. The sampling is performed over many integration cycles to achieve appropriate amplification. The lock-in pixels utilizes high-speed lateral electric field charge modulator (LEFM) to demodulate the SRS signal which is modulated at high-frequency of 20MHz. A prototype chip is implemented using 0.11μm CMOS image sensor technology.

  17. Millimeter Wave on Chip Antenna Using Dogbone Shape Artificial Magnetic Conductor

    Directory of Open Access Journals (Sweden)

    Guo Qing Luo

    2013-01-01

    Full Text Available An artificial magnetic conductor (AMC applied in millimeter wave on chip antenna design based on a standard 0.18 μm CMOS technology is studied. The AMC consisting of two-dimensional periodic dogbone shape elements is constructed at one metal layer of the CMOS structure. After its performance has been completely investigated, it has been used in an on chip dipole antenna design as an artificial background to enhance efficiency of the dipole antenna. The result shows that 0.72 dB gain has been achieved at 75 GHz when the AMC is constructed by a 4*6 dogbone array.

  18. CMOS microelectrode array for the monitoring of electrogenic cells.

    Science.gov (United States)

    Heer, F; Franks, W; Blau, A; Taschini, S; Ziegler, C; Hierlemann, A; Baltes, H

    2004-09-15

    Signal degradation and an array size dictated by the number of available interconnects are the two main limitations inherent to standalone microelectrode arrays (MEAs). A new biochip consisting of an array of microelectrodes with fully-integrated analog and digital circuitry realized in an industrial CMOS process addresses these issues. The device is capable of on-chip signal filtering for improved signal-to-noise ratio (SNR), on-chip analog and digital conversion, and multiplexing, thereby facilitating simultaneous stimulation and recording of electrogenic cell activity. The designed electrode pitch of 250 microm significantly limits the space available for circuitry: a repeated unit of circuitry associated with each electrode comprises a stimulation buffer and a bandpass filter for readout. The bandpass filter has corner frequencies of 100 Hz and 50 kHz, and a gain of 1000. Stimulation voltages are generated from an 8-bit digital signal and converted to an analog signal at a frequency of 120 kHz. Functionality of the read-out circuitry is demonstrated by the measurement of cardiomyocyte activity. The microelectrode is realized in a shifted design for flexibility and biocompatibility. Several microelectrode materials (platinum, platinum black and titanium nitride) have been electrically characterized. An equivalent circuit model, where each parameter represents a macroscopic physical quantity contributing to the interface impedance, has been successfully fitted to experimental results.

  19. A CMOS ASIC Design for SiPM Arrays.

    Science.gov (United States)

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

  20. A compact PE memory for vision chips

    Science.gov (United States)

    Cong, Shi; Zhe, Chen; Jie, Yang; Nanjian, Wu; Zhihua, Wang

    2014-09-01

    This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm2/bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.

  1. Spectrometry with consumer-quality CMOS cameras.

    Science.gov (United States)

    Scheeline, Alexander

    2015-01-01

    Many modern spectrometric instruments use diode arrays, charge-coupled arrays, or CMOS cameras for detection and measurement. As portable or point-of-use instruments are desirable, one would expect that instruments using the cameras in cellular telephones and tablet computers would be the basis of numerous instruments. However, no mass market for such devices has yet developed. The difficulties in using megapixel CMOS cameras for scientific measurements are discussed, and promising avenues for instrument development reviewed. Inexpensive alternatives to use of the built-in camera are also mentioned, as the long-term question is whether it is better to overcome the constraints of CMOS cameras or to bypass them.

  2. Nanopore-CMOS Interfaces for DNA Sequencing.

    Science.gov (United States)

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-08-06

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

  3. Harmonic Distortion in CMOS Current Mirrors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1998-01-01

    One of the origins of harmonic distortion in CMOS current mirrors is the inevitable mismatch between the MOS transistors involved. In this paper we examine both single current mirrors and complementary class AB current mirrors and develop an analytical model for the mismatch induced harmonic...... distortion. This analytical model is verified through simulations and is used for a discussion of the impact of mismatch on harmonic distortion properties of CMOS current mirrors. It is found that distortion levels somewhat below 1% can be attained by carefully matching the mirror transistors but ultra low...... distortion is not achievable with CMOS current mirrors...

  4. Bridging faults in BiCMOS circuits

    Science.gov (United States)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1993-01-01

    Combining the advantages of CMOS and bipolar, BiCMOS is emerging as a major technology for many high performance digital and mixed signal applications. Recent investigations revealed that bridging faults can be a major failure mode in IC's. Effects of bridging faults in BiCMOS circuits are presented. Bridging faults between logical units without feedback and logical units with feedback are considered. Several bridging faults can be detected by monitoring the power supply current (I(sub DDQ) monitoring). Effects of bridging faults and bridging resistance on output logic levels were examined along with their effects on noise immunity.

  5. Low-power wireless on-chip microparticle manipulation with process variation compensation

    OpenAIRE

    Kishiwada, Yasushi; Iwasaki, Hirosuke; Ueda, Shun; Dei, Yoshiaki; Miyawaki, Yusuke; Matsuoka, Toshimasa

    2013-01-01

    A chip with which to manipulate microparticles using wireless power transfer and pulse-driven dielectrophoresis has been designed and fabricated using a 0.18-µm CMOS process. The chip enables microparticle manipulation using a 0.35-V power supply and a 10∼100kHz clock, which are generated on the chip by means of an on-chip coil, a rectifier and a ring oscillator circuit with process variation compensation circuits. The proposed process variation compensation with effective gate-width tuning a...

  6. Biostability of an implantable glucose sensor chip

    Science.gov (United States)

    Fröhlich, M.; Birkholz, M.; Ehwald, K. E.; Kulse, P.; Fursenko, O.; Katzer, J.

    2012-12-01

    Surface materials of an implantable microelectronic chip intended for medical applications were evaluated with respect to their long-term stability in bio-environments. The sensor chip shall apply in a glucose monitor by operating as a microviscosimeter according to the principle of affinity viscosimetry. A monolithic integration of a microelectromechanical system (MEMS) into the sensor chip was successfully performed in a combined 0.25 μm CMOS/BiCMOS technology. In order to study material durability and biostability of the surfaces, sensor chips were exposed to various in vitro and in vivo tests. Corrosional damage of SiON, SiO2 and TiN surfaces was investigated by optical microscopy, ellipsometry and AFM. The results served for optimizing the Back-end-of-Line (BEoL) stack, from which the MEMS was prepared. Corrosion of metal lines could significantly be reduced by improving the topmost passivation layer. The experiments revealed no visible damage of the actuator or other functionally important MEMS elements. Sensor chips were also exposed to human body fluid for three month by implantation into the abdomen of a volunteer. Only small effects were observed for layer thickness and Ra roughness after explantation. In particular, TiN as used for the actuator beam showed no degradation by biocorrosion. The highest degradation rate of about 50 nm per month was revealed for the SiON passivation layer. These results suggest that the sensor chip may safely operate in subcutaneous tissue for a period of several months.

  7. Atom chips

    CERN Document Server

    Reichel, Jakob

    2010-01-01

    This book provides a stimulating and multifaceted picture of a rapidly developing field. The first part reviews fundamentals of atom chip research in tutorial style, while subsequent parts focus on the topics of atom-surface interaction, coherence on atom chips, and possible future directions of atom chip research. The articles are written by leading researchers in the field in their characteristic and individual styles.

  8. Low-loss CMOS copper plasmonic waveguides at the nanoscale (Conference Presentation)

    Science.gov (United States)

    Fedyanin, Dmitry Y.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.; Volkov, Valentyn S.

    2016-05-01

    Implementation of optical components in microprocessors can increase their performance by orders of magnitude. However, the size of optical elements is fundamentally limited by diffraction, while miniaturization is one of the essential concepts in the development of high-speed and energy-efficient electronic chips. Surface plasmon polaritons (SPPs) are widely considered to be promising candidates for the next generation of chip-scale technology thanks to the ability to break down the fundamental diffraction limit and manipulate optical signals at the truly nometer scale. In the past years, a variety of deep-subwavelength plasmonic structures have been proposed and investigated, including dielectric-loaded SPP waveguides, V-groove waveguides, hybrid plasmonic waveguides and metal nanowires. At the same time, for practical application, such waveguide structures must be integrated on a silicon chip and be fabricated using CMOS fabrication process. However, to date, acceptable characteristics have been demonstrated only with noble metals (gold and silver), which are not compatible with industry-standard manufacturing technologies. On the other hand, alternative materials introduce enormous propagation losses due absorption in the metal. This prevents plasmonic components from implementation in on-chip nanophotonic circuits. In this work, we experimentally demonstrate for the first time that copper plasmonic waveguides fabricated in a CMOS compatible process can outperform gold waveguides showing the same level of mode confinement and lower propagation losses. At telecommunication wavelengths, the fabricated ultralow-loss deep-subwavelength hybrid plasmonic waveguides ensure a relatively long propagation length of more than 50 um along with strong mode confinement with the mode size down to lambda^2/70, which is confirmed by direct scanning near-field optical microscopy (SNOM) measurements. These results create the backbone for design and development of high

  9. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

    Directory of Open Access Journals (Sweden)

    Virgilio Valente

    2016-07-01

    Full Text Available This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR channels and four voltage-readout (VR channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS analysis. Each VR channel occupies an area of 0.48 mm 2 , is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μ A. Each CR channel occupies an area of 0.21 mm 2 . The chip consumes between 530 μ A and 690 μ A per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis.

  10. 5.2-GHz RF Power Harvester in 0.18-/spl mu/m CMOS for Implantable Intraocular Pressure Monitoring

    KAUST Repository

    Ouda, Mahmoud H.

    2013-04-17

    A first fully integrated 5.2-GHz CMOS-based RF power harvester with an on-chip antenna is presented in this paper. The design is optimized for sensors implanted inside the eye to wirelessly monitor the intraocular pressure of glaucoma patients. It includes a five-stage RF rectifier with an on-chip antenna, a dc voltage limiter, two voltage sensors, a low dropout voltage regulator, and MOSCAP based on-chip storage. The chip has been designed and fabricated in a standard 0.18-μm CMOS technology. To emulate the eye environment in measurements, a custom test setup is developed that comprises Plexiglass cavities filled with saline solution. Measurements in this setup show that the proposed chip can be charged to 1 V wirelessly from a 5-W transmitter 3 cm away from the harvester chip. The energy that is stored on the 5-nF on-chip MOSCAP when charged to 1 V is 2.5 nJ, which is sufficient to drive an arbitrary 100-μW load for 9 μs at regulated 0.8 V. Simulated efficiency of the rectifier is 42% at -7 dBm of input power.

  11. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  12. CMOS circuits for passive wireless microsystems

    CERN Document Server

    Yuan, Fei

    2011-01-01

    Here is a comprehensive examination of CMOS circuits for passive wireless microsystems. Covers design challenges, fundamental issues of ultra-low power wireless communications, radio-frequency power harvesting, and advanced design techniques, and more.

  13. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  14. A CMOS imager using focal-plane pinhole effect for confocal multibeam scanning microscopy

    Science.gov (United States)

    Seo, Min-Woong; Wang, An; Li, Zhuo; Yasutomi, Keita; Kagawa, Keiichiro; Kawahito, Shoji

    2012-03-01

    A CMOS imager for confocal multi-beam scanning microscopy, where the pixel itself works as a pinhole, is proposed. This CMOS imager is suitable for building compact, low-power, and confocal microscopes because the complex Nipkow disk with a precisely aligned pinhole array can be omitted. The CMOS imager is composed of an array of sub-imagers, and can detect multiple beams at the same time. To achieve a focal-plane pinhole effect, only one pixel in each subimager, which is at the conjugate position of a light spot, accumulates the photocurrent, and the other pixels are unread. This operation is achieved by 2-dimensional vertical and horizontal shift registers. The proposed CMOS imager for the confocal multi-beam scanning microscope system was fabricated in 0.18-μm standard CMOS technology with a pinned photodiode option. The total area of the chip is 5.0mm × 5.0mm. The number of effective pixels is 256(Horizontal) × 256(Vertical). The pixel array consists of 32(H) × 32(V) sub-imagers each of which has 8(H) × 8(V) pixels. The pixel is an ordinary 4-transistor active pixel sensor using a pinned photodiode and the pixel size is 7.5μm × 7.5μm with a fillfactor of 45%. The basic operations such as normal image acquisition and selective pixel readout were experimentally confirmed. The sensitivity and the pixel conversion gain were 25.9 ke-/lx•sec and 70 μV/e- respectively.

  15. CMOS Compatible Ultra-Compact Modulator

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    A planar layout for an ultra-compact plasmonic modulator is proposed and numerically investigated. Our device utilizes potentially CMOS compatible materials and can achieve 3-dB modulation in just 65nm and insertion loss <1dB at telecommunication wavelengths.......A planar layout for an ultra-compact plasmonic modulator is proposed and numerically investigated. Our device utilizes potentially CMOS compatible materials and can achieve 3-dB modulation in just 65nm and insertion loss

  16. CLARO-CMOS: a fast, low power and radiation-hard front-end ASIC for single-photon counting in 0.35 micron CMOS technology

    Science.gov (United States)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-01-01

    The CLARO-CMOS is a prototype ASIC designed for fast photon counting with multi-anode photomultiplier tubes (MaPMT). The CLARO features a 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. The chip was designed in 0.35 μm CMOS technology, and was tested for radiation hardness with neutrons up to 1014 1 MeV neq/cm2, X-rays up to 40 kGy and protons up to 76 kGy. Its capability to read out single photons at high rate from a Hamamatsu R11265 MaPMT, the baseline photon detector for the LHCb RICH upgrade, was demonstrated both with test bench measurements and with actual signals from a R11265 MaPMT. The presented results allowed CLARO to be chosen as the front-end readout chip in the upgraded LHCb RICH detector.

  17. Design and implementation of IEEE 802.11ac MAC controller in 65 nm CMOS process

    Science.gov (United States)

    Peng, Cheng; Bin, Wu; Yong, Hei

    2016-02-01

    An IEEE-802.11ac-1*1 wireless LAN system-on-a-chip (SoC) that integrates an analog front end, a digital base-band processor and a media access controller has been implemented in 65 nm CMOS technology. It can provide significantly increased throughput, high efficiency rate selection, and fully backward compatibility with the existing 802.11a/n WLAN protocols. Especially the measured maximum throughput of UDP traffic can be up to 267 Mbps. Project supported by the National Great Specific Project of China (No. 2012ZX03004004_001).

  18. Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

    Directory of Open Access Journals (Sweden)

    Jianhong Xiao

    2007-01-01

    Full Text Available A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

  19. Prototype Active Silicon Sensor in 150 nm HR-CMOS Technology for ATLAS Inner Detector Upgrade

    CERN Document Server

    Rymaszewski, Piotr; Breugnon, Patrick; Godiot, Stépahnie; Gonella, Laura; Hemperek, Tomasz; Hirono, Toko; Hügging, Fabian; Krüger, Hans; Liu, Jian; Pangaud, Patrick; Peric, Ivan; Rozanov, Alexandre; Wang, Anqing; Wermes, Norbert

    2016-01-01

    The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of inner tracking detectors. A possible solution is to use active silicon sensors, taking advantage of commercial CMOS technologies. Currently ATLAS R&D programme is qualifying a few commercial technologies in terms of suitability for this task. In this paper a prototype designed in one of them (LFoundry 150 nm process) will be discussed. The chip architecture will be described, including different pixel types incorporated into the design, followed by simulation and measurement results.

  20. A BiCMOS synchronous pulse discriminator for the LHCb calorimeter system

    CERN Document Server

    Bota, S; Gascón, D; Graciani, R

    2002-01-01

    A monolithic prototype for the analogue readout of the Scintillator Pad Detector (SPD) of the LHCb calorimeter is presented. A low power version that works at 3.3 V has been designed using the 0.8 mu m Bi CMOS technology of AMS. It consists of a charge discriminator with a dual path structure formed by an integrator, a pile-up correction, a subtractor and a comparator. The chip also includes a DAC and serial digital control interface to program the threshold of the discriminator. Design, simulation and test results for different prototypes of the circuit will be presented and described. (8 refs).

  1. Digital Offset Calibration of an OPAMP Towards Improving Static Parameters of 90 nm CMOS DAC

    Directory of Open Access Journals (Sweden)

    D. Arbet

    2014-09-01

    Full Text Available In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC based on digitally compensated input offset of the operational amplifier (OPAMP is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90 nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error is achieved.

  2. Synchronization of Integrated Systems on a Chip

    Directory of Open Access Journals (Sweden)

    González-Díaz O.

    2012-04-01

    Full Text Available In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor N-well 0.35 µm Austria Micro Systems process parameters were used for conventional and non-conventional clock distribution nets design and simulation. Experimental results from local and global clock distribution networks fabricated using a CMOS 0.35 µm process show that the use of interconnected rings arrays, as globally asynchronous locally synchronous (GALS clock distribution networks, represent an appropriate approach due to good performance regarding scalability, low clock-skew, high-speed, faults tolerant and robust under process variations, regularity, and modularity.

  3. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  4. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  5. Studies of irradiated AMS H35 CMOS detectors for the ATLAS tracker upgrade

    Science.gov (United States)

    Cavallaro, E.; Casanova, R.; Förster, F.; Grinstein, S.; Lange, J.; Kramberger, G.; Mandić, I.; Puigdengoles, C.; Terzo, S.

    2017-01-01

    Silicon detectors based on the HV-CMOS technology are being investigated as possible candidate for the outer layers of the ATLAS pixel detector for the High Luminosity LHC. In this framework the H35Demo ASIC has been produced in the 350 nm AMS technology (H35). The H35Demo chip has a large area (18.49 × 24.40 mm2) and includes four different pixel matrices and three test structures. In this paper the radiation hardness properties, in particular the evolution of the depletion region with fluence is studied using edge-TCT on test structures. Measurements on the test structures from chips with different substrate resistivity are shown for non irradiated and irradiated devices up to a cumulative fluence of 2 ṡ 1015 1 MeV neq / cm2.

  6. Continuous-Time ΣΔ ADC with Implicit Variable Gain Amplifier for CMOS Image Sensor

    Directory of Open Access Journals (Sweden)

    Fang Tang

    2014-01-01

    amplifier (OTA, for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

  7. Studies of irradiated AMS H35 CMOS detectors for the ATLAS tracker upgrade

    CERN Document Server

    Cavallaro, Emanuele; Förster, Fabian; Grinstein, Sebastinan; Lange, Jörn; Kramberger, Gregor; Mandić, Igor; Puigdengoles, Carles; Terzo, Stefano

    2016-01-01

    Silicon detectors based on the HV-CMOS technology are being investigated as possible candidate for the outer layers of the ATLAS pixel detector for the High Luminosity LHC. In this framework the H35Demo ASIC has been produced in the 350 nm AMS technology (H35). The H35Demo chip has a large area ($18.49 \\times 24.40 \\, \\mathrm{mm^2}$) and includes four different pixel matrices and three test structures. In this paper the radiation hardness properties, in particular the evolution of the depletion region with fluence is studied using edge-TCT on test structures. Measurements on the test structures from chips with different substrate resistivity are shown for non irradiated and irradiated devices up to a cumulative fluence of $2 \\cdot 10^{15} \\, \\mathrm{1\\,MeV\\, n_{eq} / cm^{2}}$.

  8. CMOS circuits for electromagnetic vibration transducers interfaces for ultra-low voltage energy harvesting

    CERN Document Server

    Maurath, Dominic

    2015-01-01

    Chip-integrated power management solutions are a must for ultra-low power systems. This enables not only the optimization of innovative sensor applications. It is also essential for integration and miniaturization of energy harvesting supply strategies of portable and autonomous monitoring systems. The book particularly addresses interfaces for energy harvesting, which are the key element to connect micro transducers to energy storage elements. Main features of the book are: - A comprehensive technology and application review, basics on transducer mechanics, fundamental circuit and control design, prototyping and testing, up to sensor system supply and applications. - Novel interfacing concepts - including active rectifiers, MPPT methods for efficient tracking of DC as well as AC sources, and a fully-integrated charge pump for efficient maximum AC power tracking at sub-100µW ultra-low power levels. The chips achieve one of widest presented operational voltage range in standard CMOS technology: 0.44V to over...

  9. 1-GHz CMOS VCO design for wireless application using MEMS technology

    Science.gov (United States)

    Mohamed, Amal; Elsimary, Hamed; Ismail, Mohammed

    2000-04-01

    In this work, the design of RF VCO circuit, in which the oscillation frequency is controlled by a tunable capacitor based on microelectromechanical system (MEMS) technology is presented. The design of high Q-MEMS tunable capacitor has been accomplished through bulk micro machining with all metal micro structure. A standard CMOS process is used to carry out the fabrication of the VCO circuit with the MEMS tunable capacitor on the same chip. The main features of this design, is the enabling of a complete monolithic fabrication RF VCOs using on-chip IC compatible high-Q MEMS tunable capacitor. The performance of the MEMS capacitor is modeled with emphasis on the tunability range with the tuning voltage. The simulation results are presented to show the performance of RF VCO circuit with the MEMS tunable capacitor, which has a high-Q of about 60 at 1 GHZ and low insertion loss of -1dB at 40 GHz.

  10. CMOS implementation of a low-power BPSK demodulator for wireless implantable neural command transmission

    Institute of Scientific and Technical Information of China (English)

    Wu Zhaohui; Zhang Xu; Liang Zhiming; Li Bin

    2012-01-01

    A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became simpler and hence its power consumption became lower.Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system.The proposed BPSK demodulator was implemented by Global Foundries 0.35 μm CMOS technology with a 3.3 V power supply.The designed chip area is only 0.07 mm2 and the power consumption is 0.5 mW.The test results show that it can work correctly.

  11. A novel interconnect-optimal repeater insertion model with target delay constraint in 65 nm CMOS

    Institute of Scientific and Technical Information of China (English)

    Zhu Zhang-Ming; Qian Li-Bo; Yang Yin-Tang

    2009-01-01

    Repeater optimization is the key for SOC (System on Chip) interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD (computer aided design) tool for interconnect planning in nanometre SOC.

  12. CMOS implementation of a low-power BPSK demodulator for wireless implantable neural command transmission

    Science.gov (United States)

    Zhaohui, Wu; Xu, Zhang; Zhiming, Liang; Bin, Li

    2012-05-01

    A new BPSK demodulator was presented. By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator, the circuit structure of the demodulator became simpler and hence its power consumption became lower. Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system. The proposed BPSK demodulator was implemented by Global Foundries 0.35 μm CMOS technology with a 3.3 V power supply. The designed chip area is only 0.07 mm2 and the power consumption is 0.5 mW. The test results show that it can work correctly.

  13. CMOS buried quad p-n junction photodetector for multi-wavelength analysis.

    Science.gov (United States)

    Richard, Charles; Courcier, Thierry; Pittet, Patrick; Martel, Stéphane; Ouellet, Luc; Lu, Guo-Neng; Aimez, Vincent; Charette, Paul G

    2012-01-30

    This paper presents a buried quad p-n junction (BQJ) photodetector fabricated with a HV (high-voltage) CMOS process. Multiple buried junction photodetectors are wavelength-sensitive devices developed for spectral analysis applications where a compact integrated solution is preferred over systems involving bulk optics or a spectrometer due to physical size limitations. The BQJ device presented here is designed for chip-based biochemical analyses using simultaneous fluorescence labeling of multiple analytes such as with advanced labs-on-chip or miniaturized photonics-based biosensors. Modeling and experimental measurements of the spectral response of the device are presented. A matrix-based method for estimating individual spectral components in a compound spectrum is described. The device and analysis method are validated via a test setup using individually modulated LEDs to simulate light from 4-component fluorescence emission.

  14. A fully integrated direct-conversion digital satellite tuner in 0.18μ m CMOS*

    Institute of Scientific and Technical Information of China (English)

    Chen Si; Yang Zengwang; Gu Mingliang

    2011-01-01

    A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 μm CMOS, the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz Lband, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 C integrated phase error.The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

  15. Heart rate variability monitoring and assessment system on chip.

    Science.gov (United States)

    Massagram, Wansuree; Boric-Lubecke, Olga; Macchiarulo, Luca; Chen, Mingqi

    2005-01-01

    This paper describes a system on a chip for heart rate variability monitoring and assessment. The system design applies digital techniques to measure RR intervals from ECG signals, then categorizes and stores HRV measures in an internal memory. The system has been tested for functionality, synthesized and laid out in a 0.5 μm CMOS technology in a 3x3 mm2chip with less than 1.5 μW power dissipation. The chip detects all R peaks with millisecond accuracy after the initial 2 seconds of data, and stores up to 2 minutes of continuous ECG data and up to 4 minutes of HRV histogram. Compact size, low cost, and low power consumption make this chip suitable for employment in modern implantable and portable devices.

  16. Crosstalk in modern on-chip interconnects a FDTD approach

    CERN Document Server

    Kaushik, B K; Patnaik, Amalendu

    2016-01-01

    The book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based interconnects are presented. Based on the electrical equivalent models the performance comparison among the Cu, CNT and GNR-based interconnects are also discussed in the book. The proposed models are validated with the HSPICE simulations. The book introduces the current research scenario in the modeling of on-chip interconnects. It presents the structure, properties, and characteristics of graphene based on-chip interconnects and the FDTD modeling of Cu based on-chip interconnects. The model considers the non-linear effects of CMOS driver as well as the transmission line effects of interconnect line that includes coupling capacitance and mutual inductance effects. In a more realistic manner, the proposed model includes the effect of width-dependent MFP of the ...

  17. CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

    Data.gov (United States)

    Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

  18. A Transceiver for High-Speed Global On-Chip Data Communication

    NARCIS (Netherlands)

    Schinkel, Daniël; Mensink, Eisse; Klumperink, Eric; Tuijl, van Ed; Nauta, Bram

    2005-01-01

    Global on-chip data communication is becoming a concern as the gap between transistor speed and interconnect bandwidth increases with CMOS process scaling. In this paper we show how a special form of equalization, pulse-width pre-emphasis, can significantly increase the data rate for a given length

  19. A 0.18 μm CMOS fluorescent detector system for bio-sensing application

    Institute of Scientific and Technical Information of China (English)

    Liu Nan; Chen Guoping; Hong Zhiliang

    2009-01-01

    A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a "contact imaging" detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodi-ode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

  20. A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

    Science.gov (United States)

    Zhang, Fan; Niu, Hanben

    2016-06-29

    In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

  1. All-digital pulse-expansion-based CMOS digital-to-time converter

    Science.gov (United States)

    Chen, Chun-Chi; Chu, Che-Hsun

    2017-02-01

    This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μ m Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm2. Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

  2. CMOS Receiver Front-ends for Gigabit Short-Range Optical Communications

    CERN Document Server

    Aznar, Francisco; Calvo Lopez, Belén

    2013-01-01

    This book describes optical receiver solutions integrated in standard CMOS technology, attaining high-speed short-range transmission within cost-effective constraints.  These techniques support short reach applications, such as local area networks, fiber-to-the-home and multimedia systems in cars and homes. The authors show how to implement the optical front-end in the same technology as the subsequent digital circuitry, leading to integration of the entire receiver system in the same chip.  The presentation focuses on CMOS receiver design targeting gigabit transmission along a low-cost, standardized plastic optical fiber up to 50m in length.  This book includes a detailed study of CMOS optical receiver design – from building blocks to the system level. Reviews optical communications, including long-haul transmission systems and emerging applications focused on short-range; Explains necessary fundamentals, such as characteristics of a data signal, system requirements affecting receiver design and key par...

  3. Low noise CMOS readout for CdZnTe detector arrays

    CERN Document Server

    Jakobson, C G; Lev, S B; Nemirovsky, Y

    1999-01-01

    A low noise CMOS readout for CdTe and CdZnTe X- and gamma-ray detector arrays has been designed and implemented in the CMOS 2 mu m low noise analog process provided by the multi-chip program of Metal Oxide Semiconductor Implementation Service. The readout includes CMOS low noise charge sensitive preamplifier and a multiplexed semi-Gaussian pulse shaper. Thus, each detector has a dedicated charge sensitive preamplifier that integrates its signal, while a single shaping amplifier shapes the pulses after the multiplexer. Low noise and low-power operation are achieved by optimizing the input transistor of the charge sensitive preamplifier. Two optimization criteria are used to reduce noise. The first criterion is based on capacitance matching between the input transistor and the detector. The second criterion is based on bandwidth optimization, which is obtained by tailoring the shaper parameters to the particular noise mechanisms of the MOS transistor and the CdZnTe detector. Furthermore, the multiplexing functi...

  4. A digitally calibrated CMOS RMS power detector for RF automatic gain control

    Institute of Scientific and Technical Information of China (English)

    Yan Taotao; Wang Hui; Li Jinbo; Zhou Jianjun

    2013-01-01

    This paper presents the design and implementation of a digitally calibrated CMOS wideband radio frequency (RF) root-mean-square (RMS) power detector for high accuracy RF automatic gain control (AGC).The proposed RMS power detector demonstrates accurate power detection in the presence of process,supply voltage,and temperature (PVT) variations by employing a digital calibration scheme.It also consumes low power and occupies a small chip area.The measurement results show that the scheme improves the accuracy of the detector to better than 0.3 dB over the PVT variations and wide operating frequency range from 0.2 to 0.8 GHz.Implemented in a 0.18 μm CMOS process and occupying a small die area of 263 × 214 μm2,the proposed digitally calibrated CMOS RMS power detector only consumes 1.6 mA in power detection mode and 2.1 mA in digital calibration mode from a 1.8 V supply voltage.

  5. AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    N. B. ROMLI

    2015-03-01

    Full Text Available Total power dissipation in CMOS circuits has become a huge challenging in current semiconductor industry due to the leakage current and the leakage power. The exponential growth of both static and dynamic power dissipations in any CMOS process technology option has increased the cost and efficiency of the system. Technology options are used for the execution specifications and usually it depends on the optimisation and the performance constraints over the chip. This article reviews the relevant researches of the source or power dissipation, the mechanism to reduce the dynamic power dissipation as well as static power dissipation and an overview of various circuit techniques to control them. Important device parameters including voltage threshold and switching capacitance impact to the circuit performance in lowering both dynamic and static power dissipation are presented. The demand for the reduction of power dissipation in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on power dissipation and control techniques.

  6. Fully Scaled 0.5 Micron CMOS Technology Using Variable Shaped Electron Beam Lithography

    Science.gov (United States)

    Coane, Philip; Rudeck, Paul; Wang, Li-Kong; Wilson, Alan; Hohn, Fritz

    1988-06-01

    Over the past several years, CMOS technology has been continuously driven to achieve enhanced performance and higher density. The resulting reduction in semiconductor dimensions has surpasssed the limits attainable by the most advanced optical lithography tools. As a result, the utilization of electron beam lithography direct writing techniques to satisfy VLSI patterning requirements has increased significantly. In principle, variable shaped electron beam systems are capable of writing linewidths down to at least 0.1 micron. However, the successful application of sub-micron scaling principles to device fabrication involves an integration of tool capability and resist process control. In order to achieve the realization of improved CMOS device performance and circuit density, sub-micron ground rules (line width control and overlay) must be satisfied over the full chip. This paper reports on a high performance, fully scaled 0.5 micron CMOS technology developed for VLSI appli-cations. Significant gains in both density and performance at reduced power supply levels are realized over previously reported 1.0 micron technology. The details of the integrated lithography strategy used to achieve these results are presented.

  7. A very high speed lossless compression/decompression chip set

    Science.gov (United States)

    Venbrux, Jack; Liu, Norley; Liu, Kathy; Vincent, Peter; Merrell, Randy

    1991-01-01

    A chip is described that will perform lossless compression and decompression using the Rice Algorithm. The chip set is designed to compress and decompress source data in real time for many applications. The encoder is designed to code at 20 M samples/second at MIL specifications. That corresponds to 280 Mbits/second at maximum quantization or approximately 500 Mbits/second under nominal conditions. The decoder is designed to decode at 10 M samples/second at industrial specifications. A wide range of quantization levels is allowed (4...14 bits) and both nearest neighbor prediction and external prediction are supported. When the pre and post processors are bypassed, the chip set performs high speed entropy coding and decoding. This frees the chip set from being tied to one modeling technique or specific application. Both the encoder and decoder are being fabricated in a 1.0 micron CMOS process that has been tested to survive 1 megarad of total radiation dosage. The CMOS chips are small, only 5 mm on a side, and both are estimated to consume less than 1/4 of a Watt of power while operating at maximum frequency.

  8. Wavelength dependence of silicon avalanche photodiode fabricated by CMOS process

    Science.gov (United States)

    Mohammed Napiah, Zul Atfyi Fauzan; Hishiki, Takuya; Iiyama, Koichi

    2017-07-01

    Avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation by canceling photo-generated carriers in the substrate at the sacrifice of the responsivity. We describe here wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with shorted and opened guard ring structure.

  9. Installation of a TCT set-up for characterization of novel HV-CMOS planar silicon sensors

    CERN Document Server

    Marx, Lisa

    2013-01-01

    For future upgrades of the LHC it is necessary to develop new tracking detectors: more radiation hard and cost efficient pixel detectors with high spacial resolution are required for the planned high luminosity version of the LHC (HL-LHC). For future tracking devices HV-CMOS active pixel sensors are great candidates since they fulfill all the demands mentioned above. First prototypes of these sensors are assembled on custom test boards and together with FE-I4 readout chips they make up the first test pixel detectors. One approach for testing these chips is through using lasers to induce electron-hole-pairs into the depletion zone of the sensor chip diodes to simulate an ionizing particle crossing through the bulk. Comparison measurements of irradiated/non-irradiated sensors are used to explore the radiation hardness of the sensors.

  10. Delay estimation for CMOS functional cells

    DEFF Research Database (Denmark)

    Madsen, Jan

    1991-01-01

    Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitr......Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis...... on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment....

  11. CMOS Integrated Capacitive DC-DC Converters

    CERN Document Server

    Van Breussegem, Tom

    2013-01-01

    This book provides a detailed analysis of all aspects of capacitive DC-DC converter design: topology selection, control loop design and noise mitigation. Readers will benefit from the authors’ systematic overview that starts from the ground up, in-depth circuit analysis and a thorough review of recently proposed techniques and design methodologies.  Not only design techniques are discussed, but also implementation in CMOS is shown, by pinpointing the technological opportunities of CMOS and demonstrating the implementation based on four state-of-the-art prototypes.  Provides a detailed analysis of all aspects of capacitive DC-DC converter design;  Analyzes the potential of this type of DC-DC converter and introduces a number of techniques to unleash their full potential; Combines system theory with practical implementation techniques; Includes unique analysis of CMOS technology for this application; Provides in-depth analysis of four fabricated prototypes.

  12. Noise in sub-micron CMOS image sensors

    NARCIS (Netherlands)

    Wang, X.

    2008-01-01

    CMOS image sensors are devices that convert illumination signals (light intensity) into electronic signals. The goal of this thesis has been to analyze dominate noise sources in CMOS imagers and to improve the image quality by reducing the noise generated in the CMOS image sensor pixels.

  13. An RF (R) MS Power Detector in Standard CMOS

    NARCIS (Netherlands)

    Aa, van der F.H.J.

    2006-01-01

    This Master thesis describes the research towards the integration of RF power detectors for 3G cellular phones and base stations in CMOS technology1. It is a feasibility study with the emphasis on the identification of fundamental limitations of CMOS (particularly CMOS9) and of a number of squaring

  14. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    Science.gov (United States)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  15. Design and implementation of a CMOS light pulse receiver cell array for spatial optical communications.

    Science.gov (United States)

    Sarker, Md Shakowat Zaman; Itoh, Shinya; Hamai, Moeta; Takai, Isamu; Andoh, Michinori; Yasutomi, Keita; Kawahito, Shoji

    2011-01-01

    A CMOS light pulse receiver (LPR) cell for spatial optical communications is designed and evaluated by device simulations and a prototype chip implementation. The LPR cell consists of a pinned photodiode and four transistors. It works under sub-threshold region of a MOS transistor and the source terminal voltage which responds to the logarithm of the photo current are read out with a source follower circuit. For finding the position of the light spot on the focal plane, an image pixel array is embedded on the same plane of the LPR cell array. A prototype chip with 640 × 240 image pixels and 640 × 240 LPR cells is implemented with 0.18 μm CMOS technology. A proposed model of the transient response of the LPR cell agrees with the result of the device simulations and measurements. Both imaging at 60 fps and optical communication at the carrier frequency of 1 MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrents show that the spatial optical communication up to 100 m is feasible using a 10 × 10 LED array.

  16. Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

    Science.gov (United States)

    Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

    2014-01-01

    This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

  17. A high-speed low-noise transimpedance amplifier in a 025 mum CMOS technology

    CERN Document Server

    Anelli, G; Casagrande, L; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4fC, an input capacitance of 4pF and a transresistance of 135kOmega, we have measured an output pulse fall time of 3ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the constructio...

  18. Multifunctional Platform with CMOS-Compatible Tungsten Microhotplate for Pirani, Temperature, and Gas Sensor

    Directory of Open Access Journals (Sweden)

    Jiaqi Wang

    2015-10-01

    Full Text Available A multifunctional platform based on the microhotplate was developed for applications including a Pirani vacuum gauge, temperature, and gas sensor. It consisted of a tungsten microhotplate and an on-chip operational amplifier. The platform was fabricated in a standard complementary metal oxide semiconductor (CMOS process. A tungsten plug in standard CMOS process was specially designed as the serpentine resistor for the microhotplate, acting as both heater and thermister. With the sacrificial layer technology, the microhotplate was suspended over the silicon substrate with a 340 nm gap. The on-chip operational amplifier provided a bias current for the microhotplate. This platform has been used to develop different kinds of sensors. The first one was a Pirani vacuum gauge ranging from 1-1 to 105 Pa. The second one was a temperature sensor ranging from -20 to 70 °C. The third one was a thermal-conductivity gas sensor, which could distinguish gases with different thermal conductivities in constant gas pressure and environment temperature. In the fourth application, with extra fabrication processes including the deposition of gas-sensitive film, the platform was used as a metal-oxide gas sensor for the detection of gas concentration.

  19. Design and Implementation of A CMOS Light Pulse Receiver Cell Array for Spatial Optical Communications

    Directory of Open Access Journals (Sweden)

    Shoji Kawahito

    2011-02-01

    Full Text Available A CMOS light pulse receiver (LPR cell for spatial optical communications is designed and evaluated by device simulations and a prototype chip implementation. The LPR cell consists of a pinned photodiode and four transistors. It works under sub-threshold region of a MOS transistor and the source terminal voltage which responds to the logarithm of the photo current are read out with a source follower circuit. For finding the position of the light spot on the focal plane, an image pixel array is embedded on the same plane of the LPR cell array. A prototype chip with 640 × 240 image pixels and 640 × 240 LPR cells is implemented with 0.18 μm CMOS technology. A proposed model of the transient response of the LPR cell agrees with the result of the device simulations and measurements. Both imaging at 60 fps and optical communication at the carrier frequency of 1 MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrents show that the spatial optical communication up to 100 m is feasible using a 10 × 10 LED array.

  20. A Capacitor-Free, Fast Transient Response Linear Voltage Regulator In a 180nm CMOS

    DEFF Research Database (Denmark)

    Deleuran, Alexander N.; Lindbjerg, Nicklas; Pedersen, Martin K.

    2015-01-01

    A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 µm CMOS process. The design has a low component count and is tailored for system-on-chip integration....... A current step load from 0-50 mA with a rise time of 1 µs results in an undershoot in the output voltage of 140 mV for a period of 39 ns. The regulator sources up to 50 mA current load.......A 1.8 V capacitor-free linear regulator with fast transient response based on a new topology with a fast and slow regulation loop is presented. The design has been laid out and simulated in a 0.18 µm CMOS process. The design has a low component count and is tailored for system-on-chip integration...

  1. Integration of Si-CMOS embedded photo detector array and mixed signal processing system with embedded optical waveguide input

    Science.gov (United States)

    Kim, Daeik D.; Thomas, Mikkel A.; Brooke, Martin A.; Jokerst, Nan M.

    2004-06-01

    Arrays of embedded bipolar junction transistor (BJT) photo detectors (PD) and a parallel mixed-signal processing system were fabricated as a silicon complementary metal oxide semiconductor (Si-CMOS) circuit for the integration optical sensors on the surface of the chip. The circuit was fabricated with AMI 1.5um n-well CMOS process and the embedded PNP BJT PD has a pixel size of 8um by 8um. BJT PD was chosen to take advantage of its higher gain amplification of photo current than that of PiN type detectors since the target application is a low-speed and high-sensitivity sensor. The photo current generated by BJT PD is manipulated by mixed-signal processing system, which consists of parallel first order low-pass delta-sigma oversampling analog-to-digital converters (ADC). There are 8 parallel ADCs on the chip and a group of 8 BJT PDs are selected with CMOS switches. An array of PD is composed of three or six groups of PDs depending on the number of rows.

  2. A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

    Science.gov (United States)

    Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

    2016-01-01

    An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively. PMID:27792131

  3. A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

    Directory of Open Access Journals (Sweden)

    Cheng-Chun Wu

    2016-10-01

    Full Text Available An electronic nose (E-Nose is one of the applications for surface acoustic wave (SAW sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS readout application-specific integrated circuit (ASIC based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

  4. A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose.

    Science.gov (United States)

    Wu, Cheng-Chun; Liu, Szu-Chieh; Chiu, Shih-Wen; Tang, Kea-Tiong

    2016-10-25

    An electronic nose (E-Nose) is one of the applications for surface acoustic wave (SAW) sensors. In this paper, we present a low-noise complementary metal-oxide-semiconductor (CMOS) readout application-specific integrated circuit (ASIC) based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm². The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

  5. 60-GHz CMOS phase-locked loops

    CERN Document Server

    Cheema, Hammad M; van Roermund, Arthur HM

    2010-01-01

    The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. ""60-GHz CMOS Phase-Locked Loops"" focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of i

  6. Scaling CMOS devices through alternative structures

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

  7. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  8. Integrated 60GHz RF beamforming in CMOS

    CERN Document Server

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  9. A 1.0 V differential VCO in 0.13μm CMOS technology*

    Institute of Scientific and Technical Information of China (English)

    Cao Shengguo; Han Kefeng; Tan Xi; Yan Na; Min Hao

    2011-01-01

    A differential complementary LC voltage controlled oscillator (VCO) with high Q on-chip inductor is presented. The parallel resonator of the VCO consists of inversion-mode MOS (I-MOS) capacitors and an on-chip inductor. The resonator Q factor is mainly limited by the on-chip inductor. It is optimized by designing a single turn inductor that has a simulated Q factor of about 35 at 6 GHz. The proposed VCO is implemented in the SMIC 0.13μm 1P8M MMRF CMOS process, and the chip area is 1.0 × 0.8 mm2. The free-running frequency is from 5.73 to 6.35 GHz. When oscillating at 6.35 GHz, the current consumption is 2.55 mA from a supply voltage of 1.0 V and the measured phase noise at 1 MHz offset is -120.14 dBc/Hz. The figure of merit of the proposed VCO is -192.13 dBc/Hz.

  10. Investigation of Toshiba 130nm CMOS process as a possible candidate for active silicon sensors in HEP and X-ray experiments

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Yunan; Hemperek, Tomasz; Kishishita, Testsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany); Peric, Ivan [Karlsruhe Institute of Technology, Karlsruhe (Germany)

    2015-07-01

    Following the advances of commercial semiconductor manufacturing technologies there has recently been an increased interest within experimental physics community in applying CMOS manufacturing processes to developing active silicon sensors. Possibility of applying high voltage bias combined with high resistivity substrate allows for better depletion of sensor and therefore quicker and more efficient charge collection. One of processes that accommodates those features is Toshiba 130 nm CMOS technology (CMOS3E). Within our group a test chip was designed to examine the suitability of this technology for physics experiment (both for HEP and X-ray imaging). Design consisted of 4 pixel matrices with total of 12 different pixel flavors allowing for evaluation of various pixel geometries and architectures in terms of depletion depth, noise performance, charge collection efficiency, etc. During this talk initial outcome of this evaluation is presented, starting with brief introduction to technology itself, followed by results of TCAD simulations, description of final design and first measurements results.

  11. Active pixel sensors in AMS H18/H35 HV-CMOS technology for the ATLAS HL-LHC upgrade

    Science.gov (United States)

    Ristic, Branislav

    2016-09-01

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement signal processing electronics in deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150 V leading to a depletion depth of several 10 μm. Prototype sensors in the AMS H18 180 nm and H35 350 nm HV-CMOS processes were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiations with X-rays and protons revealed a tolerance to ionizing doses of 1 Grad while Edge-TCT studies assessed the effects of radiation on the charge collection. The sensors showed high detection efficiencies after neutron irradiation to 1015neq cm-2 in testbeam experiments. A full reticle size demonstrator chip, implemented in the H35 process is being submitted to prove the large scale feasibility of the HV-CMOS concept.

  12. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  13. Design automation techniques for high-resolution current folding and interpolating CMOS A/D converters

    Science.gov (United States)

    Gevaert, D.

    2007-05-01

    The design and testing of a 12-bit Analog-to-Digital (A/D) converter, in current mode, arranged in an 8-bit LSB and a 4- bit MSB architecture together with the integration of specialized test building blocks on chip allows the set up of a design automation technique for current folding and interpolation CMOS A/D converter architectures. The presented design methodology focuses on the automation for CMOS A/D building blocks in a flexible target current folding and interpolating architecture for a downscaling technology and for different quality specifications. The comprehensive understanding of all sources of mismatching in the crucial building blocks and the use of physical based mismatch modeling in the prediction of mismatch errors, more adequate and realistic sizing of all transistors will result in an overall area reduction of the A/D converter. In this design the folding degree is 16, the number of folders is 64 and the interpolation level is 4. The number of folders is reduced by creating intermediate folding signals with a 4-level interpolator based on current division techniques. Current comparators detect the zero-crossing between the differential folder output currents. The outputs of the comparators deliver a cyclic thermometer code. The digital synthesis part for decoding and error correction building blocks is a standardized digital standard cell design. The basic building blocks in the target architecture were designed in 0.35μ CMOS technology; they are suitable for topological reuse and are in an automated way downscaled into a 0.18μ CMOS technology.

  14. Variation-aware adaptive voltage scaling for digital CMOS circuits

    CERN Document Server

    Wirnshofer, Martin

    2013-01-01

    Increasing performance demands in integrated circuits, together with limited energy budgets, force IC designers to find new ways of saving power. One innovative way is the presented adaptive voltage scaling scheme, which tunes the supply voltage according to the present process, voltage and temperature variations as well as aging. The voltage is adapted “on the fly” by means of in-situ delay monitors to exploit unused timing margin, produced by state-of-the-art worst-case designs. This book discusses the design of the enhanced in-situ delay monitors and the implementation of the complete control-loop comprising the monitors, a control-logic and an on-chip voltage regulator. An analytical Markov-based model of the control-loop is derived to analyze its robustness and stability. Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits provides an in-depth assessment of the proposed voltage scaling scheme when applied to an arithmetic and an image processing circuit. This book is written for engine...

  15. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  16. Sparsely-Bonded CMOS Hybrid Imager

    Science.gov (United States)

    Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Sun, Chao (Inventor); Jones, Todd J. (Inventor); Dickie, Matthew R. (Inventor); Nikzad, Shouleh (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Newton, Kenneth W. (Inventor); Pain, Bedabrata (Inventor)

    2015-01-01

    A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

  17. Evaluation of a scientific CMOS camera for astronomical observations

    Institute of Scientific and Technical Information of China (English)

    Peng Qiu; Yong-Na Mao; Xiao-Meng Lu; E Xiang; Xiao-Jun Jiang

    2013-01-01

    We evaluate the performance of the first generation scientific CMOS (sCMOS) camera used for astronomical observations.The sCMOS camera was attached to a 25 cm telescope at Xinglong Observatory,in order to estimate its photometric capabilities.We further compared the capabilities of the sCMOS camera with that of full-frame and electron multiplying CCD cameras in laboratory tests and observations.The results indicate the sCMOS camera is capable of performing photometry of bright sources,especially when high spatial resolution or temporal resolution is desired.

  18. TGV32: A 32-channel preamplifier chip for the multiplicity vertex detector at PHENIX

    Energy Technology Data Exchange (ETDEWEB)

    Britton, C.L. Jr.; Ericson, M.N.; Frank, S.S. [and others

    1997-12-31

    The TGV32, a 32-channel preamplifier-multiplicity discriminator chip for the Multiplicity Vertex Detector (MVD) at PHENIX, is a unique silicon preamplifier in that it provides both an analog output for storage in an analog memory and a weighted summed-current output for conversion to a channel multiplicity count. The architecture and test results of the chip are presented. Details about the design of the preamplifier, discriminator, and programmable digital-analog converters (DACs) performance as well as the process variations are presented. The chip is fabricated in a 1.2-{micro}m, n-well, CMOS process.

  19. Methodology of Efficient Energy Design for Noisy Deep Submicron VLSI Chips

    Institute of Scientific and Technical Information of China (English)

    WANGJun

    2004-01-01

    Power dissipation is becoming increasingly important as technology continues to scale. This paper describes a way to consider the dynamic, static and shortcircuit power dissipation simultaneously for making complete, quantitative prediction on the total power dissipation of noisy VLSI chip. Especially, this new method elucidates the mechanism of power dissipation caused by the intrinsic noise of deep submicron VLSI chip. To capture the noise dependency of efficient energy design strategies for VLSI chip, the simulation of two illustrative cases are observed. Finally, the future works are proposed for the optimum tradeoff among the power, speed and area, which includes the use of floating-body partially depleted silicon-on-insulator CMOS technology.

  20. A 5.4mW GPS CMOS quadrature front-end based on a single-stage LNA-mixer-VCO

    DEFF Research Database (Denmark)

    Liscidini, Amtonio; Mazzanti, Andrea; Tonietto, Riccardo

    2006-01-01

    A GPS RF front-end combines the LNA, mixer, and VCO in a single stage and can operate from a 1.2V supply. The chip is implemented in a 0.13um CMOS process and occupies 1.5mm2 active area. It consumes 5.4mW with a 4.8dB NF, 36dB gain, and a P1dB of -31dBm.......A GPS RF front-end combines the LNA, mixer, and VCO in a single stage and can operate from a 1.2V supply. The chip is implemented in a 0.13um CMOS process and occupies 1.5mm2 active area. It consumes 5.4mW with a 4.8dB NF, 36dB gain, and a P1dB of -31dBm....

  1. Design of Low Power CMOS Circuits using Leakage Control Transistor and Multi-Threshold CMOS Techniques

    OpenAIRE

    2012-01-01

    The scaling down of technology in CMOS circuits, results in the down scaling of threshold voltage thereby increasing the sub-threshold leakage current. An IC consists of many circuits of which some circuits consists critical path like full adder, whereas some circuits like multiplexer and decoder has no specified critical path. LECTOR is a technique for designing leakage power reduced CMOS circuits without affecting the dynamic power dissipation, which can be used for circuits with no specifi...

  2. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  3. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  4. Low power SEU immune CMOS memory circuits

    Science.gov (United States)

    Liu, M. N.; Whitaker, Sterling

    1992-01-01

    The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

  5. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern mul

  6. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique...

  7. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  8. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  9. Fully CMOS-compatible titanium nitride nanoantennas

    Science.gov (United States)

    Briggs, Justin A.; Naik, Gururaj V.; Petach, Trevor A.; Baum, Brian K.; Goldhaber-Gordon, David; Dionne, Jennifer A.

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  10. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  11. Analog IC reliability in nanometer CMOS

    CERN Document Server

    Maricau, Elie

    2013-01-01

    This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.   The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.   ·         Enables readers to understand long-term reliability of an integrated circuit; ·         Reviews CMOS unreliability effects, with focus on those that will emerge in future CMOS nodes; ·         Provides overview of models for...

  12. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.;

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation...

  13. CMOS VHF transconductance-C lowpass filter

    NARCIS (Netherlands)

    Nauta, B.

    1990-01-01

    Experimental results of a VHF CMOS transconductance-C lowpass filter are described. The filter is built with transconductors as published earlier. The cutoff frequency can be tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response

  14. Linear CMOS transconductance element for VHF filters

    NARCIS (Netherlands)

    Nauta, B.; Seevinck, E.

    1989-01-01

    A differential transconductance element based on CMOS inverters is presented. With this circuit a linear, tunable integrator for very high-frequency continuous-time integrated filters can be made. This integrator has good linearity properties (THD<0.04%, Vipp=1.8 V), nondominant poles in the gigaher

  15. Method and circuitry for CMOS transconductor linearization

    NARCIS (Netherlands)

    Kundur Subramaniyan, Harish; Klumperink, Eric; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transisto

  16. A 2x2 W-Band Reference Time-Shifted Phase-Locked Transmitter Array in 65nm CMOS Technology

    Science.gov (United States)

    Tang, Adrian; Virbila, Gabriel; Hsiao, Frank; Wu, Hao; Murphy, David; Mehdi, Imran; Siegel, P. H.; Chang, M-C. Frank

    2013-01-01

    This paper presents a complete 2x2 phased array transmitter system operating at W-band (90-95 GHz) which employs a PLL reference time-shifting approach instead of using traditional mm-wave phase shifters. PLL reference shifting enables a phased array to be distributed over multiple chips without the need for coherent mm-wave signal distribution between chips. The proposed phased array transmitter system consumes 248 mW per array element when implemented in a 65 nm CMOS technology.

  17. Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation.

    Science.gov (United States)

    Loke, Desmond; Skelton, Jonathan M; Chong, Tow-Chong; Elliott, Stephen R

    2016-12-21

    One of the requirements for achieving faster CMOS electronics is to mitigate the unacceptably large chip areas required to steer heat away from or, more recently, toward the critical nodes of state-of-the-art devices. Thermal-guiding (TG) structures can efficiently direct heat by "meta-materials" engineering; however, some key aspects of the behavior of these systems are not fully understood. Here, we demonstrate control of the thermal-diffusion properties of TG structures by using nanometer-scale, CMOS-integrable, graphene-on-silica stacked materials through finite-element-methods simulations. It has been shown that it is possible to implement novel, controllable, thermally based Boolean-logic and spike-timing-dependent plasticity operations for advanced (neuromorphic) computing applications using such thermal-guide architectures.

  18. CLARO-CMOS, an ASIC for single photon counting with Ma-PMTs, MCPs and SiPMs

    Science.gov (United States)

    Carniti, P.; Cibinetto, G.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Maino, M.; Malaguti, R.; Pessina, G.

    2013-01-01

    An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The prototype was realized in a .35 μm CMOS technology and has four channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation and the low power dissipation, below 1 mW per channel. This paper focuses on the use of the CLARO for SiPM readout. The ASIC was tested with several SiPMs of various sizes, connected to the input of the chip both directly and through a coaxial cable about one meter long. In the latter case the ASIC is still fully functional although the speed of response is affected by the cable capacitance. The threshold could be set just above the single photoelectron level, and with 1 ×1 mm2 SiPMs the discrete photoelectron peaks could be well resolved.

  19. A Low Power Op Amp for 3-Bit Digital to Analog Converter in 0.18 µm CMOS Process

    Directory of Open Access Journals (Sweden)

    Noor A.B.A. Taib

    2013-03-01

    Full Text Available Digital to (DAC is used to get analog voltage corresponding to input digital data in VLSI circuit design with greater integration levels. However, providing linear current and voltage outputs with the use of strictly CMOS devices presents the need for a low power operational amplifier (op-amp circuit. In this research, the analysis of op-amp circuit for 3-bit DAC is illustrated. In order to reduce the power dissipation, weighted resistor is utilized in the proposed design. To design the op-amp circuit for 3-bit DAC, the design has been implemented in CEDEC 0.18 µm CMOS process. The simulated result shows that, under 8 V as the supply voltage the total power dissipation for the proposed DAC is 43.6 nW. Moreover, 143.17 µm is found as the total chip area of the designed op-amp circuit for 3-bit DAC.

  20. CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

    Science.gov (United States)

    Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

    2016-04-01

    This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

  1. A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation

    Institute of Scientific and Technical Information of China (English)

    Zhou Qianneng; Wang Yongsheng; Lai Fengchang

    2009-01-01

    A capacitor-free CMOS low-dropout(LDO)regulator for system-on-chip(SoC)applications is presented.By adopting AC-boosting and active-feedback frequency compensation(ACB-AFFC),the proposed LDO enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high.The LDO regulator is designed and fabricated in a 0.6/am CMOS process.The active silicon area is only 770×472μm2.Experimental results show that the total error of the output voltage due to line variation is less than ±0.1 97%.The load regulation is only 0.35 mV/mA when the load current changes fromoto 100mA.

  2. A 150-nA 13.4-ppm/℃ switched-capacitor CMOS sub-bandgap voltage reference*

    Institute of Scientific and Technical Information of China (English)

    Yan Wei; Li Wenhong; Liu Ran

    2011-01-01

    A nanopower switched-capacitor CMOS sub-bandgap voltage reference has been implemented using a Chartered 0.35-μm 3.3-V/5-V dual gate mixed-signal CMOS process The proposed circuit generates a precise sub-bandgap voltage of l V. The temperature coefficient of the output voltage is 13.4 ppm/℃ with the temperature varying from-20 to 80 ℃ The proposed circuit operates properly with the supply voltage down to 1.3 V, and consumes 150 nA at room temperature. The line regulation is 0.27%/V The power supply rejection ratio at 100 Hz and l MHz is -39 dB and 51 dB, respectively. The chip area is 0.2 mm2.

  3. Self-powered integrated systems-on-chip (energy chip)

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-04-23

    In today\\'s world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

  4. A $(128f_s)$ multi-bit ΣΔ CMOS audio DAC with real-time DEM and 115dB SFDR

    NARCIS (Netherlands)

    Tuijl, van Ed; Homberg, van den John; Reefman, Derk; Bastiaansen, Corné; Dussen, van der Leon

    2004-01-01

    A continuous-time 5b ΣΔ audio DAC operates at 5.65MS/s $(128f_s)$. SFDR of -115dB and noise of -119dB (unweighted) are achieved by realtime DEM that cancels mismatch completely in each sample. Chip area is $2mm^2$ in a 0.18μm, thick oxide 3.3V CMOS process. Total power consumption is 150mW.

  5. Automatic Synthesis of CMOS Algorithmic Analog To-Digital Converter.

    Science.gov (United States)

    Jusuf, Gani

    The steady decrease in technological feature size is allowing increasing levels of integration in analog/digital interface functions. These functions consist of analog as well as digital circuits. While the turn around time for an all digital IC chip is very short due to the maturity of digital IC computer-aided design (CAD) tools over the last ten years, most analog circuits have to be designed manually due to the lack of analog IC CAD tools. As a result, analog circuit design becomes the bottleneck in the design of mixed signal processing chips. One common analog function in a mixed signal processing chip is an analog-to-digital conversion (ADC) function. This function recurs frequently but with varying performance requirements. The objective of this research is to study the design methodology of a compilation program capable of synthesizing ADC's with a broad range of sampling rates and resolution, and silicon area and performance comparable with the manual approach. The automatic compilation of the ADC function is a difficult problem mainly because ADC techniques span such a wide spectrum of performance, with radically different implementations being optimum for different ranges of conversion range, resolution, and power dissipation. We will show that a proper choice of the ADC architectures and the incorporation of many analog circuit design techniques will simplify the synthesis procedure tremendously. Moreover, in order to speed up the device sizing, hierarchical optimization procedure and behavioral simulation are implemented into the ADC module generation steps. As a result of this study, a new improved algorithmic ADC without the need of high precision comparators has been developed. This type of ADC lends itself to automatic generation due to its modularity, simplicity, small area consumption, moderate speed, low power dissipation, and single parameter trim capability that can be added at high resolution. Furthermore, a performance-driven CMOS ADC module

  6. Experiment list: SRX199896 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available SRX199896 hg19 TFs and others CTCF Neural HA-sp Tissue=spinal cord|Lineage=ectoderm...cell=HA-sp || cell organism=human || cell description=astrocytes spinal cord || cell karyotype=normal || cel...|Description=astrocytes spinal cord 22728620,71.6,5.9,33283 GSM1022668: UW ChipSeq HA-sp CTCFRep2 source_nam

  7. A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro.

    Science.gov (United States)

    Tateno, Takashi; Nishikawa, Jun

    2014-01-01

    In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

  8. A CMOS IC–based multisite measuring system for stimulation and recording in neural preparations in vitro

    Directory of Open Access Journals (Sweden)

    Takashi eTateno

    2014-10-01

    Full Text Available In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS integrated circuit (IC chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 mm × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA, and a PC. To test the system, microelectrode arrays (MEAs were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μV root mean square (10 Hz to 100 kHz, which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μVpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

  9. [An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

    Science.gov (United States)

    Balashov, A M; Selishchev, S V

    2004-01-01

    An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

  10. A dual-mode secure UHF RFID tag with a crypto engine in 0.13-μm CMOS

    Science.gov (United States)

    Tao, Yang; Linghao, Zhu; Xi, Tan; Junyu, Wang; Lirong, Zheng; Hao, Min

    2016-07-01

    An ultra-high-frequency (UHF) radio frequency identification (RFID) secure tag chip with a non-crypto mode and a crypto mode is presented. During the supply chain management, the tag works in the non-crypto mode in which the on-chip crypto engine is not enabled and the tag chip has a sensitivity of -12.8 dBm for long range communication. At the point of sales (POS), the tag will be switched to the crypto mode in order to protect the privacy of customers. In the crypto mode, an advanced encryption standard (AES) crypto engine is enabled and the sensitivity of the tag chip is switched to +2 dBm for short range communication, which is a method of physical protection. The tag chip is implemented and verified in a standard 0.13-μm CMOS process. Project supported by the National Science & Technology Pillar Program of China (No. 2015BAK36B01).

  11. Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

    Science.gov (United States)

    Liu, Yu-Chia; Tsai, Ming-Han; Tang, Tsung-Lin; Fang, Weileun

    2011-10-01

    This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

  12. Current-Mode CMOS A/D Converter for pA to nA Input Currents

    DEFF Research Database (Denmark)

    Breten, Madalina; Lehmann, Torsten; Bruun, Erik

    1999-01-01

    . A prototype chip using the dual slope conversion method has been fabricated in a 0.7micron CMOS process. Experimental results from this converter are reported. Design problems and limitations of the converter are discussed and a new conversion technique providing a larger dynamic range and easy calibration......This paper describes a current mode A/D converter designed for a maximum input current range of 5nA and a resolution of the order of 1pA. The converter is designed for a potentiostat for amperometric chemical sensors and provides a constant polarization voltage for the measuring electrode...

  13. Analysis, design and implementation of analog/RF blocks suitable for a multi-band analog interface for CMOS SOCs

    OpenAIRE

    2008-01-01

    O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula ana...

  14. A four-channel, low-power CMOS charge preamplifier for silicon detectors with medium value of capacitance

    Energy Technology Data Exchange (ETDEWEB)

    Randazzo, N.; Russo, G.V.; Presti, D. Lo; Panebianco, S.; Petta, C.; Reito, S.

    1997-02-01

    The authors present a low-power CMOS charge preamplifier, suitable for use with silicon detectors having a medium value of capacitance. Noise considerations and a long decay time of the output signal command the use of unusually large devices such as an input transistor having W = 10,000 {micro}m and a 7-M{Omega} feedback resistor. Both of these devices were integrated inside the chip. They present and compare theoretical predictions together with the results of post-layout simulation and the measurements obtained.

  15. Digital Power Consumption Estimations for CHIPIX65 Pixel Readout Chip

    CERN Document Server

    Marcotulli, Andrea

    2016-01-01

    New hybrid pixel detectors with improved resolution capable of dealing with hit rates up to 3 GHz/cm2 will be required for future High Energy Physics experiments in the Large Hadron Collider (LHC) at CERN. Given this, the RD53 collaboration works on the design of the next generation pixel readout chip needed for both the ATLAS and CMS detector phase 2 pixel upgrades. For the RD53 demonstrator chip in 65nm CMOS technology, different architectures are considered. In particular the purpose of this work is estimating the power consumption of the digital architecture of the readout ASIC developed by CHIPIX65 project of the INFN National Scientific Committee. This has been done with modern chip design tools integrated with the VEPIX53 simulation framework that has been developed within the RD53 collaboration in order to assess the performance of the system in very high rate, high energy physics experiments.

  16. CMOS compatible nanoscale nonvolatile resistance switching memory.

    Science.gov (United States)

    Jo, Sung Hyun; Lu, Wei

    2008-02-01

    We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), long endurance (10(6)), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications.

  17. Noise in a CMOS digital pixel sensor

    Institute of Scientific and Technical Information of China (English)

    Zhang Chi; Yao Suying; Xu Jiangtao

    2011-01-01

    Based on the study of noise performance in CMOS digital pixel sensor (DPS),a mathematical model of noise is established with the pulse-width-modulation (PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region.In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.

  18. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

  19. Deep n-well MAPS in a 130 nm CMOS technology: Beam test results

    Energy Technology Data Exchange (ETDEWEB)

    Neri, N., E-mail: nicola.neri@pi.infn.i [Universita degli Studi di Pisa and INFN-Pisa (Italy); Avanzini, C.; Batignani, G.; Bettarini, S.; Bosi, F.; Ceccanti, M.; Cenci, R.; Cervelli, A.; Crescioli, F.; Dell' Orso, M.; Forti, F.; Giannetti, P.; Giorgi, M.A.; Gregucci, S.; Mammini, P.; Marchiori, G.; Massa, M.; Morsani, F.; Paoloni, E.; Piendibene, M. [Universita degli Studi di Pisa and INFN-Pisa (Italy)

    2010-11-01

    We report on recent beam test results for the APSEL4D chip, a new deep n-well MAPS prototype with a full in-pixel signal processing chain obtained by exploiting the triple well option of the CMOS 0.13{mu}m process. The APSEL4D chip consists of a 4096 pixel matrix (32 rows and 128 columns) with 50x50{mu}m{sup 2} pixel cell area, with custom readout architecture capable of performing data sparsification at pixel level. APSEL4D has been characterized in terms of charge collection efficiency and intrinsic spatial resolution under different conditions of discriminator threshold settings using a 12 GeV/c proton beam in the T9 area of the CERN PS. We observe a maximum hit efficiency of 92% and we estimate an intrinsic resolution of about 14{mu}m. The data driven approach of the tracking detector readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on associative memories. The analysis of the beam test data is critically reviewed along with the characterization of the device under test.

  20. Development of a multi-analyte CMOS sensor for point-of-care testing

    Directory of Open Access Journals (Sweden)

    Holger Klapproth

    2015-09-01

    Full Text Available A typical microarray experiment requires both a biochip on which the biological reactions take place and a microarray scanner for analysis and visualization of the data. Here, we report on the generation of a chip, which consists of a CMOS photodiode array onto which receptors are immobilized and which are used for the detection and quantification of proteins in sera solution. Such an approach allows direct electronic read-out of the chip via a computer port so that the size of the whole analytical setup is very compact, opening the avenue to the generation of simple handheld devices. ELISA reactions directly performed on the surface of the photodiode arrays are used to measure a number of serum factors with a broad range in concentrations of samples with volumes of less than 10 μl. As in physiological sera analyte concentrations of the different parameters vary frequently by several orders of magnitude, parallel competitive reactions are used to adjust the dynamic range of several ELISA tests on the chip. We show as a demonstration case that this allows to quantify simultaneously C-reactive protein, Immunoglobulin E, Cystatin C, Myoglobin and Ferritin in a single assay.

  1. Systematic study of packaging designs on the performance of CMOS thermoresistive micro calorimetric flow sensors

    Science.gov (United States)

    Xu, Wei; Pan, Liang; Gao, Bo; Chiu, Yi; Xu, Kun; Lee, Yi-Kuen

    2017-08-01

    We systematically study the effect of two packaging configurations for the CMOS thermoresistive micro calorimetric flow (TMCF) sensors: S-type with the sensor chip protrusion-mounted on the flow channel wall and E-type with the sensor chip flush-mounted on the flow channel wall. Although the experimental results indicated that the sensitivity of the S-type was increased by more than 30%; the corresponding flow range as compared to the E-type was dramatically reduced by 60% from 0-11 m s-1 to 0-4.5 m s-1. Comprehensive 2D CFD simulation and in-house developed 3D numerical simulations based on the gas-kinetic scheme were applied to study the flow separation of these two packaging designs with the major parameters. Indeed, the S-type design with the large protrusion would change the local convective heat transfer of the TMCF sensor and dramatically decrease the sensors’ performance. In addition, parametric CFD simulations of the packaging designs provide inspiration to propose a novel general flow regime map (FRM), i.e. normalized protrusion d * versus reduced chip Reynolds number Re*, where the critical boundary curve for the flow separation of TMCF sensors was determined at different channel aspect ratios. The proposed FRM can be a useful guideline for the packaging design and manufacturing of different micro thermal flow sensors.

  2. CMOS current amplifiers : speed versus nonlinearity

    OpenAIRE

    2000-01-01

    This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered. For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived tha...

  3. CMOS Design of Ternary Arithmetic Devices

    Institute of Scientific and Technical Information of China (English)

    吴训威; F.Prosser

    1991-01-01

    This paper presents CMOS circuit designs of a ternary adder and a ternary multiplier,formulated using transmission function theory.Binary carry signals appearing in these designs allow conventional look-ahead carry techniques to be used.compared with previous similar designs,the circuits proposed in this paper have advantages such as low dissipation,low output impedance,and simplicity of construction.

  4. CMOS Camera Array With Onboard Memory

    Science.gov (United States)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  5. Advanced CMOS Radiation Effects Testing and Analysis

    Science.gov (United States)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  6. CMOS imagers from phototransduction to image processing

    CERN Document Server

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  7. Efficient design of CMOS TSC checkers

    Science.gov (United States)

    Biddappa, Anita; Shamanna, Manjunath K.; Maki, Gary; Whitaker, Sterling

    1990-01-01

    This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

  8. A logarithmic low dark current CMOS pixel

    Science.gov (United States)

    Brunetti, Alessandro Michel; Choubey, Bhaskar

    2016-04-01

    High dynamic range pixels are required in a number of automotive and scientific applications. CMOS pixels provide different approaches to achieve this. However, these suffer from poor performance under low light conditions due to inherently high leakage current that is present in CMOS processes, also known as dark current. The typical approach to reduce this dark current involves process modifications. Nevertheless, energy considerations suggest that the leakage current will be close to zero at a close to zero voltage on the photodiode. Hence, the reduction in dark current can be achieved by forcing a zero voltage across the photodiode. In this paper, a novel logarithmic CMOS pixel design capable of reducing dark current without any process modifications is proposed. This pixel is also able to produce a wide dynamic range response. This circuit utilizes two current mirrors to force the in-pixel photodiode at a close to zero voltage. Additionally, a bias voltage is used to reduce a higher order effect known as Drain Induced Barrier Lowering (DIBL). In fact, the contribution of this effect can be compensated by increasing the body effect. In this paper, we studied the consequences of a negative bias voltage applied to the body of the current mirror pair to compensate for the DIBL effect thereby achieving a very small voltage drop on the photodiode and consequently, a higher sensitivity in low light conditions.

  9. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    Science.gov (United States)

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-11-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

  10. Optical design of microlens array for CMOS image sensors

    Science.gov (United States)

    Zhang, Rongzhu; Lai, Liping

    2016-10-01

    The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

  11. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  12. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 μm CMOS

    Science.gov (United States)

    Bin, Wu; Yumei, Zhou; Yongxu, Zhu; Zhengdong, Zhang; Jingjing, Cai

    2011-05-01

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 μm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 × 2.6 mm2 area and consumes 83 mW under typical work modes.

  13. A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

    Science.gov (United States)

    Niansong, Mei; Yu, Sun; Bo, Lu; Yaohua, Pan; Yumei, Huang; Zhiliang, Hong

    2011-03-01

    This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL). An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL. We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch. The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply. The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and -118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset, respectively; and the reference frequency spur is below -77 dBc. The chip size is 0.32 mm2 and the power consumption is 30.6 mW.

  14. A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

    Institute of Scientific and Technical Information of China (English)

    Mei Niansong; Sun Yu; Lu Bo; Pan Yaohua; Huang Yumei; Hong Zhiliang

    2011-01-01

    This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and-118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset,respectively; and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.

  15. A high-sensitivity 135 GHz millimeter-wave imager by compact split-ring-resonator in 65-nm CMOS

    Science.gov (United States)

    Li, Nan; Yu, Hao; Yang, Chang; Shang, Yang; Li, Xiuping; Liu, Xiong

    2015-11-01

    A high-sensitivity 135 GHz millimeter-wave imager is demonstrated in 65 nm CMOS by on-chip metamaterial resonator: a differential transmission-line (T-line) loaded with split-ring-resonator (DTL-SRR). Due to sharp stop-band introduced by the metamaterial load, high-Q oscillatory amplification can be achieved with high sensitivity when utilizing DTL-SRR as quench-controlled oscillator to provide regenerative detection. The developed 135 GHz mm-wave imager pixel has a compact core chip area of 0.0085 mm2 with measured power consumption of 6.2 mW, sensitivity of -76.8 dBm, noise figure of 9.7 dB, and noise equivalent power of 0.9 fW/√{HZ } Hz. Millimeter-wave images has been demonstrated with millimeter-wave imager integrated with antenna array.

  16. UHF power amplifier design in 0.35μm SiGe BiCMOS

    Institute of Scientific and Technical Information of China (English)

    Song Jiayou; Li Zhiqun; Wang Zhigon

    2009-01-01

    A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz's 0.35μm SiGe BiCMOS process. It was fully integrated excluding the inductors and the output matching network. Under a single 3.3V supply voltage, the off-chip bonding test results indicated that the circuit has a small signal gain of more than 24dB, the input and output reflectance are less than -24dB and -10dB, respectively, and the maximal output power is 23.5 dBm. At output power of 23.1 dBm, the PAE (power added efficiency) is 30.2%, the IMD2 and IMD3 are less than -32 dBc and -46 dBc, respectively. The chip size is 1.27mm×0.9mm.

  17. A 434/868 MHz CMOS low-IF receiver with I/Q imbalance calibration for SRDs application

    Institute of Scientific and Technical Information of China (English)

    Li Juan; Zhao Feng; Ye Guojing; Hong Zhiliang

    2009-01-01

    A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier (PA), frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR (image rejection ratio) so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of--60 dBm and a control gain of 60 dB. The S reaches-20 dB at 433 MHz and-10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm2 including the bias circuit.

  18. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 {mu}m CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Wu Bin; Zhou Yumei; Zhu Yongxu; Zhang Zhengdong; Cai Jingjing, E-mail: wubin@ime.ac.cn [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2011-05-15

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 {mu}m 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 x 2.6 mm{sup 2} area and consumes 83 mW under typical work modes. (semiconductor integrated circuits)

  19. sCMOS detector for imaging VNIR spectrometry

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  20. A novel CMOS transducer for giant magnetoresistance sensors

    Science.gov (United States)

    Luong, Van Su; Lu, Chih-Cheng; Yang, Jing-Wen; Jeng, Jen-Tzong

    2017-02-01

    In this work, an ASIC (application specific integrated circuits) transducer circuit for field modulated giant magnetoresistance (GMR) sensors was designed and fabricated using a 0.18-μ m CMOS process. The transducer circuits consist of a frequency divider, a digital phase shifter, an instrument amplifier, and an analog mixer. These comprise a mix of analog and digital circuit techniques. The compact chip size of 1.5 mm × 1.5 mm for both analog and digital parts was achieved using the TSMC18 1P6M (1-polysilicon 6-metal) process design kit, and the characteristics of the system were simulated using an HSpice simulator. The output of the transducer circuit is the result of the first harmonic detection, which resolves the modulated field using a phase sensitive detection (PSD) technique and is proportional to the measured magnetic field. When the dual-bridge GMR sensor is driven by the transducer circuit with a current of 10 mA at 10 kHz, the observed sensitivity of the field sensor is 10.2 mV/V/Oe and the nonlinearity error was 3% in the linear range of ±1 Oe. The performance of the system was also verified by rotating the sensor system horizontally in earth's magnetic field and recording the sinusoidal output with respect to the azimuth angle, which exhibits an error of less than ±0.04 Oe. These results prove that the ASIC transducer is suitable for driving the AC field modulated GMR sensors applied to geomagnetic measurement.