WorldWideScience

Sample records for cmos image sensors

  1. Large area CMOS image sensors

    Science.gov (United States)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  2. CMOS Image Sensors for High Speed Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2009-01-01

    Full Text Available Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps.

  3. CMOS Image Sensors for High Speed Applications.

    Science.gov (United States)

    El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

  4. Design and realization of CMOS image sensor

    Science.gov (United States)

    Xu, Jian; Xiao, Zexin

    2008-02-01

    A project was presented that instrumental design of an economical CMOS microscope image sensor. A high performance, low price, black-white camera chip OV5116P was used as the core of the sensor circuit; Designing and realizing peripheral control circuit of sensor; Through the control on dial switch to realize different functions of the sensor chip in the system. For example: auto brightness level descending function on or off; gamma correction function on or off; auto and manual backlight compensation mode conversion and so on. The optical interface of sensor is designed for commercialization and standardization. The images of sample were respectively gathered with CCD and CMOS. Result of the experiment indicates that both performances were identical in several aspects as follows: image definition, contrast control, heating degree and the function can be adjusted according to the demand of user etc. The imperfection was that the CMOS with smaller field and higher noise than CCD; nevertheless, the maximal advantage of choosing the CMOS chip is its low cost. And its imaging quality conformed to requirement of the economical microscope image sensor.

  5. Noise in sub-micron CMOS image sensors

    NARCIS (Netherlands)

    Wang, X.

    2008-01-01

    CMOS image sensors are devices that convert illumination signals (light intensity) into electronic signals. The goal of this thesis has been to analyze dominate noise sources in CMOS imagers and to improve the image quality by reducing the noise generated in the CMOS image sensor pixels.

  6. DESIGN AND IMPLEMETTATION OF CMOS IMAGE SENSOR

    Institute of Scientific and Technical Information of China (English)

    Liu Yu; Wang Guoyu

    2007-01-01

    A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.

  7. A Biologically Inspired CMOS Image Sensor

    CERN Document Server

    Sarkar, Mukul

    2013-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The eye is a compound of individual lenses with their own photoreceptor arrays.  The visual system of insects allows them to fly with a limited intelligence and brain processing power. A CMOS image sensor replicating the perception of vision in insects is discussed and designed in this book for industrial (machine vision) and medical applications. The CMOS metal layer is used to create an embedded micro-polarizer able to sense polarization information. This polarization information is shown to be useful in applications like real time material classification and autonomous agent navigation. Further the sensor is equipped with in pixel analog and digital memories which allow variation of the dynamic range and in-pixel b...

  8. Charge-Transfer CMOS Image Sensors: Device and Radiation Aspects

    NARCIS (Netherlands)

    Ramachandra Rao, P.

    2009-01-01

    The aim of this thesis was twofold: investigating the effect of ionizing radiation on 4-T CMOS image sensors and the possibility of realizing a CCD like sensor in standard 0.18-μm CMOS technology (for medical applications). Both the aims are complementary; borrowing and lending many aspects of radia

  9. CMOS image sensor with contour enhancement

    Science.gov (United States)

    Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

    2010-10-01

    Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

  10. Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    JIN Xiang-liang; CHEN Jie(member,IEEE); QIU Yu-lin

    2003-01-01

    With the scaling development of the minimum lithographic size,the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule.When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD image pixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35 μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction,which results in pixel crosstalk.The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling.Some suppressed crosstalk methods have been reviewed.The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.

  11. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    Science.gov (United States)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  12. Optical design of microlens array for CMOS image sensors

    Science.gov (United States)

    Zhang, Rongzhu; Lai, Liping

    2016-10-01

    The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

  13. Design and fabrication of vertically-integrated CMOS image sensors.

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

  14. A CMOS image sensor with row and column profiling means

    NARCIS (Netherlands)

    Xie, N.; Theuwissen, A.J.P.; Wang, X.; Leijtens, J.A.P.; Hakkesteegt, H.; Jansen, H.

    2008-01-01

    This paper describes the implementation and firstmeasurement results of a new way that obtains row and column profile data from a CMOS Image Sensor, which is developed for a micro-Digital Sun Sensor (μDSS).The basic profiling action is achieved by the pixels with p-type MOS transistors which realize

  15. On noise in time-delay integration CMOS image sensors

    Science.gov (United States)

    Levski, Deyan; Choubey, Bhaskar

    2016-05-01

    Time delay integration sensors are of increasing interest in CMOS processes owing to their low cost, power and ability to integrate with other circuit readout blocks. This paper presents an analysis of the noise contributors in current day CMOS Time-Delay-Integration image sensors with various readout architectures. An analysis of charge versus voltage domain readout modes is presented, followed by a noise classification of the existing Analog Accumulator Readout (AAR) and Digital Accumulator Readout (DAR) schemes for TDI imaging. The analysis and classification of existing readout schemes include, pipelined charge transfer, buffered direct injection, voltage as well as current-mode analog accumulators and all-digital accumulator techniques. Time-Delay-Integration imaging modes in CMOS processes typically use an N-number of readout steps, equivalent to the number of TDI pixel stages. In CMOS TDI sensors, where voltage domain readout is used, the requirements over speed and noise of the ADC readout chain are increased due to accumulation of the dominant voltage readout and ADC noise with every stage N. Until this day, the latter is the primary reason for a leap-back of CMOS TDI sensors as compared to their CCD counterparts. Moreover, most commercial CMOS TDI implementations are still based on a charge-domain readout, mimicking a CCD-like operation mode. Thus, having a good understanding of each noise contributor in the signal chain, as well as its magnitude in different readout architectures, is vital for the design of future generation low-noise CMOS TDI image sensors based on a voltage domain readout. This paper gives a quantitative classification of all major noise sources for all popular implementations in the literature.

  16. 77 FR 74513 - Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations...

    Science.gov (United States)

    2012-12-14

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain CMOS Image Sensors and Products Containing Same; Investigations: Terminations... importation, and the sale within the United States after importation of certain CMOS image sensors and...

  17. Research-grade CMOS image sensors for demanding space applications

    Science.gov (United States)

    Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

    2004-06-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

  18. Research-grade CMOS image sensors for remote sensing applications

    Science.gov (United States)

    Saint-Pe, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Martin-Gonthier, Philippe; Corbiere, Franck; Belliot, Pierre; Estribeau, Magali

    2004-11-01

    Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding space applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this paper will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments and performances of CIS prototypes built using an imaging CMOS process will be presented in the corresponding section.

  19. Contact CMOS imaging of gaseous oxygen sensor array.

    Science.gov (United States)

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O2) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O2-sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp)3](2+)) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  20. 77 FR 26787 - Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint...

    Science.gov (United States)

    2012-05-07

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Notice of Receipt of Complaint... complaint entitled Certain CMOS Image Sensors and Products Containing Same, DN 2895; the Commission is... importation of certain CMOS image sensors and products containing same. The complaint names as...

  1. CMOS image sensors as an efficient platform for glucose monitoring.

    Science.gov (United States)

    Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

    2013-10-07

    Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications.

  2. A Single-Transistor Active Pixel CMOS Image Sensor Architecture

    Institute of Scientific and Technical Information of China (English)

    ZHANG Guo-An; ZHANG Dong-Wei; HE Jin; SU Yan-Mei; WANG Cheng; CHEN Qin; LIANG Hai-Lang; YE Yun

    2012-01-01

    A single-transistor CMOS active pixel image sensor (1T CMOS APS) architecture is proposed,By switching the photosensing pinned diode,resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus,the reset and selected transistors can be removed. In addition,the reset and selected signal lines can be shared to reduce the metal signal line,leading to a very high fill factor.The pixel design and operation principles are discussed in detail.The functionality of the proposed 1 T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology.

  3. Photon detection with CMOS sensors for fast imaging

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J. [IPHC, Universite Louis Pasteur, CNRS/IN2P3, BP 28, F-67037 Strasbourg (France)], E-mail: baudot@in2p3.fr; Dulinski, W.; Winter, M. [IPHC, Universite Louis Pasteur, CNRS/IN2P3, BP 28, F-67037 Strasbourg (France); Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N. [Universite de Lyon, Universite Lyon 1, Lyon, F-69003 (France); Institut de Physique Nucleaire de Lyon, CNRS/IN2P3, Villeurbanne, F-69622 (France)

    2009-06-01

    Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e{sup -}, and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of 100{mu}s have been reached for 100 kilo-pixels sensors. These aspects of CMOS sensors are attractive for applications in photon imaging. For X-rays of a few keV, the efficiency is limited to a few % due to the thin sensitive volume. For visible photons, the back-thinned version of CMOS sensor is sensitive to low intensity sources, of a few hundred photons. When a back-thinned CMOS sensor is combined with a photo-cathode, a new hybrid detector results (EBCMOS) and operates as a fast single photon imager. The first EBCMOS was produced in 2007 and demonstrated single photon counting with low dark current capability in laboratory conditions. It has been compared, in two different biological laboratories, with existing CCD-based 2D cameras for fluorescence microscopy. The current EBCMOS sensitivity and frame rate is comparable to existing EMCCDs. On-going developments aim at increasing this frame rate by, at least, an order of magnitude. We report in conclusion, the first test of a new CMOS sensor, LUCY, which reaches 1000 frames per second.

  4. Reducing crosstalk in vertically integrated CMOS image sensors

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2010-01-01

    Image sensors can benefit from 3D IC fabrication methods because photodetectors and electronic circuits may be fabricated using significantly different processes. When fabricating the die that contains the photodetectors, it is desirable to avoid pixel level patterning of the light sensitive semiconductor. But without a physical border between adjacent photodetectors, lateral currents may flow between neighboring devices, which is called "crosstalk". This work introduces circuits that can be used to reduce crosstalk in vertically-integrated (VI) CMOS image sensors with an unpatterned photodetector array. It treats the case of a VI-CMOS image sensor composed of a silicon die with CMOS read-out circuits and a transparent die with an unpatterned array of photodetectors. A reduction in crosstalk can be achieved by maintaining a constant electric potential at all nodes, at which the photodetector array connects with the readout circuit array. This can be implemented by designing a pixel circuit that uses an operational amplifier with a logarithmic feedback to control the voltage at the input node. The work presents several optional circuit configurations for the pixel circuit, and indicates the one that is the most power efficient. Afterwards, it uses a simplified small-signal model of the pixel circuit to address stability and compensation issues. Lastly, the method is validated through circuit simulation for a standard CMOS process.

  5. New Active Digital Pixel Circuit for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.

  6. A linear stepping PGA used in CMOS image sensors

    Institute of Scientific and Technical Information of China (English)

    徐江涛; 李斌桥; 赵士彬; 李红乐; 姚素英

    2009-01-01

    A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine. The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.

  7. A Biologically Inspired CMOS Image Sensor

    NARCIS (Netherlands)

    Sarkar, M.

    2011-01-01

    Biological systems are a source of inspiration in the development of small autonomous sensor nodes. The two major types of optical vision systems found in nature are the single aperture human eye and the compound eye of insects. The latter are among the most compact and smallest vision sensors. The

  8. 77 FR 33488 - Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to...

    Science.gov (United States)

    2012-06-06

    ... COMMISSION Certain CMOS Image Sensors and Products Containing Same; Institution of Investigation Pursuant to... States after importation of certain CMOS image sensors and products containing same by reason of... image sensors and products containing same that infringe one or more of claims 1 and 2 of the `126...

  9. Design considerations for a low-noise CMOS image sensor

    Science.gov (United States)

    González-Márquez, Ana; Charlet, Alexandre; Villegas, Alberto; Jiménez-Garrido, Francisco; Medeiro, Fernando; Domínguez-Castro, Rafael; Rodríguez-Vázquez, Ángel

    2015-03-01

    This paper reports a Low-Noise CMOS Image Sensor. Low-noise operation is achieved owing to the combination of a noise-enhanced pixel, the use of a two-step ADC architecture and the analysis, and the optimization thereof, of the noise contributed by the readout channel. The paper basically gathers the sensor architecture, the ADC converter architecture, the outcome of the noise analysis and some basic characterization data. The general low-noise design framework is discussed in the companion presentation.

  10. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  11. Development of low read noise high conversion gain CMOS image sensor for photon counting level imaging

    Science.gov (United States)

    Seo, Min-Woong; Kawahito, Shoji; Kagawa, Keiichiro; Yasutomi, Keita

    2016-05-01

    A CMOS image sensor with deep sub-electron read noise and high pixel conversion gain has been developed. Its performance is recognized through image outputs from an area image sensor, confirming the capability of photoelectroncounting- level imaging. To achieve high conversion gain, the proposed pixel has special structures to reduce the parasitic capacitances around FD node. As a result, the pixel conversion gain is increased due to the optimized FD node capacitance, and the noise performance is also improved by removing two noise sources from power supply. For the first time, high contrast images from the reset-gate-less CMOS image sensor, with less than 0.3e- rms noise level, have been generated at an extremely low light level of a few electrons per pixel. In addition, the photon-counting capability of the developed CMOS imager is demonstrated by a measurement, photoelectron-counting histogram (PCH).

  12. High-stage analog accumulator for TDI CMOS image sensors

    Science.gov (United States)

    Jianxin, Li; Fujun, Huang; Yong, Zong; Jing, Gao

    2016-02-01

    The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is employed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature (PVT) variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure. Project supported by the National Natural Science Foundation of China (Nos. 61404090, 61434004).

  13. Low-Power Low-Noise CMOS Imager Design: in Micro-Digital Sun Sensor Application

    NARCIS (Netherlands)

    Xie, N.

    2012-01-01

    A digital sun sensor is superior to an analog sun sensor in aspects of resolution, albedo immunity, and integration. The proposed Micro-Digital Sun Sensor (µDSS) is an autonomous digital sun sensor which is implemented by means of a CMOS image sensor, which is named APS+. The µDSS is designed speci

  14. High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

    Science.gov (United States)

    Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

    2010-12-15

    A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging.

  15. CMOS color image sensor with overlaid organic photoconductive layers having narrow absorption band

    Science.gov (United States)

    Takada, Shunji; Ihama, Mikio; Inuiya, Masafumi; Komatsu, Takashi; Saito, Takahiro

    2007-02-01

    At EI2006, we proposed the CMOS image sensor, which was overlaid with organic photoconductive layers in order to incorporate in it large light-capturing ability of a color film owing to its multiple-layer structure, and demonstrated the pictures taken by the trial product of the proposed CMOS image sensor overlaid with an organic layer having green sensitivity. In this study, we have tried to get the optimized spectral sensitivity for the proposed CMOS image sensor by means of the simulation to minimize the color difference between the original Macbeth chart and its reproduction with the spectral sensitivity of the sensor as a parameter. As a result, it has been confirmed that the proposed CMOS image sensor with multiple-layer structure possesses high potential capability in terms of imagecapturing efficiency when it is provided with the optimized spectral sensitivity.

  16. A novel monolithic ultraviolet image sensor based on a standard CMOS process

    Institute of Scientific and Technical Information of China (English)

    Li Guike; Feng Peng; Wu Nanjian

    2011-01-01

    We present a monolithic ultraviolet (UV) image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists ofa CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16 × 16 image sensor prototype chip is implemented in a 0.18 μm standard CMOS logic process.The pixel and image sensor were measured.Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/(mJ/cm2) and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.

  17. Low-Noise CMOS Image Sensors for Radio-Molecular Imaging

    NARCIS (Netherlands)

    Chen, Y.

    2012-01-01

    This thesis presents the development of low-noise CMOS image sensors for radio-molecular imaging. The development is described in two directions: firstly, from the technology point of view to reduce the pixel noise level, and secondly from the design point of view to reduce the pixel readout circuit

  18. CMOS Image Sensor with On-Chip Image Compression: A Review and Performance Analysis

    Directory of Open Access Journals (Sweden)

    Milin Zhang

    2010-01-01

    Full Text Available Demand for high-resolution, low-power sensing devices with integrated image processing capabilities, especially compression capability, is increasing. CMOS technology enables the integration of image sensing and image processing, making it possible to improve the overall system performance. This paper reviews the current state of the art in CMOS image sensors featuring on-chip image compression. Firstly, typical sensing systems consisting of separate image-capturing unit and image-compression processing unit are reviewed, followed by systems that integrate focal-plane compression. The paper also provides a thorough review of a new design paradigm, in which image compression is performed during the image-capture phase prior to storage, referred to as compressive acquisition. High-performance sensor systems reported in recent years are also introduced. Performance analysis and comparison of the reported designs using different design paradigm are presented at the end.

  19. Single event effects in 0.18μm CMOS image sensors

    Science.gov (United States)

    Rushton, Joseph E.; Stefanov, Konstantin D.; Holland, Andrew D.; Bugnet, Henri; Mayer, Frederic; Cordrey-Gale, Matthew; Endicott, James

    2016-08-01

    CMOS image sensors are widely used on Earth and are becoming increasingly favourable for use in space. Advantages, such as low power consumption, and ever-improving imaging peformance make CMOS an attractive option. The ability to integrate camera functions on-chip, such as biasing and sequencing, simplifies designing with CMOS sensors and can improve system reliability. One potential disadvantage to the use of CMOS is the possibility of single event effects, such as single event latchup (SEL), which can cause malfunctions or even permanent destruction of the sensor. These single event effects occur in the space environment due to the high levels of radiation incident on the sensor. This work investigates the ocurrence of SEL in CMOS image sensors subjected to heavy-ion irradiation. Three devices are investigated, two of which have triple-well doping implants. The resulting latchup cross-sections are presented. It is shown that using a deep p well on 18 μm epitaxial silicon increases the radiation hardness of the sensor against latchup. The linear energy transfer (LET) threshold for latchup is increased when using this configuration. Our findings suggest deep p wells can be used to increase the radiation tolerance of CMOS image sensors for use in future space missions.

  20. Visualization of heavy ion-induced charge production in a CMOS image sensor

    CERN Document Server

    Végh, J; Klamra, W; Molnár, J; Norlin, LO; Novák, D; Sánchez-Crespo, A; Van der Marel, J; Fenyvesi, A; Valastyan, I; Sipos, A

    2004-01-01

    A commercial CMOS image sensor was irradiated with heavy ion beams in the several MeV energy range. The image sensor is equipped with a standard video output. The data were collected on-line through frame grabbing and analysed off-line after digitisation. It was shown that the response of the image sensor to the heavy ion bombardment varied with the type and energy of the projectiles. The sensor will be used for the CMS Barrel Muon Alignment system.

  1. Implementation of large area CMOS image sensor module using the precision align inspection

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Byoung Wook; Kim, Toung Ju; Ryu, Cheol Woo [Radiation Imaging Technology Center, JBTP, Iksan (Korea, Republic of); Lee, Kyung Yong; Kim, Jin Soo [Nano Sol-Tech INC., Iksan (Korea, Republic of); Kim, Myung Soo; Cho, Gyu Seong [Dept. of Nuclear and Quantum Engineering, KAIST, Daejeon (Korea, Republic of)

    2014-12-15

    This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a 2×1 butted CMOS image sensor module which except for the size of PCB is 170 mm×170 mm. And the pixel size is 55 μm×55 μm and the number of pixels is 3,072×3,072. The gap between the two CMOS image sensor module was arranged in less than one pixel size.

  2. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Directory of Open Access Journals (Sweden)

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  3. Wide dynamic range CMOS image sensor with in-pixel double-exposure and synthesis

    Energy Technology Data Exchange (ETDEWEB)

    Li Binqiao; Sun Zhongyan; Xu Jiangtao, E-mail: xujiangtao@tju.edu.c [School of Electronics and Information Engineering, Tianjin University, Tianjin 300072 (China)

    2010-05-15

    A wide-dynamic-range CMOS image sensor (CIS) based on synthesis of a long-time and a short-time exposure signal in the floating diffusion (FD) of a five-transistor active pixel is proposed. With optimized pixel operation, the response curve is compressed and a wide dynamic range image is obtained. A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18 {mu}m CIS process. With the double exposure time 2.4 ms and 70 ns, the dynamic range of the proposed sensor is 80 dB with 30 frames per second (fps). The proposed CMOS image sensor meets the demands of applications in security surveillance systems. (semiconductor integrated circuits)

  4. In vitro and in vivo on-chip biofluorescence imaging using a CMOS image sensor

    Science.gov (United States)

    Ng, David C.; Matsuo, Masamichi; Tokuda, Takashi; Kagawa, Keiichiro; Nunoshita, Masahiro; Ohta, Jun

    2006-02-01

    We have designed and fabricated a 176×144-pixels (QCIF) CMOS image sensor for on-chip bio-fluorescence imaging of the mouse brain. In our approach, a single CMOS image sensor chip without additional optics is used. This enables imaging at arbitrary depths into the brain; a clear advantage compared to existing optical microscopy methods. Packaging of the chip represents a challenge for in vivo imaging. We developed a novel packaging process whereby an excitation filter is applied onto the sensor. This eliminates the use of a filter cube found in conventional fluorescence microscopes. The fully packaged chip is about 350 μm thick. Using the device, we demonstrated in vitro on-chip fluorescence imaging of a 400 μm thick mouse brain slice detailing the hippocampus. The image obtained compares favorably to the image captured by conventional microscopes in terms of image resolution. In order to study imaging in vivo, we also developed a phantom media. In situ fluorophore measurement shows that detection through the turbid medium of up to 1 mm thickness is possible. We have successfully demonstrated imaging deep into the hippocampal region of the mouse brain where quantitative fluorometric measurements was made. This work is expected to lead to a promising new tool for imaging the brain in vivo.

  5. A CMOS image sensor with draining only modulation pixels for fluorescence lifetime imaging

    Science.gov (United States)

    Li, Zhuo; Yasutomi, Keita; Takasawa, Taishi; Itoh, Shinya; Kawahito, Shoji

    2011-03-01

    Fluorescence lifetime imaging is becoming a powerful tool in biology. A charge-domain CMOS Fluorescence Lifetime Imaging Microscopy (FLIM) chip using a pinned photo diode (PPD) and the pinned storage diode (PSD) with different depth of potential wells has been previously developed by the authors. However, a transfer gate between PPD and PSD causes charge transfer noise due to traps at the channel surface. This paper presents a time-resolved CMOS image sensor with draining only modulation pixels for fluorescence lifetime imaging, which removes the transfer gate between PPD and PSD. The time windowing is done by draining with a draining gate only, which is attached along the carrier path from PPD to PSD. This allows us to realize a trapping less charge transfer between PPD and PSD, leading to a very low-noise time-resolved signal detection. A video-rate CMOS FLIM chip has been fabricated using 0.18μm standard CMOS pinned diode image sensor process. The pixel consists of a PPD, a PSD, a charge draining gate (TD), a readout transfer gate (TX) between the PSD and the floating diffusion (FD), a reset transistor and a source follower amplifier transistor. The pixel array has 200(Row) x 256(Column) pixels and the pixel pitch is 7.5μm. Fundamental characteristics of the implemented CMOS FLIM chip are measured. The signal intensity of the PSD as a function of the TD gate voltage is also measured. The ratio of the signal for the TD off to the signal for the TD on is 212 : 1.

  6. Readout circuit design of the retina-like CMOS image sensor

    Science.gov (United States)

    Cao, Fengmei; Song, Shengyu; Bai, Tingzhu; Cao, Nan

    2015-02-01

    Readout circuit is designed for a special retina-like CMOS image sensor. To realize the pixels timing drive and readout of the sensor, the Altera's Cyclone II FPGA is used as a control chip. The voltage of the sensor is supported by a voltage chip initialized by SPI with AVR MCU system. The analog image signal outputted by the sensor is converted to digital image data by 12-bits A/D converter ADS807 and the digital data is memorized in the SRAM. Using the Camera-link image grabber, the data stored in SRAM is transformed to image shown on PC. Experimental results show the circuit works well on retina-like CMOS timing drive and image readout and images can be displayed properly on the PC.

  7. Displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor

    Directory of Open Access Journals (Sweden)

    Zujun Wang

    2014-07-01

    Full Text Available The experiments of displacement damage effects on CMOS APS image sensors induced by neutron irradiation from a nuclear reactor are presented. The CMOS APS image sensors are manufactured in the standard 0.35 μm CMOS technology. The flux of neutron beams was about 1.33 × 108 n/cm2s. The three samples were exposed by 1 MeV neutron equivalent-fluence of 1 × 1011, 5 × 1011, and 1 × 1012 n/cm2, respectively. The mean dark signal (KD, dark signal spike, dark signal non-uniformity (DSNU, noise (VN, saturation output signal voltage (VS, and dynamic range (DR versus neutron fluence are investigated. The degradation mechanisms of CMOS APS image sensors are analyzed. The mean dark signal increase due to neutron displacement damage appears to be proportional to displacement damage dose. The dark images from CMOS APS image sensors irradiated by neutrons are presented to investigate the generation of dark signal spike.

  8. Single Photon Counting Performance and Noise Analysis of CMOS SPAD-Based Image Sensors.

    Science.gov (United States)

    Dutton, Neale A W; Gyongy, Istvan; Parmesan, Luca; Henderson, Robert K

    2016-07-20

    SPAD-based solid state CMOS image sensors utilising analogue integrators have attained deep sub-electron read noise (DSERN) permitting single photon counting (SPC) imaging. A new method is proposed to determine the read noise in DSERN image sensors by evaluating the peak separation and width (PSW) of single photon peaks in a photon counting histogram (PCH). The technique is used to identify and analyse cumulative noise in analogue integrating SPC SPAD-based pixels. The DSERN of our SPAD image sensor is exploited to confirm recent multi-photon threshold quanta image sensor (QIS) theory. Finally, various single and multiple photon spatio-temporal oversampling techniques are reviewed.

  9. Recent Design Development in Molecular Imaging for Breast Cancer Detection Using Nanometer CMOS Based Sensors.

    Science.gov (United States)

    Nguyen, Dung C; Ma, Dongsheng Brian; Roveda, Janet M W

    2012-01-01

    As one of the key clinical imaging methods, the computed X-ray tomography can be further improved using new nanometer CMOS sensors. This will enhance the current technique's ability in terms of cancer detection size, position, and detection accuracy on the anatomical structures. The current paper reviewed designs of SOI-based CMOS sensors and their architectural design in mammography systems. Based on the existing experimental results, using the SOI technology can provide a low-noise (SNR around 87.8 db) and high-gain (30 v/v) CMOS imager. It is also expected that, together with the fast data acquisition designs, the new type of imagers may play important roles in the near-future high-dimensional images in additional to today's 2D imagers.

  10. High-speed CMOS image sensor for high-throughput lensless microfluidic imaging system

    Science.gov (United States)

    Yan, Mei; Huang, Xiwei; Jia, Qixiang; Nadipalli, Revanth; Wang, Tongxi; Shang, Yang; Yu, Hao; Je, Minkyu; Yeo, Kiatseng

    2012-03-01

    The integration of CMOS image sensor and microfluidics becomes a promising technology for point-of-care (POC) diagnosis. However, commercial image sensors usually have limited speed and low-light sensitivity. One high-speed and high-sensitivity CMOS image sensor chip is introduced in this paper, targeted for high-throughput microfluidic imaging system. Firstly, high speed image sensor architecture is introduced with design of column-parallel single-slope analog-todigital converter (ADC) with digital correlated double sampling (CDS). The frame rate can be achieved to 2400 frames/second (fps) with resolution of 128×96 for high-throughput microfluidic imaging. Secondly, the designed system has superior low-light sensitivity, which is achieved by large pixel size (10μm×10μm, 56% fill factor). Pixel peak signalnoise- ratio (SNR) reaches to 50dB with 10dB improvement compared to the commercial pixel (2.2μm×2.2μm). The degradation of pixel resolution is compensated by super-resolution image processing algorithm. By reconstructing single image with multiple low-resolution frames, we can equivalently achieve 2μm resolution with physical 10μm pixel. Thirdly, the system-on-chip (SoC) integration results in a real-time controlled intelligent imaging system without expensive data storage and time-consuming computer analysis. This initial sensor prototype with timing-control makes it possible to develop high-throughput lensless microfluidic imaging system for POC diagnosis.

  11. High-speed binary CMOS image sensor using a high-responsivity MOSFET-type photodetector

    Science.gov (United States)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Choi, Pyung; Shin, Jang-Kyoo

    2015-03-01

    In this paper, a complementary metal oxide semiconductor (CMOS) binary image sensor based on a gate/body-tied (GBT) MOSFET-type photodetector is proposed. The proposed CMOS binary image sensor was simulated and measured using a standard CMOS 0.18-μm process. The GBT MOSFET-type photodetector is composed of a floating gate (n+- polysilicon) tied to the body (n-well) of the p-type MOSFET. The size of the active pixel sensor (APS) using GBT photodetector is smaller than that of APS using the photodiode. This means that the resolution of the image can be increased. The high-gain GBT photodetector has a higher photosensitivity compared to the p-n junction photodiode that is used in a conventional APS. Because GBT has a high sensitivity, fast operation of the binary processing is possible. A CMOS image sensor with the binary processing can be designed with simple circuits composed of a comparator and a Dflip- flop while a complex analog to digital converter (ADC) is not required. In addition, the binary image sensor has low power consumption and high speed operation with the ability to switch back and forth between a binary mode and an analog mode.

  12. A High-Speed CMOS Image Sensor with Global Electronic Shutter Pixels Using Pinned Diodes

    Science.gov (United States)

    Yasutomi, Keita; Tamura, Toshihiro; Furuta, Masanori; Itoh, Shinya; Kawahito, Shoji

    This paper describes a high-speed CMOS image sensor with a new type of global electronic shutter pixel. A global electronic shutter is necessary for imaging fast-moving objects without motion blur or distortion. The proposed pixel has two potential wells with pinned diode structure for two-stage charge transfer that enables a global electronic shuttering and reset noise canceling. A prototype high-speed image sensor fabricated in 0.18μm standard CMOS image sensor process consists of the proposed pixel array, 12-bit column-parallel cyclic ADC arrays and 192-channel digital outputs. The sensor achieves a good linearity at low-light intensity, demonstrating the perfect charge transfer between two pinned diodes. The input referred noise of the proposed pixel is measured to be 6.3 e-.

  13. CMOS Image Sensor with a Built-in Lane Detector.

    Science.gov (United States)

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

  14. CMOS Image Sensor with a Built-in Lane Detector

    Directory of Open Access Journals (Sweden)

    Li-Chen Fu

    2009-03-01

    Full Text Available This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC or Digital Signal Processor (DSP, the proposed imager, without extra Analog to Digital Converter (ADC circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 x 2,389.8 mm, and the package uses 40 pin Dual-In-Package (DIP. The pixel cell size is 18.45 x 21.8 mm and the core size of photodiode is 12.45 x 9.6 mm; the resulting fill factor is 29.7%.

  15. Design and implementation of non-linear image processing functions for CMOS image sensor

    Science.gov (United States)

    Musa, Purnawarman; Sudiro, Sunny A.; Wibowo, Eri P.; Harmanto, Suryadi; Paindavoine, Michel

    2012-11-01

    Today, solid state image sensors are used in many applications like in mobile phones, video surveillance systems, embedded medical imaging and industrial vision systems. These image sensors require the integration in the focal plane (or near the focal plane) of complex image processing algorithms. Such devices must meet the constraints related to the quality of acquired images, speed and performance of embedded processing, as well as low power consumption. To achieve these objectives, low-level analog processing allows extracting the useful information in the scene directly. For example, edge detection step followed by a local maxima extraction will facilitate the high-level processing like objects pattern recognition in a visual scene. Our goal was to design an intelligent image sensor prototype achieving high-speed image acquisition and non-linear image processing (like local minima and maxima calculations). For this purpose, we present in this article the design and test of a 64×64 pixels image sensor built in a standard CMOS Technology 0.35 μm including non-linear image processing. The architecture of our sensor, named nLiRIC (non-Linear Rapid Image Capture), is based on the implementation of an analog Minima/Maxima Unit. This MMU calculates the minimum and maximum values (non-linear functions), in real time, in a 2×2 pixels neighbourhood. Each MMU needs 52 transistors and the pitch of one pixel is 40×40 mu m. The total area of the 64×64 pixels is 12.5mm2. Our tests have shown the validity of the main functions of our new image sensor like fast image acquisition (10K frames per second), minima/maxima calculations in less then one ms.

  16. Gamma-ray irradiation tests of CMOS sensors used in imaging techniques

    Directory of Open Access Journals (Sweden)

    Cappello Salvatore G.

    2014-01-01

    Full Text Available Technologically-enhanced electronic image sensors are used in various fields as diagnostic techniques in medicine or space applications. In the latter case the devices can be exposed to intense radiation fluxes over time which may impair the functioning of the same equipment. In this paper we report the results of gamma-ray irradiation tests on CMOS image sensors simulating the space radiation over a long time period. Gamma-ray irradiation tests were carried out by means of IGS-3 gamma irradiation facility of Palermo University, based on 60Co sources with different activities. To reduce the dose rate and realize a narrow gamma-ray beam, a lead-collimation system was purposely built. It permits to have dose rate values less than 10 mGy/s and to irradiate CMOS Image Sensors during operation. The total ionizing dose to CMOS image sensors was monitored in-situ, during irradiation, up to 1000 Gy and images were acquired every 25 Gy. At the end of the tests, the sensors continued to operate despite a background noise and some pixels were completely saturated. These effects, however, involve isolated pixels and therefore, should not affect the image quality.

  17. Low-power high-accuracy micro-digital sun sensor by means of a CMOS image sensor

    NARCIS (Netherlands)

    Xie, N.; Theuwissen, A.J.P.

    2013-01-01

    A micro-digital sun sensor (μDSS) is a sun detector which senses a satellite’s instant attitude angle with respect to the sun. The core of this sensor is a system-on-chip imaging chip which is referred to as APS+. The APS+ integrates a CMOS active pixel sensor (APS) array of 368×368  pixels , a 12-b

  18. Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing

    Directory of Open Access Journals (Sweden)

    Cally Gill

    2013-09-01

    Full Text Available The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

  19. Laser doppler blood flow imaging using a CMOS imaging sensor with on-chip signal processing.

    Science.gov (United States)

    He, Diwei; Nguyen, Hoang C; Hayes-Gill, Barrie R; Zhu, Yiqun; Crowe, John A; Gill, Cally; Clough, Geraldine F; Morgan, Stephen P

    2013-09-18

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue.

  20. Laser Doppler Blood Flow Imaging Using a CMOS Imaging Sensor with On-Chip Signal Processing

    Science.gov (United States)

    He, Diwei; Nguyen, Hoang C.; Hayes-Gill, Barrie R.; Zhu, Yiqun; Crowe, John A.; Gill, Cally; Clough, Geraldine F.; Morgan, Stephen P.

    2013-01-01

    The first fully integrated 2D CMOS imaging sensor with on-chip signal processing for applications in laser Doppler blood flow (LDBF) imaging has been designed and tested. To obtain a space efficient design over 64 × 64 pixels means that standard processing electronics used off-chip cannot be implemented. Therefore the analog signal processing at each pixel is a tailored design for LDBF signals with balanced optimization for signal-to-noise ratio and silicon area. This custom made sensor offers key advantages over conventional sensors, viz. the analog signal processing at the pixel level carries out signal normalization; the AC amplification in combination with an anti-aliasing filter allows analog-to-digital conversion with a low number of bits; low resource implementation of the digital processor enables on-chip processing and the data bottleneck that exists between the detector and processing electronics has been overcome. The sensor demonstrates good agreement with simulation at each design stage. The measured optical performance of the sensor is demonstrated using modulated light signals and in vivo blood flow experiments. Images showing blood flow changes with arterial occlusion and an inflammatory response to a histamine skin-prick demonstrate that the sensor array is capable of detecting blood flow signals from tissue. PMID:24051525

  1. Fast regional readout CMOS Image Sensor for dynamic MLC tracking

    Science.gov (United States)

    Zin, H.; Harris, E.; Osmond, J.; Evans, P.

    2014-03-01

    Advanced radiotherapy techniques such as volumetric modulated arc therapy (VMAT) require verification of the complex beam delivery including tracking of multileaf collimators (MLC) and monitoring the dose rate. This work explores the feasibility of a prototype Complementary metal-oxide semiconductor Image Sensor (CIS) for tracking these complex treatments by utilising fast, region of interest (ROI) read out functionality. An automatic edge tracking algorithm was used to locate the MLC leaves edges moving at various speeds (from a moving triangle field shape) and imaged with various sensor frame rates. The CIS demonstrates successful edge detection of the dynamic MLC motion within accuracy of 1.0 mm. This demonstrates the feasibility of the sensor to verify treatment delivery involving dynamic MLC up to ~400 frames per second (equivalent to the linac pulse rate), which is superior to any current techniques such as using electronic portal imaging devices (EPID). CIS provides the basis to an essential real-time verification tool, useful in accessing accurate delivery of complex high energy radiation to the tumour and ultimately to achieve better cure rates for cancer patients.

  2. Particle detection and classification using commercial off the shelf CMOS image sensors

    Energy Technology Data Exchange (ETDEWEB)

    Pérez, Martín [Instituto Balseiro, Av. Bustillo 9500, Bariloche, 8400 (Argentina); Comisión Nacional de Energía Atómica (CNEA), Centro Atómico Bariloche, Av. Bustillo 9500, Bariloche 8400 (Argentina); Consejo Nacional de Investigaciones Científicas y Técnicas, Centro Atómico Bariloche, Av. Bustillo 9500, 8400 Bariloche (Argentina); Lipovetzky, Jose, E-mail: lipo@cab.cnea.gov.ar [Instituto Balseiro, Av. Bustillo 9500, Bariloche, 8400 (Argentina); Comisión Nacional de Energía Atómica (CNEA), Centro Atómico Bariloche, Av. Bustillo 9500, Bariloche 8400 (Argentina); Consejo Nacional de Investigaciones Científicas y Técnicas, Centro Atómico Bariloche, Av. Bustillo 9500, 8400 Bariloche (Argentina); Sofo Haro, Miguel; Sidelnik, Iván; Blostein, Juan Jerónimo; Alcalde Bessia, Fabricio; Berisso, Mariano Gómez [Instituto Balseiro, Av. Bustillo 9500, Bariloche, 8400 (Argentina); Consejo Nacional de Investigaciones Científicas y Técnicas, Centro Atómico Bariloche, Av. Bustillo 9500, 8400 Bariloche (Argentina)

    2016-08-11

    In this paper we analyse the response of two different Commercial Off The shelf CMOS image sensors as particle detectors. Sensors were irradiated using X-ray photons, gamma photons, beta particles and alpha particles from diverse sources. The amount of charge produced by different particles, and the size of the spot registered on the sensor are compared, and analysed by an algorithm to classify them. For a known incident energy spectrum, the employed sensors provide a dose resolution lower than microGray, showing their potentials in radioprotection, area monitoring, or medical applications.

  3. Overview of CMOS process and design options for image sensor dedicated to space applications

    Science.gov (United States)

    Martin-Gonthier, P.; Magnan, P.; Corbiere, F.

    2005-10-01

    With the growth of huge volume markets (mobile phones, digital cameras...) CMOS technologies for image sensor improve significantly. New process flows appear in order to optimize some parameters such as quantum efficiency, dark current, and conversion gain. Space applications can of course benefit from these improvements. To illustrate this evolution, this paper reports results from three technologies that have been evaluated with test vehicles composed of several sub arrays designed with some space applications as target. These three technologies are CMOS standard, improved and sensor optimized process in 0.35μm generation. Measurements are focussed on quantum efficiency, dark current, conversion gain and noise. Other measurements such as Modulation Transfer Function (MTF) and crosstalk are depicted in [1]. A comparison between results has been done and three categories of CMOS process for image sensors have been listed. Radiation tolerance has been also studied for the CMOS improved process in the way of hardening the imager by design. Results at 4, 15, 25 and 50 krad prove a good ionizing dose radiation tolerance applying specific techniques.

  4. 320×240 Pixels CMOS Digital Image Sensor with Wide Dynamic Range

    Institute of Scientific and Technical Information of China (English)

    FANG Jie; WANG Jing-guang; HONG Zhi-liang

    2004-01-01

    A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.

  5. Area-efficient readout with 14-bit SAR-ADC for CMOS image sensors

    Directory of Open Access Journals (Sweden)

    Aziza Sassi Ben

    2016-01-01

    Full Text Available This paper proposes a readout design for CMOS image sensors. It has been squeezed into a 7.5um pitch under a 0.28um 1P3M technology. The ADC performs one 14-bit conversion in only 1.5us and targets a theoretical DNL feature about +1.3/-1 at 14-bit accuracy. Correlated Double Sampling (CDS is performed both in the analog and digital domains to preserve the image quality.

  6. [C-MOS flat-panel sensor for real time X-ray imaging].

    Science.gov (United States)

    Nakagawa, K; Aoki, Y; Sasaki, Y; Akanuma, A; Mizuno, S

    1998-02-01

    Flat-panel, self-scanning, solid state diagnostic x-ray imaging devices using complementary metal-oxide-semiconductor (C-MOS) arrays are under investigation. A unit device with a 5 cm by 5 cm sensor area was developed and tested. The device consists of a CsI scintillator and C-MOS detector arrays. The detector arrays are composed of a regular arrangement of pixels (256 x 256), each of which is made of a C-MOS photodiode sensor coupled to a C-MOS FET (field effect transistor). A common FET gate line is connected to all the FET gates along each column. A common date line is connected to all the FET drains of each row. The source contact of each FET is connected to that of its corresponding photodiode. A positive gate pulse applied to a gate turns on all FETs connected to the date lines. The readout continues column by column. Correlated double sampling circuits and an offset variance compensation circuit were installed to reduce noise. A sampling speed of 15 frames per second and spatial resolution of 2.5 line per mm were achieved. Noise level and maximum signal were 1.5 mV rms and 1.8 V, respectively. Image quality was considered acceptable for clinical use. It is also discussed how to fabricate a large area sensor with the unit device.

  7. Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

    Science.gov (United States)

    Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

    2016-01-01

    In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

  8. Microlens performance limits in sub-2mum pixel CMOS image sensors.

    Science.gov (United States)

    Huo, Yijie; Fesenmaier, Christian C; Catrysse, Peter B

    2010-03-15

    CMOS image sensors with smaller pixels are expected to enable digital imaging systems with better resolution. When pixel size scales below 2 mum, however, diffraction affects the optical performance of the pixel and its microlens, in particular. We present a first-principles electromagnetic analysis of microlens behavior during the lateral scaling of CMOS image sensor pixels. We establish for a three-metal-layer pixel that diffraction prevents the microlens from acting as a focusing element when pixels become smaller than 1.4 microm. This severely degrades performance for on and off-axis pixels in red, green and blue color channels. We predict that one-metal-layer or backside-illuminated pixels are required to extend the functionality of microlenses beyond the 1.4 microm pixel node.

  9. Low-light-level CMOS Image Sensor Technique%低照度CMOS图像传感器技术

    Institute of Scientific and Technical Information of China (English)

    姚立斌

    2013-01-01

      与其他固体微光器件相比,低照度CMOS图像传感器具有成本、功耗及体积优势,是固体微光器件发展的重要方向。但目前低照度CMOS图像传感器的微光性能还不能满足夜视应用要求。本文介绍了低照度 CMOS 图像传感器及提高其灵敏度的几种技术途径,采用低照度技术后 CMOS图像传感器性能已接近实用要求。随着 CMOS 工艺技术的不断发展及低照度 CMOS 图像传感器研究的不断深入,在不远的将来,低照度CMOS图像传感器将成为固体微光器件的重要一员。%Compared to other low-light-level image sensors, the CMOS image sensor has the cost, power and size advantages. Currently the performance of the low-light-level CMOS image sensor does not satisfy the night-vision application requirements due to relatively low sensitivity. Several techniques to increase the sensitivity of the low-light-level CMOS image sensor are introduced in this paper. The state-of-the-art designs are reviewed and their performance is close to EMCCD sensor. With the development of the CMOS technology and the further research on low-light-level CMOS image sensors, the CMOS image sensor is potentially a major player in the solid-state low-light-level image sensor market.

  10. Development of CMOS Active Pixel Image Sensors for Low Cost Commercial Applications

    Science.gov (United States)

    Fossum, E.; Gee, R.; Kemeny, S.; Kim, Q.; Mendis, S.; Nakamura, J.; Nixon, R.; Ortiz, M.; Pain, B.; Zhou, Z.; Ackland, B.; Dickinson, A.; Eid, E.; Inglis, D.

    1994-01-01

    This paper describes ongoing research and development of CMOS active pixel image sensors for low cost commercial applications. A number of sensor designs have been fabricated and tested in both p-well and n-well technologies. Major elements in the development of the sensor include on-chip analog signal processing circuits for the reduction of fixed pattern noise, on-chip timing and control circuits and on-chip analog-to-digital conversion (ADC). Recent results and continuing efforts in these areas will be presented.

  11. Analysis of incomplete charge transfer effects in a CMOS image sensor

    Institute of Scientific and Technical Information of China (English)

    Han Liqiang; Yao Suying; Xu Jiangtao; Xu Chao; Gao Zhiyuan

    2013-01-01

    A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size.Based on the emission current theory,a qualitative photoresponse model is established to the preliminary prediction.Further analysis of noise for incomplete charge transfer predicts the noise variation.The test pixels were fabricated in a specialized 0.18μm CMOS image sensor process and two different processes of buried N layer implantation are compared.The trend prediction corresponds with the test results,especially as it can distinguish an unobvious incomplete charge transfer.The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.

  12. A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering

    Science.gov (United States)

    Lioe, DeXing; Mars, Kamel; Takasawa, Taishi; Yasutomi, Keita; Kagawa, Keiichiro; Hashimoto, Mamoru; Kawahito, Shoji

    2016-03-01

    A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering (SRS) spectroscopy is presented in this paper. The effective SRS signal from the stimulated emission of SRS mechanism is very small in contrast to the offset of a probing laser source, which is in the ratio of 10-4 to 10-5. In order to extract this signal, the common offset component is removed, and the small difference component is sampled using switched-capacitor integrator with a fully differential amplifier. The sampling is performed over many integration cycles to achieve appropriate amplification. The lock-in pixels utilizes high-speed lateral electric field charge modulator (LEFM) to demodulate the SRS signal which is modulated at high-frequency of 20MHz. A prototype chip is implemented using 0.11μm CMOS image sensor technology.

  13. CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

    Science.gov (United States)

    Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

    2016-04-01

    This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

  14. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

    Directory of Open Access Journals (Sweden)

    Shoji Kawahito

    2010-10-01

    Full Text Available For low-noise complementary metal-oxide-semiconductor (CMOS image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e- for the simple integration CMS and 75 dB and 2.2 e- for the folding integration CMS, respectively, are obtained.

  15. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

    Science.gov (United States)

    Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

    2010-01-01

    For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e− for the simple integration CMS and 75 dB and 2.2 e− for the folding integration CMS, respectively, are obtained. PMID:22163400

  16. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  17. Fibre-optic coupling to high-resolution CCD and CMOS image sensors

    Science.gov (United States)

    van Silfhout, R. G.; Kachatkou, A. S.

    2008-12-01

    We describe a simple method of gluing fibre-optic faceplates to complementary metal oxide semiconductor (CMOS) active pixel and charge coupled device (CCD) image sensors and report on their performance. Cross-sectional cuts reveal that the bonding layer has a thickness close to the diameter of the individual fibres and is uniform over the whole sensor area. Our method requires no special tools or alignment equipment and gives reproducible and high-quality results. The method maintains a uniform bond layer thickness even if sensor dies are mounted at slight angles with their package. These fibre-coupled sensors are of particular interest to X-ray imaging applications but also provide a solution for compact optical imaging systems.

  18. Column-Parallel Single Slope ADC with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors

    NARCIS (Netherlands)

    Chen, Y.; Theuwissen, A.J.P.; Chae, Y.

    2011-01-01

    This paper presents a low noise CMOS image sensor (CIS) using 10/12 bit configurable column-parallel single slope ADCs (SS-ADCs) and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel with a pinned-photodiode as photon detector. The test sensor was fabricat

  19. Reduction of CMOS Image Sensor Read Noise to Enable Photon Counting.

    Science.gov (United States)

    Guidash, Michael; Ma, Jiaju; Vogelsang, Thomas; Endsley, Jay

    2016-04-09

    Recent activity in photon counting CMOS image sensors (CIS) has been directed to reduction of read noise. Many approaches and methods have been reported. This work is focused on providing sub 1 e(-) read noise by design and operation of the binary and small signal readout of photon counting CIS. Compensation of transfer gate feed-through was used to provide substantially reduced CDS time and source follower (SF) bandwidth. SF read noise was reduced by a factor of 3 with this method. This method can be applied broadly to CIS devices to reduce the read noise for small signals to enable use as a photon counting sensor.

  20. Polarization-Analyzing CMOS Image Sensor With Monolithically Embedded Polarizer for Microchemistry Systems.

    Science.gov (United States)

    Tokuda, T; Yamada, H; Sasagawa, K; Ohta, J

    2009-10-01

    This paper proposes and demonstrates a polarization-analyzing CMOS sensor based on image sensor architecture. The sensor was designed targeting applications for chiral analysis in a microchemistry system. The sensor features a monolithically embedded polarizer. Embedded polarizers with different angles were implemented to realize a real-time absolute measurement of the incident polarization angle. Although the pixel-level performance was confirmed to be limited, estimation schemes based on the variation of the polarizer angle provided a promising performance for real-time polarization measurements. An estimation scheme using 180 pixels in a 1deg step provided an estimation accuracy of 0.04deg. Polarimetric measurements of chiral solutions were also successfully performed to demonstrate the applicability of the sensor to optical chiral analysis.

  1. A Low Power Digital Accumulation Technique for Digital-Domain CMOS TDI Image Sensor

    Science.gov (United States)

    Yu, Changwei; Nie, Kaiming; Xu, Jiangtao; Gao, Jing

    2016-01-01

    In this paper, an accumulation technique suitable for digital domain CMOS time delay integration (TDI) image sensors is proposed to reduce power consumption without degrading the rate of imaging. In terms of the slight variations of quantization codes among different pixel exposures towards the same object, the pixel array is divided into two groups: one is for coarse quantization of high bits only, and the other one is for fine quantization of low bits. Then, the complete quantization codes are composed of both results from the coarse-and-fine quantization. The equivalent operation comparably reduces the total required bit numbers of the quantization. In the 0.18 µm CMOS process, two versions of 16-stage digital domain CMOS TDI image sensor chains based on a 10-bit successive approximate register (SAR) analog-to-digital converter (ADC), with and without the proposed technique, are designed. The simulation results show that the average power consumption of slices of the two versions are 6.47×10-8 J/line and 7.4×10-8 J/line, respectively. Meanwhile, the linearity of the two versions are 99.74% and 99.99%, respectively. PMID:27669256

  2. A Low Power Digital Accumulation Technique for Digital-Domain CMOS TDI Image Sensor.

    Science.gov (United States)

    Yu, Changwei; Nie, Kaiming; Xu, Jiangtao; Gao, Jing

    2016-09-23

    In this paper, an accumulation technique suitable for digital domain CMOS time delay integration (TDI) image sensors is proposed to reduce power consumption without degrading the rate of imaging. In terms of the slight variations of quantization codes among different pixel exposures towards the same object, the pixel array is divided into two groups: one is for coarse quantization of high bits only, and the other one is for fine quantization of low bits. Then, the complete quantization codes are composed of both results from the coarse-and-fine quantization. The equivalent operation comparably reduces the total required bit numbers of the quantization. In the 0.18 µm CMOS process, two versions of 16-stage digital domain CMOS TDI image sensor chains based on a 10-bit successive approximate register (SAR) analog-to-digital converter (ADC), with and without the proposed technique, are designed. The simulation results show that the average power consumption of slices of the two versions are 6 . 47 × 10 - 8 J/line and 7 . 4 × 10 - 8 J/line, respectively. Meanwhile, the linearity of the two versions are 99.74% and 99.99%, respectively.

  3. Projection-reflection ultrasound images using PE-CMOS sensor: a preliminary bone fracture study

    Science.gov (United States)

    Lo, Shih-Chung B.; Liu, Chu-Chuan; Freedman, Matthew T.; Mun, Seong-Ki; Kula, John; Lasser, Marvin E.; Lasser, Bob; Wang, Yue Joseph

    2008-03-01

    In this study, we investigated the characteristics of the ultrasound reflective image obtained by a CMOS sensor array coated with piezoelectric material (PE-CMOS). The laboratory projection-reflection ultrasound prototype consists of five major components: an unfocused ultrasound transducer, an acoustic beam splitter, an acoustic compound lens, a PE-CMOS ultrasound sensing array (Model I400, Imperium Inc. Silver Spring, MD), and a readout circuit system. The prototype can image strong reflective materials such as bone and metal. We found this projection-reflection ultrasound prototype is able to reveal hairline bone fractures with and without intact skin and tissue. When compared, the image generated from a conventional B-scan ultrasound on the same bone fracture is less observable. When it is observable with the B-scan system, the fracture or crack on the surface only show one single spot of echo due to its scan geometry. The corresponding image produced from the projection-reflection ultrasound system shows a bright blooming strip on the image clearly indicating the fracture on the surface of the solid material. Speckles of the bone structure are also observed in the new ultrasound prototype. A theoretical analysis is provided to link the signals as well as speckles detected in both systems.

  4. CMOS image sensor for detection of interferon gamma protein interaction as a point-of-care approach.

    Science.gov (United States)

    Marimuthu, Mohana; Kandasamy, Karthikeyan; Ahn, Chang Geun; Sung, Gun Yong; Kim, Min-Gon; Kim, Sanghyo

    2011-09-01

    Complementary metal oxide semiconductor (CMOS)-based image sensors have received increased attention owing to the possibility of incorporating them into portable diagnostic devices. The present research examined the efficiency and sensitivity of a CMOS image sensor for the detection of antigen-antibody interactions involving interferon gamma protein without the aid of expensive instruments. The highest detection sensitivity of about 1 fg/ml primary antibody was achieved simply by a transmission mechanism. When photons are prevented from hitting the sensor surface, a reduction in digital output occurs in which the number of photons hitting the sensor surface is approximately proportional to the digital number. Nanoscale variation in substrate thickness after protein binding can be detected with high sensitivity by the CMOS image sensor. Therefore, this technique can be easily applied to smartphones or any clinical diagnostic devices for the detection of several biological entities, with high impact on the development of point-of-care applications.

  5. Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor

    Directory of Open Access Journals (Sweden)

    Fang Tang

    2014-01-01

    Full Text Available Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μm CMOS technology. The chip area of the proposed ADC is 7 μm × 500 μm. The measurement results show that the energy efficiency figure-of-merit (FOM of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k μm2·cycles/sample.

  6. A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

    Science.gov (United States)

    Zhang, Fan; Niu, Hanben

    2016-06-29

    In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

  7. Two-step single slope/SAR ADC with error correction for CMOS image sensor.

    Science.gov (United States)

    Tang, Fang; Bermak, Amine; Amira, Abbes; Amor Benammar, Mohieddine; He, Debiao; Zhao, Xiaojin

    2014-01-01

    Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area. This paper presents an 11-bit two-step single slope/successive approximation register (SAR) ADC scheme for CMOS image sensor applications. The first stage single slope ADC generates a 3-bit data and 1 redundant bit. The redundant bit is combined with the following 8-bit SAR ADC output code using a proposed error correction algorithm. Instead of requiring full resolution noise performance, the first stage single slope circuit of the proposed ADC can tolerate up to 3.125% quantization noise. With the proposed error correction mechanism, the power consumption and chip area of the single slope ADC are significantly reduced. The prototype ADC is fabricated using 0.18 μ m CMOS technology. The chip area of the proposed ADC is 7 μ m × 500 μ m. The measurement results show that the energy efficiency figure-of-merit (FOM) of the proposed ADC core is only 125 pJ/sample under 1.4 V power supply and the chip area efficiency is 84 k  μ m(2) · cycles/sample.

  8. SEMICONDUCTOR DEVICES: Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

    Science.gov (United States)

    Junting, Yu; Binqiao, Li; Pingping, Yu; Jiangtao, Xu; Cun, Mou

    2010-09-01

    Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model. Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment, PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer. With the computer analysis tool ISE-TCAD, simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0 × 1012 cm-2, an implant tilt of -2°, a transfer gate channel doping dose of 3.0 × 1012 cm-2 and an operation voltage of 3.4 V. The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.

  9. CMOS active pixel sensor type imaging system on a chip

    Science.gov (United States)

    Fossum, Eric R. (Inventor); Nixon, Robert (Inventor)

    2011-01-01

    A single chip camera which includes an .[.intergrated.]. .Iadd.integrated .Iaddend.image acquisition portion and control portion and which has double sampling/noise reduction capabilities thereon. Part of the .[.intergrated.]. .Iadd.integrated .Iaddend.structure reduces the noise that is picked up during imaging.

  10. Using polynomials to simplify fixed pattern noise and photometric correction of logarithmic CMOS image sensors.

    Science.gov (United States)

    Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

    2015-10-16

    An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient.

  11. X-ray imaging and spectroscopy using low cost COTS CMOS sensors

    Energy Technology Data Exchange (ETDEWEB)

    Lane, David W., E-mail: d.w.lane@cranfield.ac.uk [Department of Engineering and Applied Science, Cranfield University, Shrivenham, Swindon SN6 8LA (United Kingdom)

    2012-08-01

    Whilst commercial X-ray sensor arrays are capable of both imaging and spectroscopy they are currently expensive and this can limit their widespread use. This study examines the use of very low cost CMOS sensors for X-ray imaging and spectroscopy based on the commercial off the shelf (COTS) technology used in cellular telephones, PC multimedia and children's toys. Some examples of imaging using a 'webcam' and a modified OmniVision OV7411 sensor are presented, as well as a simple energy dispersive X-ray detector based on an OmniVision OV7221 sensor. In each case X-ray sensitivity was enabled by replacing the sensor's front glass window with a 5 {mu}m thick aluminium foil, with X-rays detected as an increase in a pixel's dark current due to the generation of additional electron-hole pairs within its active region. The exposure control and data processing requirements for imaging and spectroscopy are discussed. The modified OV7221 sensor was found to have a linear X-ray energy calibration and a resolution of approximately 510 eV.

  12. Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

    Institute of Scientific and Technical Information of China (English)

    赵士彬; 姚素英; 聂凯明; 徐江涛

    2010-01-01

    A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissi...

  13. An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

    Directory of Open Access Journals (Sweden)

    Yuan Cao

    2014-12-01

    Full Text Available In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO based analog-to-digital converter (ADC to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS process.

  14. An ultra wide dynamic range CMOS image sensor with a linear response

    Science.gov (United States)

    Park, Jong Ho; Mase, Mitsuhito; Kawahito, Shoji; Sasaki, Masaaki; Wakamori, Yasuo; Ohta, Yukihiro

    2006-02-01

    An ultra wide dynamic range (WDR) CMOS image sensor (CIS) and the details of evaluation are presented. The proposed signal readout technique of extremely short accumulation (ESA) enables the dynamic range of image sensor to be expanded up to 146dB. Including the ESA signals, total of 4 different accumulation time signals are read out in one frame period based on burst readout technique. To achieve the high-speed signal readout required for the multiple exposure signals, column parallel A/D converters are integrated at the upper and lower sides of pixel arrays. The improved 12-bits cyclic ADCs with a built-in correlated double sampling (CDS) circuit has the differential non-linearity (DNL) of +/-0.3LSB.

  15. 10×10-pixel 606kS/s multi-point fluorescence correlation spectroscopy CMOS image sensor

    Science.gov (United States)

    Kagawa, Keiichiro; Takasawa, Taishi; Bo, Zhang; Seo, Min-Woong; Imai, Kaita; Yamamoto, Jotaro; Kinjo, Masataka; Terakawa, Susumu; Yasutomi, Keita; Kawahito, Shoji

    2014-03-01

    To observe molecular transport in a living cell, a high-speed CMOS image sensor for multi-point fluorescence correlation spectroscopy is developed. To achieve low-noise and high-speed simultaneously, a prototype CMOS image sensor is designed based on a complete pixel-parallel architecture and multi-channel pipelined pixel readout. The prototype chip with 10×10 effective pixels is fabricated in 0.18-μm CMOS image sensor technology. The pixel pitch and the photosensitive area are 56μm and 10μm in diameter without a microlens, respectively. In the experiment, the total sampling rate of 606kS/s is achieved. The measured average random noise is 24.9LSB, which is equivalent to about 2.5 electrons in average.

  16. Complete Focal Plane Compression Based on CMOS Image Sensor Using Predictive Coding

    Institute of Scientific and Technical Information of China (English)

    Yao Suying; Yu Xiao; Gao Jing; Xu Jiangtao

    2015-01-01

    In this paper, a CMOS image sensor(CIS) is proposed, which can accomplish both decorrelation and en-tropy coding of image compression directly on the focal plane. The design is based on predictive coding for image decorrelation. The predictions are performed in analog domain by 2×2 pixel units. Both the prediction residuals and original pixel values are quantized and encoded in parallel. Since the residuals have a peak distribution around zero, the output codewords can be replaced by the valid part of the residuals’ binary mode. The compressed bit stream is accessible directly at the output of CIS without extra disposition. Simulation results show that the proposed approach achieves a compression rate of 2. 2 and PSNR of 51 on different test images.

  17. Difference in electron- and gamma-irradiation effects on output characteristic of color CMOS digital image sensors

    Institute of Scientific and Technical Information of China (English)

    MENG Xiangti; KANG Aiguo; ZHANG Ximin; LI Jihong; HUANG Qiang; LI Fengmei; LIU Xiaoguang; ZHOU Hongyu

    2004-01-01

    Changes of the average brightness and non-uniformity of dark output images, and quality of pictures captured under natural lighting for the color CMOS digital image sensors irradiated at different electron doses have been studied in comparison to those from the γ-irradiated sensors. For the electron-irradiated sensors, the non-uniformity increases obviously and a small bright region on the dark image appears at the dose of 0.4 kGy. The average brightness increases at 0.4 kGy, increases sharply at 0.5 kGy. The picture is very blurry only at 0.6 kGy, showing the sensor undergoes severe performance degradation. Electron radiation damage is much more severe than γ radiation damage for the CMOS image sensors. A possible explanation is presented in this paper.

  18. A low-power column-parallel ADC for high-speed CMOS image sensor

    Science.gov (United States)

    Han, Ye; Li, Quanliang; Shi, Cong; Liu, Liyuan; Wu, Nanjian

    2013-08-01

    This paper presents a 10-bit low-power column-parallel cyclic analog-to-digital converter (ADC) used for high-speed CMOS image sensor (CIS). An opamp sharing technique is used to save power and area. Correlated double sampling (CDS) circuit and programmable gain amplifier (PGA) are integrated in the ADC, which avoids stand-alone circuit blocks. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.03mm2 was implemented in a 0.18μm 1P4M CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 2MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 2.1 LSB together with CDS, respectively. The power consumption from 1.8V supply is only 0.36mW.

  19. Microdialysis coupled with an embedded systems controller and CMOS image sensor.

    Science.gov (United States)

    Rosenbloom, Alan John; Gandhi, Heer Robin; Subrebost, George Lopez

    2009-01-01

    Continuous monitoring of specific metabolite and drug levels within a patient's blood can contribute to shorter hospital stays and more successful treatment of both chronic and acute diseases. Intravenous microdialysis is an attractive technology for continuous venous blood sampling that can be used to manage tight glucose control and to sample a large variety of molecules from human blood. In combination with lab-on-a-chip architectures, microdialysis could provide continuous monitoring of important diagnostic and therapeutic substances. Unfortunately, microdialysis is inherently variable and non-transparent, i.e., errors in sampling cannot be detected and corrected in real-time. A portable microdialysis system is presented that gauges membrane diffusive capacity by using a fluorescent tracer, providing a method to track the intrinsic variability. An embedded systems controller and CMOS image sensor is used to measure and wirelessly communicate fluorescent tracer levels. The controller has the capability to generate alarms when probe performance deteriorates, making microdialysis both more accurate and robust for clinical use. The potential to integrate a microparticle-based, turbidimetric vancomycin immunoassay with microdialysis is also demonstrated by using a CMOS image sensor to detect changes in turbidity.

  20. Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

    OpenAIRE

    Shoji Kawahito; Min-Woong Seo

    2016-01-01

    This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise...

  1. Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

    Science.gov (United States)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

    2016-05-01

    In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

  2. 1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Guo-Neng Lu

    2009-01-01

    Full Text Available We present a single-transistor pixel for CMOS image sensors (CIS. It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

  3. Low-power realization in main blocks of CMOS APS image sensor

    Science.gov (United States)

    Gao, Wei; Shen, Edward; Hornsey, Richard I.

    2005-09-01

    This paper addresses the optimization of power at the circuit level in the main blocks of CMOS APS image sensors. A pixel bias current of zero during the readout period is shown to reduce the static power and enhance the settling time of the pixel. A balanced operational transconductance amplifier (OTA) has been demonstrated to be a better candidate as an amplifier when employed in a correlated double sampling (CDS) circuit or as a comparator in an analog-to-digital (A/D) converter, as compared to a Miller two-stage amplifier. Using common-mode feedback (CMFB) in an OTA can further reduce the quiescent power of the amplifier. The low power capability of a CMFB OTA is discussed in this paper by performing a comparison with a conventional OTA using a 0.18 μm technology.

  4. Non-Linearity in Wide Dynamic Range CMOS Image Sensors Utilizing a Partial Charge Transfer Technique

    Directory of Open Access Journals (Sweden)

    Izhal Abdul Halin

    2009-11-01

    Full Text Available The partial charge transfer technique can expand the dynamic range of a CMOS image sensor by synthesizing two types of signal, namely the long and short accumulation time signals. However the short accumulation time signal obtained from partial transfer operation suffers of non-linearity with respect to the incident light. In this paper, an analysis of the non-linearity in partial charge transfer technique has been carried, and the relationship between dynamic range and the non-linearity is studied. The results show that the non-linearity is caused by two factors, namely the current diffusion, which has an exponential relation with the potential barrier, and the initial condition of photodiodes in which it shows that the error in the high illumination region increases as the ratio of the long to the short accumulation time raises. Moreover, the increment of the saturation level of photodiodes also increases the error in the high illumination region.

  5. Non-Linearity in Wide Dynamic Range CMOS Image Sensors Utilizing a Partial Charge Transfer Technique

    Science.gov (United States)

    Shafie, Suhaidi; Kawahito, Shoji; Halin, Izhal Abdul; Hasan, Wan Zuha Wan

    2009-01-01

    The partial charge transfer technique can expand the dynamic range of a CMOS image sensor by synthesizing two types of signal, namely the long and short accumulation time signals. However the short accumulation time signal obtained from partial transfer operation suffers of non-linearity with respect to the incident light. In this paper, an analysis of the non-linearity in partial charge transfer technique has been carried, and the relationship between dynamic range and the non-linearity is studied. The results show that the non-linearity is caused by two factors, namely the current diffusion, which has an exponential relation with the potential barrier, and the initial condition of photodiodes in which it shows that the error in the high illumination region increases as the ratio of the long to the short accumulation time raises. Moreover, the increment of the saturation level of photodiodes also increases the error in the high illumination region. PMID:22303133

  6. Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

    Science.gov (United States)

    Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

    2014-01-01

    This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

  7. CMOS image sensor with organic photoconductive layer having narrow absorption band and proposal of stack type solid-state image sensors

    Science.gov (United States)

    Takada, Shunji; Ihama, Mikio; Inuiya, Masafumi

    2006-02-01

    Digital still cameras overtook film cameras in Japanese market in 2000 in terms of sales volume owing to their versatile functions. However, the image-capturing capabilities such as sensitivity and latitude of color films are still superior to those of digital image sensors. In this paper, we attribute the cause for the high performance of color films to their multi-layered structure, and propose the solid-state image sensors with stacked organic photoconductive layers having narrow absorption bands on CMOS read-out circuits.

  8. CMOS Image Sensor and System for Imaging Hemodynamic Changes in Response to Deep Brain Stimulation.

    Science.gov (United States)

    Zhang, Xiao; Noor, Muhammad S; McCracken, Clinton B; Kiss, Zelma H T; Yadid-Pecht, Orly; Murari, Kartikeya

    2016-06-01

    Deep brain stimulation (DBS) is a therapeutic intervention used for a variety of neurological and psychiatric disorders, but its mechanism of action is not well understood. It is known that DBS modulates neural activity which changes metabolic demands and thus the cerebral circulation state. However, it is unclear whether there are correlations between electrophysiological, hemodynamic and behavioral changes and whether they have any implications for clinical benefits. In order to investigate these questions, we present a miniaturized system for spectroscopic imaging of brain hemodynamics. The system consists of a 144 ×144, [Formula: see text] pixel pitch, high-sensitivity, analog-output CMOS imager fabricated in a standard 0.35 μm CMOS process, along with a miniaturized imaging system comprising illumination, focusing, analog-to-digital conversion and μSD card based data storage. This enables stand alone operation without a computer, nor electrical or fiberoptic tethers. To achieve high sensitivity, the pixel uses a capacitive transimpedance amplifier (CTIA). The nMOS transistors are in the pixel while pMOS transistors are column-parallel, resulting in a fill factor (FF) of 26%. Running at 60 fps and exposed to 470 nm light, the CMOS imager has a minimum detectable intensity of 2.3 nW/cm(2) , a maximum signal-to-noise ratio (SNR) of 49 dB at 2.45 μW/cm(2) leading to a dynamic range (DR) of 61 dB while consuming 167 μA from a 3.3 V supply. In anesthetized rats, the system was able to detect temporal, spatial and spectral hemodynamic changes in response to DBS.

  9. An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

    Science.gov (United States)

    Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

    2015-03-06

    An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

  10. Optical confinement methods for continued scaling of CMOS image sensor pixels.

    Science.gov (United States)

    Fesenmaier, Christian C; Huo, Yijie; Catrysse, Peter B

    2008-12-08

    The pixels that make up CMOS image sensors have steadily decreased in size over the last decade. This scaling has two effects: first, the amount of light incident on each pixel decreases, making optical efficiency, i.e., the collection of each photon, more important. Second, diffraction comes into play when pixel size approaches the wavelength of visible light, resulting in increased spatial optical crosstalk. To address these two effects, we investigate and compare three methods for guiding incident light from the microlens down to the photodiode. Two of these techniques rely on total internal reflection (TIR) at the boundary between dielectric media of different refractive indices, while the third uses reflection at a metal-dielectric interface to confine the light. Simulations are performed using a finite-difference time-domain (FDTD) method on a realistic 1.75-mum pixel model for on-axis as well as angled incidence. We evaluate the optical efficiency and spatial crosstalk performance of these methods compared to a reference pixel and find significant (10%) improvement for the TIR designs with properly chosen parameters and nearly full spatial crosstalk elimination using metal to confine the light. We also show that these improvements are comparable to those achieved by thinning the image sensor stack.

  11. Self-amplified CMOS image sensor using a current-mode readout circuit

    Science.gov (United States)

    Santos, Patrick M.; de Lima Monteiro, Davies W.; Pittet, Patrick

    2014-05-01

    The feature size of the CMOS processes decreased during the past few years and problems such as reduced dynamic range have become more significant in voltage-mode pixels, even though the integration of more functionality inside the pixel has become easier. This work makes a contribution on both sides: the possibility of a high signal excursion range using current-mode circuits together with functionality addition by making signal amplification inside the pixel. The classic 3T pixel architecture was rebuild with small modifications to integrate a transconductance amplifier providing a current as an output. The matrix with these new pixels will operate as a whole large transistor outsourcing an amplified current that will be used for signal processing. This current is controlled by the intensity of the light received by the matrix, modulated pixel by pixel. The output current can be controlled by the biasing circuits to achieve a very large range of output signal levels. It can also be controlled with the matrix size and this permits a very high degree of freedom on the signal level, observing the current densities inside the integrated circuit. In addition, the matrix can operate at very small integration times. Its applications would be those in which fast imaging processing, high signal amplification are required and low resolution is not a major problem, such as UV image sensors. Simulation results will be presented to support: operation, control, design, signal excursion levels and linearity for a matrix of pixels that was conceived using this new concept of sensor.

  12. A high performance multi-tap CMOS lock-in pixel image sensor for biomedical applications

    Science.gov (United States)

    Seo, Min-Woong; Shirakawa, Yuya; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

    2017-02-01

    We have developed and evaluated the large full well capacity (FWC) for wide signal detection range and low temporal noise for high sensitivity lock-in pixel CMOS image sensor (CIS) embedded with two storage-diodes (SDs). In addition, for fast charge transfer from photodiode (PD) to SDs, a lateral electric field charge modulator (LEFM) is used for the developed lock-in pixel. As a result, the time-resolved CIS achieves a very large FWC of approximately 7000e-, low temporal random noise of 1.17e-rms at 45fps with true correlated double sampling (CDS) operation, and fast intrinsic response less than 500ps at 635nm. The proposed imager has an effective pixel array of 128(H)×256(V) and a pixel size of 11.2×11.2μm2. The sensor chip is fabricated by a Dongbu HiTek 1P4M 0.11μm CIS process.

  13. A high fill-factor low dark leakage CMOS image sensor with shared-pixel design

    Science.gov (United States)

    Seo, Min-Woong; Yasutomi, Keita; Kagawa, Keiichiro; Kawahito, Shoji

    2014-03-01

    We have developed and evaluated the high responsivity and low dark leakage CMOS image sensor with the ring-gate shared-pixel design. A ring-gate shared-pixel design with a high fill factor makes it possible to achieve the low-light imaging. As eliminating the shallow trench isolation in the proposed pixel, the dark leakage current is significantly decreased because one of major dark leakage sources is removed. By sharing the in-pixel transistors such as a reset transistor, a select transistor, and a source follower amplifier, each pixel has a high fill-factor of 43 % and high sensitivity of 144.6 ke-/lx·sec. In addition, the effective number of transistors per pixel is 1.75. The proposed imager achieved the relatively low dark leakage current of about 104.5 e-/s (median at 60°C), corresponding to a dark current density Jdark_proposed of about 30 pA/cm2. In contrast, the conventional type test pixel has a large dark leakage current of 2450 e-/s (median at 60°C), corresponding to Jdark_conventional of about 700 pA/cm2. Both pixels have a same pixel size of 7.5×7.5 μm2 and are fabricated in same process.

  14. A CMOS time-of-flight range image sensor using draining only modulation structure

    Science.gov (United States)

    Han, Sangman; Yasutomi, Keita; Kagawa, Keiichiro; Kawahito, Shoji

    2014-03-01

    This paper presents new structure and method of charge modulation for CMOS ToF range image sensors using pinned photodiodes. Proposed pixel structure, the draining only modulator (DOM), allows us to achieve high-speed charge transfer by generating lateral electric field from the pinned photo-diode (PPD) to the pinned storage-diode (PSD). Generated electrons by PPD are transferred to the PSD or drained off through the charge draining gate (TXD). This structure realizes trapping-less charge transfer from the PPD to PSD. To accelerate the speed of charge transfer, the generation of high lateral electric field is necessary. To generate the electric field, the width of the PPD is changed along the direction of the charge transfer. The PPD is formed by the p+ and n layer on the p-substrate. The PSD is created by doping another n type layer for higher impurity concentration than that of the n layer in the PPD. This creates the potential difference between the PPD and PSD. Another p layer underneath the n-layer of the PSD is created for preventing the injection of unwanted carrier from the substrate to the PSD. The range is calculated with signals in the three consecutive sub-frames; one for delay sensitive charge by setting the light pulse timing at the edge of TXD pulse, another for delay independent charge by setting the light pulse timing during the charge transfer, and the other for ambient light charge by setting the light pulse timing during the charge draining. To increase the photo sensitivity while realizing high-speed charge transfer, the pixel consists of 16 sub-pixels and a source follower amplifier. The outputs of 16 sub-pixels are connected to a charge sensing node which has MOS capacitor for increasing well capacity. The pixel array has 313(Row) x 240(Column) pixels and the pixel pitch is 22.4μm. A ToF range imager prototype using the DOM pixels is designed and implemented with 0.11um CMOS image sensor process. The accumulated signal intensity in the PSD

  15. High-speed charge transfer pinned-photodiode for a CMOS time-of-flight range image sensor

    Science.gov (United States)

    Takeshita, Hiroaki; Sawada, Tomonari; Iida, Tetsuya; Yasutomi, Keita; Kawahito, Shoji

    2010-01-01

    This paper presents a structure and method of range calculation for CMOS time-of-flight(TOF) range image sensors using pinned photodiodes. In the proposed method, a LED light with short pulse width and small duty ratio irradiates the objects and a back-reflected light is received by the CMOS TOF range imager.Each pixel has a pinned photodiode optimized for high speed charge transfer and unwanted charge draining. In TOF range image sensors, high speed charge transfer from the light receiving part to a charge accumulator is essential.It was found that the fastest charge transfer can be realized when the lateral electric field along the axis of charge transfer is constant and this conditon is met when the shape of the diode exactly follows the relationship between the fully-depleted potential and width. A TOF range imager prototype is designed and implemented with 0.18um CMOS image sensor technology with pinned photodiode 4transistor(T) pixels. The measurement results show that the charge transfer time is a few ns from the pinned photodiode to a charge accumulator.

  16. A novel CMOS image sensor system for quantitative loop-mediated isothermal amplification assays to detect food-borne pathogens.

    Science.gov (United States)

    Wang, Tiantian; Kim, Sanghyo; An, Jeong Ho

    2017-02-01

    Loop-mediated isothermal amplification (LAMP) is considered as one of the alternatives to the conventional PCR and it is an inexpensive portable diagnostic system with minimal power consumption. The present work describes the application of LAMP in real-time photon detection and quantitative analysis of nucleic acids integrated with a disposable complementary-metal-oxide semiconductor (CMOS) image sensor. This novel system works as an amplification-coupled detection platform, relying on a CMOS image sensor, with the aid of a computerized circuitry controller for the temperature and light sources. The CMOS image sensor captures the light which is passing through the sensor surface and converts into digital units using an analog-to-digital converter (ADC). This new system monitors the real-time photon variation, caused by the color changes during amplification. Escherichia coli O157 was used as a proof-of-concept target for quantitative analysis, and compared with the results for Staphylococcus aureus and Salmonella enterica to confirm the efficiency of the system. The system detected various DNA concentrations of E. coli O157 in a short time (45min), with a detection limit of 10fg/μL. The low-cost, simple, and compact design, with low power consumption, represents a significant advance in the development of a portable, sensitive, user-friendly, real-time, and quantitative analytic tools for point-of-care diagnosis.

  17. [Paper] Low-light Color Reproduction by Selective Averaging in Multi-aperture Camera with Bayer Color-filter Low-noise CMOS Image Sensors

    National Research Council Canada - National Science Library

    Zhang, Bo; Kagawa, Keiichiro; Takasawa, Taishi; Seo, Min Woong; Yasutomi, Keita; Kawahito, Shoji

    2015-01-01

    .... In the prototype camera, which is being developed, low-noise Bayer color-filter 0.18um CMOS image sensors based on the folding-integration and cyclic column ADCs with 1280 x 1024 effective pixels are utilized...

  18. First tests of CHERWELL, a Monolithic Active Pixel Sensor: A CMOS Image Sensor (CIS) using 180 nm technology

    Energy Technology Data Exchange (ETDEWEB)

    Mylroie-Smith, James, E-mail: j.mylroie-smith@qmul.ac.uk [Queen Mary, University of London (United Kingdom); Kolya, Scott; Velthuis, Jaap [University of Bristol (United Kingdom); Bevan, Adrian; Inguglia, Gianluca [Queen Mary, University of London (United Kingdom); Headspith, Jon; Lazarus, Ian; Lemon, Roy [Daresbury Laboratory, STFC (United Kingdom); Crooks, Jamie; Turchetta, Renato; Wilson, Fergus [Rutherford Appleton Laboratory, STFC (United Kingdom)

    2013-12-11

    The Cherwell is a 4T CMOS sensor in 180 nm technology developed for the detection of charged particles. Here, the different test structures on the sensor will be described and first results from tests on the reference pixel variant are shown. The sensors were shown to have a noise of 12 e{sup −} and a signal to noise up to 150 in {sup 55}Fe.

  19. Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

    Institute of Scientific and Technical Information of China (English)

    ZHAO Shibin; YAO Suying; NIE Kaiming; XU Jiangtao

    2010-01-01

    A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN)cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sample-and-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp)sharing is also introduced to decrease the power dissipation of traditional multi-stage switched capacitor DPGA.The circuit is designed and simulated using 1P6M 0.18 μm 1.8 V/3.3 V process.Simulation results indicate that the proposed CDS scheme can achieve an FPN of less than 1 mV.The total sampling capacitor per column is 0.9 pF and no column-wise power is dissipated.The die area and FPN value are cut by 70% and 41% respectively compared with amplifier-based CDS.The op-amp sharing gain stage can achieve a 12-bit precision and also implement an 8-bit gain controlling within a gain range of 24 dB.Its power consumption is 1.4 mW,which is reduced by 57% compared with traditional schemes.The proposed readout circuit is suitable for the application of low power cost-sensitive imaging systems.

  20. Image Quality Assessment of a CMOS/Gd2O2S:Pr,Ce,F X-Ray Sensor

    Directory of Open Access Journals (Sweden)

    Christos Michail

    2015-01-01

    Full Text Available The aim of the present study was to examine the image quality performance of a CMOS digital imaging optical sensor coupled to custom made gadolinium oxysulfide powder scintillators, doped with praseodymium, cerium, and fluorine (Gd2O2S:Pr,Ce,F. The screens, with coating thicknesses 35.7 and 71.2 mg/cm2, were prepared in our laboratory from Gd2O2S:Pr,Ce,F powder (Phosphor Technology, Ltd. by sedimentation on silica substrates and were placed in direct contact with the optical sensor. Image quality was determined through single index (information capacity, IC and spatial frequency dependent parameters, by assessing the Modulation Transfer Function (MTF and the Normalized Noise Power Spectrum (NNPS. The MTF was measured using the slanted-edge method. The CMOS sensor/Gd2O2S:Pr,Ce,F screens combinations were irradiated under the RQA-5 (IEC 62220-1 beam quality. The detector response function was linear for the exposure range under investigation. Under the general radiography conditions, both Gd2O2S:Pr,Ce,F screen/CMOS combinations exhibited moderate imaging properties, in terms of IC, with previously published scintillators, such as CsI:Tl, Gd2O2S:Tb, and Gd2O2S:Eu.

  1. A 33-mpixel 120-fps CMOS image sensor using 0.11-μm CIS process

    Science.gov (United States)

    Yasue, Toshio; Hayashida, Tetsuya; Yonai, Jun; Kitamura, Kazuya; Watabe, Toshihisa; Ootake, Hiroshi; Shimamoto, Hiroshi; Kosugi, Tomohiko; Watanabe, Takashi; Aoyama, Satoshi; Kawahito, Shoji

    2014-05-01

    We have been researching and developing a CMOS image sensor that has 2.8 μm x 2.8 μm pixel, 33-Mpixel resolution (7680 horizontal pixels x 4320 vertical pixels), 120-fps frame rate, and 12-bit analog-to-digital converter for "8K Super Hi-Vision." In order to improve its sensitivity, we used a 0.11-μm nanofabricated process and attempted to increase the conversion gain from an electron charge to a voltage in the pixel. The prototyped image sensor shows a sensitivity of 2.4 V/lx•s, which is 1.6 times higher than that of a conventional image sensor. This image sensor also realized the input-referred random noise as low as 2.1 e-rms.

  2. Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Assim Boukhayma

    2016-04-01

    Full Text Available This paper presents an overview of the read noise in CMOS image sensors (CISs based on four-transistors (4T pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are derived and discussed. The noise reduction techniques that can be implemented at the column and pixel level are verified by transient noise simulations, measurement and results from recently-published low noise CIS. We show how recently-reported process refinement, leading to the reduction of the sense node capacitance, can be combined with an optimal in-pixel source follower design to reach a sub-0.3 \\(e^{-}_{rms}\\ read noise at room temperature. This paper also discusses the impact of technology scaling on the CIS read noise. It shows how designers can take advantage of scaling and how the Metal-Oxide-Semiconductor (MOS transistor gate leakage tunneling current appears as a challenging limitation. For this purpose, both simulation results of the gate leakage current and 1/f noise data reported from different foundries and technology nodes are used.

  3. Effect of Cu pad morphology on direct-Cu pillar formation in CMOS image sensors

    Science.gov (United States)

    Choi, Eunmi; Kim, Areum; Cui, Eunwha; Lee, Ukjae; Son, Hyung Bin; Hahn, Sang June; Pyo, Sung Gyu

    2014-09-01

    We report the feasibility of forming Ni bumps directly on Cu pads in CMOS image sensor (CIS) logic elements formed by Cu wires with diameters of less than 65 nm. The direct Ni bump process proposed in this study simplifies the fabrication process and reduces costs by eliminating the need for Al pad process. In addition, this process can secure the margin of the final layer, enabling the realization of thin camera modules. In this study, we evaluated the effect of pad annealing on the direct formation of Ni bumps over Cu pads. The results suggest that the morphology of the Cu pad varies depending on the annealing sequence, and post-passivation annealing resulted in fewer defects than pad etch annealing. The shear stress of the Ni bumps was 57.77 mgf/m2, which is six times greater than the corresponding reference value. Furthermore, we evaluated the reliability of a chip with an anisotropic conductive film (ACF) and a non-conducting paste (NCP) by using high-temperature storage (HTS), thermal cycling (TC), and wet high-temperature storage (WHTS) reliability tests. The evaluation results suggest the absence of abnormalities in all samples. [Figure not available: see fulltext.

  4. Modeling random telegraph signal noise in CMOS image sensor under low light based on binomial distribution

    Science.gov (United States)

    Yu, Zhang; Xinmiao, Lu; Guangyi, Wang; Yongcai, Hu; Jiangtao, Xu

    2016-07-01

    The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random telegraph signal noise in the pixel source follower based on the binomial distribution is set up. The number of electrons captured or released by the oxide traps in the unit time is described as the random variables which obey the binomial distribution. As a result, the output states and the corresponding probabilities of the first and the second samples of the correlated double sampling circuit are acquired. The standard deviation of the output states after the correlated double sampling circuit can be obtained accordingly. In the simulation section, one hundred thousand samples of the source follower MOSFET have been simulated, and the simulation results show that the proposed model has the similar statistical characteristics with the existing models under the effect of the channel length and the density of the oxide trap. Moreover, the noise histogram of the proposed model has been evaluated at different environmental temperatures. Project supported by the National Natural Science Foundation of China (Grant Nos. 61372156 and 61405053) and the Natural Science Foundation of Zhejiang Province of China (Grant No. LZ13F04001).

  5. Modeling random telegraph signal noise in CMOS image sensor under low light based on binomial distribution

    Institute of Scientific and Technical Information of China (English)

    张钰; 逯鑫淼; 王光义; 胡永才; 徐江涛

    2016-01-01

    The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random telegraph signal noise in the pixel source follower based on the binomial distribution is set up. The number of electrons captured or released by the oxide traps in the unit time is described as the random variables which obey the binomial distribution. As a result, the output states and the corresponding probabilities of the first and the second samples of the correlated double sampling circuit are acquired. The standard deviation of the output states after the correlated double sampling circuit can be obtained accordingly. In the simulation section, one hundred thousand samples of the source follower MOSFET have been simulated, and the simulation results show that the proposed model has the similar statistical characteristics with the existing models under the effect of the channel length and the density of the oxide trap. Moreover, the noise histogram of the proposed model has been evaluated at different environmental temperatures.

  6. Noise calculation model and analysis of high-gain readout circuits for CMOS image sensors

    Science.gov (United States)

    Kawahito, Shoji; Itoh, Shinya

    2008-02-01

    A thermal noise calculation model of high-gain switched-capacitor column noise cancellers for CMOS image sensors is presented. In the high-gain noise canceller with a single noise cancelling stage, the reset noise of the readout circuits dominates the noise at high gain. Using the double-stage architecture using a switched-capacitor gain stage and a sample-and-hold stage using two sampling capacitors, the reset noise of the gain stage can be cancelled. The resulting input referred thermal noise power of high-gain double-stage switched-capacitor noise canceller is revealed to be proportional to (g_a/g_s)/GC_L where g_a, G and C_L are the transconductance, gain and output capacitance of the amplifier, respectively, and g_s is the output conductance of an in-pixel source follower. An important contribution of the proposed noise calculation formula is the inclusion of the influence of the transconductance ratio of the amplifier to that of the source follower. For low-noise design, it is important that the transconductance of the amplifier used in the noise canceller is minimized under the condition of meeting the required response time of the switched capacitor amplifier which is inversely proportional to the cutoff angular frequency.

  7. An investigation of medical radiation detection using CMOS image sensors in smartphones

    Energy Technology Data Exchange (ETDEWEB)

    Kang, Han Gyu [Department of Senior Healthcare, Graduate School of Eulji University, Daejeon 301-746 (Korea, Republic of); Song, Jae-Jun [Department of Otorhinolaryngology-Head & Neck Surgery, Korea University, Guro Hospital,148, Gurodong-ro, Guro-gu, Seoul 152-703 (Korea, Republic of); Lee, Kwonhee [Graduate Program in Bio-medical Science, Korea University, 2511 Sejong-ro, Sejong City 339-770 (Korea, Republic of); Nam, Ki Chang [Department of Medical Engineering, College of Medicine, Dongguk University, 32 Dongguk-ro, Goyang-si, Gyeonggi-do 410-820 (Korea, Republic of); Hong, Seong Jong; Kim, Ho Chul [Department of Radiological Science, Eulji University, 553 Yangji-dong, Sujeong-gu, Seongnam-si, Gyeonggi-do 431-713 (Korea, Republic of)

    2016-07-01

    Medical radiation exposure to patients has increased with the development of diagnostic X-ray devices and multi-channel computed tomography (CT). Despite the fact that the low-dose CT technique can significantly reduce medical radiation exposure to patients, the increasing number of CT examinations has increased the total medical radiation exposure to patients. Therefore, medical radiation exposure to patients should be monitored to prevent cancers caused by diagnostic radiation. However, without using thermoluminescence or glass dosimeters, it is hardly measure doses received by patients during medical examinations accurately. Hence, it is necessary to develop radiation monitoring devices and algorithms that are reasonably priced and have superior radiation detection efficiencies. The aim of this study is to investigate the feasibility of medical dose measurement using complementary metal oxide semiconductor (CMOS) sensors in smartphone cameras with an algorithm to extract the X-ray interacted pixels. We characterized the responses of the CMOS sensors in a smartphone with respect to the X-rays generated by a general diagnostic X-ray system. The characteristics of the CMOS sensors in a smartphone camera, such as dose response linearity, dose rate dependence, energy dependence, angular dependence, and minimum detectable activity were evaluated. The high energy gamma-ray of 662 keV from Cs-137 can be detected using the smartphone camera. The smartphone cameras which employ the developed algorithm can detect medical radiations.

  8. Development of a 55 μm pitch 8 inch CMOS image sensor for the high resolution NDT application

    Science.gov (United States)

    Kim, M. S.; Kim, G.; Cho, G.; Kim, D.

    2016-11-01

    A CMOS image sensor (CIS) with a large area for the high resolution X-ray imaging was designed. The sensor has an active area of 125 × 125 mm2 comprised with 2304 × 2304 pixels and a pixel size of 55 × 55 μm2. First batch samples were fabricated by using an 8 inch silicon CMOS image sensor process with a stitching method. In order to evaluate the performance of the first batch samples, the electro-optical test and the X-ray test after coupling with an image intensifier screen were performed. The primary results showed that the performance of the manufactured sensors was limited by a large stray capacitance from the long path length between the analog multiplexer on the chip and the bank ADC on the data acquisition board. The measured speed and dynamic range were limited up to 12 frame per sec and 55 dB respectively, but other parameters such as the MTF, NNPS and DQE showed a good result as designed. Based on this study, the new X-ray CIS with ~ 50 μm pitch and ~ 150 cm2 active area are going to be designed for the high resolution X-ray NDT equipment for semiconductor and PCB inspections etc.

  9. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors.

    Science.gov (United States)

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-11-06

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within -T(clk)~+T(clk). A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration.

  10. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Zhiyuan Gao

    2015-11-01

    Full Text Available This paper presents a dynamic range (DR enhanced readout technique with a two-step time-to-digital converter (TDC for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration.

  11. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

    Science.gov (United States)

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-01-01

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration. PMID:26561819

  12. A QVGA-size CMOS time-of-flight range image sensor with background light charge draining structure

    Science.gov (United States)

    Ushinaga, Takeo; Halin, Izhal Abdul; Sawada, Tomonari; Kawahito, Shoji; Homma, Mitsuru; Maeda, Yasunari

    2006-02-01

    3-D imaging systems can be used in a variety of applications such as in automobile, medicine, robot vision systems, security and so on. Recently many kinds of range finding methods have been proposed for 3-D imaging systems. This paper presents a new type of CMOS range image sensor based on the Time-of-Flight (TOF)principle with a spatial resolution of 336 × 252 (QVGA) and pixels of 15 × 15 μm2 size. A pixel structure of the sensor consists of single layer polysilicon gates on thick field oxide and has a function of background light induced charge reduction. The chip was fabricated in a 0.35 μm standard CMOS process with two poly and three metal layers. The presented sensor achieves a minimum range resolution of 2.8cm at framerate of 30fps and the resolution is improved to 4.2mm for 10 frames averaging, which corresponds to 3fps.

  13. Performance and Development Tendency on Cmos Image Sensors%图像传感器CMOS的性能及发展趋势

    Institute of Scientific and Technical Information of China (English)

    王旭颖

    2013-01-01

    自20世纪90年代以来,互补金属氧化物半导体(CMOS)图像传感器随着大规模集成电路技术的提高,发展势头也越来越强劲。主要介绍了CMOS图像传感器的工作过程,通过CMOS与电荷耦合器件(CCD)的性能参数对比,凸显出了CMOS的性能优势,并指出了CMOS的发展趋势。%Since 1990s, With the development of the large-scale integrated circuit technology, Complementary Met-al-Oxide-Semiconductor(CMOS)image sensors gets a strong development. Mainly introduce the working process of CMOS image sensors, Comparing with CMOS image sensors and Charge Coupled Device(CCD)in performance param-eters, highlights performance advantages of CMOS image sensors, and discuss the development tendency of CMOS im-age sensors.

  14. Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization

    Energy Technology Data Exchange (ETDEWEB)

    Zhao, Chumin; Kanicki, Jerzy, E-mail: kanicki@eecs.umich.edu [Solid-State Electronics Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109 (United States); Konstantinidis, Anastasios C. [Department of Medical Physics and Biomedical Engineering, University College London, London WC1E 6BT, United Kingdom and Diagnostic Radiology and Radiation Protection, Christie Medical Physics and Engineering, The Christie NHS Foundation Trust, Manchester M20 4BX (United Kingdom); Patel, Tushita [Department of Physics, University of Virginia, Charlottesville, Virginia 22908 (United States)

    2015-11-15

    Purpose: Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50–300 e{sup −}) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). Methods: In this study, imaging performance of a large area (29 × 23 cm{sup 2}) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165–400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. Results: The LFW mode shows better DQE at low air kerma (K{sub a} < 10 μGy) and should be used for DBT. At current DBT applications, air kerma (K{sub a} ∼ 10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165–400 μm in size can be resolved using a MGD range of 0.3–1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at

  15. Proximity gettering of C3H5 carbon cluster ion-implanted silicon wafers for CMOS image sensors: Gettering effects of transition metal, oxygen, and hydrogen impurities

    Science.gov (United States)

    Kurita, Kazunari; Kadono, Takeshi; Okuyama, Ryousuke; Hirose, Ryo; Onaka-Masada, Ayumi; Koga, Yoshihiro; Okuda, Hidehiko

    2016-12-01

    A new technique is described for manufacturing silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication. It is demonstrated that this technique can implant wafers simultaneously with carbon and hydrogen elements that form the projection range by using hydrocarbon compounds. Furthermore, these wafers can getter oxygen impurities out-diffused from the silicon substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen-related defects in the device active regions and improve electrical performance characteristics, such as dark current and image lag characteristics. The new technique enables the formation of high-gettering-capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly reduce dark current in advanced CMOS image sensors.

  16. 3D time-of-flight distance measurement with custom solid-state image sensors in CMOS/CCD-technology

    OpenAIRE

    Lange, Robert de

    2006-01-01

    Three-D time-of-flight distance measurement with custom solid-state image sensors in CMOS/CCD-technology Da wir in einer dreidimensionalen Welt leben, erfordert eine geeignete Beschreibung unserer Umwelt für viele Anwendungen Kenntnis über die relative Position und Bewegung der verschiedenen Objekte innerhalb einer Szene. Die daraus resultierende Anforderung räumlicher Wahrnehmung ist in der Natur dadurch gelöst, daß die meisten Tiere mindestens zwei Augen haben. Diese Fähigkeit des Stere...

  17. A wide dynamic range CMOS image sensor with dual charge storage in a pixel and a multiple sampling technique

    Science.gov (United States)

    Shafie, Suhaidi; Kawahito, Shoji

    2008-02-01

    This paper presents a dynamic range expansion technique of CMOS image sensors with dual charge storage in a pixel and multiple exposures. Each pixel contains two photodiodes, PD1 and PD2 whose sensitivity can be set independently by the accumulation time. The difference of charge accumulation time in both photodiode can be manipulated to expand the dynamic range of the sensor. It allows flexible control of the dynamic range since the accumulation time in PD2 is adjustable. The multiple exposure technique used in the sensor reduces the motion blur in the synthesized wide dynamic range image when capturing fast-moving objects. It also reduces the signal-to-nose ratio dip at the switching point of the PD1 signal to the PD2 signals in the synthesized wide dynamic range image. A wide dynamic range camera with 320x240 pixels image sensor has been tested. It is found that the sampling of 4 times for the short accumulation time signals is sufficient for the reduction of motion blur in the synthesized wide dynamic range image, and the signal-to-noise ratio dip at the switching point of the PD1 signal to the PD2 signal is improved by 6 dB using 4 short-time exposures.

  18. The Dexela 2923 CMOS X-ray detector: A flat panel detector based on CMOS active pixel sensors for medical imaging applications

    Science.gov (United States)

    Konstantinidis, Anastasios C.; Szafraniec, Magdalena B.; Speller, Robert D.; Olivo, Alessandro

    2012-10-01

    Complementary metal-oxide-semiconductors (CMOS) active pixel sensors (APS) have been introduced recently in many scientific applications. This work reports on the performance (in terms of signal and noise transfer) of an X-ray detector that uses a novel CMOS APS which was developed for medical X-ray imaging applications. For a full evaluation of the detector's performance, electro-optical and X-ray characterizations were carried out. The former included measuring read noise, full well capacity and dynamic range. The latter, which included measuring X-ray sensitivity, presampling modulation transfer function (pMTF), noise power spectrum (NPS) and the resulting detective quantum efficiency (DQE), was assessed under three beam qualities (28 kV, 50 kV (RQA3) and 70 kV (RQA5) using W/Al) all in accordance with the IEC standard. The detector features an in-pixel option for switching the full well capacity between two distinct modes, high full well (HFW) and low full well (LFW). Two structured CsI:Tl scintillators of different thickness (a “thin” one for high resolution and a thicker one for high light efficiency) were optically coupled to the sensor array to optimize the performance of the system for different medical applications. The electro-optical performance evaluation of the sensor results in relatively high read noise (∼360 e-), high full well capacity (∼1.5×106 e-) and wide dynamic range (∼73 dB) under HFW mode operation. When the LFW mode is used, the read noise is lower (∼165) at the expense of a reduced full well capacity (∼0.5×106 e-) and dynamic range (∼69 dB). The maximum DQE values at low frequencies (i.e. 0.5 lp/mm) are high for both HFW (0.69 for 28 kV, 0.71 for 50 kV and 0.75 for 70 kV) and LFW (0.69 for 28 kV and 0.7 for 50 kV) modes. The X-ray performance of the studied detector compares well to that of other mammography and general radiography systems, obtained under similar experimental conditions. This demonstrates the suitability

  19. Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel

    Directory of Open Access Journals (Sweden)

    Orly Yadid-Pecht

    2012-07-01

    Full Text Available Modern “smart” CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage “smart” image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR and Dynamic Range (DR as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

  20. Low-voltage 96 dB snapshot CMOS image sensor with 4.5 nW power dissipation per pixel.

    Science.gov (United States)

    Spivak, Arthur; Teman, Adam; Belenky, Alexander; Yadid-Pecht, Orly; Fish, Alexander

    2012-01-01

    Modern "smart" CMOS sensors have penetrated into various applications, such as surveillance systems, bio-medical applications, digital cameras, cellular phones and many others. Reducing the power of these sensors continuously challenges designers. In this paper, a low power global shutter CMOS image sensor with Wide Dynamic Range (WDR) ability is presented. This sensor features several power reduction techniques, including a dual voltage supply, a selective power down, transistors with different threshold voltages, a non-rationed logic, and a low voltage static memory. A combination of all these approaches has enabled the design of the low voltage "smart" image sensor, which is capable of reaching a remarkable dynamic range, while consuming very low power. The proposed power-saving solutions have allowed the maintenance of the standard architecture of the sensor, reducing both the time and the cost of the design. In order to maintain the image quality, a relation between the sensor performance and power has been analyzed and a mathematical model, describing the sensor Signal to Noise Ratio (SNR) and Dynamic Range (DR) as a function of the power supplies, is proposed. The described sensor was implemented in a 0.18 um CMOS process and successfully tested in the laboratory. An SNR of 48 dB and DR of 96 dB were achieved with a power dissipation of 4.5 nW per pixel.

  1. Noise in a CMOS digital pixel sensor

    Institute of Scientific and Technical Information of China (English)

    Zhang Chi; Yao Suying; Xu Jiangtao

    2011-01-01

    Based on the study of noise performance in CMOS digital pixel sensor (DPS),a mathematical model of noise is established with the pulse-width-modulation (PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region.In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.

  2. CMOS digital pixel sensors: technology and applications

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  3. Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors.

    Science.gov (United States)

    Kawahito, Shoji; Seo, Min-Woong

    2016-11-06

    This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC). The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median): 0.29 e(-)rms) when compared with the CMS gain of two (2.4 e(-)rms), or 16 (1.1 e(-)rms).

  4. Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Shoji Kawahito

    2016-11-01

    Full Text Available This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs. This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC. The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median: 0.29 e−rms when compared with the CMS gain of two (2.4 e−rms, or 16 (1.1 e−rms.

  5. High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

    Science.gov (United States)

    Ohara, Tetsuo

    2012-01-01

    A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

  6. A Dynamic Range Expansion Technique for CMOS Image Sensors with Dual Charge Storage in a Pixel and Multiple Sampling

    Science.gov (United States)

    Shafie, Suhaidi; Kawahito, Shoji; Itoh, Shinya

    2008-01-01

    A dynamic range expansion technique for CMOS image sensors with dual charge storage in a pixel and multiple sampling technique is presented. Each pixel contains a photodiode and a storage diode which is connected to the photodiode via a separation gate. The sensitivity of the signal charge in the storage diode can be controlled either by a separation gate which limits the charge to flow into the storage diode or by controlling the accumulation time in the storage diode. The operation of the sensitivity control with separation gate techniques is simulated and it is found that a blocking layer to the storage diode plays an important role for high controllability of sensitivity of the storage diode. A prototype chip for testing multiple short time accumulations is fabricated and measured. PMID:27879802

  7. A Dynamic Range Expansion Technique for CMOS Image Sensors with Dual Charge Storage in a Pixel and Multiple Sampling

    Directory of Open Access Journals (Sweden)

    Shinya Itoh

    2008-03-01

    Full Text Available A dynamic range expansion technique for CMOS image sensors with dual charge storage in a pixel and multiple sampling technique is presented. Each pixel contains a photodiode and a storage diode which is connected to the photodiode via a separation gate. The sensitivity of the signal charge in the storage diode can be controlled either by a separation gate which limits the charge to flow into the storage diode or by controlling the accumulation time in the storage diode. The operation of the sensitivity control with separation gate techniques is simulated and it is found that a blocking layer to the storage diode plays an important role for high controllability of sensitivity of the storage diode. A prototype chip for testing multiple short time accumulations is fabricated and measured.

  8. A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs.

    Science.gov (United States)

    Kim, Min-Kyu; Hong, Seong-Kwan; Kwon, Oh-Kyong

    2015-12-26

    This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 μm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 μs to 0.45 μs and random noise from 848.3 μV to 270.4 μV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

  9. Frequency-domain fluorescence lifetime imaging system (pco.flim) based on a in-pixel dual tap control CMOS image sensor

    Science.gov (United States)

    Franke, Robert; Holst, Gerhard A.

    2015-03-01

    The luminescence lifetime as a beneficial analytical parameter is known for many years and is well described by a large variety of publications. Many instruments including 2D measuring systems with cameras have been developed and applied in the past years. However, since the current instrumentation to perform either time- or frequency-domain lifetime measurements is rather complex, new developments in CMOS image sensor technology have achieved to create new image sensors, which can efficiently be integrated into easier-to-handle luminescence lifetime measuring systems. The principle of these modulatable CMOS image sensors, while initially being designed for distance measurements, shows a clear analogy to frequency-domain FLIM measurements, which was proven by researchers [1, 2]. Based on this principle a new CMOS image sensor has been developed, integrated into a camera system and has been investigated within a research project. The image sensor has a resolution of 1024 × 1024 pixels with a 5.6 μm pitch and can be modulated up to 50 MHz. First measurements show an effective dynamic range of larger than 1:1024 (corresponding to 10 bit dynamic). The maximum frame rate is in the range of 90 frames/s in dual-tap mode, resulting in an effective lifetime image frame rate for realistic measurements of approximately 22 frames/s. The camera system pco.flim, featuring that image sensor, generates all required modulation signals from 5 kHz to 50 MHz (sinusoidal and rectangular). It performs advanced pixel correction to generate linear and high-quality images, while the basic lifetime image processing is done in the computer. The modulation frequency can be freely adjusted within the specified range. The characteristics of the camera systems are presented, and first results are discussed using different representations of the data like for example the phasor approach [3], which has been established to provide a more global view to pixelwise fluorescence lifetime data and

  10. A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

    Science.gov (United States)

    Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

    2014-11-17

    A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

  11. Pixel pitch and particle energy influence on the dark current distribution of neutron irradiated CMOS image sensors.

    Science.gov (United States)

    Belloir, Jean-Marc; Goiffon, Vincent; Virmontois, Cédric; Raine, Mélanie; Paillet, Philippe; Duhamel, Olivier; Gaillardin, Marc; Molina, Romain; Magnan, Pierre; Gilard, Olivier

    2016-02-22

    The dark current produced by neutron irradiation in CMOS Image Sensors (CIS) is investigated. Several CIS with different photodiode types and pixel pitches are irradiated with various neutron energies and fluences to study the influence of each of these optical detector and irradiation parameters on the dark current distribution. An empirical model is tested on the experimental data and validated on all the irradiated optical imagers. This model is able to describe all the presented dark current distributions with no parameter variation for neutron energies of 14 MeV or higher, regardless of the optical detector and irradiation characteristics. For energies below 1 MeV, it is shown that a single parameter has to be adjusted because of the lower mean damage energy per nuclear interaction. This model and these conclusions can be transposed to any silicon based solid-state optical imagers such as CIS or Charged Coupled Devices (CCD). This work can also be used when designing an optical imager instrument, to anticipate the dark current increase or to choose a mitigation technique.

  12. Design of CMOS Based Image Sensor with Cantilever Mechanism for Smart Pathological Detection with Opto-Mechanical System

    Directory of Open Access Journals (Sweden)

    Rajeshlaik

    2012-06-01

    Full Text Available patient immobilized on slide under the microscope is extracted with imaging device. Similar kind of setup is designed to detect object with analog transducer circuit system which the mines worker use torchlight over the helmet underground with 4.5 volt of light, with 1 watt bulb is sufficient our Eye can recognize the object, but with CFL it is more brighter in dark condition to detect the object. Here the biomechanical action of the miners Eye & brain coordination inside the mining region where it is very dark to focus the object, the inverter like headlight operates in this condition and helps him to work smoothly for his neural coordination works in balanced. Focal length inversely proportional to the magnification is required to clearly visualize any object, Physically when we see any object we move nearer or far-away and maintain the distance from the object, if any person cannot clearly identify they wear glass of varying power as per their disorder, Electronic CMOS Biosensor with signal conditioning OPAMP gives the strong power to the eye to visualize the image under the microscope converting the charge of APS into the voltage amplified in a nano-second time response. The inverting action of the Eye with 01,which is simulated for Photo-sensor circuit, with equivalent silicon-on-chip based CMOS combination. Thus the detection of cancer cells is very cheap and efficient way in pathological laboratory with CMOS microscope. Comparative studies makes the efficient detection of morphological features of gross tissue section of tumor Cells clearly detected when magnified under 40 x,with CMOS biosensor phototransistor. Patient requires to check his or her body weight, prior to pathological check up, therefore the weighing machine is the very important piezo convertor of mechanical energy of the body into weight and when the smart nano-mechanical cantilever sensor chip integrates with this machine the signal will be more fast .The PH paper as a

  13. CMOS imagers from phototransduction to image processing

    CERN Document Server

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  14. A Two-Step A/D Conversion and Column Self-Calibration Technique for Low Noise CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Jaeyoung Bae

    2014-07-01

    Full Text Available In this paper, a 120 frames per second (fps low noise CMOS Image Sensor (CIS based on a Two-Step Single Slope ADC (TS SS ADC and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times than that of the Single Slope ADC (SS ADC. However, there exist some mismatching errors between the coarse block and the fine block due to the 2-step operation of the TS SS ADC. In general, this makes it difficult to implement the TS SS ADC beyond a 10-bit resolution. In order to improve such errors, a new 4-input comparator is discussed and a high resolution TS SS ADC is proposed. Further, a feedback circuit that enables column self-calibration to reduce the Fixed Pattern Noise (FPN is also described. The proposed chip has been fabricated with 0.13 μm Samsung CIS technology and the chip satisfies the VGA resolution. The pixel is based on the 4-TR Active Pixel Sensor (APS. The high frame rate of 120 fps is achieved at the VGA resolution. The measured FPN is 0.38 LSB, and measured dynamic range is about 64.6 dB.

  15. Performance test and image processing of area CMOS image sensor%面阵CMOS图像传感器性能测试及图像处理

    Institute of Scientific and Technical Information of China (English)

    董建婷; 杨小乐; 董杰

    2013-01-01

    CMOS image sensor have the advantages of simple drive signals, single power supply voltage, high integration, low power consumption and strong radiation resistance. But in the field of space optical remote sensing, CMOS image sensor is not widely applied. The large-scale, high reading rate, high dynamic range CMOS image sensor is urgently in need. The 4 Megapixel CMOS image sensor of LUPA4000 is just such one. So LUPA4000 was chosen as the research target and its performance was tested. The image processing was conducted according to the results of performance test. In the research work, the parameters of defective pixels, response non uniformity (PRNU) and signal to noise ratio(SNR) were tested. The test results show that the CMOS image sensor of LUPA4000 has the following problems: the defective pixels are numerous, the PRNU is not ideal and the SNR is low. So the following image processing methods were adopted: dark background deduction to decrease the dark signal noise, defective pixels replacement to reduce the influence of defective pixels, and nonuniformity correction to reduce PRNU. The different processing combination among the three methods was applied . In order to evaluate the treatment effect of above processing combination, the contrasts of SNR and imaging quality between the original images and processed images were executed. The contrast results show that the method that combined defective pixels replacement with nonuniformity correction is the best combination.%CMOS图像传感器具有驱动简单、单电源供电、集成度高、功耗低、抗辐射能力强等优点。但是在航天光学遥感领域,CMOS图像传感器应用还不普遍。在该领域亟需大规模、高读出速度、大动态范围的图像传感器,CMOS图像传感器LUPA4000正是这样一款高性能面阵图像传感器,因此,选择LUPA4000作为研究对象,对其缺陷像元、光响应非均匀性、信噪比等性能指标进

  16. Study of Shallow Backside Junctions for Backside Illumination of CMOS Image Sensors

    Science.gov (United States)

    Choi, Chung Seok; Yeo, Sang Chul; Kim, Dohwan; Kim, Jongchae; Yoo, Kyung Dong; Lee, Hyuck Mo

    2014-11-01

    Backside illumination complementary metal oxide semiconductor image sensors (BSI CISs) represent an advanced technology that produces high-quality image sensors. However, BSI CISs are limited by high dark signals and noise signals on the backside. To address these problems, backside junctions are commonly used. High-dose backside junctions effectively reduce dark signals and noise signals. The depth of the implantation profile is a key factor in determining the junction depth. A laser thermal annealing process is conducted only near the surface to the activation, and thus broader doping profiles are limitations to be activation of dopants. Changing the dopant from B to BF2 can decrease the implant projected range. However, there are abnormal activation rates for BF2 in applications involving laser thermal annealing processes for shallow junctions. Although the need for BF2 is increasing, a mechanism for its slow activation and low activation rates has not yet been confirmed. Here, we identify the mechanism by which BF2 undergoes low activation after a melting threshold temperature and explain why this phenomenon occurs. In addition, we confirm a condition that provides high activation rates of BF2 and show the reduction of dark signals and noise signals at the high density BSI CISs.

  17. Noise minimization via deep submicron system-on-chip integration in megapixel CMOS imaging sensors

    Science.gov (United States)

    Kozlowski, L. J.

    2006-03-01

    Infrared sensor designers have long maximized S/N ratio by employing pixel-based amplification in conjunction with supplemental noise suppression. Instead, we suppress photodiode noise using novel SoC implementation with simple three transistor pixel; supporting SoC components include a feedback amplifier having elements distributed amongst the pixel and column buffer, a tapered reset clock waveform, and reset timing generator. The tapered reset method does not swell pixel area, compel processing of the correlated reset and signal values, or require additional memory. Integrated in a 2.1 M pixel imager developed for generating high definition television, random noise is ˜8e-at video rates to 225 MHz. Random noise of ˜30e-would otherwise he predicted for the 5 μm 5 μm pixels having 5.5 fF detector capacitance with negligible image lag. Minimum sensor S/N ratio is 52 dB with 1920 by 1080 progressive readout at 60 Hz, 72 Hz and 90 Hz. Fixed pattern noise is <2 DN via on-chip signal processing.

  18. Sensors for 3D Imaging: Metric Evaluation and Calibration of a CCD/CMOS Time-of-Flight Camera

    Directory of Open Access Journals (Sweden)

    Fulvio Rinaudo

    2009-12-01

    Full Text Available 3D imaging with Time-of-Flight (ToF cameras is a promising recent technique which allows 3D point clouds to be acquired at video frame rates. However, the distance measurements of these devices are often affected by some systematic errors which decrease the quality of the acquired data. In order to evaluate these errors, some experimental tests on a CCD/CMOS ToF camera sensor, the SwissRanger (SR-4000 camera, were performed and reported in this paper. In particular, two main aspects are treated: the calibration of the distance measurements of the SR-4000 camera, which deals with evaluation of the camera warm up time period, the distance measurement error evaluation and a study of the influence on distance measurements of the camera orientation with respect to the observed object; the second aspect concerns the photogrammetric calibration of the amplitude images delivered by the camera using a purpose-built multi-resolution field made of high contrast targets.

  19. Sensors for 3D Imaging: Metric Evaluation and Calibration of a CCD/CMOS Time-of-Flight Camera.

    Science.gov (United States)

    Chiabrando, Filiberto; Chiabrando, Roberto; Piatti, Dario; Rinaudo, Fulvio

    2009-01-01

    3D imaging with Time-of-Flight (ToF) cameras is a promising recent technique which allows 3D point clouds to be acquired at video frame rates. However, the distance measurements of these devices are often affected by some systematic errors which decrease the quality of the acquired data. In order to evaluate these errors, some experimental tests on a CCD/CMOS ToF camera sensor, the SwissRanger (SR)-4000 camera, were performed and reported in this paper. In particular, two main aspects are treated: the calibration of the distance measurements of the SR-4000 camera, which deals with evaluation of the camera warm up time period, the distance measurement error evaluation and a study of the influence on distance measurements of the camera orientation with respect to the observed object; the second aspect concerns the photogrammetric calibration of the amplitude images delivered by the camera using a purpose-built multi-resolution field made of high contrast targets.

  20. Efficiency enhancement in a backside illuminated 1.12 μm pixel CMOS image sensor via parabolic color filters.

    Science.gov (United States)

    Lee, Jong-Kwon; Kim, Ahreum; Kang, Dong-Wan; Lee, Byung Yang

    2016-07-11

    The shrinkage of pixel size down to sub-2 μm in high-resolution CMOS image sensors (CISs) results in degraded efficiency and increased crosstalk. The backside illumination technology can increase the efficiency, but the crosstalk still remains an critical issue to improve the image quality of the CIS devices. In this paper, by adopting a parabolic color filter (P-CF), we demonstrate efficiency enhancement without any noticeable change in optical crosstalk of a backside illuminated 1.12 μm pixel CIS with deep-trench-isolation structure. To identify the observed results, we have investigated the effect of radius of curvature (r) of the P-CF on the efficiency and optical crosstalk of the CIS by performing an electromagnetic analysis. As the r of P-CF becomes equal to (or half) that of the microlens, the efficiencies of the B-, G-, and R-pixels increase by a factor of 14.1% (20.3%), 9.8% (15.3%), and 15.0% (15.7%) with respect to the flat CF cases without any noticeable crosstalk change. Also, as the incident angle increases up to 30°, the angular dependence of the efficiency and crosstalk significantly decreases by utilizing the P-CF in the CIS. Meanwhile, further reduction of r severely increases the optical crosstalk due to the increased diffraction effect, which has been confirmed with the simulated electric-field intensity distribution inside the devices.

  1. Multiband CMOS sensor simplify FPA design

    Science.gov (United States)

    Wang, Weng Lyang B.; Ling, Jer

    2015-10-01

    Push broom multi-band Focal Plane Array (FPA) design needs to consider optics, image sensor, electronic, mechanic as well as thermal. Conventional FPA use two or several CCD device as an image sensor. The CCD image sensor requires several high speed, high voltage and high current clock drivers as well as analog video processors to support their operation. Signal needs to digitize using external sample / hold and digitized circuit. These support circuits are bulky, consume a lot of power, must be shielded and placed in close to the CCD to minimize the introduction of unwanted noise. The CCD also needs to consider how to dissipate power. The end result is a very complicated FPA and hard to make due to more weighs and draws more power requiring complex heat transfer mechanisms. In this paper, we integrate microelectronic technology and multi-layer soft / hard Printed Circuit Board (PCB) technology to design electronic portion. Since its simplicity and integration, the optics, mechanic, structure and thermal design will become very simple. The whole FPA assembly and dis-assembly reduced to a few days. A multi-band CMOS Sensor (dedicated as C468) was used for this design. The CMOS Sensor, allow for the incorporation of clock drivers, timing generators, signal processing and digitization onto the same Integrated Circuit (IC) as the image sensor arrays. This keeps noise to a minimum while providing high functionality at reasonable power levels. The C468 is a first Multiple System-On-Chip (MSOC) IC. This device used our proprietary wafer butting technology and MSOC technology to combine five long sensor arrays into a size of 120 mm x 23.2 mm and 155 mm x 60 mm for chip and package, respectively. The device composed of one Panchromatic (PAN) and four different Multi- Spectral (MS) sensors. Due to its integration on the electronic design, a lot of room is clear for the thermal design. The optical and mechanical design is become very straight forward. The flight model FPA

  2. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  3. Optimization of linear-logarithmic CMOS image sensor using a photogate and a cascode MOSFET for reducing pixel response variation

    Science.gov (United States)

    Bae, Myunghan; Choi, Byoung-Soo; Kim, Sang-Hwan; Lee, Jimin; Oh, Chang-Woo; Shin, Jang-Kyoo

    2017-02-01

    Recently, CMOS image sensors (CISs) have become more and more complex because they require high-performances such as wide dynamic range, low-noise, high-speed operation, high-resolution and so on. First of all, wide dynamic range (WDR) is the first requirement for high-performance CIS. Several techniques have been proposed to improve the dynamic range. Although logarithmic pixel can achieve wide dynamic range, it leads to a poor signal-to-noise ratio due to small output swings. Furthermore, the fixed pattern noise of logarithmic pixel is significantly greater compared with other CISs. In this paper, we propose an optimized linear-logarithmic pixel. Compared to a conventional 3-transistor active pixel sensor structure, the proposed linear-logarithmic pixel is using a photogate and a cascode MOSFET in addition. The photogate which is surrounding a photodiode carries out change of sensitivity in the linear response and thus increases the dynamic range. The logarithmic response is caused by a cascode MOSFET. Although the dynamic range of the pixel has been improved, output curves of each pixel were not uniform. In general, as the number of devices increases in the pixel, pixel response variation is more pronounced. Hence, we optimized the linear-logarithmic pixel structure to minimize the pixel response variation. We applied a hard reset method and an optimized cascode MOSFET to the proposed pixel for reducing pixel response variation. Unlike the conventional reset operation, a hard reset using a p-type MOSFET fixes the voltage of each pixel to the same voltage. This reduces non-uniformity of the response in the linear response. The optimized cascode MOSFET achieves less variation in the logarithmic response. We have verified that the optimized pixel shows more uniform response than the conventional pixel, by both simulation and experiment.

  4. Continuous-Time ΣΔ ADC with Implicit Variable Gain Amplifier for CMOS Image Sensor

    Directory of Open Access Journals (Sweden)

    Fang Tang

    2014-01-01

    amplifier (OTA, for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

  5. CMOS Cell Sensors for Point-of-Care Diagnostics

    Directory of Open Access Journals (Sweden)

    Haluk Kulah

    2012-07-01

    Full Text Available The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS. CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

  6. CMOS cell sensors for point-of-care diagnostics.

    Science.gov (United States)

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies.

  7. 65 nm CMOS Sensors Applied to Mathematically Exact Colorimetric Reconstruction

    CERN Document Server

    Mayr, C; Krause, A; Schlüßler, J -U; Schüffny, R

    2014-01-01

    Extracting colorimetric image information from the spectral characteristics of image sensors is a key issue in accurate image acquisition. Technically feasible filter/sensor combinations usually do not replicate colorimetric responses with sufficient accuracy to be directly applicable to color representation. A variety of transformations have been proposed in the literature to compensate for this. However, most of those rely on heuristics and/or introduce a reconstruction dependent on the composition of the incoming illumination. In this work, we present a spectral reconstruction method that is independent of illumination and is derived in a mathematically strict way. It provides a deterministic method to arrive at a least mean squared error approximation of a target spectral characteristic from arbitrary sensor response curves. Further, we present a new CMOS sensor design in a standard digital 65nm CMOS technology. Novel circuit techniques are used to achieve performance comparable with much larger-sized spe...

  8. Gamma measurement based on CMOS sensor and ARM microcontroller

    National Research Council Canada - National Science Library

    Cheng, Qian-Qian; Yuan, Yan-Zhong; Ma, Chun-Wang; Wang, Fang

    2017-01-01

    A setup based on CMOS sensor and ARM microcontroller is designed to measure the γ-rays. STM32F103 is used as the main platform to control real-time online analysis of the image collected by the OV7670 CAMERACHIP...

  9. e2v CCD and CMOS sensors and systems designed for astronomical applications

    Science.gov (United States)

    Jorden, Paul; Jerram, Paul; Jordan, Douglas; Pratlong, Jérôme; Robbins, Mark

    2016-08-01

    e2v continues to evolve its product range of sensors and systems, with CCD and CMOS sensors. We describe recent developments of high performance image sensors and precision system components. Several low noise backthinned CMOS sensors have been developed for scientific applications. CCDs have become larger whilst retaining very low noise and high quantum efficiency. Examples of sensors and sub-systems are presented including the recently completed 1.2 GigaPixel J-PAS cryogenic camera.

  10. A Multi-Resolution Mode CMOS Image Sensor with a Novel Two-Step Single-Slope ADC for Intelligent Surveillance Systems

    Directory of Open Access Journals (Sweden)

    Daehyeok Kim

    2017-06-01

    Full Text Available In this paper, we present a multi-resolution mode CMOS image sensor (CIS for intelligent surveillance system (ISS applications. A low column fixed-pattern noise (CFPN comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 μm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS is 4.4 μm × 4.4 μm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution with supply voltages of 3.3 V (analog and 1.8 V (digital and 14 frame/s of frame rates.

  11. CMOS MEMS capacitive absolute pressure sensor

    Science.gov (United States)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  12. Estimation of the particle concentration in hydraulic liquid by the in-line automatic particle counter based on the CMOS image sensor

    Science.gov (United States)

    Kornilin, Dmitriy V.; Kudryavtsev, Ilya A.; McMillan, Alison J.; Osanlou, Ardeshir; Ratcliffe, Ian

    2017-06-01

    Modern hydraulic systems should be monitored on the regular basis. One of the most effective ways to address this task is utilizing in-line automatic particle counters (APC) built inside of the system. The measurement of particle concentration in hydraulic liquid by APC is crucial because increasing numbers of particles should mean functional problems. Existing automatic particle counters have significant limitation for the precise measurement of relatively low concentration of particle in aerospace systems or they are unable to measure higher concentration in industrial ones. Both issues can be addressed by implementation of the CMOS image sensor instead of single photodiode used in the most of APC. CMOS image sensor helps to overcome the problem of the errors in volume measurement caused by inequality of particle speed inside of tube. Correction is based on the determination of the particle position and parabolic velocity distribution profile. Proposed algorithms are also suitable for reducing the errors related to the particles matches in measurement volume. The results of simulation show that the accuracy increased up to 90 per cent and the resolution improved ten times more compared to the single photodiode sensor.

  13. CMOS imager for pointing and tracking applications

    Science.gov (United States)

    Pain, Bedabrata (Inventor); Sun, Chao (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

    2006-01-01

    Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

  14. Design and characterization of a 256 x 64-pixel single-photon imager in CMOS for a MEMS-based laser scanning time-of-flight sensor.

    Science.gov (United States)

    Niclass, Cristiano; Ito, Kota; Soga, Mineki; Matsubara, Hiroyuki; Aoyagi, Isao; Kato, Satoru; Kagami, Manabu

    2012-05-21

    We introduce an optical time-of-flight image sensor taking advantage of a MEMS-based laser scanning device. Unlike previous approaches, our concept benefits from the high timing resolution and the digital signal flexibility of single-photon pixels in CMOS to allow for a nearly ideal cooperation between the image sensor and the scanning device. This technique enables a high signal-to-background light ratio to be obtained, while simultaneously relaxing the constraint on size of the MEMS mirror. These conditions are critical for devising practical and low-cost depth sensors intended to operate in uncontrolled environments, such as outdoors. A proof-of-concept prototype capable of operating in real-time was implemented. This paper focuses on the design and characterization of a 256 x 64-pixel image sensor, which also comprises an event-driven readout circuit, an array of 64 row-level high-throughput time-to-digital converters, and a 16 Gbit/s global readout circuit. Quantitative evaluation of the sensor under 2 klux of background light revealed a repeatability error of 13.5 cm throughout the distance range of 20 meters.

  15. CMOS图像传感器芯片的自动白平衡算法%Auto White Balance Algorithm for CMOS Image Sensor Chip

    Institute of Scientific and Technical Information of China (English)

    甘波; 魏廷存; 郑然

    2011-01-01

    针对CMOS图像传感器芯片中的自动白平衡图像处理电路,提出了一种便于硬件实现的增益计算方法,并在此基础上实现了一个用于CMOS图像传感器芯片的自动白平衡算法.该算法将增益计算的计算法与迭代法结合使用,并用比较器和移位寄存器来取代复杂的组合逻辑单元,在不增加硬件开销的基础上提高了计算精度与处理速度.%A method of gain calculation for auto white balance is proposed which is suitable for hardware implement in CMOS image sensors chip.Based on the method, an auto white balance algorithm used in CMOS image sensors chip is completed.Iterative method and calculation method are combined in this algorithm, and comparator and shift registers are used instead of complex combination logic cells.The computation accuracy and processing speed are improved without hardware expenses.

  16. Planar pixel sensors in commercial CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut der Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Macchiolo, Anna [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany)

    2015-07-01

    For the upgrade of the ATLAS experiment at the high luminosity LHC, an all-silicon tracker is foreseen to cope with the increased rate and radiation levels. Pixel and strip detectors will have to cover an area of up to 200m2. To produce modules in high number at reduced costs, new sensor and bonding technologies have to be investigated. Commercial CMOS technologies on high resistive substrates can provide significant advantages in this direction. They offer cost effective, large volume sensor production. In addition to this, production is done on 8'' wafers allowing wafer-to-wafer bonding to the electronics, an interconnection technology substantially cheaper than the bump bonding process used for hybrid pixel detectors at the LHC. Both active and passive n-in-p pixel sensor prototypes have been submitted in a 150 nm CMOS technology on a 2kΩ cm substrate. The passive sensor design will be used to characterize sensor properties and to investigate wafer-to-wafer bonding technologies. This first prototype is made of a matrix of 36 x 16 pixels of size compatible with the FE-I4 readout chip (i.e. 50 μm x 250 μm). Results from lab characterization of this first submission are shown together with TCAD simulations. Work towards a full size FE-I4 sensor for wafer-to-wafer bonding is discussed.

  17. Advanced microlens and color filter process technology for the high-efficiency CMOS and CCD image sensors

    Science.gov (United States)

    Fan, Yang-Tung; Peng, Chiou-Shian; Chu, Cheng-Yu

    2000-12-01

    New markets are emerging for digital electronic image device, especially in visual communications, PC camera, mobile/cell phone, security system, toys, vehicle image system and computer peripherals for document capture. To enable one-chip image system that image sensor is with a full digital interface, can make image capture devices in our daily lives. Adding a color filter to such image sensor in a pattern of mosaics pixel or wide stripes can make image more real and colorful. We can say 'color filter makes the life more colorful color filter is? Color filter means can filter image light source except the color with specific wavelength and transmittance that is same as color filter itself. Color filter process is coating and patterning green, red and blue (or cyan, magenta and yellow) mosaic resists onto matched pixel in image sensing array pixels. According to the signal caught from each pixel, we can figure out the environment image picture. Widely use of digital electronic camera and multimedia applications today makes the feature of color filter becoming bright. Although it has challenge but it is very worthy to develop the process of color filter. We provide the best service on shorter cycle time, excellent color quality, high and stable yield. The key issues of advanced color process have to be solved and implemented are planarization and micro-lens technology. Lost of key points of color filter process technology have to consider will also be described in this paper.

  18. Charge Transfer Inefficiency in Pinned Photodiode CMOS image sensors: Simple Montecarlo modeling and experimental measurement based on a pulsed storage-gate method

    Science.gov (United States)

    Pelamatti, Alice; Goiffon, Vincent; Chabane, Aziouz; Magnan, Pierre; Virmontois, Cédric; Saint-Pé, Olivier; de Boisanger, Michel Breart

    2016-11-01

    The charge transfer time represents the bottleneck in terms of temporal resolution in Pinned Photodiode (PPD) CMOS image sensors. This work focuses on the modeling and estimation of this key parameter. A simple numerical model of charge transfer in PPDs is presented. The model is based on a Montecarlo simulation and takes into account both charge diffusion in the PPD and the effect of potential obstacles along the charge transfer path. This work also presents a new experimental approach for the estimation of the charge transfer time, called pulsed Storage Gate (SG) method. This method, which allows reproduction of a "worst-case" transfer condition, is based on dedicated SG pixel structures and is particularly suitable to compare transfer efficiency performances for different pixel geometries.

  19. A pipeline ADC design for low noise CMOS image sensor and verification for digital image%用于低噪声CMOS图像传感器的流水线ADC设计及其成像验证

    Institute of Scientific and Technical Information of China (English)

    邓若汉; 徐星; 王洪彬; 余金金; 陈世军; 陈永平

    2012-01-01

    In recent years, besides concerning about the noise analyzation, the signal digitization is also a very important research spot in the research field of low noise CMOS image sensor. A 12bit, 10Msps pipeline ADC is presented which can be used as a chip-level analog-to-digital converter in a low noise CMOS image sensor, and it was taped-out in the 0.5μm CMOS standard process. Finally, by using of this ADC, an analog-output low-noise CMOS image sensor achieves analog-to-digital convert in a PCB test board, and based on an independent development image-forming system, this test board achieved a very good imaging test. The imaging result shows that this ADC can be used as a chip-level ADC of a low-noise CMOS image sensor.%在对低噪声CMOS图像传感器的研究中,除需关注其噪声外,目前数字化也是它的一个重要的研究和设计方向,设计了一种可用于低噪声CMOS图像传感器的12bit,10Msps的流水线型ADC,并基于0.5μm标准CMOS工艺进行了流片。最后,通过在PCB测试版上用本文设计的ADC实现了模拟输出的低噪声CMOS图像传感器的模数转换,并基于自主开发的成像测试系统进行了成像验证,结果表明,成像画面清晰,该ADC可作为低噪声CMOS图像传感器的芯片级模数转换器应用。

  20. Architectures for Low-noise CMOS Electronic Imaging

    Science.gov (United States)

    Kawahito, Shoji

    This chapter discusses various types of signal readout architectures for CMOS image sensors, implementing ultra-low-noise conversion of photo-generated charge packets into digital output values. It is based on a detailed analysis of the different noise sources in a CMOS imager, the noise responses of column noise cancelling circuits using correlated double sampling (CDS) and correlated multiple sampling (CMS) techniques and a noiseless signal readout technique using a precise digitizer. Finally, a practical example for the design of a CMOS image sensor with single-photon resolution is presented, and the technological requirements for meeting the condition for room-temperature readout noise of significantly less than 1 electron are discussed.

  1. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  2. Image Sensors Enhance Camera Technologies

    Science.gov (United States)

    2010-01-01

    In the 1990s, a Jet Propulsion Laboratory team led by Eric Fossum researched ways of improving complementary metal-oxide semiconductor (CMOS) image sensors in order to miniaturize cameras on spacecraft while maintaining scientific image quality. Fossum s team founded a company to commercialize the resulting CMOS active pixel sensor. Now called the Aptina Imaging Corporation, based in San Jose, California, the company has shipped over 1 billion sensors for use in applications such as digital cameras, camera phones, Web cameras, and automotive cameras. Today, one of every three cell phone cameras on the planet feature Aptina s sensor technology.

  3. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    CMOS pixel sensors are often opposed to hybrid pixel sensors due to their very different sensitive layer. In standard CMOS imaging processes, a thin (about 20 μm) low resistivity epitaxial layer acts as the sensitive volume and charge collection is mostly driven by thermal agitation. In contrast, the so-called hybrid pixel technology exploits a thick (typically 300 μm) silicon sensor with high resistivity allowing for the depletion of this volume, hence charges drift toward collecting electrodes. But this difference is fading away with the recent availability of some CMOS imaging processes based on a relatively thick (about 50 μm) high resistivity epitaxial layer which allows for full depletion. This evolution extents the range of applications for CMOS pixel sensors where their known assets, high sensitivity and granularity combined with embedded signal treatment, could potentially foster breakthrough in detection performances for specific scientific instruments. One such domain is the Xray detection for soft energies, typically below 10 keV, where the thin sensitive layer was previously severely impeding CMOS sensor usage. Another application becoming realistic for CMOS sensors, is the detection in environment with a high fluence of non-ionizing radiation, such as hadron colliders. However, when considering highly demanding applications, it is still to be proven that micro-circuits required to uniformly deplete the sensor at the pixel level, do not mitigate the sensitivity and efficiency required. Prototype sensors in two different technologies with resistivity higher than 1 kΩ, sensitive layer between 40 and 50 μm and featuring pixel pitch in the range 25 to 50 μm, have been designed and fabricated. Various biasing architectures were adopted to reach full depletion with only a few volts. Laboratory investigations with three types of sources (X-rays, β-rays and infrared light) demonstrated the validity of the approach with respect to depletion, keeping a

  4. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  5. Performance Analysis of Visible Light Communication Using CMOS Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hop Do

    2016-02-01

    Full Text Available This paper elucidates the fundamentals of visible light communication systems that use the rolling shutter mechanism of CMOS sensors. All related information involving different subjects, such as photometry, camera operation, photography and image processing, are studied in tandem to explain the system. Then, the system performance is analyzed with respect to signal quality and data rate. To this end, a measure of signal quality, the signal to interference plus noise ratio (SINR, is formulated. Finally, a simulation is conducted to verify the analysis.

  6. TDI型CMOS图像传感器时序控制设计与实现%Designand Implementation of Timing Control for TDI CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    桑美贞; 徐江涛; 聂凯明; 姚素英

    2011-01-01

    The timing control circuit of 1 024×128 time-delay-integration (TDI) CMOS image sensor was designed. The synchronization of charge transfer between pixels and signal accumulation was implemented, based on along-track-rolling exposure mode and through increasing the frequency of exposure. The timing control circuits of pixel array, accumulator and column level ADC were designed and verified. I2C bus controlled variation of the related parameters. The design costs 761 standard cells, and the layout size is 125μm× 160μm. Total dynamic power consumption is 40. 55μW, and leakage power consumption is 10. 43μW. Timing is correct and meets the requirements. The combination of timing control circuit and analog circuit implements a TDI CMOS image sensor.%设计了1 024× 128时间延迟积分型(TDI) CMOS图像传感器的时序控制电路.基于沿扫描方向的行滚筒式曝光方式、通过增加曝光频率实现了像素间电荷转移的同时性和信号累加的同步性.完成了像素阵列、像素外电荷累加和列级ADC的时序控制电路,相关参数通过I2C总线控制.设计共耗费761个标准逻辑单元,版图大小为125μm×160μm,总的动态功耗40.55 μW,泄漏功耗为10.43μW,时序正确并满足要求.时序控制电路与模拟电路的结合实现了TDI型CMOS图像传感器.

  7. Radiation imaging with a new scintillator and a CMOS camera

    Science.gov (United States)

    Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

    2014-07-01

    A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 ± 0.4 μm and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

  8. Co-integration of a smart CMOS image sensor and a spatial light modulator for real-time optical phase modulation

    Science.gov (United States)

    Laforest, Timothé; Verdant, Arnaud; Dupret, Antoine; Gigan, Sylvain; Ramaz, François; Tessier, Gilles

    2014-03-01

    We present a CMOS light detector-actuator array, in which every pixel combines a spatial light modulator and a photodiode. It will be used in medical imaging based on acousto-optical coherence tomography with a digital holographic detection scheme. Our architecture is able to measure an interference pattern between a scattered beam transmitted through a scattering media and a reference beam. The array of 16 μm pixels pitch has a frame rate of several kfps, which makes this sensor compliant with the correlation time of light in biological tissues. In-pixel analog processing of the interference pattern allows controlling the polarization of a stacked light modulator and thus, to control the phase of the reflected beam. This reflected beam can then be focused on a region of interest, i.e. for therapy. The stacking of a photosensitive element with a spatial light modulator on the same chip brings a significant robustness over the state of the art such as perfect optical matching and reduced delay in controlling light.

  9. CMOS monolithic pixel sensors research and development at LBNL

    Indian Academy of Sciences (India)

    D Contarato; J-M Bussat; P Denes; L Griender; T Kim; T Stezeberger; H Weiman; M Battaglia; B Hooberman; L Tompkins

    2007-12-01

    This paper summarizes the recent progress in the design and characterization of CMOS pixel sensors at LBNL. Results of lab tests, beam tests and radiation hardness tests carried out at LBNL on a test structure with pixels of various sizes are reported. The first results of the characterization of back-thinned CMOS pixel sensors are also reported, and future plans and activities are discussed.

  10. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  11. Improvement to the signaling interface for CMOS pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Shi, Zhan, E-mail: sz1134@163.com [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Tang, Zhenan, E-mail: tangza@dlut.edu.cn [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Feng, Chong [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China); Dalian Minzu University, No.18 Liaohe West Road, 116600 Dalian (China); Cai, Hong [Dalian University of Technology, No.2 Linggong Road, 116024 Dalian (China)

    2016-10-01

    The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 µm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.

  12. Improvement to the signaling interface for CMOS pixel sensors

    Science.gov (United States)

    Shi, Zhan; Tang, Zhenan; Feng, Chong; Cai, Hong

    2016-10-01

    The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18 μm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2 Gb/s with a power consumption of 19.1 mW.

  13. 用于医用X射线图像传感器的14位流水线ADC设计%A 14-bit pipeline ADC design for medical X-ray CMOS image sensor

    Institute of Scientific and Technical Information of China (English)

    朱天成; 叶旭明; 徐伯夏

    2011-01-01

    CMOS(complementary metal oxide semiconductor)图像传感器取代传统医用X射线透视仪器对于医疗设备的便携化、数字化具有重大意义.由于医疗应用的特殊要求,对于CMOS图像传感器要求具有12位以上分辨率的输出,因此本文设计了一个具有14位分辨率的流水线ADC(analog digital converter)来满足X射线CMOS图像传感器系统的要求.由于X射线CMOS图像传感器的面积很大,因此将像素阵列分割成若干块同时并行读出.每一块将用到一个14位的流水线ADC.这种并行结构将大大降低对于ADC速度的要求.根据系统要求,本文设计的ADC的速度为3 MS/s.通过采用类似并行流水线ADC的结构,将ADC设计的速度要求降低一倍,缓解由于高精度设计带来的设计压力.仿真结果表明本设计可以达到14位的设计精度.%Objective Using CMOS (complementary metal oxide semiconductor) image sensor to replace traditional X-ray apparatus is a great significance for miniaturization and digitalization of medical equipments. For the special requirements of medical application, the CMOS image sensor output resolution should be more than 12 bits, and in this study we use a 14-bit pipeline ADC (analog digital converter) to meet the system requirements. As the area of X-ray CMOS image sensor is very large, we divide the CMOS image sensor into many partitions, and read data in parallel. Each partition adopts a 14-bit pipeline ADC to readout. The parallel structure greatly reduces the requirement for speed. According to the system requirements, a speed of 3 MS/s is adopted in this work. A pseudo-parallel pipeline ADC has been introduced into this work, which allows to reduce the speed requirement by a half, releasing the design pressure from high precision requirement. The simulation results demonstrate that the design can achieve a 14-bit resolution.

  14. Lab-on-CMOS integration of microfluidics and electrochemical sensors.

    Science.gov (United States)

    Huang, Yue; Mason, Andrew J

    2013-10-07

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

  15. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  16. Analog Encoding Voltage—A Key to Ultra-Wide Dynamic Range and Low Power CMOS Image Sensor

    Directory of Open Access Journals (Sweden)

    Orly Yadid-Pecht

    2013-03-01

    Full Text Available Usually Wide Dynamic Range (WDR sensors that autonomously adjust their integration time to fit intra-scene illumination levels use a separate digital memory unit. This memory contains the data needed for the dynamic range. Motivated by the demands for low power and chip area reduction, we propose a different implementation of the aforementioned WDR algorithm by replacing the external digital memory with an analog in-pixel memory. This memory holds the effective integration time represented by analog encoding voltage (AEV. In addition, we present a “ranging” scheme of configuring the pixel integration time in which the effective integration time is configured at the first half of the frame. This enables a substantial simplification of the pixel control during the rest of the frame and thus allows for a significantly more remarkable DR extension. Furthermore, we present the implementation of “ranging” and AEV concepts on two different designs, which are targeted to reach five and eight decades of DR, respectively. We describe in detail the operation of both systems and provide the post-layout simulation results for the second solution. The simulations show that the second design reaches DR up to 170 dBs. We also provide a comparative analysis in terms of the number of operations per pixel required by our solution and by other widespread WDR algorithms. Based on the calculated results, we conclude that the proposed two designs, using “ranging” and AEV concepts, are attractive, since they obtain a wide dynamic range at high operation speed and low power consumption.

  17. X-ray characterization of CMOS imaging detector with high resolution for fluoroscopic imaging application

    Science.gov (United States)

    Cha, Bo Kyung; Kim, Cho Rong; Jeon, Seongchae; Kim, Ryun Kyung; Seo, Chang-Woo; Yang, Keedong; Heo, Duchang; Lee, Tae-Bum; Shin, Min-Seok; Kim, Jong-Boo; Kwon, Oh-Kyung

    2013-12-01

    This paper introduces complementary metal-oxide semiconductor (CMOS) active pixel sensor (APS)-based X-ray imaging detectors with high spatial resolution for medical imaging application. In this study, our proposed X-ray CMOS imaging sensor has been fabricated by using a 0.35 μm 1 Poly 4 Metal CMOS process. The pixel size is 100 μm×100 μm and the pixel array format is 24×96 pixels, which provide a field-of-view (FOV) of 9.6 mm×2.4 mm. The 14.3-bit extend counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. Both thallium-doped CsI (CsI:Tl) and Gd2O2S:Tb scintillator screens were used as converters for incident X-rays to visible light photons. The optical property and X-ray imaging characterization such as X-ray to light response as a function of incident X-ray exposure dose, spatial resolution and X-ray images of objects were measured under different X-ray energy conditions. The measured results suggest that our developed CMOS-based X-ray imaging detector has the potential for fluoroscopic imaging and cone-beam computed tomography (CBCT) imaging applications.

  18. Non-equal spacing CMOS sensor impact on response between even and odd pixels

    Science.gov (United States)

    Liu, Cynthia; Chen, Nai-Yu

    2010-10-01

    With the self-developing CMOS imaging sensors in the instrument Focal Plane Assembly (FPA), there is flexibility in the trade-off for optimal specifications of CMOS sensor for systematic study. The criteria considered for the optimization are MTF and SNR, the CMOS imaging sensor considered is with TDI (time delay integration) feature. Among the specifications, fill factor is a key item. It affect not only the window effect in FPA MTF (static), but also the smearing effect in dynamic MTF, especially in satellite along track direction. Considering different fill factors, mirror-type and non-mirror-type pixel layout were studied for estimating the system MTF, another concern from image user point of view is mirror type pixel layout may cause different response between even and odd pixels. This work is to present the analysis results based on the construction of the non-equal spacing signal via Whittaker -Shannon interpolation formula. Further to present the analysis results about fill factor and stage number of TDI CMOS sensor. The result can function as a practice of FPA design specification.

  19. CMOS low data rate imaging method based on compressed sensing

    Science.gov (United States)

    Xiao, Long-long; Liu, Kun; Han, Da-peng

    2012-07-01

    Complementary metal-oxide semiconductor (CMOS) technology enables the integration of image sensing and image compression processing, making improvements on overall system performance possible. We present a CMOS low data rate imaging approach by implementing compressed sensing (CS). On the basis of the CS framework, the image sensor projects the image onto a separable two-dimensional (2D) basis set and measures the corresponding coefficients obtained. First, the electrical current output from the pixels in a column are combined, with weights specified by voltage, in accordance with Kirchhoff's law. The second computation is performed in an analog vector-matrix multiplier (VMM). Each element of the VMM considers the total value of each column as the input and multiplies it by a unique coefficient. Both weights and coefficients are reprogrammable through analog floating-gate (FG) transistors. The image can be recovered from a percentage of these measurements using an optimization algorithm. The percentage, which can be altered flexibly by programming on the hardware circuit, determines the image compression ratio. These novel designs facilitate image compression during the image-capture phase before storage, and have the potential to reduce power consumption. Experimental results demonstrate that the proposed method achieves a large image compression ratio and ensures imaging quality.

  20. Passive radiation detection using optically active CMOS sensors

    Science.gov (United States)

    Dosiek, Luke; Schalk, Patrick D.

    2013-05-01

    Recently, there have been a number of small-scale and hobbyist successes in employing commodity CMOS-based camera sensors for radiation detection. For example, several smartphone applications initially developed for use in areas near the Fukushima nuclear disaster are capable of detecting radiation using a cell phone camera, provided opaque tape is placed over the lens. In all current useful implementations, it is required that the sensor not be exposed to visible light. We seek to build a system that does not have this restriction. While building such a system would require sophisticated signal processing, it would nevertheless provide great benefits. In addition to fulfilling their primary function of image capture, cameras would also be able to detect unknown radiation sources even when the danger is considered to be low or non-existent. By experimentally profiling the image artifacts generated by gamma ray and β particle impacts, algorithms are developed to identify the unique features of radiation exposure, while discarding optical interaction and thermal noise effects. Preliminary results focus on achieving this goal in a laboratory setting, without regard to integration time or computational complexity. However, future work will seek to address these additional issues.

  1. Piezoresistive Sensors Development Using Monolithic CMOS MEMS Technology

    Directory of Open Access Journals (Sweden)

    A. Chaehoi

    2011-04-01

    Full Text Available This paper presents the development of a monolithic CMOS-MEMS platform under the iDesign and SemeMEMS projects with the aim of jointly providing an open access “one-stop-shop” design and prototyping facility for integrated CMOS-MEMS. This work addresses the implementation of a 3-axis accelerometer and a pressure sensor using Semefab’s in-house 2-poly 1-metal CMOS process on a 380/4/15 μm SOI wafer; the membrane and the proof mass being micromachined using double-sided Deep Reactive Ion Etching (DRIE. This monolithic approach promises, in high volume production and using low complexity processes, a dramatic cost reduction over hybrid sensors. Furthermore, the embedded signal conditioning and the low-noise level in polysilicon gauges enables high performance to be achieved by implementing dedicated on-chip amplification and filtering circuitry.

  2. Study of CMOS integrated signal processing circuit in capacitive sensors

    Institute of Scientific and Technical Information of China (English)

    CAO Yi-jiang; YU Xiang; WANG Lei

    2007-01-01

    A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output voltage's frequency. The whole circuit is designed with 1.5 μm P-well CMOS process and simulated by PSpice software.Output frequency varies from 261.05 kHz to 47.93 kHz if capacitance varies in the range of 1PF~15PF. And the variation of frequency can be easily detected using counter or SCU.

  3. 12Bit Low Power Single Slope ADC Design for CMOS Image Sensor%用于CMOS图像传感器的12位低功耗单斜坡模数转换器设计

    Institute of Scientific and Technical Information of China (English)

    唐枋; 唐建国

    2013-01-01

    A high quantization resolution and low power consumption single slope ADC scheme, for CMOS image sensor applications is proposed. The proposed scheme is composed of the variable gain amplifier,preamplifier and the dynamic latch comparator. Compared to the prior art structure, the proposed circuit can achieve a reasonable noise performance, consume less power and occupy smaller chip area. This proposed ADC is implemented as a column-parallel ADC array inside a fabricated CMOS image sensor chip.The experimental results verify the conception proposed in this paper.%本文提出了一种应用于CMOS图像传感器中的高精度低功耗单斜坡模数转换器(single slope analog-to-digital converter)设计方案.该ADC方案由可变增益放大器、前置预放大器和动态锁存比较器组成.相比现有的设计方案,本文提出的电路在不牺牲噪声性能的前提下,具有更低的功耗和更小的芯片面积.通过集成列并行的单斜坡模数转换器在最新设计的高精度高速CMOS图像传感器设计中,实验结果证明了设计的有效性.

  4. Damage analysis of CMOS electro-optical imaging system by a continuous wave laser

    Science.gov (United States)

    Yoon, Sunghee; Jhang, Kyung-Young; Shin, Wan-Soon

    2016-08-01

    EOIS (electro-optical imaging system) is vulnerable to laser beam because EOIS focuses the incident laser beam onto the image sensor via lens module. Accordingly, the laser-induced damage of EOIS is necessary to be identified for the counter-measure against the laser attack. In this study, the damage of CMOS EOIS and image sensor induced by CW (continuous wave) NIR (near infrared) laser was experimentally investigated. When the laser was emitted to CMOS EOIS, a temporary damage was occurred first such as flickering or dazzling and then a permanent damage was followed as the increase of laser irradiance and irradiation time. If the EIOS is composed of the optical equipment made of heatresistant material, laser beam can penetrate the lens module of EOIS without melting the lens and lens guide. Thus, it is necessary to investigate the damage of CMOS image sensor by the CW laser and we performed experimentally investigation of damage on the CMOS image sensor similar with case of CMOS EOIS. And we analyzed the experiment results by using OM (optical microscopy) and check the image quality through tomography. As the increase of laser irradiance and irradiation time, the permanent damage such as discoloration and breakdown were sequentially appeared.

  5. High-performance VGA-resolution digital color CMOS imager

    Science.gov (United States)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  6. CMOS: Efficient Clustered Data Monitoring in Sensor Networks

    Directory of Open Access Journals (Sweden)

    Jun-Ki Min

    2013-01-01

    Full Text Available Tiny and smart sensors enable applications that access a network of hundreds or thousands of sensors. Thus, recently, many researchers have paid attention to wireless sensor networks (WSNs. The limitation of energy is critical since most sensors are battery-powered and it is very difficult to replace batteries in cases that sensor networks are utilized outdoors. Data transmission between sensor nodes needs more energy than computation in a sensor node. In order to reduce the energy consumption of sensors, we present an approximate data gathering technique, called CMOS, based on the Kalman filter. The goal of CMOS is to efficiently obtain the sensor readings within a certain error bound. In our approach, spatially close sensors are grouped as a cluster. Since a cluster header generates approximate readings of member nodes, a user query can be answered efficiently using the cluster headers. In addition, we suggest an energy efficient clustering method to distribute the energy consumption of cluster headers. Our simulation results with synthetic data demonstrate the efficiency and accuracy of our proposed technique.

  7. NV-CMOS HD camera for day/night imaging

    Science.gov (United States)

    Vogelsong, T.; Tower, J.; Sudol, Thomas; Senko, T.; Chodelka, D.

    2014-06-01

    SRI International (SRI) has developed a new multi-purpose day/night video camera with low-light imaging performance comparable to an image intensifier, while offering the size, weight, ruggedness, and cost advantages enabled by the use of SRI's NV-CMOS HD digital image sensor chip. The digital video output is ideal for image enhancement, sharing with others through networking, video capture for data analysis, or fusion with thermal cameras. The camera provides Camera Link output with HD/WUXGA resolution of 1920 x 1200 pixels operating at 60 Hz. Windowing to smaller sizes enables operation at higher frame rates. High sensitivity is achieved through use of backside illumination, providing high Quantum Efficiency (QE) across the visible and near infrared (NIR) bands (peak QE biofluorescence/microscopy imaging, day/night security and surveillance, and other high-end applications which require HD video imaging with high sensitivity and wide dynamic range. The camera comes with an array of lens mounts including C-mount and F-mount. The latest test data from the NV-CMOS HD camera will be presented.

  8. Design considerations for a new, high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS).

    Science.gov (United States)

    Loughran, Brendan; Swetadri Vasan, S N; Singh, Vivek; Ionita, Ciprian N; Jain, Amit; Bednarek, Daniel R; Titus, Albert; Rudin, Stephen

    2013-03-06

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  9. Design considerations for a new high resolution Micro-Angiographic Fluoroscope based on a CMOS sensor (MAF-CMOS)

    Science.gov (United States)

    Loughran, Brendan; Swetadri Vasan, S. N.; Singh, Vivek; Ionita, Ciprian N.; Jain, Amit; Bednarek, Daniel R.; Titus, Albert H.; Rudin, Stephen

    2013-03-01

    The detectors that are used for endovascular image-guided interventions (EIGI), particularly for neurovascular interventions, do not provide clinicians with adequate visualization to ensure the best possible treatment outcomes. Developing an improved x-ray imaging detector requires the determination of estimated clinical x-ray entrance exposures to the detector. The range of exposures to the detector in clinical studies was found for the three modes of operation: fluoroscopic mode, high frame-rate digital angiographic mode (HD fluoroscopic mode), and DSA mode. Using these estimated detector exposure ranges and available CMOS detector technical specifications, design requirements were developed to pursue a quantum limited, high resolution, dynamic x-ray detector based on a CMOS sensor with 50 μm pixel size. For the proposed MAF-CMOS, the estimated charge collected within the full exposure range was found to be within the estimated full well capacity of the pixels. Expected instrumentation noise for the proposed detector was estimated to be 50-1,300 electrons. Adding a gain stage such as a light image intensifier would minimize the effect of the estimated instrumentation noise on total image noise but may not be necessary to ensure quantum limited detector operation at low exposure levels. A recursive temporal filter may decrease the effective total noise by 2 to 3 times, allowing for the improved signal to noise ratios at the lowest estimated exposures despite consequent loss in temporal resolution. This work can serve as a guide for further development of dynamic x-ray imaging prototypes or improvements for existing dynamic x-ray imaging systems.

  10. From vertex detectors to inner trackers with CMOS pixel sensors

    Science.gov (United States)

    Besson, A.; Pérez, A. Pérez; Spiriti, E.; Baudot, J.; Claus, G.; Goffe, M.; Winter, M.

    2017-02-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R & D results for the conception of a CPS well adapted for the ALICE-ITS.

  11. From vertex detectors to inner trackers with CMOS pixel sensors

    CERN Document Server

    Besson, A; Spiriti, E.; Baudot, J.; Claus, G.; Goffe, M.; Winter, M.

    2016-01-01

    The use of CMOS Pixel Sensors (CPS) for high resolution and low material vertex detectors has been validated with the 2014 and 2015 physics runs of the STAR-PXL detector at RHIC/BNL. This opens the door to the use of CPS for inner tracking devices, with 10-100 times larger sensitive area, which require therefore a sensor design privileging power saving, response uniformity and robustness. The 350 nm CMOS technology used for the STAR-PXL sensors was considered as too poorly suited to upcoming applications like the upgraded ALICE Inner Tracking System (ITS), which requires sensors with one order of magnitude improvement on readout speed and improved radiation tolerance. This triggered the exploration of a deeper sub-micron CMOS technology, Tower-Jazz 180 nm, for the design of a CPS well adapted for the new ALICE-ITS running conditions. This paper reports the R&D results for the conception of a CPS well adapted for the ALICE-ITS.

  12. An integrating CMOS APS for X-ray imaging with an in-pixel preamplifier

    Science.gov (United States)

    Abdalla, M. A.; Fröjdh, C.; Petersson, C. S.

    2001-06-01

    We present in this paper an integrating CMOS Active Pixel Sensor (APS) circuit coated with scintillator type sensors for intra-oral dental X-ray imaging systems. The photosensing element in the pixel is formed by the p-diffusion on the n-well diode. The advantage of this photosensor is its very low direct absorption of X-rays compared to the other available photosensing elements in the CMOS pixel. The pixel features an integrating capacitor in the feedback loop of a preamplifier of a finite gain in order to increase the optical sensitivity. To verify the effectiveness of this in-pixel preamplification, a prototype 32×80 element CMOS active pixel array was implemented in a 0.8 μm CMOS double poly, n-well process with a pixel pitch of 50 μm. Measured results confirmed the improved optical sensitivity performance of the APS. Various measurements on device performance are presented.

  13. Vertical Isolation for Photodiodes in CMOS Imagers

    Science.gov (United States)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  14. CMOS-based Integrated Wavefront Sensor

    NARCIS (Netherlands)

    De Lima Monteiro, D.W.

    2002-01-01

    This thesis addresses the design, implementation and performance of an integrated Hartmann-Shack wavefront sensor suitable for real-time operation and compatible with a standard technology. A wavefront sensor can be used for the detection of distortions in the profile of a light beam or of an optica

  15. SOI CMOS Imager with Suppression of Cross-Talk

    Science.gov (United States)

    Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

    2009-01-01

    A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

  16. Integrated CMOS sensor technologies for the CLIC tracker

    CERN Document Server

    AUTHOR|(SzGeCERN)754303

    2017-01-01

    Integrated technologies are attractive candidates for an all silicon tracker at the proposed future multi-TeV linear e+e- collider CLIC. In this context CMOS circuitry on a high resistivity epitaxial layer has been studied using the ALICE Investigator test-chip. Test-beam campaigns have been performed to study the Investigator performance and a Technology Computer Aided Design based simulation chain has been developed to further explore the sensor technology.

  17. CMOS APS detector characterization for quantitative X-ray imaging

    Energy Technology Data Exchange (ETDEWEB)

    Endrizzi, Marco, E-mail: m.endrizzi@ucl.ac.uk [Dipartimento di Fisica, Università di Siena, Via Roma 56, 53100 Siena (Italy); Istituto Nazionale di Fisica Nucleare INFN, sezione di Pisa, 56127 Pisa (Italy); Oliva, Piernicola [Dipartimento di Chimica e Farmacia, Università di Sassari, via Piandanna 4, 07100 Sassari (Italy); Istituto Nazionale di Fisica Nucleare INFN, Sezione di Cagliari, 09042 Cagliari (Italy); Golosio, Bruno [Sezione di Matematica, Fisica e Ingegneria dell' Informazione, Università di Sassari, via Piandanna 4, 07100 Sassari (Italy); Istituto Nazionale di Fisica Nucleare INFN, Sezione di Cagliari, 09042 Cagliari (Italy); Delogu, Pasquale [Dipartimento di Fisica “E. Fermi”, Università di Pisa, Largo B. Pontecorvo 3, 56127 Pisa (Italy); Istituto Nazionale di Fisica Nucleare INFN, sezione di Pisa, 56127 Pisa (Italy)

    2013-03-01

    An X-ray Imaging detector based on CMOS Active Pixel Sensor and structured scintillator is characterized for quantitative X-ray imaging in the energy range 11–30 keV. Linearity, dark noise, spatial resolution and flat-field correction are the characteristics of the detector subject of investigation. The detector response, in terms of mean Analog-to-Digital Unit and noise, is modeled as a function of the energy and intensity of the X-rays. The model is directly tested using monochromatic X-ray beams and it is also indirectly validated by means of polychromatic X-ray-tube spectra. Such a characterization is suitable for quantitative X-ray imaging and the model can be used in simulation studies that take into account the actual performance of the detector.

  18. Measurement and analysis of image sensors

    Science.gov (United States)

    Vitek, Stanislav

    2005-06-01

    For astronomical applications is necessary to have high precision in sensing and processing the image data. In this time are used the large CCD sensors from the various reasons. For the replacement of CCD sensors with CMOS sensing devices is important to know transfer characteristics of used CCD sensors. In the special applications like the robotic telescopes (fully automatic, without human interactions) seems to be good using of specially designed smart sensors, which have integrated more functions and have more features than CCDs.

  19. CMOS vertical hall magnetic sensors on flexible substrate

    OpenAIRE

    2016-01-01

    This paper presents the realization of different\\ud Vertical Hall Sensors (VHSs) implemented using a 0.18-μm\\ud CMOS technology and mounted on flexible substrates. Various\\ud geometries of VHS have been studied to obtain the optimum\\ud sensor device dimension and shape. COMSOL multiphysics\\ud simulation results are validated with respect to the electrical\\ud behaviour of an 8-resistor Verilog-A model implemented in\\ud Cadence environment. Simulation and measurement results are in\\ud good agre...

  20. A CMOS active pixel sensor for retinal stimulation

    Science.gov (United States)

    Prydderch, Mark L.; French, Marcus J.; Mathieson, Keith; Adams, Christopher; Gunning, Deborah; Laudanski, Jonathan; Morrison, James D.; Moodie, Alan R.; Sinclair, James

    2006-02-01

    Degenerative photoreceptor diseases, such as age-related macular degeneration and retinitis pigmentosa, are the most common causes of blindness in the western world. A potential cure is to use a microelectronic retinal prosthesis to provide electrical stimulation to the remaining healthy retinal cells. We describe a prototype CMOS Active Pixel Sensor capable of detecting a visual scene and translating it into a train of electrical pulses for stimulation of the retina. The sensor consists of a 10 x 10 array of 100 micron square pixels fabricated on a 0.35 micron CMOS process. Light incident upon each pixel is converted into output current pulse trains with a frequency related to the light intensity. These outputs are connected to a biocompatible microelectrode array for contact to the retinal cells. The flexible design allows experimentation with signal amplitudes and frequencies in order to determine the most appropriate stimulus for the retina. Neural processing in the retina can be studied by using the sensor in conjunction with a Field Programmable Gate Array (FPGA) programmed to behave as a neural network. The sensor has been integrated into a test system designed for studying retinal response. We present the most recent results obtained from this sensor.

  1. A High-Speed CMOS Image Sensor for Real-Time Vision Chip%面向实时视觉芯片的高速CMOS图像传感器

    Institute of Scientific and Technical Information of China (English)

    付秋瑜; 林清宇; 张万成; 吴南健

    2011-01-01

    A high-speed CMOS image sensor for real-time vision chip is proposed. The high-speed CMOS image sensor consists of CMOS photodiode array, correlated double sampling (CDS) array, programmable gain amplifier (PGA) array, area-efficient single-slope analog-to-digital converter (ADC) array and controller circuit. It can perform the image capturing and row-parallel signal processing. It outputs digital signal or digital image at a frame rate of over 1000 frame/s. It can reduce the fixed pattern noise (FPN) and amplify (or shrink) the output signals of the photodiode array to maintain the amplitude of the signal in row-parallel fashion. It can continuously perform 8-bit ADC conversion in row-parallel. A 128 pixel × 128 pixel image sensor with 128 rows of CDS, PGA and single-slope ADC is fabricated by using 0.18 μm 1P6M CMOS process. The chip size is 2. 2 mm× 2. 6 mm. The measured results demonstrate that the designed chip can perform high-speed real-time optical signal capturing and processing. It can be applied to the real-time vision chip system.%提出了一种面向实时视觉芯片的高速CMOS图像传感器.该高速图像传感器主要包括CMOS像素单元阵列、相关双采样(CDS)阵列、可编程增益放大(PGA)阵列、单次比较模数转换(ADC)阵列和控制模块.该传感器集成了光信号采集和行并行信号处理等功能,以大于1000 frame/s的速度输出数字信号或数字图像,同时实现了行并行方式的固定模式噪声消除、编程控制输出信号动态范围调节、连续8位行并行模数信号转换的功能.采用0.18 μm 1P6M CMOS工艺实现了高速图像传感器,芯片面积为2.2 mm×2.6 mm,测试结果表明,该芯片可以完成实时高速光信号采集及处理,适用于集成高速实时视觉芯片系统.

  2. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  3. A CMOS Imager with Focal Plane Compression using Predictive Coding

    Science.gov (United States)

    Leon-Salas, Walter D.; Balkir, Sina; Sayood, Khalid; Schemm, Nathan; Hoffman, Michael W.

    2007-01-01

    This paper presents a CMOS image sensor with focal-plane compression. The design has a column-level architecture and it is based on predictive coding techniques for image decorrelation. The prediction operations are performed in the analog domain to avoid quantization noise and to decrease the area complexity of the circuit, The prediction residuals are quantized and encoded by a joint quantizer/coder circuit. To save area resources, the joint quantizerlcoder circuit exploits common circuitry between a single-slope analog-to-digital converter (ADC) and a Golomb-Rice entropy coder. This combination of ADC and encoder allows the integration of the entropy coder at the column level. A prototype chip was fabricated in a 0.35 pm CMOS process. The output of the chip is a compressed bit stream. The test chip occupies a silicon area of 2.60 mm x 5.96 mm which includes an 80 X 44 APS array. Tests of the fabricated chip demonstrate the validity of the design.

  4. Sparsely-Bonded CMOS Hybrid Imager

    Science.gov (United States)

    Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Sun, Chao (Inventor); Jones, Todd J. (Inventor); Dickie, Matthew R. (Inventor); Nikzad, Shouleh (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Newton, Kenneth W. (Inventor); Pain, Bedabrata (Inventor)

    2015-01-01

    A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

  5. Lower-Dark-Current, Higher-Blue-Response CMOS Imagers

    Science.gov (United States)

    Pain, Bedabrata; Cunningham, Thomas; Hancock, Bruce

    2008-01-01

    Several improved designs for complementary metal oxide/semiconductor (CMOS) integrated-circuit image detectors have been developed, primarily to reduce dark currents (leakage currents) and secondarily to increase responses to blue light and increase signal-handling capacities, relative to those of prior CMOS imagers. The main conclusion that can be drawn from a study of the causes of dark currents in prior CMOS imagers is that dark currents could be reduced by relocating p/n junctions away from Si/SiO2 interfaces. In addition to reflecting this conclusion, the improved designs include several other features to counteract dark-current mechanisms and enhance performance.

  6. Multi-Aperture CMOS Sun Sensor for Microsatellite Attitude Determination

    Directory of Open Access Journals (Sweden)

    Michele Grassi

    2009-06-01

    Full Text Available This paper describes the high precision digital sun sensor under development at the University of Naples. The sensor determines the sun line orientation in the sensor frame from the measurement of the sun position on the focal plane. It exploits CMOS technology and an original optical head design with multiple apertures. This allows simultaneous multiple acquisitions of the sun as spots on the focal plane. The sensor can be operated either with a fixed or a variable number of sun spots, depending on the required field of view and sun-line measurement precision. Multiple acquisitions are averaged by using techniques which minimize the computational load to extract the sun line orientation with high precision. Accuracy and computational efficiency are also improved thanks to an original design of the calibration function relying on neural networks. Extensive test campaigns are carried out using a laboratory test facility reproducing sun spectrum, apparent size and distance, and variable illumination directions. Test results validate the sensor concept, confirming the precision improvement achievable with multiple apertures, and sensor operation with a variable number of sun spots. Specifically, the sensor provides accuracy and precision in the order of 1 arcmin and 1 arcsec, respectively.

  7. CMOS Pixel Spectroscopic Circuits for Cd(ZnTe Gamma Ray Imagers

    Directory of Open Access Journals (Sweden)

    Hatzistratis D.

    2016-01-01

    Full Text Available A family of 2-D pixel CMOS ASICs have been developed to be used as readout electronics of gamma ray imaging instruments based on hybrid pixel sensor arrays. One element of the sensor array consists of a pixilated single crystal of CdTe or CdZnTe semiconductor bump bonded to the CMOS electronic circuit. The first member of the family can process single photon signals which deliver up to 4fCb charge, while the two other can process signals up to 36fCb. A unique readout mode and the simultaneous extraction of energy and time tagging information of the converted photons differentiate the members of this family from other existing CMOS readout circuits.

  8. A mathematical model of the inline CMOS matrix sensor for investigation of particles in hydraulic liquids

    Science.gov (United States)

    Kornilin, DV; Kudryavtsev, IA

    2016-10-01

    One of the most effective ways to diagnose the state of hydraulic system is an investigation of the particles in their liquids. The sizes of such particles range from 2 to 200 gm and their concentration and shape reveal important information about the current state of equipment and the necessity of maintenance. In-line automatic particle counters (APC), which are built into hydraulic system, are widely used for determination of particle size and concentration. These counters are based on a single photodiode and a light emitting diode (LED); however, samples of liquid are needed for analysis using microscope or industrial video camera in order to get information about particle shapes. The act of obtaining the sample leads to contamination by other particles from the air or from the sample tube, meaning that the results are usually corrupted. Using the CMOS or CCD matrix sensor without any lens for inline APC is the solution proposed by authors. In this case the matrix sensors are put into the liquid channel of the hydraulic system and illuminated by LED. This system could be stable in arduous conditions like high pressure and the vibration of the hydraulic system; however, the image or signal from that matrix sensor needs to be processed differently in comparison with the signal from microscope or industrial video camera because of relatively short distance between LED and sensor. This paper introduces mathematical model of a sensor with CMOS and LED, which can be built into hydraulic system. It is also provided a computational algorithm and results, which can be useful for calculation of particle sizes and shapes using the signal from the CMOS matrix sensor.

  9. NEMS/CMOS sensor for monitoring deposition rates in stencil lithography

    OpenAIRE

    Sansa, Marc; Arcamone, Julien; Verd, Jaume; Uranga, Arantxa; Abadal, Gabriel; Núria, Barniol; Savu, Veronica; van den Boogaart, Marc; Brugger, Jürgen; Perez-Murano, Francesc

    2009-01-01

    A nanoelectromechanical mass sensor is used to characterize material deposition rates in stencil lithography. The material flux through micron size apertures is mapped with high spatial (below 1 μm) and deposition rate (below 10 pm/s) resolutions by displacing the stencil apertures over the sensor. The sensor is based on a resonating metallic beam (with submicron size width and thickness) monolithically integrated with a CMOS circuit, resulting in a CMOS/NEMS self-oscillator. The sensor is us...

  10. Wide Dynamic Range CMOS Potentiostat for Amperometric Chemical Sensor

    Directory of Open Access Journals (Sweden)

    Wei-Song Wang

    2010-03-01

    Full Text Available Presented is a single-ended potentiostat topology with a new interface connection between sensor electrodes and potentiostat circuit to avoid deviation of cell voltage and linearly convert the cell current into voltage signal. Additionally, due to the increased harmonic distortion quantity when detecting low-level sensor current, the performance of potentiostat linearity which causes the detectable current and dynamic range to be limited is relatively decreased. Thus, to alleviate these irregularities, a fully-differential potentiostat is designed with a wide output voltage swing compared to single-ended potentiostat. Two proposed potentiostats were implemented using TSMC 0.18-μm CMOS process for biomedical application. Measurement results show that the fully differential potentiostat performs relatively better in terms of linearity when measuring current from 500 ºpA to 10 uA. Besides, the dynamic range value can reach a value of 86 dB.

  11. A rad-hard CMOS active pixel sensor for electron microscopy

    Energy Technology Data Exchange (ETDEWEB)

    Battaglia, Marco [Department of Physics, University of California at Berkeley, CA 94720 (United States); Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)], E-mail: MBattaglia@lbl.gov; Contarato, Devis; Denes, Peter; Doering, Dionisio [Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Giubilato, Piero [Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); INFN, Sezione di Padova, I-35131 (Italy); Dipartimento di Fisica, Universita degli Studi, Padova I-35131 (Italy); Kim, Tae Sung [Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Mattiazzo, Serena [INFN, Sezione di Padova, I-35131 (Italy); Dipartimento di Fisica, Universita degli Studi, Padova I-35131 (Italy); Radmilovic, Velimir [Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Zalusky, Sarah [Department of Physics, University of California at Berkeley, CA 94720 (United States); Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)

    2009-01-11

    Monolithic CMOS pixel sensors offer unprecedented opportunities for fast nano-imaging through direct electron detection in transmission electron microscopy. We present the design and a full characterisation of a CMOS pixel test structure able to withstand doses in excess of 1 Mrad. Data collected with electron beams at various energies of interest in electron microscopy are compared to predictions of simulation and to 1.5 GeV electron data to disentagle the effect of multiple scattering. The point spread function measured with 300 keV electrons is (8.1{+-}1.6){mu}m for 10{mu}m pixel and (10.9{+-}2.3){mu}m for 20{mu}m pixels, respectively, which agrees well with the values of 8.4 and 10.5{mu}m predicted by our simulation.

  12. A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

    Directory of Open Access Journals (Sweden)

    Fangming Deng

    2015-03-01

    Full Text Available This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  13. A CMOS pressure sensor tag chip for passive wireless applications.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

    2015-03-23

    This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

  14. Design and image-quality performance of high resolution CMOS-based X-ray imaging detectors for digital mammography

    Science.gov (United States)

    Cha, B. K.; Kim, J. Y.; Kim, Y. J.; Yun, S.; Cho, G.; Kim, H. K.; Seo, C.-W.; Jeon, S.; Huh, Y.

    2012-04-01

    In digital X-ray imaging systems, X-ray imaging detectors based on scintillating screens with electronic devices such as charge-coupled devices (CCDs), thin-film transistors (TFT), complementary metal oxide semiconductor (CMOS) flat panel imagers have been introduced for general radiography, dental, mammography and non-destructive testing (NDT) applications. Recently, a large-area CMOS active-pixel sensor (APS) in combination with scintillation films has been widely used in a variety of digital X-ray imaging applications. We employed a scintillator-based CMOS APS image sensor for high-resolution mammography. In this work, both powder-type Gd2O2S:Tb and a columnar structured CsI:Tl scintillation screens with various thicknesses were fabricated and used as materials to convert X-ray into visible light. These scintillating screens were directly coupled to a CMOS flat panel imager with a 25 × 50 mm2 active area and a 48 μm pixel pitch for high spatial resolution acquisition. We used a W/Al mammographic X-ray source with a 30 kVp energy condition. The imaging characterization of the X-ray detector was measured and analyzed in terms of linearity in incident X-ray dose, modulation transfer function (MTF), noise-power spectrum (NPS) and detective quantum efficiency (DQE).

  15. CAOS-CMOS camera.

    Science.gov (United States)

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

  16. Compressive Sensing Image Sensors-Hardware Implementation

    Directory of Open Access Journals (Sweden)

    Shahram Shirani

    2013-04-01

    Full Text Available The compressive sensing (CS paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal–oxide–semiconductor technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed.

  17. Photon imaging using post-processed CMOS chips

    NARCIS (Netherlands)

    Melai, Joost

    2010-01-01

    This thesis presents our work on an integrated photon detector made by post-processing of CMOS sensor arrays. The aim of the post-processing is to combine all elements of the detector into a single monolithic device. These elements include a photocathode to convert photon radiation into electronic s

  18. A time-resolved image sensor for tubeless streak cameras

    Science.gov (United States)

    Yasutomi, Keita; Han, SangMan; Seo, Min-Woong; Takasawa, Taishi; Kagawa, Keiichiro; Kawahito, Shoji

    2014-03-01

    This paper presents a time-resolved CMOS image sensor with draining-only modulation (DOM) pixels for tube-less streak cameras. Although the conventional streak camera has high time resolution, the device requires high voltage and bulky system due to the structure with a vacuum tube. The proposed time-resolved imager with a simple optics realize a streak camera without any vacuum tubes. The proposed image sensor has DOM pixels, a delay-based pulse generator, and a readout circuitry. The delay-based pulse generator in combination with an in-pixel logic allows us to create and to provide a short gating clock to the pixel array. A prototype time-resolved CMOS image sensor with the proposed pixel is designed and implemented using 0.11um CMOS image sensor technology. The image array has 30(Vertical) x 128(Memory length) pixels with the pixel pitch of 22.4um. .

  19. Radiation hardness studies on CMOS monolithic pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Battaglia, Marco [Department of Physics, University of California at Berkeley, CA 94720 (United States); Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Bisello, Dario [Dipartimento di Fisica, Universita di Padova and INFN, Sezione di Padova, I-35131 Padova (Italy); Contarato, Devis, E-mail: DContarato@lbl.go [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Denes, Peter; Doering, Dionisio [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Giubilato, Piero [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Dipartimento di Fisica, Universita di Padova and INFN, Sezione di Padova, I-35131 Padova (Italy); Sung Kim, Tae [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Mattiazzo, Serena [Dipartimento di Fisica, Universita di Padova and INFN, Sezione di Padova, I-35131 Padova (Italy); Radmilovic, Velimir [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Zalusky, Sarah [Department of Physics, University of California at Berkeley, CA 94720 (United States); Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States)

    2010-12-11

    This paper presents irradiation studies performed on a CMOS monolithic pixel sensor prototype implementing different optimizations of the pixel cell aimed at a superior radiation tolerance. Irradiations with 200 keV electrons up to a total dose of 1.1 Mrad have been performed in view of the utilization of such a design in Transmission Electron Microscopy (TEM) applications. Comparative irradiations were performed with 29 MeV protons up to a 2 Mrad total dose and with 1-14 MeV neutrons up to fluences in excess of 10{sup 13} n{sub eq} cm{sup -2}. Experimental results show an improved performance of pixels designed with Enclosed Layout Transistor (ELT) rules and an optimized layout of the charge collecting diodes.

  20. Micro-digital sun sensor: an imaging sensor for space applications

    NARCIS (Netherlands)

    Xie, N.; Theuwissen, A.J.P.; Büttgen, B.; Hakkesteegt, H.C.; Jasen, H.; Leijtens, J.A.P.

    2010-01-01

    Micro-Digital Sun Sensor is an attitude sensor which senses relative position of micro-satellites to the sun in space. It is composed of a solar cell power supply, a RF communication block and an imaging chip which is called APS+. The APS+ integrates a CMOS Active Pixel Sensor (APS) of 512×512 pixel

  1. Edge-TCT measurements on irradiated HV CMOS sensors

    CERN Document Server

    Weisser, Constantin

    2014-01-01

    Passive $100 \\times 100 \\,\\mu$m test diodes in an unirradiated and an irradiated HV2FEI4v3 HV-CMOS silicon sensor were analysed using the edge TCT technique. To integrate the sensor into the setup a PCB was designed to extract the signals, a cooling mechanism was constructed and the system housed in a shielding box. The observed signal had fast and slow contributions, that were interpreted as drift and diffusion. The former peaked in a region, that was interpreted as the depletion region, while the latter peaked further in the bulk material. Raising the bias voltage increased the depth of the former region, while pushing the latter region further into the bulk. The irradiated sample lost signal strength mainly in its slow part compared to the unirradiated sample, while its quick signal remained largely unaffected. As only the signal interpreted as drift is fast enough to be useful in LHC operation the investigated sensors could be considered radiation hard for this purpose. This gives further promise to ...

  2. Feasibility Study of Analogue and Digital Temperature Sensors in Nanoscale CMOS Technologies

    NARCIS (Netherlands)

    Geljon, M.; Sill, F.; De Lima Monteiro, D.W.

    2009-01-01

    The downscaling of CMOS technology gives rise to a myriad of nanoscale effects. At the same time, power density and thus heat generation increases. The aim of this paper is to evaluate the feasibility of both analogue and digital temperature sensors in nanoscale CMOS using the Berkeley Predictive Te

  3. A novel CMOS transducer for giant magnetoresistance sensors

    Science.gov (United States)

    Luong, Van Su; Lu, Chih-Cheng; Yang, Jing-Wen; Jeng, Jen-Tzong

    2017-02-01

    In this work, an ASIC (application specific integrated circuits) transducer circuit for field modulated giant magnetoresistance (GMR) sensors was designed and fabricated using a 0.18-μ m CMOS process. The transducer circuits consist of a frequency divider, a digital phase shifter, an instrument amplifier, and an analog mixer. These comprise a mix of analog and digital circuit techniques. The compact chip size of 1.5 mm × 1.5 mm for both analog and digital parts was achieved using the TSMC18 1P6M (1-polysilicon 6-metal) process design kit, and the characteristics of the system were simulated using an HSpice simulator. The output of the transducer circuit is the result of the first harmonic detection, which resolves the modulated field using a phase sensitive detection (PSD) technique and is proportional to the measured magnetic field. When the dual-bridge GMR sensor is driven by the transducer circuit with a current of 10 mA at 10 kHz, the observed sensitivity of the field sensor is 10.2 mV/V/Oe and the nonlinearity error was 3% in the linear range of ±1 Oe. The performance of the system was also verified by rotating the sensor system horizontally in earth's magnetic field and recording the sinusoidal output with respect to the azimuth angle, which exhibits an error of less than ±0.04 Oe. These results prove that the ASIC transducer is suitable for driving the AC field modulated GMR sensors applied to geomagnetic measurement.

  4. 基于压缩感知的低功耗高效率CMOS图像传感器设计%Low Power High Efficiency CMOS Image Sensor Design Based on Compressed Sensing

    Institute of Scientific and Technical Information of China (English)

    赵士彬; 姚素英; 徐江涛

    2011-01-01

    A low power high efficiency CMOS image sensor(CIS) based on compressed sensing is proposed. In this compressed sensing CIS, frame storage, frame difference detection and frame compression are respectively integrated in the pixel, column and chip level circuits and the fusion of image compression and image sensing is achieved. This fusion can improve the efficiency in power consumption, transmission bandwidth and output data. The whole design has been fabricated by using Global Foundry 0.18 μm 1P6M mixed-signal process. The testing results indicate that the proposed pixel structure can not only realize the smaller pixel size and better fill factor but also keep the better tradeoff compared with other counterparts. The self-adaptive quantization scheme can also make selective processing for different pixel readout and achieve low-power real-time image compression. It proves that the proposed CIS archi tecture is suitable to the application to low power high efficiency imaging system such as wireless video sensor network (WVSN).%提出一种基于压缩感知的低功耗高效率CMOS图像传感器(CIS)设计.在这种压缩感知CIS中,帧存储、帧差求解和帧压缩等过程分别集成于像素级、列级和芯片级电路中,实现了图像传感过程和图像压缩过程的融合.这种融合提高了CIS在功耗、传输带宽和输出数据等方面的效率.所提出的CIS设计已采用Global Foundries 0.18 μm 1P6M混合信号工艺进行了投片验证.验证结果显示,其像素结构可以实现较小的像素面积和较好的填充因子,相比于其他相关设计更具折衷性.而自适应读出量化方法则可以根据不同的数据类型实现选择化处理,实现低功耗实时图像压缩.结果表明,所提出的CIS结构适用于诸如无线视频传感网络等低功耗高效率成像系统.

  5. Meteor Film Recording with Digital Film Cameras with large CMOS Sensors

    Science.gov (United States)

    Slansky, P. C.

    2016-12-01

    In this article the author combines his professional know-how about cameras for film and television production with his amateur astronomy activities. Professional digital film cameras with high sensitivity are still quite rare in astronomy. One reason for this may be their costs of up to 20 000 and more (camera body only). In the interim, however,consumer photo cameras with film mode and very high sensitivity have come to the market for about 2 000 EUR. In addition, ultra-high sensitive professional film cameras, that are very interesting for meteor observation, have been introduced to the market. The particular benefits of digital film cameras with large CMOS sensors, including photo cameras with film recording function, for meteor recording are presented by three examples: a 2014 Camelopardalid, shot with a Canon EOS C 300, an exploding 2014 Aurigid, shot with a Sony alpha7S, and the 2016 Perseids, shot with a Canon ME20F-SH. All three cameras use large CMOS sensors; "large" meaning Super-35 mm, the classic 35 mm film format (24x13.5 mm, similar to APS-C size), or full format (36x24 mm), the classic 135 photo camera format. Comparisons are made to the widely used cameras with small CCD sensors, such as Mintron or Watec; "small" meaning 12" (6.4x4.8 mm) or less. Additionally, special photographic image processing of meteor film recordings is discussed.

  6. Development of radiation hard CMOS active pixel sensors for HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Pernegger, Heinz, E-mail: heinz.pernegger@cern.ch

    2016-07-11

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  7. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    AUTHOR|(CDS)2070112; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  8. A CMOS imager using focal-plane pinhole effect for confocal multibeam scanning microscopy

    Science.gov (United States)

    Seo, Min-Woong; Wang, An; Li, Zhuo; Yasutomi, Keita; Kagawa, Keiichiro; Kawahito, Shoji

    2012-03-01

    A CMOS imager for confocal multi-beam scanning microscopy, where the pixel itself works as a pinhole, is proposed. This CMOS imager is suitable for building compact, low-power, and confocal microscopes because the complex Nipkow disk with a precisely aligned pinhole array can be omitted. The CMOS imager is composed of an array of sub-imagers, and can detect multiple beams at the same time. To achieve a focal-plane pinhole effect, only one pixel in each subimager, which is at the conjugate position of a light spot, accumulates the photocurrent, and the other pixels are unread. This operation is achieved by 2-dimensional vertical and horizontal shift registers. The proposed CMOS imager for the confocal multi-beam scanning microscope system was fabricated in 0.18-μm standard CMOS technology with a pinned photodiode option. The total area of the chip is 5.0mm × 5.0mm. The number of effective pixels is 256(Horizontal) × 256(Vertical). The pixel array consists of 32(H) × 32(V) sub-imagers each of which has 8(H) × 8(V) pixels. The pixel is an ordinary 4-transistor active pixel sensor using a pinned photodiode and the pixel size is 7.5μm × 7.5μm with a fillfactor of 45%. The basic operations such as normal image acquisition and selective pixel readout were experimentally confirmed. The sensitivity and the pixel conversion gain were 25.9 ke-/lx•sec and 70 μV/e- respectively.

  9. Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

    CERN Document Server

    Benoit, M; de Mendizabal, J. Bilbao; Chen, H; Chen, K; Di Bello, F.A; Ferrere, D; Golling, T; Gonzalez-Sevilla, S; Iacobucci, G; Lanni, F; Liu, H; Meng, L; Miucci, A; Muenstermann, D; Nessi, M; Peric, I; Rimoldi, M; Ristic, B; Pinto, M. Vicente Barrero; Vossebeld, J; Weber, M; Wu, W; Xu, L

    2016-01-01

    Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. This paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. Results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

  10. CMOS与CCD图像传感器的比较研究和发展趋势%Comparative research and future tendency between CMOS and CCD image sensor

    Institute of Scientific and Technical Information of China (English)

    王旭东; 叶玉堂

    2010-01-01

    对目前的两类图像传感器CCD和CMOs做了系统的分析和研究.对CMOs与CCD的结构特点,相关的性能参数进行了深入比较研究.针对CMOs图像传感器的低灵敏度、高噪声,暗电流,低凑充度和成像质量差等技术问题,提出了DRSCAN噪声消除技术,CMOs C3D技术,片上模拟处理技术和彩色插值算法等解决途径.通过进一步对图像传感器的应用发展情况和发展趋势的分析与研究,得出:在未来发展中,由于CMOs图像传感器已经克服了已有的技术瓶颐,在视频监控,航空探测设备,医疗设备,眼膜识别,可视通信等诸多领城的应用前景将会优于CCD图像传感器.

  11. A Multi-Modality CMOS Sensor Array for Cell-Based Assay and Drug Screening.

    Science.gov (United States)

    Chi, Taiyun; Park, Jong Seok; Butts, Jessica C; Hookway, Tracy A; Su, Amy; Zhu, Chengjie; Styczynski, Mark P; McDevitt, Todd C; Wang, Hua

    2015-12-01

    In this paper, we present a fully integrated multi-modality CMOS cellular sensor array with four sensing modalities to characterize different cell physiological responses, including extracellular voltage recording, cellular impedance mapping, optical detection with shadow imaging and bioluminescence sensing, and thermal monitoring. The sensor array consists of nine parallel pixel groups and nine corresponding signal conditioning blocks. Each pixel group comprises one temperature sensor and 16 tri-modality sensor pixels, while each tri-modality sensor pixel can be independently configured for extracellular voltage recording, cellular impedance measurement (voltage excitation/current sensing), and optical detection. This sensor array supports multi-modality cellular sensing at the pixel level, which enables holistic cell characterization and joint-modality physiological monitoring on the same cellular sample with a pixel resolution of 80 μm × 100 μm. Comprehensive biological experiments with different living cell samples demonstrate the functionality and benefit of the proposed multi-modality sensing in cell-based assay and drug screening.

  12. Improved Signal Chains for Readout of CMOS Imagers

    Science.gov (United States)

    Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

    2009-01-01

    An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

  13. On the response of a europium doped phosphor-coated CMOS digital imaging detector

    Energy Technology Data Exchange (ETDEWEB)

    Seferis, I.E. [Department of Medical Physics, Faculty of Medicine, University of Patras, 26500 Patras (Greece); Michail, C.M.; Valais, I.G.; Fountos, G.P.; Kalyvas, N.I. [Department of Medical Instruments Technology, Technological Educational Institute (TEI) of Athens, Agios Spyridonos, 12210 Athens (Greece); Stromatia, F. [Department of Radiology and Nuclear Medicine, “IASO” General Hospital, Mesogion 264, 15562 Holargos (Greece); Oikonomou, G. [Department of Medical Radiological Technology, Faculty of Health and Caring Professions, Technological Educational Institute (TEI) of Athens, Agios Spyridonos, 12210 Athens (Greece); Kandarakis, I.S., E-mail: kandarakis@teiath.gr [Department of Medical Instruments Technology, Technological Educational Institute (TEI) of Athens, Agios Spyridonos, 12210 Athens (Greece); Panayiotakis, G.S. [Department of Medical Physics, Faculty of Medicine, University of Patras, 26500 Patras (Greece)

    2013-11-21

    Purpose: The purpose of the present study was to assess the information content of a high resolution active pixel CMOS imaging sensor coupled to Gd{sub 2}O{sub 2}S:Eu phosphor screens in terms of single index image quality metrics such as the information capacity (IC) and the noise equivalent passband (Ne). Methods: The CMOS sensor was coupled to two Gd{sub 2}O{sub 2}S:Eu scintillator screens with coating thicknesses of 33.3 and 65.1 mg/cm{sup 2}. IC and Ne were obtained by means of experimentally determined parameters such as the modulation transfer function (MTF), the detective quantum efficiency (DQE) and the noise equivalent quanta (NEQ). Measurements were performed using the standard IEC-RQA5 radiation beam quality (70 kVp) and a W/Rh beam quality (28 kVp). Results: It was found that the detector response function was linear for the exposure ranges under investigation. At 70 kVp, under the RQA 5 conditions IC values were found to range between 1730 and 1851 bits/mm{sup 2} and Ne values were found between 2.28 and 2.52 mm{sup −1}. At 28 kVp the corresponding IC values were found to range between 2535 and 2747 bits/mm{sup 2}, while the Ne values were found between 5.91 and 7.09 mm{sup −1}. Conclusion: IC and Ne of the red emitting phosphor/CMOS sensor combination were found with high values suggesting an acceptable imaging performance in terms of information content and sharpness, for X-ray digital imaging. -- Highlights: •Gd{sub 2}O{sub 2}S:Eu/CMOS combination has comparable image quality parameters to Gd{sub 2}O{sub 2}S:Tb/CMOS. •Information capacity was found with high values suggesting an acceptable imaging performance. •Red emitting phosphors coupled to silicon based optical sensors could be used in developing efficient imaging detectors.

  14. High-resolution three-dimensional imaging of a depleted CMOS sensor using an edge Transient Current Technique based on the Two Photon Absorption process (TPA-eTCT)

    CERN Document Server

    García, Marcos Fernández; Echeverría, Richard Jaramillo; Moll, Michael; Santos, Raúl Montero; Moya, David; Pinto, Rogelio Palomo; Vila, Iván

    2016-01-01

    For the first time, the deep n-well (DNW) depletion space of a High Voltage CMOS sensor has been characterized using a Transient Current Technique based on the simultaneous absorption of two photons. This novel approach has allowed to resolve the DNW implant boundaries and therefore to accurately determine the real depleted volume and the effective doping concentration of the substrate. The unprecedented spatial resolution of this new method comes from the fact that measurable free carrier generation in two photon mode only occurs in a micrometric scale voxel around the focus of the beam. Real three-dimensional spatial resolution is achieved by scanning the beam focus within the sample.

  15. Charge collection and non-ionizing radiation tolerance of CMOS pixel sensors using a 0.18 μm CMOS process

    Science.gov (United States)

    Zhang, Ying; Zhu, Hongbo; Zhang, Liang; Fu, Min

    2016-09-01

    The proposed Circular Electron Positron Collider (CEPC) will be primarily aimed for precision measurements of the discovered Higgs boson. Its innermost vertex detector, which will play a critical role in heavy-flavor tagging, must be constructed with fine-pitched silicon pixel sensors with low power consumption and fast readout. CMOS pixel sensor (CPS), as one of the most promising candidate technologies, has already demonstrated its excellent performance in several high energy physics experiments. Therefore it has been considered for R&D for the CEPC vertex detector. In this paper, we present the preliminary studies to improve the collected signal charge over the equivalent input capacitance ratio (Q / C), which will be crucial to reduce the analog power consumption. We have performed detailed 3D device simulation and evaluated potential impacts from diode geometry, epitaxial layer properties and non-ionizing radiation damage. We have proposed a new approach to improve the treatment of the boundary conditions in simulation. Along with the TCAD simulation, we have designed the exploratory prototype utilizing the TowerJazz 0.18 μm CMOS imaging sensor process and we will verify the simulation results with future measurements.

  16. Design and Fabrication of High-Efficiency CMOS/CCD Imagers

    Science.gov (United States)

    Pain, Bedabrata

    2007-01-01

    An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the

  17. Radiation Tolerance of CMOS Monolithic Active Pixel Sensors with Self-Biased Pixels

    CERN Document Server

    Deveaux, M; Besson, A; Claus, G; Colledani, C; Dorokhov, M; Dritsa, C; Dulinski, W; Fröhlich, I; Goffe, M; Grandjean, D; Heini, S; Himmi, A; Hu, C; Jaaskelainen, K; Müntz, C; Shabetai, A; Stroth, J; Szelezniak, M; Valin, I; Winter, M

    2009-01-01

    CMOS Monolithic Active Pixel Sensors (MAPS) are proposed as a technology for various vertex detectors in nuclear and particle physics. We discuss the mechanisms of ionizing radiation damage on MAPS hosting the the dead time free, so-called self bias pixel. Moreover, we discuss radiation hardened sensor designs which allow operating detectors after exposing them to irradiation doses above 1 Mrad

  18. A custom CMOS imager for multi-beam laser scanning microscopy and an improvement of scanning speed

    Science.gov (United States)

    Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

    2013-02-01

    Multi-beam laser scanning confocal microscopy with a 256 × 256-pixel custom CMOS imager performing focal-plane pinhole effect, in which any rotating disk is not required, is demonstrated. A specimen is illuminated by 32 × 32 diffraction limited light spots whose wavelength and pitch are 532nm and 8.4 μm, respectively. The spot array is generated by a microlens array, which is scanned by two-dimensional piezo actuator according to the scanning of the image sensor. The frame rate of the prototype is 0.17 Hz, which is limited by the actuator. The confocal effect has been confirmed by comparing the axial resolution in the confocal imaging mode with that of the normal imaging mode. The axial resolution in the confocal mode measured by the full width at half maximum (FWHM) for a planar mirror was 8.9 μm, which is showed that the confocality has been achieved with the proposed CMOS image sensor. The focal-plane pinhole effect in the confocal microscopy with the proposed CMOS imager has been demonstrated at low frame rate. An improvement of the scanning speed and a CMOS imager with photo-sensitivity modulation pixels suitable for high-speed scanning are also discussed.

  19. Design of high speed camera based on CMOS technology

    Science.gov (United States)

    Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

    2007-12-01

    The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

  20. sCMOS detector for imaging VNIR spectrometry

    Science.gov (United States)

    Eckardt, Andreas; Reulke, Ralf; Schwarzer, Horst; Venus, Holger; Neumann, Christian

    2013-09-01

    The facility Optical Information Systems (OS) at the Robotics and Mechatronics Center of the German Aerospace Center (DLR) has more than 30 years of experience with high-resolution imaging technology. This paper shows the scientific results of the institute of leading edge instruments and focal plane designs for EnMAP VIS/NIR spectrograph. EnMAP (Environmental Mapping and Analysis Program) is one of the selected proposals for the national German Space Program. The EnMAP project includes the technological design of the hyper spectral space borne instrument and the algorithms development of the classification. The EnMAP project is a joint response of German Earth observation research institutions, value-added resellers and the German space industry like Kayser-Threde GmbH (KT) and others to the increasing demand on information about the status of our environment. The Geo Forschungs Zentrum (GFZ) Potsdam is the Principal Investigator of EnMAP. DLR OS and KT were driving the technology of new detectors and the FPA design for this project, new manufacturing accuracy and on-chip processing capability in order to keep pace with the ambitious scientific and user requirements. In combination with the engineering research, the current generations of space borne sensor systems are focusing on VIS/NIR high spectral resolution to meet the requirements on earth and planetary observation systems. The combination of large swath and high spectral resolution with intelligent synchronization control, fast-readout ADC chains and new focal-plane concepts open the door to new remote-sensing and smart deep space instruments. The paper gives an overview over the detector verification program at DLR on FPA level, new control possibilities for sCMOS detectors in global shutter mode and key parameters like PRNU, DSNU, MTF, SNR, Linearity, Spectral Response, Quantum Efficiency, Flatness and Radiation Tolerance will be discussed in detail.

  1. Beam imaging sensor

    Energy Technology Data Exchange (ETDEWEB)

    McAninch, Michael D.; Root, Jeffrey J.

    2016-07-05

    The present invention relates generally to the field of sensors for beam imaging and, in particular, to a new and useful beam imaging sensor for use in determining, for example, the power density distribution of a beam including, but not limited to, an electron beam or an ion beam. In one embodiment, the beam imaging sensor of the present invention comprises, among other items, a circumferential slit that is either circular, elliptical or polygonal in nature.

  2. Linear dynamic range enhancement in a CMOS imager

    Science.gov (United States)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

  3. Noise sources and noise suppression in CMOS imagers

    Science.gov (United States)

    Pain, Bedabrata; Cunningham, Thomas J.; Hancock, Bruce R.

    2004-01-01

    Mechanisms for noise coupling in CMOS imagers are complex, since unlike a CCD, a CMOS imager has to be considered as a full digital-system-on-a-chip, with a highly sensitive front-end. In this paper, we analyze the noise sources in a photodiode CMOS imager, and model their propagation through the signal chain to determine the nature and magnitude of noise coupling. We present methods for reduction of noise, and present measured data to show their viability. For temporal read noise reduction, we present pixel signal chain design techniques to achieve near 2 electrons read noise. We model the front-end reset noise both for conventional photodiode and CTIA type of pixels. For the suppression of reset noise, we present a column feedback-reset method to reduce reset noise below 6 electrons. For spatial noise reduction, we present the design of column signal chain that suppresses both spatial noise and power supply coupling noise. We conclude by identifying problems in low-noise design caused by dark current spatial distribution.

  4. Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

    CERN Document Server

    Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

    2012-01-01

    CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

  5. A photovoltaic-driven and energy-autonomous CMOS implantable sensor.

    Science.gov (United States)

    Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

    2012-08-01

    An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest μW's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-μW integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes.

  6. A CMOS-Based Tactile Sensor for Continuous Blood Pressure Monitoring

    CERN Document Server

    Kirstein, K -U; Salo, T; Hagleitner, C; Vancura, T; Hierlemann, A

    2011-01-01

    A monolithic integrated tactile sensor array is presented, which is used to perform non-invasive blood pressure monitoring of a patient. The advantage of this device compared to a hand cuff based approach is the capability of recording continuous blood pressure data. The capacitive, membrane-based sensor device is fabricated in an industrial CMOS-technology combined with post-CMOS micromachining. The capacitance change is detected by a S?-modulator. The modulator is operated at a sampling rate of 128kS/s and achieves a resolution of 12bit with an external decimation filter and an OSR of 128.

  7. Direct detection in Transmission Electron Microscopy with a 5{mu}m pitch CMOS pixel sensor

    Energy Technology Data Exchange (ETDEWEB)

    Contarato, Devis, E-mail: DContarato@lbl.go [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States); Denes, Peter; Doering, Dionisio; Joseph, John; Krieger, Brad [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720 (United States)

    2011-04-11

    This paper presents the characterization of a CMOS monolithic pixel sensor prototype optimized for direct detection in Transmission Electron Microscopy (TEM). The sensor was manufactured in a deep-submicron commercial CMOS process and features pixels of 5{mu}m pitch. Different pixel architectures have been implemented in the test chip, and the best performing architecture has been selected from a series of tests performed with 300 keV electrons. Irradiation tests to high electron doses have also been performed in order to estimate device lifetime.

  8. Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

    OpenAIRE

    2016-01-01

    We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency) CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to redu...

  9. Design of optoelectronic imaging system with high resolution and large field-of-view based on dual CMOS

    Science.gov (United States)

    Cheng, Hanglin; Hao, Qun; Hu, Yao; Cao, Jie; Wang, Shaopu; Li, Lin

    2016-10-01

    With the advantages of high resolution, large field of view and compacted size, optoelectronic imaging sensors are widely used in many fields, such as robot's navigation, industrial measurement and remote sensing. Many researchers pay more attention to improve the comprehensive performances of imaging sensors, including large field of view (FOV), high resolution, compact size and high imaging efficiency, etc. One challenge is the tradeoff between high resolution and large field of view simultaneously considering compacted size. In this paper, we propose an optoelectronic imaging system combining the lenses of short focal length and long focal length based on dual CMOS to simulate the characters of human eyes which observe object within large FOV in high resolution. We design and optimize the two lens, the lens of short focal length is used to search object in a wide field and the long one is responsible for high resolution imaging of the target area. Based on a micro-CMOS imaging sensor with low voltage differential transmission technology-MIPI (Mobile Industry Processor Interface), we design the corresponding circuits to realize collecting optical information with high speed. The advantage of the interface is to help decreasing power consumption, improving transmission efficiency and achieving compacted size of imaging sensor. Meanwhile, we carried out simulations and experiments to testify the optoelectronic imaging system. The results show that the proposed method is helpful to improve the comprehensive performances of optoelectronic imaging sensors.

  10. Simulation and Analysis of Photo-charge Transfer Characteristics of Bipolar Junction Photogate Transistor for CMOS Imagers

    Institute of Scientific and Technical Information of China (English)

    2003-01-01

    The principle of the two carriers contributing to carry the pixel signal charges is firstly presented,and then the bipolar junction photogate transistor(BJPT)with high performance is proposed for the CMOS image sensor.The numerical analytical model of the photo-charge transfer for the bipolar junction photogate is established in detail. Some numerical simulations are obtained under 0.6μm CMOS process,which show that its readout rate increases exponentially with the increase of the photo-charge at applied voltage.

  11. Nanophotonic Image Sensors.

    Science.gov (United States)

    Chen, Qin; Hu, Xin; Wen, Long; Yu, Yan; Cumming, David R S

    2016-09-01

    The increasing miniaturization and resolution of image sensors bring challenges to conventional optical elements such as spectral filters and polarizers, the properties of which are determined mainly by the materials used, including dye polymers. Recent developments in spectral filtering and optical manipulating techniques based on nanophotonics have opened up the possibility of an alternative method to control light spectrally and spatially. By integrating these technologies into image sensors, it will become possible to achieve high compactness, improved process compatibility, robust stability and tunable functionality. In this Review, recent representative achievements on nanophotonic image sensors are presented and analyzed including image sensors with nanophotonic color filters and polarizers, metamaterial-based THz image sensors, filter-free nanowire image sensors and nanostructured-based multispectral image sensors. This novel combination of cutting edge photonics research and well-developed commercial products may not only lead to an important application of nanophotonics but also offer great potential for next generation image sensors beyond Moore's Law expectations.

  12. Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique

    Directory of Open Access Journals (Sweden)

    Chien-Fu Fong

    2015-10-01

    Full Text Available A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS-microelectromechanical system (MEMS technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm.

  13. An investigation into the use of CMOS active pixel technology in image-guided radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Osmond, J P F; Holland, A D [School of Engineering and Design, Brunel University, Uxbridge, UB8 3PH (United Kingdom); Harris, E J; Ott, R J; Evans, P M [Joint Department of Physics, Institute of Cancer Research and Royal Marsden NHS Trust, Downs Road, Sutton, Surrey, SM2 5PT (United Kingdom); Clark, A T [Science and Technology Facilities Council, Rutherford Appleton Laboratory, Harwell Science and Innovation Campus, Didcot, OX11 0QX (United Kingdom)], E-mail: john.osmond@brunel.ac.uk

    2008-06-21

    The increased intelligence, read-out speed, radiation hardness and potential large size of CMOS active pixel sensors (APS) gives them a potential advantage over systems currently used for verification of complex treatments such as IMRT and the tracking of moving tumours. The aim of this work is to investigate the feasibility of using an APS-based system to image the megavoltage treatment beam produced by a linear accelerator (Linac), and to demonstrate the logic which may ultimately be incorporated into future sensor and FPGA design to evaluate treatment and track motion. A CMOS APS was developed by the MI{sup 3} consortium and incorporated into a megavoltage imaging system using the standard lens and mirror configuration employed in camera-based EPIDs. The ability to resolve anatomical structure was evaluated using an Alderson RANDO head phantom, resolution evaluated using a quality control (QC3) phantom and contrast using an in-house developed phantom. A complex intensity-modulated radiotherapy (IMRT) treatment was imaged and two algorithms were used to determine the field-area and delivered dose, and the position of multi-leaf collimator (MLC) leaves off-line. Results were compared with prediction from the prescription and found to agree within a single image frame time for dose delivery and 0.02-0.03 cm for the position of collimator leaves. Such a system therefore shows potential as the basis for an on-line verification system capable of treatment verification and monitoring patient motion.

  14. Fourier transform acousto-optic imaging with a custom-designed CMOS smart-pixels array.

    Science.gov (United States)

    Barjean, Kinia; Contreras, Kevin; Laudereau, Jean-Baptiste; Tinet, Éric; Ettori, Dominique; Ramaz, François; Tualle, Jean-Michel

    2015-03-01

    We report acousto-optic imaging (AOI) into a scattering medium using a Fourier Transform (FT) analysis to achieve axial resolution. The measurement system was implemented using a CMOS smart-pixels sensor dedicated to the real-time analysis of speckle patterns. This first proof-of-principle of FT-AOI demonstrates some of its potential advantages, with a signal-to-noise ratio comparable to the one obtained without axial resolution, and with an acquisition rate compatible with a use on living biological tissue.

  15. Nanocantilever based mass sensor integrated with cmos circuitry

    DEFF Research Database (Denmark)

    Davis, Zachary James; Abadal, G.; Campabadal, F.;

    2003-01-01

    We have demonstrated the successful integration of a cantilever based mass detector with standard CMOS circuitry. The purpose of the circuitry is to facilitate the readout of the cantilever's deflection in order to measure resonant frequency shifts of the cantilever. The principle and design of t...

  16. Design of a CMOS temperature sensor with current output

    NARCIS (Netherlands)

    Kolling, A.; Kölling, Arjan; Bak, Frans; Bergveld, Piet; Seevinck, E.; Seevinck, Evert

    1990-01-01

    In this paper a CMOS temperature-to-current converter is presented of which the output current is the difference between a PTC current and an NTC current. The PTC current is derived from a PTAT cell, while the NTC current is derived from a threshold voltage reference source. It is shown that this

  17. Onboard Image Processing System for Hyperspectral Sensor

    Directory of Open Access Journals (Sweden)

    Hiroki Hihara

    2015-09-01

    Full Text Available Onboard image processing systems for a hyperspectral sensor have been developed in order to maximize image data transmission efficiency for large volume and high speed data downlink capacity. Since more than 100 channels are required for hyperspectral sensors on Earth observation satellites, fast and small-footprint lossless image compression capability is essential for reducing the size and weight of a sensor system. A fast lossless image compression algorithm has been developed, and is implemented in the onboard correction circuitry of sensitivity and linearity of Complementary Metal Oxide Semiconductor (CMOS sensors in order to maximize the compression ratio. The employed image compression method is based on Fast, Efficient, Lossless Image compression System (FELICS, which is a hierarchical predictive coding method with resolution scaling. To improve FELICS’s performance of image decorrelation and entropy coding, we apply a two-dimensional interpolation prediction and adaptive Golomb-Rice coding. It supports progressive decompression using resolution scaling while still maintaining superior performance measured as speed and complexity. Coding efficiency and compression speed enlarge the effective capacity of signal transmission channels, which lead to reducing onboard hardware by multiplexing sensor signals into a reduced number of compression circuits. The circuitry is embedded into the data formatter of the sensor system without adding size, weight, power consumption, and fabrication cost.

  18. Onboard Image Processing System for Hyperspectral Sensor.

    Science.gov (United States)

    Hihara, Hiroki; Moritani, Kotaro; Inoue, Masao; Hoshi, Yoshihiro; Iwasaki, Akira; Takada, Jun; Inada, Hitomi; Suzuki, Makoto; Seki, Taeko; Ichikawa, Satoshi; Tanii, Jun

    2015-09-25

    Onboard image processing systems for a hyperspectral sensor have been developed in order to maximize image data transmission efficiency for large volume and high speed data downlink capacity. Since more than 100 channels are required for hyperspectral sensors on Earth observation satellites, fast and small-footprint lossless image compression capability is essential for reducing the size and weight of a sensor system. A fast lossless image compression algorithm has been developed, and is implemented in the onboard correction circuitry of sensitivity and linearity of Complementary Metal Oxide Semiconductor (CMOS) sensors in order to maximize the compression ratio. The employed image compression method is based on Fast, Efficient, Lossless Image compression System (FELICS), which is a hierarchical predictive coding method with resolution scaling. To improve FELICS's performance of image decorrelation and entropy coding, we apply a two-dimensional interpolation prediction and adaptive Golomb-Rice coding. It supports progressive decompression using resolution scaling while still maintaining superior performance measured as speed and complexity. Coding efficiency and compression speed enlarge the effective capacity of signal transmission channels, which lead to reducing onboard hardware by multiplexing sensor signals into a reduced number of compression circuits. The circuitry is embedded into the data formatter of the sensor system without adding size, weight, power consumption, and fabrication cost.

  19. CMOS sensors in 90 nm fabricated on high resistivity wafers: Design concept and irradiation results

    CERN Document Server

    Rivetti, A; Wyss, J; Bisello, D; Costa, M; Kloukinas, K; Demaria, N; Pantano, D; Rousset, J; Battaglia, M; Mansuy, C; Potenza, A; Ikemoto, Y; Giubilato, P; Chalmet, P; Mugnier, H; Silvestrin, L; Marchioro, A

    2013-01-01

    The LePix project aims at improving the radiation hardness and the readout speed of monolithic CMOS sensors through the use of standard CMOS technologies fabricated on high resistivity substrates. In this context, high resistivity means beyond 400 Omega cm, which is at least one order of magnitude greater than the typical value (1-10 Omega cm) adopted for integrated circuit production. The possibility of employing these lightly doped substrates was offered by one foundry for an otherwise standard 90 nm CMOS process. In the paper, the case for such a development is first discussed. The sensor design is then described, along with the key challenges encountered in fabricating the detecting element in a very deep submicron process. Finally, irradiation results obtained on test matrices are reported. (C) 2013 Elsevier B.V. All rights reserved

  20. Investigation of Toshiba 130nm CMOS process as a possible candidate for active silicon sensors in HEP and X-ray experiments

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Yunan; Hemperek, Tomasz; Kishishita, Testsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany); Peric, Ivan [Karlsruhe Institute of Technology, Karlsruhe (Germany)

    2015-07-01

    Following the advances of commercial semiconductor manufacturing technologies there has recently been an increased interest within experimental physics community in applying CMOS manufacturing processes to developing active silicon sensors. Possibility of applying high voltage bias combined with high resistivity substrate allows for better depletion of sensor and therefore quicker and more efficient charge collection. One of processes that accommodates those features is Toshiba 130 nm CMOS technology (CMOS3E). Within our group a test chip was designed to examine the suitability of this technology for physics experiment (both for HEP and X-ray imaging). Design consisted of 4 pixel matrices with total of 12 different pixel flavors allowing for evaluation of various pixel geometries and architectures in terms of depletion depth, noise performance, charge collection efficiency, etc. During this talk initial outcome of this evaluation is presented, starting with brief introduction to technology itself, followed by results of TCAD simulations, description of final design and first measurements results.

  1. Coupling of a CMOS Optical Sensor to a Micromachined Deformable Mirror with an Adaline Neural Method

    NARCIS (Netherlands)

    De Lima Monteiro, D.W.; Ferreira, A.I.; Teixeira, F.B.; Melo, J.G.M.; Vdovin, G.V.

    2006-01-01

    We report on the preliminary results of an Adaline neural method for the coupling of a custom CMOS wavefront sensor to a micromachined adaptive mirror. The algorithm does not rely on a fixed basis matrix -as opposed to traditional methods-, offers excellent immunity to round-off errors and admits re

  2. Coupling of a CMOS Optical Sensor to a Micromachined Deformable Mirror with an Adaline Neural Method

    NARCIS (Netherlands)

    De Lima Monteiro, D.W.; Ferreira, A.I.; Teixeira, F.B.; Melo, J.G.M.; Vdovin, G.V.

    2006-01-01

    We report on the preliminary results of an Adaline neural method for the coupling of a custom CMOS wavefront sensor to a micromachined adaptive mirror. The algorithm does not rely on a fixed basis matrix -as opposed to traditional methods-, offers excellent immunity to round-off errors and admits re

  3. A MGy Radiation-Hardened Sensor Instrumentation SoC in 65nm CMOS Technology

    OpenAIRE

    Verbeeck, Jens; Cao, Ying; Van Uffelen, Marco; Mont Casellas, Laura; Damiani, Carlo; Meek, Richard; Haist, Bernhard; Steyaert, Michiel; Leroux, Paul

    2014-01-01

    A radiation-hardened sensor instrumentation SoC is presented in this paper. The SoC is implemented in a standard 65nm CMOS technology, and achieves MGy-level TID radiation hardness through radiation-hardening-by-design.

  4. A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications

    Directory of Open Access Journals (Sweden)

    Li Li

    2012-02-01

    Full Text Available Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from −40 °C to 120 °C.

  5. A Highly Sensitive CMOS Digital Hall Sensor for Low Magnetic Field Applications

    Science.gov (United States)

    Xu, Yue; Pan, Hong-Bin; He, Shu-Zhuan; Li, Li

    2012-01-01

    Integrated CMOS Hall sensors have been widely used to measure magnetic fields. However, they are difficult to work with in a low magnetic field environment due to their low sensitivity and large offset. This paper describes a highly sensitive digital Hall sensor fabricated in 0.18 μm high voltage CMOS technology for low field applications. The sensor consists of a switched cross-shaped Hall plate and a novel signal conditioner. It effectively eliminates offset and low frequency 1/f noise by applying a dynamic quadrature offset cancellation technique. The measured results show the optimal Hall plate achieves a high current related sensitivity of about 310 V/AT. The whole sensor has a remarkable ability to measure a minimum ±2 mT magnetic field and output a digital Hall signal in a wide temperature range from −40 °C to 120 °C. PMID:22438758

  6. A CMOS detection chip for amperometric sensors with chopper stabilized incremental ΔΣ ADC

    Science.gov (United States)

    Min, Chen; Yuntao, Liu; Jingbo, Xiao; Jie, Chen

    2016-06-01

    This paper presents a low noise complimentary metal-oxide-semiconductor (CMOS) detection chip for amperometric electrochemical sensors. In order to effectively remove the input offset of the cascaded integrators and the low frequency noise in the modulator, a novel offset cancellation chopping scheme was proposed in the Incremental ΔΣ analog to digital converter (IADC). A novel low power potentiostat was employed in this chip to provide the biasing voltage for the sensor while mirroring the sensor current out for detection. The chip communicates with FPGA through standard built in I2C interface and SPI bus. Fabricated in 0.18-μm CMOS process, this chip detects current signal with high accuracy and high linearity. A prototype microsystem was produced to verify the detection chip performance with current input as well as micro-sensors. Project supported by the State Key Development Program for Basic Research of China (No. 2015CB352100).

  7. Optical readout of a triple-GEM detector by means of a CMOS sensor

    Energy Technology Data Exchange (ETDEWEB)

    Marafini, M. [INFN Sezione di Roma (Italy); Museo Storico della Fisica e Centro Studi e Ricerche “E. Fermi”, Roma (Italy); Patera, V. [INFN Sezione di Roma (Italy); Museo Storico della Fisica e Centro Studi e Ricerche “E. Fermi”, Roma (Italy); Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Pinci, D., E-mail: davide.pinci@roma1.infn.it [INFN Sezione di Roma (Italy); Sarti, A. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Dipartimento di Scienze di Base e Applicate per Ingegneria, Sapienza Università di Roma (Italy); Sciubba, A. [INFN Sezione di Roma (Italy); Museo Storico della Fisica e Centro Studi e Ricerche “E. Fermi”, Roma (Italy); Dipartimento di Scienze di Base e Applicate per Ingegneria, Sapienza Università di Roma (Italy); Spiriti, E. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy)

    2016-07-11

    In last years, the development of optical sensors has produced objects able to provide very interesting performance. Large granularity is offered along with a very high sensitivity. CMOS sensors with millions of pixels able to detect as few as two or three photons per pixel are commercially available and can be used to read-out the optical signals provided by tracking particle detectors. In this work the results obtained by optically reading-out a triple-GEM detector by a commercial CMOS sensor will be presented. A standard detector was assembled with a transparent window below the third GEM allowing the light to get out. The detector is supplied with an Ar/CF{sub 4} based gas mixture producing 650 nm wavelength photons matching the maximum quantum efficiency of the sensor.

  8. System-in Package of Integrated Humidity Sensor Using CMOS-MEMS Technology.

    Science.gov (United States)

    Lee, Sung Pil

    2015-10-01

    Temperature/humidity microchips with micropump were fabricated using a CMOS-MEMS process and combined with ZigBee modules to implement a sensor system in package (SIP) for a ubiquitous sensor network (USN) and/or a wireless communication system. The current of a diode temperature sensor to temperature and a normalized current of FET humidity sensor to relative humidity showed linear characteristics, respectively, and the use of the micropump has enabled a faster response. A wireless reception module using the same protocol as that in transmission systems processed the received data within 10 m and showed temperature and humidity values in the display.

  9. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-11-04

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)(-0.1) in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

  10. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications

    Directory of Open Access Journals (Sweden)

    Mohtashim Mansoor

    2016-11-01

    Full Text Available An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors, a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

  11. Characterization and performance studies of high-voltage CMOS based pixel sensors

    CERN Document Server

    Smaranda, Dumitru Dan

    2015-01-01

    The high luminosity upgrade of the LHC will push the limits for detectors, specially the silicon trackers which are closest to the interaction point. The ATLAS CMOS Sensor R&D efort is investigating a new technology using high-voltage CMOS processes for producing pixel and strip sensors. In contrast to the currently used technology these devices implement active electronics on the sensor itself, offering a multitude of tuning parameters for achieving the best performance. My summer project revolved around characterising existing samples along with assembling and debugging hardware required for their improvement and functionality. Other tasks involved writing communication protocols using pyBAR to remotely control injection circuitry on a GPAC card, and helping various members of the group with data collection and analysis. Through the summer student programme I have had the opportunity to be part of a vibrant scientic community at the forefront of research, to create bonds with fellow students from univ...

  12. A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

    Science.gov (United States)

    Kim, Jungsuk

    2016-12-01

    This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

  13. Monolithic integration of GMR sensors for standard CMOS-IC current sensing

    Science.gov (United States)

    De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

    2017-09-01

    In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

  14. Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

    CERN Document Server

    Kremastiotis, Iraklis; Campbell, Michael; Dannheim, Dominik; Fiergolski, Adrian; Hynds, Daniel; Kulis, Szymon; Peric, Ivan

    2017-01-01

    The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128 × 128 square pixels with 25 μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼ 20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼ 20 ns for a power consumption of 5 μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼ 20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using...

  15. 50 μm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    Science.gov (United States)

    Zhao, C; Konstantinidis, A C; Zheng, Y; Anaxagoras, T; Speller, R D; Kanicki, J

    2015-12-07

    Wafer-scale CMOS active pixel sensors (APSs) have been developed recently for x-ray imaging applications. The small pixel pitch and low noise are very promising properties for medical imaging applications such as digital breast tomosynthesis (DBT). In this work, we evaluated experimentally and through modeling the imaging properties of a 50 μm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). A modified cascaded system model was developed for CMOS APS x-ray detectors by taking into account the device nonlinear signal and noise properties. The imaging properties such as modulation transfer function (MTF), noise power spectrum (NPS), and detective quantum efficiency (DQE) were extracted from both measurements and the nonlinear cascaded system analysis. The results show that the DynAMITe x-ray detector achieves a high spatial resolution of 10 mm(-1) and a DQE of around 0.5 at spatial frequencies  CMOS APS x-ray detector, image aquisition geometry and image reconstruction techniques should be considered.

  16. Characterisation of a CMOS Active Pixel Sensor for use in the TEAM Microscope

    CERN Document Server

    Battaglia, Marco; Denes, Peter; Doering, Dionisio; Duden, Thomas; Krieger, Brad; Giubilato, Piero; Gnani, Dario; Radmilovic, Velimir

    2010-01-01

    A 1M- and a 4M-pixel monolithic CMOS active pixel sensor with 9.5x9.5 micron^2 pixels have been developed for direct imaging in transmission electron microscopy as part of the TEAM project. We present the design and a full characterisation of the detector. Data collected with electron beams at various energies of interest in electron microscopy are used to determine the detector response. Data are compared to predictions of simulation. The line spread function measured with 80 keV and 300 keV electrons is (12.1+/-0.7) micron and (7.4+/-0.6) micron, respectively, in good agreement with our simulation. We measure the detection quantum efficiency to be 0.78+/-0.04 at 80 keV and 0.74+/-0.03 at 300 keV. Using a new imaging technique, based on single electron reconstruction, the line spread function for 80 keV and 300 keV electrons becomes (6.7+/-0.3) micron and (2.4+/-0.2) micron, respectively. The radiation tolerance of the pixels has been tested up to 5 Mrad and the detector is still functional with a decrease o...

  17. Characterisation of a CMOS active pixel sensor for use in the TEAM microscope

    Energy Technology Data Exchange (ETDEWEB)

    Battaglia, Marco, E-mail: MBattaglia@lbl.go [Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Santa Cruz Institute of Particle Physics, University of California at Santa Cruz, CA 95064 (United States); Contarato, Devis; Denes, Peter; Doering, Dionisio; Duden, Thomas; Krieger, Brad [Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Giubilato, Piero [Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States); Dipartimento di Fisica, Universita degli Studi, Padova I-35131 (Italy); Gnani, Dario; Radmilovic, Velimir [Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)

    2010-10-21

    A 1M- and a 4M-pixel monolithic CMOS active pixel sensor with 9.5x9.5{mu}m{sup 2} pixels have been developed for direct imaging in transmission electron microscopy as part of the TEAM project. We present the design and a full characterisation of the detector. Data collected with electron beams at various energies of interest in electron microscopy are used to determine the detector response. Data are compared to predictions of simulation. The line spread function measured with 80 and 300 keV electrons is (12.1{+-}0.7) and (7.4{+-}0.6){mu}m, respectively, in good agreement with our simulation. We measure the detection quantum efficiency to be 0.78{+-}0.04 at 80 keV and 0.74{+-}0.03 at 300 keV. Using a new imaging technique, based on single electron reconstruction, the line spread function for 80 and 300 keV electrons becomes (6.7{+-}0.3) and (2.4{+-}0.2){mu}m, respectively. The radiation tolerance of the pixels has been tested up to 5 Mrad and the detector is still functional with a decrease of dynamic range by {approx_equal}30%, corresponding to a reduction in full-well depth from {approx}39 to {approx}27 primary 300 keV electrons, due to leakage current increase, but identical line spread function performance.

  18. Optimal Geometry of CMOS Voltage-Mode and Current-Mode Vertical Magnetic Hall Sensors

    OpenAIRE

    2015-01-01

    Four different geometries of a vertical Hall sensor\\ud are presented and studied in this paper. The current spinning\\ud technique compensates for the offset and the sensors, driven in\\ud current-mode, provide a differential signal current for a possible\\ud capacitive integration over a defined time-slot. The sensors have\\ud been fabricated using a 6-metal 0.18-μm CMOS technology and\\ud fully experimentally tested. The optimal solution will be further\\ud investigated for bendable electronics. ...

  19. Design and fabrication of a CMOS-compatible MHP gas sensor

    Directory of Open Access Journals (Sweden)

    Ying Li

    2014-03-01

    Full Text Available A novel micro-hotplate (MHP gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO2 film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperature in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3% in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.

  20. Integrated X-ray and charged particle active pixel CMOS sensor arrays using an epitaxial silicon sensitive region

    Energy Technology Data Exchange (ETDEWEB)

    Kleinfelder, Stuart; Bichsel, Hans; Bieser, Fred; Matis, Howard S.; Rai, Gulshan; Retiere, Fabrice; Weiman, Howard; Yamamoto, Eugene

    2002-07-01

    Integrated CMOS Active Pixel Sensor (APS) arrays have been fabricated and tested using X-ray and electron sources. The 128 by 128 pixel arrays, designed in a standard 0.25 micron process, use a {approx}10 micron epitaxial silicon layer as a deep detection region. The epitaxial layer has a much greater thickness than the surface features used by standard CMOS APS, leading to stronger signals and potentially better signal-to-noise ratio (SNR). On the other hand, minority carriers confined within the epitaxial region may diffuse to neighboring pixels, blur images and reduce peak signal intensity. But for low-rate, sparse-event images, centroid analysis of this diffusion may be used to increase position resolution. Careful trade-offs involving pixel size and sense-node area verses capacitance must be made to optimize overall performance. The prototype sensor arrays, therefore, include a range of different pixel designs, including different APS circuits and a range of different epitaxial layer contact structures. The fabricated arrays were tested with 1.5 GeV electrons and Fe-55 X-ray sources, yielding a measured noise of 13 electrons RMS and an SNR for single Fe-55 X-rays of greater than 38.

  1. Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

    Directory of Open Access Journals (Sweden)

    Min Yoon

    2016-01-01

    Full Text Available We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency CMOS (fT/fmax=120/140 GHz technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to reduce parasitic capacitance at the band of 24 GHz. The proposed sensor has low cost and low power dissipation since it is realized using CMOS process. The proposed sensor showed the lowest noise figure of 2.9 dB and the highest conversion gain of 40.2 dB as compared to recently reported research results. It also showed small chip size of 0.56 mm2, low power dissipation of 39.5 mW, and wide operating temperature range of −40 to +125°C.

  2. Three-dimensional cascaded system analysis of a 50 µm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    Science.gov (United States)

    Zhao, C; Vassiljev, N; Konstantinidis, A C; Speller, R D; Kanicki, J

    2017-03-07

    High-resolution, low-noise x-ray detectors based on the complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been developed and proposed for digital breast tomosynthesis (DBT). In this study, we evaluated the three-dimensional (3D) imaging performance of a 50 µm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). The two-dimensional (2D) angle-dependent modulation transfer function (MTF), normalized noise power spectrum (NNPS), and detective quantum efficiency (DQE) were experimentally characterized and modeled using the cascaded system analysis at oblique incident angles up to 30°. The cascaded system model was extended to the 3D spatial frequency space in combination with the filtered back-projection (FBP) reconstruction method to calculate the 3D and in-plane MTF, NNPS and DQE parameters. The results demonstrate that the beam obliquity blurs the 2D MTF and DQE in the high spatial frequency range. However, this effect can be eliminated after FBP image reconstruction. In addition, impacts of the image acquisition geometry and detector parameters were evaluated using the 3D cascaded system analysis for DBT. The result shows that a wider projection angle range (e.g.  ±30°) improves the low spatial frequency (below 5 mm(-1)) performance of the CMOS APS detector. In addition, to maintain a high spatial resolution for DBT, a focal spot size of smaller than 0.3 mm should be used. Theoretical analysis suggests that a pixelated scintillator in combination with the 50 µm pixel pitch CMOS APS detector could further improve the 3D image resolution. Finally, the 3D imaging performance of the CMOS APS and an indirect amorphous silicon (a-Si:H) thin-film transistor (TFT) passive pixel sensor (PPS) detector was simulated and compared.

  3. Three-dimensional cascaded system analysis of a 50 µm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis

    Science.gov (United States)

    Zhao, C.; Vassiljev, N.; Konstantinidis, A. C.; Speller, R. D.; Kanicki, J.

    2017-03-01

    High-resolution, low-noise x-ray detectors based on the complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been developed and proposed for digital breast tomosynthesis (DBT). In this study, we evaluated the three-dimensional (3D) imaging performance of a 50 µm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). The two-dimensional (2D) angle-dependent modulation transfer function (MTF), normalized noise power spectrum (NNPS), and detective quantum efficiency (DQE) were experimentally characterized and modeled using the cascaded system analysis at oblique incident angles up to 30°. The cascaded system model was extended to the 3D spatial frequency space in combination with the filtered back-projection (FBP) reconstruction method to calculate the 3D and in-plane MTF, NNPS and DQE parameters. The results demonstrate that the beam obliquity blurs the 2D MTF and DQE in the high spatial frequency range. However, this effect can be eliminated after FBP image reconstruction. In addition, impacts of the image acquisition geometry and detector parameters were evaluated using the 3D cascaded system analysis for DBT. The result shows that a wider projection angle range (e.g.  ±30°) improves the low spatial frequency (below 5 mm-1) performance of the CMOS APS detector. In addition, to maintain a high spatial resolution for DBT, a focal spot size of smaller than 0.3 mm should be used. Theoretical analysis suggests that a pixelated scintillator in combination with the 50 µm pixel pitch CMOS APS detector could further improve the 3D image resolution. Finally, the 3D imaging performance of the CMOS APS and an indirect amorphous silicon (a-Si:H) thin-film transistor (TFT) passive pixel sensor (PPS) detector was simulated and compared.

  4. A CMOS One-chip Wireless Camera with Digital Image Transmission Function for Capsule Endoscopes

    Science.gov (United States)

    Itoh, Shinya; Kawahito, Shoji; Terakawa, Susumu

    This paper presents the design and implementation of a one-chip camera device for capsule endoscopes. This experimental chip integrates functional circuits required for capsule endoscopes and digital image transmission function. The integrated functional blocks include an image array, a timing generator, a clock generator, a voltage regulator, a 10b cyclic A/D converter, and a BPSK modulator. It can be operated autonomously with 3 pins (VDD, GND, and DATAOUT). A prototype image sensor chip which has 320x240 effective pixels was fabricated using 0.25μm CMOS image sensor process and the autonomous imaging was demonstrated. The chip size is 4.84mmx4.34mm. With a 2.0 V power supply, the analog part consumes 950μW and the total power consumption at 2 frames per second (fps) is 2.6mW. Error-free image transmission over a distance of 48cm at 2.5Mbps corresponding to 2fps has been succeeded with inductive coupling.

  5. Detailed study of the column-based priority logic readout of Topmetal-II- CMOS pixel direct charge sensor

    CERN Document Server

    An, Mangmang; Gao, Chaosong; Han, Mikyung; Huang, Guangming; Ji, Rong; Li, Xiaoting; Mei, Yuan; Pei, Hua; Sun, Quan; Sun, Xiangming; Wang, Kai; Xiao, Le; Yang, Ping; Zhang, Wei; Zhou, Wei

    2016-01-01

    We present the detailed study of the digital readout of Topmetal-II- CMOS pixel direct charge sensor. Topmetal-II- is an integrated sensor with an array of 72X72 pixels each capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through comparators with individually DAC settable thresholds in each pixel. The hits are read out via a column-based priority logic structure, retaining both hit location and time information. The in-array column-based priority logic is fully combinational hence there is no clock distributed in the pixel array. Sequential logic and clock are placed on the peripheral of the array. We studied the detailed working behavior and performance of this readout, and demonstrated its potential in imaging applications.

  6. Wide Dynamic Range CMOS Potentiostat for Amperometric Chemical Sensor

    OpenAIRE

    Wei-Song Wang; Wei-Ting Kuo; Hong-Yi Huang; Ching-Hsing Luo

    2010-01-01

    Presented is a single-ended potentiostat topology with a new interface connection between sensor electrodes and potentiostat circuit to avoid deviation of cell voltage and linearly convert the cell current into voltage signal. Additionally, due to the increased harmonic distortion quantity when detecting low-level sensor current, the performance of potentiostat linearity which causes the detectable current and dynamic range to be limited is relatively decreased. Thus, to alleviate these irreg...

  7. Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

    Science.gov (United States)

    Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

    2009-01-01

    In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

  8. Use and imaging performance of CMOS flat panel imager with LiF/ZnS(Ag) and Gadox scintillation screens for neutron radiography

    Science.gov (United States)

    Cha, B. K.; kim, J. Y.; Kim, T. J.; Sim, C.; Cho, G.; Lee, D. H.; Seo, C.-W.; Jeon, S.; Huh, Y.

    2011-01-01

    In digital neutron radiography system, a thermal neutron imaging detector based on neutron-sensitive scintillating screens with CMOS(complementary metal oxide semiconductor) flat panel imager is introduced for non-destructive testing (NDT) application. Recently, large area CMOS APS (active-pixel sensor) in conjunction with scintillation films has been widely used in many digital X-ray imaging applications. Instead of typical imaging detectors such as image plates, cooled-CCD cameras and amorphous silicon flat panel detectors in combination with scintillation screens, we tried to apply a scintillator-based CMOS APS to neutron imaging detection systems for high resolution neutron radiography. In this work, two major Gd2O2S:Tb and 6LiF/ZnS:Ag scintillation screens with various thickness were fabricated by a screen printing method. These neutron converter screens consist of a dispersion of Gd2O2S:Tb and 6LiF/ZnS:Ag scintillating particles in acrylic binder. These scintillating screens coupled-CMOS flat panel imager with 25x50mm2 active area and 48μm pixel pitch was used for neutron radiography. Thermal neutron flux with 6x106n/cm2/s was utilized at the NRF facility of HANARO in KAERI. The neutron imaging characterization of the used detector was investigated in terms of relative light output, linearity and spatial resolution in detail. The experimental results of scintillating screen-based CMOS flat panel detectors demonstrate possibility of high sensitive and high spatial resolution imaging in neutron radiography system.

  9. Capacitive micropressure sensors with underneath readout circuit using a standard CMOS process

    Science.gov (United States)

    Chang, Shihchen; Dai, Chingliang; Chiou, Jinghung; Chang, Peizen

    2001-08-01

    A capacitive micropressure sensor with readout circuits on a single chip is fabricated using commercial 0.35micrometers CMOS process technology and post-processing. The main break through feature of the chip is the positioning of its readout circuits under the pressure sensor, allowing the chip to be smaller. Post-processing included anisotropic dry etching and wet etching to remove the sacrificial layer, and the use of PECVD nitride to seal the etching holes of the pressure sensor. The sacrificial layer was the metal 3 layer of the standard 0.35 micrometers CMOS process. In addition, the readout circuit is divided into analog and digital parts, with the digital part being an alternate coupled RS flip- flop with four inverters that sharpened the output wave. Moreover, the analog part is employed switched capacitor methodology. The pressure sensor contained an 8 X 8 sensing cells array, and the total area of the pressure sensor chip is 2mmx2 mm. In addition to illustrating the design and fabrication of the capacitive pressure sensor, this investigation demonstrates the simulation and testing results of the readout circuit.

  10. A CMOS pressure sensor with integrated interface for passive RFID applications

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Wu, Xiang; Fu, Zhihui

    2014-12-01

    This paper presents a CMOS pressure sensor with integrated interface for passive RFID sensing applications. The pressure sensor consists of three parts: top electrode, dielectric layer and bottom electrode. The dielectric layer consists of silicon oxide and an air gap. The bottom electrode is made of polysilicon. The gap is formed by sacrificial layer release and the Al vapor process is used to seal the gap and form the top electrode. The sensor interface is based on phase-locked architecture, which allows the use of fully digital blocks. The proposed pressure sensor and interface is fabricated in a 0.18 μm CMOS process. The measurement results show the pressure sensor achieves excellent linearity with a sensitivity of 1.2 fF kPa-1. The sensor interface consumes only 1.1 µW of power at 0.5 V voltage supply, which is at least an order of magnitude better than state-of-the-art designs.

  11. Image processing occupancy sensor

    Science.gov (United States)

    Brackney, Larry J.

    2016-09-27

    A system and method of detecting occupants in a building automation system environment using image based occupancy detection and position determinations. In one example, the system includes an image processing occupancy sensor that detects the number and position of occupants within a space that has controllable building elements such as lighting and ventilation diffusers. Based on the position and location of the occupants, the system can finely control the elements to optimize conditions for the occupants, optimize energy usage, among other advantages.

  12. Quality assessment of ultra-thin CMOS sensors for the micro vertex detector of the CBM experiment at FAIR

    Energy Technology Data Exchange (ETDEWEB)

    Koziel, Michal; Bialas, Norbert; Milanovic, Borislaw [University of Frankfurt, Germany (Germany); Collaboration: CBM-MVD-Collaboration

    2014-07-01

    The Compressed Baryonic Matter experiment installed at the future FAIR facility will be equipped with a high-precision micro-vertex detector aiming at an outstanding primary and secondary vertex resolution. Highly granular, ultra-low material budget sensors, so-called Monolithic Active Pixel Sensors, manufactured at standard CMOS process, will be employed. Imperfections in CMOS process as well as further dicing and thinning procedures affect the yield of sensors to be mounted in the detector stations. To select sensors with the best characteristics, probe testing prior to integration is mandatory. handling and testing of 50-μm thin CMOS pixel sensors is non-standard. This contribution presents the dedicated tools and procedures, focusing on the question whether such thin devices can be efficiently and reliably probe-tested.

  13. Multifunctional Platform with CMOS-Compatible Tungsten Microhotplate for Pirani, Temperature, and Gas Sensor

    Directory of Open Access Journals (Sweden)

    Jiaqi Wang

    2015-10-01

    Full Text Available A multifunctional platform based on the microhotplate was developed for applications including a Pirani vacuum gauge, temperature, and gas sensor. It consisted of a tungsten microhotplate and an on-chip operational amplifier. The platform was fabricated in a standard complementary metal oxide semiconductor (CMOS process. A tungsten plug in standard CMOS process was specially designed as the serpentine resistor for the microhotplate, acting as both heater and thermister. With the sacrificial layer technology, the microhotplate was suspended over the silicon substrate with a 340 nm gap. The on-chip operational amplifier provided a bias current for the microhotplate. This platform has been used to develop different kinds of sensors. The first one was a Pirani vacuum gauge ranging from 1-1 to 105 Pa. The second one was a temperature sensor ranging from -20 to 70 °C. The third one was a thermal-conductivity gas sensor, which could distinguish gases with different thermal conductivities in constant gas pressure and environment temperature. In the fourth application, with extra fabrication processes including the deposition of gas-sensitive film, the platform was used as a metal-oxide gas sensor for the detection of gas concentration.

  14. A CMOS Active Pixel Sensor for Charged Particle Detection

    Energy Technology Data Exchange (ETDEWEB)

    Matis, Howard S.; Bieser, Fred; Kleinfelder, Stuart; Rai, Gulshan; Retiere, Fabrice; Ritter, Hans George; Singh, Kunal; Wurzel, Samuel E.; Wieman, Howard; Yamamoto, Eugene

    2002-12-02

    Active Pixel Sensor (APS) technology has shown promise for next-generation vertex detectors. This paper discusses the design and testing of two generations of APS chips. Both are arrays of 128 by 128 pixels, each 20 by 20 {micro}m. Each array is divided into sub-arrays in which different sensor structures (4 in the first version and 16 in the second) and/or readout circuits are employed. Measurements of several of these structures under Fe{sup 55} exposure are reported. The sensors have also been irradiated by 55 MeV protons to test for radiation damage. The radiation increased the noise and reduced the signal. The noise can be explained by shot noise from the increased leakage current and the reduction in signal is due to charge being trapped in the epi layer. Nevertheless, the radiation effect is small for the expected exposures at RHIC and RHIC II. Finally, we describe our concept for mechanically supporting a thin silicon wafer in an actual detector.

  15. Low Light CMOS Contact Imager with an Integrated Poly-Acrylic Emission Filter for Fluorescence Detection

    Directory of Open Access Journals (Sweden)

    Yonathan Dattner

    2010-05-01

    Full Text Available This study presents the fabrication of a low cost poly-acrylic acid (PAA based emission filter integrated with a low light CMOS contact imager for fluorescence detection. The process involves the use of PAA as an adhesive for the emission filter. The poly-acrylic solution was chosen due its optical transparent properties, adhesive properties, miscibility with polar protic solvents and most importantly its bio-compatibility with a biological environment. The emission filter, also known as an absorption filter, involves dissolving an absorbing specimen in a polar protic solvent and mixing it with the PAA to uniformly bond the absorbing specimen and harden the filter. The PAA is optically transparent in solid form and therefore does not contribute to the absorbance of light in the visible spectrum. Many combinations of absorbing specimen and polar protic solvents can be derived, yielding different filter characteristics in different parts of the spectrum. We report a specific combination as a first example of implementation of our technology. The filter reported has excitation in the green spectrum and emission in the red spectrum, utilizing the increased quantum efficiency of the photo sensitive sensor array. The thickness of the filter (20 μm was chosen by calculating the desired SNR using Beer-Lambert’s law for liquids, Quantum Yield of the fluorophore and the Quantum Efficiency of the sensor array. The filters promising characteristics make it suitable for low light fluorescence detection. The filter was integrated with a fully functional low noise, low light CMOS contact imager and experimental results using fluorescence polystyrene micro-spheres are presented.

  16. Real-time detection of fast and thermal neutrons in radiotherapy with CMOS sensors

    Science.gov (United States)

    Arbor, Nicolas; Higueret, Stephane; Elazhar, Halima; Combe, Rodolphe; Meyer, Philippe; Dehaynin, Nicolas; Taupin, Florence; Husson, Daniel

    2017-03-01

    The peripheral dose distribution is a growing concern for the improvement of new external radiation modalities. Secondary particles, especially photo-neutrons produced by the accelerator, irradiate the patient more than tens of centimeters away from the tumor volume. However the out-of-field dose is still not estimated accurately by the treatment planning softwares. This study demonstrates the possibility of using a specially designed CMOS sensor for fast and thermal neutron monitoring in radiotherapy. The 14 microns-thick sensitive layer and the integrated electronic chain of the CMOS are particularly suitable for real-time measurements in γ/n mixed fields. An experimental field size dependency of the fast neutron production rate, supported by Monte Carlo simulations and CR-39 data, has been observed. This dependency points out the potential benefits of a real-time monitoring of fast and thermal neutron during beam intensity modulated radiation therapies.

  17. A CMOS analog front-end chip for amperometric electrochemical sensors

    Science.gov (United States)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (Σ-Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  18. Characterization of zeolite-trench-embedded microcantilevers with CMOS strain gauge for integrated gas sensor applications

    Science.gov (United States)

    Inoue, Shu; Denoual, Matthieu; Awala, Hussein; Grand, Julien; Mintova, Sveltana; Tixier-Mita, Agnès; Mita, Yoshio

    2016-04-01

    Custom-synthesized zeolite is coated and fixed into microcantilevers with microtrenches of 1 to 5 µm width. Zeolite is a porous material that absorbs chemical substances; thus, it is expected to work as a sensitive chemical-sensing head. The total mass increases with gas absorption, and the cantilever resonance frequency decreases accordingly. In this paper, a thick zeolite cantilever sensor array system for high sensitivity and selectivity is proposed. The system is composed of an array of microcantilevers with silicon deep trenches. The cantilevers are integrated with CMOS-made polysilicon strain gauges for frequency response electrical measurement. The post-process fabrication of such an integrated array out of a foundry-made CMOS chip is successful. On the cantilevers, three types of custom zeolite (FAU-X, LTL, and MFI) are integrated by dip and heating methods. The preliminary measurement has shown a clear shift of resonance frequency by the chemical absorbance of ethanol gas.

  19. Compressive Sensing Based Bio-Inspired Shape Feature Detection CMOS Imager

    Science.gov (United States)

    Duong, Tuan A. (Inventor)

    2015-01-01

    A CMOS imager integrated circuit using compressive sensing and bio-inspired detection is presented which integrates novel functions and algorithms within a novel hardware architecture enabling efficient on-chip implementation.

  20. CMOS front-end electronics for radiation sensors

    CERN Document Server

    Rivetti, Angelo

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  1. A Low-Noise CMOS Pixel Direct Charge Sensor, Topmetal-II-

    CERN Document Server

    An, Mangmang; Gao, Chaosong; Han, Mikyung; Ji, Rong; Li, Xiaoting; Mei, Yuan; Sun, Quan; Sun, Xiangming; Wang, Kai; Xiao, Le; Xu, Nu; Yang, Ping; Zhou, Wei

    2016-01-01

    We report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35um CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e- analog noise and a 200e- minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.

  2. A low-noise CMOS pixel direct charge sensor, Topmetal-II-

    Science.gov (United States)

    An, Mangmang; Chen, Chufeng; Gao, Chaosong; Han, Mikyung; Ji, Rong; Li, Xiaoting; Mei, Yuan; Sun, Quan; Sun, Xiangming; Wang, Kai; Xiao, Le; Yang, Ping; Zhou, Wei

    2016-02-01

    We report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a analog noise and a 200e- minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.

  3. Colorimetric Sensor Arrays System Based on FPGA for Image Recognition

    Institute of Scientific and Technical Information of China (English)

    Rui Chen; Jian-Hua Xu; Ya-Dong Jiang

    2009-01-01

    A FPGA-based image recognition system is designed for colorimetric sensor array in order to recognize a wide range of volatile organic compounds. The gas molecule is detected by the responsive sensor array and the responsive image is obtained. The image is decomposed to RGB color components using CMOS image sensor. An embedded image recognition archi- tecture based on Xilinx Spartan-3 FPGA is designed to implement the algorithms of image recognition. The algorithm of color coherence vector is discussed in detail[X1] compared with the algorithm of color histograms, and experimental results demonstrate that both of the two algorithms could be analyzed effectively to represent different volatile organic compounds according to their different responsive images in this system.

  4. Optical Characterization of Lorentz Force Based CMOS-MEMS Magnetic Field Sensor

    Directory of Open Access Journals (Sweden)

    John Ojur Dennis

    2015-07-01

    Full Text Available Magnetic field sensors are becoming an essential part of everyday life due to the improvements in their sensitivities and resolutions, while at the same time they have become compact, smaller in size and economical. In the work presented herein a Lorentz force based CMOS-MEMS magnetic field sensor is designed, fabricated and optically characterized. The sensor is fabricated by using CMOS thin layers and dry post micromachining is used to release the device structure and finally the sensor chip is packaged in DIP. The sensor consists of a shuttle which is designed to resonate in the lateral direction (first mode of resonance. In the presence of an external magnetic field, the Lorentz force actuates the shuttle in the lateral direction and the amplitude of resonance is measured using an optical method. The differential change in the amplitude of the resonating shuttle shows the strength of the external magnetic field. The resonance frequency of the shuttle is determined to be 8164 Hz experimentally and from the resonance curve, the quality factor and damping ratio are obtained. In an open environment, the quality factor and damping ratio are found to be 51.34 and 0.00973 respectively. The sensitivity of the sensor is determined in static mode to be 0.034 µm/mT when a current of 10 mA passes through the shuttle, while it is found to be higher at resonance with a value of 1.35 µm/mT at 8 mA current. Finally, the resolution of the sensor is found to be 370.37 µT.

  5. Optical Characterization of Lorentz Force Based CMOS-MEMS Magnetic Field Sensor.

    Science.gov (United States)

    Dennis, John Ojur; Ahmad, Farooq; Khir, M Haris Bin Md; Bin Hamid, Nor Hisham

    2015-07-27

    Magnetic field sensors are becoming an essential part of everyday life due to the improvements in their sensitivities and resolutions, while at the same time they have become compact, smaller in size and economical. In the work presented herein a Lorentz force based CMOS-MEMS magnetic field sensor is designed, fabricated and optically characterized. The sensor is fabricated by using CMOS thin layers and dry post micromachining is used to release the device structure and finally the sensor chip is packaged in DIP. The sensor consists of a shuttle which is designed to resonate in the lateral direction (first mode of resonance). In the presence of an external magnetic field, the Lorentz force actuates the shuttle in the lateral direction and the amplitude of resonance is measured using an optical method. The differential change in the amplitude of the resonating shuttle shows the strength of the external magnetic field. The resonance frequency of the shuttle is determined to be 8164 Hz experimentally and from the resonance curve, the quality factor and damping ratio are obtained. In an open environment, the quality factor and damping ratio are found to be 51.34 and 0.00973 respectively. The sensitivity of the sensor is determined in static mode to be 0.034 µm/mT when a current of 10 mA passes through the shuttle, while it is found to be higher at resonance with a value of 1.35 µm/mT at 8 mA current. Finally, the resolution of the sensor is found to be 370.37 µT.

  6. CMOS based sensor for dielectric spectroscopy of biological cell suspension

    Science.gov (United States)

    Guha, S.; Schmalz, K.; Meliani, C.; Wenger, Ch

    2013-04-01

    In this work we investigate the use of microwave frequency range to measure the concentration of cells in a biological cell suspension. A theoretical model is discussed and the advantage of high frequency, which is to avoid dispersion mechanisms due to the cell parameters at lower frequencies (for example membrane capacitance), has been described. Interdigitated capacitor (IDC) has been proposed as the sensor for analysing the concentration of a cell species in the suspension. The read-out circuit is a VCO using the IDC and a pair of inductors as resonator. The capacitance of the IDC which is the function of the permittivity of the biological cell suspension determines the resonant frequency of the LC tank oscillator. Thus the concentration of cells in a solution, affecting its permittivity, is read out as the frequency of the oscillator.

  7. A novel CMOS-compatible, monolithically integrated line-scan hyperspectral imager covering the VIS-NIR range

    Science.gov (United States)

    Gonzalez, Pilar; Tack, Klaas; Geelen, Bert; Masschelein, Bart; Charle, Wouter; Vereecke, Bart; Lambrechts, Andy

    2016-05-01

    Imec has developed a process for the monolithic integration of optical filters on top of CMOS image sensors, leading to compact, cost-efficient and faster hyperspectral cameras. Different prototype sensors are available, most notably a 600- 1000 nm line-scan imager, and two mosaic sensors: a 4x4 VIS (470-620 nm range) and a 5x5 VNIR (600-1000 nm). In response to the users' demand for a single sensor able to cover both the VIS and NIR ranges, further developments have been made to enable more demanding applications. As a result, this paper presents the latest addition to imec's family of monolithically-integrated hyperspectral sensors: a line scan sensor covering the range 470-900 nm. This new prototype sensor can acquire hyperspectral image cubes of 2048 pixels over 192 bands (128 bands for the 600- 900 nm range, and 64 bands for the 470-620 nm range) at 340 cubes per second for normal machine vision illumination levels.

  8. Recent results with HV-CMOS and planar sensors for the CLIC vertex detector

    CERN Document Server

    AUTHOR|(SzGeCERN)734627

    2016-01-01

    The physics aims for the future multi-TeV e+e- Compact Linear Collider (CLIC) impose high precision requirements on the vertex detector which has to match the experimental conditions, such as the time structure of the collisions and the presence of beam-induced backgrounds. The principal challenges are: a point resolution of 3μm, 10 ns time stamping capabilities, low mass (⇠0.2% X0 per layer), low power dissipation and pulsed power operation. Recent results of test beam measurements and GEANT4 simulations for assemblies with Timepix3 ASICs and thin active-edge sensors are presented. The 65 nm CLICpix readout ASIC with 25μm pitch was bump bonded to planar silicon sensors and also capacitively coupled through a thin layer of glue to active HV-CMOS sensors. Test beam results for these two hybridisation concepts are presented.

  9. CMOS Humidity Sensor System Using Carbon Nitride Film as Sensing Materials

    Directory of Open Access Journals (Sweden)

    Shaestagir Chowdhury

    2008-04-01

    Full Text Available An integrated humidity sensor system with nano-structured carbon nitride film as humidity sensing material is fabricated by a 0.8 μm analog mixed CMOS process. The integrated sensor system consists of differential humidity sensitive field effect transistors (HUSFET, temperature sensor, and operational amplifier. The process contains two poly, two metal and twin well technology. To form CNx film on Si3N4/Si substrate, plasma etching is performed to the gate area as well as trenches. CNx film is deposited by reactive RF magnetron sputtering method and patterned by the lift-off technique. The drain current is proportional to the dielectric constant, and the sensitivity is 2.8 ㎂/%RH.

  10. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

    Science.gov (United States)

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-10-27

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

  11. One-chip electronic detection of DNA hybridization using precision impedance-based CMOS array sensor.

    Science.gov (United States)

    Lee, Kang-Ho; Lee, Jeong-Oen; Sohn, Mi-Jin; Lee, Byunghun; Choi, Suk-Hwan; Kim, Sang Kyu; Yoon, Jun-Bo; Cho, Gyu-Hyeong

    2010-12-15

    This paper describes a label-free and fully electronic detection method of DNA hybridization, which is achieved through the use of a 16×8 microarray sensor in conjunction with a new type of impedance spectroscopy constructed with standard complementary metal-oxide-semiconductor (CMOS) technology. The impedance-based method is based on changes in the reactive capacitance and the charge-transfer resistance after hybridization with complementary DNA targets. In previously published label-free techniques, the measured capacitance presented unstable capacitive properties due to the parallel resistance that is not infinite and can cause a leakage by discharging the charge on the capacitor. This paper presents an impedance extraction method that uses excitation by triangular wave voltage, which enables a reliable measurement of both C and R producing a highly sensitive sensor with a stable operation independent of external variables. The system was fabricated in an industrial 0.35-μm 4-metal 2-poly CMOS process, integrating working electrodes and readout electronics into one chip. The integrated readout, which uses a parasitic insensitive integrator, achieves an enlarged detection range and improved noise performance. The maximum average relative variations of C and R are 31.5% and 68.6%, respectively, after hybridization with a 1 μM target DNA. The proposed sensor allows quantitative evaluation of the molecule densities on the chip with distinguishable variation in the impedance. This fully electronic microsystem has great potential for use with bioanalytical tools and point-of-care diagnosis.

  12. On drift fields in CMOS Monolithic Active Pixel Sensors with point-like collection diodes

    CERN Document Server

    Deveaux, M; Dorokhov, A; Doering, D; Heymes, J; Kachel, M; Koziel, M; Linnik, B; Müntz, C; Stroth, J

    2016-01-01

    CMOS Monolithic Active Pixel Sensors for charged particle tracking are considered as technology for numerous experiments in heavy ion and particle physics. To match the requirements for those applications in terms of tolerance to non-ionizing radiation, it is being tried to deplete the sensitive volume of the, traditionally non-depleted, silicon sensors. We study the feasibility of this approach for the common case that the collection diodes of the pixel are small as compared to the pixel pitch. An analytic equation predicting the thickness of the depletion depth and the capacity of this point-like junction is introduced. We find that the predictions of this equations differs qualitatively from the usual results for flat PN junctions and that $dC/dU$-measurements are not suited to measure the depletion depth of diodes with point-like geometry. The predictions of the equation is compared with measurements on the depletion depth of CMOS sensors, which were carried out with a novel measurement protocol. It is fo...

  13. Testbeam results of irradiated ams H18 HV-CMOS pixel sensor prototypes

    CERN Document Server

    INSPIRE-00211411; Braccini, S.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F.A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Kiehn, M.; Lanni, F.; Liu, H.; Meng, L.; Merlassino, C.; Miucci, A.; Muenstermann, D.; Nessi, M.; Okawa, H.; Peric, I.; Rimoldi, M.; Ristic, B.; Vicente Barrero Pinto, M.; Vossebeld, J.; Weber, M.; Weston, T.; Wu, W.; Xu, L.; Zaffaroni, E.

    2016-01-01

    HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the $4^{\\mathrm{th}}$ generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between $1\\cdot 10^{14}$ and $5\\cdot 10^{15}$ 1-MeV-n$_\\textrm{eq}$/cm$^2$. The sensors were glued to ATLAS FE-I4 pixel readout chips and measured at the CERN SPS H8 beamline using the FE-I4 beam telescope. Results for all fluences are very encouraging with all hit efficiencies being better than 97% for bias voltages of $85\\,$V. The sample irradiated to a fluence of $1\\cdot 10^{15}$ n$_\\textrm{eq}$/cm$^2$ - a relevant value for a large volume of the upgraded tracker - exhibited 99.7% average hit ...

  14. A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

    Directory of Open Access Journals (Sweden)

    Chang-Hung Lee

    2014-05-01

    Full Text Available A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

  15. CMOS pixel sensors on high resistive substrate for high-rate, high-radiation environments

    Science.gov (United States)

    Hirono, Toko; Barbero, Marlon; Breugnon, Patrick; Godiot, Stephanie; Gonella, Laura; Hemperek, Tomasz; Hügging, Fabian; Krüger, Hans; Liu, Jian; Pangaud, Patrick; Peric, Ivan; Pohl, David-Leon; Rozanov, Alexandre; Rymaszewski, Piotr; Wang, Anqing; Wermes, Norbert

    2016-09-01

    A depleted CMOS active pixel sensor (DMAPS) has been developed on a substrate with high resistivity in a high voltage process. High radiation tolerance and high time resolution can be expected because of the charge collection by drift. A prototype of DMAPS was fabricated in a 150 nm process by LFoundry. Two variants of the pixel layout were tested, and the measured depletion depths of the variants are 166 μm and 80 μm. We report the results obtained with the prototype fabricated in this technology.

  16. Prototype Active Silicon Sensor in 150 nm HR-CMOS Technology for ATLAS Inner Detector Upgrade

    CERN Document Server

    Rymaszewski, Piotr; Breugnon, Patrick; Godiot, Stépahnie; Gonella, Laura; Hemperek, Tomasz; Hirono, Toko; Hügging, Fabian; Krüger, Hans; Liu, Jian; Pangaud, Patrick; Peric, Ivan; Rozanov, Alexandre; Wang, Anqing; Wermes, Norbert

    2016-01-01

    The LHC Phase-II upgrade will lead to a significant increase in luminosity, which in turn will bring new challenges for the operation of inner tracking detectors. A possible solution is to use active silicon sensors, taking advantage of commercial CMOS technologies. Currently ATLAS R&D programme is qualifying a few commercial technologies in terms of suitability for this task. In this paper a prototype designed in one of them (LFoundry 150 nm process) will be discussed. The chip architecture will be described, including different pixel types incorporated into the design, followed by simulation and measurement results.

  17. CMOS pixel sensors on high resistive substrate for high-rate, high-radiation environments

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko, E-mail: thirono@uni-bonn.de [Physikalisches Institute der Universität Bonn, Bonn (Germany); Barbero, Marlon; Breugnon, Patrick; Godiot, Stephanie [CPPM, Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Gonella, Laura; Hemperek, Tomasz; Hügging, Fabian; Krüger, Hans [Physikalisches Institute der Universität Bonn, Bonn (Germany); Liu, Jian; Pangaud, Patrick [CPPM, Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Peric, Ivan [IPE, Karlsruher Institut für Technologie, Karlsruhe (Germany); Pohl, David-Leon [Physikalisches Institute der Universität Bonn, Bonn (Germany); Rozanov, Alexandre [CPPM, Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Rymaszewski, Piotr [Physikalisches Institute der Universität Bonn, Bonn (Germany); Wang, Anqing [CPPM, Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Wermes, Norbert [Physikalisches Institute der Universität Bonn, Bonn (Germany)

    2016-09-21

    A depleted CMOS active pixel sensor (DMAPS) has been developed on a substrate with high resistivity in a high voltage process. High radiation tolerance and high time resolution can be expected because of the charge collection by drift. A prototype of DMAPS was fabricated in a 150 nm process by LFoundry. Two variants of the pixel layout were tested, and the measured depletion depths of the variants are 166 μm and 80 μm. We report the results obtained with the prototype fabricated in this technology.

  18. CMOS pixel sensor response to low energy electrons in transmission electron microscopy

    Energy Technology Data Exchange (ETDEWEB)

    Battaglia, Marco [Department of Physics, University of California at Berkeley, CA 94720 (United States); Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)], E-mail: MBattaglia@lbl.gov; Contarato, Devis; Denes, Peter; Doering, Dionisio; Radmilovic, Velimir [Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)

    2009-07-01

    This letter presents the results of a study of the response of a test CMOS sensor with a radiation tolerant pixel cell design to 80 and 100 keV electrons. The point spread function is measured to be (13.0{+-}1.7){mu}m at 100 keV and (12.1{+-}1.6){mu}m at 80 keV, for 20{mu}m pixels. Results agree well with values predicted by a Geant-4 and dedicated charge collection simulation.

  19. CMOS time-resolved, contact, and multispectral fluorescence imaging for DNA molecular diagnostics.

    Science.gov (United States)

    Guo, Nan; Cheung, Kawai; Wong, Hiu Tong; Ho, Derek

    2014-10-31

    Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA) detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS) technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

  20. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    Directory of Open Access Journals (Sweden)

    Nan Guo

    2014-10-01

    Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

  1. Real-time imaging of microparticles and living cells with CMOS nanocapacitor arrays

    Science.gov (United States)

    Laborde, C.; Pittino, F.; Verhoeven, H. A.; Lemay, S. G.; Selmi, L.; Jongsma, M. A.; Widdershoven, F. P.

    2015-09-01

    Platforms that offer massively parallel, label-free biosensing can, in principle, be created by combining all-electrical detection with low-cost integrated circuits. Examples include field-effect transistor arrays, which are used for mapping neuronal signals and sequencing DNA. Despite these successes, however, bioelectronics has so far failed to deliver a broadly applicable biosensing platform. This is due, in part, to the fact that d.c. or low-frequency signals cannot be used to probe beyond the electrical double layer formed by screening salt ions, which means that under physiological conditions the sensing of a target analyte located even a short distance from the sensor (∼1 nm) is severely hampered. Here, we show that high-frequency impedance spectroscopy can be used to detect and image microparticles and living cells under physiological salt conditions. Our assay employs a large-scale, high-density array of nanoelectrodes integrated with CMOS electronics on a single chip and the sensor response depends on the electrical properties of the analyte, allowing impedance-based fingerprinting. With our platform, we image the dynamic attachment and micromotion of BEAS, THP1 and MCF7 cancer cell lines in real time at submicrometre resolution in growth medium, demonstrating the potential of the platform for label/tracer-free high-throughput screening of anti-tumour drug candidates.

  2. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  3. System on chip thermal vacuum sensor based on standard CMOS process

    Institute of Scientific and Technical Information of China (English)

    Li Jinfeng; Tang Zhen'an; Wang Jiaqi

    2009-01-01

    An on-chip microelectromechanical system was fabricated in a 0.5μm standard CMOS process for gas pressure detection. The sensor was based on a micro-hotplate (MHP) and had been integrated with a rail to rail operational amplifier and an 8-bit successive approximation register (SAR) A/D converter. A tungsten resistor was manufactured on the MHP as the sensing element, and the sacrificial layer of the sensor was made from polysilicon and etched by surface-micromachining technology. The operational amplifier was configured to make the sensor operate in constant current mode. A digital bit stream was provided as the system output. The measurement results demonstrate that the gas pressure sensitive range of the vacuum sensor extends from 1 to 105 Pa. In the gas pressure range from 1 to 100 Pa, the sensitivity of the sensor is 0.23 mV/Pa, the linearity is 4.95%, and the hysteresis is 8.69%. The operational amplifier can drive 200 Ω resistors distortionlessly, and the SAR A/D converter achieves a resolution of 7.4 bit with 100 kHz sample rate. The performance of the operational amplifier and the SAR A/D converter meets the requirements of the sensor system.

  4. Systematic study of packaging designs on the performance of CMOS thermoresistive micro calorimetric flow sensors

    Science.gov (United States)

    Xu, Wei; Pan, Liang; Gao, Bo; Chiu, Yi; Xu, Kun; Lee, Yi-Kuen

    2017-08-01

    We systematically study the effect of two packaging configurations for the CMOS thermoresistive micro calorimetric flow (TMCF) sensors: S-type with the sensor chip protrusion-mounted on the flow channel wall and E-type with the sensor chip flush-mounted on the flow channel wall. Although the experimental results indicated that the sensitivity of the S-type was increased by more than 30%; the corresponding flow range as compared to the E-type was dramatically reduced by 60% from 0-11 m s-1 to 0-4.5 m s-1. Comprehensive 2D CFD simulation and in-house developed 3D numerical simulations based on the gas-kinetic scheme were applied to study the flow separation of these two packaging designs with the major parameters. Indeed, the S-type design with the large protrusion would change the local convective heat transfer of the TMCF sensor and dramatically decrease the sensors’ performance. In addition, parametric CFD simulations of the packaging designs provide inspiration to propose a novel general flow regime map (FRM), i.e. normalized protrusion d * versus reduced chip Reynolds number Re*, where the critical boundary curve for the flow separation of TMCF sensors was determined at different channel aspect ratios. The proposed FRM can be a useful guideline for the packaging design and manufacturing of different micro thermal flow sensors.

  5. CMOS Compatible 3-Axis Magnetic Field Sensor using Hall Effect Sensing

    Science.gov (United States)

    Locke, Joshua R.

    The purpose of this study is to design, fabricate and test a CMOS compatible 3-axis Hall effect sensor capable of detecting the earth's magnetic field, with strength's of ˜50 muT. Preliminary testing of N-well Van Der Pauw structures using strong neodymium magnets showed proof of concept for hall voltage sensing, however, poor geometry of the structures led to a high offset voltage. A 1-axis Hall effect sensor was designed, fabricated and tested with a sensitivity of 1.12x10-3 mV/Gauss using the RIT metal gate PMOS process. Poor geometry and insufficient design produced an offset voltage of 0.1238 volts in the 1-axis design; prevented sensing of the earth's magnetic field. The new design features improved geometry for sensing application, improved sensitivity and use the RIT sub-CMOS process. The completed 2-axis device showed an average sensitivity to large magnetic fields of 0.0258 muV/Gauss at 10 mA supply current.

  6. e2v CMOS and CCD sensors and systems for astronomy

    Science.gov (United States)

    Jorden, P. R.; Jerram, P. A.; Fryer, M.; Stefanov, K. D.

    2017-07-01

    e2v designs and manufactures a wide range of sensors for space and astronomy applications. This includes high performance CCDs for X-ray, visible and near-IR wavelengths. In this paper we illustrate the maturity of CMOS capability for these applications; examples are presented together with performance data. The majority of e2v sensors for these applications are back-thinned for highest spectral response and designed for very low read-out noise; the combination delivers high signal to noise ratio in association with a variety of formats and package designs. The growing e2v capability in delivery of sub-systems and cryogenic cameras is illustrated—including the 1.2 Giga-pixel J-PAS camera system.

  7. An integrated low 1/f noise and high-sensitivity CMOS instrumentation amplifier for TMR sensors

    Science.gov (United States)

    Gao, Zhiqiang; Luan, Bo; Zhao, Jincai; Liu, Xiaowei

    2017-03-01

    In this paper, a very low 1/f noise integrated Wheatstone bridge magnetoresistive sensor ASIC based on magnetic tunnel junction (MTJ) technology is presented for high sensitivity measurements. The present CMOS instrumentation amplifier employs the gain-boost folded-cascode structure based on the capacitive-feedback chopper-stabilized technique. By chopping both the input and the output of the amplifier, combined with MTJ magnetoresistive sensitive elements, a noise equivalent magnetoresistance 1 nT/Hz1/2 at 2 Hz, the equivalent input noise spectral density 17 nV/Hz1/2(@2Hz) is achieved. The chip-scale package of the TMR sensor and the instrumentation amplifier is only about 5 mm × 5 mm × 1 mm, while the whole DC current dissipates only 2 mA.

  8. Low-cost compact thermal imaging sensors for body temperature measurement

    Science.gov (United States)

    Han, Myung-Soo; Han, Seok Man; Kim, Hyo Jin; Shin, Jae Chul; Ahn, Mi Sook; Kim, Hyung Won; Han, Yong Hee

    2013-06-01

    This paper presents a 32x32 microbolometer thermal imaging sensor for human body temperature measurement. Waferlevel vacuum packaging technology allows us to get a low cost and compact imaging sensor chip. The microbolometer uses V-W-O film as sensing material and ROIC has been designed 0.35-um CMOS process in UMC. A thermal image of a human face and a hand using f/1 lens convinces that it has a potential of human body temperature for commercial use.

  9. Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor

    Science.gov (United States)

    Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

    2013-09-01

    This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

  10. Design of an Embedded CMOS Temperature Sensor for Passive RFID Tag Chips.

    Science.gov (United States)

    Deng, Fangming; He, Yigang; Li, Bing; Zhang, Lihua; Wu, Xiang; Fu, Zhihui; Zuo, Lei

    2015-05-18

    This paper presents an ultra-low embedded power temperature sensor for passive RFID tags. The temperature sensor converts the temperature variation to a PTAT current, which is then transformed into a temperature-controlled frequency. A phase locked loop (PLL)-based sensor interface is employed to directly convert this temperature-controlled frequency into a corresponding digital output without an external reference clock. The fabricated sensor occupies an area of 0.021 mm2 using the TSMC 0.18 1P6M mixed-signal CMOS process. Measurement results of the embedded sensor within the tag system shows a 92 nW power dissipation under 1.0 V supply voltage at room temperature, with a sensing resolution of 0.15 °C/LSB and a sensing accuracy of -0.7/0.6 °C from -30 °C to 70 °C after 1-point calibration at 30 °C.

  11. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

    Directory of Open Access Journals (Sweden)

    Chun-Chi Chen

    2016-01-01

    Full Text Available This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs. Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI system.

  12. All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

    Science.gov (United States)

    Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

    2016-01-30

    This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

  13. Noise Reduction for CFA Image Sensors Exploiting HVS Behaviour

    Directory of Open Access Journals (Sweden)

    Angelo Bosco

    2009-03-01

    Full Text Available This paper presents a spatial noise reduction technique designed to work on CFA (Color Filtering Array data acquired by CCD/CMOS image sensors. The overall processing preserves image details using some heuristics related to the HVS (Human Visual System; estimates of local texture degree and noise levels are computed to regulate the filter smoothing capability. Experimental results confirm the effectiveness of the proposed technique. The method is also suitable for implementation in low power mobile devices with imaging capabilities such as camera phones and PDAs.

  14. Studies for a 10{mu}s, thin, high resolution CMOS pixel sensor for future vertex detectors

    Energy Technology Data Exchange (ETDEWEB)

    Voutsinas, G. [IPHC/IN2P3/CNRS and Universite de Strasbourg, Strasbourg (France); Amar-Youcef, S. [IFK, Goethe-Universitaet, Frankfurt am Main (Germany); Baudot, J.; Bertolone, G.; Brogna, A.; Chon-Sen, N.; Claus, G.; Colledani, C.; Dorokhov, A.; Doziere, G.; Dulinski, W. [IPHC/IN2P3/CNRS and Universite de Strasbourg, Strasbourg (France); Degerli, Y. [IRFU / SEDI (CEA) Saclay (France); De Masi, R. [IPHC/IN2P3/CNRS and Universite de Strasbourg, Strasbourg (France); Deveaux, M. [IFK, Goethe-Universitaet, Frankfurt am Main (Germany); Gelin, M.; Goffe, M.; Hu-Guo, Ch.; Himmi, A.; Jaaskelainen, K.; Koziel, M. [IPHC/IN2P3/CNRS and Universite de Strasbourg, Strasbourg (France)

    2011-06-15

    Future high energy physics (HEP) experiments require detectors with unprecedented performances for track and vertex reconstruction. These requirements call for high precision sensors, with low material budget and short integration time. The development of CMOS sensors for HEP applications was initiated at IPHC Strasbourg more than 10 years ago, motivated by the needs for vertex detectors at the International Linear Collider (ILC) [R. Turchetta et al, NIM A 458 (2001) 677]. Since then several other applications emerged. The first real scale digital CMOS sensor MIMOSA26 equips Flavour Tracker at RHIC, as well as for the microvertex detector of the CBM experiment at FAIR. MIMOSA sensors may also offer attractive performances for the ALICE upgrade at LHC. This paper will demonstrate the substantial performance improvement of CMOS sensors based on a high resistivity epitaxial layer. First studies for integrating the sensors into a detector system will be addressed and finally the way to go to a 10{mu}s readout sensor will be discussed.

  15. Development of fast and high throughput tomography using CMOS image detector at SPring-8

    Science.gov (United States)

    Uesugi, Kentaro; Hoshino, Masato; Takeuchi, Akihisa; Suzuki, Yoshio; Yagi, Naoto

    2012-10-01

    A fast micro-tomography system and a high throughput micro-tomography system using state-of-the-art Complementary Metal Oxide Semiconductor (CMOS) imaging devices have been developed at SPring-8. Those systems adopt simple projection type tomography using synchrotron radiation X-ray. The fast micro-tomography system achieves a scan time around 2 s with 1000 projections, which is 15 times faster than previously developed system at SPring-8. The CMOS camera for fast tomography has 64 Giga Byte on-board memory, therefore, the obtained images must be transferred to a PC at the appropriate timing. A melting process of snow at room temperature was imaged every 30 s as a demonstration of the system. The high throughput tomography system adopts a scientific CMOS (sCMOS) camera with a low noise and high quantum efficiency. The system achieves a scan time around 5 minutes which is three times faster than before. The images quality of the system has been compared to the existing system with Charge-Coupled Device (CCD) camera. The results have shown the advantage of the new sCMOS camera.

  16. Active pixel sensors in AMS H18/H35 HV-CMOS technology for the ATLAS HL-LHC upgrade

    Science.gov (United States)

    Ristic, Branislav

    2016-09-01

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement signal processing electronics in deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150 V leading to a depletion depth of several 10 μm. Prototype sensors in the AMS H18 180 nm and H35 350 nm HV-CMOS processes were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiations with X-rays and protons revealed a tolerance to ionizing doses of 1 Grad while Edge-TCT studies assessed the effects of radiation on the charge collection. The sensors showed high detection efficiencies after neutron irradiation to 1015neq cm-2 in testbeam experiments. A full reticle size demonstrator chip, implemented in the H35 process is being submitted to prove the large scale feasibility of the HV-CMOS concept.

  17. Method for implementation of back-illuminated CMOS or CCD imagers

    Science.gov (United States)

    Pain, Bedabrata (Inventor)

    2008-01-01

    A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

  18. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Drago Strle

    2015-07-01

    Full Text Available This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC. The DSP is currently implemented on FPGA.

  19. Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

    Science.gov (United States)

    Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

    2015-01-01

    This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

  20. A low-power CMOS smart temperature sensor for RFID application

    Science.gov (United States)

    Liangbo, Xie; Jiaxin, Liu; Yao, Wang; Guangjun, Wen

    2014-11-01

    This paper presents the design and implement of a CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC). The analog front-end generates a proportional-to-absolute-temperature (PTAT) voltage with MOSFET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 μm CMOS technology, measurement results show that the temperature error is -0.69/+0.85 °C after one-point calibration over a temperature range of -40 to 100 °C. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 μW while the chip area is 230 × 225 μm2, and it is suitable for RFID application.

  1. A low-power CMOS smart temperature sensor for RFID application

    Institute of Scientific and Technical Information of China (English)

    Xie Liangbo; Liu Jiaxin; Wang Yao; Wen Guangjun

    2014-01-01

    This paper presents the design and implement ofa CMOS smart temperature sensor,which consists of a low power analog front-end and a 12-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC).The analog front-end generates a proportional-to-absolute-temperature (PTAT) voltage with MOSFET circuits operating in the sub-threshold region.A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage.Using 0.18 μm CMOS technology,measurement results show that the temperature error is-0.69/+0.85 ℃ after one-point calibration over a temperature range of-40 to 100 ℃.Under a conversion speed of 1K samples/s,the power consumption is only 2.02μW while the chip area is 230 × 225 μm2,and it is suitable for RFID application.

  2. M.i.p. detection performances of a 100 us read-out CMOS pixel sensor with digitised outputs

    CERN Document Server

    Winter, Marc; Besson, Auguste; Colledani, Claude; Degerli, Yavuz; De Masi, Rita; Dorokhov, Andrei; Doziere, Guy; Dulinski, Wojciech; Gelin, Marie; Guilloux, Fabrice; Himmi, Abdelkader; Hu-Guo, Christine; Morel, Frederic; Orsini, Fabienne; Valin, Isabelle; Voutsinas, Georgios

    2009-01-01

    Swift, high resolution CMOS pixel sensors are being developed for the ILC vertex detector, aiming to allow approaching the interaction point very closely. A major issue is the time resolution of the sensors needed to deal with the high occupancy generated by the beam related background. A 128x576 pixel sensor providing digitised outputs at a read-out time of 92.5 us, was fabricated in 2008 within the EU project EUDET, and tested with charged particles at the CERN-SPS. Its prominent performances in terms of noise, detection efficiency versus fake hit rate, spatial resolution and radiation tolerance are overviewed. They validate the sensor architecture.

  3. Characterization of the column-based priority logic readout of Topmetal-II‑ CMOS pixel direct charge sensor

    Science.gov (United States)

    An, M.; Zhang, W.; Xiao, L.; Gao, C.; Chen, C.; Han, M.; Huang, G.; Ji, R.; Li, X.; Liu, J.; Mei, Y.; Pei, H.; Sun, Q.; Sun, X.; Wang, K.; Yang, P.; Zhou, W.

    2017-03-01

    We present the detailed study of the digital readout of Topmetal-II- CMOS pixel direct charge sensor. Topmetal-II- is an integrated sensor with an array of 72×72 pixels each capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through comparators in each pixel with individually adjustable thresholds. The hits are read out via a column-based priority logic structure, retaining both hit location and time information. The in-array column-based priority logic features with a full clock-less circuitry hence there is no continuously running clock distributed in the pixel and matrix logic. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments. We studied the detailed working behavior and performance of this readout, and demonstrated its functional validity and potential in imaging applications.

  4. Vision communications based on LED array and imaging sensor

    Science.gov (United States)

    Yoo, Jong-Ho; Jung, Sung-Yoon

    2012-11-01

    In this paper, we propose a brand new communication concept, called as "vision communication" based on LED array and image sensor. This system consists of LED array as a transmitter and digital device which include image sensor such as CCD and CMOS as receiver. In order to transmit data, the proposed communication scheme simultaneously uses the digital image processing and optical wireless communication scheme. Therefore, the cognitive communication scheme is possible with the help of recognition techniques used in vision system. By increasing data rate, our scheme can use LED array consisting of several multi-spectral LEDs. Because arranged each LED can emit multi-spectral optical signal such as visible, infrared and ultraviolet light, the increase of data rate is possible similar to WDM and MIMO skills used in traditional optical and wireless communications. In addition, this multi-spectral capability also makes it possible to avoid the optical noises in communication environment. In our vision communication scheme, the data packet is composed of Sync. data and information data. Sync. data is used to detect the transmitter area and calibrate the distorted image snapshots obtained by image sensor. By making the optical rate of LED array be same with the frame rate (frames per second) of image sensor, we can decode the information data included in each image snapshot based on image processing and optical wireless communication techniques. Through experiment based on practical test bed system, we confirm the feasibility of the proposed vision communications based on LED array and image sensor.

  5. Establishing imaging sensor specifications for digital still cameras

    Science.gov (United States)

    Kriss, Michael A.

    2007-02-01

    Digital Still Cameras, DSCs, have now displaced conventional still cameras in most markets. The heart of a DSC is thought to be the imaging sensor, be it Full Frame CCD, and Interline CCD, a CMOS sensor or the newer Foveon buried photodiode sensors. There is a strong tendency by consumers to consider only the number of mega-pixels in a camera and not to consider the overall performance of the imaging system, including sharpness, artifact control, noise, color reproduction, exposure latitude and dynamic range. This paper will provide a systematic method to characterize the physical requirements of an imaging sensor and supporting system components based on the desired usage. The analysis is based on two software programs that determine the "sharpness", potential for artifacts, sensor "photographic speed", dynamic range and exposure latitude based on the physical nature of the imaging optics, sensor characteristics (including size of pixels, sensor architecture, noise characteristics, surface states that cause dark current, quantum efficiency, effective MTF, and the intrinsic full well capacity in terms of electrons per square centimeter). Examples will be given for consumer, pro-consumer, and professional camera systems. Where possible, these results will be compared to imaging system currently on the market.

  6. Development of CMOS Pixel Sensors with digital pixel dedicated to future particle physics experiments

    Science.gov (United States)

    Zhao, W.; Wang, T.; Pham, H.; Hu-Guo, C.; Dorokhov, A.; Hu, Y.

    2014-02-01

    Two prototypes of CMOS pixel sensor with in-pixel analog to digital conversion have been developed in a 0.18 μm CIS process. The first design integrates a discriminator into each pixel within an area of 22 × 33 μm2 in order to meet the requirements of the ALICE inner tracking system (ALICE-ITS) upgrade. The second design features 3-bit charge encoding inside a 35 × 35 μm2 pixel which is motivated by the specifications of the outer layers of the ILD vertex detector (ILD-VXD). This work aims to validate the concept of in-pixel digitization which offers higher readout speed, lower power consumption and less dead zone compared with the column-level charge encoding.

  7. Millimeter-wave imaging sensor

    Science.gov (United States)

    Wilson, W. J.; Howard, R. J.; Ibbott, A. C.; Parks, G. S.; Ricketts, W. B.

    1986-01-01

    A scanning 3-mm radiometer system has been built and used on a helicopter to produce moderate-resolution (0.5 deg) images of the ground. This millimeter-wave sensor can be used for a variety of remote-sensing applications and produces images through clouds, smoke, and dust when visual and IR sensors are not usable. The system is described and imaging results are presented.

  8. Color calibration of a CMOS digital camera for mobile imaging

    Science.gov (United States)

    Eliasson, Henrik

    2010-01-01

    As white balance algorithms employed in mobile phone cameras become increasingly sophisticated by using, e.g., elaborate white-point estimation methods, a proper color calibration is necessary. Without such a calibration, the estimation of the light source for a given situation may go wrong, giving rise to large color errors. At the same time, the demands for efficiency in the production environment require the calibration to be as simple as possible. Thus it is important to find the correct balance between image quality and production efficiency requirements. The purpose of this work is to investigate camera color variations using a simple model where the sensor and IR filter are specified in detail. As input to the model, spectral data of the 24-color Macbeth Colorchecker was used. This data was combined with the spectral irradiance of mainly three different light sources: CIE A, D65 and F11. The sensor variations were determined from a very large population from which 6 corner samples were picked out for further analysis. Furthermore, a set of 100 IR filters were picked out and measured. The resulting images generated by the model were then analyzed in the CIELAB space and color errors were calculated using the ΔE94 metric. The results of the analysis show that the maximum deviations from the typical values are small enough to suggest that a white balance calibration is sufficient. Furthermore, it is also demonstrated that the color temperature dependence is small enough to justify the use of only one light source in a production environment.

  9. 用于时间延迟积分型图像传感器的流水采样列级运放共享累加器∗%A Pipelined Sampling Accumulator with Opamp Sharing Technique Fit for CMOS TDI Image Sensor

    Institute of Scientific and Technical Information of China (English)

    夏雨; 姚素英; 聂凯明; 徐江涛

    2015-01-01

    提出了一种适用于TDI-CIS(时间延迟积分CMOS图像传感器)的模拟域流水采样列级运放共享累加器结构。提出的这种模拟累加器结构应用流水采样结构在不改变运放速率的前提下,将累加器的速率提升为传统累加器的2倍;采用积分电容列运放共享技术将n级TDI-CIS所需的运放个数减少至采用传统累加器所需个数的1/n。分析了流水采样累加器结构的原理以及输出噪声。使用标准0.18μm CMOS工艺进行了电路设计。仿真结果显示,提出的模拟累加器结构功耗为0.29 mW,采样率为2 Msample/s。结果表明流水采样列级运放共享累加器结构在保持低电路面积和功耗的同时,可将TDI-CIS最大可达到的行频增加一倍,更适于高速扫描的应用环境。%A novel pipelined sampling accumulator structure with opamp sharing technique is presented,which is fit for CMOS TDI( time-delay-integration) image sensor. The sampling speed of the analog accumulator can be doubled with only 1 opamp instead of n opamps for an n-stage accumulator. This structure decreases chip area and power dissipation and increases accumulating speed as well. This paper illustrates the topology of the proposed structure and analyzes the output noise. The proposed circuit is designed in a 0. 18 μm CMOS process. Simulation results show that the power dissipation of the proposed circuit is 0.29 mW under 3.3 V voltage supply,and the sampling rate of the accumulator is 2 Msample/s. It proves that the proposed accumulator structure is suitable to the applica-tion at high scanning speed.

  10. An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

    Science.gov (United States)

    DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

    2016-01-01

    This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

  11. Effect and suppression of parasitic surface damage in neutron irradiated CMOS Monolithic Active Pixel Sensors

    CERN Document Server

    Deveaux, M; Scharrer, P; Stroth, J

    2016-01-01

    CMOS Monolithic Active Pixel Sensors (MAPS) were chosen as sensor technology for the vertex detectors of STAR, CBM and the upgraded ALICE-ITS. They also constitute a valuable option for tracking devices at future e+e- colliders. Those applications require a substantial tolerance to both, ionizing and non-ionizing radiation. To allow for a focused optimization of the radiation tolerance, prototypes are tested by irradiating the devices either with purely ionizing radiation (e.g. soft X-rays) or the most pure sources of non-ionizing radiation available (e.g. reactor neutrons). In the second case, it is typically assumed that the impact of the parasitic $\\gamma$-rays found in the neutron beams is negligible. We checked this assumption by irradiating MAPS with $\\gamma$-rays and comparing the radiation damage generated with the one in neutron irradiated sensors. We conclude that the parasitic radiation doses may cause non-negligible radiation damage. Based on the results we propose a procedure to recognize and to ...

  12. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

    Directory of Open Access Journals (Sweden)

    Haiyun Huang

    2015-10-01

    Full Text Available This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

  13. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics

    Science.gov (United States)

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-01-01

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW. PMID:26516864

  14. An Autonomous Wireless Sensor Node With Asynchronous ECG Monitoring in 0.18 μ m CMOS.

    Science.gov (United States)

    Mansano, Andre L; Li, Yongjia; Bagga, Sumit; Serdijn, Wouter A

    2016-06-01

    The design of a 13.56 MHz/402 MHz autonomous wireless sensor node with asynchronous ECG monitoring for near field communication is presented. The sensor node consists of an RF energy harvester (RFEH), a power management unit, an ECG readout, a data encoder and an RF backscattering transmitter. The energy harvester supplies the system with 1.25 V and offers a power conversion efficiency of 19% from a -13 dBm RF source at 13.56 MHz. The power management unit regulates the output voltage of the RFEH to supply the ECG readout with VECG = 0.95 V and the data encoder with VDE = 0.65 V . The ECG readout comprises an analog front-end (low noise amplifier and programmable voltage to current converter) and an asynchronous level crossing ADC with 8 bits resolution. The ADC output is encoded by a pulse generator that drives a backscattering transmitter at 402 MHz. The total power consumption of the sensor node circuitry is 9.7 μ W for a data rate of 90 kb/s and a heart rate of 70 bpm. The chip has been designed in a 0.18 μm CMOS process and shows superior RF input power sensitivity and lower power consumption when compared to previous works.

  15. Autonomous vision networking: miniature wireless sensor networks with imaging technology

    Science.gov (United States)

    Messinger, Gioia; Goldberg, Giora

    2006-09-01

    The recent emergence of integrated PicoRadio technology, the rise of low power, low cost, System-On-Chip (SOC) CMOS imagers, coupled with the fast evolution of networking protocols and digital signal processing (DSP), created a unique opportunity to achieve the goal of deploying large-scale, low cost, intelligent, ultra-low power distributed wireless sensor networks for the visualization of the environment. Of all sensors, vision is the most desired, but its applications in distributed sensor networks have been elusive so far. Not any more. The practicality and viability of ultra-low power vision networking has been proven and its applications are countless, from security, and chemical analysis to industrial monitoring, asset tracking and visual recognition, vision networking represents a truly disruptive technology applicable to many industries. The presentation discusses some of the critical components and technologies necessary to make these networks and products affordable and ubiquitous - specifically PicoRadios, CMOS imagers, imaging DSP, networking and overall wireless sensor network (WSN) system concepts. The paradigm shift, from large, centralized and expensive sensor platforms, to small, low cost, distributed, sensor networks, is possible due to the emergence and convergence of a few innovative technologies. Avaak has developed a vision network that is aided by other sensors such as motion, acoustic and magnetic, and plans to deploy it for use in military and commercial applications. In comparison to other sensors, imagers produce large data files that require pre-processing and a certain level of compression before these are transmitted to a network server, in order to minimize the load on the network. Some of the most innovative chemical detectors currently in development are based on sensors that change color or pattern in the presence of the desired analytes. These changes are easily recorded and analyzed by a CMOS imager and an on-board DSP processor

  16. Multichannel lens-free CMOS sensors for real-time monitoring of cell growth.

    Science.gov (United States)

    Chang, Ko-Tung; Chang, Yu-Jen; Chen, Chia-Ling; Wang, Yao-Nan

    2015-02-01

    A low-cost platform is proposed for the growth and real-time monitoring of biological cells. The main components of the platform include a PMMA cell culture microchip and a multichannel lens-free CMOS (complementary metal-oxide-semiconductor) / LED imaging system. The PMMA microchip comprises a three-layer structure and is fabricated using a low-cost CO2 laser ablation technique. The CMOS / LED monitoring system is controlled using a self-written LabVIEW program. The platform has overall dimensions of just 130 × 104 × 115 mm(3) and can therefore be placed within a commercial incubator. The feasibility of the proposed system is demonstrated using HepG2 cancer cell samples with concentrations of 5000, 10 000, 20 000, and 40 000 cells/mL. In addition, cell cytotoxicity tests are performed using 8, 16, and 32 mM cyclophosphamide. For all of the experiments, the cell growth is observed over a period of 48 h. The cell growth rate is found to vary in the range of 44∼52% under normal conditions and from 17.4∼34.5% under cyclophosphamide-treated conditions. In general, the results confirm the long-term cell growth and real-time monitoring ability of the proposed system. Moreover, the magnification provided by the lens-free CMOS / LED observation system is around 40× that provided by a traditional microscope. Consequently, the proposed system has significant potential for long-term cell proliferation and cytotoxicity evaluation investigations.

  17. Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Ristic, Branislav

    2016-01-01

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

  18. Compact characterization of liquid absorption and emission spectra using linear variable filters integrated with a CMOS imaging camera

    Science.gov (United States)

    Wan, Yuhang; Carlson, John A.; Kesler, Benjamin A.; Peng, Wang; Su, Patrick; Al-Mulla, Saoud A.; Lim, Sung Jun; Smith, Andrew M.; Dallesasse, John M.; Cunningham, Brian T.

    2016-07-01

    A compact analysis platform for detecting liquid absorption and emission spectra using a set of optical linear variable filters atop a CMOS image sensor is presented. The working spectral range of the analysis platform can be extended without a reduction in spectral resolution by utilizing multiple linear variable filters with different wavelength ranges on the same CMOS sensor. With optical setup reconfiguration, its capability to measure both absorption and fluorescence emission is demonstrated. Quantitative detection of fluorescence emission down to 0.28 nM for quantum dot dispersions and 32 ng/mL for near-infrared dyes has been demonstrated on a single platform over a wide spectral range, as well as an absorption-based water quality test, showing the versatility of the system across liquid solutions for different emission and absorption bands. Comparison with a commercially available portable spectrometer and an optical spectrum analyzer shows our system has an improved signal-to-noise ratio and acceptable spectral resolution for discrimination of emission spectra, and characterization of colored liquid’s absorption characteristics generated by common biomolecular assays. This simple, compact, and versatile analysis platform demonstrates a path towards an integrated optical device that can be utilized for a wide variety of applications in point-of-use testing and point-of-care diagnostics.

  19. Image stacking approach to increase sensitivity of fluorescence detection using a low cost complementary metal-oxide-semiconductor (CMOS) webcam.

    Science.gov (United States)

    Balsam, Joshua; Bruck, Hugh Alan; Kostov, Yordan; Rasooly, Avraham

    2012-01-01

    Optical technologies are important for biological analysis. Current biomedical optical analyses rely on high-cost, high-sensitivity optical detectors such as photomultipliers, avalanched photodiodes or cooled CCD cameras. In contrast, Webcams, mobile phones and other popular consumer electronics use lower-sensitivity, lower-cost optical components such as photodiodes or CMOS sensors. In order for consumer electronics devices, such as webcams, to be useful for biomedical analysis, they must have increased sensitivity. We combined two strategies to increase the sensitivity of CMOS-based fluorescence detector. We captured hundreds of low sensitivity images using a Webcam in video mode, instead of a single image typically used in cooled CCD devices.We then used a computational approach consisting of an image stacking algorithm to remove the noise by combining all of the images into a single image. While video mode is widely used for dynamic scene imaging (e.g. movies or time-lapse photography), it is not used to capture a single static image, which removes noise and increases sensitivity by more than thirty fold. The portable, battery-operated Webcam-based fluorometer system developed here consists of five modules: (1) a low cost CMOS Webcam to monitor light emission, (2) a plate to perform assays, (3) filters and multi-wavelength LED illuminator for fluorophore excitation, (4) a portable computer to acquire and analyze images, and (5) image stacking software for image enhancement. The samples consisted of various concentrations of fluorescein, ranging from 30 μM to 1000 μM, in a 36-well miniature plate. In the single frame mode, the fluorometer's limit-of-detection (LOD) for fluorescein is ∼1000 μM, which is relatively insensitive. However, when used in video mode combined with image stacking enhancement, the LOD is dramatically reduced to 30 μM, sensitivity which is similar to that of state-of-the-art ELISA plate photomultiplier-based readers. Numerous medical

  20. Performance and Stress Analysis of Metal Oxide Films for CMOS-Integrated Gas Sensors

    Directory of Open Access Journals (Sweden)

    Lado Filipovic

    2015-03-01

    Full Text Available The integration of gas sensor components into smart phones, tablets and wrist watches will revolutionize the environmental health and safety industry by providing individuals the ability to detect harmful chemicals and pollutants in the environment using always-on hand-held or wearable devices. Metal oxide gas sensors rely on changes in their electrical conductance due to the interaction of the oxide with a surrounding gas. These sensors have been extensively studied in the hopes that they will provide full gas sensing functionality with CMOS integrability. The performance of several metal oxide materials, such as tin oxide (SnO2, zinc oxide (ZnO, indium oxide (In2O3 and indium-tin-oxide (ITO, are studied for the detection of various harmful or toxic cases. Due to the need for these films to be heated to temperatures between 250°C and 550°C during operation in order to increase their sensing functionality, a considerable degradation of the film can result. The stress generation during thin film deposition and the thermo-mechanical stress that arises during post-deposition cooling is analyzed through simulations. A tin oxide thin film is deposited using the efficient and economical spray pyrolysis technique, which involves three steps: the atomization of the precursor solution, the transport of the aerosol droplets towards the wafer and the decomposition of the precursor at or near the substrate resulting in film growth. The details of this technique and a simulation methodology are presented. The dependence of the deposition technique on the sensor performance is also discussed.

  1. Performance and stress analysis of metal oxide films for CMOS-integrated gas sensors.

    Science.gov (United States)

    Filipovic, Lado; Selberherr, Siegfried

    2015-03-25

    The integration of gas sensor components into smart phones, tablets and wrist watches will revolutionize the environmental health and safety industry by providing individuals the ability to detect harmful chemicals and pollutants in the environment using always-on hand-held or wearable devices. Metal oxide gas sensors rely on changes in their electrical conductance due to the interaction of the oxide with a surrounding gas. These sensors have been extensively studied in the hopes that they will provide full gas sensing functionality with CMOS integrability. The performance of several metal oxide materials, such as tin oxide (SnO2), zinc oxide (ZnO), indium oxide (In2O3) and indium-tin-oxide (ITO), are studied for the detection of various harmful or toxic cases. Due to the need for these films to be heated to temperatures between 250°C and 550°C during operation in order to increase their sensing functionality, a considerable degradation of the film can result. The stress generation during thin film deposition and the thermo-mechanical stress that arises during post-deposition cooling is analyzed through simulations. A tin oxide thin film is deposited using the efficient and economical spray pyrolysis technique, which involves three steps: the atomization of the precursor solution, the transport of the aerosol droplets towards the wafer and the decomposition of the precursor at or near the substrate resulting in film growth. The details of this technique and a simulation methodology are presented. The dependence of the deposition technique on the sensor performance is also discussed.

  2. Improved Design of Active Pixel CMOS Sensors for Charged Particle Detection

    Energy Technology Data Exchange (ETDEWEB)

    Deptuch, Grzegorz

    2007-11-12

    The Department of Energy (DOE) nuclear physics program requires developments in detector instrumentation electronics with improved energy, position and timing resolution, sensitivity, rate capability, stability, dynamic range, and background suppression. The current Phase-I project was focused on analysis of standard-CMOS photogate Active Pixel Sensors (APS) as an efficient solution to this challenge. The advantages of the CMOS APS over traditional hybrid approaches (i.e., separate detection regions bump-bonded to readout circuits) include greatly reduced cost, low power and the potential for vastly larger pixel counts and densities. However, challenges remain in terms of the signal-to-noise ratio (SNR) and readout speed (currently on the order of milliseconds), which is the major problem for this technology. Recent work has shown that the long readout time for photogate APS is due to the presence of (interface) traps at the semiconductor-oxide interface. This Phase-I work yielded useful results in two areas: (a) Advanced three-dimensional (3D) physics-based simulation models and simulation-based analysis of the impact of interface trap density on the transient charge collection characteristics of existing APS structures; and (b) Preliminary analysis of the feasibility of an improved photogate pixel structure (i.e., new APS design) with an induced electric field under the charge collecting electrode to enhance charge collection. Significant effort was dedicated in Phase-I to the critical task of implementing accurate interface trap models in CFDRC's NanoTCAD 3D semiconductor device-physics simulator. This resulted in validation of the new NanoTCAD models and simulation results against experimental (published) data, within the margin of uncertainty associated with obtaining device geometry, material properties, and experimentation details. Analyses of the new, proposed photogate APS design demonstrated several promising trends.

  3. Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

    Science.gov (United States)

    Liu, Mao-Chen; Dai, Ching-Liang; Chan, Chih-Hua; Wu, Chyan-Chyi

    2009-01-01

    This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature. PMID:22399944

  4. Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

    Directory of Open Access Journals (Sweden)

    Chyan-Chyi Wu

    2009-02-01

    Full Text Available This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature

  5. Micro Ethanol Sensors with a Heater Fabricated Using the Commercial 0.18 μm CMOS Process

    Directory of Open Access Journals (Sweden)

    Wei-Zhen Liao

    2013-09-01

    Full Text Available The study investigates the fabrication and characterization of an ethanol microsensor equipped with a heater. The ethanol sensor is manufactured using the commercial 0.18 µm complementary metal oxide semiconductor (CMOS process. The sensor consists of a sensitive film, a heater and interdigitated electrodes. The sensitive film is zinc oxide prepared by the sol-gel method, and it is coated on the interdigitated electrodes. The heater is located under the interdigitated electrodes, and it is used to supply a working temperature to the sensitive film. The sensor needs a post-processing step to remove the sacrificial oxide layer, and to coat zinc oxide on the interdigitated electrodes. When the sensitive film senses ethanol gas, the resistance of the sensor generates a change. An inverting amplifier circuit is utilized to convert the resistance variation of the sensor into the output voltage. Experiments show that the sensitivity of the ethanol sensor is 0.35 mV/ppm.

  6. Development of a novel pixel-level signal processing chain for fast readout 3D integrated CMOS pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Y.; Torheim, O.; Hu-Guo, C. [Institut Pluridisciplinaire Hubert Curien (IPHC), 23 rue du loess, BP 28, 67037 Strasbourg (France); Degerli, Y. [CEA Saclay, IRFU/SEDI, 91191 Gif-sur-Yvette Cedex (France); Hu, Y., E-mail: yann.hu@iphc.cnrs.fr [Institut Pluridisciplinaire Hubert Curien (IPHC), 23 rue du loess, BP 28, 67037 Strasbourg (France)

    2013-03-11

    In order to resolve the inherent readout speed limitation of traditional 2D CMOS pixel sensors, operated in rolling shutter readout, a parallel readout architecture has been developed by taking advantage of 3D integration technologies. Since the rows of the pixel array are zero-suppressed simultaneously instead of sequentially, a frame readout time of a few microseconds is expected for coping with high hit rates foreseen in future collider experiments. In order to demonstrate the pixel readout functionality of such a pixel sensor, a 2D proof-of-concept chip including a novel pixel-level signal processing chain was designed and fabricated in a 0.13μm CMOS technology. The functionalities of this chip have been verified through experimental characterization.

  7. Structure for implementation of back-illuminated CMOS or CCD imagers

    Science.gov (United States)

    Pain, Bedabrata (Inventor); Cunningham, Thomas J. (Inventor)

    2009-01-01

    A structure for implementation of back-illuminated CMOS or CCD imagers. An epitaxial silicon layer is connected with a passivation layer, acting as a junction anode. The epitaxial silicon layer converts light passing through the passivation layer and collected by the imaging structure to photoelectrons. A semiconductor well is also provided, located opposite the passivation layer with respect to the epitaxial silicon layer, acting as a junction cathode. Prior to detection, light does not pass through a dielectric separating interconnection metal layers.

  8. Signal and noise transfer properties of CMOS based active pixel flat panel imager coupled to structured CsI:Tl.

    Science.gov (United States)

    Arvanitis, C D; Bohndiek, S E; Blakesley, J; Olivo, A; Speller, R D

    2009-01-01

    Complementary metal-oxide-semiconductors (CMOS) active pixel sensors can be optically coupled to CsI:Tl phosphors forming a indirect active pixel flat panel imager (APFPI) for high performance medical imaging. The aim of this work is to determine the x-ray imaging capabilities of CMOS-based APFPI and study the signal and noise transfer properties of CsI:Tl phosphors. Three different CsI:Tl phosphors from two different vendors have been used to produce three system configurations. The performance of each system configuration has been studied in terms of the modulation transfer function (MTF), noise power spectra, and detective quantum efficiency (DQE) in the mammographic energy range. A simple method to determine quantum limited systems in this energy range is also presented. In addition, with aid of monochromatic synchrotron radiation, the effect of iodine characteristic x-rays of the CsI:Tl on the MTF has been determined. A Monte Carlo simulation of the signal transfer properties of the imager is also presented in order to study the stages that degrade the spatial resolution of our current system. The effect of using substrate patterning during the growth of CsI:Tl columnar structure was also studied, along with the effect of CsI:Tl fixed pattern noise due to local variations in the scintillation light. CsI:Tl fixed pattern noise appears to limit the performance of our current system configurations. All the system configurations are quantum limited at 0.23 microC/kg with two of them having DQE (0) equal to 0.57. Active pixel flat panel imagers are shown to be digital x-ray imagers with almost constant DQE throughout a significant part of their dynamic range and in particular at very low exposures.

  9. Design of star sensor imaging driver module based on IMX224

    Science.gov (United States)

    Ye, Zunzong; Wei, Xinguo; Wang, Gangyi

    2017-03-01

    This paper introduces the design and implementation of a high sensitivity star sensor imaging driver module. The high sensitivity CMOS imaging chip IMX224 was used. It can capture high resolution color image in 0.005 lux in low light conditions. Using FPGA embedded ARM core to design and control the entire driver module to achieve the imaging driver acquisition and storage. Finally, through the actual field observing experiments, the experimental results show that the detection ability of magnitude of the high sensitivity star sensor imaging driver module can meet the design requirements.

  10. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  11. Characterization of the C-MOS Cd-Te Imager PIXIRAD for energy discriminated X-ray imaging

    Science.gov (United States)

    Romano, A.; Pacella, D.; Claps, G.; Causa, F.; Gabellieri, L.

    2015-02-01

    The aim of the present work is to assess the operational characteristics of the PIXIRAD Imaging Counter for use in high-definition energy resolved X-ray imaging for different applications. The PIXIRAD imager was developed by an INFN-Pisa Spin-off. It works in photon counting mode in a wide energy range, soft and hard X-rays (2-100 keV), with pulse discrimination defined by two thresholds. The 650 μ m thick CdTe X-ray sensor is interfaced with a CMOS VLSI chip organized on a 512× 476 matrix of 55 μ m exagonal pixels (total active area of 30.7× 24.8 mm2). The experimental characterization was carried out in the range 3.7-80 keV, to assess the energy discrimination capability and detection efficiency of the PIXIRAD. Energy discrimination in bands was investigated using calibrated monochromatic X-ray sources (fluorescence of Ca, Fe, Cu, Br, Mo, Ag, I, Ta) and a BaCs radioactive source. In addition, two absolutely calibrated X-ray sources (Moxtek 50 kV Bullet and Oxford Instruments SB-80-1M) were utilized. The experimental data show that the PIXIRAD energy response is linear up to about 15 keV, beyond which the cluster size becomes larger than the pixel dimension. It produces multiple counts resulting in a tail at lower energy. Energy resolution was estimated to be about 30%. The effects in term of energy discrimination and a ``smooth energy discrimination'' in bands has been investigated by studying the separation between different energy lines, acquiring combined images with different energy ranges and setting properly the PIXIRAD threshold.

  12. Focal Plane Assembly and Calibrating of CMOS Star Sensor%CMOS星敏感器焦平面装配及标定

    Institute of Scientific and Technical Information of China (English)

    钟兴; 金光; 王栋; 邢飞

    2011-01-01

    Focal plane's misalignment is analyzed theoretically to match the requirement of high precision CMOS star sensor. System for assembly and calibrating measurement of CMOS star sensor is established. Defocusing distance and tilt of detector plane are acquired by on-axis and off-axis star sensor imaging test through collimator's image plane moving. Some CMOS star sensor with 50 mm focal length, F/l .25, and 20° field of view is successfully assembled under direction of testing data. Defocusing distance is less than 0.01 mm, and tilt is less than 2'. Principal distance test and distortion calibration are done with measuring system. Principal distance is calculated to be 49.77 mm, and the error is 0.007 2 mm. Distortion of star sensor system is calibrated by third order polynomial fitting data, and the residual error caused by distortion can be reduced to 6.6" when measuring single star.%针对高精度CMOS星敏感器的使用要求,本文对焦平面装配的误差进行了理论分析,搭建了CMOS星敏感器装配及标定测试系统,利用长焦距平行光管像面移动测量方法进行了星敏感器轴上和轴外的星点成像,获取了焦平面离焦量及倾斜数据.在这些数据指导下,成功完成了对某焦距50 mm,相对孔径1/1.25,全视场20°的CMOS星敏感器的焦平面装配,轴上点离焦小于0.01 mm,倾斜小于2′.对装配后的星敏感器在高精度气浮转台上进行了主距测试和畸变标定,标定计算得到主距为49.77 mm,精度0.007 2 mm.利用三阶多项式拟合的方法对系统畸变进行了修正,修正后的残余畸变对单个星点测量的精度影响可减小到6.6”左右,满足高精度星敏感器的使用要求.

  13. Installation of a TCT set-up for characterization of novel HV-CMOS planar silicon sensors

    CERN Document Server

    Marx, Lisa

    2013-01-01

    For future upgrades of the LHC it is necessary to develop new tracking detectors: more radiation hard and cost efficient pixel detectors with high spacial resolution are required for the planned high luminosity version of the LHC (HL-LHC). For future tracking devices HV-CMOS active pixel sensors are great candidates since they fulfill all the demands mentioned above. First prototypes of these sensors are assembled on custom test boards and together with FE-I4 readout chips they make up the first test pixel detectors. One approach for testing these chips is through using lasers to induce electron-hole-pairs into the depletion zone of the sensor chip diodes to simulate an ionizing particle crossing through the bulk. Comparison measurements of irradiated/non-irradiated sensors are used to explore the radiation hardness of the sensors.

  14. On-chip Phase Locked Loop (PLL) design for clock multiplier in CMOS Monolithic Active Pixel Sensors (MAPS)

    CERN Document Server

    Sun, Q; Valin, I; Claus, G; Hu-Guo, Ch; Hu, Yu

    2009-01-01

    In a detector system, clock distribution to sensors must be controlled at a level allowing proper synchronisation. In order to reach theses requirements for the HFT (Heavy Flavor Tracker) upgrade at STAR (Solenoidal Tracker at RHIC), we have proposed to distribute a low frequency clock at 10 MHz which will be multiplied to 160 MHz in each sensor by a PLL. A PLL has been designed for period jitter less than 20 ps rms, low power consumption and manufactured in a 0.35 μm CMOS process.

  15. Development of CMOS Compatible Humidity Sensor%CMOS兼容湿度传感器的研究进展

    Institute of Scientific and Technical Information of China (English)

    严先蔚; 秦明; 黄庆安

    2001-01-01

    In this paper, we present the design principle and fabrication method of six different CMOS compatible humidity sensors and their measuring circuits. The prospect of the humidity sensor is also discussed.%本文主要介绍几种与CMOS工艺兼容的湿度传感器的结构、工艺、特点以及处理电路,并对湿度传感器的发展趋势作了探讨。

  16. Development of Radiation-hard Bandgap Reference and Temperature Sensor in CMOS 130 nm Technology

    CERN Document Server

    Kuczynska, Marika; Bugiel, Szymon; Firlej, Miroslaw; Fiutowski, Tomasz; Idzik, Marek; Michelis, Stefano; Moron, Jakub; Przyborowski, Dominik; Swientek, Krzysztof

    2015-01-01

    A stable reference voltage (or current) source is a standard component of today's microelectronics systems. In particle physics experiments such reference is needed in spite of harsh ionizing radiation conditions, i.e. doses exceeding 100 Mrads and fluences above 1e15 n/cm2. After such radiation load a bandgap reference using standard p-n junction of bipolar transistor does not work properly. Instead of using standard p-n junctions, two enclosed layout transistor (ELTMOS) structures are used to create radiation-hard diodes: the ELT bulk diode and the diode obtained using the ELTMOS as dynamic threshold transistor (DTMOS). In this paper we have described several sub-1V references based on ELTMOS bulk diode and DTMOS based diode, using CMOS 130 nm process. Voltage references the structures with additional PTAT (Proportional To Absolute Temperature) output for temperature measurements were also designed. We present and compare post-layout simulations of the developed bandgap references and temperature sensors, w...

  17. An optimal design of thermal-actuated and piezoresistive-sensed CMOS-MEMS resonant sensor

    Science.gov (United States)

    Wang, Chun-Chieh; Tsai, Chun-Yin; Chen, Tsung-Lin; Liao, Sin-Hao

    2013-11-01

    This paper proposes an optimal design of the thermal-actuated, piezoresistive-sensed resonator fabricated by a foundry-provided CMOS-MEMS process. The optimal design is achieved both by quantitatively comparing the mechanical properties of different composite films as well as by deriving an analytical model for determining the device dimensions. The analytical model includes a stress model of an asymmetric mechanical structure and a piezoresistivity model of the heavily doped, n-type polysilicon film. The analytical model predicts that the optimal length of the displacement sensor is 200 μm when the thermal actuator is 200 μm in length and the absorption plate is 100 μm in length. Additionally, the model predicts the resistivity of the polysilicon film of (6.8 ± 2.2) mΩ cm and the gauge factor of (6.8 ± 2.9) when the grain size is (250 ± 100) nm. Experimental results agree well with simulation results. Experimental data show that the resonant frequency of the device is 80.06 kHz and shifts to 79.8 kHz when a brick of Pt mass is deposited on the resonator. The mass of the Pt estimated from the frequency shift is 4.5419 × 10-12 kg, while estimated from the measured dimension is 4.4204 × 10-12 kg. Sensitivity of the resonant sensor is calculated to be 1.8 × 102 Hz ng-1. Experimental results further show that the polysilicon film used in the experiments has a grain size of (241 ± 105) nm, an average gauge factor of 5.56 and average resistivity of 5.5 mΩ cm.

  18. Active-Pixel Image Sensor With Analog-To-Digital Converters

    Science.gov (United States)

    Fossum, Eric R.; Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.

    1995-01-01

    Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

  19. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

    Science.gov (United States)

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-09

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  20. Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

    Science.gov (United States)

    Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

    2016-05-01

    Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V‑1 sec‑1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

  1. A data parallel digitizer for a time-based simulation of CMOS Monolithic Active Pixel Sensors with FairRoot

    Science.gov (United States)

    Sitzmann, P.; Amar-Youcef, S.; Doering, D.; Deveaux, M.; Fröhlich, I.; Koziel, M.; Krebs, E.; Linnik, B.; Michel, J.; Milanovic, B.; Müntz, C.; Li, Q.; Stroth, J.; Tischler, T.

    2014-06-01

    CMOS Monolithic Active Pixel Sensors (MAPS) demonstrated excellent performances in the field of charged particle tracking. They feature an excellent single point resolution of few μm, a light material budget of 0.05% Xo in combination with a good radiation tolerance and time resolution. This makes the sensors a valuable technology for micro vertex detectors (MVD) of various experiments in heavy ion and particle physics like STAR and CBM. State of the art MAPS are equipped with a rolling shutter readout. Therefore, the data of one individual event is typically found in more than one data train generated by the sensor. This paper presents a concept to introduce this feature in both simulation and data analysis, taking profit of the sensor topology of the MVD. This topology allows to use for massive parallel data streaming and handling strategies within the FairRoot framework.

  2. A hybrid CMOS-imager with integrated solution-processable organic photodiodes

    OpenAIRE

    Baierl, Daniela

    2013-01-01

    The solution-processability of organic photodetectors allows a straightforward combination with other materials and technologies, including inorganic ones, without increasing cost and process complexity significantly compared to conventional crystalline semiconductors. Present CMOS-imagers exhibit a small pixel fill factor of about 30 % which decreases the light sensitivity significantly. The fill factor can be increased up to 100 % by replacing the silicon photodiodes with an organic ph...

  3. Smart image sensor with adaptive correction of brightness

    Science.gov (United States)

    Paindavoine, Michel; Ngoua, Auguste; Brousse, Olivier; Clerc, Cédric

    2012-03-01

    Today, intelligent image sensors require the integration in the focal plane (or near the focal plane) of complex algorithms for image processing. Such devices must meet the constraints related to the quality of acquired images, speed and performance of embedded processing, as well as low power consumption. To achieve these objectives, analog pre-processing are essential, on the one hand, to improve the quality of the images making them usable whatever the light conditions, and secondly, to detect regions of interest (ROIs) to limit the amount of pixels to be transmitted to a digital processor performing the high-level processing such as feature extraction for pattern recognition. To show that it is possible to implement analog pre-processing in the focal plane, we have designed and implemented in 130nm CMOS technology, a test circuit with groups of 4, 16 and 144 pixels, each incorporating analog average calculations.

  4. Low-Power Smart Imagers for Vision-Enabled Sensor Networks

    CERN Document Server

    Fernández-Berni, Jorge; Rodríguez-Vázquez, Ángel

    2012-01-01

    This book presents a comprehensive, systematic approach to the development of vision system architectures that employ sensory-processing concurrency and parallel processing to meet the autonomy challenges posed by a variety of safety and surveillance applications.  Coverage includes a thorough analysis of resistive diffusion networks embedded within an image sensor array. This analysis supports a systematic approach to the design of spatial image filters and their implementation as vision chips in CMOS technology. The book also addresses system-level considerations pertaining to the embedding of these vision chips into vision-enabled wireless sensor networks.  Describes a system-level approach for designing of vision devices and  embedding them into vision-enabled, wireless sensor networks; Surveys state-of-the-art, vision-enabled WSN nodes; Includes details of specifications and challenges of vision-enabled WSNs; Explains architectures for low-energy CMOS vision chips with embedded, programmable spatial f...

  5. Functional brain fluorescence plurimetry in rat by implantable concatenated CMOS imaging system.

    Science.gov (United States)

    Kobayashi, Takuma; Masuda, Hiroyuki; Kitsumoto, Chikara; Haruta, Makito; Motoyama, Mayumi; Ohta, Yasumi; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Shiosaka, Sadao; Ohta, Jun

    2014-03-15

    Measurement of brain activity in multiple areas simultaneously by minimally invasive methods contributes to the study of neuroscience and development of brain machine interfaces. However, this requires compact wearable instruments that do not inhibit natural movements. Application of optical potentiometry with voltage-sensitive fluorescent dye using an implantable image sensor is also useful. However, the increasing number of leads required for the multiple wired sensors to measure larger domains inhibits natural behavior. For imaging broad areas by numerous sensors without excessive wiring, a web-like sensor that can wrap the brain was developed. Kaleidoscopic potentiometry is possible using the imaging system with concatenated sensors by changing the alignment of the sensors. This paper describes organization of the system, evaluation of the system by a fluorescence imaging, and finally, functional brain fluorescence plurimetry by the sensor. The recorded data in rat somatosensory cortex using the developed multiple-area imaging system compared well with electrophysiology results.

  6. A new subdivision technique for grating based on CMOS microscopic imaging

    Institute of Scientific and Technical Information of China (English)

    Bo Yuan; Huimin Yan; Xiangqun Cao; Bin Lin

    2007-01-01

    We propose a new subdivision technique directly subdividing the grating stripe by using complementary metal-oxide semiconductor (CMOS) microscopic imaging system combined with image processing. The corresponding optical system, subdivision principle, and image processing methods are illuminated. The relations of systemic resolution to subdivision number, grating period, magnifying power and tilt angle are theoretically discussed and experimentally checked on the Abbe comparator. The measurement precision for displacement of the proposed subdivision system is tested in the range of 5 mm and the maximum displacement error is less than 0.4μm. The factors contributing to the systemic error are also discussed.

  7. Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

    Science.gov (United States)

    Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

    2017-05-01

    In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

  8. Low noise Millimeter-wave and THz Receivers, Imaging Arrays, Switches in Advanced CMOS and SiGe Processes /

    OpenAIRE

    Uzunkol, Mehmet

    2013-01-01

    The thesis presents advanced millimeter-wave and THz receivers, imaging arrays, switches and detectors in CMOS and SiGe BiCMOS technologies. First, an in-depth analysis of a SiGe BiCMOS on-off keying (OOK) receiver composed of a low noise SiGe amplifier and an OOK detector is presented. The analysis indicates that the bias circuit and bias current have a substantial impact on the receiver and should be optimized for best performance. Also, the LO leakage from the transmitter can have a detrim...

  9. Multiple-Event, Single-Photon Counting Imaging Sensor

    Science.gov (United States)

    Zheng, Xinyu; Cunningham, Thomas J.; Sun, Chao; Wang, Kang L.

    2011-01-01

    The single-photon counting imaging sensor is typically an array of silicon Geiger-mode avalanche photodiodes that are monolithically integrated with CMOS (complementary metal oxide semiconductor) readout, signal processing, and addressing circuits located in each pixel and the peripheral area of the chip. The major problem is its single-event method for photon count number registration. A single-event single-photon counting imaging array only allows registration of up to one photon count in each of its pixels during a frame time, i.e., the interval between two successive pixel reset operations. Since the frame time can t be too short, this will lead to very low dynamic range and make the sensor merely useful for very low flux environments. The second problem of the prior technique is a limited fill factor resulting from consumption of chip area by the monolithically integrated CMOS readout in pixels. The resulting low photon collection efficiency will substantially ruin any benefit gained from the very sensitive single-photon counting detection. The single-photon counting imaging sensor developed in this work has a novel multiple-event architecture, which allows each of its pixels to register as more than one million (or more) photon-counting events during a frame time. Because of a consequently boosted dynamic range, the imaging array of the invention is capable of performing single-photon counting under ultra-low light through high-flux environments. On the other hand, since the multiple-event architecture is implemented in a hybrid structure, back-illumination and close-to-unity fill factor can be realized, and maximized quantum efficiency can also be achieved in the detector array.

  10. Plasmonic Structures for CMOS Photonics and Control of Spontaneous Emission

    Science.gov (United States)

    2013-04-01

    Red, Green, Blue, Yellow, Magenta, Cyan) averaged CIE Delta-E 2000 = 16.6-19.3 after a white balance and color matrix correction is applied to the...insertion loss and also metal-insulator-metal waveguides; iii) developed a full format CMOS image sensor with plasmonic color filters; iv) explored... color filters and demonstration of imaging. v. Design of a plasMOStor plasmonic switching device, with low insertion loss, implemented in CMOS Si

  11. Measurement of multi-directional azimuth and tilt angles using an improved DVD pickup head with a CMOS sensor: A simulation design study

    Science.gov (United States)

    Sun, Wen-Shing; Lin, Yan-Nan; Tien, Chuen-Lin; Chang, Jenq-Yang

    2013-06-01

    We present a new detection method for an improved DVD pickup head system capable of measuring the multidirectional azimuth and small tilt angles. A complementary metal-oxide semiconductor (CMOS) sensor is used to capture images and analyze the slight shift of the central position of the beam shape when the test plane rotates to create a tilt angle and angular signal. The proposed detection method can determine the azimuth angle of the test plane from 0° to 360° at intervals of 5°. The tilt angle measurement is varied from 0° to 4.2° at intervals of 0.3°. The simulation results show that the improved DVD pickup head system can recognize multi-directional azimuth angles of the test plane under a small tilt.

  12. Radiation-hard Active Pixel Sensors for HL-LHC Detector Upgrades based on HV-CMOS Technology

    CERN Document Server

    Miucci, A; Hemperek, T.; Hügging, F.; Krüger, H.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Backhaus, M.; Capeans, M.; Feigl, S.; Nessi, M.; Pernegger, H.; Ristic, B.; Gonzalez-Sevilla, S.; Ferrere, D.; Iacobucci, G.; Rosa, A.La; Muenstermann, D.; George, M.; Grosse-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.; Kreidl, C.; Peric, I.; Breugnon, P.; Pangaud, P.; Godiot-Basolo, S.; Fougeron, D.; Bompard, F.; Clemens, J.C.; Liu, J; Barbero, M.; Rozanov, A

    2014-01-01

    Luminosity upgrades are discussed for the LHC (HL-LHC) which would make updates to the detectors necessary, requiring in particular new, even more radiation-hard and granular, sensors for the inner detector region. 1Corresponding author. c CERN 2014, published under the terms of the Creative Commons Attribution 3.0 License by IOP Publishing Ltd and Sissa Medialab srl. Any further distribution of this work must maintain attribution to the author(s) and the published article’s title, journal citation and DOI. doi:10.1088/1748-0221/9/05/C050642014 JINST 9 C05064 A proposal for the next generation of inner detectors is based on HV-CMOS: a new family of silicon sensors based on commercial high-voltage CMOS technology, which enables the fabrication of part of the pixel electronics inside the silicon substrate itself. The main advantages of this technology with respect to the standard silicon sensor technology are: low material budget, fast charge collection time, high radiation tolerance, low cost and operation a...

  13. A three-phase time-correlation image sensor using pinned photodiode active pixels

    Science.gov (United States)

    Han, Sangman; Iwahori, Tomohiro; Sawada, Tomonari; Kawahito, Shoji; Ando, Shigeru

    2010-01-01

    A time correlation (TC) image sensor is a device that produces 3-phase time-correlated signals between the incident light intensity and three reference signals. A conventional implementation of the TC image sensor using a standard CMOS technology works at low frequency and with low sensitivity. In order to achieve higher modulation frequency and high sensitivity, the TC image sensor with a dual potential structure using a pinned diode is proposed. The dual potential structure is created by changing the impurity doping concentration in the two different potential regions. In this structure, high-frequency modulation can be achieved, while maintaining a sufficient light receiving area. A prototype TC image sensor with 366×390pixels is implemented with 0.18-μm 1P4M CMOS image sensor technology. Each pixel with the size of 12μm×12μm has one pinned photodiode with the dual potential structure, 12 transistors and 3capacitors to implement three-parallel-output active pixel circuits. A fundamental operation of the implemented TC sensor is demonstrated.

  14. Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensors

    Science.gov (United States)

    Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

    2011-09-01

    In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100 nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/ f and white noise terms is studied as a function of the main device parameters before and after exposure to 10 keV X-rays and 60Co γ-rays. A prototype chip designed in a 65 nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced.

  15. Towards monolithically integrated CMOS cameras for active imaging with 600 GHz radiation

    Science.gov (United States)

    Boppel, Sebastian; Lisauskas, Alvydas; Krozer, Viktor; Roskos, Hartmut G.

    2012-02-01

    We explore terahertz imaging with CMOS field-effect transistors exploiting their plasmonic detection capability and the advantages of CMOS technology for the fabrication of THz cameras with respect to process stability, array uniformity, ease of integration of additional functionality, scalability and cost-effectiveness. A 100×100-pixel camera with an active area of 20×20 mm² is physically simulated by scanning single detectors and groups of a few detectors in the image plane. Using detectors with a noise-equivalent power of 43 pW/√Hz, a distributed illumination of 432 μW at 591.4 GHz, and an integration time of 20 ms (for a possible frame rate of 17 fps), this virtual camera allows to obtain images with a dynamic range of at least 20 dB and a resolution approaching the diffraction limit. Imaging examples acquired in direct and heterodyne detection mode, and in transmission and reflection geometry, show the potential for real-time operation. It is demonstrated that heterodyning (i) improves the dynamic range substantially even if the radiation from the local oscillator is distributed over the camera area, and (ii) allows sensitive determination of object-induced phase changes, which promises the realization of coherent imaging systems.

  16. Real-time monitoring of inhibitory effects on glutamate-induced neurotransmitter release using a potassium ion image sensor

    Science.gov (United States)

    Kono, Akiteru; Sakurai, Takashi; Hattori, Toshiaki; Okumura, Koichi; Ishida, Makoto; Sawada, Kazuaki

    2015-02-01

    To directly image the release of neurotransmitters from neurons, we combined a substance-selective layer with a 128 × 128-pixel ion image sensor based on CMOS technology. Using the substance-specific image sensors, we studied the dynamics of potassium ion ( K+) release from neurons and examined the effect of ouabain on K+ release. K+ transients were significantly inhibited by ouabain. The K+ image sensor used in this study demonstrated the dynamic analysis of ligand-operated signal release and the pharmacological assessment of secretagogues without requiring cell labeling.

  17. Power-Performance Tradeoffs in Wide Dynamic Range Image Sensors with Multiple Reset Approach

    Directory of Open Access Journals (Sweden)

    Arthur Spivak

    2011-03-01

    Full Text Available A variety of solutions for widening the dynamic range (DR of CMOS image sensors have been proposed throughout the years. These solutions can be categorized into different groups according to the principle used for DR widening. One of the methods, which is based on autonomous control over the integration time, was implemented by our group. We proposed the multiple resets algorithm, which was successfully implemented in three generations of WDR image sensors. While achieving the same goal of widening the DR of the sensor, each of the implemented imagers had a different architecture, and therefore presented different performance and power figures. This paper reviews designs of the aforementioned sensors and presents a comprehensive analysis of their power consumption. Power-performance tradeoffs are also discussed. Advantages and disadvantages of each sensor are presented.

  18. LGSD/NGSD: high speed visible CMOS imagers for E-ELT adaptive optics

    Science.gov (United States)

    Downing, Mark; Kolb, Johann; Dierickx, Bart; Defernez, Arnaud; Feautrier, Philippe; Fryer, Martin; Gach, Jean-Luc; Jerram, Paul; Jorden, Paul; Meyer, Manfred; Pike, Andrew; Reyes, Javier; Stadler, Eric; Swift, Nick

    2016-08-01

    The success of the next generation of instruments for ELT class telescopes will depend upon improving the image quality by exploiting sophisticated Adaptive Optics (AO) systems. One of the critical components of the AO systems for the European Extremely Large Telescope (E-ELT) has been identified as the Large Visible Laser/Natural Guide Star AO Wavefront Sensing (WFS) detector. The combination of large format, 1600x1600 pixels to finely sample the wavefront and the spot elongation of laser guide stars (LGS), fast frame rate of 700 frames per second (fps), low read noise ( 90%) makes the development of this device extremely challenging. Results of design studies concluded that a highly integrated Backside Illuminated CMOS Imager built on High Resistivity silicon as the most suitable technology. Two generations of the CMOS Imager are planned: a) a smaller `pioneering' device of > 800x800 pixels capable of meeting first light needs of the E-ELT. The NGSD, the topic of this paper, is the first iteration of this device; b) the larger full sized device called LGSD. The NGSD has come out of production, it has been thinned to 12μm, backside processed and packaged in a custom 370pin Ceramic PGA (Pin Grid Array). Results of comprehensive tests performed both at e2v and ESO are presented that validate the choice of CMOS Imager as the correct technology for the E-ELT Large Visible WFS Detector. These results along with plans for a second iteration to improve two issues of hot pixels and cross-talk are presented.

  19. Theoretical performance analysis for CMOS based high resolution detectors.

    Science.gov (United States)

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-06

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

  20. CMOS Flat-Panel CBCT for Dental Imaging

    Energy Technology Data Exchange (ETDEWEB)

    Youn, Han Bean; Cho, Min Kook; Kim, Jee Young; Lee, Hyun Ji; Cho, Bong Hye [Pusan National University, Busan (Korea, Republic of); Heo, Sung Kyn [E-WOO Technology, Co., Yongin (Korea, Republic of)

    2009-05-15

    Computed tomography (CT) has become one of the most frequently used imaging modalities for the preoperative evaluation of the jaw for dental implants. Sometimes dental Implant surgery needs histologic information of the regeneration of bone structure However conventional dental CT cannot serve these information because of its resolution limit. Hence we suggest dental CT which has micro scale resolution with high magnification factor. In these regards, We investigated micro dental CT with optimal magnification factor about our hardware system and evaluated along the 2D and 3D performance experimentally.

  1. A comparison of film and 3 digital imaging systems for natural dental caries detection: CCD, CMOS, PSP and film

    Energy Technology Data Exchange (ETDEWEB)

    Han, Won Jeong [Dankook University College of Medicine, Seoul (Korea, Republic of)

    2004-03-15

    To evaluate the diagnostic accuracy of occlusal and proximal caries detection using CCD, CMOS, PSP and film system. 32 occlusal and 30 proximal tooth surfaces were radiographed under standardized conditions using 3 digital systems; CCD (CDX-2000HQ, Biomedysis Co., Seoul, Korea), CMOS (Schick, Schick Inc., Long Island, USA), PSP (Digora FMX, Orion Co./Soredex, Helsinki, Finland) and 1 film system (Kodak Insight, Eastman Kodak, Rochester, USA). 5 observers examined the radiographs for occlusal and proximal caries using a 5-point confidence scale. The presence of caries was validated histologically and radiographically. Diagnostic accuracy was evaluated using ROC curve areas (AZ). Analysis using ROC curves revealed the area under each curve which indicated a diagnostic accuracy. For occlusal caries, Kodak Insight film had an Az of 0.765, CCD one of 0.730, CMOS one of 0.742 and PSP one of 0.735. For proximal caries, Kodak Insight film had an Az of 0.833, CCD one of 0.832, CMOS one of 0.828 and PSP one of 0.868. No statistically significant difference was noted between any of the imaging modalities. CCD, CMOS, PSP and film performed equally well in the detection of occlusal and proximal dental caries. CCD, CMOS and PSP-based digital images provided a level of diagnostic performance comparable to Kodak Insight film.

  2. CMOS Imager Has Better Cross-Talk and Full-Well Performance

    Science.gov (United States)

    Pain, Bedabrata; Cunningham, Thomas J.

    2011-01-01

    A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the

  3. CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detector based on CMOS pixel techology. Such detectors provide charge collection, analog and digital amplification in the same silicon bulk. The radiation hardness is obtained with multiple nested wells that have embedded the CMOS electronics with sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC. A number of alternative solutions have been explored and characterised, and are presented in this document.

  4. Development of CMOS Monolithic Active Pixel Sensors for the ALICE-ITS Outer Barrel and for the CBM-MVD

    CERN Document Server

    Deveaux, Michael

    2015-01-01

    After more than a decade of R&D;, CMOS Monolithic Active Pixel Sensors (MAPS or CPS) have proven to offer concrete answers to the demanding requirements of subatomic physics experi- ments. Their main advantages result from their low material budget, their very high granularity and their integrated signal processing circuitry, which allows coping with high particle rates. Moreover, they offer a valuable radiation tolerance and may be produced at low cost. Sensors of the MIMOSA series have offered an opportunity for nuclear and particle physics exper- iments to address with improved sensitivity physics studies requiring an accurate reconstruction of short living and soft particles. One of their major applications is the STAR-PXL detector, which is the first vertex detector based on MAPS. While this experiment is successfully taking data since two years, it was found that the 0.35 m CMOS technology used for this purpose is not suited for upcoming applications like the CBM micro-vertex detector (MVD) and the ...

  5. Experiment on digital CDS with 33-M pixel 120-fps super hi-vision image sensor

    Science.gov (United States)

    Yonai, J.; Yasue, T.; Kitamura, K.; Hayashida, T.; Watabe, T.; Shimamoto, H.; Kawahito, S.

    2014-03-01

    We have developed a CMOS image sensor with 33 million pixels and 120 frames per second (fps) for Super Hi-Vision (SHV:8K version of UHDTV). There is a way to reduce the fixed pattern noise (FPN) caused in CMOS image sensors by using digital correlated double sampling (digital CDS), but digital CDS methods need high-speed analog-to-digital conversion and are not applicable to conventional UHDTV image sensors due to their speed limit. Our image sensor, on the other hand, has a very fast analog-to-digital converter (ADC) using "two-stage cyclic ADC" architecture that is capable of being driven at 120-fps, which is double the normal frame rate for TV. In this experiment, we performed experimental digital CDS using the high-frame rate UHDTV image sensor. By reading the same row twice at 120-fps and subtracting dark pixel signals from accumulated pixel signals, we obtained a 60-fps equivalent video signal with digital noise reduction. The results showed that the VFPN was effectively reduced from 24.25 e-rms to 0.43 e-rms.

  6. Sticker-type ECG/PPG concurrent monitoring system hybrid integration of CMOS SoC and organic sensor device.

    Science.gov (United States)

    Lee, Yongsu; Lee, Hyeonwoo; Yoo, Seunghyup; Yoo, Hoi-Jun; Yongsu Lee; Hyeonwoo Lee; Seunghyup Yoo; Hoi-Jun Yoo; Yoo, Seunghyup; Lee, Yongsu; Yoo, Hoi-Jun; Lee, Hyeonwoo

    2016-08-01

    The sticker-type sensor system is proposed targeting ECG/PPG concurrent monitoring for cardiovascular diseases. The stickers are composed of two types: Hub and Sensor-node (SN) sticker. Low-power CMOS SoC for measuring ECG and PPG signal is hybrid integrated with organic light emitting diodes (OLEDs) and organic photo detector (OPD). The sticker has only 2g weight and only consumes 141μW. The optical calibration loop is adopted for maintaining SNR of PPG signal higher than 30dB. The pulse arrival time (PAT) and SpO2 value can be extracted from various body parts and verified comparing with the reference device from 20 people in-vivo experiments.

  7. Anti-scatter grid artifact elimination for high resolution x-ray imaging CMOS detectors

    Science.gov (United States)

    Rana, R.; Singh, V.; Jain, A.; Bednarek, D. R.; Rudin, S.

    2015-03-01

    Higher resolution in dynamic radiological imaging such as angiography is increasingly being demanded by clinicians; however, when standard anti-scatter grids are used with such new high resolution detectors, grid-line artifacts become more apparent resulting in increased structured noise that may overcome the contrast signal improvement benefits of the scatter-reducing grid. Although grid-lines may in theory be eliminated by dividing the image of a patient taken with the grid by a flat-field image taken with the grid obtained prior to the clinical image, unless the remaining additive scatter contribution is subtracted in real-time from the dynamic clinical image sequence before the division by the reference image, severe grid-line artifacts may remain. To investigate grid-line elimination, a stationary Smit Röntgen X-ray grid (line density: 70 lines/cm, grid ratio 13:1) was used with both a 75 micron-pixel CMOS detector and a standard 194 micron-pixel flat panel detector (FPD) to image an artery block insert placed in a modified uniform frontal head phantom for a 20 x 20cm FOV (approximately). Contrast and contrast-to-noise ratio (CNR) were measured with and without scatter subtraction prior to grid-line correction. The fixed pattern noise caused by the grid was substantially higher for the CMOS detector compared to the FPD and caused a severe reduction of CNR. However, when the scatter subtraction corrective method was used, the removal of the fixed pattern noise (grid artifacts) became evident resulting in images with improved CNR.

  8. Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

    Science.gov (United States)

    Liang, Z.; Affolder, A.; Arndt, K.; Bates, R.; Benoit, M.; Di Bello, F.; Blue, A.; Bortoletto, D.; Buckland, M.; Buttar, C.; Caragiulo, P.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hoeferkamp, M.; Hommels, L. B. A.; Huffman, B. T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, J.; Mandić, I.; Maneuski, D.; Martinez-Mckinney, F.; McMahon, S.; Meng, L.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Peric, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seidel, S.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zhang, J.; Zhu, H.

    2016-09-01

    This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

  9. Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Liang, Z., E-mail: zhijun.liang@cern.ch [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Institute of High Energy Physics, Beijing (China); Affolder, A. [University of Liverpool (United Kingdom); Arndt, K. [University of Oxford (United Kingdom); Bates, R. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Benoit, M.; Di Bello, F. [University of Geneva (Switzerland); Blue, A. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Bortoletto, D. [University of Oxford (United Kingdom); Buckland, M. [University of Liverpool (United Kingdom); CERN, European Center for Nuclear Research (Switzerland); Buttar, C. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Caragiulo, P. [SLAC National Accelerator Laboratory (United States); Das, D.; Dopke, J. [Rutherford Appleton Laboratory, Didcot (United Kingdom); Dragone, A. [SLAC National Accelerator Laboratory (United States); Ehrler, F. [Karlsruhe Institute of Technology (Germany); Fadeyev, V.; Galloway, Z.; Grabas, H. [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Gregor, I.M. [Deutsches Elektronen-Synchrotron (Germany); Grenier, P. [SLAC National Accelerator Laboratory (United States); and others

    2016-09-21

    This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

  10. Full well capacity and quantum efficiency optimization for small size backside illuminated CMOS image pixels with a new photodiode structure

    Institute of Scientific and Technical Information of China (English)

    Sun Yu; Zhang Ping; Xu Jiangtao; Gao Zhiyuan; Xu Chao

    2012-01-01

    To improve the full well capacity (FWC) of a small size backside illuminated (BSI) CMOS image sensor (CIS),the effect of photodiode capacitance (CPD) on FWC is studied,and a reformed pinned photodiode (PPD) structure is proposed.Two procedures are implemented for the optimization.The first is to form a varying doping concentration and depth stretched new N region,which is implemented by an additional higher-energy and lower-dose N type implant beneath the original N region.The FWC of this structure is increased by extending the side wall junctions in the substrate.Secondly,in order to help the enlarged well capacity achieve full depletion,two step P-type implants with different implant energies are introduced to form a P-type insertion region in the interior of the stretched N region.This vertical inserted P region guarantees that the proposed new PD structure achieves full depletion in the reset period.The simulation results show that the FWC can be improved from 1289e-to 6390e-,and this improvement does not sacrifice any image lag performance.Additionally,quantum efficiency (QE) is enhanced in the full wavelength range,especially 6.3% at 520 nm wavelength.This technique can not only be used in such BSI structures,but also adopted in an FSI pixel with any photodiode-type readout scheme.

  11. Tracking and flavour-tagging performance for HV-CMOS sensors in the context of the ATLAS ITK pixel simulation program

    Science.gov (United States)

    Calandri, A.; Vacavant, L.; Barbero, M.; Rozanov, A.; Djama, F.

    2016-12-01

    The HV-CMOS (High Voltage - Complementary Metal-Oxide Semiconductor) pixel technology has recently risen interest for the upgrade of the pixel detector of the ATLAS experiment towards the High Luminosity phase of the Large Hadron Collider (LHC) . HV-CMOS sensors can be employed in the pixel outer layers (R >15 cm), where the radiation hardness requirements are less stringent, as they could instrument large areas at a relatively low cost. In addition, smaller pixel granularity can be achieved by exploiting sub-pixel encoding technology. Therefore, the largest impact on physics performance, tracking and flavour tagging, could be reached if exploited in the innermost layer (in place of the current IBL) or in the next-to-innermost layer. This proceeding will present studies on tracking and flavour-tagging performance in presence of HV-CMOS sensors in the innermost layer of the ATLAS detector.

  12. Ultralow power, high fill factor smart complementary metal oxide semiconductor image sensor with motion detection capability

    Science.gov (United States)

    Mahbod, Abbas; Karimiyan, Hossein

    2016-11-01

    Bandwidth saving, power consumption, and fill factor improvement are known as vitally important challenges image sensor designers face in order to accomplish high-performance imaging systems. This paper presents an ultralow power, high fill factor smart complementary metal oxide semiconductor (CMOS) image sensor with motion detection capability. In this efficient methodology, the amount of redundant data processed in unimportant frames has been reduced significantly, and therefore, the proposed imaging system consumes less power compared with counterpart imagers. Furthermore, a pixel structure is introduced that outputs two consecutive frame voltages in series, with the result that the pixel size is minimized and a higher fill factor is achieved. In order to simulate the image capturing procedure, a state-of-the-art approach based on MATLAB and HSPICE software is devised, which is another important achievement of this paper. The performance of this technique is demonstrated using a 64×64 pixel sensor designed in a 0.18-μm standard CMOS technology. The sensor chip consumes 0.2 mW of power while operating at 100 fps with a fill factor of 45%.

  13. A CMOS image-rejection mixer with 58-dB IRR for DTV receivers

    Institute of Scientific and Technical Information of China (English)

    Yuan Shuai; Li Zhiqun; Huang Jing; Wang Zhigong

    2009-01-01

    The design, implementation, and characterization of an image-rejection double quadrature conversion mixer based on RC asymmetric polyphase filters (PPF) are presented. The mixer consists of three sets of PPFs and a mixer core for quadrature down conversion. Two sets of PPFs are used for the quadrature generation and the other one is used for the IF signal selection to reject the unwanted image band. Realized in 0.18-μm CMOS technology as a part of the DVB-T receiver chip, the mixer exhibits a high image rejection ratio (IRR) of 58 dB, a power consumption of 11 mW, and a 1-dB gain compression point of -15 dBm.

  14. A CMOS-compatible large-scale monolithic integration of heterogeneous multi-sensors on flexible silicon for IoT applications

    KAUST Repository

    Nassar, Joanna M.

    2017-02-07

    We report CMOS technology enabled fabrication and system level integration of flexible bulk silicon (100) based multi-sensors platform which can simultaneously sense pressure, temperature, strain and humidity under various physical deformations. We also show an advanced wearable version for body vital monitoring which can enable advanced healthcare for IoT applications.

  15. Experimental and theoretical performance analysis for a CMOS-based high resolution image detector.

    Science.gov (United States)

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2014-03-19

    Increasing complexity of endovascular interventional procedures requires superior x-ray imaging quality. Present state-of-the-art x-ray imaging detectors may not be adequate due to their inherent noise and resolution limitations. With recent developments, CMOS based detectors are presenting an option to fulfill the need for better image quality. For this work, a new CMOS detector has been analyzed experimentally and theoretically in terms of sensitivity, MTF and DQE. The detector (Dexela Model 1207, Perkin-Elmer Co., London, UK) features 14-bit image acquisition, a CsI phosphor, 75 µm pixels and an active area of 12 cm × 7 cm with over 30 fps frame rate. This detector has two modes of operations with two different full-well capacities: high and low sensitivity. The sensitivity and instrumentation noise equivalent exposure (INEE) were calculated for both modes. The detector modulation-transfer function (MTF), noise-power spectra (NPS) and detective quantum efficiency (DQE) were measured using an RQA5 spectrum. For the theoretical performance evaluation, a linear cascade model with an added aliasing stage was used. The detector showed excellent linearity in both modes. The sensitivity and the INEE of the detector were found to be 31.55 DN/µR and 0.55 µR in high sensitivity mode, while they were 9.87 DN/µR and 2.77 µR in low sensitivity mode. The theoretical and experimental values for the MTF and DQE showed close agreement with good DQE even at fluoroscopic exposure levels. In summary, the Dexela detector's imaging performance in terms of sensitivity, linear system metrics, and INEE demonstrates that it can overcome the noise and resolution limitations of present state-of-the-art x-ray detectors.

  16. Experimental and theoretical performance analysis for a CMOS-based high resolution image detector

    Science.gov (United States)

    Jain, Amit; Bednarek, Daniel R.; Rudin, Stephen

    2014-03-01

    Increasing complexity of endovascular interventional procedures requires superior x-ray imaging quality. Present stateof- the-art x-ray imaging detectors may not be adequate due to their inherent noise and resolution limitations. With recent developments, CMOS based detectors are presenting an option to fulfill the need for better image quality. For this work, a new CMOS detector has been analyzed experimentally and theoretically in terms of sensitivity, MTF and DQE. The detector (Dexela Model 1207, Perkin-Elmer Co., London, UK) features 14-bit image acquisition, a CsI phosphor, 75 μm pixels and an active area of 12 cm x 7 cm with over 30 fps frame rate. This detector has two modes of operations with two different full-well capacities: high and low sensitivity. The sensitivity and instrumentation noise equivalent exposure (INEE) were calculated for both modes. The detector modulation-transfer function (MTF), noise-power spectra (NPS) and detective quantum efficiency (DQE) were measured using an RQA5 spectrum. For the theoretical performance evaluation, a linear cascade model with an added aliasing stage was used. The detector showed excellent linearity in both modes. The sensitivity and the INEE of the detector were found to be 31.55 DN/μR and 0.55 μR in high sensitivity mode, while they were 9.87 DN/μR and 2.77 μR in low sensitivity mode. The theoretical and experimental values for the MTF and DQE showed close agreement with good DQE even at fluoroscopic exposure levels. In summary, the Dexela detector's imaging performance in terms of sensitivity, linear system metrics, and INEE demonstrates that it can overcome the noise and resolution limitations of present state-of-the-art x-ray detectors.

  17. Novel rangefinding system using a correlation image sensor

    Science.gov (United States)

    Kimachi, Akira; Kurihara, Toru; Takamoto, Masao; Ando, Shigeru

    2000-12-01

    This paper proposes a 3D measurement principle for the correlation image sensor (CIS), which generates temporal correlation between light intensity and an external reference signal at each pixel. Another key of our system besides the CIS is amplitude-modulation of the scanning sheet beam, the phase of which relative to a reference signal is varied according to the scanning angle. After a scan within a frame, the phase is demodulated with a quadrature pair of reference signals and output by the CIS to compute the individual angle of the sheet bam at each pixel. By virtue of lock-in detection principle, the effects of background illumination and/or surface reflectance nonuniformity of the object are thoroughly removed. We implemented this system using our CMOS 64 by 64 pixel CIS, and successfully reconstructed a depth map under its frame rate.

  18. High speed global shutter image sensors for professional applications

    Science.gov (United States)

    Wu, Xu; Meynants, Guy

    2015-04-01

    Global shutter imagers expand the use to miscellaneous applications, such as machine vision, 3D imaging, medical imaging, space etc. to eliminate motion artifacts in rolling shutter imagers. A low noise global shutter pixel requires more than one non-light sensitive memory to reduce the read noise. But larger memory area reduces the fill-factor of the pixels. Modern micro-lenses technology can compensate this fill-factor loss. Backside illumination (BSI) is another popular technique to improve the pixel fill-factor. But some pixel architecture may not reach sufficient shutter efficiency with backside illumination. Non-light sensitive memory elements make the fabrication with BSI possible. Machine vision like fast inspection system, medical imaging like 3D medical or scientific applications always ask for high frame rate global shutter image sensors. Thanks to the CMOS technology, fast Analog-to-digital converters (ADCs) can be integrated on chip. Dual correlated double sampling (CDS) on chip ADC with high interface digital data rate reduces the read noise and makes more on-chip operation control. As a result, a global shutter imager with digital interface is a very popular solution for applications with high performance and high frame rate requirements. In this paper we will review the global shutter architectures developed in CMOSIS, discuss their optimization process and compare their performances after fabrication.

  19. Fast frame rate rodent cardiac x-ray imaging using scintillator lens coupled to CMOS camera

    Science.gov (United States)

    Swathi Lakshmi, B.; Sai Varsha, M. K. N.; Kumar, N. Ashwin; Dixit, Madhulika; Krishnamurthi, Ganapathy

    2017-03-01

    Micro-Computed Tomography (MCT) systems for small animal imaging plays a critical role for monitoring disease progression and therapy evaluation. In this work, an in-house built micro-CT system equipped with a X-ray scintillator lens coupled to a commercial CMOS camera was used to test the feasibility of its application to Digital Subtraction Angiography (DSA). Literature has reported such studies being done with clinical X-ray tubes that can be pulsed rapidly or with rotating gantry systems, thus increasing the cost and infrastructural requirements.The feasibility of DSA was evaluated by injected Iodinated contrast agent (ICA) through the tail vein of a mouse. Projection images of the heart were acquired pre and post contrast using the high frame rate X-ray detector and processing done to visualize transit of ICA through the heart.

  20. Burn imaging with a whole field laser Doppler perfusion imager based on a CMOS imaging array

    NARCIS (Netherlands)

    van Herpt, Heleen; Draijer, Matthijs; Hondebrink, Erwin; Nieuwenhuis, Marianne; Beerthuizen, Gerard; van Leeuwen, Ton; Steenbergen, Wiendelt

    2010-01-01

    Laser Doppler perfusion imaging (LDPI) has been proven to be a useful tool in predicting the burn wound outcome in an early stage. A major disadvantage of scanning beam LDPI devices is their slow scanning speed, leading to patient discomfort and imaging artifacts. We have developed the Twente Optica

  1. Burn imaging with a whole field laser Doppler perfusion imager based on a CMOS imaging array

    NARCIS (Netherlands)

    van Herpt, Heleen; Draijer, Matthijs; Hondebrink, Erwin; Nieuwenhuis, Marianne; Beerthuizen, Gerard; van Leeuwen, Ton; van Leeuwen, Ton; Steenbergen, Wiendelt

    2010-01-01

    Laser Doppler perfusion imaging (LDPI) has been proven to be a useful tool in predicting the burn wound outcome in an early stage. A major disadvantage of scanning beam LDPI devices is their slow scanning speed, leading to patient discomfort and imaging artifacts. We have developed the Twente

  2. A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18μm standard CMOS process

    Institute of Scientific and Technical Information of China (English)

    Feng Peng; Zhang Qi; Wu Nanjian

    2011-01-01

    This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor.The chip tag integrates a temperature sensor,an RF/analog front-end circuit,an NVM memory and a digital baseband in a standard CMOS process.The sensor with a low power sigma-delta (Σ△) ADC is designed to operate in low and high resolution modes.It can not only achieve the target accuracy but also reduce the power consumption and the sensing time.A CMOS-only RF rectifier and a single-poly non-volatile memory (NVM) are designed to realize a low cost tag chip.The 192-bit-NVM tag chip with an area of 1 mm2 is implemented in a 0.18-μm standard CMOS process.The sensitivity of the tag is -10.7 dBm/-8.4 dBm when the sensor is disabled/enabled.It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP.The inaccuracy of the sensor is -0.6 ℃/0.5 ℃ (-1.0 ℃/1.2 ℃) in the operating range from 5 to 15 ℃ in high resolution mode (-30 to 50 ℃ in low resolution mode).The resolution of the sensor achieves 0.02 ℃ (0.18 ℃) in high (low) resolution mode.

  3. CMOS Ultrasound Transceiver Chip for High-Resolution Ultrasonic Imaging Systems.

    Science.gov (United States)

    Insoo Kim; Hyunsoo Kim; Griggio, F; Tutwiler, R L; Jackson, T N; Trolier-McKinstry, S; Kyusun Choi

    2009-10-01

    The proposed CMOS ultrasound transceiver chip will enable the development of portable high resolution, high-frequency ultrasonic imaging systems. The transceiver chip is designed for close-coupled MEMS transducer arrays which operate with a 3.3-V power supply. In addition, a transmit digital beamforming system architecture is supported in this work. A prototype chip containing 16 receive and transmit channels with preamplifiers, time-gain compensation amplifiers, a multiplexed analog-to-digital converter with 3 kB of on-chip SRAM, and 50-MHz resolution time delayed excitation pulse generators has been fabricated. By utilizing a shared A/D converter architecture, the number of A/D converter and SRAM is cut down to one, unlike typical digital beamforming systems which need 16 A/D converters for 16 receive channels. The chip was fabricated in a 0.35-mum standard CMOS process. The chip size is 10 mm(2), and its average power consumption in receive mode is approximately 270 mW with a 3.3-V power supply. The transceiver chip specifications and designs are described, as well as measured results of each transceiver component and initial pulse-echo experimental results are presented.

  4. Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

    Directory of Open Access Journals (Sweden)

    Ler Chun Lee

    2008-01-01

    Full Text Available A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA. A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHz

  5. A CMOS Integrating Amplifier for the PHENIX Ring Imaging Cherenkov detector

    Energy Technology Data Exchange (ETDEWEB)

    Wintenberg, A.L.; Jones, J.P. Jr.; Young, G.R. [Oak Ridge National Lab., TN (United States); Moscone, C.G. [Tennessee Univ., Knoxville, TN (United States)

    1997-11-01

    A CMOS integrating amplifier has been developed for use in the PHENIX Ring Imaging Cherenkov (RICH) detector. The amplifier, consisting of a charge-integrating amplifier followed by a variable gain amplifier (VGA), is an element of a photon measurement system comprising a photomultiplier tube, a wideband, gain of 10 amplifier, the integrating amplifier, and an analog memory followed by an ADC and double correlated sampling implemented in software. The integrating amplifier is designed for a nominal full scale input of 160 pC with a gain of 20 mV/pC and a dynamic range of 1000:1. The VGA is used for equalizing gains prior to forming analog sums for trigger purposes. The gain of the VGA is variable over a 3:1 range using a 5 bits digital control, and the risetime is held to approximately 20 ns using switched compensation in the VGA. Details of the design and results from several prototype devices fabricated in 1.2 {micro}m Orbit CMOS are presented. A complete noise analysis of the integrating amplifier and the correlated sampling process is included as well as a comparison of calculated, simulated and measured results.

  6. A noiseless kilohertz frame rate imaging detector based on microchannel plates read out with the Medipix2 CMOS pixel chip

    CERN Document Server

    Mikulec, Bettina; Ferrère, Didier; La Marra, Daniel; McPhate, J B; Tremsin, A S; Siegmund, O H W; Vallerga, J V; Clement, J; Ponchut, C; Rigal, J M; CERN. Geneva

    2006-01-01

    A new hybrid optical imaging detector is described that is being developed for the next generation adaptive optics (AO) wavefront sensors (WFS) for ground-based telescopes. The detector consists of a photocathode and proximity focused microchannel plates (MCPs) read out by the Medipix2 CMOS pixel ASIC. Each pixel of the Medipix2 device measures 55x55 um2 and comprises pre-amplifier, a window discriminator and a 14-bit counter. The 256x256 Medipix2 array can be read out noiselessly in 287 us. The readout can be electronically shuttered down to a temporal window of a few us. The Medipix2 is buttable on 3 sides to produce 512x(n*256) pixel devices. Measurements with ultraviolet light yield a spatial resolution of the detector at the Nyquist limit. Sub-pixel resolution can be achieved using centroiding algorithms. For the AO application, very high continuous frame rates of the order of 1 kHz are required for a matrix of 512x512 pixels. The design concepts of a parallel readout board are presented that will allow ...

  7. Smart Image Sensor with Integrated Low Complexity Image Processing for Wireless Endoscope Capsules

    Institute of Scientific and Technical Information of China (English)

    LI Xiaowen; ZHANG Milin; WANG Zhihua; Amine Bermak

    2009-01-01

    A smart image sensor was developed which integrates a digital pixel image sensor array with an image processor, designed for wireless endoscope capsules. The camera-on-a-chip architecture and its on-chip functionality facilitate the design of the packaging and power consumption of the integrated capsule. The power reduction techniques were carried out at both the architectural and circuit level. Gray coding and power gating in the sensor array to eliminate almost 50% of the switch activity on the data bus and more than 99% of the power dissipation in each pixel at a transmitting rate of 2 frames per second. Filtering and compression in the processor reduces the data transmission by more than 2/3. A parallel fully pipelined ar-chitecture with a dedicated clock management scheme was implemented in the JPEG-LS engine to reduce the power consumption by 15.7%. The smart sensor has been implemented in 0.18 μm CMOS technology.

  8. Visual Image Sensor Organ Replacement

    Science.gov (United States)

    Maluf, David A.

    2014-01-01

    This innovation is a system that augments human vision through a technique called "Sensing Super-position" using a Visual Instrument Sensory Organ Replacement (VISOR) device. The VISOR device translates visual and other sensors (i.e., thermal) into sounds to enable very difficult sensing tasks. Three-dimensional spatial brightness and multi-spectral maps of a sensed image are processed using real-time image processing techniques (e.g. histogram normalization) and transformed into a two-dimensional map of an audio signal as a function of frequency and time. Because the human hearing system is capable of learning to process and interpret extremely complicated and rapidly changing auditory patterns, the translation of images into sounds reduces the risk of accidentally filtering out important clues. The VISOR device was developed to augment the current state-of-the-art head-mounted (helmet) display systems. It provides the ability to sense beyond the human visible light range, to increase human sensing resolution, to use wider angle visual perception, and to improve the ability to sense distances. It also allows compensation for movement by the human or changes in the scene being viewed.

  9. Compact all-CMOS spatiotemporal compressive sensing video camera with pixel-wise coded exposure.

    Science.gov (United States)

    Zhang, Jie; Xiong, Tao; Tran, Trac; Chin, Sang; Etienne-Cummings, Ralph

    2016-04-18

    We present a low power all-CMOS implementation of temporal compressive sensing with pixel-wise coded exposure. This image sensor can increase video pixel resolution and frame rate simultaneously while reducing data readout speed. Compared to previous architectures, this system modulates pixel exposure at the individual photo-diode electronically without external optical components. Thus, the system provides reduction in size and power compare to previous optics based implementations. The prototype image sensor (127 × 90 pixels) can reconstruct 100 fps videos from coded images sampled at 5 fps. With 20× reduction in readout speed, our CMOS image sensor only consumes 14μW to provide 100 fps videos.

  10. A directly converting high-resolution intra-oral X-ray imaging sensor

    CERN Document Server

    Spartiotis, K; Schulman, T; Puhakka, K; Muukkonen, K

    2003-01-01

    A digital intra-oral X-ray imaging sensor with an active area of 3.6x2.9 cm sup 2 and consisting of six charge-integrating CMOS signal readout circuits bump bonded to one high-resistivity silicon pixel detector has been developed and tested. The pixel size is 35 mu m. The X-rays entering the sensor window are converted directly to electrical charge in the depleted detector material yielding minimum lateral signal spread and maximum image sharpness. The signal charge is collected on the gates of the input field effect transistors of the CMOS signal readout circuits. The analog signal readout is performed by multiplexing in the current mode independent of the signal charge collection enabling multiple readout cycles with negligible dead time and thus imaging with wide dynamic range. Since no intermediate conversion material of X-rays to visible light is needed, the sensor structure is very compact. The analog image signals are guided from the sensor output through a thin cable to signal processing, AD conversio...

  11. Analysis of dark current images of a CMOS camera during gamma irradiation

    Energy Technology Data Exchange (ETDEWEB)

    Náfrádi, Gábor, E-mail: nafradi@reak.bme.hu [INT, BME, EURATOM Association, H-1111 Budapest (Hungary); Czifrus, Szabolcs, E-mail: czifrus@reak.bme.hu [INT, BME, EURATOM Association, H-1111 Budapest (Hungary); Kocsis, Gábor, E-mail: kocsis.gabor@wigner.mta.hu [Wigner RCP, RMI, EURATOM Association, POB 49, 1525 Budapest (Hungary); Pór, Gábor, E-mail: por@reak.bme.hu [INT, BME, EURATOM Association, H-1111 Budapest (Hungary); Szepesi, Tamás, E-mail: szepesi.tamas@wigner.mta.hu [Wigner RCP, RMI, EURATOM Association, POB 49, 1525 Budapest (Hungary); Zoletnik, Sándor, E-mail: zoletnik.sandor@wigner.mta.hu [Wigner RCP, RMI, EURATOM Association, POB 49, 1525 Budapest (Hungary)

    2013-12-15

    Highlights: • Radiation tolerance of a fast framing CMOS camera EDICAM examined. • We estimate the expected gamma dose and spectrum of EDICAM with MCNP. • We irradiate EDICAM by 23.5 Gy in 70 min in a fission rector. • Dose rate normalised average brightness of frames grows linearly with the dose. • Dose normalised average brightness of frames follows the dose rate time evolution. -- Abstract: We report on the behaviour of the dark current images of the Event Detection Intelligent Camera (EDICAM) when placed into an irradiation field of gamma rays. EDICAM is an intelligent fast framing CMOS camera operating in the visible spectral range, which is designed for the video diagnostic system of the Wendelstein 7-X (W7-X) stellarator. Monte Carlo calculations were carried out in order to estimate the expected gamma spectrum and dose for an entire year of operation in W7-X. EDICAM was irradiated in a pure gamma field in the Training Reactor of BME with a dose of approximately 23.5 Gy in 1.16 h. During the irradiation, numerous frame series were taken with the camera with exposure times 20 μs, 50 μs, 100 μs, 1 ms, 10 ms, 100 ms. EDICAM withstood the irradiation, but suffered some dynamic range degradation. The behaviour of the dark current images during irradiation is described in detail. We found that the average brightness of dark current images depends on the total ionising dose that the camera is exposed to and the dose rate as well as on the applied exposure times.

  12. Single photon detection and localization accuracy with an ebCMOS camera

    Science.gov (United States)

    Cajgfinger, T.; Dominjon, A.; Barbier, R.

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 μm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  13. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  14. Highly curved image sensors: a practical approach for improved optical performance

    Science.gov (United States)

    Guenter, Brian; Joshi, Neel; Stoakley, Richard; Keefe, Andrew; Geary, Kevin; Freeman, Ryan; Hundley, Jake; Patterson, Pamela; Hammon, David; Herrera, Guillermo; Sherman, Elena; Nowak, Andrew; Schubert, Randall; Brewer, Peter; Yang, Louis; Mott, Russell; McKnight, Geoff

    2017-06-01

    The significant optical and size benefits of using a curved focal surface for imaging systems have been well studied yet never brought to market for lack of a high-quality, mass-producible, curved image sensor. In this work we demonstrate that commercial silicon CMOS image sensors can be thinned and formed into accurate, highly curved optical surfaces with undiminished functionality. Our key development is a pneumatic forming process that avoids rigid mechanical constraints and suppresses wrinkling instabilities. A combination of forming-mold design, pressure membrane elastic properties, and controlled friction forces enables us to gradually contact the die at the corners and smoothly press the sensor into a spherical shape. Allowing the die to slide into the concave target shape enables a threefold increase in the spherical curvature over prior approaches having mechanical constraints that resist deformation, and create a high-stress, stretch-dominated state. Our process creates a bridge between the high precision and low-cost but planar CMOS process, and ideal non-planar component shapes such as spherical imagers for improved optical systems. We demonstrate these curved sensors in prototype cameras with custom lenses, measuring exceptional resolution of 3220 line-widths per picture height at an aperture of f/1.2 and nearly 100% relative illumination across the field. Though we use a 1/2.3" format image sensor in this report, we also show this process is generally compatible with many state of the art imaging sensor formats. By example, we report photogrammetry test data for an APS-C sized silicon die formed to a 30$^\\circ$ subtended spherical angle. These gains in sharpness and relative illumination enable a new generation of ultra-high performance, manufacturable, digital imaging systems for scientific, industrial, and artistic use.

  15. Label-free CMOS bio sensor with on-chip noise reduction scheme for real-time quantitative monitoring of biomolecules.

    Science.gov (United States)

    Seong-Jin Kim; Euisik Yoon

    2012-06-01

    We present a label-free CMOS field-effect transistor sensing array to detect the surface potential change affected by the negative charge in DNA molecules for real-time monitoring and quantification. The proposed CMOS bio sensor includes a new sensing pixel architecture implemented with correlated double sampling for reducing offset fixed pattern noise and 1/f noise of the sensing devices. We incorporated non-surface binding detection which allows real-time continuous monitoring of DNA concentrations without immobilizing them on the sensing surface. Various concentrations of 19-bp oligonucleotides solution can be discriminated using the prototype device fabricated in 1- μm double-poly double-metal standard CMOS process. The detection limit was measured as 1.1 ng/μl with a dynamic range of 40 dB and the transient response time was measured less than 20 seconds.

  16. Improved Space Object Observation Techniques Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  17. CMOS detector arrays in a virtual 10-kilopixel camera for coherent terahertz real-time imaging.

    Science.gov (United States)

    Boppel, Sebastian; Lisauskas, Alvydas; Max, Alexander; Krozer, Viktor; Roskos, Hartmut G

    2012-02-15

    We demonstrate the principle applicability of antenna-coupled complementary metal oxide semiconductor (CMOS) field-effect transistor arrays as cameras for real-time coherent imaging at 591.4 GHz. By scanning a few detectors across the image plane, we synthesize a focal-plane array of 100×100 pixels with an active area of 20×20 mm2, which is applied to imaging in transmission and reflection geometries. Individual detector pixels exhibit a voltage conversion loss of 24 dB and a noise figure of 41 dB for 16 μW of the local oscillator (LO) drive. For object illumination, we use a radio-frequency (RF) source with 432 μW at 590 GHz. Coherent detection is realized by quasioptical superposition of the image and the LO beam with 247 μW. At an effective frame rate of 17 Hz, we achieve a maximum dynamic range of 30 dB in the center of the image and more than 20 dB within a disk of 18 mm diameter. The system has been used for surface reconstruction resolving a height difference in the μm range.

  18. Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure

    Science.gov (United States)

    Chen, Cao; Bing, Zhang; Longsheng, Wu; Xin, Li; Junfeng, Wang

    2014-07-01

    A novel analytical model of pinch-off voltage for CMOS image pixels with a pinned photodiode structure is proposed. The derived model takes account of the gradient doping distributions in the N buried layer due to the impurity compensation formed by manufacturing processes; the impurity distribution characteristics of two boundary PN junctions located in the region for particular spectrum response of a pinned photodiode are quantitative analyzed. By solving Poisson's equation in vertical barrier regions, the relationships between the pinch-off voltage and the corresponding process parameters such as peak doping concentration, N type width and doping concentration gradient of the N buried layer are established. Test results have shown that the derived model features the variations of the pinch-off voltage versus the process implant conditions more accurately than the traditional model. The research conclusions in this paper provide theoretical evidence for evaluating the pinch-off voltage design.

  19. A CMOS vision chip for a contrast-enhanced image using a logarithmic APS and a switch-selective resistive network

    Science.gov (United States)

    Kong, Jae-Sung; Kim, Sang-Heon; Sung, Dong-Kyu; Seo, Sang-Ho; Shin, Jang-Kyoo

    2007-02-01

    In this paper, a vision chip for a contrast-enhanced image based on a structure of a biological retina is introduced. The key advantage of this structure is high speed of signal processing. In a conventional active pixel sensor (APS), the charge accumulation time limits its operation speed. In order to enhance the speed, a logarithmic APS was applied to the vision chip. By applying a MOS-type photodetector to the logarithmic APS, we could achieve sufficient output swing for the vision chip in natural illumination condition. In addition, a CMOS buffer circuit, a common drain amplifier, is commonly used for both raw and smoothed images by using additional switches. By using the switch-selective resistive network, the total number of MOSFETs for a unit pixel and the fixed-pattern noise were reduced. A vision chip with a 160×120 pixel array was fabricated using a 0.35 μm double-poly four-metal CMOS technology, and its operation was experimentally investigated.

  20. Uncooled microbolometer thermal imaging sensors for unattended ground sensor applications

    Science.gov (United States)

    Figler, Burton D.

    2001-09-01

    Starting in the early 1990's, uncooled microbolometer thermal imaging sensor technology began to move out of the basic development laboratories of the Honeywell Corporation in Minneapolis and into applied development at several companies which have licensed the basic technology. Now, this technology is addressing military, government, and commercial applications in the real world. Today, thousands of uncooled microbolometer thermal imaging sensors are being produced and sold annually. At the same time, applied research and development on the technology continues at an unabated pace. These research and development efforts have two primary goals: 1) improving sensor performance in terms of increased resolution and greater thermal sensitivity and 2) reducing sensor cost. Success is being achieved in both areas. In this paper we will describe advances in uncooled microbolometer thermal imaging sensor technology as they apply to the modern battlefield and to unattended ground sensor applications in particular. Improvements in sensor performance include: a) reduced size, b) increased spatial resolution, c) increased thermal sensitivity, d) reduced electrical power, and e) reduced weight. For battlefield applications, unattended sensors are used not only in fixed ground locations, but also on a variety of moving platforms, including remotely operated ground vehicles, as well as Micro and Miniature Aerial Vehicles. The use of uncooled microbolometer thermal imaging sensors on these platforms will be discussed, and the results from simulations, of an uncooled microbolometer sensor flying on a Micro Aerial Vehicle will be presented. Finally, we will describe microbolometer technology advancements currently being made or planned at BAE SYSTEMS. Where possible, examples of actual improvements, in the form of real imagery and/or actual performance measurements, will be provided.

  1. SPIDER: Next Generation Chip Scale Imaging Sensor Update

    Science.gov (United States)

    Duncan, A.; Kendrick, R.; Ogden, C.; Wuchenich, D.; Thurman, S.; Su, T.; Lai, W.; Chun, J.; Li, S.; Liu, G.; Yoo, S. J. B.

    2016-09-01

    The Lockheed Martin Advanced Technology Center (LM ATC) and the University of California at Davis (UC Davis) are developing an electro-optical (EO) imaging sensor called SPIDER (Segmented Planar Imaging Detector for Electro-optical Reconnaissance) that seeks to provide a 10x to 100x size, weight, and power (SWaP) reduction alternative to the traditional bulky optical telescope and focal-plane detector array. The substantial reductions in SWaP would reduce cost and/or provide higher resolution by enabling a larger-aperture imager in a constrained volume. Our SPIDER imager replaces the traditional optical telescope and digital focal plane detector array with a densely packed interferometer array based on emerging photonic integrated circuit (PIC) technologies that samples the object being imaged in the Fourier domain (i.e., spatial frequency domain), and then reconstructs an image. Our approach replaces the large optics and structures required by a conventional telescope with PICs that are accommodated by standard lithographic fabrication techniques (e.g., complementary metal-oxide-semiconductor (CMOS) fabrication). The standard EO payload integration and test process that involves precision alignment and test of optical components to form a diffraction limited telescope is, therefore, replaced by in-process integration and test as part of the PIC fabrication, which substantially reduces associated schedule and cost. This paper provides an overview of performance data on the second-generation PIC for SPIDER developed under the Defense Advanced Research Projects Agency (DARPA)'s SPIDER Zoom research funding. We also update the design description of the SPIDER Zoom imaging sensor and the second-generation PIC (high- and low resolution versions).

  2. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    Science.gov (United States)

    Cha, Bo Kyung; Jeon, Seongchae; Seo, Chang-Woo

    2016-09-01

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 μm 1-poly/4-metal CMOS process. The pixel size is 100 μm×100 μm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd2O2S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  3. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    Energy Technology Data Exchange (ETDEWEB)

    Cha, Bo Kyung, E-mail: goldrain99@kaist.ac.kr [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Jeon, Seongchae [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Seo, Chang-Woo [Department of Radiological Science, Yonsei University, Gangwon-do 220-710 (Korea, Republic of)

    2016-09-21

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 µm 1-poly/4-metal CMOS process. The pixel size is 100 µm×100 µm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd{sub 2}O{sub 2}S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  4. Transfer Function and Fluorescence Measurements on New CMOS Pixel Sensor for ATLAS

    CERN Document Server

    Kaemingk, Michael

    2017-01-01

    A new generation of pixel sensors is being designed for the phase II upgrade of the ATLAS Inner Tracker (ITk). These pixel sensors are being tested to ensure that they meet the demands of the ATLAS detector. As a summer student, I was involved in some of the measurements taken for this purpose.

  5. Panoramic imaging perimeter sensor design and modeling

    Energy Technology Data Exchange (ETDEWEB)

    Pritchard, D.A.

    1993-12-31

    This paper describes the conceptual design and preliminary performance modeling of a 360-degree imaging sensor. This sensor combines automatic perimeter intrusion detection with immediate visual assessment and is intended to be used for fast deployment around fixed or temporary high-value assets. The sensor requirements, compiled from various government agencies, are summarized. The conceptual design includes longwave infrared and visible linear array technology. An auxiliary millimeter-wave sensing technology is also considered for use during periods of infrared and visible obscuration. The infrared detectors proposed for the sensor design are similar to the Standard Advanced Dewar Assembly Types Three A and B (SADA-IIIA/B). An overview of the sensor and processor is highlighted. The infrared performance of this sensor design has been predicted using existing thermal imaging system models and is described in the paper. Future plans for developing a prototype are also presented.

  6. Position sensor based on slit imaging

    Institute of Scientific and Technical Information of China (English)

    Aijun Zeng(曾爱军); Xiangzhao Wang(王向朝); Yang Bu(步扬); Dailin Li(李代林)

    2004-01-01

    A position sensor based on slit imaging is proposed and its measurement principle is described.An imaging slit is illuminated by a collimated laser beam with square-wave modulation and imaged on a detection double slit through a 4f system.A magnified image of the detection double slit is formed on a bi-cell detector.The position of the imaging slit is obtained by detecting light intensity on two parts of the bi-cell detector.In experiments,the feasibility of the sensor was verified.The repeatability was less than 40 nm.

  7. Noiseless, kilohertz-frame-rate, imaging detector based on micro-channel plates readout with the Medipix2 CMOS pixel chip

    CERN Document Server

    McPhate, J; Tremsin, A; Siegmund, O; Mikulec, Bettina; Clark, Allan G; CERN. Geneva

    2005-01-01

    A new hybrid imaging detector is described that is being developed for the next generation adaptive optics (AO) wavefront sensors. The detector consists of proximity focused microchannel plates (MCPs) read out by pixelated CMOS application specific integrated circuit (ASIC) chips developed at CERN ("Medipix2"). Each Medipix2 pixel has an amplifier, lower and upper charge discriminators, and a 14-bit chounter. The 256x256 array can be read out noiselessly (photon counting) in 286 us. The Medipix2 is buttable on 3 sides to produce 512x(n*256) pixel devices. The readout can be electronically shuttered down to a terporal window of a few microseconds with an accuracy of 10 ns. Good quantum efficiencies can be achieved from the x-ray (open faced with opaque photocathodes) to the optical (sealed tube with multialkali or GaAs photocathode).

  8. Design and realisation of integrated circuits for the readout of pixel sensors in high-energy physics and biomedical imaging

    Energy Technology Data Exchange (ETDEWEB)

    Peric, I.

    2004-08-01

    Radiation tolerant pixel-readout chip for the ATLAS pixel detector has been designed, implemented in a deep-submicron CMOS technology and successfully tested. The chip contains readout-channels with complex analog and digital circuits. Chip for steering of the DEPFET active-pixel matrix has been implemented in a high-voltage CMOS technology. The chip contains channels which generate fast sequences of high-voltage signals. Detector containing this chip has been successfully tested. Pixel-readout test chip for an X-ray imaging pixel sensor has been designed, implemented in a CMOS technology and tested. Pixel-readout channels are able to simultaneously count the signals generated by passage of individual photons and to sum the total charge generated during exposure time. (orig.)

  9. Color reproductivity improvement with additional virtual color filters for WRGB image sensor

    Science.gov (United States)

    Kawada, Shun; Kuroda, Rihito; Sugawa, Shigetoshi

    2013-02-01

    We have developed a high accuracy color reproduction method based on an estimated spectral reflectance of objects using additional virtual color filters for a wide dynamic range WRGB color filter CMOS image sensor. The four virtual color filters are created by multiplying the spectral sensitivity of White pixel by gauss functions which have different central wave length and standard deviation, and the virtual sensor outputs of those virtual filters are estimated from the four real output signals of the WRGB image sensor. The accuracy of color reproduction was evaluated with a Macbeth Color Checker (MCC), and the averaged value of the color difference ΔEab of 24 colors was 1.88 with our approach.

  10. Onboard Image Processing System for Hyperspectral Sensor

    National Research Council Canada - National Science Library

    Hihara, Hiroki; Moritani, Kotaro; Inoue, Masao; Hoshi, Yoshihiro; Iwasaki, Akira; Takada, Jun; Inada, Hitomi; Suzuki, Makoto; Seki, Taeko; Ichikawa, Satoshi; Tanii, Jun

    2015-01-01

    .... Since more than 100 channels are required for hyperspectral sensors on Earth observation satellites, fast and small-footprint lossless image compression capability is essential for reducing the size...

  11. Performance of a 512 x 512 gated CMOS imager with a 250 ps exposure time

    Science.gov (United States)

    Teruya, Alan T.; Vernon, Stephen P.; Moody, James D.; Hsing, Warren W.; Brown, Christopher G.; Griffin, Matthew; Mead, Andrew S.; Tran, Vu

    2012-10-01

    We describe the performance of a 512x512 gated CMOS read out integrated circuit (ROIC) with a 250 ps exposure time. A low-skew, H-tree trigger distribution system is used to locally generate individual pixel gates in each 8x8 neighborhood of the ROIC. The temporal width of the gate is voltage controlled and user selectable via a precision potentiometer. The gating implementation was first validated in optical tests of a 64x64 pixel prototype ROIC developed as a proof-of-concept during the early phases of the development program. The layout of the H-Tree addresses each quadrant of the ROIC independently and admits operation of the ROIC in two modes. If "common mode" triggering is used, the camera provides a single 512x512 image. If independent triggers are used, the camera can provide up to four 256x256 images with a frame separation set by the trigger intervals. The ROIC design includes small (sub-pixel) optical photodiode structures to allow test and characterization of the ROIC using optical sources prior to bump bonding. Reported test results were obtained using short pulse, second harmonic Ti:Sapphire laser systems operating at λ~ 400 nm at sub-ps pulse widths.

  12. Analysis of EMCCD and sCMOS readout noise models for Shack-Hartmann wavefront sensor accuracy

    CERN Document Server

    Basden, Alastair

    2015-01-01

    In recent years, detectors with sub-electron readout noise have been used very effectively in astronomical adaptive optics systems. Here, we compare readout noise models for the two key faint flux level detector technologies that are commonly used: EMCCD and scientific CMOS (sCMOS) detectors. We find that in almost all situations, EMCCD technology is advantageous, and that the commonly used simplified model for EMCCD readout is appropriate. We also find that the commonly used simple models for sCMOS readout noise are optimistic, and recommend that a proper treatment of the sCMOS rms readout noise probability distribution should be considered during instrument performance modelling and development.

  13. A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.

    Science.gov (United States)

    Huang, Xiwei; Cheong, Jia Hao; Cha, Hyouk-Kyu; Yu, Hongbin; Je, Minkyu; Yu, Hao

    2013-01-01

    One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

  14. Design, Analysis, and Optimization of a CMOS Active Pixel Sensor%CMOS有源像素传感器特性分析与优化设计

    Institute of Scientific and Technical Information of China (English)

    徐江涛; 姚素英; 李斌桥; 史再峰; 高静

    2006-01-01

    A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed. The circuit is embedded in a 64 × 64 pixel array CMOS image sensor and success fully taped out with a Chartered 0.35μm process. The pixel pitch is 8μm × 8μm with a fill factor of 57% ,the photo-sensitivity is 0.8V/(lux · s) ,and the dynamic range is 50dB. Theoretical analysis and test results indicate that as the process is scaled down, a smaller pixel pitch reduces the sensitivity. A deep junction n-well/p-substrate photodiode with a reasonable fill factor and high sensitivity are more appropriate for submicron processes.%设计了一个三管有源像素和其用开关电容放大器实现的双采样读出电路.该电路被嵌入一64×64像素阵列CMOS图像传感器,在Chartered公司0.35μm工艺线上成功流片.在8μm×8μm像素尺寸下实现了57%的填充因子.测得可见光响应灵敏度为0.8V/(lux·s),动态范围为50dB.理论分析和实验结果表明随着工艺尺寸缩小,像素尺寸减小会使光响应灵敏度降低.在深亚微米工艺条件下,较深的n阱/p衬底结光电二极管可以提供合理的填充因子和光响应灵敏度.

  15. Infrared sensor by inkjet printing cytochrome c on suspending aluminum electrodes of post CMOS process

    Science.gov (United States)

    Liang, Shuo-Feng; Yen, Po-Hsien; Su, Guo-Dung John

    2016-09-01

    Cytochrome c protein thin film possesses a high temperature coefficient of resistance. In this paper, we systematically investigated the characteristics of cytochrome c, whose absorption coefficient is 65% at wavelengths of 8 12 μm. We found that the changes in resistance resulted from surface roughness. We also discovered that, while cytochrome c improves the temperature coefficient of resistance, a pure protein solution does not conduct well. It needs a buffer solution, acting as an electrolyte, to increase electrical conductance. However, the buffer solution decreases the temperature coefficient. Therefore, optimization of the ratio of cytochrome c protein to buffer solution is required. We determined the best mixing ratio of the protein solution for a sensing material. We then designed a chip for an infrared microbolometer with a MEMS structure of suspended aluminum electrodes. The protein solution was deposited on the sensing pixel using an inkjet printer. The temperature coefficient of resistance, thermal conductance, time constant and responsivity were 25.98%/K, 7.96 × 10-5 W/K, 1.094 ms and 2.57 × 105 V/W at 2 μA bias current, respectively. We experimentally demonstrated integrating cytochrome c protein with a CMOS circuit as a sensing pixel for a longwavelength infrared microbolometer. Based on our experimental results, such a microbolometer array holds promise for the future.

  16. Development of a multi-analyte CMOS sensor for point-of-care testing

    Directory of Open Access Journals (Sweden)

    Holger Klapproth

    2015-09-01

    Full Text Available A typical microarray experiment requires both a biochip on which the biological reactions take place and a microarray scanner for analysis and visualization of the data. Here, we report on the generation of a chip, which consists of a CMOS photodiode array onto which receptors are immobilized and which are used for the detection and quantification of proteins in sera solution. Such an approach allows direct electronic read-out of the chip via a computer port so that the size of the whole analytical setup is very compact, opening the avenue to the generation of simple handheld devices. ELISA reactions directly performed on the surface of the photodiode arrays are used to measure a number of serum factors with a broad range in concentrations of samples with volumes of less than 10 μl. As in physiological sera analyte concentrations of the different parameters vary frequently by several orders of magnitude, parallel competitive reactions are used to adjust the dynamic range of several ELISA tests on the chip. We show as a demonstration case that this allows to quantify simultaneously C-reactive protein, Immunoglobulin E, Cystatin C, Myoglobin and Ferritin in a single assay.

  17. A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18 μm standard CMOS process

    Science.gov (United States)

    Peng, Feng; Qi, Zhang; Nanjian, Wu

    2011-11-01

    This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor, an RF/analog front-end circuit, an NVM memory and a digital baseband in a standard CMOS process. The sensor with a low power sigma—delta (ΣΔ) ADC is designed to operate in low and high resolution modes. It can not only achieve the target accuracy but also reduce the power consumption and the sensing time. A CMOS-only RF rectifier and a single-poly non-volatile memory (NVM) are designed to realize a low cost tag chip. The 192-bit-NVM tag chip with an area of 1 mm2 is implemented in a 0.18-μm standard CMOS process. The sensitivity of the tag is -10.7 dBm/-8.4 dBm when the sensor is disabled/enabled. It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP. The inaccuracy of the sensor is -0.6 °C/0.5 °C (-1.0 °C/1.2 °C) in the operating range from 5 to 15 °C in high resolution mode (-30 to 50 °C in low resolution mode). The resolution of the sensor achieves 0.02 °C (0.18 °C) in high (low) resolution mode.

  18. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Directory of Open Access Journals (Sweden)

    Rescigno R.

    2014-03-01

    Full Text Available Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  19. Simulation toolkit with CMOS detector in the framework of hadrontherapy

    Science.gov (United States)

    Rescigno, R.; Finck, Ch.; Juliani, D.; Baudot, J.; Dauvergne, D.; Dedes, G.; Krimmer, J.; Ray, C.; Reithinger, V.; Rousseau, M.; Testa, E.; Winter, M.

    2014-03-01

    Proton imaging can be seen as a powerful technique for on-line monitoring of ion range during carbon ion therapy irradiation. The protons detection technique uses, as three-dimensional tracking system, a set of CMOS sensor planes. A simulation toolkit based on GEANT4 and ROOT is presented including detector response and reconstruction algorithm.

  20. Evaluation of dual-wavelength excitation autofluorescence imaging of colorectal tumours with a high-sensitivity CMOS imager: a cross-sectional study.

    Science.gov (United States)

    Kominami, Yoko; Yoshida, Shigeto; Tanaka, Shinji; Miyaki, Rie; Sanomura, Yoji; Seo, Min-Woong; Kagawa, Keiichiro; Kawahito, Shoji; Arimoto, Hidenobu; Yamada, Kenji; Chayama, Kazuaki

    2015-09-02

    It is important to devise efficient and easy methods of detecting colorectal tumours to reduce mortality from colorectal cancer. Dual-wavelength excitation autofluorescence intensity can be used to visualize colorectal tumours. Therefore, we evaluated dual-wavelength excitation autofluorescence images of colorectal tumours obtained with a newly developed, high-sensitivity complementary metal-oxide-semiconductor (CMOS) imager. A total 107 colorectal tumours (44 adenomas, 43 adenocarcinomas with intramucosal invasion, and 20 sessile serrated adenoma/polyps [SSA/Ps]) in 98 patients who underwent endoscopic tumour resection were included. The specimens were irradiated with excitation light at 365 nm and 405 nm, and autofluorescence images measured with a 475 ± 25-nm band pass filter were obtained using a new, high-sensitivity CMOS imager. Ratio images (F365ex/F405ex) were created to evaluate the lesion brightness compared with that of normal mucosa, and specimens were categorized into a no signal or high signal group. Adenomas and adenocarcinomas were depicted in 87 ratio images, with 86.2% (n = 75) in the High signal group. SSA/P was depicted in 20 ratio images, with 70.0% (n = 14) in the High signal group. Dual-wavelength excitation autofluorescence images of colorectal tumours can be acquired using our high-sensitivity CMOS imager, and are useful in detecting colorectal tumours.

  1. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  2. CMOS integrated avalanche photodiodes and frequency-mixing optical sensor front end for portable NIR spectroscopy instruments.

    Science.gov (United States)

    Yun, Ruida; Sthalekar, Chirag; Joyner, Valencia M

    2011-01-01

    This paper presents the design and measurement results of two avalanche photodiode structures (APDs) and a novel frequency-mixing transimpedance amplifier (TIA), which are key building blocks towards a monolithically integrated optical sensor front end for near-infrared (NIR) spectroscopy applications. Two different APD structures are fabricated in an unmodified 0.18 \\im CMOS process, one with a shallow trench isolation (STI) guard ring and the other with a P-well guard ring. The APDs are characterized in linear mode. The STI bounded APD demonstrates better performance and exhibits 3.78 A/W responsivity at a wavelength of 690 nm and bias voltage of 10.55 V. The frequency-mixing TIA (FM-TIA) employs a T-feedback network incorporating gate-controlled transistors for resistance modulation, enabling the simultaneous down-conversion and amplification of the high frequency modulated photodiode (PD) current. The TIA achieves 92 dS Ω conversion gain with 0.5 V modulating voltage. The measured IIP(3) is 10.6/M. The amplifier together with the 50 Ω output buffer draws 23 mA from a1.8 V power supply.

  3. Experimental comparison of the high-speed imaging performance of an EM-CCD and sCMOS camera in a dynamic live-cell imaging test case.

    Directory of Open Access Journals (Sweden)

    Hope T Beier

    Full Text Available The study of living cells may require advanced imaging techniques to track weak and rapidly changing signals. Fundamental to this need is the recent advancement in camera technology. Two camera types, specifically sCMOS and EM-CCD, promise both high signal-to-noise and high speed (>100 fps, leaving researchers with a critical decision when determining the best technology for their application. In this article, we compare two cameras using a live-cell imaging test case in which small changes in cellular fluorescence must be rapidly detected with high spatial resolution. The EM-CCD maintained an advantage of being able to acquire discernible images with a lower number of photons due to its EM-enhancement. However, if high-resolution images at speeds approaching or exceeding 1000 fps are desired, the flexibility of the full-frame imaging capabilities of sCMOS is superior.

  4. A novel design of subminiature star sensor's imaging system based on TMS320DM3730

    Science.gov (United States)

    Liu, Meiying; Wang, Hu; Wen, Desheng; Yang, Shaodong

    2017-02-01

    Development of the next generation star sensor is tending to miniaturization, low cost and low power consumption, so the imaging system based on FPGA in the past could not meet its developing requirements. A novel design of digital imaging system is discussed in this paper. Combined with the MT9P031 CMOS image sensor's timing sequence and working mode, the sensor driving circuit and image data memory circuit were implemented with the main control unit TMS320DM3730. In order to make the hardware system has the advantage of small size and light weight, the hardware adopted miniaturization design. The software simulation and experimental results demonstrated that the designed imaging system was reasonable, the function of tunable integration time and selectable window readout modes were realized. The communication with computer was exact. The system has the advantage of the powerful image processing, small-size, compact, stable, reliable and low power consumption. The whole system volume is 40 mm *40 mm *40mm,the system weight is 105g, the system power consumption is lower than 1w. This design provided a feasible solution for the realization of the subminiature star sensor's imaging system.

  5. Radiation tolerant compact image sensor using CdTe photodiode and field emitter array (Conference Presentation)

    Science.gov (United States)

    Masuzawa, Tomoaki; Neo, Yoichiro; Mimura, Hidenori; Okamoto, Tamotsu; Nagao, Masayoshi; Akiyoshi, Masafumi; Sato, Nobuhiro; Takagi, Ikuji; Tsuji, Hiroshi; Gotoh, Yasuhito

    2016-10-01

    A growing demand on incident detection is recognized since the Great East Japan Earthquake and successive accidents in Fukushima nuclear power plant in 2011. Radiation tolerant image sensors are powerful tools to collect crucial information at initial stages of such incidents. However, semiconductor based image sensors such as CMOS and CCD have limited tolerance to radiation exposure. Image sensors used in nuclear facilities are conventional vacuum tubes using thermal cathodes, which have large size and high power consumption. In this study, we propose a compact image sensor composed of a CdTe-based photodiode and a matrix-driven Spindt-type electron beam source called field emitter array (FEA). A basic principle of FEA-based image sensors is similar to conventional Vidicon type camera tubes, but its electron source is replaced from a thermal cathode to FEA. The use of a field emitter as an electron source should enable significant size reduction while maintaining high radiation tolerance. Current researches on radiation tolerant FEAs and development of CdTe based photoconductive films will be presented.

  6. Giga-pixel lensfree holographic microscopy and tomography using color image sensors.

    Directory of Open Access Journals (Sweden)

    Serhan O Isikman

    Full Text Available We report Giga-pixel lensfree holographic microscopy and tomography using color sensor-arrays such as CMOS imagers that exhibit Bayer color filter patterns. Without physically removing these color filters coated on the sensor chip, we synthesize pixel super-resolved lensfree holograms, which are then reconstructed to achieve ~350 nm lateral resolution, corresponding to a numerical aperture of ~0.8, across a field-of-view of ~20.5 mm(2. This constitutes a digital image with ~0.7 Billion effective pixels in both amplitude and phase channels (i.e., ~1.4 Giga-pixels total. Furthermore, by changing the illumination angle (e.g., ± 50° and scanning a partially-coherent light source across two orthogonal axes, super-resolved images of the same specimen from different viewing angles are created, which are then digitally combined to synthesize tomographic images of the object. Using this dual-axis lensfree tomographic imager running on a color sensor-chip, we achieve a 3D spatial resolution of ~0.35 µm × 0.35 µm × ~2 µm, in x, y and z, respectively, creating an effective voxel size of ~0.03 µm(3 across a sample volume of ~5 mm(3, which is equivalent to >150 Billion voxels. We demonstrate the proof-of-concept of this lensfree optical tomographic microscopy platform on a color CMOS image sensor by creating tomograms of micro-particles as well as a wild-type C. elegans nematode.

  7. Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

    Science.gov (United States)

    Dey, Samrat; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2012-01-01

    Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs).

  8. 14-bit pipeline-SAR ADC for image sensor readout circuits

    Science.gov (United States)

    Wang, Gengyun; Peng, Can; Liu, Tianzhao; Ma, Cheng; Ding, Ning; Chang, Yuchun

    2015-03-01

    A two stage 14bit pipeline-SAR analog-to-digital converter includes a 5.5bit zero-crossing MDAC and a 9bit asynchronous SAR ADC for image sensor readout circuits built in 0.18um CMOS process is described with low power dissipation as well as small chip area. In this design, we employ comparators instead of high gain and high bandwidth amplifier, which consumes as low as 20mW of power to achieve the sampling rate of 40MSps and 14bit resolution.

  9. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

    Science.gov (United States)

    Aull, Brian

    2016-04-08

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  10. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    Directory of Open Access Journals (Sweden)

    Brian Aull

    2016-04-01

    Full Text Available This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  11. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    OpenAIRE

    Brian Aull

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  12. Charged particle detection performances of CMOS pixel sensors produced in a 0.18 um process with a high resistivity epitaxial layer

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Gilles; Cousin, Loic; Dorokhov, Andrei; Dulinski, Wojciech; Goffe, Mathieu; Hu-Guo, Christine; Winter, Marc

    2013-01-01

    The apparatus of the ALICE experiment at CERN will be upgraded in 2017/18 during the second long shutdown of the LHC (LS2). A major motivation for this upgrade is to extend the physics reach for charmed and beauty particles down to low transverse momenta. This requires a substantial improvement of the spatial resolution and the data rate capability of the ALICE Inner Tracking System (ITS). To achieve this goal, the new ITS will be equipped with 50 um thin CMOS Pixel Sensors (CPS) covering either the 3 innermost layers or all the 7 layers of the detector. The CPS being developed for the ITS upgrade at IPHC (Strasbourg) is derived from the MIMOSA 28 sensor realised for the STAR-PXL at RHIC in a 0.35 um CMOS process. In order to satisfy the ITS upgrade requirements in terms of readout speed and radiation tolerance, a CMOS process with a reduced feature size and a high resistivity epitaxial layer should be exploited. In this respect, the charged particle detection performance and radiation hardness of the TowerJa...

  13. Micromachined thin-film sensors for SOI-CMOS co-integration

    CERN Document Server

    Laconte, Jean; Raskin, Jean-Pierre

    2006-01-01

    Co-integration of MEMS and MOS in SOI technology is promising and well demonstrated hereThe impact of Micromachining on SOI devices is deeply analyzed for the first timeInclude extensive TMAH etching, residual stress, microheaters, gas-flow sensors reviewResidual stresses in thin films need to be more and more monitored in MEMS designsTMAH micromachining is an attractive alternative to KOH.

  14. Low temperature co-fired ceramic packaging of CMOS capacitive sensor chip towards cell viability monitoring

    Directory of Open Access Journals (Sweden)

    Niina Halonen

    2016-11-01

    Full Text Available Cell viability monitoring is an important part of biosafety evaluation for the detection of toxic effects on cells caused by nanomaterials, preferably by label-free, noninvasive, fast, and cost effective methods. These requirements can be met by monitoring cell viability with a capacitance-sensing integrated circuit (IC microchip. The capacitance provides a measurement of the surface attachment of adherent cells as an indication of their health status. However, the moist, warm, and corrosive biological environment requires reliable packaging of the sensor chip. In this work, a second generation of low temperature co-fired ceramic (LTCC technology was combined with flip-chip bonding to provide a durable package compatible with cell culture. The LTCC-packaged sensor chip was integrated with a printed circuit board, data acquisition device, and measurement-controlling software. The packaged sensor chip functioned well in the presence of cell medium and cells, with output voltages depending on the medium above the capacitors. Moreover, the manufacturing of microfluidic channels in the LTCC package was demonstrated.

  15. CMOS-Based Biosensor Arrays

    CERN Document Server

    Thewes, R; Schienle, M; Hofmann, F; Frey, A; Brederlow, R; Augustyniak, M; Jenkner, M; Eversmann, B; Schindler-Bauer, P; Atzesberger, M; Holzapfl, B; Beer, G; Haneder, T; Hanke, H -C

    2011-01-01

    CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

  16. High dynamic range imaging sensors and architectures

    CERN Document Server

    Darmont, Arnaud

    2013-01-01

    Illumination is a crucial element in many applications, matching the luminance of the scene with the operational range of a camera. When luminance cannot be adequately controlled, a high dynamic range (HDR) imaging system may be necessary. These systems are being increasingly used in automotive on-board systems, road traffic monitoring, and other industrial, security, and military applications. This book provides readers with an intermediate discussion of HDR image sensors and techniques for industrial and non-industrial applications. It describes various sensor and pixel architectures capable

  17. Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

    Directory of Open Access Journals (Sweden)

    Jong-Ryul Yang

    2016-03-01

    Full Text Available A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

  18. Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System.

    Science.gov (United States)

    Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

    2016-03-02

    A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

  19. A 9 megapixel large-area back-thinned CMOS sensor with high sensitivity and high frame-rate for the TAOS II program

    Science.gov (United States)

    Pratlong, Jérôme; Wang, Shiang-Yu; Lehner, Matthew; Jorden, Paul; Jerram, Paul; Johnson, Steven

    2016-07-01

    The Transneptunian Automated Occultation Survey (TAOS II) is a robotic telescope system using three telescopes in San Pedro Martir Observatory in Mexico. It measures occultation of background stars by small TransNeptunian Objects (TNO) in order to determine their size distribution. Each telescope focal plane uses ten buttable backthinned CMOS sensors. Key performance features of the sensors are: Large array format 4608 x 1920, Pixel size 16μm, Multi ROIs, 8 analogue video channels, Frame rate of 20-40 fps [using ROIs], Low noise 90% peak quantum efficiency. The paper describes top level application requirements for the TAOS II detector. The sensor design including the pixel and buttable package are described together with performance at room temperature and cryogenic temperature of backthinned devices. The key performance specifications have been demonstrated and will be presented. The production set of 40 devices are due for completion within 2017.

  20. A new interpolating method based on the variation of spectra energy using CMOS array

    Institute of Scientific and Technical Information of China (English)

    Tianjin Tang; Xiangqun Cao; Hongqiu Chen; Bin Lin

    2005-01-01

    @@ A new interpolating method to enhance the resolution of gratings using complementary metal-oxide semiconductor (CMOS) according to the variation of some specified spectral light intensities during the motion of scale grating in a periodic separation is proposed. CMOS image sensor (pixel array 648 × 488) was also introduced as receiving device and its stability was verified experimentally. Many factors in the experiment were analyzed theoretically and contrasted with experiment. The advantages of this novel method were featured by CMOS and the specified spectral variation of the energy distribution was discussed.