WorldWideScience

Sample records for classified-data processor device

  1. Digital signal processor for silicon audio playback devices; Silicon audio saisei kikiyo digital signal processor

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital audio signal processor (DSP) TC9446F series has been developed silicon audio playback devices with a memory medium of, e.g., flash memory, DVD players, and AV devices, e.g., TV sets. It corresponds to AAC (advanced audio coding) (2ch) and MP3 (MPEG1 Layer3), as the audio compressing techniques being used for transmitting music through an internet. It also corresponds to compressed types, e.g., Dolby Digital, DTS (digital theater system) and MPEG2 audio, being adopted for, e.g., DVDs. It can carry a built-in audio signal processing program, e.g., Dolby ProLogic, equalizer, sound field controlling, and 3D sound. TC9446XB has been lined up anew. It adopts an FBGA (fine pitch ball grid array) package for portable audio devices. (translated by NEDO)

  2. Adaptive Motion Estimation Processor for Autonomous Video Devices

    Directory of Open Access Journals (Sweden)

    Dias T

    2007-01-01

    Full Text Available Motion estimation is the most demanding operation of a video encoder, corresponding to at least 80% of the overall computational cost. As a consequence, with the proliferation of autonomous and portable handheld devices that support digital video coding, data-adaptive motion estimation algorithms have been required to dynamically configure the search pattern not only to avoid unnecessary computations and memory accesses but also to save energy. This paper proposes an application-specific instruction set processor (ASIP to implement data-adaptive motion estimation algorithms that is characterized by a specialized datapath and a minimum and optimized instruction set. Due to its low-power nature, this architecture is highly suitable to develop motion estimators for portable, mobile, and battery-supplied devices. Based on the proposed architecture and the considered adaptive algorithms, several motion estimators were synthesized both for a Virtex-II Pro XC2VP30 FPGA from Xilinx, integrated within an ML310 development platform, and using a StdCell library based on a 0.18 μm CMOS process. Experimental results show that the proposed architecture is able to estimate motion vectors in real time for QCIF and CIF video sequences with a very low-power consumption. Moreover, it is also able to adapt the operation to the available energy level in runtime. By adjusting the search pattern and setting up a more convenient operating frequency, it can change the power consumption in the interval between 1.6 mW and 15 mW.

  3. Next generation Associative Memory devices for the FTK tracking processor of the ATLAS experiment

    CERN Document Server

    Andreani, A; The ATLAS collaboration; Beccherle, B; Beretta, M; Citterio, M; Crescioli, F; Colombo, A; Giannetti, P; Liberali, V; Shojaii, J; Stabile, A

    2013-01-01

    The AMchip is a VLSI device that implements the associative memory function, a special content addressable memory specifically designed for high energy physics applications and first used in the CDF experiment at Tevatron. The 4th generation of AMchip has been developed for the core pattern recognition stage of the Fast TracKer (FTK) processor: a hardware processor for online reconstruction of particle trajectories at the ATLAS experiment at LHC. We present the architecture, design considerations, power consumption and performance measurements of the 4th generation of AMchip. We present also the design innovations toward the 5th generation and the first prototype results.

  4. Study of low insertion loss and miniaturization wavelet transform and inverse transform processor using SAW devices.

    Science.gov (United States)

    Jiang, Hua; Lu, Wenke; Zhang, Guoan

    2013-07-01

    In this paper, we propose a low insertion loss and miniaturization wavelet transform and inverse transform processor using surface acoustic wave (SAW) devices. The new SAW wavelet transform devices (WTDs) use the structure with two electrode-widths-controlled (EWC) single phase unidirectional transducers (SPUDT-SPUDT). This structure consists of the input withdrawal weighting interdigital transducer (IDT) and the output overlap weighting IDT. Three experimental devices for different scales 2(-1), 2(-2), and 2(-3) are designed and measured. The minimum insertion loss of the three devices reaches 5.49dB, 4.81dB, and 5.38dB respectively which are lower than the early results. Both the electrode width and the number of electrode pairs are reduced, thus making the three devices much smaller than the early devices. Therefore, the method described in this paper is suitable for implementing an arbitrary multi-scale low insertion loss and miniaturization wavelet transform and inverse transform processor using SAW devices. Copyright © 2013 Elsevier B.V. All rights reserved.

  5. A novel compensation method of insertion losses for wavelet inverse-transform processors using surface acoustic wave devices.

    Science.gov (United States)

    Lu, Wenke; Zhu, Changchun

    2011-11-01

    The objective of this research was to investigate the possibility of compensating for the insertion losses of the wavelet inverse-transform processors using SAW devices. The motivation for this work was prompted by the processors which are of large insertion losses. In this paper, the insertion losses are the key problem of the wavelet inverse-transform processors using SAW devices. A novel compensation method of the insertion losses is achieved in this study. When the output ends of the wavelet inverse-transform processors are respectively connected to the amplifiers, their insertion losses can be compensated for. The bandwidths of the amplifiers and their adjustment method are also given in this paper. © 2011 American Institute of Physics

  6. Research on two-port network of wavelet transform processor using surface acoustic wavelet devices and its application.

    Science.gov (United States)

    Liu, Shoubing; Lu, Wenke; Zhu, Changchun

    2017-11-01

    The goal of this research is to study two-port network of wavelet transform processor (WTP) using surface acoustic wave (SAW) devices and its application. The motive was prompted by the inconvenience of the long research and design cycle and the huge research funding involved with traditional method in this field, which were caused by the lack of the simulation and emulation method of WTP using SAW devices. For this reason, we introduce the two-port network analysis tool, which has been widely used in the design and analysis of SAW devices with uniform interdigital transducers (IDTs). Because the admittance parameters calculation formula of the two-port network can only be used for the SAW devices with uniform IDTs, this analysis tool cannot be directly applied into the design and analysis of the processor using SAW devices, whose input interdigital transducer (IDT) is apodized weighting. Therefore, in this paper, we propose the channel segmentation method, which can convert the WTP using SAW devices into parallel channels, and also provide with the calculation formula of the number of channels, the number of finger pairs and the static capacitance of an interdigital period in each parallel channel firstly. From the parameters given above, we can calculate the admittance parameters of the two port network for each channel, so that we can obtain the admittance parameter of the two-port network of the WTP using SAW devices on the basis of the simplification rule of parallel two-port network. Through this analysis tool, not only can we get the impulse response function of the WTP using SAW devices but we can also get the matching circuit of it. Large numbers of studies show that the parameters of the two-port network obtained by this paper are consistent with those measured by network analyzer E5061A, and the impulse response function obtained by the two-port network analysis tool is also consistent with that measured by network analyzer E5061A, which can meet the

  7. Solution to the influence of the MSSW propagating velocity on the bandwidths of the single-scale wavelet-transform processor using MSSW device.

    Science.gov (United States)

    Lu, Wenke; Zhu, Changchun; Kuang, Lun; Zhang, Ting; Zhang, Jingduan

    2012-01-01

    The objective of this research was to investigate the possibility of solving the influence of the magnetostatic surface wave (MSSW) propagating velocity on the bandwidths of the single-scale wavelet transform processor using MSSW device. The motivation for this work was prompted by the processor that -3dB bandwidth varies as the propagating velocity of MSSW changes. In this paper, we present the influence of the magnetostatic surface wave (MSSW) propagating velocity on the bandwidths as the key problem of the single-scale wavelet transform processor using MSSW device. The solution to the problem is achieved in this study. we derived the function between the propagating velocity of MSSW and the -3dB bandwidth, so we know from the function that -3dB bandwidth of the single-scale wavelet transform processor using MSSW device varies as the propagating velocity of MSSW changes. Through adjusting the distance and orientation of the permanent magnet, we can implement the control of the MSSW propagating velocity, so that the influence of the MSSW propagating velocity on the bandwidths of the single-scale wavelet transform processor using MSSW device is solved. Copyright © 2011 Elsevier B.V. All rights reserved.

  8. THE SEMICONDUCTOR THERMOELECTRIC DEVICE FOR TEMPERATURE CONTROL OF COMPUTER PROCESSOR WITH USE OF MATERIALS IN THE CONDITION OF PHASE TRANSITION

    Directory of Open Access Journals (Sweden)

    H. M. Gadjiyev

    2015-01-01

    Full Text Available The article deals with the cooling system computer processor on the based sublimation phase transitions, allowing to provide temperature control mode in a transient thermal load, which will prevent the failure of the VLSI processor

  9. Accuracy-energy configurable sensor processor and IoT device for long-term activity monitoring in rare-event sensing applications.

    Science.gov (United States)

    Park, Daejin; Cho, Jeonghun

    2014-01-01

    A specially designed sensor processor used as a main processor in IoT (internet-of-thing) device for the rare-event sensing applications is proposed. The IoT device including the proposed sensor processor performs the event-driven sensor data processing based on an accuracy-energy configurable event-quantization in architectural level. The received sensor signal is converted into a sequence of atomic events, which is extracted by the signal-to-atomic-event generator (AEG). Using an event signal processing unit (EPU) as an accelerator, the extracted atomic events are analyzed to build the final event. Instead of the sampled raw data transmission via internet, the proposed method delays the communication with a host system until a semantic pattern of the signal is identified as a final event. The proposed processor is implemented on a single chip, which is tightly coupled in bus connection level with a microcontroller using a 0.18 μm CMOS embedded-flash process. For experimental results, we evaluated the proposed sensor processor by using an IR- (infrared radio-) based signal reflection and sensor signal acquisition system. We successfully demonstrated that the expected power consumption is in the range of 20% to 50% compared to the result of the basement in case of allowing 10% accuracy error.

  10. Accuracy-Energy Configurable Sensor Processor and IoT Device for Long-Term Activity Monitoring in Rare-Event Sensing Applications

    Directory of Open Access Journals (Sweden)

    Daejin Park

    2014-01-01

    Full Text Available A specially designed sensor processor used as a main processor in IoT (internet-of-thing device for the rare-event sensing applications is proposed. The IoT device including the proposed sensor processor performs the event-driven sensor data processing based on an accuracy-energy configurable event-quantization in architectural level. The received sensor signal is converted into a sequence of atomic events, which is extracted by the signal-to-atomic-event generator (AEG. Using an event signal processing unit (EPU as an accelerator, the extracted atomic events are analyzed to build the final event. Instead of the sampled raw data transmission via internet, the proposed method delays the communication with a host system until a semantic pattern of the signal is identified as a final event. The proposed processor is implemented on a single chip, which is tightly coupled in bus connection level with a microcontroller using a 0.18 μm CMOS embedded-flash process. For experimental results, we evaluated the proposed sensor processor by using an IR- (infrared radio- based signal reflection and sensor signal acquisition system. We successfully demonstrated that the expected power consumption is in the range of 20% to 50% compared to the result of the basement in case of allowing 10% accuracy error.

  11. Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Luis Parrilla

    2018-01-01

    Full Text Available Security is a critical challenge for the effective expansion of all new emerging applications in the Internet of Things paradigm. Therefore, it is necessary to define and implement different mechanisms for guaranteeing security and privacy of data interchanged within the multiple wireless sensor networks being part of the Internet of Things. However, in this context, low power and low area are required, limiting the resources available for security and thus hindering the implementation of adequate security protocols. Group keys can save resources and communications bandwidth, but should be combined with public key cryptography to be really secure. In this paper, a compact and unified co-processor for enabling Elliptic Curve Cryptography along to Advanced Encryption Standard with low area requirements and Group-Key support is presented. The designed co-processor allows securing wireless sensor networks with independence of the communications protocols used. With an area occupancy of only 2101 LUTs over Spartan 6 devices from Xilinx, it requires 15% less area while achieving near 490% better performance when compared to cryptoprocessors with similar features in the literature.

  12. Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks.

    Science.gov (United States)

    Parrilla, Luis; Castillo, Encarnación; López-Ramos, Juan A; Álvarez-Bermejo, José A; García, Antonio; Morales, Diego P

    2018-01-16

    Security is a critical challenge for the effective expansion of all new emerging applications in the Internet of Things paradigm. Therefore, it is necessary to define and implement different mechanisms for guaranteeing security and privacy of data interchanged within the multiple wireless sensor networks being part of the Internet of Things. However, in this context, low power and low area are required, limiting the resources available for security and thus hindering the implementation of adequate security protocols. Group keys can save resources and communications bandwidth, but should be combined with public key cryptography to be really secure. In this paper, a compact and unified co-processor for enabling Elliptic Curve Cryptography along to Advanced Encryption Standard with low area requirements and Group-Key support is presented. The designed co-processor allows securing wireless sensor networks with independence of the communications protocols used. With an area occupancy of only 2101 LUTs over Spartan 6 devices from Xilinx, it requires 15% less area while achieving near 490% better performance when compared to cryptoprocessors with similar features in the literature.

  13. Multithreaded Processors

    Indian Academy of Sciences (India)

    Home; Journals; Resonance – Journal of Science Education; Volume 20; Issue 9. Multithreaded Processors. Venkat Arun. General Article Volume 20 Issue 9 September 2015 pp 844-855. Fulltext. Click here to view fulltext PDF. Permanent link: http://www.ias.ac.in/article/fulltext/reso/020/09/0844-0855. Keywords.

  14. 21 CFR 892.1900 - Automatic radiographic film processor.

    Science.gov (United States)

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Automatic radiographic film processor. 892.1900 Section 892.1900 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... processor. (a) Identification. An automatic radiographic film processor is a device intended to be used to...

  15. Testing and operating a multiprocessor chip with processor redundancy

    Science.gov (United States)

    Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

    2014-10-21

    A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

  16. Spaceborne Processor Array

    Science.gov (United States)

    Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

    2008-01-01

    A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

  17. Development of the integrated methanol fuel processor using micro-channel patterned devices and its performance for steam reforming of methanol

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, Jung Min [Department of Mineral Resources and Energy Engineering, Chonbuk Nat' l University, 664-14 Duckjin-dong, Duckjin-gu, Jeonju, Jeonbuk, 561-756 (Korea); Chang Byun, Young; Yeon Cho, Jun; Choe, Jaehoon [LG Chem, Ltd./Research Park, 104-1, Moonji-dong Yuseong-gu Daejeon, 305-380 (Korea); Ho Song, Kwang [Department of Chemical and Biological Engineering, Korea University, Seoul 136-713 (Korea)

    2007-12-15

    A plate-type integrated fuel processor consisting of three different micro-structured modules was developed for hydrogen production in a 150 W PEMFC system. This system includes a reformer with combustor, two heat exchangers, and an evaporator with a combustor. Methanol steam reforming was chosen as a means to produce hydrogen for the PEMFC system. This system could be operated without any external heat supply. Hydrogen was used as the initial combustion fuel during startup, while methanol was used later. Cu/Zn/Al{sub 2}O{sub 3} and Pt/Al{sub 2}O{sub 3} catalysts were chosen for the steam reforming of methanol and the combustion, respectively, and coated on microchannel-patterned stainless steel sheets. The integrated system was operated consistently with 80% of methanol conversion at 300 {sup circle} C for 20 h without deactivation of the catalysts. The production rate on dry basis and the composition of hydrogen was 2.4NL-{sup -1} and ca 70%, respectively. Overall the thermal efficiency of this fuel processor based on the LHV was 56.7%. (author)

  18. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  19. Multithreading in vector processors

    Energy Technology Data Exchange (ETDEWEB)

    Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

    2018-01-16

    In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

  20. Limit characteristics of digital optoelectronic processor

    Science.gov (United States)

    Kolobrodov, V. G.; Tymchik, G. S.; Kolobrodov, M. S.

    2018-01-01

    In this article, the limiting characteristics of a digital optoelectronic processor are explored. The limits are defined by diffraction effects and a matrix structure of the devices for input and output of optical signals. The purpose of a present research is to optimize the parameters of the processor's components. The developed physical and mathematical model of DOEP allowed to establish the limit characteristics of the processor, restricted by diffraction effects and an array structure of the equipment for input and output of optical signals, as well as to optimize the parameters of the processor's components. The diameter of the entrance pupil of the Fourier lens is determined by the size of SLM and the pixel size of the modulator. To determine the spectral resolution, it is offered to use a concept of an optimum phase when the resolved diffraction maxima coincide with the pixel centers of the radiation detector.

  1. Array processors in chemistry

    Energy Technology Data Exchange (ETDEWEB)

    Ostlund, N.S.

    1980-01-01

    The field of attached scientific processors (''array processors'') is surveyed, and an attempt is made to indicate their present and possible future use in computational chemistry. The current commercial products from Floating Point Systems, Inc., Datawest Corporation, and CSP, Inc. are discussed.

  2. DMS processor evolution study

    Science.gov (United States)

    Liu, Yuan-Kwei

    1990-01-01

    Increasing the processor performance and capability has not only become a wish list item for the Space Station Freedom (SSF) Data Management System (DMS), but also a necessity. There are many commercially available processors which have superior performance compared to the 386, but we cannot only consider performance when selecting a processor for the DMS. The processor is the 'foundation' of the DMS. It will affect the local bus, system bus, interface unit, global network, etc., that have been selected for the DMS. Besides, once the processor instruction set architecture (ISA) is selected, all of the important system software will be implemented based on this ISA. Selecting an ISA that has a strong commercial support and can be upgraded in the 30-year life cycle of the Space Station Freedom is one of the most important items for the DMS.

  3. Optoelectronic correlation processors with photorefractive crystals for the storage elements

    Directory of Open Access Journals (Sweden)

    Lipinskii A. Y.

    2011-12-01

    Full Text Available The paper presents review of optical and acousto-optic correlation processors that contain photorefractive crystals. Optical correlators are the efficient devices for the image recognition due to the parallel way high operation rate processing of significant data amount. The shift-invariant holographic joint-transform correlators, dynamic holographic correlator, acousto-optic correlation processors with memory were considered.

  4. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...

  5. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    ... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...

  6. Graphics Processor Units (GPUs)

    Science.gov (United States)

    Wyrwas, Edward J.

    2017-01-01

    This presentation will include information about Graphics Processor Units (GPUs) technology, NASA Electronic Parts and Packaging (NEPP) tasks, The test setup, test parameter considerations, lessons learned, collaborations, a roadmap, NEPP partners, results to date, and future plans.

  7. Noise limitations in optical linear algebra processors.

    Science.gov (United States)

    Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

    1990-05-10

    A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

  8. Array processor architecture

    Science.gov (United States)

    Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

    1983-01-01

    A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

  9. Functional unit for a processor

    NARCIS (Netherlands)

    Rohani, A.; Kerkhoff, Hans G.

    2013-01-01

    The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

  10. First Results of an "Artificial Retina" Processor Prototype

    Science.gov (United States)

    Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John

    2016-11-01

    We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called "artificial retina algorithm", inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate.

  11. Programmable DNA-Mediated Multitasking Processor.

    Science.gov (United States)

    Shu, Jian-Jun; Wang, Qi-Wen; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

    2015-04-30

    Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

  12. Configurable Multi-Purpose Processor

    Science.gov (United States)

    Valencia, J. Emilio; Forney, Chirstopher; Morrison, Robert; Birr, Richard

    2010-01-01

    Advancements in technology have allowed the miniaturization of systems used in aerospace vehicles. This technology is driven by the need for next-generation systems that provide reliable, responsive, and cost-effective range operations while providing increased capabilities such as simultaneous mission support, increased launch trajectories, improved launch, and landing opportunities, etc. Leveraging the newest technologies, the command and telemetry processor (CTP) concept provides for a compact, flexible, and integrated solution for flight command and telemetry systems and range systems. The CTP is a relatively small circuit board that serves as a processing platform for high dynamic, high vibration environments. The CTP can be reconfigured and reprogrammed, allowing it to be adapted for many different applications. The design is centered around a configurable field-programmable gate array (FPGA) device that contains numerous logic cells that can be used to implement traditional integrated circuits. The FPGA contains two PowerPC processors running the Vx-Works real-time operating system and are used to execute software programs specific to each application. The CTP was designed and developed specifically to provide telemetry functions; namely, the command processing, telemetry processing, and GPS metric tracking of a flight vehicle. However, it can be used as a general-purpose processor board to perform numerous functions implemented in either hardware or software using the FPGA s processors and/or logic cells. Functionally, the CTP was designed for range safety applications where it would ultimately become part of a vehicle s flight termination system. Consequently, the major functions of the CTP are to perform the forward link command processing, GPS metric tracking, return link telemetry data processing, error detection and correction, data encryption/ decryption, and initiate flight termination action commands. Also, the CTP had to be designed to survive and

  13. Reconfigurable signal processor designs for advanced digital array radar systems

    Science.gov (United States)

    Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

    2017-05-01

    The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

  14. Beyond processor sharing

    NARCIS (Netherlands)

    S. Aalto; U. Ayesta (Urtzi); S.C. Borst (Sem); V. Misra; R. Núñez Queija (Rudesindo (Sindo))

    2007-01-01

    textabstractWhile the (Egalitarian) Processor-Sharing (PS) discipline offers crucial insights in the performance of fair resource allocation mechanisms, it is inherently limited in analyzing and designing differentiated scheduling algorithms such as Weighted Fair Queueing and Weighted Round-Robin.

  15. Ultra Dependable Processor

    Science.gov (United States)

    Sakai, Shuichi; Goshima, Masahiro; Irie, Hidetsugu

    This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.

  16. The Central Trigger Processor (CTP)

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

  17. Processor register error correction management

    Energy Technology Data Exchange (ETDEWEB)

    Bose, Pradip; Cher, Chen-Yong; Gupta, Meeta S.

    2016-12-27

    Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

  18. A Domain Specific DSP Processor

    OpenAIRE

    Tell, Eric

    2001-01-01

    This thesis describes the design of a domain specific DSP processor. The thesis is divided into two parts. The first part gives some theoretical background, describes the different steps of the design process (both for DSP processors in general and for this project) and motivates the design decisions made for this processor. The second part is a nearly complete design specification. The intended use of the processor is as a platform for hardware acceleration units. Support for this has howe...

  19. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  20. Dual-core Itanium Processor

    CERN Multimedia

    2006-01-01

    Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

  1. Metasurface Spatial Processor for Electromagnetic Remote Control

    CERN Document Server

    Achouri, Karim; Salem, Mohamed Ahmed; Caloz, Christophe

    2015-01-01

    We introduce the concept of metasurface spatial processor, whose transmission is remotely and coherently controlled by the superposition of an incident wave and a control wave through the metasurface. The conceptual operation of this device is analogous to both that of a transistor and a Mach-Zehnder interferometer, while offering much more diversity in terms of electromagnetic transformations. We demonstrate two metasurfaces, that perform the operation of electromagnetic switching and amplification.

  2. 21 CFR 864.3875 - Automated tissue processor.

    Science.gov (United States)

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Automated tissue processor. 864.3875 Section 864.3875 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES HEMATOLOGY AND PATHOLOGY DEVICES Pathology Instrumentation and Accessories § 864.3875...

  3. Distributed processor allocation for launching applications in a massively connected processors complex

    Science.gov (United States)

    Pedretti, Kevin

    2008-11-18

    A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.

  4. AMD's 64-bit Opteron processor

    CERN Multimedia

    CERN. Geneva

    2003-01-01

    This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

  5. Cache Energy Optimization Techniques For Modern Processors

    Energy Technology Data Exchange (ETDEWEB)

    Mittal, Sparsh [ORNL

    2013-01-01

    Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems. In this book, we present novel cache leakage energy saving schemes for single-core and multicore systems; desktop, QoS, real-time and server systems. Also, we present cache energy saving techniques for caches designed with both conventional SRAM devices and emerging non-volatile devices such as STT-RAM (spin-torque transfer RAM). We present software-controlled, hardware-assisted techniques which use dynamic cache reconfiguration to configure the cache to the most energy efficient configuration while keeping the performance loss bounded. To profile and test a large number of potential configurations, we utilize low-overhead, micro-architecture components, which can be easily integrated into modern processor chips. We adopt a system-wide approach to save energy to ensure that cache reconfiguration does not increase energy consumption of other components of the processor. We have compared our techniques with state-of-the-art techniques and have found that our techniques outperform them in terms of energy efficiency and other relevant metrics. The techniques presented in this book have important applications in improving energy-efficiency of higher-end embedded, desktop, QoS, real-time, server processors and multitasking systems. This book is intended to be a valuable guide for both

  6. Nanofilm processors controlled by electrolyte flows of femtoliter volume.

    Science.gov (United States)

    Nolte, Marius; Knoll, Meinhard

    2013-06-25

    Nanofilm processors are a new kind of smart system based on the lateral self-oxidation of nanoscale aluminum films. The time dependency of these devices is controlled by electrolyte flows of femtoliter volume which can be modulated by different mechanisms. In this paper, we provide a deeper investigation of the electrolyte transport in the nanofilm processor and the different possibilities to control the aluminum oxidation velocity. A method for the in situ investigation of the acidic characteristic of the channel electrolyte is demonstrated. The obtained results form a set of instruments for constructing more complex electrolyte circuits and should allow the creation of nanofilm processors of arbitrary time dependence. Because the nanofilm processor combines different functional blocks and can operate in a self-sustained manner, without requiring batteries, this smart system may serve as a basis for many potential applications.

  7. Micromechanical Signal Processors

    Science.gov (United States)

    Nguyen, Clark Tu-Cuong

    Completely monolithic high-Q micromechanical signal processors constructed of polycrystalline silicon and integrated with CMOS electronics are described. The signal processors implemented include an oscillator, a bandpass filter, and a mixer + filter--all of which are components commonly required for up- and down-conversion in communication transmitters and receivers, and all of which take full advantage of the high Q of micromechanical resonators. Each signal processor is designed, fabricated, then studied with particular attention to the performance consequences associated with miniaturization of the high-Q element. The fabrication technology which realizes these components merges planar integrated circuit CMOS technologies with those of polysilicon surface micromachining. The technologies are merged in a modular fashion, where the CMOS is processed in the first module, the microstructures in a following separate module, and at no point in the process sequence are steps from each module intermixed. Although the advantages of such modularity include flexibility in accommodating new module technologies, the developed process constrained the CMOS metallization to a high temperature refractory metal (tungsten metallization with TiSi _2 contact barriers) and constrained the micromachining process to long-term temperatures below 835^circC. Rapid-thermal annealing (RTA) was used to relieve residual stress in the mechanical structures. To reduce the complexity involved with developing this merged process, capacitively transduced resonators are utilized. High-Q single resonator and spring-coupled micromechanical resonator filters are also investigated, with particular attention to noise performance, bandwidth control, and termination design. The noise in micromechanical filters is found to be fairly high due to poor electromechanical coupling on the micro-scale with present-day technologies. Solutions to this high series resistance problem are suggested, including smaller

  8. Scalable Sensor Data Processor: A Multi-Core Payload Data Processor ASIC

    Science.gov (United States)

    Berrojo, L.; Moreno, R.; Regada, R.; Garcia, E.; Trautner, R.; Rauwerda, G.; Sunesen, K.; He, Y.; Redant, S.; Thys, G.; Andersson, J.; Habinc, S.

    2015-09-01

    The Scalable Sensor Data Processor (SSDP) project, under ESA contract and with TAS-E as prime contractor, targets the development of a multi-core ASIC for payload data processing to be used, among other terrestrial and space application areas, in future scientific and exploration missions with harsh radiation environments. The SSDP is a mixed-signal heterogeneous multi-core System-on-Chip (SoC). It combines GPP and NoC-based DSP subsystems with on-chip ADCs and several standard space I/Fs to make a flexible, configurable and scalable device. The NoC comprises two state-of-the-art fixed point Xentium® DSP processors, providing the device with high data processing capabilities.

  9. Embedded Data Processor and Portable Computer Technology testbeds

    Science.gov (United States)

    Alena, Richard; Liu, Yuan-Kwei; Goforth, Andre; Fernquist, Alan R.

    1993-01-01

    Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

  10. Never Trust Your Word Processor

    Science.gov (United States)

    Linke, Dirk

    2009-01-01

    In this article, the author talks about the auto correction mode of word processors that leads to a number of problems and describes an example in biochemistry exams that shows how word processors can lead to mistakes in databases and in papers. The author contends that, where this system is applied, spell checking should not be left to a word…

  11. Embedded Processor Oriented Compiler Infrastructure

    Directory of Open Access Journals (Sweden)

    DJUKIC, M.

    2014-08-01

    Full Text Available In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures. However, industrial strength compilers, besides ability to generate efficient code, must also be robust, understandable, maintainable, and extensible. This raises the need for compiler infrastructure that provides means for convenient implementation of embedded processor oriented compiler techniques. Cirrus Logic Coyote 32 DSP is an example that shows how traditional compiler infrastructure is not able to cope with the problem. That is why the new compiler infrastructure was developed for this processor, based on research. in the field of embedded system software tools and experience in development of industrial strength compilers. The new infrastructure is described in this paper. Compiler generated code quality is compared with code generated by the previous compiler for the same processor architecture.

  12. Wastewater treatment: options for Louisiana seafood processors

    National Research Council Canada - National Science Library

    Zachritz, W.H; Malone, R.F

    1991-01-01

    ...) to define the environmental regulatory requirements that apply to seafood processors; 3) to catalog available historical data for describing the wastewaters of major Louisiana seafood processors, and 4...

  13. First Results of an “Artificial Retina” Processor Prototype

    Directory of Open Access Journals (Sweden)

    Cenci Riccardo

    2016-01-01

    Full Text Available We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate.

  14. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    .... The technical challenges in the development of this technology included development of a fractionation device to reduce the size of sulfur scrubber beds, a cracking process with high conversion...

  15. Meteorological Processors and Accessory Programs

    Science.gov (United States)

    Surface and upper air data, provided by NWS, are important inputs for air quality models. Before these data are used in some of the EPA dispersion models, meteorological processors are used to manipulate the data.

  16. A trigger processor for ARGUS

    CERN Document Server

    Schulz, H D

    1981-01-01

    The ARGUS detector at the electron-positron storage ring DORIS consists of various particle detectors arranged in cylindrical symmetry in and around an axial magnetic field. A fast secondary trigger processor has been designed to find and count circular tracks in the r- phi -plane of the detector that originate from the interaction point. The processor serves as a filter in the trigger system of the ARGUS detector and is expected to reduce the rate of background triggers by two orders of magnitude. The processor hardware is built in ECL to perform simple operations with very high speed and partly in parallel. The track finding process takes about 9 mu s plus 3 mu s for each encountered track element. Control information is stored in memories that may be loaded via CAMAC from the online computer allowing easy adaption of the processor to different experimental conditions. (1 refs).

  17. 40 CFR 791.45 - Processors.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 31 2010-07-01 2010-07-01 true Processors. 791.45 Section 791.45...) DATA REIMBURSEMENT Basis for Proposed Order § 791.45 Processors. (a) Generally, processors will be... processors will have a responsibility to provide reimbursement directly to those paying for the testing: (1...

  18. 7 CFR 926.13 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 926.13 Section 926.13 Agriculture... Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in the form of concentrate from handlers, producer-handlers, importers, brokers or other processors and...

  19. Design of free space interconnected signal processor

    Science.gov (United States)

    Murdocca, Miles; Stone, Thomas

    1993-12-01

    Progress is described on a collaborative effort between the Photonics Center at Rome Laboratory (RL), Griffiss AFB and Rutgers University, through the RL Expert Science and Engineering (ES&E) program. The goal of the effort is to develop a prototype random access memory (RAM) that can be used in a signal processor for a computing model that consists of cascaded arrays of optical logic gates interconnected in free space with regular patterns. The effort involved the optical and architectural development of a cascadable optical logic system in which microlaser pumped S-SEED devices serve as logic gates. At the completion of the contract, two gate-level layouts of the module were completed which were created in collaboration with RL personnel. The basic layout of the optical system has been developed, and key components have been tested. The delayed delivery of microlaser arrays precluded completion of the processor during the contract period, but preliminary testing was made possible through the use of other microlaser devices.

  20. Early experience with the cochlear ESPrit ear-level speech processor in children.

    Science.gov (United States)

    Totten, C; Cope, Y; McCormick, B

    2000-12-01

    The ESPrit ear-level speech processor has recently become available in the United Kingdom for use with the Nucleus CI24M multichannel cochlear implant. We report on the use of this ear-level processor with 6 children, ages 8 to 15 years. In this study, all patients were initially fitted with the SPrint body-worn processor, this being a prerequisite for programming the ESPrit. Five of the children were fitted successfully with the ESPrit and are using their devices consistently. The results show that patient experience with the ESPrit has been favorable, although there have been some device and programming difficulties. Aided threshold measures show that the ESPrit processor performs at least as well as the SPrint processor, with a trend toward improved aided thresholds for the ESPrit processor compared with the SPrint processor. Further study of the functional benefit of both of these devices may confirm these potential gains. The ESPrit device currently has a disadvantage for children in that it does not support FM radio hearing aid use. Finally, caution is advised in the fitting of the ESPrit in very young children or inexperienced listeners, because of difficulties in monitoring device function.

  1. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  2. A photonic integrated signal processor

    Science.gov (United States)

    Yao, Jianping

    2017-02-01

    A photonic integrated signal processor based on the InP-InGaAsP material system consisting of a bypass waveguide and three mutually-coupled micro rings with each ring having two semiconductor optical amplifiers (SOAs) and a current-injection phase modulator (PM) for ultra-wideband signal processing and microwave signal generation is discussed. The signal processor can be reconfigured to perform signal processing functions including temporal differentiation, and temporal integration. The reconfigurability is achieved by controlling the coupling between the rings and the bypass waveguide by a multi-mode interference (MMI) Mach-Zehnder interferometer (MZI) coupler and the injection currents to the SOAs. The current injection PM in a ring is used for wavelength tuning. In addition to signal processing, the signal processor can also be reconfigured to operate as a microwave signal generator. The generation a linearly chirped microwave waveform is discussed.

  3. Java Processor Optimized for RTSJ

    Directory of Open Access Journals (Sweden)

    Tu Shiliang

    2007-01-01

    Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

  4. Making CSB + -Trees Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performan...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  5. A Course on Reconfigurable Processors

    Science.gov (United States)

    Shoufan, Abdulhadi; Huss, Sorin A.

    2010-01-01

    Reconfigurable computing is an established field in computer science. Teaching this field to computer science students demands special attention due to limited student experience in electronics and digital system design. This article presents a compact course on reconfigurable processors, which was offered at the Technische Universitat Darmstadt,…

  6. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    Home; Journals; Resonance – Journal of Science Education; Volume 6; Issue 12. Very Long Instruction Word Processors. S Balakrishnan. General Article Volume 6 Issue 12 December 2001 pp 61-68. Fulltext. Click here to view fulltext PDF. Permanent link: http://www.ias.ac.in/article/fulltext/reso/006/12/0061-0068 ...

  7. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    purpose applications are hard to detect at compile time. The superscalar processor's hardware (control subsystem) for detect- ing parallelism and dynamically scheduling operations allows runtime detection and exploitation of parallelism in applica- tions where parallelism is hard to detect at compile time. The. Intel Pentium ...

  8. Entanglement in a Quantum Annealing Processor

    Science.gov (United States)

    2016-09-07

    Entanglement in a Quantum Annealing Processor T. Lanting,1,* A. J. Przybysz,1 A. Yu. Smirnov,1 F. M. Spedalieri,2,3 M. H. Amin,1,4 A. J. Berkley,1 R...promising path to a practical quantum processor . We have built a series of architecturally scalable QA processors consisting of networks of manufactured...such processor , demonstrating quantum coherence in these systems. We present experimental evidence that, during a critical portion of QA, the qubits

  9. 7 CFR 989.13 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements... CALIFORNIA Order Regulating Handling Definitions § 989.13 Processor. Processor means any person who receives...

  10. 7 CFR 1215.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 10 2010-01-01 2010-01-01 false Processor. 1215.14 Section 1215.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS... Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

  11. 7 CFR 927.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 927.14 Section 927.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements... Order Regulating Handling Definitions § 927.14 Processor. Processor means any person who as owner, agent...

  12. Communications systems and methods for subsea processors

    Science.gov (United States)

    Gutierrez, Jose; Pereira, Luis

    2016-04-26

    A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

  13. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...... on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate...... through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration....

  14. Log-Output Signal Processor Scans Eight Decades

    Science.gov (United States)

    Hayden, J. L.

    1982-01-01

    Processor has automatic range switching and continuous readout over eight decades. Comparator output switches logarithmic converter to detector of interest and enables blinder grid to protect more-sensitive detector when operating in high-input range. Could be used to process any wide-varying signal that is to be read on a limited-range recording device such as a strip-chart recorder.

  15. Invasive tightly coupled processor arrays

    CERN Document Server

    LARI, VAHID

    2016-01-01

    This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

  16. The UA1 trigger processor

    CERN Document Server

    Grayer, G H

    1981-01-01

    Experiment UA1 is a large multipurpose spectrometer at the CERN proton-antiproton collider. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead-time losses due to the bunched nature of the beam. To achieve this fast 8-bit charge to digital converters have been built followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, and to transverse energy in the other. Each processor forms four sums from a chosen combination of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in...

  17. PDSparc: A Drop-In Replacement for LEON3 Written Using Synopsys Processor Designer

    Science.gov (United States)

    2015-09-24

    SNUG  2015   1   PDSparc:  A  Drop-­‐In  Replacement  for  LEON3   Written  Using  Synopsys   Processor  Designer PDSparc...A  Drop-­‐In  Replacement  for  LEON3  Written  Using   Synopsys   Processor  Designer12   David  Whelihan,  Ph.D.  and...fabricate a range of stand-alone processors . However the proliferation of small computing devices such as cell phones, laptop computers, and internet

  18. Slime mould processors, logic gates and sensors.

    Science.gov (United States)

    Adamatzky, A

    2015-07-28

    A heterotic, or hybrid, computation implies that two or more substrates of different physical nature are merged into a single device with indistinguishable parts. These hybrid devices then undertake coherent acts on programmable and sensible processing of information. We study the potential of heterotic computers using slime mould acting under the guidance of chemical, mechanical and optical stimuli. Plasmodium of acellular slime mould Physarum polycephalum is a gigantic single cell visible to the unaided eye. The cell shows a rich spectrum of behavioural morphological patterns in response to changing environmental conditions. Given data represented by chemical or physical stimuli, we can employ and modify the behaviour of the slime mould to make it solve a range of computing and sensing tasks. We overview results of laboratory experimental studies on prototyping of the slime mould morphological processors for approximation of Voronoi diagrams, planar shapes and solving mazes, and discuss logic gates implemented via collision of active growing zones and tactile responses of P. polycephalum. We also overview a range of electronic components--memristor, chemical, tactile and colour sensors-made of the slime mould. © 2015 The Author(s) Published by the Royal Society. All rights reserved.

  19. SMART AS A CRYPTOGRAPHIC PROCESSOR

    OpenAIRE

    Saroja Kanchi; Nozar Tabrizi; Cody Hayden

    2016-01-01

    SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designed and successfully mapped into a FPGA chip in our ECE department. In this paper, we use SMaRT to run the well-known encryption algorithm, Data Encryption Standard. For information security purposes, encryption is a must in today’s sophisticated and ever-increasing computer communications such as ATM machines and SIM cards. For comparison and evaluation purposes, we also map the same algori...

  20. Analog Processor To Solve Optimization Problems

    Science.gov (United States)

    Duong, Tuan A.; Eberhardt, Silvio P.; Thakoor, Anil P.

    1993-01-01

    Proposed analog processor solves "traveling-salesman" problem, considered paradigm of global-optimization problems involving routing or allocation of resources. Includes electronic neural network and auxiliary circuitry based partly on concepts described in "Neural-Network Processor Would Allocate Resources" (NPO-17781) and "Neural Network Solves 'Traveling-Salesman' Problem" (NPO-17807). Processor based on highly parallel computing solves problem in significantly less time.

  1. Low-Latency Embedded Vision Processor (LLEVS)

    Science.gov (United States)

    2016-03-01

    DP Double Precision DSP Digital Signal Processor DU Drexel University DVE Degraded Visual Environment DWT Discrete Wavelet Transform EMI...AFRL-RH-WP-TR-2016-0017 Low-Latency Embedded Vision Processor (LLEVS) Greg Cream*, Wesley Sheridan*, and Prawat Nagvajara...Embedded Vision Processor (LLEVS) 5a. CONTRACT NUMBER FA8650-15-M-6659 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 65502F 6. AUTHOR(S) Greg

  2. In-Network Adaptation of Video Streams Using Network Processors

    Directory of Open Access Journals (Sweden)

    Mohammad Shorfuzzaman

    2009-01-01

    problem can be addressed, near the network edge, by applying dynamic, in-network adaptation (e.g., transcoding of video streams to meet available connection bandwidth, machine characteristics, and client preferences. In this paper, we extrapolate from earlier work of Shorfuzzaman et al. 2006 in which we implemented and assessed an MPEG-1 transcoding system on the Intel IXP1200 network processor to consider the feasibility of in-network transcoding for other video formats and network processor architectures. The use of “on-the-fly” video adaptation near the edge of the network offers the promise of simpler support for a wide range of end devices with different display, and so forth, characteristics that can be used in different types of environments.

  3. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

    2012-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  4. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie L.; Adam, Niklas M.; Barta, Daniel; Meyer, Caitlin E.; Pensinger, Stuart; Vega, Leticia M.; Callahan, Michael R.; Flynn, Michael; Wheeler, Ray; hide

    2013-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrification and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  5. From TEMPO+ to OPUS 2: what can music tests tell us about processor upgrades?

    Science.gov (United States)

    van Besouw, R M; Grasmeder, M L

    2011-08-01

    Tests for quantifying the music perception abilities of cochlear implant users are currently being developed and trialled at the South of England Cochlear Implant Centre. In addition to measures of speech perception, tests of rhythm, and pitch have been administered to MED-EL C40+ implant users before and after upgrading from the TEMPO+ processor with continuous interleaved sampling strategy to the OPUS 2 processor with fine structure processing strategy, with the aims of comparing device performance and evaluating the potential of music perception tests for informing processor upgrades and tuning. Eight experienced adult C40+ implant recipients performed tests of rhythm and pitch discrimination using the TEMPO+ processor and, after a minimum of 6 weeks acclimatization, using the OPUS 2 processor. Stimuli included piano and sine tones in two note ranges for the pitch tasks, and drum beats for the rhythm task. Rhythm, pitch, and speech perception scores were comparable for both processors. An effect of note range was observed (z = -2.52, p = 0.008 (two-tailed), r = -0.63), which indicated that the higher range of notes used for the pitch tasks was easier for participants than the lower range. Measures of pitch discrimination in different frequency ranges further informed changes made to one participant's map, resulting in improved pitch discrimination and speech perception scores. The outcomes of this study demonstrate that music perception tests can provide important additional measures for tuning cochlear implant parameters and assessing the impact of changes to device type and processing strategy.

  6. An Empirical Evaluation of XQuery Processors

    NARCIS (Netherlands)

    S. Manegold (Stefan)

    2007-01-01

    textabstractThis paper presents an extensive and detailed experimental evaluation of XQuery processors. The study consists of running five publicly available XQuery benchmarks --- the Michigan benchmark (MBench), XBench, XMach-1, XMark and X007 --- on six XQuery processors, three stand-alone

  7. An Empirical Evaluation of XQuery Processors

    NARCIS (Netherlands)

    S. Manegold (Stefan)

    2008-01-01

    textabstractThis paper presents an extensive and detailed experimental evaluation of XQuery processors. The study consists of running five publicly available XQuery benchmarks --- the Michigan benchmark (MBench), XBench, XMach-1, XMark and X007 --- on six XQuery processors, three stand-alone

  8. Adapting implicit methods to parallel processors

    Energy Technology Data Exchange (ETDEWEB)

    Reeves, L.; McMillin, B.; Okunbor, D.; Riggins, D. [Univ. of Missouri, Rolla, MO (United States)

    1994-12-31

    When numerically solving many types of partial differential equations, it is advantageous to use implicit methods because of their better stability and more flexible parameter choice, (e.g. larger time steps). However, since implicit methods usually require simultaneous knowledge of the entire computational domain, these methods axe difficult to implement directly on distributed memory parallel processors. This leads to infrequent use of implicit methods on parallel/distributed systems. The usual implementation of implicit methods is inefficient due to the nature of parallel systems where it is common to take the computational domain and distribute the grid points over the processors so as to maintain a relatively even workload per processor. This creates a problem at the locations in the domain where adjacent points are not on the same processor. In order for the values at these points to be calculated, messages have to be exchanged between the corresponding processors. Without special adaptation, this will result in idle processors during part of the computation, and as the number of idle processors increases, the lower the effective speed improvement by using a parallel processor.

  9. The TM3270 Media-processor

    NARCIS (Netherlands)

    van de Waerdt, J.W.

    2006-01-01

    I n this thesis, we present the TM3270 VLIW media-processor, the latest of TriMedia processors, and describe the innovations with respect to its prede- cessor: the TM3260. We describe enhancements to the load/store unit design, such as a new data prefetching technique, and architectural

  10. The Case for a Generic Implant Processor

    NARCIS (Netherlands)

    Strydis, C.; Gaydadjiev, G.N.

    2008-01-01

    A more structured and streamlined design of implants is nowadays possible. In this paper we focus on implant processors located in the heart of implantable systems. We present a real and representative biomedical-application scenario where such a new processor can be employed. Based on a suitably

  11. Ultrafast Fourier-transform parallel processor

    Energy Technology Data Exchange (ETDEWEB)

    Greenberg, W.L.

    1980-04-01

    A new, flexible, parallel-processing architecture is developed for a high-speed, high-precision Fourier transform processor. The processor is intended for use in 2-D signal processing including spatial filtering, matched filtering and image reconstruction from projections.

  12. Towards a Process Algebra for Shared Processors

    DEFF Research Database (Denmark)

    Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

    2002-01-01

    We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

  13. Cassava processors' awareness of occupational and environmental ...

    African Journals Online (AJOL)

    ... investigated cassava processors' awareness of occupational and environmental hazards associated with and factors affecting cassava processing in three states - Oyo, Ogun and Ondo in South-western Nigeria. A total of 380 cassava processors were purposively and randomly selected from the three states. Data were ...

  14. Time-memory-processor tradeoffs

    Energy Technology Data Exchange (ETDEWEB)

    Amirazizi, H.R.; Hellman, M.E.

    This paper demonstrates that usual time-memory tradeoffs offer no asymptotic advantage over exhaustive search. Instead, it proposes tradoffs between time, memory, and parallel processing. Using this approach it is shown that most searching problems allow a tradeoff between c/sub s/, the cost per solution, and c/sub m/, the cost of the machine; doubling c/sub m/ increases the solution rate by a factor of four, halving c/sub s/. The machine which achieves this has an unusual architecture, with a number of processors sharing a large memory through a sorting/switching network. The implications for cryptanalysis, the knapsack problem, multiple encryption and VLSI are discussed.

  15. The ATLAS fast tracker processor design

    CERN Document Server

    Volpi, Guido; Albicocco, Pietro; Alison, John; Ancu, Lucian Stefan; Anderson, James; Andari, Nansi; Andreani, Alessandro; Andreazza, Attilio; Annovi, Alberto; Antonelli, Mario; Asbah, Needa; Atkinson, Markus; Baines, J; Barberio, Elisabetta; Beccherle, Roberto; Beretta, Matteo; Biesuz, Nicolo Vladi; Blair, R E; Bogdan, Mircea; Boveia, Antonio; Britzger, Daniel; Bryant, Partick; Burghgrave, Blake; Calderini, Giovanni; Camplani, Alessandra; Cavaliere, Viviana; Cavasinni, Vincenzo; Chakraborty, Dhiman; Chang, Philip; Cheng, Yangyang; Citraro, Saverio; Citterio, Mauro; Crescioli, Francesco; Dawe, Noel; Dell'Orso, Mauro; Donati, Simone; Dondero, Paolo; Drake, G; Gadomski, Szymon; Gatta, Mauro; Gentsos, Christos; Giannetti, Paola; Gkaitatzis, Stamatios; Gramling, Johanna; Howarth, James William; Iizawa, Tomoya; Ilic, Nikolina; Jiang, Zihao; Kaji, Toshiaki; Kasten, Michael; Kawaguchi, Yoshimasa; Kim, Young Kee; Kimura, Naoki; Klimkovich, Tatsiana; Kolb, Mathis; Kordas, K; Krizka, Karol; Kubota, T; Lanza, Agostino; Li, Ho Ling; Liberali, Valentino; Lisovyi, Mykhailo; Liu, Lulu; Love, Jeremy; Luciano, Pierluigi; Luongo, Carmela; Magalotti, Daniel; Maznas, Ioannis; Meroni, Chiara; Mitani, Takashi; Nasimi, Hikmat; Negri, Andrea; Neroutsos, Panos; Neubauer, Mark; Nikolaidis, Spiridon; Okumura, Y; Pandini, Carlo; Petridou, Chariclia; Piendibene, Marco; Proudfoot, James; Rados, Petar Kevin; Roda, Chiara; Rossi, Enrico; Sakurai, Yuki; Sampsonidis, Dimitrios; Saxon, James; Schmitt, Stefan; Schoening, Andre; Shochet, Mel; Shoijaii, Jafar; Soltveit, Hans Kristian; Sotiropoulou, Calliope-Louisa; Stabile, Alberto; Swiatlowski, Maximilian J; Tang, Fukun; Taylor, Pierre Thor Elliot; Testa, Marianna; Tompkins, Lauren; Vercesi, V; Wang, Rui; Watari, Ryutaro; Zhang, Jianhong; Zeng, Jian Cong; Zou, Rui; Bertolucci, Federico

    2015-01-01

    The extended use of tracking information at the trigger level in the LHC is crucial for the trigger and data acquisition (TDAQ) system to fulfill its task. Precise and fast tracking is important to identify specific decay products of the Higgs boson or new phenomena, as well as to distinguish the contributions coming from the many collisions that occur at every bunch crossing. However, track reconstruction is among the most demanding tasks performed by the TDAQ computing farm; in fact, complete reconstruction at full Level-1 trigger accept rate (100 kHz) is not possible. In order to overcome this limitation, the ATLAS experiment is planning the installation of a dedicated processor, the Fast Tracker (FTK), which is aimed at achieving this goal. The FTK is a pipeline of high performance electronics, based on custom and commercial devices, which is expected to reconstruct, with high resolution, the trajectories of charged-particle tracks with a transverse momentum above 1 GeV, using the ATLAS inner tracker info...

  16. KIDNEY DISEASE VISUALIZED ON DIGITAL PROCESSOR

    Directory of Open Access Journals (Sweden)

    Rade R. Babić

    2013-09-01

    Full Text Available Radiological methods of examination in diagnosis of pathological conditions and diseases of urinary system are numerous and various, reliable and dominant. They became indispensable and without competition, among other diagnostic methods, using the digital techniques. The aim of this paper was to present the radiological image of pathological conditions and diseases of urinary system diagnosed by intravenous urography using digital techniques and to show the diagnostic possibilities and importance of digital techniques in diagnostic radiology. The paper analyzes pathological conditions and diseases of the kidney in a series of 3100 intravenous urographies (IVU performed at the Radiology Center, Clinical Center Niš, during the period 2009-2012. Radiographic examination was performed on X-ray device with a TV chain Schimadzu. IVU was performed according to the standard protocol. Contrast media: Ultravist 370®. X-ray images were digitally processed in Agfa CR-30 digital processor. The results are shown illustratively, by urographic images - anomalies, calculosis, hydronephrosis, tumors and other pathological conditions and diseases of the urinary system. This paper presents numerous and various pathological conditions and diseases of the urinary system. Among the valuable radiological examination methods IVU has maintained a leading position. The usage of digital techniques made IVU faster, easy and efficient method of examination, while the obtained urograms are of satisfactory quality and adequate contrast visualization of the urinary system.

  17. SCAN secure processor and its biometric capabilities

    Science.gov (United States)

    Kannavara, Raghudeep; Mertoguno, Sukarno; Bourbakis, Nikolaos

    2011-04-01

    This paper presents the design of the SCAN secure processor and its extended instruction set to enable secure biometric authentication. The SCAN secure processor is a modified SparcV8 processor architecture with a new instruction set to handle voice, iris, and fingerprint-based biometric authentication. The algorithms for processing biometric data are based on the local global graph methodology. The biometric modules are synthesized in reconfigurable logic and the results of the field-programmable gate array (FPGA) synthesis are presented. We propose to implement the above-mentioned modules in an off-chip FPGA co-processor. Further, the SCAN-secure processor will offer a SCAN-based encryption and decryption of 32 bit instructions and data.

  18. ALMA Correlator Real-Time Data Processor

    Science.gov (United States)

    Pisano, J.; Amestica, R.; Perez, J.

    2005-10-01

    The design of a real-time Linux application utilizing Real-Time Application Interface (RTAI) to process real-time data from the radio astronomy correlator for the Atacama Large Millimeter Array (ALMA) is described. The correlator is a custom-built digital signal processor which computes the cross-correlation function of two digitized signal streams. ALMA will have 64 antennas with 2080 signal streams each with a sample rate of 4 giga-samples per second. The correlator's aggregate data output will be 1 gigabyte per second. The software is defined by hard deadlines with high input and processing data rates, while requiring interfaces to non real-time external computers. The designed computer system - the Correlator Data Processor or CDP, consists of a cluster of 17 SMP computers, 16 of which are compute nodes plus a master controller node all running real-time Linux kernels. Each compute node uses an RTAI kernel module to interface to a 32-bit parallel interface which accepts raw data at 64 megabytes per second in 1 megabyte chunks every 16 milliseconds. These data are transferred to tasks running on multiple CPUs in hard real-time using RTAI's LXRT facility to perform quantization corrections, data windowing, FFTs, and phase corrections for a processing rate of approximately 1 GFLOPS. Highly accurate timing signals are distributed to all seventeen computer nodes in order to synchronize them to other time-dependent devices in the observatory array. RTAI kernel tasks interface to the timing signals providing sub-millisecond timing resolution. The CDP interfaces, via the master node, to other computer systems on an external intra-net for command and control, data storage, and further data (image) processing. The master node accesses these external systems utilizing ALMA Common Software (ACS), a CORBA-based client-server software infrastructure providing logging, monitoring, data delivery, and intra-computer function invocation. The software is being developed in tandem

  19. Performance Analysis of Digital Signal Processors Using SMV Benchmark

    OpenAIRE

    Erh-Wen Hu; Cyril S. Ku; Andrew T. Russo; Bogong Su; Jian Wang

    2009-01-01

    Unlike general-purpose processors, digital signal processors (DSP processors) are strongly application-dependent. To meet the needs for diverse applications, a wide variety of DSP processors based on different architectures ranging from the traditional to VLIW have been introduced to the market over the years. The functionality, performance, and cost of these processors vary over a wide range. In order to select a processor that meets the design criteria for an applicatio...

  20. Benchmarking of Sleipnir DSP Processor, ePUMA Platform

    OpenAIRE

    Murugesan, Somasekar

    2011-01-01

    Choosing a right processor for an embedded application, or designing a new pro-cessor requires us to know how it stacks up against the competition, or sellinga processor requires a credible communication about its performance to the cus-tomers, which means benchmarking of a processor is very important. They arerecognized world wide by processor vendors and customers alike as the fact-basedway to evaluate and communicate embedded processor performance. In this the-sis, the benchmarking of ePUM...

  1. Sequence information signal processor for local and global string comparisons

    Science.gov (United States)

    Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

    1997-01-01

    A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

  2. The Level 0 Trigger Processor for the NA62 experiment

    Energy Technology Data Exchange (ETDEWEB)

    Chiozzi, S. [INFN, Ferrara (Italy); Gamberini, E. [University of Ferrara and INFN, Ferrara (Italy); Gianoli, A. [INFN, Ferrara (Italy); Mila, G. [University of Turin and INFN, Turin (Italy); Neri, I., E-mail: neri@fe.infn.it [University of Ferrara and INFN, Ferrara (Italy); Petrucci, F. [University of Ferrara and INFN, Ferrara (Italy); Soldi, D. [University of Turin and INFN, Turin (Italy)

    2016-07-11

    In the NA62 experiment at CERN, the intense flux of particles requires a high-performance trigger for the data acquisition system. A Level 0 Trigger Processor (L0TP) was realized, performing the event selection based on trigger primitives coming from sub-detectors and reducing the trigger rate from 10 to 1 MHz. The L0TP is based on a commercial FPGA device and has been implemented in two different solutions. The performance of the two systems are highlighted and compared.

  3. Fabrication Security and Trust of Domain-Specific ASIC Processors

    Science.gov (United States)

    2016-10-30

    EW/ESM: electronic warfare/ electronic support measures; Comm.: communications) The domain-specific ASIC processors under development are System-on...10] J. A. Roy, F. Koushanfar and I. L. Markov, "Ending piracy of integrated circuits," in Computer, vol. 43, no. 10, pp. 30-38, Oct. 2010. [11] R. S... Electron Devices Meeting (IEDM), pp. 8.5.1-8.5.4. [15] C. Maxfield, “2D vs. 2.5D vs. 3D ICs 101,” EE Times, 4/8/2012. [16] M. Brunnbauer et al

  4. Enabling Future Robotic Missions with Multicore Processors

    Science.gov (United States)

    Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

    2011-01-01

    Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

  5. Effect of processor temperature on film dosimetry.

    Science.gov (United States)

    Srivastava, Shiv P; Das, Indra J

    2012-01-01

    Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d(max.), 10 × 10 cm(2), 100 cm) to a given dose. An automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4-40.6°C (85-105°F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used. Copyright © 2012 American Association of Medical Dosimetrists. Published by Elsevier Inc. All rights reserved.

  6. Hardware Trigger Processor for the MDT System

    CERN Document Server

    Costa De Paiva, Thiago; The ATLAS collaboration

    2017-01-01

    We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the ATLAS Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

  7. Clinical Validation of a Sound Processor Upgrade in Direct Acoustic Cochlear Implant Subjects.

    Science.gov (United States)

    Kludt, Eugen; D'hondt, Christiane; Lenarz, Thomas; Maier, Hannes

    2017-06-01

    The objectives of the investigation were to evaluate the effect of a sound processor upgrade on the speech reception threshold in noise and to collect long-term safety and efficacy data after 2½ to 5 years of device use of direct acoustic cochlear implant (DACI) recipients. The study was designed as a mono-centric, prospective clinical trial. Tertiary referral center. Fifteen patients implanted with a direct acoustic cochlear implant. Upgrade with a newer generation of sound processor. Speech recognition test in quiet and in noise, pure tone thresholds, subject-reported outcome measures. The speech recognition in quiet and in noise is superior after the sound processor upgrade and stable after long-term use of the direct acoustic cochlear implant. The bone conduction thresholds did not decrease significantly after long-term high level stimulation. The new sound processor for the DACI system provides significant benefits for DACI users for speech recognition in both quiet and noise. Especially the noise program with the use of directional microphones (Zoom) allows DACI patients to have much less difficulty when having conversations in noisy environments. Furthermore, the study confirms that the benefits of the sound processor upgrade are available to the DACI recipients even after several years of experience with a legacy sound processor. Finally, our study demonstrates that the DACI system is a safe and effective long-term therapy.

  8. Monitoring device for attachment to a surface of a subject

    DEFF Research Database (Denmark)

    2012-01-01

    The invention provides a monitoring device (1) for attachment to a surface of a subject. The device comprises a data collector (2) and a processor (3) as two separate parts which can be detachably joined such that physiological signals which are detected by the data collector can be transferred...... surface, and may comprise an adapter (6) for the detachable attachment of the processor....

  9. Heterogeneous Multicore Processor Technologies for Embedded Systems

    CERN Document Server

    Uchiyama, Kunio; Kasahara, Hironori; Nojiri, Tohru; Noda, Hideyuki; Tawara, Yasuhiro; Idehara, Akio; Iwata, Kenichi; Shikano, Hiroaki

    2012-01-01

    To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-p...

  10. Radiation Tolerant Software Defined Video Processor Project

    Data.gov (United States)

    National Aeronautics and Space Administration — MaXentric's is proposing a radiation tolerant Software Define Video Processor, codenamed SDVP, for the problem of advanced motion imaging in the space environment....

  11. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  12. Implementation of an Ethernet-Based Communication Channel for the Patmos Processor

    DEFF Research Database (Denmark)

    Pezzarossa, Luca; Kenn Toft, Jakob; Lønbæk, Jesper

    The Patmos processor, which is used as the intellectual property of the T-CREST platform, is only equipped with a RS-232 serial port for communication with the outside world. The serial port is a minimal input/output device with a limited speed and without native networking features. An Ethernet 10...

  13. Clinical outcomes with the Kanso™ off-the-ear cochlear implant sound processor.

    Science.gov (United States)

    Mauger, Stefan J; Jones, Marian; Nel, Esti; Del Dot, Janine

    2017-04-01

    To investigate clinical outcomes and subjective ratings of the Kanso™ off-the-ear (OTE) cochlear implant sound processor. Prospective, within-subject design investigating outcomes with a range of single and dual-microphone programmes for Kanso compared to conventional behind-the-ear (BTE) sound processors. Twenty post-lingually hearing-impaired cochlear implant recipients who were experienced Nucleus® 5 or Nucleus® 6 BTE users. No significant difference in performance was found for words in quiet or sentences in co-located noise between the Kanso and Nucleus 6 devices. For the moderately directional Standard programme, no significant difference was found for sentences in spatially separated noise between the Kanso and Nucleus 6 devices, but a performance decrement between 1.4 and 2.0 dB was found in highly directional and adaptive directional programmes. The default Kanso programme, SCAN, provided improvements of 6.9 dB over a single-microphone programme and 2.3 dB over the Standard programme in spatially separated noise. Participants rated Kanso significantly better than their own BTE processor on measures of comfort, look and feel, ease of use, music and overall hearing performance. Dual-microphone directional processing provides significant benefit over a single microphone for OTE processors. This study demonstrates clinical outcomes and acceptance of the Kanso OTE sound processor.

  14. GPU: the biggest key processor for AI and parallel processing

    Science.gov (United States)

    Baji, Toru

    2017-07-01

    Two types of processors exist in the market. One is the conventional CPU and the other is Graphic Processor Unit (GPU). Typical CPU is composed of 1 to 8 cores while GPU has thousands of cores. CPU is good for sequential processing, while GPU is good to accelerate software with heavy parallel executions. GPU was initially dedicated for 3D graphics. However from 2006, when GPU started to apply general-purpose cores, it was noticed that this architecture can be used as a general purpose massive-parallel processor. NVIDIA developed a software framework Compute Unified Device Architecture (CUDA) that make it possible to easily program the GPU for these application. With CUDA, GPU started to be used in workstations and supercomputers widely. Recently two key technologies are highlighted in the industry. The Artificial Intelligence (AI) and Autonomous Driving Cars. AI requires a massive parallel operation to train many-layers of neural networks. With CPU alone, it was impossible to finish the training in a practical time. The latest multi-GPU system with P100 makes it possible to finish the training in a few hours. For the autonomous driving cars, TOPS class of performance is required to implement perception, localization, path planning processing and again SoC with integrated GPU will play a key role there. In this paper, the evolution of the GPU which is one of the biggest commercial devices requiring state-of-the-art fabrication technology will be introduced. Also overview of the GPU demanding key application like the ones described above will be introduced.

  15. Rapid recovery from transient faults in the fault-tolerant processor with fault-tolerant shared memory

    Science.gov (United States)

    Harper, Richard E.; Butler, Bryan P.

    1990-01-01

    The Draper fault-tolerant processor with fault-tolerant shared memory (FTP/FTSM), which is designed to allow application tasks to continue execution during the memory alignment process, is described. Processor performance is not affected by memory alignment. In addition, the FTP/FTSM incorporates a hardware scrubber device to perform the memory alignment quickly during unused memory access cycles. The FTP/FTSM architecture is described, followed by an estimate of the time required for channel reintegration.

  16. 7 CFR 1435.310 - Sharing processors' allocations with producers.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 10 2010-01-01 2010-01-01 false Sharing processors' allocations with producers. 1435... Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

  17. 50 CFR 648.6 - Dealer/processor permits.

    Science.gov (United States)

    2010-10-01

    ... 50 Wildlife and Fisheries 8 2010-10-01 2010-10-01 false Dealer/processor permits. 648.6 Section... Dealer/processor permits. (a) General. (1) All dealers of NE multispecies, monkfish, skates, Atlantic...; Atlantic surf clam and ocean quahog processors; Atlantic hagfish dealers and/or processors, and Atlantic...

  18. 49 CFR 234.275 - Processor-based systems.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Processor-based systems. 234.275 Section 234.275..., Inspection, and Testing Requirements for Processor-Based Systems § 234.275 Processor-based systems. (a... requirements of this subpart, a railroad may elect to qualify an existing processor-based product under part...

  19. 7 CFR 1160.108 - Fluid milk processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 9 2010-01-01 2009-01-01 true Fluid milk processor. 1160.108 Section 1160.108... Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who... term fluid milk processor shall not include in each of the respective fiscal periods those persons who...

  20. The Associative Memory system for the FTK processor at ATLAS

    CERN Document Server

    Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2013-01-01

    Experiments at the LHC hadron collider search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and instantaneus luminosity increase, increasingly complex and exclusive selections are necessary. We present results and performances of a new prototype of Associative Memory (AM) system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the ATLAS experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the "combinatorial challenge", is beat by the AM technology exploiting parallelism to the maximum level. The Associative Memory compares the event to pre-calculated "expectations" or "patterns" (pattern matching) at once and look for candidate tracks called "roads". The problem is solved by the time data are loaded into the AM devices. We report ...

  1. The Associative Memory system for the FTK processor at ATLAS

    CERN Document Server

    Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2013-01-01

    Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. We present results and performances of a new prototype of Associative Memory system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the Atlas experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the Associative Memory (AM) technology exploiting parallelism to the maximum level: it compares the event to pre-calculated “expectations” or “patterns” (pattern matching) at once looking for candidate tracks called “roads”. The problem is solved by the time data are loaded into the AM devices. We report on the tests of the integrate...

  2. The Associative Memory system for the FTK processor at ATLAS

    CERN Document Server

    Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2014-01-01

    Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. We present results and performances of a new prototype of Associative Memory system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the Atlas experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the Associative Memory (AM) technology exploiting parallelism to the maximum level: it compares the event to pre-calculated “expectations” or “patterns” (pattern matching) at once looking for candidate tracks called “roads”. The problem is solved by the time data are loaded into the AM devices. We report on the tests of the integrate...

  3. Testing the Tester: Lessons Learned During the Testing of a State-of-the-Art Commercial 14nm Processor Under Proton Irradiation

    Science.gov (United States)

    Szabo, Carl M., Jr.; Duncan, Adam R.; Label, Kenneth A.

    2017-01-01

    Testing of an Intel 14nm desktop processor was conducted under proton irradiation. We share lessons learned, demonstrating that complex devices beget further complex challenges requiring practical and theoretical investigative expertise to solve.

  4. Performance of the Harmony™ behind-the-ear processor with the first generation of Advanced Bionics™ implant systems.

    Science.gov (United States)

    Brendel, Martina; Rottmann, Tobias; Lenarz, Thomas; Buechner, Andreas

    2013-01-01

    When new cochlear implant (CI) sound processors are being introduced by the manufacturers, usually the newest generation implants benefit first from the new technology in order to release the full potential of the new hardware. Subsequently, for the Advanced Bionics system the Harmony behind-the-ear processor was only compatible to the newer generation implants, i.e. the CII and HiRes90K, at the time of market release. After further development of a new Digital Signal Processing code the Harmony could also support the first implant generation, the 'C1' (Clarion 1.0 and 1.2). This study reports on a field trial with a new sound processor designed to be used with older generation CIs from Advanced Bionics, focussing on ergonomic and performance benefits. Speech perception tests (Freiburger monosyllables, HSM sentence tests) were performed at a baseline appointment with the subject's clinical processor, followed by the fitting of the Harmony. After a 1 month take-home period the tests were repeated with the Harmony. Additionally, subjective evaluation through questionnaires and a structured interview were administered after upgrading to the sound processor 'C1 Harmony'. Adult users of Advanced Bionics C1 series CIs (n = 29) participated in this study. The new processor provided superior performance in many, though not all, of the speech recognition measurements. Subjective reports indicated certain practical benefits from the new processor, particularly for previous users of body-worn processors. Overall, 80% of the subjects preferred the new processor. The positive outcomes from this trial have resulted in the decision to make the new C1 Harmony processor available to all existing users of the early C1 devices.

  5. Level Zero Trigger processor for the ultra rare kaon decay experiment—NA62

    CERN Document Server

    Chiozzi, S; Gianoli, A; Mila, G; Neri, I; Petrucci, F; Soldi, D

    2016-01-01

    n the NA62 experiment at CERN-SPS the communication between detectors and the Lowest Level (L0) trigger processor is performed via Ethernet packets, using the UDP protocol. The L0 Trigger Processor handles the signals from sub-detectors that take part to the trigger generation. In order to choose the best solution for its realization, two different approaches have been implemented. The first approach is fully based on a FPGA device while the second one joins an off-the-shelf PC to the FPGA. The performance of the two systems will be discussed and compared.

  6. Embedded SoPC Design with Nios II Processor and Verilog Examples

    CERN Document Server

    Chu, Pong P

    2012-01-01

    Explores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog An SoPC (system on a programmable chip) integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as well-allowing us to configure the soft-core processor, create tailored I/O interfaces, and develop s

  7. An "artificial retina" processor for track reconstruction at the full LHC crossing rate

    Science.gov (United States)

    Abba, A.; Bedeschi, F.; Caponio, F.; Cenci, R.; Citterio, M.; Cusimano, A.; Fu, J.; Geraci, A.; Grizzuti, M.; Lusardi, N.; Marino, P.; Morello, M. J.; Neri, N.; Ninci, D.; Petruzzo, M.; Piucci, A.; Punzi, G.; Ristori, L.; Spinella, F.; Stracka, S.; Tonelli, D.; Walsh, J.

    2016-07-01

    We present the latest results of an R&D study for a specialized processor capable of reconstructing, in a silicon pixel detector, high-quality tracks from high-energy collision events at 40 MHz. The processor applies a highly parallel pattern-recognition algorithm inspired to quick detection of edges in mammals visual cortex. After a detailed study of a real-detector application, demonstrating that online reconstruction of offline-quality tracks is feasible at 40 MHz with sub-microsecond latency, we are implementing a prototype using common high-bandwidth FPGA devices.

  8. An “artificial retina” processor for track reconstruction at the full LHC crossing rate

    Energy Technology Data Exchange (ETDEWEB)

    Abba, A. [Istituto Nazionale di Fisica Nucleare – Sez. di Milano, Milano (Italy); Politecnico di Milano, Milano (Italy); Bedeschi, F. [Istituto Nazionale di Fisica Nucleare – Sez. di Pisa, Pisa (Italy); Caponio, F. [Istituto Nazionale di Fisica Nucleare – Sez. di Milano, Milano (Italy); Politecnico di Milano, Milano (Italy); Cenci, R., E-mail: riccardo.cenci@pi.infn.it [Istituto Nazionale di Fisica Nucleare – Sez. di Pisa, Pisa (Italy); Scuola Normale Superiore, Pisa (Italy); Citterio, M. [Istituto Nazionale di Fisica Nucleare – Sez. di Milano, Milano (Italy); Cusimano, A. [Istituto Nazionale di Fisica Nucleare – Sez. di Milano, Milano (Italy); Politecnico di Milano, Milano (Italy); Fu, J. [Istituto Nazionale di Fisica Nucleare – Sez. di Milano, Milano (Italy); Geraci, A.; Grizzuti, M.; Lusardi, N. [Istituto Nazionale di Fisica Nucleare – Sez. di Milano, Milano (Italy); Politecnico di Milano, Milano (Italy); Marino, P.; Morello, M.J. [Istituto Nazionale di Fisica Nucleare – Sez. di Pisa, Pisa (Italy); Scuola Normale Superiore, Pisa (Italy); Neri, N. [Istituto Nazionale di Fisica Nucleare – Sez. di Milano, Milano (Italy); Ninci, D. [Istituto Nazionale di Fisica Nucleare – Sez. di Pisa, Pisa (Italy); Università di Pisa, Pisa (Italy); Petruzzo, M. [Istituto Nazionale di Fisica Nucleare – Sez. di Milano, Milano (Italy); Università di Milano, Milano (Italy); Piucci, A.; Punzi, G. [Istituto Nazionale di Fisica Nucleare – Sez. di Pisa, Pisa (Italy); Università di Pisa, Pisa (Italy); Ristori, L. [Fermi National Accelerator Laboratory, Batavia, IL (United States); Spinella, F. [Istituto Nazionale di Fisica Nucleare – Sez. di Pisa, Pisa (Italy); and others

    2016-07-11

    We present the latest results of an R&D study for a specialized processor capable of reconstructing, in a silicon pixel detector, high-quality tracks from high-energy collision events at 40 MHz. The processor applies a highly parallel pattern-recognition algorithm inspired to quick detection of edges in mammals visual cortex. After a detailed study of a real-detector application, demonstrating that online reconstruction of offline-quality tracks is feasible at 40 MHz with sub-microsecond latency, we are implementing a prototype using common high-bandwidth FPGA devices.

  9. Pattern-Recognition Processor Using Holographic Photopolymer

    Science.gov (United States)

    Chao, Tien-Hsin; Cammack, Kevin

    2006-01-01

    proposed joint-transform optical correlator (JTOC) would be capable of operating as a real-time pattern-recognition processor. The key correlation-filter reading/writing medium of this JTOC would be an updateable holographic photopolymer. The high-resolution, high-speed characteristics of this photopolymer would enable pattern-recognition processing to occur at a speed three orders of magnitude greater than that of state-of-the-art digital pattern-recognition processors. There are many potential applications in biometric personal identification (e.g., using images of fingerprints and faces) and nondestructive industrial inspection. In order to appreciate the advantages of the proposed JTOC, it is necessary to understand the principle of operation of a conventional JTOC. In a conventional JTOC (shown in the upper part of the figure), a collimated laser beam passes through two side-by-side spatial light modulators (SLMs). One SLM displays a real-time input image to be recognized. The other SLM displays a reference image from a digital memory. A Fourier-transform lens is placed at its focal distance from the SLM plane, and a charge-coupled device (CCD) image detector is placed at the back focal plane of the lens for use as a square-law recorder. Processing takes place in two stages. In the first stage, the CCD records the interference pattern between the Fourier transforms of the input and reference images, and the pattern is then digitized and saved in a buffer memory. In the second stage, the reference SLM is turned off and the interference pattern is fed back to the input SLM. The interference pattern thus becomes Fourier-transformed, yielding at the CCD an image representing the joint-transform correlation between the input and reference images. This image contains a sharp correlation peak when the input and reference images are matched. The drawbacks of a conventional JTOC are the following: The CCD has low spatial resolution and is not an ideal square

  10. Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

    Science.gov (United States)

    Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

    2010-01-01

    The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for

  11. Entanglement in a Quantum Annealing Processor

    Science.gov (United States)

    Lanting, T.; Przybysz, A. J.; Smirnov, A. Yu.; Spedalieri, F. M.; Amin, M. H.; Berkley, A. J.; Harris, R.; Altomare, F.; Boixo, S.; Bunyk, P.; Dickson, N.; Enderud, C.; Hilton, J. P.; Hoskinson, E.; Johnson, M. W.; Ladizinsky, E.; Ladizinsky, N.; Neufeld, R.; Oh, T.; Perminov, I.; Rich, C.; Thom, M. C.; Tolkacheva, E.; Uchaikin, S.; Wilson, A. B.; Rose, G.

    2014-04-01

    Entanglement lies at the core of quantum algorithms designed to solve problems that are intractable by classical approaches. One such algorithm, quantum annealing (QA), provides a promising path to a practical quantum processor. We have built a series of architecturally scalable QA processors consisting of networks of manufactured interacting spins (qubits). Here, we use qubit tunneling spectroscopy to measure the energy eigenspectrum of two- and eight-qubit systems within one such processor, demonstrating quantum coherence in these systems. We present experimental evidence that, during a critical portion of QA, the qubits become entangled and entanglement persists even as these systems reach equilibrium with a thermal environment. Our results provide an encouraging sign that QA is a viable technology for large-scale quantum computing.

  12. Intrusion Detection Architecture Utilizing Graphics Processors

    Directory of Open Access Journals (Sweden)

    Branislav Madoš

    2012-12-01

    Full Text Available With the thriving technology and the great increase in the usage of computer networks, the risk of having these network to be under attacks have been increased. Number of techniques have been created and designed to help in detecting and/or preventing such attacks. One common technique is the use of Intrusion Detection Systems (IDS. Today, number of open sources and commercial IDS are available to match enterprises requirements. However, the performance of these systems is still the main concern. This paper examines perceptions of intrusion detection architecture implementation, resulting from the use of graphics processor. It discusses recent research activities, developments and problems of operating systems security. Some exploratory evidence is presented that shows capabilities of using graphical processors and intrusion detection systems. The focus is on how knowledge experienced throughout the graphics processor inclusion has played out in the design of intrusion detection architecture that is seen as an opportunity to strengthen research expertise.

  13. Making CSB+-Tree Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performan...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  14. Time Manager Software for a Flight Processor

    Science.gov (United States)

    Zoerne, Roger

    2012-01-01

    Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

  15. Software-defined reconfigurable microwave photonics processor.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José

    2015-06-01

    We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

  16. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  17. Intra- and intersubject comparison of cochlear implant systems using the Esprit and the Tempo+ behind-the-ear speech processor.

    Science.gov (United States)

    Kompis, Martin; Jenk, Martin; Vischer, Mattheus W; Seifert, Eberhard; Häusler, Rudolf

    2002-12-01

    A patient with bilateral profound deafness was implanted with a Nucleus CI24M cochlear implant (CI) and used an Esprit behind-the-ear (BTE) speech processor. Thirteen months later, the implant had to be removed because of a cholesteatoma. As the same electrode could not be reinserted, a Medel combi40s CI was implanted in the same ear, and the patient used a Tempo+ BTE processor. After 1 year of use of the Combi40s/Tempo+ system, speech recognition was better and was rated better subjectively than with the CI24M/Esprit system. Speech recognition and subjective ratings were also assessed for two matched groups of nine CI users each, using either an Esprit or a Tempo+ processor. On average, speech recognition scores were higher for the group of Tempo+ users, but the difference was not statistically significant. Users of the Esprit processors rated their device higher in terms of cosmetic appearance and comfort of wearing.

  18. Silicon quantum processor with robust long-distance qubit couplings.

    Science.gov (United States)

    Tosi, Guilherme; Mohiyaddin, Fahd A; Schmitt, Vivien; Tenberg, Stefanie; Rahman, Rajib; Klimeck, Gerhard; Morello, Andrea

    2017-09-06

    Practical quantum computers require a large network of highly coherent qubits, interconnected in a design robust against errors. Donor spins in silicon provide state-of-the-art coherence and quantum gate fidelities, in a platform adapted from industrial semiconductor processing. Here we present a scalable design for a silicon quantum processor that does not require precise donor placement and leaves ample space for the routing of interconnects and readout devices. We introduce the flip-flop qubit, a combination of the electron-nuclear spin states of a phosphorus donor that can be controlled by microwave electric fields. Two-qubit gates exploit a second-order electric dipole-dipole interaction, allowing selective coupling beyond the nearest-neighbor, at separations of hundreds of nanometers, while microwave resonators can extend the entanglement to macroscopic distances. We predict gate fidelities within fault-tolerance thresholds using realistic noise models. This design provides a realizable blueprint for scalable spin-based quantum computers in silicon.Quantum computers will require a large network of coherent qubits, connected in a noise-resilient way. Tosi et al. present a design for a quantum processor based on electron-nuclear spins in silicon, with electrical control and coupling schemes that simplify qubit fabrication and operation.

  19. Assessment of directionality performances: comparison between Freedom and CP810 sound processors.

    Science.gov (United States)

    Razza, Sergio; Albanese, Greta; Ermoli, Lucilla; Zaccone, Monica; Cristofari, Eliana

    2013-10-01

    To compare speech recognition in noise for the Nucleus Freedom and CP810 sound processors using different directional settings among those available in the SmartSound portfolio. Single-subject, repeated measures study. Tertiary care referral center. Thirty-one monoaurally and binaurally implanted subjects (24 children and 7 adults) were enrolled. They were all experienced Nucleus Freedom sound processor users and achieved a 100% open set word recognition score in quiet listening conditions. Each patient was fitted with the Freedom and the CP810 processor. The program setting incorporated Adaptive Dynamic Range Optimization (ADRO) and adopted the directional algorithm BEAM (both devices) and ZOOM (only on CP810). Speech reception threshold (SRT) was assessed in a free-field layout, with disyllabic word list and interfering multilevel babble noise in the 3 different pre-processing configurations. On average, CP810 improved significantly patients' SRTs as compared to Freedom SP after 1 hour of use. Instead, no significant difference was observed in patients' SRT between the BEAM and the ZOOM algorithm fitted in the CP810 processor. The results suggest that hardware developments achieved in the design of CP810 allow an immediate and relevant directional advantage as compared to the previous-generation Freedom device.

  20. Focal-plane sensor-processor chips

    CERN Document Server

    Zarándy, Ákos

    2011-01-01

    Focal-Plane Sensor-Processor Chips explores both the implementation and application of state-of-the-art vision chips. Presenting an overview of focal plane chip technology, the text discusses smart imagers and cellular wave computers, along with numerous examples of current vision chips.

  1. Globe hosts launch of new processor

    CERN Multimedia

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  2. Multimode Radar Signal Processor Integration Facility.

    Science.gov (United States)

    1983-05-01

    been created in Lae host processor, the loader segment of the MRSP Support Software Package is invoked. This segment provides the user with a method...program, which is a tedious process and highly prone to error. 24 AFWAL-TR-83-1045 OP- INSTRUCTION W ’E CODE 01 LOAD HARD REGISTER 02 READ SOFT REGISTER 03

  3. Fuel processors for fuel cell APU applications

    Science.gov (United States)

    Aicher, T.; Lenz, B.; Gschnell, F.; Groos, U.; Federici, F.; Caprile, L.; Parodi, L.

    The conversion of liquid hydrocarbons to a hydrogen rich product gas is a central process step in fuel processors for auxiliary power units (APUs) for vehicles of all kinds. The selection of the reforming process depends on the fuel and the type of the fuel cell. For vehicle power trains, liquid hydrocarbons like gasoline, kerosene, and diesel are utilized and, therefore, they will also be the fuel for the respective APU systems. The fuel cells commonly envisioned for mobile APU applications are molten carbonate fuel cells (MCFC), solid oxide fuel cells (SOFC), and proton exchange membrane fuel cells (PEMFC). Since high-temperature fuel cells, e.g. MCFCs or SOFCs, can be supplied with a feed gas that contains carbon monoxide (CO) their fuel processor does not require reactors for CO reduction and removal. For PEMFCs on the other hand, CO concentrations in the feed gas must not exceed 50 ppm, better 20 ppm, which requires additional reactors downstream of the reforming reactor. This paper gives an overview of the current state of the fuel processor development for APU applications and APU system developments. Furthermore, it will present the latest developments at Fraunhofer ISE regarding fuel processors for high-temperature fuel cell APU systems on board of ships and aircrafts.

  4. Monotonicity in the limited processor sharing queue

    NARCIS (Netherlands)

    M. Nuyens; W. van der Weij (Wemke)

    2008-01-01

    htmlabstractWe study a processor sharing queue with a limited number of service positions and an infinite buffer. The occupied service positions share an underlying resource. We prove that for service times with a decreasing failure rate, the queue length is stochastically decreasing in the number

  5. A Demo Processor as an Educational Tool

    NARCIS (Netherlands)

    van Moergestel, L.; van Nieuwland, K.; Vermond, L.; Meyer, John-Jules Charles

    2014-01-01

    Explaining the workings of a processor can be done in several ways. Just a written explanation, some pictures, a simulator program or a real hardware demo. The research presented here is based on the idea that a slowly working hardware demo could be a nice tool to explain to IT students the inner

  6. CERN Technical Training: Signal Processor

    CERN Multimedia

    HR Department

    2009-01-01

    A new training is going to be held at CERN on the ADSP SHARC Family. The "System Development and Programming with the Analog Devices’ SHARC Family" course is a 3.5-day hands-on training on Analog Devices SHARC DSPs, focusing on the latest ‘368/9 and 37x families. General DSP architecture, peripherals available, booting up process and DSP code development will be covered. Hardware tools, debugging and hardware design guidelines will be introduced as well. The course id designed for System Designers needing to make informed decisions on design tradeoffs, Hardware Designers needing to develop external interfaces, and Code Developers needing to know how to get the highest performance from their algorithms. The course will take place, in English, from 31 March to 4 April in the CERN Technical Training Center. Few places are still available. Registrations are opened on the Technical Training page. More information on our catalogue: http://cta.cern.ch/cta2/f?p=110:9 or contact us with your que...

  7. Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

    Science.gov (United States)

    Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

    2017-11-01

    Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

  8. Clock generators for SOC processors circuits and architectures

    CERN Document Server

    Fahim, Amr

    2004-01-01

    This book explores the design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. The text takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The comprehensive coverage includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discrete-time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The book provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, as well as the circuit level.

  9. Array processors based on Gaussian fraction-free method

    Energy Technology Data Exchange (ETDEWEB)

    Peng, S.; Sedukhin, S. [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I.

    1998-03-01

    The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

  10. Small scale processors' engagement in cassava postharvest and ...

    African Journals Online (AJOL)

    ... to provide the needed services to the processors in terms of technical advice which will help them maximize the benefits of post-harvest technologies. Also, policies that will encourage the rural processors in diversification is recommended. Keywords: Cassava, Small scale, Processors, Livelihood activities and Household ...

  11. A lock circuit for a multi-core processor

    DEFF Research Database (Denmark)

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores that...

  12. Implementation of KRoC on Analog Devices' "SHARC" DSP

    NARCIS (Netherlands)

    Otten, G.W.; Schwirtz, M.H.; Schwirtz, Marcellinus H.; Bruis, R.; Bruis, R.; Broenink, Johannes F.; Bakkers, André; O'Neill, Brian C.

    1996-01-01

    This paper summarises the experiences gained at the Control Laboratory of the University of Twente in porting the Kent Retargetable occam Compiler -KroC -to the Analog Devices' ADSP21060 SHARC Digital Signal Processor. The choice of porting the KRoC to the DSP processor was in our view both a

  13. Multi-Core Processor Memory Contention Benchmark Analysis Case Study

    Science.gov (United States)

    Simon, Tyler; McGalliard, James

    2009-01-01

    Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

  14. Multiple core computer processor with globally-accessible local memories

    Energy Technology Data Exchange (ETDEWEB)

    Shalf, John; Donofrio, David; Oliker, Leonid

    2016-09-20

    A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

  15. Designing and evaluating hybrid techniques to detect transient faults in processors embedded in FPGAs

    OpenAIRE

    José Rodrigo Furlanetto de Azambuja

    2013-01-01

    Recent technology advances have provided faster and smaller devices for manufacturing circuits that while more efficient have become more sensitive to the effects of radiation. Smaller transistor dimensions, higher density integration, lower voltage supplies and higher operating frequencies are some of the characteristics that make energized particles an issue when dealing with integrated circuits in harsh environments. These types of particles have a major influence in processors working in ...

  16. Design of Processors with Reconfigurable Microarchitecture

    Directory of Open Access Journals (Sweden)

    Andrey Mokhov

    2014-01-01

    Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

  17. RISC Processors and High Performance Computing

    Science.gov (United States)

    Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

    1995-01-01

    This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

  18. Simplifying cochlear implant speech processor fitting

    OpenAIRE

    Willeboer, C.

    2008-01-01

    Conventional fittings of the speech processor of a cochlear implant (CI) rely to a large extent on the implant recipient's subjective responses. For each of the 22 intracochlear electrodes the recipient has to indicate the threshold level (T-level) and comfortable loudness level (C-level) while stimulated with pulse trains. Obtaining these behavioral measurements is a time-consuming task. It requires cooperation and considerable effort of the CI recipient. Especially in adults that have been ...

  19. CoNNeCT Baseband Processor Module

    Science.gov (United States)

    Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

    2011-01-01

    A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

  20. AC-DC Power Processor, Type I.

    Science.gov (United States)

    1979-11-01

    output vol taqv S ice the out put rectifiers drop is a 1 arqe percentaote of the output voltate value. F i ure 24 Ows5 the out put impedance of the AC-I)C...65- TABLE XII- AC-DC POWER PROCESSOR TEMPERATURE PROFILE AT 83"F AMBIENT (COMPONENT AND UNIT TEMPERATURES AT END OF 72 HOUR TESI ) T.C. NO. LOCATION

  1. Keystone Business Models for Network Security Processors

    Directory of Open Access Journals (Sweden)

    Arthur Low

    2013-07-01

    Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

  2. Intelligent trigger processor for the crystal box

    CERN Document Server

    Sanders, G H; Cooper, M D; Hart, G W; Hoffman, C M; Hogan, G E; Hughes, E B; Matis, H S; Rolfe, J; Sandberg, V D; Williams, R A; Wilson, S; Zeman, H

    1981-01-01

    A large solid angle angular modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor-changing decays of the muon. A beam of up to 10/sup 6/ muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor. Further reduction to <1 Hz is achieved by a microprocessor-based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic logic. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex ...

  3. A proposed electroacoustic test protocol for personal FM receivers coupled to cochlear implant sound processors.

    Science.gov (United States)

    Schafer, Erin C; Musgrave, Elizabeth; Momin, Sadaf; Sandrock, Carl; Romine, Denise

    2013-01-01

    Current fitting guidelines from the American Academy of Audiology (Academy) support the use of objective electroacoustic measures and behavioral testing when fitting frequency modulation (FM) systems to hearing aids. However, only behavioral testing is recommended when fitting FM systems to individuals with cochlear implants (CIs) because a protocol for conducting electroacoustic measures has yet to be developed for this population. The purpose of this study was to propose and examine the validity of a newly developed, objective, electroacoustic test protocol for fitting electrically and electromagnetically coupled FM systems to CI sound processors. Electroacoustic measures were conducted and replicated in the laboratory with three contemporary CI sound processors and several FM system combinations. A repeated measures design was used with four participants to examine the validity of the proposed electroacoustic test protocol. Three contemporary CI sound processors were tested electroacoustically in the laboratory while coupled to combinations of five FM receivers and four FM transmitters. Two adolescents using Cochlear Nucleus 5 sound processors and two adult participants using MED-EL OPUS 2 sound processors completed behavioral and subjective measures. Using current hearing aid practice guidelines from the Academy, electroacoustic measurements were conducted in the laboratory with the CIs and FM systems to determine transparency, where equivalent inputs to the CI and FM microphones result in equivalent outputs. Using a hearing aid analyzer, acoustic output from the CI sound processor was measured via monitor earphones and specialized equipment from CI manufacturers with 65 dB SPL speech inputs (1) to the sound processor and (2) to the FM transmitter microphones. The FM gain or volume was adjusted to attempt to achieve transparency for outputs from the two input devices. The four participants completed some or all of the following measures: speech recognition in

  4. Merged ozone profiles from four MIPAS processors

    Science.gov (United States)

    Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus

    2017-04-01

    The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv

  5. Software for embedded processors: Problems and solutions

    Science.gov (United States)

    Bogaerts, J. A. C.

    1990-08-01

    Data Acquistion systems in HEP experiments use a wide spectrum of computers to cope with two major problems: high event rates and a large data volume. They do this by using special fast trigger processors at the source to reduce the event rate by several orders of magnitude. The next stage of a data acquisition system consists of a network of fast but conventional microprocessors which are embedded in high speed bus systems where data is still further reduced, filtered and merged. In the final stage complete events are farmed out to a another collection of processors, which reconstruct the events and perhaps achieve a further event rejection by a small factor, prior to recording onto magnetic tape. Detectors are monitored by analyzing a fraction of the data. This may be done for individual detectors at an early state of the data acquisition or it may be delayed till the complete events are available. A network of workstations is used for monitoring, displays and run control. Software for trigger processors must have a simple structure. Rejection algorithms are carefully optimized, and overheads introduced by system software cannot be tolerated. The embedded microprocessors have to co-operate, and need to be synchronized with the preceding and following stages. Real time kernels are typically used to solve synchronization and communication problems. Applications are usually coded in C, which is reasonably efficient and allows direct control over low level hardware functions. Event reconstruction software is very similar or even identical to offline software, predominantly written in FORTRAN. With the advent of powerful RISC processors, and with manufacturers tending to adopt open bus architectures, there is a move towards commercial processors and hence the introduction of the UNIX operating system. Building and controlling such a heterogeneous data acquisition system puts a heavy strain on the software. Communications is now as important as CPU capacity and I

  6. Productivity and quality performance of an innovative firewood processor

    Directory of Open Access Journals (Sweden)

    Raffaele Cavalli

    2014-06-01

    Full Text Available The growing interest about wood as fuel regards not only wood chips and pellets but also firewood, especially in mountain and rural areas where domestic heating plants are widely used. Due to the increased demand for firewood, harvesting activities have extended on broadleaved high forests as well as coppice. As a consequence, the diameter of logs has increased requiring larger and larger splitting machines; nowadays it is not uncommon to find on the market splitters able to process logs with diameter up to 50-60 cm. In order to increase the productivity, the effort of machine producers is directed to obtain the complete splitting of the log into firewood in only one step using multiple ways splitting knives. This technical solution may cause some drawbacks especially when the splitting knives are not properly adapted to the log diameter; it happens that the size of firewood is not homogeneous and splinters are produced, which requires using screens to separate them from the main product. In order to evaluate the work quality of a firewood processor, equipped with multiple ways splitting knives, an experimental test has been carried out using a machine in which the log diameter is automatically detected through a laser device; according to the log diameter the multiple ways splitting knives (formed by fixed and mobile knives, the latter hydraulically operated is properly set up to obtain regularly sized firewood. Furthermore the log is automatically centred on the splitting knife set-up. The results of the experimental test showed that the firewood processor is able to produce firewood with homogeneous size and with a low production of splinters, regardless of log diameter.

  7. Performance aspects of the adjustable bandwidth concept (ABC) predetection processor

    Science.gov (United States)

    Noga, Andrew J.

    2003-08-01

    There are a variety of domains in which signal channelization has proven to be useful, including the time, frequency, spatial and polarization domains. These partitioning techniques are necessary for the proper management and effective utilization of the overall channel resource. The term "multi-channel" is used to describe this partitioning of these domains. However, there are other "domains" in which channelization techniques can be employed. These include the coding domain (as in code-division multiple-access) and the less obvious steganographic domain. One can argue that these latter examples of domains lack the physical interpretation of their counterparts, or that they are each in fact a clever use of the standard domains. But from the view of the overall channel resource, very effective utilization and management tools can be developed, operated and described in these domains. In this paper, a technique is studied which is based upon a novel utilization of the signal bandwidth domain, for pre-processing prior to detection and parameter estimation. Experimental and theoretical results will be given for assessment of device performance. The studied technique is referred to as the Adjustable Bandwidth Concept (ABC) signal energy detector. When implemented digitally, this device is essentially a cepstral-based pre-processor for generating multiple channels for the analysis and detection of signal components of distinguishable bandwidths. The ABC device processes an input log-magnitude spectrogram and results in a multi-channel output. Each output channel contains information regarding the input spectrogram which is sorted or partitioned based on the bandwidth of signal components within the spectrogram. A primary application of such a device is as a pre-processing step prior to detection and estimation, for automated spectral survey and characterization.

  8. The artificial retina processor for track reconstruction at the LHC crossing rate

    Science.gov (United States)

    Abba, A.; Bedeschi, F.; Citterio, M.; Caponio, F.; Cusimano, A.; Geraci, A.; Marino, P.; Morello, M. J.; Neri, N.; Punzi, G.; Piucci, A.; Ristori, L.; Spinella, F.; Stracka, S.; Tonelli, D.

    2015-03-01

    We present results of an R&D study for a specialized processor capable of precisely reconstructing, in pixel detectors, hundreds of charged-particle tracks from high-energy collisions at 40 MHz rate. We apply a highly parallel pattern-recognition algorithm, inspired by studies of the processing of visual images by the brain as it happens in nature, and describe in detail an efficient hardware implementation in high-speed, high-bandwidth FPGA devices. This is the first detailed demonstration of reconstruction of offline-quality tracks at 40 MHz and makes the device suitable for processing Large Hadron Collider events at the full crossing frequency.

  9. Digital signal processors in the LHCb level-1 vertex trigger system

    CERN Document Server

    Bouianov, O

    1999-01-01

    99-002 The note discusses the use of Analog Devices' SHARC Digital Signal Processors for the Level-1 Vertex Trigger system implementation. It presents a short overview of current and future Analog Devices' floating-point DSP architectures, multiprocessor system architectures and a survey of available standard DSP board-level components and software for multiprocessor applications. A possible solution for mapping the vertex trigger algorithm on the scaleable DSP multiprocessor is discussed with analysis of its implementation using standard DSP multiprocessor components.

  10. Introduction to programming multiple-processor computers

    Energy Technology Data Exchange (ETDEWEB)

    Hicks, H.R.; Lynch, V.E.

    1985-04-01

    FORTRAN applications programs can be executed on multiprocessor computers in either a unitasking (traditional) or multitasking form. The latter allows a single job to use more than one processor simultaneously, with a consequent reduction in wall-clock time and, perhaps, the cost of the calculation. An introduction to programming in this environment is presented. The concepts of synchronization and data sharing using EVENTS and LOCKS are illustrated with examples. The strategy of strong synchronization and the use of synchronization templates are proposed. We emphasize that incorrect multitasking programs can produce irreproducible results, which makes debugging more difficult.

  11. Optical linear algebra processors - Architectures and algorithms

    Science.gov (United States)

    Casasent, David

    1986-01-01

    Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

  12. Search Engine Processor: filtering and organizing PSMs

    Science.gov (United States)

    Carvalho, Paulo C.; Fischer, Juliana S. G.; Xu, Tao; Cociorva, Daniel; Balbuena, Tiago S.; Valente, Richard H.; Perales, Jonas; Yates, John R.; Barbosa, Valmir C.

    2012-01-01

    The Search Engine Processor (SEPro) is a tool for filtering, organizing, sharing, and displaying peptide spectrum matches. It employs a novel three-tier Bayesian approach that uses layers of spectrum, peptide, and protein logic to lead the data to converge to a single list of reliable protein identifications. SEPro is integrated into the PatternLab for proteomics environment, where an arsenal of tools for analyzing shotgun proteomic data is provided. By using the semi-labeled decoy approach for benchmarking, we show that SEPro significantly outperforms a commercially available competitor. PMID:22311825

  13. Digital signal processor fundamentals and system design

    CERN Document Server

    Angoletta, M E

    2008-01-01

    Digital Signal Processors (DSPs) have been used in accelerator systems for more than fifteen years and have largely contributed to the evolution towards digital technology of many accelerator systems, such as machine protection, diagnostics and control of beams, power supply and motors. This paper aims at familiarising the reader with DSP fundamentals, namely DSP characteristics and processing development. Several DSP examples are given, in particular on Texas Instruments DSPs, as they are used in the DSP laboratory companion of the lectures this paper is based upon. The typical system design flow is described; common difficulties, problems and choices faced by DSP developers are outlined; and hints are given on the best solution.

  14. Electromagnetic versus electrical coupling of personal frequency modulation (FM) receivers to cochlear implant sound processors.

    Science.gov (United States)

    Schafer, Erin C; Romine, Denise; Musgrave, Elizabeth; Momin, Sadaf; Huynh, Christy

    2013-01-01

    that both FM receivers provided significantly better speech-recognition performance in noise than the CI alone; however, the electromagnetically coupled receiver provided significantly better speech-recognition performance in noise and better ratings in some situations than the electrically coupled receiver when set to the same gain. In Experiment 2, the primary analysis suggested significantly better speech-recognition performance in noise for the neck-loop versus electrically coupled receiver, but a second analysis, using the best performance across gain settings for each device, revealed no significant differences between the two FM receivers. Experiment 3 revealed monitor-earphone output differences in the Nucleus 5 sound processor for the two FM receivers when set to the +8 setting used in Experiment 1 but equal output when the electrically coupled device was set to a +16 gain setting and the electromagnetically coupled device was set to the +8 gain setting. Individuals with contemporary sound processors may show more favorable speech-recognition performance in noise electromagnetically coupled FM systems (i.e., Oticon Arc), which is most likely related to the input processing and signal processing pathway within the CI sound processor for direct input versus telecoil input. Further research is warranted to replicate these findings with a larger sample size and to develop and validate a more objective approach to fitting FM systems to CI sound processors. American Academy of Audiology.

  15. A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding

    Directory of Open Access Journals (Sweden)

    Muhammad Asif

    2015-01-01

    Full Text Available One of the key requirements for mobile devices is to provide high-performance computing at lower power consumption. The processors used in these devices provide specific hardware resources to handle computationally intensive video processing and interactive graphical applications. Moreover, processors designed for low-power applications may introduce limitations on the availability and usage of resources, which present additional challenges to the system designers. Owing to the specific design of the JZ47x series of mobile application processors, a hybrid software-hardware implementation scheme for H.264/AVC encoder is proposed in this work. The proposed scheme distributes the encoding tasks among hardware and software modules. A series of optimization techniques are developed to speed up the memory access and data transferring among memories. Moreover, an efficient data reusage design is proposed for the deblock filter video processing unit to reduce the memory accesses. Furthermore, fine grained macroblock (MB level parallelism is effectively exploited and a pipelined approach is proposed for efficient utilization of hardware processing cores. Finally, based on parallelism in the proposed design, encoding tasks are distributed between two processing cores. Experiments show that the hybrid encoder is 12 times faster than a highly optimized sequential encoder due to proposed techniques.

  16. Vibration analysis of a blood processor centrifuge with anti-twister mechanism.

    Science.gov (United States)

    Herman, H; Dastane, A; Sofer, S

    1991-01-01

    This paper deals with the vibration analysis of a blood processor centrifuge with an anti-twister mechanism. Blood processors that employ anti-twister mechanisms are becoming increasingly popular because they cause relatively less damage to the blood than the conventional ones, which employ rotating seals. Knowledge of the vibration response of the device in its operating regime is important for trouble-free operation. A simple, three-degree-of-freedom, lumped-parameter, torsional-mode model is presented here. This model was used to analyse an existing blood processor. On comparing experimental and analytical values, it was found that the fundamental frequency as predicted analytically is within 19 per cent of the experimental value; the predicted second harmonic is about 28 per cent higher than the experimental one. Thus the proposed model predicts the fundamental frequency with reasonable accuracy. In design, the goal is to keep the operating frequency of the device sufficiently above the fundamental frequency to avoid resonance problems.

  17. Systems and methods for reconfiguring input devices

    Science.gov (United States)

    Lancaster, Jeff (Inventor); De Mers, Robert E. (Inventor)

    2012-01-01

    A system includes an input device having first and second input members configured to be activated by a user. The input device is configured to generate activation signals associated with activation of the first and second input members, and each of the first and second input members are associated with an input function. A processor is coupled to the input device and configured to receive the activation signals. A memory coupled to the processor, and includes a reconfiguration module configured to store the input functions assigned to the first and second input members and, upon execution of the processor, to reconfigure the input functions assigned to the input members when the first input member is inoperable.

  18. Jones matrix treatment for optical Fourier processors with structured polarization

    National Research Council Canada - National Science Library

    Moreno, Ignacio; Iemmi, Claudio; Campos, Juan; Yzuel, Maria J

    2011-01-01

    .... The proposed method is a generalization of the standard classical optical Fourier transform processor, but considering vectorial spatial functions with two complex components corresponding to two...

  19. Compiler Optimization to Improve Data Locality for Processor Multithreading

    Directory of Open Access Journals (Sweden)

    Balaram Sinharoy

    1999-01-01

    Full Text Available Over the last decade processor speed has increased dramatically, whereas the speed of the memory subsystem improved at a modest rate. Due to the increase in the cache miss latency (in terms of the processor cycle, processors stall on cache misses for a significant portion of its execution time. Multithreaded processors has been proposed in the literature to reduce the processor stall time due to cache misses. Although multithreading improves processor utilization, it may also increase cache miss rates, because in a multithreaded processor multiple threads share the same cache, which effectively reduces the cache size available to each individual thread. Increased processor utilization and the increase in the cache miss rate demands higher memory bandwidth. A novel compiler optimization method has been presented in this paper that improves data locality for each of the threads and enhances data sharing among the threads. The method is based on loop transformation theory and optimizes both spatial and temporal data locality. The created threads exhibit high level of intra‐thread and inter‐thread data locality which effectively reduces both the data cache miss rates and the total execution time of numerically intensive computation running on a multithreaded processor.

  20. Reconfigurable Very Long Instruction Word (VLIW) Processor

    Science.gov (United States)

    Velev, Miroslav N.

    2015-01-01

    Future NASA missions will depend on radiation-hardened, power-efficient processing systems-on-a-chip (SOCs) that consist of a range of processor cores custom tailored for space applications. Aries Design Automation, LLC, has developed a processing SOC that is optimized for software-defined radio (SDR) uses. The innovation implements the Institute of Electrical and Electronics Engineers (IEEE) RazorII voltage management technique, a microarchitectural mechanism that allows processor cores to self-monitor, self-analyze, and selfheal after timing errors, regardless of their cause (e.g., radiation; chip aging; variations in the voltage, frequency, temperature, or manufacturing process). This highly automated SOC can also execute legacy PowerPC 750 binary code instruction set architecture (ISA), which is used in the flight-control computers of many previous NASA space missions. In developing this innovation, Aries Design Automation has made significant contributions to the fields of formal verification of complex pipelined microprocessors and Boolean satisfiability (SAT) and has developed highly efficient electronic design automation tools that hold promise for future developments.

  1. Coordinated Energy Management in Heterogeneous Processors

    Directory of Open Access Journals (Sweden)

    Indrani Paul

    2014-01-01

    Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

  2. Comparisons of sound processors based on osseointegrated implants in patients with conductive or mixed hearing loss.

    Science.gov (United States)

    Pfiffner, Flurin; Caversaccio, Marco D; Kompis, Martin

    2011-07-01

    To compare the patient benefit of the Bone-Anchored Hearing Aid (Baha) Divino and the Baha BP100 sound processors. Prospective experimental study. Tertiary referral center. Twenty experienced Baha Divino users with conductive or mixed hearing loss. Speech understanding in quiet and in noise was measured in unaided conditions and with the subjects' own Divino sound processors. Speech in noise was tested with the noise arriving either from the front or from the back of the subjects. Then, participants were fitted with BP100 sound processors. After 3 months of use, all speech tests were repeated with the new sound processor along with a subset of the tests from the first session to assess learning or training effects. The Abbreviated Profile of Hearing Aid Benefit (APHAB) questionnaires were administered at 0 and at 3 months. Aided speech understanding in quiet and in noise. No significant differences were found between the two devices regarding speech understanding in quiet. Speech understanding in noise was improved, on average, by +1.0 to +2.3 dB with the BP100 when compared to the Divino. No significant learning effects were found. Subjective ratings assessed by the Abbreviated Profile of Hearing Aid Benefit (APHAB) questionnaire showed statistically significantly better scores for the BP100 for noisy or reverberant environments, when compared with the Divino. The performance of both devices is similar for speech understanding in quiet. Speech understanding in noise is significantly better with the Baha BP100 than with the Baha Divino, presumably as a result of the improved signal processing.

  3. Off the ear with no loss in speech understanding: comparing the RONDO and the OPUS 2 cochlear implant audio processors.

    Science.gov (United States)

    Dazert, Stefan; Thomas, Jan Peter; Büchner, Andreas; Müller, Joachim; Hempel, John Martin; Löwenheim, Hubert; Mlynski, Robert

    2017-03-01

    The RONDO is a single-unit cochlear implant audio processor, which omits the need for a behind-the-ear (BTE) audio processor. The primary aim was to compare speech perception results in quiet and in noise with the RONDO and the OPUS 2, a BTE audio processor. Secondary aims were to determine subjects' self-assessed levels of sound quality and gather subjective feedback on RONDO use. All speech perception tests were performed with the RONDO and the OPUS 2 behind-the-ear audio processor at 3 test intervals. Subjects were required to use the RONDO between test intervals. Subjects were tested at upgrade from the OPUS 2 to the RONDO and at 1 and 6 months after upgrade. Speech perception was determined using the Freiburg Monosyllables in quiet test and the Oldenburg Sentence Test (OLSA) in noise. Subjective perception was determined using the Hearing Implant Sound Quality Index (HISQUI19), and a RONDO device-specific questionnaire. 50 subjects participated in the study. Neither speech perception scores nor self-perceived sound quality scores were significantly different at any interval between the RONDO and the OPUS 2. Subjects reported high levels of satisfaction with the RONDO. The RONDO provides comparable speech perception to the OPUS 2 while providing users with high levels of satisfaction and comfort without increasing health risk. The RONDO is a suitable and safe alternative to traditional BTE audio processors.

  4. On the effective parallel programming of multi-core processors

    NARCIS (Netherlands)

    Varbanescu, A.L.

    2010-01-01

    Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are

  5. Temporal Partitioning and Multi-Processor Scheduling for Reconfigurable Architectures

    DEFF Research Database (Denmark)

    Popp, Andreas; Le Moullec, Yannick; Koch, Peter

    This poster presentation outlines a proposed framework for handling mapping of signal processing applications to heterogeneous reconfigurable architectures. The methodology consists of an extension to traditional multi-processor scheduling by creating a separate HW track for generation of groups...... of tasks that are handled similarly to SW processes in a traditional multi-processor scheduling context....

  6. assessment of processors and marketers of sheabutter (vitellaria

    African Journals Online (AJOL)

    User

    ABSTRACT. The study examined the processing and marketing of Shea butter in Zuru Local Government. Area of Kebbi State, Nigeria to identify the socioeconomic characteristics of Shea butter processors and marketers, the average cost and return of Shea butter processors and marketers and the determinant variables of ...

  7. Soft-core processor study for node-based architectures.

    Energy Technology Data Exchange (ETDEWEB)

    Van Houten, Jonathan Roger; Jarosz, Jason P.; Welch, Benjamin James; Gallegos, Daniel E.; Learn, Mark Walter

    2008-09-01

    Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable Field Programmable Gate Array (FPGA) based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hardcore processor built into the FPGA or as a soft-core processor built out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA based processors for use in future NBA systems--two soft cores (MicroBlaze and non-fault-tolerant LEON) and one hard core (PowerPC 405). Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration. Cache configurations impacted the results greatly; for optimal processor efficiency it is necessary to enable caches on the processors. Processor caches carry a penalty; cache error mitigation is necessary when operating in a radiation environment.

  8. Excavator-based processor operator productivity and cost analysis ...

    African Journals Online (AJOL)

    Operator impact on productivity and cost using similar processor machines was addressed in this case study. The study had two objectives: (1) determine the extent of operator productivity variation between six processor operators in a harvesting operation; and (2) determine potential cost implications associated with ...

  9. Message Passing on a Time-predictable Multicore Processor

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Puffitsch, Wolfgang; Schoeberl, Martin

    2015-01-01

    Real-time systems need time-predictable computing platforms. For a multicore processor to be time-predictable, communication between processor cores needs to be time-predictable as well. This paper presents a time-predictable message-passing library for such a platform. We show how to build up...

  10. A processor sharing model for wireless data communication

    DEFF Research Database (Denmark)

    Hansen, Martin Bøgsted

    ) allow already established resources for data connections to be downgraded to allow a new connection to be established. As noted by Litjens and Boucherie (2002) this resembles classical processor sharing models, and in this spirit we formulate a variant of the processor sharing model with a limited...

  11. GA103 a microprogrammable processor for online filtering

    CERN Document Server

    Calzas, A; Danon, G

    1981-01-01

    GA103 is a 16 bit microprogrammable processor, which emulates the PDP 11 instruction set. It is based on the Am2900 slices. It allows user- implemented microinstructions and addition of hardwired processors. It will perform online filtering tasks in the NA14 experiment at CERN, based on the reconstruction of transverse momentum of photons detected in a lead glass calorimeter. (3 refs).

  12. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  13. Assessment of Processors and Marketers of Sheabutter ( Vitellaria ...

    African Journals Online (AJOL)

    The study examined the processing and marketing of Shea butter in Zuru Local Government Area of Kebbi State, Nigeria to identify the socioeconomic characteristics of Shea butter processors and marketers, the average cost and return of Shea butter processors and marketers and the determinant variables of profitability ...

  14. A software framework to calculate local temperatures in CMOS processors

    NARCIS (Netherlands)

    Rohani, A.; Ebrahimi, Hassan; Kerkhoff, Hans G.

    2016-01-01

    A conventional technique to rise temperature in a processor involves the usage of thermal ovens or infrared techniques to heat up and then measure the temperature of the processor. However, local temperatures of each module cannot be controlled by these techniques. This paper presents a software

  15. Digital Signal Processor System for AC Power Drivers

    Directory of Open Access Journals (Sweden)

    Ovidiu Neamtu

    2009-10-01

    Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  16. Efficient quantum walk on a quantum processor

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L.; Wang, Jingbo B.; Matthews, Jonathan C. F.

    2016-01-01

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor. PMID:27146471

  17. Automated Sequence Processor: Something Old, Something New

    Science.gov (United States)

    Streiffert, Barbara; Schrock, Mitchell; Fisher, Forest; Himes, Terry

    2012-01-01

    High productivity required for operations teams to meet schedules Risk must be minimized. Scripting used to automate processes. Scripts perform essential operations functions. Automated Sequence Processor (ASP) was a grass-roots task built to automate the command uplink process System engineering task for ASP revitalization organized. ASP is a set of approximately 200 scripts written in Perl, C Shell, AWK and other scripting languages.. ASP processes/checks/packages non-interactive commands automatically.. Non-interactive commands are guaranteed to be safe and have been checked by hardware or software simulators.. ASP checks that commands are non-interactive.. ASP processes the commands through a command. simulator and then packages them if there are no errors.. ASP must be active 24 hours/day, 7 days/week..

  18. Efficient quantum walk on a quantum processor.

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L; Wang, Jingbo B; Matthews, Jonathan C F

    2016-05-05

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor.

  19. Processor-in-memory-and-storage architecture

    Energy Technology Data Exchange (ETDEWEB)

    DeBenedictis, Erik

    2018-01-02

    A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

  20. Face feature processor on mobile service robot

    Science.gov (United States)

    Ahn, Ho Seok; Park, Myoung Soo; Na, Jin Hee; Choi, Jin Young

    2005-12-01

    In recent years, many mobile service robots have been developed. These robots are different from industrial robots. Service robots were confronted to unexpected changes in the human environment. So many capabilities were needed to service mobile robot, for example, the capability to recognize people's face and voice, the capability to understand people's conversation, and the capability to express the robot's thinking etc. This research considered face detection, face tracking and face recognition from continuous camera image. For face detection module, it used CBCH algorithm using openCV library from Intel Corporation. For face tracking module, it used the fuzzy controller to control the pan-tilt camera movement smoothly with face detection result. A PCA-FX, which adds class information to PCA, was used for face recognition module. These three procedures were called face feature processor, which were implemented on mobile service robot OMR to verify.

  1. RADAP II, an interim radar data processor

    Science.gov (United States)

    Greene, D. R.; Nilsen, J. D.; Saffle, R. E.; Holmes, D. W.; Hudlow, M. D.; Ahnert, P. R.

    The RADAP (radar data processor) II system, which is developed by the National Weather Service and is a follow-up of the D/RADEX (Digitized Radar Experiment) is described. RADAP maintains the present automatic digital processing capabilities at the D/RADEX sites and extends these capabilities to include 10 network sites in order to fulfill the digital radar data requirements during the period before the production of the Next-Generation Weather Radar (NEXRAD) systems. Consideration is given to the current and future users of the RADAP II data, to the system capability, operational requirements, and hardware; to the installation schedule, and to the products of RADAP II. RADAP II is used for the continued development and testing of applications software to provide feedback on the operational usefulness of the software which is critical to the successful design and development of the NEXRAD system.

  2. Silicon quantum processor with robust long-distance qubit couplings

    Energy Technology Data Exchange (ETDEWEB)

    Tosi, Guilherme; Mohiyaddin, Fahd A.; Schmitt, Vivien; Tenberg, Stefanie; Rahman, Rajib; Klimeck, Gerhard; Morello, Andrea

    2017-09-06

    Practical quantum computers require a large network of highly coherent qubits, interconnected in a design robust against errors. Donor spins in silicon provide state-of-the-art coherence and quantum gate fidelities, in a platform adapted from industrial semiconductor processing. Here we present a scalable design for a silicon quantum processor that does not require precise donor placement and leaves ample space for the routing of interconnects and readout devices. We introduce the flip-flop qubit, a combination of the electron-nuclear spin states of a phosphorus donor that can be controlled by microwave electric fields. Two-qubit gates exploit a second-order electric dipole-dipole interaction, allowing selective coupling beyond the nearest-neighbor, at separations of hundreds of nanometers, while microwave resonators can extend the entanglement to macroscopic distances. We predict gate fidelities within fault-tolerance thresholds using realistic noise models. This design provides a realizable blueprint for scalable spin-based quantum computers in silicon.

  3. Multi-threaded ATLAS simulation on Intel Knights Landing processors

    Science.gov (United States)

    Farrell, Steven; Calafiura, Paolo; Leggett, Charles; Tsulaia, Vakhtang; Dotti, Andrea; ATLAS Collaboration

    2017-10-01

    The Knights Landing (KNL) release of the Intel Many Integrated Core (MIC) Xeon Phi line of processors is a potential game changer for HEP computing. With 72 cores and deep vector registers, the KNL cards promise significant performance benefits for highly-parallel, compute-heavy applications. Cori, the newest supercomputer at the National Energy Research Scientific Computing Center (NERSC), was delivered to its users in two phases with the first phase online at the end of 2015 and the second phase now online at the end of 2016. Cori Phase 2 is based on the KNL architecture and contains over 9000 compute nodes with 96GB DDR4 memory. ATLAS simulation with the multithreaded Athena Framework (AthenaMT) is a good potential use-case for the KNL architecture and supercomputers like Cori. ATLAS simulation jobs have a high ratio of CPU computation to disk I/O and have been shown to scale well in multi-threading and across many nodes. In this paper we will give an overview of the ATLAS simulation application with details on its multi-threaded design. Then, we will present a performance analysis of the application on KNL devices and compare it to a traditional x86 platform to demonstrate the capabilities of the architecture and evaluate the benefits of utilizing KNL platforms like Cori for ATLAS production.

  4. Heat dissipation for the Intel Core i5 processor using multiwalled carbon-nanotube-based ethylene glycol

    Science.gov (United States)

    Thang, Bui Hung; Van Trinh, Pham; Quang, Le Dinh; Huong, Nguyen Thi; Khoi, Phan Hong; Minh, Phan Ngoc

    2014-08-01

    Carbon nanotubes (CNTs) are some of the most valuable materials with high thermal conductivity. The thermal conductivity of individual multiwalled carbon nanotubes (MWCNTs) grown by using chemical vapor deposition is 600 ± 100 Wm-1K-1 compared with the thermal conductivity 419 Wm-1K-1 of Ag. Carbon-nanotube-based liquids — a new class of nanomaterials, have shown many interesting properties and distinctive features offering potential in heat dissipation applications for electronic devices, such as computer microprocessor, high power LED, etc. In this work, a multiwalled carbon-nanotube-based liquid was made of well-dispersed hydroxyl-functional multiwalled carbon nanotubes (MWCNT-OH) in ethylene glycol (EG)/distilled water (DW) solutions by using Tween-80 surfactant and an ultrasonication method. The concentration of MWCNT-OH in EG/DW solutions ranged from 0.1 to 1.2 gram/liter. The dispersion of the MWCNT-OH-based EG/DW solutions was evaluated by using a Zeta-Sizer analyzer. The MWCNT-OH-based EG/DW solutions were used as coolants in the liquid cooling system for the Intel Core i5 processor. The thermal dissipation efficiency and the thermal response of the system were evaluated by directly measuring the temperature of the micro-processor using the Core Temp software and the temperature sensors built inside the micro-processor. The results confirmed the advantages of CNTs in thermal dissipation systems for computer processors and other high-power electronic devices.

  5. Acoustooptic linear algebra processors - Architectures, algorithms, and applications

    Science.gov (United States)

    Casasent, D.

    1984-01-01

    Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

  6. Experimental testing of the noise-canceling processor.

    Science.gov (United States)

    Collins, Michael D; Baer, Ralph N; Simpson, Harry J

    2011-09-01

    Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

  7. Multiple Embedded Processors for Fault-Tolerant Computing

    Science.gov (United States)

    Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

    2005-01-01

    A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

  8. A Fully Automatic Burnt Area Mapping Processor Based on AVHRR Imagery—A TIMELINE Thematic Processor

    Directory of Open Access Journals (Sweden)

    Simon Plank

    2018-02-01

    Full Text Available The German Aerospace Center’s (DLR TIMELINE project (“Time Series Processing of Medium Resolution Earth Observation Data Assessing Long-Term Dynamics in our Natural Environment” aims to develop an operational processing and data management environment to process 30 years of National Oceanic and Atmospheric Administration (NOAA—Advanced Very High-Resolution Radiometer (AVHRR raw data into Level (L 1b, L2, and L3 products. This article presents the current status of the fully automated L3 burnt area mapping processor, which is based on multi-temporal datasets. The advantages of the proposed approach are (I the combined use of different indices to improve the classification result, (II the provision of a fully automated processor, (III the generation and usage of an up-to-date cloud-free pre-fire dataset, (IV classification with adaptive thresholding, and (V the assignment of five different probability levels to the burnt areas detected. The results of the AVHRR data-based burn scar mapping processor were validated with the Moderate Resolution Imaging Spectroradiometer (MODIS burnt area product MCD64 at four different European study sites. In addition, the accuracy of the AVHRR-based classification and that of the MCD64 itself were assessed by means of Landsat imagery.

  9. Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

    Science.gov (United States)

    Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

    2009-03-17

    A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

  10. Speech Intelligibility in Various Noise Conditions with the Nucleus® 5 CP810 Sound Processor.

    Science.gov (United States)

    Dillier, Norbert; Lai, Wai Kong

    2015-06-11

    The Nucleus(®) 5 System Sound Processor (CP810, Cochlear™, Macquarie University, NSW, Australia) contains two omnidirectional microphones. They can be configured as a fixed directional microphone combination (called Zoom) or as an adaptive beamformer (called Beam), which adjusts the directivity continuously to maximally reduce the interfering noise. Initial evaluation studies with the CP810 had compared performance and usability of the new processor in comparison with the Freedom™ Sound Processor (Cochlear™) for speech in quiet and noise for a subset of the processing options. This study compares the two processing options suggested to be used in noisy environments, Zoom and Beam, for various sound field conditions using a standardized speech in noise matrix test (Oldenburg sentences test). Nine German-speaking subjects who previously had been using the Freedom speech processor and subsequently were upgraded to the CP810 device participated in this series of additional evaluation tests. The speech reception threshold (SRT for 50% speech intelligibility in noise) was determined using sentences presented via loudspeaker at 65 dB SPL in front of the listener and noise presented either via the same loudspeaker (S0N0) or at 90 degrees at either the ear with the sound processor (S0NCI+) or the opposite unaided ear (S0NCI-). The fourth noise condition consisted of three uncorrelated noise sources placed at 90, 180 and 270 degrees. The noise level was adjusted through an adaptive procedure to yield a signal to noise ratio where 50% of the words in the sentences were correctly understood. In spatially separated speech and noise conditions both Zoom and Beam could improve the SRT significantly. For single noise sources, either ipsilateral or contralateral to the cochlear implant sound processor, average improvements with Beam of 12.9 and 7.9 dB in SRT were found. The average SRT of -8 dB for Beam in the diffuse noise condition (uncorrelated noise from both sides and

  11. Associative Memory design for the Fast TracK processor (FTK) at Atlas

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Piendibene, M; Sacco, I; Sartori, L; Tripiccione, R

    2010-01-01

    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF using a standard-cell VLSI design methodology. We propose now a new design (90 nm technology) where we introduce a full custom standard cell. This is a customized design that allows to maximize the pattern density and to minimize the power consumption. We discuss also possible future extensions based on 3-D technology. This processor has a flexible and easily configurable structure that makes it suitabl...

  12. Exergy analysis of an integrated fuel processor and fuel cell (FP-FC) system

    Energy Technology Data Exchange (ETDEWEB)

    Delsman, E.R. [Department of Chemical Engineering and Chemistry, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven (Netherlands); Uju, C.U. [Department of Chemical Engineering and Chemistry, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven (Netherlands); Croon, M.H.J.M. de [Department of Chemical Engineering and Chemistry, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven (Netherlands); Schouten, J.C. [Department of Chemical Engineering and Chemistry, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven (Netherlands); Ptasinski, K.J. [Department of Chemical Engineering and Chemistry, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven (Netherlands)]. E-mail: k.j.ptasinski@tue.nl

    2006-12-15

    Fuel cells have great application potential as stationary power plants, as power sources in transportation, and as portable power generators for electronic devices. Most fuel cells currently being developed for use in vehicles and as portable power generators require hydrogen as a fuel. Chemical storage of hydrogen in liquid fuels is considered to be one of the most advantageous options for supplying hydrogen to the cell. In this case a fuel processor is needed to convert the liquid fuel into a hydrogen-rich stream. This paper presents a second-law analysis of an integrated fuel processor and fuel cell system. The following primary fuels are considered: methanol, ethanol, octane, ammonia, and methane. The maximum amount of electrical work and corresponding heat effects produced from these fuels are evaluated. An exergy analysis is performed for a methanol processor integrated with a proton exchange membrane fuel cell, for use as a portable power generator. The integrated FP-FC system, which can produce 100 W of electricity, is simulated with a computer model using the flow-sheeting program Aspen Plus. The influence of various operating conditions on the system efficiency is investigated, such as the methanol concentration in the feed, the temperature in the reformer and in the fuel cell, as well as the fuel cell efficiency. Finally, it is shown that the calculated overall exergetic efficiency of the FP-FC system is higher than that of typical combustion engines and rechargeable batteries.

  13. Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors

    Directory of Open Access Journals (Sweden)

    Qadri MuhammadYasir

    2009-01-01

    Full Text Available Abstract Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathematical models have been proposed in the past. Most of these models are complex enough to be adapted for modern applications like run-time cache reconfiguration. This paper improves and validates previously proposed energy and throughput models for a data cache, which could be used for overhead analysis for various cache types with relatively small amount of inputs. These models analyze the energy and throughput of a data cache on an application basis, thus providing the hardware and software designer with the feedback vital to tune the cache or application for a given energy budget. The models are suitable for use at design time in the cache optimization process for embedded processors considering time and energy overhead or could be employed at runtime for reconfigurable architectures.

  14. Data Cache-Energy and Throughput Models: Design Exploration for Embedded Processors

    Directory of Open Access Journals (Sweden)

    Muhammad Yasir Qadri

    2009-01-01

    Full Text Available Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathematical models have been proposed in the past. Most of these models are complex enough to be adapted for modern applications like run-time cache reconfiguration. This paper improves and validates previously proposed energy and throughput models for a data cache, which could be used for overhead analysis for various cache types with relatively small amount of inputs. These models analyze the energy and throughput of a data cache on an application basis, thus providing the hardware and software designer with the feedback vital to tune the cache or application for a given energy budget. The models are suitable for use at design time in the cache optimization process for embedded processors considering time and energy overhead or could be employed at runtime for reconfigurable architectures.

  15. 78 FR 40434 - Proposed Information Collection; Comment Request; Survey of Fish Processors and Disruptions...

    Science.gov (United States)

    2013-07-05

    ... Fish Processors and Disruptions Caused by Hurricane Sandy AGENCY: National Oceanic and Atmospheric... seeks to collect data on distribution networks and business practices from fish processors that process...

  16. 75 FR 20811 - Proposed Information Collection; Comment Request; Produce Processor Profiles of Fish Processing...

    Science.gov (United States)

    2010-04-21

    ... Processor Profiles of Fish Processing Plants in Alaska AGENCY: National Oceanic and Atmospheric... which have an onshore fish processing facility. ] This project would produce ``processor profiles...

  17. Reducing the impact of wind noise on cochlear implant processors with two microphones.

    Science.gov (United States)

    Kokkinakis, Kostas; Cox, Casey

    2014-05-01

    Behind-the-ear (BTE) processors of cochlear implant (CI) devices offer little to almost no protection from wind noise in most incidence angles. To assess speech intelligibility, eight CI recipients were tested in 3 and 9 m/s wind. Results indicated that speech intelligibility decreased substantially when the wind velocity, and in turn the wind sound pressure level, increased. A two-microphone wind noise suppression strategy was developed. Scores obtained with this strategy indicated substantial gains in speech intelligibility over other conventional noise reduction strategies tested.

  18. Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions

    Directory of Open Access Journals (Sweden)

    Hoare Raymond R

    2006-01-01

    Full Text Available This paper presents an architecture that combines VLIW (very long instruction word processing with the capability to introduce application-specific customized instructions and highly parallel combinational hardware functions for the acceleration of signal processing applications. To support this architecture, a compilation and design automation flow is described for algorithms written in C. The key contributions of this paper are as follows: (1 a 4-way VLIW processor implemented in an FPGA, (2 large speedups through hardware functions, (3 a hardware/software interface with zero overhead, (4 a design methodology for implementing signal processing applications on this architecture, (5 tractable design automation techniques for extracting and synthesizing hardware functions. Several design tradeoffs for the architecture were examined including the number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing blocks that execute multiply-accumulate operations. Using the MediaBench benchmark suite, we tested our methodology and architecture to accelerate software. Our combined VLIW processor with hardware functions was compared to that of software executing on a RISC processor, specifically the soft core embedded NIOS II processor. For software kernels converted into hardware functions, we show a hardware performance multiplier of up to times that of software with an average times faster. For the entire application in which only a portion of the software is converted to hardware, the performance improvement is as much as 30X times faster than the nonaccelerated application, with a 12X improvement on average.

  19. Load power device, system and method of load control and management employing load identification

    Energy Technology Data Exchange (ETDEWEB)

    Yang, Yi; Luebke, Charles John; Schoepf, Thomas J.

    2018-01-09

    A load power device includes a power input, at least one power output for at least one load, a plurality of sensors structured to sense voltage and current at the at least one power output, and a processor. The processor provides: (a) load identification based upon the sensed voltage and current, and (b) load control and management based upon the load identification.

  20. Ethernet-Enabled Power and Communication Module for Embedded Processors

    Science.gov (United States)

    Perotti, Jose; Oostdyk, Rebecca

    2010-01-01

    The power and communications module is a printed circuit board (PCB) that has the capability of providing power to an embedded processor and converting Ethernet packets into serial data to transfer to the processor. The purpose of the new design is to address the shortcomings of previous designs, including limited bandwidth and program memory, lack of control over packet processing, and lack of support for timing synchronization. The new design of the module creates a robust serial-to-Ethernet conversion that is powered using the existing Ethernet cable. This innovation has a small form factor that allows it to power processors and transducers with minimal space requirements.

  1. Median and Morphological Specialized Processors for a Real-Time Image Data Processing

    Directory of Open Access Journals (Sweden)

    Wiatr Kazimierz

    2002-01-01

    Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

  2. Silicon Processors Using Organically Reconfigurable Techniques (SPORT)

    Science.gov (United States)

    2014-05-19

    of devices including modulators[4], ring resonators [5], etc. which have broad application in telecommunications and imaging. Despite these promising...The device is depicted in Figure 25. A CPW electrode on top of a Liquid Crystalline Polymer (LCP) substrate will be contacted with a commercially...available SMA to CPW converter. The signal conductor of the CPW can be wirebonded to a microstrip transmission line which is patterned on top of an

  3. Preventing Precipitation in the ISS Urine Processor

    Science.gov (United States)

    Muirhead, Dean; Carter, Layne; Williamson, Jill; Chambers, Antja

    2017-01-01

    The ISS Urine Processor Assembly (UPA) was initially designed to achieve 85% recovery of water from pretreated urine on ISS. Pretreated urine is comprised of crew urine treated with flush water, an oxidant (chromium trioxide), and an inorganic acid (sulfuric acid) to control microbial growth and inhibit precipitation. Unfortunately, initial operation of the UPA on ISS resulted in the precipitation of calcium sulfate at 85% recovery. This occurred because the calcium concentration in the crew urine was elevated in microgravity due to bone loss. The higher calcium concentration precipitated with sulfate from the pretreatment acid, resulting in a failure of the UPA due to the accumulation of solids in the Distillation Assembly. Since this failure, the UPA has been limited to a reduced recovery of water from urine to prevent calcium sulfate from reaching the solubility limit. NASA personnel have worked to identify a solution that would allow the UPA to return to a nominal recovery rate of 85%. This effort has culminated with the development of a pretreatment based on phosphoric acid instead of sulfuric acid. By eliminating the sulfate associated with the pretreatment, the brine can be concentrated to a much higher concentration before calcium sulfate reach the solubility limit. This paper summarizes the development of this pretreatment and the testing performed to verify its implementation on ISS.

  4. Scientific Computing Kernels on the Cell Processor

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Samuel W.; Shalf, John; Oliker, Leonid; Kamil, Shoaib; Husbands, Parry; Yelick, Katherine

    2007-04-04

    The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on a 3.2GHz Cell blade. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

  5. Project Report: Automatic Sequence Processor Software Analysis

    Science.gov (United States)

    Benjamin, Brandon

    2011-01-01

    The Mission Planning and Sequencing (MPS) element of Multi-Mission Ground System and Services (MGSS) provides space missions with multi-purpose software to plan spacecraft activities, sequence spacecraft commands, and then integrate these products and execute them on spacecraft. Jet Propulsion Laboratory (JPL) is currently is flying many missions. The processes for building, integrating, and testing the multi-mission uplink software need to be improved to meet the needs of the missions and the operations teams that command the spacecraft. The Multi-Mission Sequencing Team is responsible for collecting and processing the observations, experiments and engineering activities that are to be performed on a selected spacecraft. The collection of these activities is called a sequence and ultimately a sequence becomes a sequence of spacecraft commands. The operations teams check the sequence to make sure that no constraints are violated. The workflow process involves sending a program start command, which activates the Automatic Sequence Processor (ASP). The ASP is currently a file-based system that is comprised of scripts written in perl, c-shell and awk. Once this start process is complete, the system checks for errors and aborts if there are any; otherwise the system converts the commands to binary, and then sends the resultant information to be radiated to the spacecraft.

  6. Multipurpose silicon photonics signal processor core.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

    2017-09-21

    Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

  7. Element Load Data Processor (ELDAP) Users Manual

    Science.gov (United States)

    Ramsey, John K., Jr.; Ramsey, John K., Sr.

    2015-01-01

    Often, the shear and tensile forces and moments are extracted from finite element analyses to be used in off-line calculations for evaluating the integrity of structural connections involving bolts, rivets, and welds. Usually the maximum forces and moments are desired for use in the calculations. In situations where there are numerous structural connections of interest for numerous load cases, the effort in finding the true maximum force and/or moment combinations among all fasteners and welds and load cases becomes difficult. The Element Load Data Processor (ELDAP) software described herein makes this effort manageable. This software eliminates the possibility of overlooking the worst-case forces and moments that could result in erroneous positive margins of safety and/or selecting inconsistent combinations of forces and moments resulting in false negative margins of safety. In addition to forces and moments, any scalar quantity output in a PATRAN report file may be evaluated with this software. This software was originally written to fill an urgent need during the structural analysis of the Ares I-X Interstage segment. As such, this software was coded in a straightforward manner with no effort made to optimize or minimize code or to develop a graphical user interface.

  8. A CNN-Specific Integrated Processor

    Science.gov (United States)

    Malki, Suleyman; Spaanenburg, Lambert

    2009-12-01

    Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  9. A CNN-Specific Integrated Processor

    Directory of Open Access Journals (Sweden)

    Suleyman Malki

    2009-01-01

    Full Text Available Integrated Processors (IP are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  10. Fast parallel computation of polynomials using few processors

    DEFF Research Database (Denmark)

    Valiant, Leslie; Skyum, Sven

    1981-01-01

    It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors....

  11. Fault Mitigation Schemes for Future Spaceflight Multicore Processors

    Science.gov (United States)

    Some, Rafi; Gostelow, Kim P.; Lai, John; Reder, Leonard; Alexander, James; Clement, Brad

    2012-01-01

    The goal of this work is to achieve fail-operational and graceful-degradation behavior in realistic flight mission scenarios, of multicore processors such as Mars Entry-Descent-Landing (EDL) and Primitive Body proximity operations.

  12. A Shared Memory Module for Asynchronous Arrays of Processors

    Directory of Open Access Journals (Sweden)

    Meeuwsen MichaelJ

    2007-01-01

    Full Text Available A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μm CMOS.

  13. Reconfigurable VLIW Processor for Software Defined Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the...

  14. 2009 Survey of Gulf of Mexico Dockside Seafood Processors

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This survey gathered and analyze economic data from seafood processors throughout the states in the Gulf region. The survey sought to collect financial variables...

  15. Assembly processor program converts symbolic programming language to machine language

    Science.gov (United States)

    Pelto, E. V.

    1967-01-01

    Assembly processor program converts symbolic programming language to machine language. This program translates symbolic codes into computer understandable instructions, assigns locations in storage for successive instructions, and computer locations from symbolic addresses.

  16. Compiler for Fast, Accurate Mathematical Computing on Integer Processors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposers will develop a computer language compiler to enable inexpensive, low-power, integer-only processors to carry our mathematically-intensive comptutations...

  17. Multitask neurovision processor with extensive feedback and feedforward connections

    Science.gov (United States)

    Gupta, Madan M.; Knopf, George K.

    1991-11-01

    A multi-task neuro-vision parameter which performs a variety of information processing operations associated with the early stages of biological vision is presented. The network architecture of this neuro-vision processor, called the positive-negative (PN) neural processor, is loosely based on the neural activity fields exhibited by thalamic and cortical nervous tissue layers. The computational operation performed by the processor arises from the strength of the recurrent feedback among the numerous positive and negative neural computing units. By adjusting the feedback connections it is possible to generate diverse dynamic behavior that may be used for short-term visual memory (STVM), spatio-temporal filtering (STF), and pulse frequency modulation (PFM). The information attributes that are to be processes may be regulated by modifying the feedforward connections from the signal space to the neural processor.

  18. Ultrafast Power Processor for Smart Grid Power Module Development

    Energy Technology Data Exchange (ETDEWEB)

    MAITRA, ARINDAM [EPRI; LITWIN, RAY [EPRI; lai, Jason [Enertronics; Syracuse, David [Silicon Power

    2012-12-30

    This project’s goal was to increase the switching speed and decrease the losses of the power semiconductor devices and power switch modules necessary to enable Smart Grid energy flow and control equipment such as the Ultra-Fast Power Processor. The primary focus of this project involves exploiting the new silicon-based Super-GTO (SGTO) technology and build on prototype modules already being developed. The prototype super gate-turn-off thyristor (SGTO) has been tested fully under continuously conducting and double-pulse hard-switching conditions for conduction and switching characteristics evaluation. The conduction voltage drop measurement results indicate that SGTO has excellent conduction characteristics despite inconsistency among some prototype devices. Tests were conducted with two conditions: (1) fixed gate voltage and varying anode current condition, and (2) fixed anode current and varying gate voltage condition. The conduction voltage drop is relatively a constant under different gate voltage condition. In terms of voltage drop as a function of the load current, there is a fixed voltage drop about 0.5V under zero current condition, and then the voltage drop is linearly increased with the current. For a 5-kV voltage blocking device that may operate under 2.5-kV condition, the projected voltage drop is less than 2.5 V under 50-A condition, or 0.1%. If the device is adopted in a converter operating under soft-switching condition, then the converter can achieve an ultrahigh efficiency, typically above 99%. The two-pulse switching test results indicate that SGTO switching speed is very fast. The switching loss is relatively low as compared to that of the insulated-gate-bipolar-transistors (IGBTs). A special phenomenon needs to be noted is such a fast switching speed for the high-voltage switching tends to create an unexpected Cdv/dt current, which reduces the turn-on loss because the dv/dt is negative and increases the turn-off loss because the dv/dt is

  19. On the Distribution of Control in Asynchronous Processor Architectures

    OpenAIRE

    Rebello, Vinod

    1997-01-01

    The effective performance of computer systems is to a large measure determined by the synergy between the processor architecture, the instruction set and the compiler. In the past, the sequencing of information within processor architectures has normally been synchronous: controlled centrally by a clock. However, this global signal could possibly limit the future gains in performance that can potentially be achieved through improvements in implementation technology. T...

  20. Industry Analysis: Apple Processors in the Northeastern U.S.

    OpenAIRE

    Rowles, Kristin L.

    2001-01-01

    Apple processors are an important link in the marketing chain from apple growers to consumers, and their perspective is critical in understanding the industry?s situation and projecting the industry?s future. This paper reports the results of a survey of Northeastern U.S. apple processors. The survey was conducted to provide a snapshot of current strategic issues in the industry, to assess the industry?s strengths and weaknesses, to identify opportunities and threats, to forecast future trend...

  1. Review of trigger and on-line processors at SLAC

    Energy Technology Data Exchange (ETDEWEB)

    Lankford, A.J.

    1984-07-01

    The role of trigger and on-line processors in reducing data rates to manageable proportions in e/sup +/e/sup -/ physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e/sup +/e/sup -/ annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e/sup +/e/sup -/ context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table.

  2. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...

  3. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...

  4. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A

    2014-01-01

    The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...

  5. 7 CFR 160.50 - Reports to be made by accredited processors.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 3 2010-01-01 2010-01-01 false Reports to be made by accredited processors. 160.50... made by accredited processors. Each accredited processor shall furnish the Administrator such reports... processor to keep such records as may be necessary for him to submit correct reports, or failure by the...

  6. An efficient processor allocation strategy that maintains a high degree of contiguity among processors in 2D mesh connected multicomputers

    OpenAIRE

    Bani-Mohammad, S.; Ould-Khaoua, M.; Abaneh, I.; Mackenzie, L.M.

    2007-01-01

    Two strategies are used for the allocation of jobs to processors connected by mesh topologies: contiguous allocation and non-contiguous allocation. In non-contiguous allocation, a job request can be split into smaller parts that are allocated to non-adjacent free sub-meshes rather than always waiting until a single sub-mesh of the requested size and shape is available. Lifting the contiguity condition is expected to reduce processor fragmentation and increase system utilization. However, the ...

  7. THOR Fields and Wave Processor - FWP

    Science.gov (United States)

    Soucek, Jan; Rothkaehl, Hanna; Ahlen, Lennart; Balikhin, Michael; Carr, Christopher; Dekkali, Moustapha; Khotyaintsev, Yuri; Lan, Radek; Magnes, Werner; Morawski, Marek; Nakamura, Rumi; Uhlir, Ludek; Yearby, Keith; Winkler, Marek; Zaslavsky, Arnaud

    2017-04-01

    If selected, Turbulence Heating ObserveR (THOR) will become the first spacecraft mission dedicated to the study of plasma turbulence. The Fields and Waves Processor (FWP) is an integrated electronics unit for all electromagnetic field measurements performed by THOR. FWP will interface with all THOR fields sensors: electric field antennas of the EFI instrument, the MAG fluxgate magnetometer, and search-coil magnetometer (SCM), and perform signal digitization and on-board data processing. FWP box will house multiple data acquisition sub-units and signal analyzers all sharing a common power supply and data processing unit and thus a single data and power interface to the spacecraft. Integrating all the electromagnetic field measurements in a single unit will improve the consistency of field measurement and accuracy of time synchronization. The scientific value of highly sensitive electric and magnetic field measurements in space has been demonstrated by Cluster (among other spacecraft) and THOR instrumentation will further improve on this heritage. Large dynamic range of the instruments will be complemented by a thorough electromagnetic cleanliness program, which will prevent perturbation of field measurements by interference from payload and platform subsystems. Taking advantage of the capabilities of modern electronics and the large telemetry bandwidth of THOR, FWP will provide multi-component electromagnetic field waveforms and spectral data products at a high time resolution. Fully synchronized sampling of many signals will allow to resolve wave phase information and estimate wavelength via interferometric correlations between EFI probes. FWP will also implement a plasma resonance sounder and a digital plasma quasi-thermal noise analyzer designed to provide high cadence measurements of plasma density and temperature complementary to data from particle instruments. FWP will rapidly transmit information about magnetic field vector and spacecraft potential to the

  8. Optical Symbolic Processor for Expert System Execution

    Science.gov (United States)

    1989-12-31

    primitive funcions are contained in leaf nodes. A leaf node is a node whose LC contains a value and whose RC is empty. The & node described earlier is used...device was designed using a semi- vectorial finite-difference analysis technique, enabling the range of experimental parameters to be investigated to be...scheme for evaluating propagation constants and mode profiles of optical waveguides. It is semi- vectorial in that solutions to the 1 eigenvalue equation

  9. Programmable Quantum Photonic Processor Using Silicon Photonics

    Science.gov (United States)

    2017-04-01

    al, ’’ Semiconductor Quantum Technologies for Information Processing and Sensing,,’’ Canadian Institute for Advanced Research - Quantum Information... Graphene Optoelectronic Devices for Optical Interconnects,’’ , CLEO/Europe-EQEC 2015, Munich, Germany (6/21/2015) ● Jacob Mower, Nicholas C. Harris...Processing Using Active Silicon Photonic Integrated Circuits,’’ CLEO/Europe-EQEC 2015, Munich, Germany (6/22/2015) ● D. Englund et al, ’’ Semiconductor

  10. [Improving speech comprehension using a new cochlear implant speech processor].

    Science.gov (United States)

    Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

    2009-06-01

    The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg

  11. Phase coherence adaptive processor for automatic signal detection and identification

    Science.gov (United States)

    Wagstaff, Ronald A.

    2006-05-01

    A continuously adapting acoustic signal processor with an automatic detection/decision aid is presented. Its purpose is to preserve the signals of tactical interest, and filter out other signals and noise. It utilizes single sensor or beamformed spectral data and transforms the signal and noise phase angles into "aligned phase angles" (APA). The APA increase the phase temporal coherence of signals and leave the noise incoherent. Coherence thresholds are set, which are representative of the type of source "threat vehicle" and the geographic area or volume in which it is operating. These thresholds separate signals, based on the "quality" of their APA coherence. An example is presented in which signals from a submerged source in the ocean are preserved, while clutter signals from ships and noise are entirely eliminated. Furthermore, the "signals of interest" were identified by the processor's automatic detection aid. Similar performance is expected for air and ground vehicles. The processor's equations are formulated in such a manner that they can be tuned to eliminate noise and exploit signal, based on the "quality" of their APA temporal coherence. The mathematical formulation for this processor is presented, including the method by which the processor continuously self-adapts. Results show nearly complete elimination of noise, with only the selected category of signals remaining, and accompanying enhancements in spectral and spatial resolution. In most cases, the concept of signal-to-noise ratio looses significance, and "adaptive automated /decision aid" is more relevant.

  12. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  13. Architecture of a complex arithmetic processor for communication signal processing

    Science.gov (United States)

    Gilfeather, Susan L.; Gehman, John B., Jr.; Harrison, Calvin

    1994-10-01

    The Complex Arithmetic Processor (CAP) is a high performance, single chip Digital Signal Processor optimized for communication signal processing operations. The CAP VLSI provides the communication system building block necessary to meet the increased signal processing requirements of complex modulation types, voice and image compression while maintaining the requirement for small, low power implementations. The chip is intended for high speed, low power digital communication system applications such as hand held spread spectrum communications systems. The CAP architecture has been developed specifically for the complex arithmetic functions required in communication signal processing. The CAP is a software programmable, highly integrated parallel array of processors containing the arithmetic resources, memories, address generation, bit manipulation and logic functions necessary to support the sophisticated processing required in advanced communication equipment. The CAP executes a 1024 point complex Fast Fourier Transform in 131 microseconds.

  14. The ATLAS Level-1 Central Trigger Processor (CTP)

    CERN Document Server

    Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

    2005-01-01

    The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.

  15. Characterization of the Jason Multiagent Platform on Multicore Processors

    Directory of Open Access Journals (Sweden)

    Pascual Pérez-Carro

    2014-01-01

    Full Text Available Multiagent platforms need to be evaluated focusing on the underlying computer architecture in order to allow developers to exploit the parallelism available in multicore processors. This paper presents the characterization of Jason, a well-known Java-based multiagent platform, when executed on distributed shared memory architectures. Since this kind of architecture is already present in current multicore processors, this should be the first step for the characterization of this platform on distributed systems. To this end, we propose the execution of a set of benchmarks recently proposed for evaluating multiagent platforms. The results obtained show that Jason can be used to program CPU-intensive multiagent applications without loosing the Java scalability over multicore processors. Though, Jason's performance for communication-intensive applications depends on the traffic pattern generated by the agents, the layout of the cores and the selected execution mode (i.e. synchronous or asynchronous.

  16. A Bayesian sequential processor approach to spectroscopic portal system decisions

    Energy Technology Data Exchange (ETDEWEB)

    Sale, K; Candy, J; Breitfeller, E; Guidry, B; Manatt, D; Gosnell, T; Chambers, D

    2007-07-31

    The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waiting for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.

  17. Adaptive detection and enhancement pre-processor for tracking

    Science.gov (United States)

    Scott, Douglas; Mise, Olegs

    2009-05-01

    An adaptive image pre-processor has been developed as a high-performance front-end for a next-generation multi-target tracking (MTT) system. The tracking system is designed to track targets across potentially multiple and distributed electro-optic video sensors. Typically a pre-processor operates to enhance targets and assist the tracking. However, they frequently rely on expert knowledge to configure the algorithm for the particular application and hence do not cope adequately given unexpected variations or generic application. The pre-processor developed for our MTT system achieves a significantly improved and robust performance by using an adaptive approach based on wavelet decomposition and a "supporting-classifier" method. It is capable of detecting and dynamically maintaining a target-definition optimized for tracking, whilst maximally suppressing non-related clutter. This paper presents an overview of the architecture and demonstrates its performance on real video scenes.

  18. Safety-Critical Java on a Time-predictable Processor

    DEFF Research Database (Denmark)

    Korsholm, Stephan Erbs; Schoeberl, Martin; Puffitsch, Wolfgang

    2015-01-01

    ; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor.......For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor...

  19. Safety-critical Java on a time-predictable processor

    DEFF Research Database (Denmark)

    Korsholm, Stephan E.; Schoeberl, Martin; Puffitsch, Wolfgang

    2015-01-01

    ; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor.......For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor...

  20. Token-Aware Completion Functions for Elastic Processor Verification

    Directory of Open Access Journals (Sweden)

    Sudarshan K. Srinivasan

    2009-01-01

    Full Text Available We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which—in the context of this problem—are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.

  1. Modal Processor Effects Inspired by Hammond Tonewheel Organs

    Directory of Open Access Journals (Sweden)

    Kurt James Werner

    2016-06-01

    Full Text Available In this design study, we introduce a novel class of digital audio effects that extend the recently introduced modal processor approach to artificial reverberation and effects processing. These pitch and distortion processing effects mimic the design and sonics of a classic additive-synthesis-based electromechanical musical instrument, the Hammond tonewheel organ. As a reverb effect, the modal processor simulates a room response as the sum of resonant filter responses. This architecture provides precise, interactive control over the frequency, damping, and complex amplitude of each mode. Into this framework, we introduce two types of processing effects: pitch effects inspired by the Hammond organ’s equal tempered “tonewheels”, “drawbar” tone controls, vibrato/chorus circuit, and distortion effects inspired by the pseudo-sinusoidal shape of its tonewheels and electromagnetic pickup distortion. The result is an effects processor that imprints the Hammond organ’s sonics onto any audio input.

  2. Comparison of speech perception performance between Sprint/Esprit 3G and Freedom processors in children implanted with nucleus cochlear implants.

    Science.gov (United States)

    Santarelli, Rosamaria; Magnavita, Vincenzo; De Filippi, Roberta; Ventura, Laura; Genovese, Elisabetta; Arslan, Edoardo

    2009-04-01

    To compare speech perception performance in children fitted with previous generation Nucleus sound processor, Sprint or Esprit 3G, and the Freedom, the most recently released system from the Cochlear Corporation that features a larger input dynamic range. Prospective intrasubject comparative study. University Medical Center. Seventeen prelingually deafened children who had received the Nucleus 24 cochlear implant and used the Sprint or Esprit 3G sound processor. Cochlear implantation with Cochlear device. Speech perception was evaluated at baseline (Sprint, n = 11; Esprit 3G, n = 6) and after 1 month's experience with the Freedom sound processor. Identification and recognition of disyllabic words and identification of vowels were performed via recorded voice in quiet (70 dB [A]), in the presence of background noise at various levels of signal-to-noise ratio (+10, +5, 0, -5) and at a soft presentation level (60 dB [A]). Consonant identification and recognition of disyllabic words, trisyllabic words, and sentences were evaluated in live voice. Frequency discrimination was measured in a subset of subjects (n = 5) by using an adaptive, 3-interval, 3-alternative, forced-choice procedure. Identification of disyllabic words administered at a soft presentation level showed a significant increase when switching to the Freedom compared with the previously worn processor in children using the Sprint or Esprit 3G. Identification and recognition of disyllabic words in the presence of background noise as well as consonant identification and sentence recognition increased significantly for the Freedom compared with the previously worn device only in children fitted with the Sprint. Frequency discrimination was significantly better when switching to the Freedom compared with the previously worn processor. Serial comparisons revealed that that speech perception performance evaluated in children aged 5 to 15 years was superior with the Freedom than previous generations of Nucleus

  3. Benchmarking NWP Kernels on Multi- and Many-core Processors

    Science.gov (United States)

    Michalakes, J.; Vachharajani, M.

    2008-12-01

    Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

  4. Satellite on-board real-time SAR processor prototype

    Science.gov (United States)

    Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

    2017-11-01

    A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and

  5. CERN Technical Training: Digital Signal Processors

    CERN Multimedia

    HR Department

    2009-01-01

    A new training is going to be held at CERN on the ADSP SHARC Family. The “System Development and Programming with the Analog Devices' SHARC Family” course is a 3.5-day hands-on training on Analog Devices SHARC DSPs, focusing on the latest ‘368/9 and 37x families. General DSP architecture, peripherals available, booting up process and DSP code development will be covered. Hardware tools, debugging and hardware design guidelines will be introduced as well. The course id designed for System Designers needing to make informed decisions on design tradeoffs, Hardware Designers needing to develop external interfaces, and Code Developers needing to know how to get the highest performance from their algorithms. The course will take place, in English, from 31 March to 4 April in the CERN Technical Training Center. Few places are still available. Registrations are opened on the Technical Training page. More information on our catalogue: http://cta.cern.ch/cta2/f?p=110:9 or conta...

  6. MPC Related Computational Capabilities of ARMv7A Processors

    DEFF Research Database (Denmark)

    Frison, Gianluca; Jørgensen, John Bagterp

    2015-01-01

    are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...... and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In particular...

  7. Reconfigurable lattice mesh designs for programmable photonic processors.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José; Soref, Richard A

    2016-05-30

    We propose and analyse two novel mesh design geometries for the implementation of tunable optical cores in programmable photonic processors. These geometries are the hexagonal and the triangular lattice. They are compared here to a previously proposed square mesh topology in terms of a series of figures of merit that account for metrics that are relevant to on-chip integration of the mesh. We find that that the hexagonal mesh is the most suitable option of the three considered for the implementation of the reconfigurable optical core in the programmable processor.

  8. Signal Processing with Teams of Embedded Workhorse Processors

    Directory of Open Access Journals (Sweden)

    Hobson RF

    2006-01-01

    Full Text Available Advanced signal processing for voice and data in wired or wireless environments can require massive computational power. Due to the complexity and continuing evolution of such systems, it is desirable to maintain as much software controllability in the field as possible. Time to market can also be improved by reducing the amount of hardware design. This paper describes an architecture based on clusters of embedded "workhorse" processors which can be dynamically harnessed in real time to support a wide range of computational tasks. Low-power processors and memory are important ingredients in such a highly parallel environment.

  9. The associative memory system for the FTK processor at ATLAS

    CERN Document Server

    Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M

    2014-01-01

    In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.

  10. Global synchronization of parallel processors using clock pulse width modulation

    Science.gov (United States)

    Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

    2013-04-02

    A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

  11. Matrix preconditioning: a robust operation for optical linear algebra processors.

    Science.gov (United States)

    Ghosh, A; Paparao, P

    1987-07-15

    Analog electrooptical processors are best suited for applications demanding high computational throughput with tolerance for inaccuracies. Matrix preconditioning is one such application. Matrix preconditioning is a preprocessing step for reducing the condition number of a matrix and is used extensively with gradient algorithms for increasing the rate of convergence and improving the accuracy of the solution. In this paper, we describe a simple parallel algorithm for matrix preconditioning, which can be implemented efficiently on a pipelined optical linear algebra processor. From the results of our numerical experiments we show that the efficacy of the preconditioning algorithm is affected very little by the errors of the optical system.

  12. Advanced Avionics and Processor Systems for Space and Lunar Exploration

    Science.gov (United States)

    Keys, Andrew S.; Adams, James H.; Ray, Robert E.; Johnson, Michael A.; Cressler, John D.

    2009-01-01

    NASA's newly named Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to mature and develop the avionic and processor technologies required to fulfill NASA's goals for future space and lunar exploration. Over the past year, multiple advancements have been made within each of the individual AAPS technology development tasks that will facilitate the success of the Constellation program elements. This paper provides a brief review of the project's recent technology advancements, discusses their application to Constellation projects, and addresses the project's plans for the coming year.

  13. Method for fast start of a fuel processor

    Science.gov (United States)

    Ahluwalia, Rajesh K [Burr Ridge, IL; Ahmed, Shabbir [Naperville, IL; Lee, Sheldon H. D. [Willowbrook, IL

    2008-01-29

    An improved fuel processor for fuel cells is provided whereby the startup time of the processor is less than sixty seconds and can be as low as 30 seconds, if not less. A rapid startup time is achieved by either igniting or allowing a small mixture of air and fuel to react over and warm up the catalyst of an autothermal reformer (ATR). The ATR then produces combustible gases to be subsequently oxidized on and simultaneously warm up water-gas shift zone catalysts. After normal operating temperature has been achieved, the proportion of air included with the fuel is greatly diminished.

  14. Parallel Processor for 3D Recovery from Optical Flow

    Directory of Open Access Journals (Sweden)

    Jose Hugo Barron-Zambrano

    2009-01-01

    Full Text Available 3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.

  15. A fast processor for di-lepton triggers

    CERN Document Server

    Kostarakis, P; Barsotti, E; Conetti, S; Cox, B; Enagonio, J; Haldeman, M; Haynes, W; Katsanevas, S; Kerns, C; Lebrun, P; Smith, H; Soszyniski, T; Stoffel, J; Treptow, K; Turkot, F; Wagner, R

    1981-01-01

    As a new application of the Fermilab ECL-CAMAC logic modules a fast trigger processor was developed for Fermilab experiment E-537, aiming to measure the higher mass di-muon production by antiprotons. The processor matches the hit information received from drift chambers and scintillation counters, to find candidate muon tracks and determine their directions and momenta. The tracks are then paired to compute an invariant mass: when the computed mass falls within the desired range, the event is accepted. The process is accomplished in times of 5 to 10 microseconds, while achieving a trigger rate reduction of up to a factor of ten. (5 refs).

  16. The Danish real-time SAR processor: first results

    DEFF Research Database (Denmark)

    Dall, Jørgen; Jørgensen, Jørn Hjelm; Netterstrøm, Anders

    1993-01-01

    A real-time processor (RTP) for the Danish airborne Synthetic Aperture Radar (SAR) has been designed and constructed at the Electromagnetics Institute. The implementation was completed in mid 1992, and since then the RTP has been operated successfully on several test and demonstration flights....... The processor is capable of focusing the entire swath of the raw SAR data into full resolution, and depending on the choice made by the on-board operator, either a high resolution one-look zoom image or a spatially multilooked overview image is displayed. After a brief design review, the paper addresses various...

  17. Post-silicon and runtime verification for modern processors

    CERN Document Server

    Wagner, Ilya

    2010-01-01

    The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solution

  18. Formal characterizations of FA-based string processors

    CSIR Research Space (South Africa)

    Ngassam, EK

    2010-08-01

    Full Text Available -based String Processors Ernest Ketcha Ngassam1,2,?, Bruce W. Watson3, and Derrick G. Kourie3 1SAP Meraka UTD, Pretoria, South Africa 2School of Computing University of South Africa Pretoria 0001 ernest.ngassam@sap.com 3Department of Computer Science... ongoing and results presenting their performance can be found in [1–3, 5]. 2 Formal Characterizations of FA-based String Processors References 1. E. N. Ketcha, D. G. Kourie, and B. W. Watson: Reordering finite automatata states for fast string...

  19. Validating a Timing Simulator for the NGMP Multicore Processor

    Science.gov (United States)

    Jalle, Javier; Abella, Jaume; Fossati, Luca; Zulianello, Marco; Cazorla, Francisco J.

    2016-08-01

    Timing simulation is a key element in multicore systems design. It enables a fast and cost effective design space exploration, allowing to simulate new architectural improvements without requiring RTL abstraction levels. Timing simulation also allows software developers to perform early testing of the timing behavior of their software without the need of buying the actual physical board, which can be very expensive when the board uses non-COTS technology. In this paper we present the validation of a timing simulator for the NGMP multicore processor, which is a 4 core processor being developed to become the reference platform for future missions of the European Space Agency.

  20. Molecular processors: from qubits to fuzzy logic.

    Science.gov (United States)

    Gentili, Pier Luigi

    2011-03-14

    Single molecules or their assemblies are information processing devices. Herein it is demonstrated how it is possible to process different types of logic through molecules. As long as decoherent effects are maintained far away from a pure quantum mechanical system, quantum logic can be processed. If the collapse of superimposed or entangled wavefunctions is unavoidable, molecules can still be used to process either crisp (binary or multi-valued) or fuzzy logic. The way for implementing fuzzy inference engines is declared and it is supported by the examples of molecular fuzzy logic systems devised so far. Fuzzy logic is drawing attention in the field of artificial intelligence, because it models human reasoning quite well. This ability may be due to some structural analogies between a fuzzy logic system and the human nervous system. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  1. Environment quality monitoring using ARM processor

    Science.gov (United States)

    Vinaya, C. H.; Krishna Thanikanti, Vamsi; Ramasamy, Sudha

    2017-11-01

    This paper of air quality monitoring system describes a model of sensors network to continuously monitoring the environment with low cost developed model. At present time all over the world turned into a great revolution in industrial domain and on the other hand environment get polluting in a dangerous value. There are so many technologies present to reduce the polluting contents but still there is no completely reduction of that pollution. Even there are different methods to monitor the pollution content; these are much costly that not everyone can adapt those methods or devices. Now we are proposing a sensors connected network to monitor the environment continuously and displaying the pollutant gases percentage in air surroundings and can transmit the results to our mobiles by message. The advantage of this system is easy to design, establish at area to monitor, maintenance and most cost effective as well.

  2. Signal processors for position-sensitive detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hasegawa, Ken-ichi [Hosei Univ., Koganei, Tokyo (Japan). Coll. of Engineering

    1996-07-01

    Position-sensitive detectors (PSD) are widely used in following various fields: condensed matter studies, material engineering, medical radiology particle physics, astrophysics and industrial applications. X-ray diffraction analysis is one of the field where PSDs are the most important instruments. In this field, many types of PSAs are employed: position-sensitive proportional counters (PSPC), multi-wire proportional chambers (MWPC), imaging plates, image intensifiers combined CCD cameras and semiconductor array devices. Two readout systems used for PSDs, where one is a charge-division type with high stability and the other is an encoder with multiple delay, line readout circuits useful for fast counting, were reported in this paper. The multiple delay line encoding system can be applicable to high counting rate 1D and 2D gas proportional detectors. (G.K.)

  3. Associative Memory Design for the Fast TracKer Processor (FTK)at ATLAS

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Beretta, M; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Hoff, J; Liu, T; Liberali, V; Sacco, I; Schoening, A; Soltveit, H K; Stabile, A; Tripiccione, R

    2011-01-01

    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF [1] using a standard-cell VLSI design methodology. We propose a new design that introduces a full custom CAM cell and takes advantage of 65 nm technology. The customized design maximizes the pattern density, minimizes the power consumption and implements the functionalities needed for the planned Fast Tracker (FTK) [2], an ATLAS trigger upgrade project at LHC. We introduce a new variable resolution patt...

  4. DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor

    Science.gov (United States)

    Chuang, Chung-Lun; Shaffer, Scott; Smythe, Robert; Niamsuwan, Noppasin; Li, Samuel; Liao, Eric; Lim, Chester; Morfopolous, Arin; Veilleux, Louise

    2013-01-01

    The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.

  5. The Trigger Processor and Trigger Processor Algorithms for the ATLAS New Small Wheel Upgrade

    CERN Document Server

    Lazovich, Tomo; The ATLAS collaboration

    2015-01-01

    The ATLAS New Small Wheel (NSW) is an upgrade to the ATLAS muon endcap detectors that will be installed during the next long shutdown of the LHC. Comprising both MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), this system will drastically improve the performance of the muon system in a high cavern background environment. The NSW trigger, in particular, will significantly reduce the rate of fake triggers coming from track segments in the endcap not originating from the interaction point. We will present an overview of the trigger, the proposed sTGC and MM trigger algorithms, and the hardware implementation of the trigger. In particular, we will discuss both the heart of the trigger, an ATCA system with FPGA-based trigger processors (using the same hardware platform for both MM and sTGC triggers), as well as the full trigger electronics chain, including dedicated cards for transmission of data via GBT optical links. Finally, we will detail the challenges of ensuring that the trigger electronics can ...

  6. Evaluation of the Intel Nehalem-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

  7. Fast Parallel Computation of Polynomials Using Few Processors

    DEFF Research Database (Denmark)

    Valiant, Leslie G.; Skyum, Sven; Berkowitz, S.

    1983-01-01

    It is shown that any multivariate polynomial of degree $d$ that can be computed sequentially in $C$ steps can be computed in parallel in $O((\\log d)(\\log C + \\log d))$ steps using only $(Cd)^{O(1)} $ processors....

  8. Assessment of food safety practices among cassava processors in ...

    African Journals Online (AJOL)

    Food safety assessment is an effective means of discovering knowledge and data gaps that limit effective risk analysis and at the same time providing information to develop public policies on food safety management. The study assessed the cassava food safety practices among cassava processors in selected rural ...

  9. Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

    Science.gov (United States)

    Sharma, Anuj; Manolakos, Elias S

    2015-01-01

    Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub.

  10. Low-latency optoelectronic processor-memory interconnection demonstrator

    Science.gov (United States)

    Fancey, Stuart J.; Jahns, Juergen; Lukowicz, Paul; Grzyb, Janusz

    2001-12-01

    A principal performance limitation of current computers is memory access latency. The random access time of DRAM can be as low as 20 ns but the overhead imposed by communication latency can increase the retrieval time to 150 ns in single processor systems or 1 ms in large multiprocessor systems. Optically interconnected VLSI offers the possibility of reductions in the communication component of memory latency of an order of magnitude. The improvement arises from the potential of direct high bandwidth low-latency links between any one chip and each one of a set of others. This potential principally arises from the ease of an optical implementation of fan-out and fan-in operations, together with the intrinsically high bandwidth of optical links. We have designed a scaleable system of processor-memory interconnections to explore this technology. Optical fan-out and fan-in modules will link a single processor to a bank of memory chips. The approach allows for multiple processors to be connected to multiple memory banks in an analogous fashion. The demonstrator will use 1-D VCSEL and photodiode arrays to provide optical i/o for the CPU and memory chips. The optical fan-out, fan-in and image relay can be implemented using an integrated planar optical system.

  11. Experiences with Compiler Support for Processors with Exposed Pipelines

    DEFF Research Database (Denmark)

    Jensen, Nicklas Bo; Schleuniger, Pascal; Hindborg, Andreas Erik

    2015-01-01

    Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means...

  12. Interactive high-resolution isosurface ray casting on multicore processors.

    Science.gov (United States)

    Wang, Qin; JaJa, Joseph

    2008-01-01

    We present a new method for the interactive rendering of isosurfaces using ray casting on multi-core processors. This method consists of a combination of an object-order traversal that coarsely identifies possible candidate 3D data blocks for each small set of contiguous pixels, and an isosurface ray casting strategy tailored for the resulting limited-size lists of candidate 3D data blocks. While static screen partitioning is widely used in the literature, our scheme performs dynamic allocation of groups of ray casting tasks to ensure almost equal loads among the different threads running on multi-cores while maintaining spatial locality. We also make careful use of memory management environment commonly present in multi-core processors. We test our system on a two-processor Clovertown platform, each consisting of a Quad-Core 1.86-GHz Intel Xeon Processor, for a number of widely different benchmarks. The detailed experimental results show that our system is efficient and scalable, and achieves high cache performance and excellent load balancing, resulting in an overall performance that is superior to any of the previous algorithms. In fact, we achieve an interactive isosurface rendering on a 1024(2) screen for all the datasets tested up to the maximum size of the main memory of our platform.

  13. Random access quantum information processors using multimode circuit quantum electrodynamics.

    Science.gov (United States)

    Naik, R K; Leung, N; Chakram, S; Groszkowski, Peter; Lu, Y; Earnest, N; McKay, D C; Koch, Jens; Schuster, D I

    2017-12-04

    Qubit connectivity is an important property of a quantum processor, with an ideal processor having random access-the ability of arbitrary qubit pairs to interact directly. This a challenge with superconducting circuits, as state-of-the-art architectures rely on only nearest-neighbor coupling. Here, we implement a random access superconducting quantum information processor, demonstrating universal operations on a nine-qubit memory, with a Josephson junction transmon circuit serving as the central processor. The quantum memory uses the eigenmodes of a linear array of coupled superconducting resonators. We selectively stimulate vacuum Rabi oscillations between the transmon and individual eigenmodes through parametric flux modulation of the transmon frequency. Utilizing these oscillations, we perform a universal set of quantum gates on 38 arbitrary pairs of modes and prepare multimode entangled states, all using only two control lines. We thus achieve hardware-efficient random access multi-qubit control in an architecture compatible with long-lived microwave cavity-based quantum memories.

  14. The hardware track finder processor in CMS at CERN

    CERN Document Server

    Kluge, A

    1997-01-01

    The work covers the design of the Track Finder Processor in the high energy experiment CMS (Compact Muon Solenoid, planned for 2005) at CERN/Geneva. The task of this processor is to identify muons and measure their transverse momentum. The track finder processor makes it possible to determine the physical relevance of each high energetic collision and to forward only interesting data to the data an alysis units. Data of more than two hundred thousand detector cells are used to determine the location of muons and measure their transverse momentum. Each 25 ns a new data set is generated. Measurem ent of location and transverse momentum of the muons can be terminated within 350 ns by using an ASIC (Application Specific Integrated Circuit). A pipeline architecture processes new data sets with th e required data rate of 40 MHz to ensure dead time free operation. In the framework of this study specifications and the overall concept of the track finder processor were worked out in detail. Simul ations were performed...

  15. A Digital Data Processor for Synthetic Aperture Radar

    NARCIS (Netherlands)

    Vlothuizen, W.J.; Medenblik, H.J.W.

    2007-01-01

    This paper presents a Digital Data Processor (DDP) for Synthetic Aperture Radar (SAR). The DDP captures SAR data at a 1 GHz sample rate and processes data at 350 MB/s. Data reduction is performed by a digital down converter, programmable decimating filter and a fully programmable presummer. The

  16. Optical linear algebra processors - Noise and error-source modeling

    Science.gov (United States)

    Casasent, D.; Ghosh, A.

    1985-01-01

    The modeling of system and component noise and error sources in optical linear algebra processors (OLAPs) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.

  17. Optical linear algebra processors: noise and error-source modeling.

    Science.gov (United States)

    Casasent, D; Ghosh, A

    1985-06-01

    The modeling of system and component noise and error sources in optical linear algebra processors (OLAP's) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.

  18. Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures

    Science.gov (United States)

    Manolakos, Elias S.

    2015-01-01

    Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub. PMID:26605332

  19. Using a Multicore Processor for Rover Autonomous Science

    Science.gov (United States)

    Bornstein, Benjamin; Estlin, Tara; Clement, Bradley; Springer, Paul

    2011-01-01

    Multicore processing promises to be a critical component of future spacecraft. It provides immense increases in onboard processing power and provides an environment for directly supporting fault-tolerant computing. This paper discusses using a state-of-the-art multicore processor to efficiently perform image analysis onboard a Mars rover in support of autonomous science activities.

  20. Support for RESTOR, EMIST, and CHREC Space Processor

    Science.gov (United States)

    Shea, Bradley Franklin

    2014-01-01

    The goal of this project was to provide support for three different projects including RESTOR, CHREC Space Processor, and EMIST. LabVIEW software was written to verify tags in an excel spreadsheet, testing preparation was accomplished for CHREC, and full payload integration was completed for EMIST. All of these projects will contribute to advanced exploration in space and provide valuable experience.

  1. A post-processor for the PEST code

    Energy Technology Data Exchange (ETDEWEB)

    Priesche, S.; Manickam, J.; Johnson, J.L.

    1992-01-01

    A new post-processor has been developed for use with output from the PEST tokamak stability code. It allows us to use quantities calculated by PEST and take better advantage of the physical picture of the plasma instability which they can provide. This will improve comparison with experimentally measured quantities as well as facilitate understanding of theoretical studies.

  2. Generalized processor sharing queues with heterogeneous traffic classes

    NARCIS (Netherlands)

    Borst, Sem; Mandjes, M.R.H.; van Uitert, Miranda

    2003-01-01

    We consider a queue fed by a mixture of light-tailed and heavy-tailed traffic. The two traffic flows are served in accordance with the generalized processor sharing (GPS) discipline. GPS-based scheduling algorithms, such as weighted fair queueing (WFQ), have emerged as an important mechanism for

  3. Thermal Expansion and Aging Effects in Neuromorphic Signal Processor

    NARCIS (Netherlands)

    Zjajo, A.; van Leuken, T.G.R.M.

    2016-01-01

    In this paper, we propose an efficient methodology based on a real-time estimator and predictor-corrector scheme for accurate thermal expansion profile and aging evaluation of a neuromorphic signal processor circuit components. As the experimental results indicate, for comparable mesh size, the

  4. Digital signal processor and processing method for GPS receivers

    Science.gov (United States)

    Thomas, Jr., Jess B. (Inventor)

    1989-01-01

    A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

  5. 3-D Scene Generation On A Shared Memory Parallel Processor

    Science.gov (United States)

    Kelly, R. F.

    1987-06-01

    Realistic 3-D scene generation is now a possibility for many applications. One barrier to increased use of this technique is the large amount of computer processing time needed to render a scene. With the advent of parallel processors that barrier may be overcome if efficient parallel scene generation algorithms can be developed. In general, this has not been true because of restrictions imposed by non-shared memory and limited processor interconnect architectures. In addition, vector processors do not efficiently support the adaptive nature of many of the algorithms. A new parallel computer, the NYU Ultracomputer, has been developed which features a shared memory with a combining network. The com-bining network permits simultaneous reads and writes to the same memory location using a new instruction the Fetch and_Op. These memory references are resolved in the memory access network and result in particularly efficient shared data structures. Basic elements of this architecture are also being used in the design of the gigaflop range RP3 at IBM. Some algorithms typical of image synthesis are explored in the paper and a class of equivalent queue based algorithms are developed. These algorithms are particularly well suited to the Ultra-computer class processor and hold the promise for many new applications of realistic scene generation.

  6. Evaluating the Use of Word Processors in Teaching Writing Composition.

    Science.gov (United States)

    Moore, Margaret A.; Turner, Susan D.

    1988-01-01

    This exploratory study evaluated the effects of using word processors to aid fourth- and fifth-graders in developing writing skills. The study focused on the Developmental Writing Program of the Hillsborough County (Florida) School District. A pre-study assessment indicated that, although students wrote well, they were reluctant to revise and edit…

  7. Processors' training needs on modern shea butter processing ...

    African Journals Online (AJOL)

    The need for continual production of high quality shea butter in Nigeria through the use of modern processing technologies necessitated this study. The study was carried out to ascertain training needs of shea butter processors on modern processing technologies in North Central Agro-ecological zone of Nigeria. Primary ...

  8. Rapid-Prototyping of Application Specific Signal Processors (RASSP) Education and Facilitation

    National Research Council Canada - National Science Library

    Gadient, Anthony

    2000-01-01

    The Rapid-Prototyping of Application Specific Signal Processors (RASSP) program was a major DARPA/Tri-Service initiative to reinvent the process by which embedded digital signal processors were developed...

  9. A soft-core processor architecture optimised for radar signal processing applications

    CSIR Research Space (South Africa)

    Broich, R

    2013-12-01

    Full Text Available Current radar signal processor architectures lack either performance or flexibility in terms of ease of modification and large design time overheads. Combinations of processors and FPGAs are typically hard-wired together into a precisely timed...

  10. Space shuttle navigation filter development. [data processor for radar tracking data

    Science.gov (United States)

    Lear, W. M.

    1976-01-01

    Problems encountered in developing a high speed trajectory data processor for the shuttle ascent and entry phases are described. The development of a 19 state acceleration filter for the processor is reported.

  11. A Real-Time Multi-Processor for Adaptive Control Experiments

    National Research Council Canada - National Science Library

    Bernstein, Dennis

    1999-01-01

    .... The key instrumentation is a special purpose multiprocessor configuration based on 4 Texas Instruments TMS320C40 60 MHz DSP processors and 4 DEC Alpha AXP 21164 500 MHz processors with 32 input...

  12. Real-time optical processor prototype for remote SAR applications

    Science.gov (United States)

    Marchese, Linda; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Bourqui, Pascal; Legros, Mathieu; Desnoyers, Nichola; Guillot, Ludovic; Mercier, Luc; Savard, Maxime; Martel, Anne; Châteauneuf, François; Bergeron, Alain

    2009-09-01

    A Compact Real-Time Optical SAR Processor has been successfully developed and tested. SAR, or Synthetic Aperture Radar, is a powerful tool providing enhanced day and night imaging capabilities. SAR systems typically generate large amounts of information generally in the form of complex data that are difficult to compress. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Indeed, the first SAR images have been optically processed. The optical processor architecture provides inherent parallel computing capabilities that can be used advantageously for the SAR data processing. Onboard SAR image generation would provide local access to processed information paving the way for real-time decision-making. This could eventually benefit navigation strategy and instrument orientation decisions. Moreover, for interplanetary missions, onboard analysis of images could provide important feature identification clues and could help select the appropriate images to be transmitted to Earth, consequently helping bandwidth management. This could ultimately reduce the data throughput requirements and related transmission bandwidth. This paper reviews the design of a compact optical SAR processor prototype that would reduce power, weight, and size requirements and reviews the analysis of SAR image generation using the table-top optical processor. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and size are reviewed. Results of image generation from simulated point targets as well as real satellite-acquired raw data are presented.

  13. A complete miniaturized microstructured methanol fuel processor/fuel cell system for low power applications

    Energy Technology Data Exchange (ETDEWEB)

    Men, Yong; Kolb, Gunther; Zapf, Ralf; Tiemann, David; Wichert, Martin; Hessel, Volker; Loewe, Holger [Institut fuer Mikrotechnik Mainz GmbH, Carl Zeiss Str. 18-20, D-55129, Mainz (Germany)

    2008-02-15

    A complete miniaturized methanol fuel processor/fuel cell system was developed and put into operation as compact hydrogen supplier for low power application. The whole system consisting of a micro-structured evaporator, a micro-structured reformer and two stages of preferential oxidation of CO (PROX) reactor, micro-structured catalytic burner, and fuel cell was operated to evaluate the performance of the whole production line from methanol to electricity. The performance of micro methanol steam reformer and PROX reactor was systematically investigated. The effect of reaction temperature, steam to carbon ratio, and contact time on the methanol steam reformer performance is presented in terms of catalytic activity, selectivity, and reformate yield. The performance of PROX reactor fed with the reformate produced by the reformer reactor was evaluated by the variation of reaction temperature and oxygen to CO ratio. The results demonstrate that micro-structured device may be an attractive power source candidate for low power application. (author)

  14. Lossy Compression of Biometric Images Implemented Using Floating Point DSP Processor

    Directory of Open Access Journals (Sweden)

    Azuwam Azuwam Ali Alhadi

    2017-01-01

    Full Text Available In this paper, several numbers of biometric images are compressed in order to reduce the number of bits needed in representing an image with conservation of image quality. Biometric images compression is important to solve the problem of efficiently transmitting data and storing large number of biometric images in low capacity of memory device. Biometric images are compressed using two techniques which are DCT and Quantization. The compression algorithm is implemented on general purpose computer and DSP processor in order to compare between both of them in terms processing time and evaluate the performance of this technique by measuring the difference between the original image and reconstructed image using PSNR, SSIM and MSE. Experimental results show DCT algorithm produces a high quality for reconstructed images with acceptable compression rate in terms of quality level is more than 50%. Furthermore, implementing the proposed algorithm using DSP board achieves better performance in terms of processing time compared with PC based.

  15. The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

    Science.gov (United States)

    Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin

    2017-01-01

    Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs. PMID:28241437

  16. The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

    Directory of Open Access Journals (Sweden)

    Seung-Ho Ok

    2017-02-01

    Full Text Available Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV, three-dimensional (3D stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

  17. The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.

    Science.gov (United States)

    Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin

    2017-02-22

    Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

  18. 17 CFR 242.609 - Registration of securities information processors: form of application and amendments.

    Science.gov (United States)

    2010-04-01

    ... information processors: form of application and amendments. 242.609 Section 242.609 Commodity and Securities....609 Registration of securities information processors: form of application and amendments. (a) An application for the registration of a securities information processor shall be filed on Form SIP (§ 249.1001...

  19. 40 CFR 80.840 - What requirements apply to transmix processors?

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 16 2010-07-01 2010-07-01 false What requirements apply to transmix processors? 80.840 Section 80.840 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR... Requirements § 80.840 What requirements apply to transmix processors? Any transmix processor who produces...

  20. 50 CFR 679.63 - Catch weighing requirements for vessels and processors.

    Science.gov (United States)

    2010-10-01

    ... and processors. 679.63 Section 679.63 Wildlife and Fisheries FISHERY CONSERVATION AND MANAGEMENT... Management Measures § 679.63 Catch weighing requirements for vessels and processors. (a) What are the requirements for listed AFA catcher/processors and AFA motherships?—(1) Catch weighing. All groundfish landed...

  1. 77 FR 44572 - Second Fishing Capacity Reduction Program for the Longline Catcher Processor Subsector of the...

    Science.gov (United States)

    2012-07-30

    ... Reduction Program for the Longline Catcher Processor Subsector of the Bering Sea and Aleutian Islands Non... Longline Catcher Processor Subsector of the Bering Sea and Aleutian Islands (BSAI) non-pollock groundfish... Catcher Processor Subsector, NMFS must publish these regulations. Initial Reduction Program The measures...

  2. 50 CFR 660.160 - Catcher/processor (C/P) Coop Program.

    Science.gov (United States)

    2010-10-01

    ... 50 Wildlife and Fisheries 9 2010-10-01 2010-10-01 false Catcher/processor (C/P) Coop Program. 660... Groundfish-Limited Entry Trawl Fisheries § 660.160 Catcher/processor (C/P) Coop Program. (a) General. The C/P... fishery and is a single voluntary coop. Eligible harvesters and processors must meet the requirements set...

  3. 50 CFR 679.81 - Rockfish Program annual harvester and processor privileges.

    Science.gov (United States)

    2010-10-01

    ... processor privileges. 679.81 Section 679.81 Wildlife and Fisheries FISHERY CONSERVATION AND MANAGEMENT... EXCLUSIVE ECONOMIC ZONE OFF ALASKA Rockfish Program § 679.81 Rockfish Program annual harvester and processor.../processor sector or the catcher vessel sector. The tonnage of fish assigned to a sector will be further...

  4. Method and apparatus for delegation of secure operating mode access privilege from processor to peripheral

    NARCIS (Netherlands)

    Bosch, H.G.P.; McLellan Jr, Hubert Rae; Mullender, Sape J.

    2007-01-01

    In a processing system comprising a processor and a plurality of peripherals coupled to the processor, access privileges of a secure operating mode of the processor are delegated to at least a given one of the peripherals. The given peripheral is configured to store, in a secure portion of that

  5. 77 FR 124 - Biological Processors of Alabama; Decatur, Morgan County, AL; Notice of Settlement

    Science.gov (United States)

    2012-01-03

    ... AGENCY Biological Processors of Alabama; Decatur, Morgan County, AL; Notice of Settlement AGENCY... Biological Processors of Alabama Superfund Site located in Decatur, Morgan County, Alabama. DATES: The Agency... name Biological Processors of Alabama Superfund Site by one of the following methods: www.epa.gov...

  6. Long-term subjective benefit with a bone conduction implant sound processor in 44 patients with single-sided deafness.

    Science.gov (United States)

    Desmet, Jolien; Wouters, Kristien; De Bodt, Marc; Van de Heyning, Paul

    2014-07-01

    Studies that investigate the subjective benefit from a bone conduction implant (BCI) sound processor in patients with single-sided sensorineural deafness (SSD) have been limited to examining short- and mid-term benefit. In the current study, we performed a survey among 44 SSD BCI users with a median follow-up time of 50 months. Forty-four experienced SSD BCI users participated in the survey, which consisted of the Abbreviated Profile of Hearing Aid Benefit, the Single-Sided Deafness Questionnaire, the Short Hearing Handicap Inventory for Adults, and a self-made user questionnaire. For patients with tinnitus, the Tinnitus Questionnaire was also completed. The results of the survey were correlated with contralateral hearing loss, age at implantation, duration of the hearing loss at the time of implantation, duration of BCI use, and the presence and burden of tinnitus. In total, 86% of the patients still used their sound processor. The Abbreviated Profile of Hearing Aid Benefit and the Short Hearing Handicap Inventory for Adults show a statistically significant overall improvement with the BCI. The Single-Sided Deafness Questionnaire and the user questionnaire showed that almost 40% of the patients reported daily use of the sound processor. However, the survey of daily use reveals benefit only in certain circumstances. Speech understanding in noisy situations is rated rather low, and 58% of all patients reported that their BCI benefit was less than expected. The majority of the patients reported an overall improvement from using their BCI. However, the number of users decreases during a longer follow-up time and patients get less enthusiastic about the device after an extended period of use, especially in noisy situations. However, diminished satisfaction because of time-related reductions in processor function could not be ruled out.

  7. An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

    Science.gov (United States)

    Hudec, Ján; Gramatová, Elena

    2015-07-01

    The paper presents a new functional test generation method for processors testing based on genetic algorithms and evolutionary strategies. The tests are generated over an instruction set architecture and a processor description. Such functional tests belong to the software-oriented testing. Quality of the tests is evaluated by code coverage of the processor description using simulation. The presented test generation method uses VHDL models of processors and the professional simulator ModelSim. The rules, parameters and fitness functions were defined for various genetic algorithms used in automatic test generation. Functionality and effectiveness were evaluated using the RISC type processor DP32.

  8. NMRFx Processor: a cross-platform NMR data processing program

    Energy Technology Data Exchange (ETDEWEB)

    Norris, Michael; Fetler, Bayard [One Moon Scientific, Inc. (United States); Marchant, Jan [University of Maryland Baltimore County, Howard Hughes Medical Institute (United States); Johnson, Bruce A., E-mail: bruce.johnson@asrc.cuny.edu [One Moon Scientific, Inc. (United States)

    2016-08-15

    NMRFx Processor is a new program for the processing of NMR data. Written in the Java programming language, NMRFx Processor is a cross-platform application and runs on Linux, Mac OS X and Windows operating systems. The application can be run in both a graphical user interface (GUI) mode and from the command line. Processing scripts are written in the Python programming language and executed so that the low-level Java commands are automatically run in parallel on computers with multiple cores or CPUs. Processing scripts can be generated automatically from the parameters of NMR experiments or interactively constructed in the GUI. A wide variety of processing operations are provided, including methods for processing of non-uniformly sampled datasets using iterative soft thresholding. The interactive GUI also enables the use of the program as an educational tool for teaching basic and advanced techniques in NMR data analysis.

  9. Programming massively parallel processors a hands-on approach

    CERN Document Server

    Kirk, David B

    2010-01-01

    Programming Massively Parallel Processors discusses basic concepts about parallel programming and GPU architecture. ""Massively parallel"" refers to the use of a large number of processors to perform a set of computations in a coordinated parallel way. The book details various techniques for constructing parallel programs. It also discusses the development process, performance level, floating-point format, parallel patterns, and dynamic parallelism. The book serves as a teaching guide where parallel programming is the main topic of the course. It builds on the basics of C programming for CUDA, a parallel programming environment that is supported on NVI- DIA GPUs. Composed of 12 chapters, the book begins with basic information about the GPU as a parallel computer source. It also explains the main concepts of CUDA, data parallelism, and the importance of memory access efficiency using CUDA. The target audience of the book is graduate and undergraduate students from all science and engineering disciplines who ...

  10. Dense and Sparse Matrix Operations on the Cell Processor

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Samuel W.; Shalf, John; Oliker, Leonid; Husbands,Parry; Yelick, Katherine

    2005-05-01

    The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. Therefore, the high performance computing community is examining alternative architectures that address the limitations of modern superscalar designs. In this work, we examine STI's forthcoming Cell processor: a novel, low-power architecture that combines a PowerPC core with eight independent SIMD processing units coupled with a software-controlled memory to offer high FLOP/s/Watt. Since neither Cell hardware nor cycle-accurate simulators are currently publicly available, we develop an analytic framework to predict Cell performance on dense and sparse matrix operations, using a variety of algorithmic approaches. Results demonstrate Cell's potential to deliver more than an order of magnitude better GFLOP/s per watt performance, when compared with the Intel Itanium2 and Cray X1 processors.

  11. Using graphics processors to accelerate protein docking calculations.

    Science.gov (United States)

    Ritchie, David W; Venkatraman, Vishwesh; Mavridis, Lazaros

    2010-01-01

    Protein docking is the computationally intensive task of calculating the three-dimensional structure of a protein complex starting from the individual structures of the constituent proteins. In order to make the calculation tractable, most docking algorithms begin by assuming that the structures to be docked are rigid. This article describes some recent developments we have made to adapt our FFT-based "Hex" rigid-body docking algorithm to exploit the computational power of modern graphics processors (GPUs). The Hex algorithm is very efficient on conventional central processor units (CPUs), yet significant further speed-ups have been obtained by using GPUs. Thus, FFT-based docking calculations which formerly took many hours to complete using CPUs may now be carried out in a matter of seconds using GPUs. The Hex docking program and access to a server version of Hex on a GPU-based compute cluster are both available for public use.

  12. Jones matrix treatment for optical Fourier processors with structured polarization.

    Science.gov (United States)

    Moreno, Ignacio; Iemmi, Claudio; Campos, Juan; Yzuel, Maria J

    2011-02-28

    We present a Jones matrix method useful to analyze coherent optical Fourier processors employing structured polarization. The proposed method is a generalization of the standard classical optical Fourier transform processor, but considering vectorial spatial functions with two complex components corresponding to two orthogonal linear polarizations. As a result we derive a Jones matrix that describes the polarization output in terms of two vectorial functions defining respectively the structured polarization input and the generalized polarization impulse response. We apply the method to show and analyze an experiment in which a regular scalar diffraction grating is converted into equivalent polarization diffraction gratings by means of an appropriate polarization filtering. The technique is further demonstrated to generate arbitrary structured polarizations. Excellent experimental results are presented.

  13. Signal Processing with Teams of Embedded Workhorse Processors

    Directory of Open Access Journals (Sweden)

    B. Ressl

    2006-09-01

    Full Text Available Advanced signal processing for voice and data in wired or wireless environments can require massive computational power. Due to the complexity and continuing evolution of such systems, it is desirable to maintain as much software controllability in the field as possible. Time to market can also be improved by reducing the amount of hardware design. This paper describes an architecture based on clusters of embedded “workhorse” processors which can be dynamically harnessed in real time to support a wide range of computational tasks. Low-power processors and memory are important ingredients in such a highly parallel environment.

  14. Ingredients of Adaptability: A Survey of Reconfigurable Processors

    Directory of Open Access Journals (Sweden)

    Anupam Chattopadhyay

    2013-01-01

    Full Text Available For a design to survive unforeseen physical effects like aging, temperature variation, and/or emergence of new application standards, adaptability needs to be supported. Adaptability, in its complete strength, is present in reconfigurable processors, which makes it an important IP in modern System-on-Chips (SoCs. Reconfigurable processors have risen to prominence as a dominant computing platform across embedded, general-purpose, and high-performance application domains during the last decade. Significant advances have been made in many areas such as, identifying the advantages of reconfigurable platforms, their modeling, implementation flow and finally towards early commercial acceptance. This paper reviews these progresses from various perspectives with particular emphasis on fundamental challenges and their solutions. Empowered with the analysis of past, the future research roadmap is proposed.

  15. The fast tracker processor for hadronic collider triggers

    CERN Document Server

    Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, F; Pietri, M; Varotto, G

    2000-01-01

    Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points (patterns) for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at a rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution traces with transverse momentum above few GeV and search secondary vertexes within typical level-2 times. 15 Refs.

  16. The fast tracker processor for hadron collider triggers

    CERN Document Server

    Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, E; Pietri, M; Varotto, G

    2001-01-01

    Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times. (15 refs).

  17. Investigation of DMSD Trend in the ISS Water Processor Assembly

    Science.gov (United States)

    Carter, Layne; Bowman, Elizabeth; Wilson, Mark; Gentry, Greg; Rector, Tony

    2013-01-01

    The ISS Water Recovery System (WRS) is responsible for providing potable water to the crew, to the Oxygen Generation System (OGS) for oxygen production via electrolysis, to the Waste & Hygiene Compartment (WHC) for flush water, and for experiments on ISS. The WRS includes the Water Processor Assembly (WPA) and the Urine Processor Assembly (UPA). The WPA processes condensate from the cabin air and distillate produced by the UPA. In 2010, an increasing trend in the Total Organic Carbon (TOC) in the potable water was ultimately identified as dimethylsilanediol (DMSD). The increasing trend was ultimately reversed after replacing the WPA's two multifiltration beds. However, the reason for the TOC trend and the subsequent recovery was not understood. A subsequent trend occurred in 2012. This paper summarizes the current understanding of the fate of DMSD in the WPA, how the increasing TOC trend occurred, and the plan for modifying the WPA to prevent recurrence.

  18. Optical chirp z-transform processor with a simplified architecture.

    Science.gov (United States)

    Ngo, Nam Quoc

    2014-12-29

    Using a simplified chirp z-transform (CZT) algorithm based on the discrete-time convolution method, this paper presents the synthesis of a simplified architecture of a reconfigurable optical chirp z-transform (OCZT) processor based on the silica-based planar lightwave circuit (PLC) technology. In the simplified architecture of the reconfigurable OCZT, the required number of optical components is small and there are no waveguide crossings which make fabrication easy. The design of a novel type of optical discrete Fourier transform (ODFT) processor as a special case of the synthesized OCZT is then presented to demonstrate its effectiveness. The designed ODFT can be potentially used as an optical demultiplexer at the receiver of an optical fiber orthogonal frequency division multiplexing (OFDM) transmission system.

  19. Analog parallel processor hardware for high speed pattern recognition

    Science.gov (United States)

    Daud, T.; Tawel, R.; Langenbacher, H.; Eberhardt, S. P.; Thakoor, A. P.

    1990-01-01

    A VLSI-based analog processor for fully parallel, associative, high-speed pattern matching is reported. The processor consists of two main components: an analog memory matrix for storage of a library of patterns, and a winner-take-all (WTA) circuit for selection of the stored pattern that best matches an input pattern. An inner product is generated between the input vector and each of the stored memories. The resulting values are applied to a WTA network for determination of the closest match. Patterns with up to 22 percent overlap are successfully classified with a WTA settling time of less than 10 microsec. Applications such as star pattern recognition and mineral classification with bounded overlap patterns have been successfully demonstrated. This architecture has a potential for an overall pattern matching speed in excess of 10 exp 9 bits per second for a large memory.

  20. NMRFx Processor: a cross-platform NMR data processing program.

    Science.gov (United States)

    Norris, Michael; Fetler, Bayard; Marchant, Jan; Johnson, Bruce A

    2016-08-01

    NMRFx Processor is a new program for the processing of NMR data. Written in the Java programming language, NMRFx Processor is a cross-platform application and runs on Linux, Mac OS X and Windows operating systems. The application can be run in both a graphical user interface (GUI) mode and from the command line. Processing scripts are written in the Python programming language and executed so that the low-level Java commands are automatically run in parallel on computers with multiple cores or CPUs. Processing scripts can be generated automatically from the parameters of NMR experiments or interactively constructed in the GUI. A wide variety of processing operations are provided, including methods for processing of non-uniformly sampled datasets using iterative soft thresholding. The interactive GUI also enables the use of the program as an educational tool for teaching basic and advanced techniques in NMR data analysis.

  1. Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures

    Directory of Open Access Journals (Sweden)

    Ausif Mahmood

    1996-01-01

    Full Text Available The development of multi-processor architectures requires extensive behavioral simulations to verify the correctness of design and to evaluate its performance. A high level language can provide maximum flexibility in this respect if the constructs for handling concurrent processes and a time mapping mechanism are added. This paper describes a novel technique for emulating hardware processes involved in a parallel architecture such that an object-oriented description of the design is maintained. The communication and synchronization between hardware processes is handled by splitting the processes into their equivalent subprograms at the entry points. The proper scheduling of these subprograms is coordinated by a timing wheel which provides a time mapping mechanism. Finally, a high level language pre-processor is proposed so that the timing wheel and the process emulation details can be made transparent to the user.

  2. Biological Water Processor and Forward Osmosis Secondary Treatment

    Science.gov (United States)

    Shull, Sarah; Meyer, Caitlin

    2014-01-01

    The goal of the Biological Water Processor (BWP) is to remove 90% organic carbon and 75% ammonium from an exploration-based wastewater stream for four crew members. The innovative design saves on space, power and consumables as compared to the ISS Urine Processor Assembly (UPA) by utilizing microbes in a biofilm. The attached-growth system utilizes simultaneous nitrification and denitrification to mineralize organic carbon and ammonium to carbon dioxide and nitrogen gas, which can be scrubbed in a cabin air revitalization system. The BWP uses a four-crew wastewater comprised of urine and humidity condensate, as on the ISS, but also includes hygiene (shower, shave, hand washing and oral hygiene) and laundry. The BWP team donates 58L per day of this wastewater processed in Building 7.

  3. Performance of Distributed CFAR Processors in Pearson Distributed Clutter

    Directory of Open Access Journals (Sweden)

    Faouzi Soltani

    2007-01-01

    Full Text Available This paper deals with the distributed constant false alarm rate (CFAR radar detection of targets embedded in heavy-tailed Pearson distributed clutter. In particular, we extend the results obtained for the cell averaging (CA, order statistics (OS, and censored mean level CMLD CFAR processors operating in positive alpha-stable (P&S random variables to more general situations, specifically to the presence of interfering targets and distributed CFAR detectors. The receiver operating characteristics of the greatest of (GO and the smallest of (SO CFAR processors are also determined. The performance characteristics of distributed systems are presented and compared in both homogeneous and in presence of interfering targets. We demonstrate, via simulation results, that the distributed systems when the clutter is modelled as positive alpha-stable distribution offer robustness properties against multiple target situations especially when using the “OR” fusion rule.

  4. Performance of Distributed CFAR Processors in Pearson Distributed Clutter

    Directory of Open Access Journals (Sweden)

    Messali Zoubeida

    2007-01-01

    Full Text Available This paper deals with the distributed constant false alarm rate (CFAR radar detection of targets embedded in heavy-tailed Pearson distributed clutter. In particular, we extend the results obtained for the cell averaging (CA, order statistics (OS, and censored mean level CMLD CFAR processors operating in positive alpha-stable (P&S random variables to more general situations, specifically to the presence of interfering targets and distributed CFAR detectors. The receiver operating characteristics of the greatest of (GO and the smallest of (SO CFAR processors are also determined. The performance characteristics of distributed systems are presented and compared in both homogeneous and in presence of interfering targets. We demonstrate, via simulation results, that the distributed systems when the clutter is modelled as positive alpha-stable distribution offer robustness properties against multiple target situations especially when using the "OR" fusion rule.

  5. SPP: A data base processor data communications protocol

    Science.gov (United States)

    Fishwick, P. A.

    1983-01-01

    The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

  6. JIST: Just-In-Time Scheduling Translation for Parallel Processors

    Directory of Open Access Journals (Sweden)

    Giovanni Agosta

    2005-01-01

    Full Text Available The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to software instruction scheduling, a must for the VLIW architectures. We have implemented JIST, a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor. We show the impact of various optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmark programs. We report significant speedups, and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JITcompiler. Further optimizations are discussed.

  7. The ATLAS Trigger Algorithms for General Purpose Graphics Processor Units

    CERN Document Server

    Tavares Delgado, Ademar; The ATLAS collaboration

    2016-01-01

    The ATLAS Trigger Algorithms for General Purpose Graphics Processor Units Type: Talk Abstract: We present the ATLAS Trigger algorithms developed to exploit General­ Purpose Graphics Processor Units. ATLAS is a particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system has two levels, hardware-­based Level 1 and the High Level Trigger implemented in software running on a farm of commodity CPU. Performing the trigger event selection within the available farm resources presents a significant challenge that will increase future LHC upgrades. are being evaluated as a potential solution for trigger algorithms acceleration. Key factors determining the potential benefit of this new technology are the relative execution speedup, the number of GPUs required and the relative financial cost of the selected GPU. We have developed a trigger demonstrator which includes algorithms for reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Cal...

  8. Onboard fuel processor for PEM fuel cell vehicles

    Energy Technology Data Exchange (ETDEWEB)

    Bowers, Brian J.; Zhao, Jian L.; Ruffo, Michael; Khan, Rafey; Dattatraya, Druva; Dushman, Nathan [Nuvera Fuel Cells, Inc, 20 Acorn Park, Cambridge, MA 02140 (United States); Beziat, Jean-Christophe; Boudjemaa, Fabien [Renault, Service 64240 - FR TCR GRA 0 75, Technocentre Renault - 1 avenue du Golf, 78288 Guyancourt (France)

    2007-07-15

    To lower vehicle greenhouse gas emissions, many automotive companies are exploring fuel cell technologies, which combine hydrogen and oxygen to produce electricity and water. While hydrogen storage and infrastructure remain issues, Renault and Nuvera Fuel Cells are developing an onboard fuel processor, which can convert a variety of fuels into hydrogen to power these fuel cell vehicles. The fuel processor is now small enough and powerful enough for use on a vehicle. The catalysts and heat exchangers occupy 80 l and can be packaged with balance of plant controls components in a 150-l volume designed to fit under the vehicle. Recent systems can operate on gasoline, ethanol, and methanol with fuel inputs up to 200 kWth and hydrogen efficiencies above 77%. The startup time is now less than 4 min to lower the CO in the hydrogen stream to the target value for the fuel cell. (author)

  9. A 1024 Processor 64-bit System-On-Chip

    Science.gov (United States)

    2017-03-01

    2X the memory per processor, and custom ISAs for deep learning, communication, and cryptography . Figure 1: Epiphany-V Overview Summary of...extensions for deep learning, communication, and cryptography Multiple Epiphany-V chips can be connected together at the board and system level using point...extensions for deep learning, communication, and cryptography e. I/O The Epiphany-V has a total of 1024 programmable I/O pins and 16 control input

  10. Dormancy and Recovery Testing for Biological Wastewater Processors

    Science.gov (United States)

    Hummerick, Mary F.; Coutts, Janelle L.; Lunn, Griffin M.; Spencer, LaShelle; Khodadad, Christina L.; Birmele, Michele N.; Frances, Someliz; Wheeler, Raymond

    2015-01-01

    Resource recovery and recycling waste streams to usable water via biological water processors is a plausible component of an integrated water purification system. Biological processing as a pretreatment can reduce the load of organic carbon and nitrogen compounds entering physiochemical systems downstream. Aerated hollow fiber membrane bioreactors, have been proposed and studied for a number of years as an approach for treating wastewater streams for space exploration.

  11. Challenge and Trend of Programming Model for Many Core Processor

    OpenAIRE

    Adnan, Adnan

    2012-01-01

    This paper reviews some important issues for scalability in programming and future trend with many-core technology. According some experimental results of different parallel programs, such as fast Fourier transform and Unbalanced Tree Search and on twelve cores of a parallel computer, we identified two issues that should be concerned in programming the many-core processor, and . The issues are efficiency, loadimbalance. Low efficiency of parallel program makes scalability...

  12. Reversible machine code and its abstract processor architecture

    DEFF Research Database (Denmark)

    Axelsen, Holger Bock; Glück, Robert; Yokoyama, Tetsuo

    2007-01-01

    A reversible abstract machine architecture and its reversible machine code are presented and formalized. For machine code to be reversible, both the underlying control logic and each instruction must be reversible. A general class of machine instruction sets was proven to be reversible, building ...... on our concept of reversible updates. The presentation is abstract and can serve as a guideline for a family of reversible processor designs. By example, we illustrate programming principles for the abstract machine architecture formalized in this paper....

  13. DEMAND FOR WILD BLUEBERRIES AT FARM AND PROCESSOR LEVELS

    OpenAIRE

    Cheng, Hsiang-Tai; Peavey, Stephanie R.; Kezis, Alan S.

    2000-01-01

    The wild blueberry crop harvested in Maine and eastern Canada has increased considerably in recent years. The purpose of this study is to understand the recent trends in demand for wild blueberries with particular attention to the effects of production and the marketing of wild and cultivated blueberries. A price response model was developed to analyze farm-gate price and the processor price, using annual data from 1978 through 1997. Key explanatory variables in the model include quantity of ...

  14. Method for Processing Liver Spheroids Using an Automatic Tissue Processor

    Science.gov (United States)

    2016-05-01

    tissue processor (Leica Biosystems, Inc.; Nussloch, Germany). This instrument is used to prepare tissue for histologic study through a process of...microscopy because they make it possible to observe the microscopic anatomy of the samples. The Molecular Toxicology Branch intends to use the Leica...approximately 1 mm in diameter, which is significantly smaller than the traditional histology whole-tissue samples. Because of the smaller size of these

  15. Clock-modulation based watermark for protection of embedded processors

    OpenAIRE

    Kufel, Jedrzej; Wilson, Peter; Hill, Stephen; Al-Hashimi, Bashir; Whatmough, Paul N.; Myers, James

    2014-01-01

    This paper presents a novel watermark generation technique for the protection of embedded processors. In previous work, a load circuit is used to generate detectable watermark patterns in the ASIC power supply. This approach leads to hardware area overheads. We propose removing the dedicated load circuit entirely, instead to compensate the reduced power consumption the watermark power pattern is emulated by reusing existing clock gated sequential logic as a zero-overhead load circuit and modu...

  16. Implementation and Evaluation of Fock Matrix Calculation Program on the Cell Processor

    Science.gov (United States)

    Honda, Hiroaki; Hayashi, Tetsuo; Inadomi, Yuichi; Inoue, Koji; Murakami, Kazuaki J.

    2007-12-01

    Various processor architectures have been proposed until today, and the performance has improved remarkably. Recently, the Chip Multi-processors (CMPs), which has many processor cores onto a chip, are proposed for further performance improvement. The Cell processor is one of such CMP and shows high computational performance. Although this processor is designed for the multimedia, that high performance character can be utilized to molecular orbital calculation. In this study we implemented Fock matrix construction program on the Cell processor, and evaluated computational performance. As a result, there were two kinds of main stalls by the branch prediction and the data alignment, which are controlled by software mechanism for the simplification of the Cell processor hardware. It is possible to improve the performance about 30%, if the branch prediction hit ratio could be improved to 99%. For data alignment stall, a part of stalls, which is originated by data shuffle pipeline, could be decreased by preparing hardware data alignment mechanism.

  17. Performance Scaling of Individual SPEC INT 2006 Results for AMD Processors

    Directory of Open Access Journals (Sweden)

    Abdul KAREEM P.

    2009-07-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. In this paper we describe the performance scaling trends in AMD Opteron 2000+ and AMD Opteron 8000+ series processors. The micro architecture of these processors is implemented using the basis of a new family of processors to AMD x86-64 processors. These processors can provide a performance boost for many key application areas in modern generation. We analyze the scaling of performance in two major series of AMD processors (AMD Opteron 2000+ and AMD Opteron 8000+ Series by using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. Our results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  18. Design and implementation of a high performance network security processor

    Science.gov (United States)

    Wang, Haixin; Bai, Guoqiang; Chen, Hongyi

    2010-03-01

    The last few years have seen many significant progresses in the field of application-specific processors. One example is network security processors (NSPs) that perform various cryptographic operations specified by network security protocols and help to offload the computation intensive burdens from network processors (NPs). This article presents a high performance NSP system architecture implementation intended for both internet protocol security (IPSec) and secure socket layer (SSL) protocol acceleration, which are widely employed in virtual private network (VPN) and e-commerce applications. The efficient dual one-way pipelined data transfer skeleton and optimised integration scheme of the heterogenous parallel crypto engine arrays lead to a Gbps rate NSP, which is programmable with domain specific descriptor-based instructions. The descriptor-based control flow fragments large data packets and distributes them to the crypto engine arrays, which fully utilises the parallel computation resources and improves the overall system data throughput. A prototyping platform for this NSP design is implemented with a Xilinx XC3S5000 based FPGA chip set. Results show that the design gives a peak throughput for the IPSec ESP tunnel mode of 2.85 Gbps with over 2100 full SSL handshakes per second at a clock rate of 95 MHz.

  19. A Geometric Algebra Co-Processor for Color Edge Detection

    Directory of Open Access Journals (Sweden)

    Biswajit Mishra

    2015-01-01

    Full Text Available This paper describes advancement in color edge detection, using a dedicated Geometric Algebra (GA co-processor implemented on an Application Specific Integrated Circuit (ASIC. GA provides a rich set of geometric operations, giving the advantage that many signal and image processing operations become straightforward and the algorithms intuitive to design. The use of GA allows images to be represented with the three R, G, B color channels defined as a single entity, rather than separate quantities. A novel custom ASIC is proposed and fabricated that directly targets GA operations and results in significant performance improvement for color edge detection. Use of the hardware described in this paper also shows that the convolution operation with the rotor masks within GA belongs to a class of linear vector filters and can be applied to image or speech signals. The contribution of the proposed approach has been demonstrated by implementing three different types of edge detection schemes on the proposed hardware. The overall performance gains using the proposed GA Co-Processor over existing software approaches are more than 3.2× faster than GAIGEN and more than 2800× faster than GABLE. The performance of the fabricated GA co-processor is approximately an order of magnitude faster than previously published results for hardware implementations.

  20. A programmable analog VLSI neural network processor for communication receivers.

    Science.gov (United States)

    Choi, J; Bang, S H; Sheu, B J

    1993-01-01

    An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.

  1. Broadband set-top box using MAP-CA processor

    Science.gov (United States)

    Bush, John E.; Lee, Woobin; Basoglu, Chris

    2001-12-01

    Advances in broadband access are expected to exert a profound impact in our everyday life. It will be the key to the digital convergence of communication, computer and consumer equipment. A common thread that facilitates this convergence comprises digital media and Internet. To address this market, Equator Technologies, Inc., is developing the Dolphin broadband set-top box reference platform using its MAP-CA Broadband Signal ProcessorT chip. The Dolphin reference platform is a universal media platform for display and presentation of digital contents on end-user entertainment systems. The objective of the Dolphin reference platform is to provide a complete set-top box system based on the MAP-CA processor. It includes all the necessary hardware and software components for the emerging broadcast and the broadband digital media market based on IP protocols. Such reference design requires a broadband Internet access and high-performance digital signal processing. By using the MAP-CA processor, the Dolphin reference platform is completely programmable, allowing various codecs to be implemented in software, such as MPEG-2, MPEG-4, H.263 and proprietary codecs. The software implementation also enables field upgrades to keep pace with evolving technology and industry demands.

  2. Hardware Synchronization for Embedded Multi-Core Processors

    DEFF Research Database (Denmark)

    Stoif, Christian; Schoeberl, Martin; Liccardi, Benito

    2011-01-01

    Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establi...... single-ported memory if the multiple cores use inherent parallelism by locking shared memory more intelligently using an address-sensitive method......., establishing coherence and consistency for different types of shared memory by hardware means. Also support for point-to-point synchronization between the processor cores is realized implementing different hardware barriers. The practical examinations focus on the logical first step from single- to dual......-core systems, using an FPGA-development board with two hard PowerPC processor cores. Best- and worst-case results, together with intensive benchmarking of all synchronization primitives implemented, show the expected superiority of the hardware solutions. It is also shown that dual-ported memory outperforms...

  3. Insertion devices

    CERN Document Server

    Bahrdt, J

    2006-01-01

    The interaction of an insertion device with the electron beam in a storage ring is discussed. The radiation property including brightness, ux and polarization of an ideal and real planar and helical / elliptical device is described. The magnet design of planar, helical, quasiperiodic devices and of devices with a reduced on axis power density are resumed.

  4. A Fully Automatic Instantaneous Fire Hotspot Detection Processor Based on AVHRR Imagery—A TIMELINE Thematic Processor

    Directory of Open Access Journals (Sweden)

    Simon Plank

    2017-01-01

    Full Text Available The German Aerospace Center’s (DLR TIMELINE project aims to develop an operational processing and data management environment to process 30 years of National Oceanic and Atmospheric Administration (NOAA—Advanced Very High Resolution Radiometer (AVHRR raw data into L1b, L2 and L3 products. This article presents the current status of the fully automated L2 active fire hotspot detection processor, which is based on single-temporal datasets in orbit geometry. Three different probability levels of fire detection are provided. The results of the hotspot processor were tested with simulated fire data. Moreover, the processing results of real AVHRR imagery were validated with five different datasets: MODIS hotspots, visually confirmed MODIS hotspots, fire-news data from the European Forest Fire Information System (EFFIS, burnt area mapping of the Copernicus Emergency Management Service (EMS and data of the Piedmont fire database.

  5. 40 CFR 80.213 - What alternative sulfur standards and requirements apply to transmix processors and transmix...

    Science.gov (United States)

    2010-07-01

    ... requirements apply to transmix processors and transmix blenders? 80.213 Section 80.213 Protection of... requirements apply to transmix processors and transmix blenders? Transmix processors and transmix blenders, as... standards otherwise applicable to a refiner under subpart H of this part. (a) Any transmix processor who...

  6. GPU-based Parallel Application Design for Emerging Mobile Devices

    Science.gov (United States)

    Gupta, Kshitij

    A revolution is underway in the computing world that is causing a fundamental paradigm shift in device capabilities and form-factor, with a move from well-established legacy desktop/laptop computers to mobile devices in varying sizes and shapes. Amongst all the tasks these devices must support, graphics has emerged as the 'killer app' for providing a fluid user interface and high-fidelity game rendering, effectively making the graphics processor (GPU) one of the key components in (present and future) mobile systems. By utilizing the GPU as a general-purpose parallel processor, this dissertation explores the GPU computing design space from an applications standpoint, in the mobile context, by focusing on key challenges presented by these devices---limited compute, memory bandwidth, and stringent power consumption requirements---while improving the overall application efficiency of the increasingly important speech recognition workload for mobile user interaction. We broadly partition trends in GPU computing into four major categories. We analyze hardware and programming model limitations in current-generation GPUs and detail an alternate programming style called Persistent Threads, identify four use case patterns, and propose minimal modifications that would be required for extending native support. We show how by manually extracting data locality and altering the speech recognition pipeline, we are able to achieve significant savings in memory bandwidth while simultaneously reducing the compute burden on GPU-like parallel processors. As we foresee GPU computing to evolve from its current 'co-processor' model into an independent 'applications processor' that is capable of executing complex work independently, we create an alternate application framework that enables the GPU to handle all control-flow dependencies autonomously at run-time while minimizing host involvement to just issuing commands, that facilitates an efficient application implementation. Finally, as

  7. Power-Energy Simulation for Multi-Core Processors in Bench-marking

    Directory of Open Access Journals (Sweden)

    Mona A. Abou-Of

    2017-01-01

    Full Text Available At Microarchitectural level, multi-core processor, as a complex System on Chip, has sophisticated on-chip components including cores, shared caches, interconnects and system controllers such as memory and ethernet controllers. At technological level, architects should consider the device types forecast in the International Technology Roadmap for Semiconductors (ITRS. Energy simulation enables architects to study two important metrics simultaneously. Timing is a key element of the CPU performance that imposes constraints on the CPU target clock frequency. Power and the resulting heat impose more severe design constraints, such as core clustering, while semiconductor industry is providing more transistors in the die area in pace with Moore’s law. Energy simulators provide a solution for such serious challenge. Energy is modelled either by combining performance benchmarking tool with a power simulator or by an integrated framework of both performance simulator and power profiling system. This article presents and asses trade-offs between different architectures using four cores battery-powered mobile systems by running a custom-made and a standard benchmark tools. The experimental results assure the Energy/ Frequency convexity rule over a range of frequency settings on different number of enabled cores. The reported results show that increasing the number of cores has a great effect on increasing the power consumption. However, a minimum energy dissipation will occur at a lower frequency which reduces the power consumption. Despite that, increasing the number of cores will also increase the effective cores value which will reflect a better processor performance.

  8. Cochlear implants: 100 pediatric case conversions from the body worn to the nucleus esprit 22 ear level speech processor.

    Science.gov (United States)

    Dodd, M C; Nikolopoulos, T P; Totten, C; Cope, Y; O'Donoghue, G M

    2005-07-01

    To assess performance of Nucleus 22 mini system pediatric users converted from the Spectra 22 body-worn to the ESPrit 22 ear-level speech processor using aided thresholds and speech discrimination measures before and after the conversion. Spectra 22 body-worn speech processor users were chosen using preselection criteria (stable map, ability to report on the quality of the signal, no device problems). The subjects underwent tuning, map conversion, fitting of the ESPrit 22, and aided soundfield threshold and speech discrimination testing. The first 100 consecutive conversions are analyzed in this study. Fifty children (50%) were female, and 50 (50%) were male. The average age at implantation was 4.6 years (median 4.3 years, range 1.7 to 11 years). The average age of fitting the ear level speech processor was 11.1 years (median 11 years, range 6.2 to 18.2 years). Tertiary referral pediatric cochlear implant center in the United Kingdom. Of the 100 fittings attempted, all Spectra 22 maps could to be converted for use in the ESPrit 22. Of these 100 fittings, 44 were straightforward with no adjustment to map parameters being required, and 56 needed rate reductions and other map adjustments to achieve the conversion. The difference of the mean thresholds before and after the conversion did not exceed 2 dB across the frequencies studied (0.5-4 kHz). In 95% of the cases, the differences were less than 9 dB(A). With regard to speech discrimination testing, the mean threshold before the conversion was 53.4 dB and after the conversion 52.7 dB. Of the 100 conversions, only five children stopped using the ESPrit 22 despite fitting being achieved. Conversion from the Spectra 22 body worn to the ESPrit 22 ear level speech processor was found to be feasible in all the 100 cases studied. Only a minority (5%) of children chose not to use the ear level speech processor suggesting that children and parents were satisfied from the conversion.

  9. Maximum-likelihood and other processors for incoherent and coherent matched-field localization.

    Science.gov (United States)

    Dosso, Stan E; Wilmut, Michael J

    2012-10-01

    This paper develops a series of maximum-likelihood processors for matched-field source localization given various states of information regarding the frequency and time variation of source amplitude and phase, and compares these with existing approaches to coherent processing with incomplete source knowledge. The comparison involves elucidating each processor's approach to source spectral information within a unifying formulation, which provides a conceptual framework for classifying and comparing processors and explaining their relative performance, as quantified in a numerical study. The maximum-likelihood processors represent optimal estimators given the assumption of Gaussian noise, and are based on analytically maximizing the corresponding likelihood function over explicit unknown source spectral parameters. Cases considered include knowledge of the relative variation in source amplitude over time and/or frequency (e.g., a flat spectrum), and tracking the relative phase variation over time, as well as incoherent and coherent processing. Other approaches considered include the conventional (Bartlett) processor, cross-frequency incoherent processor, pair-wise processor, and coherent normalized processor. Processor performance is quantified as the probability of correct localization from Monte Carlo appraisal over a large number of random realizations of noise, source location, and environmental parameters. Processors are compared as a function of signal-to-noise ratio, number of frequencies, and number of sensors.

  10. A digital magnetic resonance imaging spectrometer using digital signal processor and field programmable gate array.

    Science.gov (United States)

    Liang, Xiao; Binghe, Sun; Yueping, Ma; Ruyan, Zhao

    2013-05-01

    A digital spectrometer for low-field magnetic resonance imaging is described. A digital signal processor (DSP) is utilized as the pulse programmer on which a pulse sequence is executed as a subroutine. Field programmable gate array (FPGA) devices that are logically mapped into the external addressing space of the DSP work as auxiliary controllers of gradient control, radio frequency (rf) generation, and rf receiving separately. The pulse programmer triggers an event by setting the 32-bit control register of the corresponding FPGA, and then the FPGA automatically carries out the event function according to preset configurations in cooperation with other devices; accordingly, event control of the spectrometer is flexible and efficient. Digital techniques are in widespread use: gradient control is implemented in real-time by a FPGA; rf source is constructed using direct digital synthesis technique, and rf receiver is constructed using digital quadrature detection technique. Well-designed performance is achieved, including 1 μs time resolution of the gradient waveform, 1 μs time resolution of the soft pulse, and 2 MHz signal receiving bandwidth. Both rf synthesis and rf digitalization operate at the same 60 MHz clock, therefore, the frequency range of transmitting and receiving is from DC to ~27 MHz. A majority of pulse sequences have been developed, and the imaging performance of the spectrometer has been validated through a large number of experiments. Furthermore, the spectrometer is also suitable for relaxation measurement in nuclear magnetic resonance field.

  11. An Alternative Water Processor for Long Duration Space Missions

    Science.gov (United States)

    Barta, Daniel J.; Pickering, Karen D.; Meyer, Caitlin; Pennsinger, Stuart; Vega, Leticia; Flynn, Michael; Jackson, Andrew; Wheeler, Raymond

    2014-01-01

    A new wastewater recovery system has been developed that combines novel biological and physicochemical components for recycling wastewater on long duration human space missions. Functionally, this Alternative Water Processor (AWP) would replace the Urine Processing Assembly on the International Space Station and reduce or eliminate the need for the multi-filtration beds of the Water Processing Assembly (WPA). At its center are two unique game changing technologies: 1) a biological water processor (BWP) to mineralize organic forms of carbon and nitrogen and 2) an advanced membrane processor (Forward Osmosis Secondary Treatment) for removal of solids and inorganic ions. The AWP is designed for recycling larger quantities of wastewater from multiple sources expected during future exploration missions, including urine, hygiene (hand wash, shower, oral and shave) and laundry. The BWP utilizes a single-stage membrane-aerated biological reactor for simultaneous nitrification and denitrification. The Forward Osmosis Secondary Treatment (FOST) system uses a combination of forward osmosis (FO) and reverse osmosis (RO), is resistant to biofouling and can easily tolerate wastewaters high in non-volatile organics and solids associated with shower and/or hand washing. The BWP has been operated continuously for over 300 days. After startup, the mature biological system averaged 85% organic carbon removal and 44% nitrogen removal, close to stoichiometric maximum based on available carbon. To date, the FOST has averaged 93% water recovery, with a maximum of 98%. If the wastewater is slighty acidified, ammonia rejection is optimal. This paper will provide a description of the technology and summarize results from ground-based testing using real wastewater

  12. State-based Communication on Time-predictable Multicore Processors

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Schoeberl, Martin; Sparsø, Jens

    2016-01-01

    Some real-time systems use a form of task-to-task communication called state-based or sample-based communication that does not impose any flow control among the communicating tasks. The concept is similar to a shared variable, where a reader may read the same value multiple times or may not read...... of tasks on other cores. Assuming a specific time-predictable multicore processor, we evaluate how the read and write primitives of the five algorithms contribute to the worst-case execution time of the communicating tasks. Each of the five algorithms has specific capabilities that make them suitable...

  13. Power estimation on functional level for programmable processors

    Directory of Open Access Journals (Sweden)

    M. Schneider

    2004-01-01

    Full Text Available In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA. Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA. This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated

  14. Addressing Thermal and Performance Variability Issues in Dynamic Processors

    Energy Technology Data Exchange (ETDEWEB)

    Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Llopis, Pablo [Univ. Carlos III de Madrid (Spain); Zhang, Kaicheng [Northwestern Univ., Evanston, IL (United States); Luo, Yingyi [Northwestern Univ., Evanston, IL (United States); Ogrenci-Memik, Seda [Northwestern Univ., Evanston, IL (United States); Memik, Gokhan [Northwestern Univ., Evanston, IL (United States); Sankaran, Rajesh [Argonne National Lab. (ANL), Argonne, IL (United States); Beckman, Pete [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-03-01

    As CMOS scaling nears its end, parameter variations (process, temperature and voltage) are becoming a major concern. To overcome parameter variations and provide stability, modern processors are becoming dynamic, opportunistically adjusting voltage and frequency based on thermal and energy constraints, which negatively impacts traditional bulk-synchronous parallelism-minded hardware and software designs. As node-level architecture is growing in complexity, implementing variation control mechanisms only with hardware can be a challenging task. In this paper we investigate a software strategy to manage hardwareinduced variations, leveraging low-level monitoring/controlling mechanisms.

  15. A Versatile Glass Processor for High-Performance Photonic Platforms

    Science.gov (United States)

    2015-12-08

    SECURITY CLASSIFICATION OF: With the DURIP fund, we acquire a glass processing station to enhance our capabilities to achieve ultra-high performance...funded by PECASE (supported by DoD-ARO under the contract/grant number W911NF-12-1-0026) on high performance optical sensors. The multipurpose glass ...Distribution Unlimited UU UU UU UU 08-12-2016 1-Aug-2014 31-Jul-2015 Final Report: A Versatile Glass Processor for High-Performance Photonic Platforms The views

  16. The Associative Memory Boards for the FTK Processor at ATLAS

    CERN Document Server

    Calabro, D; The ATLAS collaboration; Citraro, S; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2013-01-01

    The Associative Memory (AM) system, the main part of the FastTracker (FTK) processor, is designed to perform pattern matching using the information of the silicon tracking detectors. It finds track candidates at low resolution that are seeds for the following step performing precise track fitting. The system has to support challenging data traffic, handled by a group of modern low cost FPGAs, the Xilinx Spartan6 chips, which have Low-Power Gigabit Transceivers (GTP). Each GTP transceiver is a combined transmitter and receiver capable of operating at data rates up to 3.2 Gb/s. \

  17. Negative base encoding in optical linear algebra processors

    Science.gov (United States)

    Perlee, C.; Casasent, D.

    1986-01-01

    In the digital multiplication by analog convolution algorithm, the bits of two encoded numbers are convolved to form the product of the two numbers in mixed binary representation; this output can be easily converted to binary. Attention is presently given to negative base encoding, treating base -2 initially, and then showing that the negative base system can be readily extended to any radix. In general, negative base encoding in optical linear algebra processors represents a more efficient technique than either sign magnitude or 2's complement encoding, when the additions of digitally encoded products are performed in parallel.

  18. FlexFilm - an Image Processor for Digital Film Processing

    OpenAIRE

    Heithecker, Sven; do Carmo Lucas, Amilcar; Ernst, Rolf

    2006-01-01

    Digital film processing is characterized by a resolution of at least 2K (2048x1536 pixels per frame at 30 bit/pixel and 24 pictures/s, data rate of 2.2 GBit/s); higher resolutions of 4K (8.8 GBit/s) and even 8K (35.2 GBit/s) are on their way. Real-time processing at this data rate is beyond the scope of today's standard and DSP processors, and ASICs are not economically viable due to the small market volume. Therefore, an FPGA-based approach was followed in the FlexFilm project. Different app...

  19. FPGA Based Intelligent Co-operative Processor in Memory Architecture

    DEFF Research Database (Denmark)

    Ahmed, Zaki; Sotudeh, Reza; Hussain, Dil Muhammad Akbar

    2011-01-01

    benefits of PIM, a concept of Co-operative Intelligent Memory (CIM) was developed by the intelligent system group of University of Hertfordshire, based on the previously developed Co-operative Pseudo Intelligent Memory (CPIM). This paper provides an overview on previous works (CPIM, CIM) and realization......In a continuing effort to improve computer system performance, Processor-In-Memory (PIM) architecture has emerged as an alternative solution. PIM architecture incorporates computational units and control logic directly on the memory to provide immediate access to the data. To exploit the potential...

  20. High performance deformable image registration algorithms for manycore processors

    CERN Document Server

    Shackleford, James; Sharp, Gregory

    2013-01-01

    High Performance Deformable Image Registration Algorithms for Manycore Processors develops highly data-parallel image registration algorithms suitable for use on modern multi-core architectures, including graphics processing units (GPUs). Focusing on deformable registration, we show how to develop data-parallel versions of the registration algorithm suitable for execution on the GPU. Image registration is the process of aligning two or more images into a common coordinate frame and is a fundamental step to be able to compare or fuse data obtained from different sensor measurements. E

  1. Processor operated correlator with applications to laser Doppler signals

    DEFF Research Database (Denmark)

    Bisgaard, C.; Johnsen, B.; Hassager, Ole

    1984-01-01

    A 64-channel correlator is designed with application to the processing of laser Doppler anemometry signals in the range 200 Hz to 250 kHz. The correlator is processor operated to enable the consecutive sampling of 448 correlation functions at a rate up to 500 Hz. Software is described to identify...... a Doppler frequency from each correlation and the system is especially designed for transient flow signals. Doppler frequencies are determined with an accuracy of about 0.1%. Review of Scientific Instruments is copyrighted by The American Institute of Physics....

  2. Timing organization of a real-time multicore processor

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Sparsø, Jens

    2017-01-01

    Real-time systems need a time-predictable computing platform. Computation, communication, and access to shared resources needs to be time-predictable. We use time division multiplexing to statically schedule all computation and communication resources, such as access to main memory or message...... passing over a network-on-chip. We use time-driven communication over an asynchronous network-on-chip to enable time division multiplexing even in a globally asynchronous, locally synchronous multicore architecture. Using time division multiplexing at all levels of the architecture yields in a time......-predictable multicore processor where we can statically analyze the worst-case execution time of tasks....

  3. Safety-critical Java on a Java processor

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Rios Rivas, Juan Ricardo

    2012-01-01

    The safety-critical Java (SCJ) specification is developed within the Java Community Process under specification request number JSR 302. The specification is available as public draft, but details are still discussed by the expert group. In this stage of the specification we need prototype...... implementations of SCJ and first test applications that are written with SCJ, even when the specification is not finalized. The feedback from those prototype implementations is needed for final decisions. To help the SCJ expert group, a prototype implementation of SCJ on top of the Java optimized processor...

  4. Photovoltaic device

    Science.gov (United States)

    Reese, Jason A.; Keenihan, James R.; Gaston, Ryan S.; Kauffmann, Keith L.; Langmaid, Joseph A.; Lopez, Leonardo C.; Maak, Kevin D.; Mills, Michael E.; Ramesh, Narayan; Teli, Samar R.

    2015-09-01

    The present invention is premised upon an improved photovoltaic device ("PV device"), more particularly to an improved photovoltaic device (10) with a multilayered photovoltaic cell assembly (100) and a body portion (200) joined at an interface region (410) and including an intermediate layer (500), at least one interconnecting structural member (1500), relieving feature (2500), unique component geometry, or any combination thereof.

  5. Photovoltaic device

    Energy Technology Data Exchange (ETDEWEB)

    Reese, Jason A; Keenihan, James R; Gaston, Ryan S; Kauffmann, Keith L; Langmaid, Joseph A; Lopez, Leonardo; Maak, Kevin D; Mills, Michael E; Ramesh, Narayan; Teli, Samar R

    2017-03-21

    The present invention is premised upon an improved photovoltaic device ("PV device"), more particularly to an improved photovoltaic device with a multilayered photovoltaic cell assembly and a body portion joined at an interface region and including an intermediate layer, at least one interconnecting structural member, relieving feature, unique component geometry, or any combination thereof.

  6. Concentration device

    DEFF Research Database (Denmark)

    2013-01-01

    A concentration device (2) for filter filtration concentration of particles (4) from a volume of a fluid (6). The concentration device (2) comprises a filter (8) configured to filter particles (4) of a predefined size in the volume of the fluid (6). The concentration device (2) comprises...

  7. Multi-processor system for real-time flow estimation in medical ultrasound imaging

    DEFF Research Database (Denmark)

    Stetson, Paul F.; Jensen, Jesper Lomborg; Antonius, Peter

    1997-01-01

    is necessary for proper clinical evaluation of many algorithms, but this is generally impossible with conventional equipment.We present a multi-processor system capable of performing 1.2 billion flops, consisting of sixteen ADSP 21060 processors. Our system is based on four boards, each with four processors...... and shared internal and external memory. The processors can be flexibly configured using parallel communications links, so that almost any conceivable network of the sixteen processors can be made. The same type of links are used to interface with the data sampling system and with the PC used to display...... the processed data. The generous bandwidth of the links makes it easy to balance the computational load among the processors.In order to manage the shared system memory and to make use of the parallel processing capabilities of the system, a real-time multitasking kernel has been developed. The kernel uses...

  8. PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP

    OpenAIRE

    R. Maheswari; Pattabiraman, V.

    2012-01-01

    In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing) in the CPU/DSP (Digital Signal Processor) unit of OR1200 (Open Reduced Instruction Set Computer (RISC)...

  9. Anpassning av en C-kompilator för kodgenerering till en DSP-processor

    OpenAIRE

    Antelius, Henrik

    2004-01-01

    The purpose of this thesis is to retarget a C compiler for a DSP processor. Developing a new compiler from scratch is a major task. Instead, modifying an existing compiler so that it generates code for another target is a common way to develop compilers for new processors. This is called retargeting. This thesis describes how this was done with the LCC C compiler for the Motorola DSP56002 processor.

  10. Performance of High-Reliability Space-Qualified Processors Implementing Software Defined Radios

    Science.gov (United States)

    2014-03-01

    digital signal processor ( DSP ), a field programmable gate array (FPGA), or some combination of these. Since the modulation and coding are...NPS-EC-14-002 NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIFORNIA PERFORMANCE OF HIGH-RELIABILITY SPACE-QUALIFIED PROCESSORS ...Report 3. DATES COVERED (From-To) 01-01-2012 to 31-12-2013 4. TITLE AND SUBTITLE Performance of High-Reliability Space-Qualified Processors

  11. Open|SpeedShop Ease of Use Performance Analysis for Heterogenious Processor Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose building upon the modular extensible architecture and existing capabilities of Open|SpeedShop to provide seamless, integrated, heterogeneous processor...

  12. 'Smart', remote holographic processor based on the materials characteristics of LiNbO3

    Science.gov (United States)

    Vahey, D. W.

    1978-01-01

    A class of 'Smart' remote holographic processors based on the material characteristics of LiNbO3 is introduced. The processors rely on holographic subtraction to detect differences in optical wavefronts that are spatially modulated to reflect either incoming or reference information. The state of the art of their fabrication and performance is described in the following paper. This paper outlines the principles of holography and photorefractivity that make these processors possible. Particular emphasis is placed on a potential mode of operation termed self-subtraction, in which the holographic processor is able to adapt to changes in reference information without the need for commands from an external operator.

  13. Diversification of Processors Based on Redundancy in Instruction Set

    Science.gov (United States)

    Ichikawa, Shuichi; Sawada, Takashi; Hata, Hisashi

    By diversifying processor architecture, computer software is expected to be more resistant to plagiarism, analysis, and attacks. This study presents a new method to diversify instruction set architecture (ISA) by utilizing the redundancy in the instruction set. Our method is particularly suited for embedded systems implemented with FPGA technology, and realizes a genuine instruction set randomization, which has not been provided by the preceding studies. The evaluation results on four typical ISAs indicate that our scheme can provide a far larger degree of freedom than the preceding studies. Diversified processors based on MIPS architecture were actually implemented and evaluated with Xilinx Spartan-3 FPGA. The increase of logic scale was modest: 5.1% in Specialized design and 3.6% in RAM-mapped design. The performance overhead was also modest: 3.4% in Specialized design and 11.6% in RAM-mapped design. From these results, our scheme is regarded as a practical and promising way to secure FPGA-based embedded systems.

  14. Unmixed fuel processors and methods for using the same

    Science.gov (United States)

    Kulkarni, Parag Prakash; Cui, Zhe

    2010-08-24

    Disclosed herein are unmixed fuel processors and methods for using the same. In one embodiment, an unmixed fuel processor comprises: an oxidation reactor comprising an oxidation portion and a gasifier, a CO.sub.2 acceptor reactor, and a regeneration reactor. The oxidation portion comprises an air inlet, effluent outlet, and an oxygen transfer material. The gasifier comprises a solid hydrocarbon fuel inlet, a solids outlet, and a syngas outlet. The CO.sub.2 acceptor reactor comprises a water inlet, a hydrogen outlet, and a CO.sub.2 sorbent, and is configured to receive syngas from the gasifier. The regeneration reactor comprises a water inlet and a CO.sub.2 stream outlet. The regeneration reactor is configured to receive spent CO.sub.2 adsorption material from the gasification reactor and to return regenerated CO.sub.2 adsorption material to the gasification reactor, and configured to receive oxidized oxygen transfer material from the oxidation reactor and to return reduced oxygen transfer material to the oxidation reactor.

  15. The Topological Processor for the future ATLAS Level-1 Trigger

    CERN Document Server

    Kahra, C; The ATLAS collaboration

    2014-01-01

    ATLAS is an experiment on the Large Hadron Collider (LHC), located at the European Organization for Nuclear Research (CERN) in Switzerland. By 2015 the LHC instantaneous luminosity will be increased from $10^{34}$ up to $3\\cdot 10^{34} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 1kHz while at the same time, selecting those events that contain interesting physics events. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 100kHz and decision latency of less than $2.5 \\mu \\mathrm{s}$. It is composed of the Calorimeter Trigger, the Muon Trigger and the Central Trigger Processor (CTP). In 2014, there will be a new electronics module: the Topological Processor (L1Topo). The L1Topo will make it possible, for the first time, to use detailed information from subdetectors in a single Level-1 module. This allows the determi...

  16. Adaptive Robotic Welding Using A Rapid Image Pre-Processor

    Science.gov (United States)

    Dufour, M.; Begin, G.

    1984-02-01

    The rapid pre-processor initially developed by NRCC and Leigh Instruments Inc. as part of the visual aid system of the space shuttle arm 1 has been adapted to perform real time seam tracking of multipass butt weld and other adaptive welding functions. The weld preparation profile is first enhanced by a projected laser target formed by a line and dots. A standard TV camera is used to observe the target image at an angle. Displacement and distorsion of the target image on a monitor are simple functions of the preparation surface distance and shape respectively. Using the video signal, the pre-processor computes in real time the area and first moments of the white level figure contained within four independent rectangular windows in the field of view of the camera. The shape, size, and position of each window can be changed dynamically for each successive image at the standard 30 images/sec rate, in order to track some target image singularities. Visual sensing and welding are done simultaneously. As an example, it is shown that thin sheet metal welding can be automated using a single window for seam tracking, gap width measurement and torch height estimation. Using a second window, measurement of sheet misalignment and their orientation in space were also achieved. The system can be used at welding speed of up to 1 m/min. Simplicity, speed and effectiveness are the main advantages of this system.

  17. Fuel processor and method for generating hydrogen for fuel cells

    Science.gov (United States)

    Ahmed, Shabbir [Naperville, IL; Lee, Sheldon H. D. [Willowbrook, IL; Carter, John David [Bolingbrook, IL; Krumpelt, Michael [Naperville, IL; Myers, Deborah J [Lisle, IL

    2009-07-21

    A method of producing a H.sub.2 rich gas stream includes supplying an O.sub.2 rich gas, steam, and fuel to an inner reforming zone of a fuel processor that includes a partial oxidation catalyst and a steam reforming catalyst or a combined partial oxidation and stream reforming catalyst. The method also includes contacting the O.sub.2 rich gas, steam, and fuel with the partial oxidation catalyst and the steam reforming catalyst or the combined partial oxidation and stream reforming catalyst in the inner reforming zone to generate a hot reformate stream. The method still further includes cooling the hot reformate stream in a cooling zone to produce a cooled reformate stream. Additionally, the method includes removing sulfur-containing compounds from the cooled reformate stream by contacting the cooled reformate stream with a sulfur removal agent. The method still further includes contacting the cooled reformate stream with a catalyst that converts water and carbon monoxide to carbon dioxide and H.sub.2 in a water-gas-shift zone to produce a final reformate stream in the fuel processor.

  18. Reconfigurable Secure Video Codec Based on DWT and AES Processor

    Directory of Open Access Journals (Sweden)

    Rached Tourki

    2010-01-01

    Full Text Available In this paper, we proposed a secure video codec based on the discrete wavelet transformation (DWT and the Advanced Encryption Standard (AES processor. Either, use of video coding with DWT or encryption using AES is well known. However, linking these two designs to achieve secure video coding is leading. The contributions of our work are as follows. First, a new method for image and video compression is proposed. This codec is a synthesis of JPEG and JPEG2000,which is implemented using Huffman coding to the JPEG and DWT to the JPEG2000. Furthermore, an improved motion estimation algorithm is proposed. Second, the encryptiondecryption effects are achieved by the AES processor. AES is aim to encrypt group of LL bands. The prominent feature of this method is an encryption of LL bands by AES-128 (128-bit keys, or AES-192 (192-bit keys, or AES-256 (256-bit keys.Third, we focus on a method that implements partial encryption of LL bands. Our approach provides considerable levels of security (key size, partial encryption, mode encryption, and has very limited adverse impact on the compression efficiency. The proposed codec can provide up to 9 cipher schemes within a reasonable software cost. Latency, correlation, PSNR and compression rate results are analyzed and shown.

  19. The data handling processor of the Belle II DEPFET detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Tetsuichi; Paschen, Botho; Luetticke, Florian; Krueger, Hans; Marinas, Carlos; Wermes, Norbert [Universitaet Bonn (Germany); Collaboration: Belle II-Collaboration

    2016-07-01

    A two layer highly granular DEPFET pixel detector will be operated as the innermost subsystem of the Belle II experiment, at the new Japanese super flavor factory (SuperKEKB). Such a finely segmented system will allow to improve the vertex reconstruction in such ultra high luminosity environment but, at the same time, the raw data stream generated by the 8 million pixel detector will exceed the capability of real-time processing due to its high frame rate, considering the limited material budged and strict space constrains. For this reason a new ASIC, the Data Handling Processor (DHP) is designed to provide data processing at the level of the front-end electronics, such as zero-suppression and common mode correction. Additional feature of the Data Handling Processor is the control block, providing control signals for the on-module ASICs used in the pixel detector. In this contribution, the description of the latest chip revision in TSMC 65 nm technology together with the latest test results of the interface functionality tests are presented.

  20. Selection of a Brine Processor Technology for NASA Manned Missions

    Science.gov (United States)

    Carter, Donald L.; Gleich, Andrew F.

    2016-01-01

    The current ISS Water Recovery System (WRS) reclaims water from crew urine, humidity condensate, and Sabatier product water. Urine is initially processed by the Urine Processor Assembly (UPA) which recovers 75% of the urine as distillate. The remainder of the water is present in the waste brine which is currently disposed of as trash on ISS. For future missions this additional water must be reclaimed due to the significant resupply penalty for missions beyond Low Earth Orbit (LEO). NASA has pursued various technology development programs for a brine processor in the past several years. This effort has culminated in a technology down-select to identify the optimum technology for future manned missions. The technology selection is based on various criteria, including mass, power, reliability, maintainability, and safety. Beginning in 2016 the selected technology will be transitioned to a flight hardware program for demonstration on ISS. This paper summarizes the technology selection process, the competing technologies, and the rationale for the technology selected for future manned missions.

  1. Discovering Motifs in Biological Sequences Using the Micron Automata Processor.

    Science.gov (United States)

    Roy, Indranil; Aluru, Srinivas

    2016-01-01

    Finding approximately conserved sequences, called motifs, across multiple DNA or protein sequences is an important problem in computational biology. In this paper, we consider the (l, d) motif search problem of identifying one or more motifs of length l present in at least q of the n given sequences, with each occurrence differing from the motif in at most d substitutions. The problem is known to be NP-complete, and the largest solved instance reported to date is (26,11). We propose a novel algorithm for the (l,d) motif search problem using streaming execution over a large set of non-deterministic finite automata (NFA). This solution is designed to take advantage of the micron automata processor, a new technology close to deployment that can simultaneously execute multiple NFA in parallel. We demonstrate the capability for solving much larger instances of the (l, d) motif search problem using the resources available within a single automata processor board, by estimating run-times for problem instances (39,18) and (40,17). The paper serves as a useful guide to solving problems using this new accelerator technology.

  2. Quantum transport simulations in a programmable nanophotonic processor

    Science.gov (United States)

    Harris, Nicholas C.; Steinbrecher, Gregory R.; Prabhu, Mihika; Lahini, Yoav; Mower, Jacob; Bunandar, Darius; Chen, Changchen; Wong, Franco N. C.; Baehr-Jones, Tom; Hochberg, Michael; Lloyd, Seth; Englund, Dirk

    2017-07-01

    Environmental noise and disorder play critical roles in quantum particle and wave transport in complex media, including solid-state and biological systems. While separately both effects are known to reduce transport, recent work predicts that in a limited region of parameter space, noise-induced dephasing can counteract localization effects, leading to enhanced quantum transport. Photonic integrated circuits are promising platforms for studying such effects, with a central goal of developing large systems providing low-loss, high-fidelity control over all parameters of the transport problem. Here, we fully map the role of disorder in quantum transport using a nanophotonic processor: a mesh of 88 generalized beamsplitters programmable on microsecond timescales. Over 64,400 experiments we observe distinct transport regimes, including environment-assisted quantum transport and the 'quantum Goldilocks' regime in statically disordered discrete-time systems. Low-loss and high-fidelity programmable transformations make this nanophotonic processor a promising platform for many-boson quantum simulation experiments.

  3. A day in the life of a pharmacovigilance case processor

    Directory of Open Access Journals (Sweden)

    Ritesh Bhangale

    2017-01-01

    Full Text Available Pharmacovigilance (PV has grown significantly in India in the last couple of decades. The etymological roots for the word “pharmacovigilance” are “Pharmakon” (Greek for drug and “Vigilare” (Latin for to keep watch. It relies on information gathered from the collection of individual case safety reports and other pharmacoepidemiological data. The PV data processing cycle starts with data collection in computerized systems followed by complete data entry which includes adverse event coding, drug coding, causality and expectedness assessment, narrative writing, quality control, and report submissions followed by data storage and maintenance. A case processor plays an important role in conducting these various tasks. The case processor should also manage drug safety information, possess updated knowledge about global drug safety regulations, summarize clinical safety data, participate in meetings, write narratives with medical input from a physician, report serious adverse events to the regulatory authorities, participate in the training of operational staff on drug safety issues, quality control work of other staff in the department, and take on any other task as assigned by the manager or medical director within the capabilities of the drug safety associate. There can be challenges while handling all these tasks at a time, hence the associate will have to maintain a balance to overcome them and keep on updating their knowledge on drug safety regulations, which in turn, would help in increasing their learning curve.

  4. Point and track-finding processors for multiwire chambers

    CERN Document Server

    Hansroul, M

    1973-01-01

    The hardware processors described below are designed to be used in conjunction with multi-wire chambers. They have the characteristic of being based on computational methods in contrast to analogue procedures. In a sense, they are hardware implementations of computer programs. But, being specially designed for their purpose, they are free of the restrictions imposed by the architecture of the computer on which the equivalent program is to run. The parallelism inherent in the algorithms can thus be fully exploited. Combined with the use of fast access scratch-pad memories and the non-sequential nature of the control program, the parallelism accounts for the fact that these processors are expected to execute 2-3 orders of magnitude faster than the equivalent Fortran programs on a CDC 7600 or 6600. As a consequence, methods which are simple and straightforward, but which are impractical because they require an exorbitant amount of computer time can on the contrary be very attractive for hardware implementation. ...

  5. Experiences of the use of FOX, an intelligent agent, for programming cochlear implant sound processors in new users.

    Science.gov (United States)

    Vaerenberg, Bart; Govaerts, Paul J; de Ceulaer, Geert; Daemers, Kristin; Schauwers, Karen

    2011-01-01

    This report describes the application of the software tool "Fitting to Outcomes eXpert" (FOX) in programming the cochlear implant (CI) processor in new users. FOX is an intelligent agent to assist in the programming of CI processors. The concept of FOX is to modify maps on the basis of specific outcome measures, achieved using heuristic logic and based on a set of deterministic "rules". A prospective study was conducted on eight consecutive CI-users with a follow-up of three months. Eight adult subjects with postlingual deafness were implanted with the Advanced Bionics HiRes90k device. The implants were programmed using FOX, running a set of rules known as Eargroup's EG0910 advice, which features a set of "automaps". The protocol employed for the initial 3 months is presented, with description of the map modifications generated by FOX and the corresponding psychoacoustic test results. The 3 month median results show 25 dBHL as PTA, 77% (55 dBSPL) and 71% (70 dBSPL) phoneme score at speech audiometry and loudness scaling in or near to the normal zone at different frequencies. It is concluded that this approach is feasible to start up CI fitting and yields good outcome.

  6. Shortcut model for water-balanced operation in fuel processor fuel cell systems

    NARCIS (Netherlands)

    Biesheuvel, P.M.; Kramer, G.J.

    2004-01-01

    In a fuel processor, a hydrocarbon or oxygenate fuel is catalytically converted into a mixture rich in hydrogen which can be fed to a fuel cell to generate electricity. In these fuel processor fuel cell systems (FPFCs), water is recovered from the exhaust gases and recycled back into the system. We

  7. 7 CFR 1435.306 - Allocation of marketing allotments to processors.

    Science.gov (United States)

    2010-01-01

    ... stored beets, as CCC determines, during the 1998 through 2000 crop years. (b) Each sugarcane processor's... affected sugarcane processors and growers by July 15th, to afford all interested persons the opportunity to... of sugar for the production of ethanol or other bioenergy under the Feedstock Flexibility program or...

  8. Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

    Science.gov (United States)

    Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

    2013-03-01

    With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

  9. Run-time Adaptable VLIW Processors : Resources, Performance, Power Consumption, and Reliability Trade-offs

    NARCIS (Netherlands)

    Anjam, F.

    2013-01-01

    In this dissertation, we propose to combine programmability with reconfigurability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor

  10. 27 CFR 31.48 - Alcohol beverage producers, processors, and bonded warehousemen.

    Science.gov (United States)

    2010-04-01

    ... 27 Alcohol, Tobacco Products and Firearms 1 2010-04-01 2010-04-01 false Alcohol beverage producers, processors, and bonded warehousemen. 31.48 Section 31.48 Alcohol, Tobacco Products and Firearms ALCOHOL AND..., processors, and bonded warehousemen. Brewers and proprietors of distilled spirits plants, bonded wine cellars...

  11. 7 CFR 201.73 - Processors and processing of all classes of certified seed.

    Science.gov (United States)

    2010-01-01

    ... seed. 201.73 Section 201.73 Agriculture Regulations of the Department of Agriculture (Continued... (CONTINUED) FEDERAL SEED ACT FEDERAL SEED ACT REGULATIONS Certified Seed § 201.73 Processors and processing of all classes of certified seed. The following requirements must be met by processors of all classes...

  12. A hierarchical, automated target recognition algorithm for a parallel analog processor

    Science.gov (United States)

    Woodward, Gail; Padgett, Curtis

    1997-01-01

    A hierarchical approach is described for an automated target recognition (ATR) system, VIGILANTE, that uses a massively parallel, analog processor (3DANN). The 3DANN processor is capable of performing 64 concurrent inner products of size 1x4096 every 250 nanoseconds.

  13. Space and frequency-multiplexed optical linear algebra processor - Fabrication and initial tests

    Science.gov (United States)

    Casasent, D.; Jackson, J.

    1986-01-01

    A new optical linear algebra processor architecture is described. Space and frequency-multiplexing are used to accommodate bipolar and complex-valued data. A fabricated laboratory version of this processor is described, the electronic support system used is discussed, and initial test data obtained on it are presented.

  14. Text Production in the Foreign Language Classroom and the Word Processor.

    Science.gov (United States)

    Dam, Leni; And Others

    1990-01-01

    Observation of English-as-a-Second-Language students' small-group writing activities involving a word processor found that the word processor was a valuable tool in promoting writing abilities and providing excellent interactional activity. (four references) (Author/CB)

  15. Feasibility analysis of real-time physical modeling using WaveCore processor technology on FPGA

    NARCIS (Netherlands)

    Verstraelen, Martinus Johannes Wilhelmina; Pfeifle, Florian; Bader, Rolf

    2015-01-01

    WaveCore is a scalable many-core processor technology. This technology is specifically developed and optimized for real-time acoustical modeling applications. The programmable WaveCore soft-core processor is silicon-technology independent and hence can be targeted to ASIC or FPGA technologies. The

  16. Two soft-error mitigation techniques for functional units of DSP processors

    NARCIS (Netherlands)

    Rohani, A.; Kerkhoff, Hans G.

    This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been

  17. An architecture of the real-time parallel processor CODA

    Energy Technology Data Exchange (ETDEWEB)

    Nishida, Kenji; Toda, Kenji; Takahashi, Eiichi; Yamaguchi, Yoshinori [Electrotechnical Lab., Tsukuba, Ibaraki (Japan)

    1995-08-01

    The architecture described in this paper supports a wide I/O bandwidth, a high performance computation ability, and a real-time property required for sensor fusion processing. The entire system consists of 64 processing elements connected by multi-stage communication network. The processing element has a hardware task queue to help manage tasks for two execution pipelines (one for executing tasks, and the other for communication). Two pipelines are connected with multi-port register file preventing access contension between pipelines. Therefore, a task can be executed without being interfered by inter-processor communication processing. A register file contains eight context to improve the context switch response. Utilizing hardware features employed for CODA, execution predictability will be improved. (author).

  18. Fault-tolerant interface between quantum memories and quantum processors.

    Science.gov (United States)

    Poulsen Nautrup, Hendrik; Friis, Nicolai; Briegel, Hans J

    2017-11-06

    Topological error correction codes are promising candidates to protect quantum computations from the deteriorating effects of noise. While some codes provide high noise thresholds suitable for robust quantum memories, others allow straightforward gate implementation needed for data processing. To exploit the particular advantages of different topological codes for fault-tolerant quantum computation, it is necessary to be able to switch between them. Here we propose a practical solution, subsystem lattice surgery, which requires only two-body nearest-neighbor interactions in a fixed layout in addition to the indispensable error correction. This method can be used for the fault-tolerant transfer of quantum information between arbitrary topological subsystem codes in two dimensions and beyond. In particular, it can be employed to create a simple interface, a quantum bus, between noise resilient surface code memories and flexible color code processors.

  19. Compressed sensing MRI with multichannel data using multicore processors.

    Science.gov (United States)

    Chang, Ching-Hua; Ji, Jim

    2010-10-01

    Compressed sensing (CS) is a promising method to speed up MRI. Because most clinical MRI scanners are equipped with multichannel receive systems, integrating CS with multichannel systems may not only shorten the scan time but also provide improved image quality. However, significant computation time is required to perform CS reconstruction, whose complexity is scaled by the number of channels. In this article, we propose a reconstruction procedure that uses ubiquitously available multicore central processing unit to accelerate CS reconstruction from multiple channel data. The experimental results show that the reconstruction efficiency benefits significantly from parallelizing the CS reconstructions and pipelining multichannel data into multicore processors. In our experiments, an additional speedup factor of 1.6-2.0 was achieved using the proposed method on a quad-core central processing unit. The proposed method provides a straightforward way to accelerate CS reconstruction with multichannel data for parallel computation.

  20. Scientific Computing on the Itanium® Processor

    Directory of Open Access Journals (Sweden)

    Bruce Greer

    2002-01-01

    Full Text Available The 64-bit Intel® Itanium® architecture is designed for high-performance scientific and enterprise computing, and the Itanium processor is its first silicon implementation. Features such as extensive arithmetic support, predication, speculation, and explicit parallelism can be used to provide a sound infrastructure for supercomputing. A large number of high-performance computer companies are offering Itanium® -based systems, some capable of peak performance exceeding 50 GFLOPS. In this paper we give an overview of the most relevant architectural features and provide illustrations of how these features are used in both low-level and high-level support for scientific and engineering computing, including transcendental functions and linear algebra kernels.

  1. The Associative Memory Boards for the FTK Processor at ATLAS

    CERN Document Server

    Calabro', D; The ATLAS collaboration; Citraro, S; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibena, M

    2013-01-01

    The Associative Memory (AM) system, the main part of the FastTracker (FTK) processor, is designed to perform pattern matching using the information of the silicon tracking detectors of the ATLAS experiment. It finds track candidates at low resolution that are seeds for the following step performing precise track fitting. The system has to support challenging data traffic, handled by a group of modern low-cost FPGAs, the Xilinx Artix 7 chips, which have Low-Power Gigabit Transceivers (GTPs). Each GTP is a combined transmitter and receiver capable of operating at data rates up to 7 Gb/s. The paper reports about the design and the initial tests of the most recent version of the AM system, based on the new AM chip design provided of serialized I/O. An estimation of the power consumption of the final system is also provided and the cooling system design is described. The first cooling tests results are reported.

  2. Deep Trek Re-configurable Processor for Data Acquisition (RPDA)

    Energy Technology Data Exchange (ETDEWEB)

    Bruce Ohme; Michael Johnson

    2009-06-30

    This report summarizes technical progress achieved during the cooperative research agreement between Honeywell and U.S. Department of Energy to develop a high-temperature Re-configurable Processor for Data Acquisition (RPDA). The RPDA development has incorporated multiple high-temperature (225C) electronic components within a compact co-fired ceramic Multi-Chip-Module (MCM) package. This assembly is suitable for use in down-hole oil and gas applications. The RPDA module is programmable to support a wide range of functionality. Specifically this project has demonstrated functional integrity of the RPDA package and internal components, as well as functional integrity of the RPDA configured to operate as a Multi-Channel Data Acquisition Controller. This report reviews the design considerations, electrical hardware design, MCM package design, considerations for manufacturing assembly, test and screening, and results from prototype assembly and characterization testing.

  3. Speeding up the MATLAB complex networks package using graphic processors

    Science.gov (United States)

    Zhang, Bai-Da; Tang, Yu-Hua; Wu, Jun-Jie; Li, Xin

    2011-09-01

    The availability of computers and communication networks allows us to gather and analyse data on a far larger scale than previously. At present, it is believed that statistics is a suitable method to analyse networks with millions, or more, of vertices. The MATLAB language, with its mass of statistical functions, is a good choice to rapidly realize an algorithm prototype of complex networks. The performance of the MATLAB codes can be further improved by using graphic processor units (GPU). This paper presents the strategies and performance of the GPU implementation of a complex networks package, and the Jacket toolbox of MATLAB is used. Compared with some commercially available CPU implementations, GPU can achieve a speedup of, on average, 11.3×. The experimental result proves that the GPU platform combined with the MATLAB language is a good combination for complex network research.

  4. Airborne ocean water lidar (OWL) real time processor (RTP)

    Science.gov (United States)

    Hryszko, M.

    1995-03-01

    The Hyperflo Real Time Processor (RTP) was developed by Pacific-Sierra Research Corporation as a part of the Naval Air Warfare Center's Ocean Water Lidar (OWL) system. The RTP was used for real time support of open ocean field tests at Barbers Point, Hawaii, in March 1993 (EMERALD I field test), and Jacksonville, Florida, in July 1994 (EMERALD I field test). This report describes the system configuration, and accomplishments associated with the preparation and execution of these exercises. This document is intended to supplement the overall test reports and provide insight into the development and use of the PTP. A secondary objective is to provide basic information on the capabilities, versatility and expandability of the Hyperflo RTP for possible future projects. It is assumed herein that the reader has knowledge of the OWL system, field test operations, general lidar processing methods, and basic computer architecture.

  5. Solving Systems of Linear Equations with a Superconducting Quantum Processor.

    Science.gov (United States)

    Zheng, Yarui; Song, Chao; Chen, Ming-Cheng; Xia, Benxiang; Liu, Wuxin; Guo, Qiujiang; Zhang, Libo; Xu, Da; Deng, Hui; Huang, Keqiang; Wu, Yulin; Yan, Zhiguang; Zheng, Dongning; Lu, Li; Pan, Jian-Wei; Wang, H; Lu, Chao-Yang; Zhu, Xiaobo

    2017-05-26

    Superconducting quantum circuits are a promising candidate for building scalable quantum computers. Here, we use a four-qubit superconducting quantum processor to solve a two-dimensional system of linear equations based on a quantum algorithm proposed by Harrow, Hassidim, and Lloyd [Phys. Rev. Lett. 103, 150502 (2009)PRLTAO0031-900710.1103/PhysRevLett.103.150502], which promises an exponential speedup over classical algorithms under certain circumstances. We benchmark the solver with quantum inputs and outputs, and characterize it by nontrace-preserving quantum process tomography, which yields a process fidelity of 0.837±0.006. Our results highlight the potential of superconducting quantum circuits for applications in solving large-scale linear systems, a ubiquitous task in science and engineering.

  6. The data handling processor of the Belle II DEPFET detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Testsuichi; Krueger, Hans; Luetticke, Florian; Marinas, Carlos; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn (Germany); Collaboration: Belle II-Collaboration

    2015-07-01

    A two layer highly granular DEPFET pixel detector will be operated as the innermost subsystem of the Belle II experiment, at the new Japanese super flavor factory (SuperKEKB). Such a finely segmented system will allow to improve the vertex reconstruction in such ultra high luminosity environment but, at the same time, the raw data stream generated by the 8 million pixel detector will exceed the capability of real-time processing due to its high rate. For this reason a new ASIC, the Data Handling Processor (DHP) is designed to provide full functionality of data processing at the level of the front-end electronics and to cover the task of controling the pixel read-out scheme. In this contribution, the description of the latest prototype chip in TSMC 65 nm technology together with the latest test results of the interface functionality are presented.

  7. Small Universal Accepting Networks of Evolutionary Processors with Filtered Connections

    Directory of Open Access Journals (Sweden)

    Remco Loos

    2009-07-01

    Full Text Available In this paper, we present some results regarding the size complexity of Accepting Networks of Evolutionary Processors with Filtered Connections (ANEPFCs. We show that there are universal ANEPFCs of size 10, by devising a method for simulating 2-Tag Systems. This result significantly improves the known upper bound for the size of universal ANEPFCs which is 18. We also propose a new, computationally and descriptionally efficient simulation of nondeterministic Turing machines by ANEPFCs. More precisely, we describe (informally, due to space limitations how ANEPFCs with 16 nodes can simulate in O(f(n time any nondeterministic Turing machine of time complexity f(n. Thus the known upper bound for the number of nodes in a network simulating an arbitrary Turing machine is decreased from 26 to 16.

  8. Directions in parallel processor architecture, and GPUs too

    CERN Multimedia

    CERN. Geneva

    2014-01-01

    Modern computing is power-limited in every domain of computing. Performance increments extracted from instruction-level parallelism (ILP) are no longer power-efficient; they haven't been for some time. Thread-level parallelism (TLP) is a more easily exploited form of parallelism, at the expense of programmer effort to expose it in the program. In this talk, I will introduce you to disparate topics in parallel processor architecture that will impact programming models (and you) in both the near and far future. About the speaker Olivier is a senior GPU (SM) architect at NVIDIA and an active participant in the concurrency working group of the ISO C++ committee. He has also worked on very large diesel engines as a mechanical engineer, and taught at McGill University (Canada) as a faculty instructor.

  9. Modified Acousto-Optic Adaptive Processor (Mod-AOAP)

    Science.gov (United States)

    Keefer, Christopher W.; Malowicki, John E.; Payson, Paul M.

    1992-12-01

    Multipath jamming noise introduced into a radar antenna's sidelobes effectively reduces the radar's target detection capability. The acousto-optic adaptive processor (AOAP) was developed to demonstrate an optical implementation of the least mean square (LMS) algorithm for adaptively cancelling noise jamming. The AOAP system demonstrated 30 dB cancellation of monotone CW signals, with degraded performance as the bandwidth increased. The liquid crystal light valve (LCLV), used as the integrator/ spatial light modulator in the AOAP, has been identified as limiting system performance. In this report we report on modifications to the AOAP. Specifically, the LCLV has been replaced with a photorefractive crystal. Cancellation performance and cancellation speed of the mod-AOAP are presented and compared to the original results.

  10. Fast neural net simulation with a DSP processor array.

    Science.gov (United States)

    Muller, U A; Gunzinger, A; Guggenbuhl, W

    1995-01-01

    This paper describes the implementation of a fast neural net simulator on a novel parallel distributed-memory computer. A 60-processor system, named MUSIC (multiprocessor system with intelligent communication), is operational and runs the backpropagation algorithm at a speed of 330 million connection updates per second (continuous weight update) using 32-b floating-point precision. This is equal to 1.4 Gflops sustained performance. The complete system with 3.8 Gflops peak performance consumes less than 800 W of electrical power and fits into a 19-in rack. While reaching the speed of modern supercomputers, MUSIC still can be used as a personal desktop computer at a researcher's own disposal. In neural net simulation, this gives a computing performance to a single user which was unthinkable before. The system's real-time interfaces make it especially useful for embedded applications.

  11. Optimization of the Continuous Wavelet Transform for DSP Processor Implementation.

    Science.gov (United States)

    Patil, Sunil; Abel, E

    2005-01-01

    The redundant wavelet transform is an effective tool when emphasis is on the analysis of non-stationary signals and on localization and characterization of singularities. Here we describe an optimized method to implement a B-spline based redundant wavelet transform (RWT) on a Digital Signal Processor (DSP) for integer scales. Expressions are derived to give an exact operation count at any integer scale m for any B-spline of order n. Finally experimental results are given using cubic b-spline as scaling function and first-and second-order derivative of B-splines as wavelets. It has been shown that optimized method improves the execution speed over the standard method by 20-28%.

  12. An online emission spectral tomography system with digital signal processor.

    Science.gov (United States)

    Wan, Xiong; Xiong, Wenlin; Zhang, Zhimin; Chang, Fangfei

    2009-03-30

    Emission spectral tomography (EST) has been adopted to test the three-dimensional distribution parameters of fluid fields, such as burning gas, flame and plasma etc. In most cases, emission spectral data received by the video cameras are enormous so that the emission spectral tomography calculation is often time-consuming. Hence, accelerating calculation becomes the chief factor that one must consider for the practical application of EST. To solve the problem, a hardware implementation method was proposed in this paper, which adopted a digital signal processor (DSP) DM642 in an emission spectral tomography test system. The EST algorithm was fulfilled in the DSP, then calculation results were transmitted to the main computer via the user datagram protocol. Compared with purely VC++ software implementations, this new approach can decrease the calculation time significantly.

  13. Energy efficient image/video data transmission on commercial multi-core processors.

    Science.gov (United States)

    Lee, Sungju; Kim, Heegon; Chung, Yongwha; Park, Daihee

    2012-11-01

    In transmitting image/video data over Video Sensor Networks (VSNs), energy consumption must be minimized while maintaining high image/video quality. Although image/video compression is well known for its efficiency and usefulness in VSNs, the excessive costs associated with encoding computation and complexity still hinder its adoption for practical use. However, it is anticipated that high-performance handheld multi-core devices will be used as VSN processing nodes in the near future. In this paper, we propose a way to improve the energy efficiency of image and video compression with multi-core processors while maintaining the image/video quality. We improve the compression efficiency at the algorithmic level or derive the optimal parameters for the combination of a machine and compression based on the tradeoff between the energy consumption and the image/video quality. Based on experimental results, we confirm that the proposed approach can improve the energy efficiency of the straightforward approach by a factor of 2~5 without compromising image/video quality.

  14. Performance analysis of general purpose and digital signal processor kernels for heterogeneous systems-on-chip

    Directory of Open Access Journals (Sweden)

    T. von Sydow

    2003-01-01

    Full Text Available Various reasons like technology progress, flexibility demands, shortened product cycle time and shortened time to market have brought up the possibility and necessity to integrate different architecture blocks on one heterogeneous System-on-Chip (SoC. Architecture blocks like programmable processor cores (DSP- and GPP-kernels, embedded FPGAs as well as dedicated macros will be integral parts of such a SoC. Especially programmable architecture blocks and associated optimization techniques are discussed in this contribution. Design space exploration and thus the choice which architecture blocks should be integrated in a SoC is a challenging task. Crucial to this exploration is the evaluation of the application domain characteristics and the costs caused by individual architecture blocks integrated on a SoC. An ATE-cost function has been applied to examine the performance of the aforementioned programmable architecture blocks. Therefore, representative discrete devices have been analyzed. Furthermore, several architecture dependent optimization steps and their effects on the cost ratios are presented.

  15. Case Study of Using High Performance Commercial Processors in Space

    Science.gov (United States)

    Ferguson, Roscoe C.; Olivas, Zulema

    2009-01-01

    The purpose of the Space Shuttle Cockpit Avionics Upgrade project (1999 2004) was to reduce crew workload and improve situational awareness. The upgrade was to augment the Shuttle avionics system with new hardware and software. A major success of this project was the validation of the hardware architecture and software design. This was significant because the project incorporated new technology and approaches for the development of human rated space software. An early version of this system was tested at the Johnson Space Center for one month by teams of astronauts. The results were positive, but NASA eventually cancelled the project towards the end of the development cycle. The goal to reduce crew workload and improve situational awareness resulted in the need for high performance Central Processing Units (CPUs). The choice of CPU selected was the PowerPC family, which is a reduced instruction set computer (RISC) known for its high performance. However, the requirement for radiation tolerance resulted in the re-evaluation of the selected family member of the PowerPC line. Radiation testing revealed that the original selected processor (PowerPC 7400) was too soft to meet mission objectives and an effort was established to perform trade studies and performance testing to determine a feasible candidate. At that time, the PowerPC RAD750s were radiation tolerant, but did not meet the required performance needs of the project. Thus, the final solution was to select the PowerPC 7455. This processor did not have a radiation tolerant version, but had some ability to detect failures. However, its cache tags did not provide parity and thus the project incorporated a software strategy to detect radiation failures. The strategy was to incorporate dual paths for software generating commands to the legacy Space Shuttle avionics to prevent failures due to the softness of the upgraded avionics.

  16. Onboard Data Processors for Planetary Ice-Penetrating Sounding Radars

    Science.gov (United States)

    Tan, I. L.; Friesenhahn, R.; Gim, Y.; Wu, X.; Jordan, R.; Wang, C.; Clark, D.; Le, M.; Hand, K. P.; Plaut, J. J.

    2011-12-01

    Among the many concerns faced by outer planetary missions, science data storage and transmission hold special significance. Such missions must contend with limited onboard storage, brief data downlink windows, and low downlink bandwidths. A potential solution to these issues lies in employing onboard data processors (OBPs) to convert raw data into products that are smaller and closely capture relevant scientific phenomena. In this paper, we present the implementation of two OBP architectures for ice-penetrating sounding radars tasked with exploring Europa and Ganymede. Our first architecture utilizes an unfocused processing algorithm extended from the Mars Advanced Radar for Subsurface and Ionosphere Sounding (MARSIS, Jordan et. al. 2009). Compared to downlinking raw data, we are able to reduce data volume by approximately 100 times through OBP usage. To ensure the viability of our approach, we have implemented, simulated, and synthesized this architecture using both VHDL and Matlab models (with fixed-point and floating-point arithmetic) in conjunction with Modelsim. Creation of a VHDL model of our processor is the principle step in transitioning to actual digital hardware, whether in a FPGA (field-programmable gate array) or an ASIC (application-specific integrated circuit), and successful simulation and synthesis strongly indicate feasibility. In addition, we examined the tradeoffs faced in the OBP between fixed-point accuracy, resource consumption, and data product fidelity. Our second architecture is based upon a focused fast back projection (FBP) algorithm that requires a modest amount of computing power and on-board memory while yielding high along-track resolution and improved slope detection capability. We present an overview of the algorithm and details of our implementation, also in VHDL. With the appropriate tradeoffs, the use of OBPs can significantly reduce data downlink requirements without sacrificing data product fidelity. Through the development

  17. 77 FR 9589 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using...

    Science.gov (United States)

    2012-02-17

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Trawl Gear in the Western Regulatory Area... directed fishing for Pacific cod by catcher/processors (C/Ps) using trawl gear in the Western Regulatory...

  18. 78 FR 54592 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using...

    Science.gov (United States)

    2013-09-05

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Trawl Gear in the Central Regulatory Area... directed fishing for Pacific cod by catcher/processors (C/Ps) using trawl gear in the Central Regulatory...

  19. 78 FR 23683 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using...

    Science.gov (United States)

    2013-04-22

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Trawl Gear in the Central Regulatory Area... directed fishing for Pacific cod by catcher/processors (C/Ps) using trawl gear in the Central Regulatory...

  20. 78 FR 4346 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using...

    Science.gov (United States)

    2013-01-22

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Trawl Gear in the Western Regulatory Area... directed fishing for Pacific cod by catcher/processors (C/Ps) using trawl gear in the Western Regulatory...

  1. 77 FR 54837 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using...

    Science.gov (United States)

    2012-09-06

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Trawl Gear in the Western Regulatory Area... directed fishing for Pacific cod by catcher/processors (C/Ps) using trawl gear in the Western Regulatory...

  2. 77 FR 21683 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/processors Using...

    Science.gov (United States)

    2012-04-11

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/processors Using Trawl Gear in the Central Regulatory Area... directed fishing for Pacific cod by catcher/processors (C/Ps) using trawl gear in the Central Regulatory...

  3. 78 FR 23864 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Hook...

    Science.gov (United States)

    2013-04-23

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Hook-and-line Gear in the Western... directed fishing for Pacific cod by catcher/processors (C/Ps) using hook-and-line gear in the Western...

  4. 77 FR 11776 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Hook...

    Science.gov (United States)

    2012-02-28

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Hook-and-Line Gear in the Central... directed fishing for Pacific cod by catcher/processors (C/Ps) using hook-and-line gear in the Central...

  5. Programmable optical processor chips: toward photonic RF filters with DSP-level flexibility and MHz-band selectivity

    NARCIS (Netherlands)

    Xie, Yiwei; Geng, Zihan; Zhuang, Leimeng; Burla, M.; Taddei, Caterina; Hoekman, M.; Leinse, Arne; Roeloffzen, C.G.H.; Boller, Klaus J.; Lowery, C.J.

    2017-01-01

    Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic

  6. Optical links in handheld multimedia devices

    Science.gov (United States)

    van Geffen, S.; Duis, J.; Miller, R.

    2008-04-01

    Ever emerging applications in handheld multimedia devices such as mobile phones, laptop computers, portable video games and digital cameras requiring increased screen resolutions are driving higher aggregate bitrates between host processor and display(s) enabling services such as mobile video conferencing, video on demand and TV broadcasting. Larger displays and smaller phones require complex mechanical 3D hinge configurations striving to combine maximum functionality with compact building volumes. Conventional galvanic interconnections such as Micro-Coax and FPC carrying parallel digital data between host processor and display module may produce Electromagnetic Interference (EMI) and bandwidth limitations caused by small cable size and tight cable bends. To reduce the number of signals through a hinge, the mobile phone industry, organized in the MIPI (Mobile Industry Processor Interface) alliance, is currently defining an electrical interface transmitting serialized digital data at speeds >1Gbps. This interface allows for electrical or optical interconnects. Above 1Gbps optical links may offer a cost effective alternative because of their flexibility, increased bandwidth and immunity to EMI. This paper describes the development of optical links for handheld communication devices. A cable assembly based on a special Plastic Optical Fiber (POF) selected for its mechanical durability is terminated with a small form factor molded lens assembly which interfaces between an 850nm VCSEL transmitter and a receiving device on the printed circuit board of the display module. A statistical approach based on a Lean Design For Six Sigma (LDFSS) roadmap for new product development tries to find an optimum link definition which will be robust and low cost meeting the power consumption requirements appropriate for battery operated systems.

  7. Framework for utilizing computational devices within simulation

    Directory of Open Access Journals (Sweden)

    Miroslav Mintál

    2013-12-01

    Full Text Available Nowadays there exist several frameworks to utilize a computation power of graphics cards and other computational devices such as FPGA, ARM and multi-core processors. The best known are either low-level and need a lot of controlling code or are bounded only to special graphic cards. Furthermore there exist more specialized frameworks, mainly aimed to the mathematic field. Described framework is adjusted to use in a multi-agent simulations. Here it provides an option to accelerate computations when preparing simulation and mainly to accelerate a computation of simulation itself.

  8. 77 FR 3638 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

    Science.gov (United States)

    2012-01-25

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian... for Pacific cod by pot catcher/processors in the Bering Sea and Aleutian Islands management area (BSAI... allowable catch (TAC) specified for pot catcher/processors in the BSAI. DATES: Effective 1200 hrs, Alaska...

  9. 76 FR 4552 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

    Science.gov (United States)

    2011-01-26

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian... for Pacific cod by pot catcher/processors in the Bering Sea and Aleutian Islands management area (BSAI... allowable catch (TAC) specified for pot catcher/processors in the BSAI. DATES: Effective 1200 hrs, Alaska...

  10. 75 FR 59157 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

    Science.gov (United States)

    2010-09-27

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian... for Pacific cod by pot catcher/processors in the Bering Sea and Aleutian Islands management area (BSAI...) specified for pot catcher/ processors in the BSAI. DATES: Effective 1200 hrs, Alaska local time (A.l.t...

  11. 76 FR 43934 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Ocean Perch for Catcher/Processors...

    Science.gov (United States)

    2011-07-22

    ... Economic Zone Off Alaska; Pacific Ocean Perch for Catcher/Processors Participating in the Rockfish Limited...; closure. SUMMARY: NMFS is prohibiting directed fishing for Pacific ocean perch by catcher/processors... perch allocated to catcher/processors participating in the rockfish limited access fishery in the...

  12. 40 CFR 279.41 - Restrictions on transporters who are not also processors or re-refiners.

    Science.gov (United States)

    2010-07-01

    ... not also processors or re-refiners. 279.41 Section 279.41 Protection of Environment ENVIRONMENTAL... processors or re-refiners. (a) Used oil transporters may consolidate or aggregate loads of used oil for... transporters may not process used oil unless they also comply with the requirements for processors/re-refiners...

  13. 76 FR 66195 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

    Science.gov (United States)

    2011-10-26

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian... for Pacific cod by pot catcher/processors in the Bering Sea and Aleutian Islands management area (BSAI...) specified for pot catcher/ processors in the BSAI. DATES: Effective 1200 hrs, Alaska local time (A.l.t...

  14. 75 FR 42337 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Ocean Perch for Catcher/Processors...

    Science.gov (United States)

    2010-07-21

    ... Economic Zone Off Alaska; Pacific Ocean Perch for Catcher/Processors Participating in the Rockfish Limited...; closure. SUMMARY: NMFS is prohibiting directed fishing for Pacific ocean perch by catcher/processors... perch allocated to catcher/processors participating in the rockfish limited access fishery in the...

  15. 78 FR 7280 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

    Science.gov (United States)

    2013-02-01

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian... for Pacific cod by pot catcher/processors in the Bering Sea and Aleutian Islands management area (BSAI... allowable catch (TAC) specified for pot catcher/processors in the BSAI. DATES: Effective 1200 hrs, Alaska...

  16. 75 FR 7403 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Hook...

    Science.gov (United States)

    2010-02-19

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Hook-and-Line Gear in the Bering Sea and... directed fishing for Pacific cod by catcher/processors using hook-and-line gear in the Bering Sea and... allowance of the 2010 Pacific cod total allowable catch (TAC) allocated to catcher/processors using hook-and...

  17. 75 FR 42336 - Fisheries of the Exclusive Economic Zone Off Alaska; Northern Rockfish for Catcher/Processors...

    Science.gov (United States)

    2010-07-21

    ... Economic Zone Off Alaska; Northern Rockfish for Catcher/Processors Participating in the Rockfish Limited...; closure. SUMMARY: NMFS is prohibiting directed fishing for northern rockfish by catcher/processors... allocated to catcher/processors participating in the rockfish limited access fishery in the Central...

  18. 76 FR 44283 - Fisheries of the Exclusive Economic Zone Off Alaska; Northern Rockfish for Catcher/Processors...

    Science.gov (United States)

    2011-07-25

    ... Economic Zone Off Alaska; Northern Rockfish for Catcher/Processors Participating in the Rockfish Limited...; closure. SUMMARY: NMFS is prohibiting directed fishing for northern rockfish by catcher/processors... allocated to catcher/ processors participating in the rockfish limited access fishery in the Central...

  19. 75 FR 8840 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

    Science.gov (United States)

    2010-02-26

    ... Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian... for Pacific cod by pot catcher/processors in the Bering Sea and Aleutian Islands management area (BSAI... allowable catch (TAC) specified for pot catcher/processors in the BSAI. DATES: Effective 1200 hrs, Alaska...

  20. 17 CFR 249.1001 - Form SIP, for application for registration as a securities information processor or to amend such...

    Science.gov (United States)

    2010-04-01

    ... registration as a securities information processor or to amend such an application or registration. 249.1001..., SECURITIES EXCHANGE ACT OF 1934 Form for Registration of, and Reporting by Securities Information Processors § 249.1001 Form SIP, for application for registration as a securities information processor or to amend...

  1. 50 CFR 600.1106 - Longline catcher processor subsector Bering Sea and Aleutian Islands (BSAI) non-pollock...

    Science.gov (United States)

    2010-10-01

    ... 50 Wildlife and Fisheries 8 2010-10-01 2010-10-01 false Longline catcher processor subsector... Fishery or Program Fishing Capacity Reduction Regulations § 600.1106 Longline catcher processor subsector... longline catcher processor subsector of the BSAI non-pollock groundfish fishery that § 679.2 of this...

  2. Formulation of detailed consumables management models for the development (preoperational) period of advanced space transportation system. Volume 5: Flight operations processor requirements

    Science.gov (United States)

    Zamora, M. A.

    1976-01-01

    The functional requirements for the Flight Operations Processor are defined. The Flight Operations Processor is that element of the Consumables Management System providing support during the flight operations.

  3. Ferroelectric devices

    CERN Document Server

    Uchino, Kenji

    2009-01-01

    Updating its bestselling predecessor, Ferroelectric Devices, Second Edition assesses the last decade of developments-and setbacks-in the commercialization of ferroelectricity. Field pioneer and esteemed author Uchino provides insight into why this relatively nascent and interdisciplinary process has failed so far without a systematic accumulation of fundamental knowledge regarding materials and device development.Filling the informational void, this collection of information reviews state-of-the-art research and development trends reflecting nano and optical technologies, environmental regulat

  4. Catalytic devices

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Ming; Zhang, Xiang

    2018-01-23

    This disclosure provides systems, methods, and apparatus related to catalytic devices. In one aspect, a device includes a substrate, an electrically insulating layer disposed on the substrate, a layer of material disposed on the electrically insulating layer, and a catalyst disposed on the layer of material. The substrate comprises an electrically conductive material. The substrate and the layer of material are electrically coupled to one another and configured to have a voltage applied across them.

  5. Recovery Act: Integrated DC-DC Conversion for Energy-Efficient Multicore Processors

    Energy Technology Data Exchange (ETDEWEB)

    Shepard, Kenneth L

    2013-03-31

    devices. These new approaches to scaled voltage regulation for computing devices also promise significant impact on electricity consumption in the United States and abroad by improving the efficiency of all computational platforms. In 2006, servers and datacenters in the United States consumed an estimated 61 billion kWh or about 1.5% of the nation's total energy consumption. Federal Government servers and data centers alone accounted for about 10 billion kWh, for a total annual energy cost of about $450 million. Based upon market growth and efficiency trends, estimates place current server and datacenter power consumption at nearly 85 billion kWh in the US and at almost 280 billion kWh worldwide. Similar estimates place national desktop, mobile and portable computing at 80 billion kWh combined. While national electricity utilization for computation amounts to only 4% of current usage, it is growing at a rate of about 10% a year with volume servers representing one of the largest growth segments due to the increasing utilization of cloud-based services. The percentage of power that is consumed by the processor in a server varies but can be as much as 30% of the total power utilization, with an additional 50% associated with heat removal. The approaches considered here should allow energy efficiency gains as high as 30% in processors for all computing platforms, from high-end servers to smart phones, resulting in a direct annual energy savings of almost 15 billion kWh nationally, and 50 billion kWh globally. The work developed here is being commercialized by the start-up venture, Ferric Semiconductor, which has already secured two Phase I SBIR grants to bring these technologies to the marketplace.

  6. Benefits from upgrade to the CP810 sound processor for Nucleus 24 cochlear implant recipients.

    Science.gov (United States)

    Mosnier, Isabelle; Marx, Mathieu; Venail, Frederic; Loundon, Natalie; Roux-Vaillard, Samantha; Sterkers, Olivier

    2014-01-01

    The objective of this study was to measure performance benefits obtained by upgrading recipients of the Cochlear Nucleus CI24 cochlear implant to the new CP810 sound processor. Speech recognition in quiet and in spatially separated noise was measured in established users of the Cochlear ESPrit 3G (n = 22) and Freedom (n = 13) sound processors, using the "Everyday" listening program. Subjects were then upgraded to the CP810 processor and were re-assessed after a 3-month period, using both the "Everyday" program and the new "Noise" program, which incorporates several pre-processing features including a new directional microphone algorithm ("Zoom"). Subjective perceptions were also recorded using the abbreviated profile of hearing aid benefit (APHAB) questionnaire. Mean scores for monosyllables in quiet, presented at 50 and 60 dB SPL, increased by 11% (p processor groups. In noise, the mean scores were 60.0 and 67.4% for the original and CP810 Everyday programs, respectively (difference not significant). With the CP810 Noise programs the mean score increased to 82.5% (p processor groups. There was evidence of slightly greater upgrade benefit in users of the ESPrit 3G processor and in relatively poor performers. The APHAB questionnaire also indicated significant reduction in perceived difficulty in the background noise and reverberation sub-scales after upgrade. The findings of the study appear to support the expectation of increased benefit from the new CP810 sound processor.

  7. Survey of cochlear implant user satisfaction with the Neptune™ waterproof sound processor

    Directory of Open Access Journals (Sweden)

    Jeroen J. Briaire

    2016-04-01

    Full Text Available A multi-center self-assessment survey was conducted to evaluate patient satisfaction with the Advanced Bionics Neptune™ waterproof sound processor used with the AquaMic™ totally submersible microphone. Subjective satisfaction with the different Neptune™ wearing options, comfort, ease of use, sound quality and use of the processor in a range of active and water related situations were assessed for 23 adults and 73 children, using an online and paper based questionnaire. Upgraded subjects compared their previous processor to the Neptune™. The Neptune™ was most popular for use in general sports and in the pool. Subjects were satisfied with the sound quality of the sound processor outside and under water and following submersion. Seventyeight percent of subjects rated waterproofness as being very useful and 83% of the newly implanted subjects selected waterproofness as one of the reasons why they chose the Neptune™ processor. Providing a waterproof sound processor is considered by cochlear implant recipients to be useful and important and is a factor in their processor choice. Subjects reported that they were satisfied with the Neptune™ sound quality, ease of use and different wearing options.

  8. FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

  9. Benefits of Adaptive Signal Processing in a Commercially Available Cochlear Implant Sound Processor.

    Science.gov (United States)

    Wolfe, Jace; Neumann, Sara; Marsh, Megan; Schafer, Erin; Lianos, Leslie; Gilden, Jan; O'Neill, Lori; Arkis, Pete; Menapace, Christine; Nel, Esti; Jones, Marian

    2015-08-01

    Cochlear implant recipients often experience difficulty understanding speech in noise. The primary objective of this study was to evaluate the potential improvement in speech recognition in noise provided by an adaptive, commercially available sound processor that performs acoustic scene classification and automatically adjusts input signal processing to maximize performance in noise. Within-subjects, repeated-measures design. This multicenter study was conducted across five sites in the U.S.A. and Australia. Ninety-three adults and children with Nucleus Freedom, CI422, and CI512 cochlear implants. Subjects (previous users of the Nucleus 5 sound processor) were fitted with the Nucleus 6 sound processor. Performance was assessed while these subjects used each sound processor in the manufacturer's recommended default program (standard directionality, ASC + ADRO for the Nucleus 5 processor and ASC + ADRO and SNR-NR with SCAN for the Nucleus 6 sound processor). The subjects were also evaluated with the Nucleus 6 with standard directionality, ASC + ADRO and SNR-NR enabled but SCAN disabled. Speech recognition in noise was assessed with AzBio sentences. Sentence recognition in noise was significantly better with the Nucleus 6 sound processor when used with the default input processing (ASC + ADRO, SNR-NR, and SCAN) compared to performance with the Nucleus 5 sound processor and default input processing (standard directionality, ASC + ADRO). Specifically, use of the Nucleus 6 at default settings resulted in a mean improvement in sentence recognition in noise of 27 percentage points relative to performance with the Nucleus 5 sound processor. Use of the Nucleus 6 sound processor using standard directionality, ASC + ADRO and SNR-NR (SCAN disabled) resulted in a mean improvement of 9 percentage points in sentence recognition in noise compared to performance with the Nucleus 5. The results of this study suggest that the Nucleus 6 sound processor with acoustic scene

  10. Real-Time Power Management for a Multi-Performance Processor

    OpenAIRE

    Ishihara, Tohru

    2009-01-01

    This paper presents an energy efficient embedded processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded real-time system design. The processor consists of multiple same-ISA PE (processing element) cores and a selective set-associative cache memory. The PE-cores differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating. T...

  11. Tinuso: A processor architecture for a multi-core hardware simulation platform

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; Karlsson, Sven

    2010-01-01

    accurate hardware simulation platform. We have developed the Tinuso processor architecture for this platform. Tinuso is a processor architecture optimized for FPGA implementation. The instruction set makes use of predicated instructions and supports C/C++ and assembly language programming. It is designed...... to be easy extendable to maintain the exibility required for the research on multi-core systems. Tinuso contains a co-processor interface to connect to a network interface. This interface allow for communication over an on-chip network. A clock frequency estimation study on a deeply pipelined Tinuso...

  12. The Potential of the Cell Processor for Scientific Computing

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Samuel; Shalf, John; Oliker, Leonid; Husbands, Parry; Kamil, Shoaib; Yelick, Katherine

    2005-10-14

    The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of the using the forth coming STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. We are the first to present quantitative Cell performance data on scientific kernels and show direct comparisons against leading superscalar (AMD Opteron), VLIW (IntelItanium2), and vector (Cray X1) architectures. Since neither Cell hardware nor cycle-accurate simulators are currently publicly available, we develop both analytical models and simulators to predict kernel performance. Our work also explores the complexity of mapping several important scientific algorithms onto the Cells unique architecture. Additionally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

  13. Concurrent and Accurate Short Read Mapping on Multicore Processors.

    Science.gov (United States)

    Martínez, Héctor; Tárraga, Joaquín; Medina, Ignacio; Barrachina, Sergio; Castillo, Maribel; Dopazo, Joaquín; Quintana-Ortí, Enrique S

    2015-01-01

    We introduce a parallel aligner with a work-flow organization for fast and accurate mapping of RNA sequences on servers equipped with multicore processors. Our software, HPG Aligner SA (HPG Aligner SA is an open-source application. The software is available at http://www.opencb.org, exploits a suffix array to rapidly map a large fraction of the RNA fragments (reads), as well as leverages the accuracy of the Smith-Waterman algorithm to deal with conflictive reads. The aligner is enhanced with a careful strategy to detect splice junctions based on an adaptive division of RNA reads into small segments (or seeds), which are then mapped onto a number of candidate alignment locations, providing crucial information for the successful alignment of the complete reads. The experimental results on a platform with Intel multicore technology report the parallel performance of HPG Aligner SA, on RNA reads of 100-400 nucleotides, which excels in execution time/sensitivity to state-of-the-art aligners such as TopHat 2+Bowtie 2, MapSplice, and STAR.

  14. Transporters as information processors in bacterial signalling pathways.

    Science.gov (United States)

    Piepenbreier, Hannah; Fritz, Georg; Gebhard, Susanne

    2017-04-01

    Transporters are essential players in bacterial growth and survival, since they are key for uptake of nutrients on the one hand, and for defence against endogenous and environmental stresses on the other hand. Remarkably, in addition to their primary role in substrate translocation, it has become clear that some transporters have acquired a secondary function as sensors and information processors in signalling pathways. In this review, we describe recent advances in our understanding of the role of transporters in such signalling cascades, and discuss some of the emergent dynamic behaviour found in hallmark examples. A particular focus is placed on new insights into mechanistic details of information transfer between transporters and regulatory proteins. Quantitative considerations reveal that these signalling complexes can implement a remarkable diversity of regulatory logic functions, where the transporter can act as activity switch, as positive or negative reporter of transport flux, or as a signalling hub for the integration of multiple inputs. Such a dual use of transport proteins not only enables efficient substrate translocation but is also an elegant strategy to integrate important information about the cell's external conditions with its current physiological state. © 2017 John Wiley & Sons Ltd.

  15. Virtual Modular Redundancy of Processor Module in the PLC

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Kwang-Il; Hwang, SungJae; Yoon, DongHwa [SOOSAN ENS Co., Seoul (Korea, Republic of)

    2016-10-15

    Dual Modular Redundancy (DMR) is mainly used to implement these safety control systems. DMR is conveyed when components of a system are duplicated, providing another component in case one should fault or fail. This feature has a high availability and large fault tolerant. It provides zero downtime that is required for nuclear power plants. So nuclear power plant has been commercialized by multiple redundant systems. The following paper, we propose a Virtual Modular Redundancy (VMR) rather than physical triple of the Programmable Logic Controller (PLC) processor module to ensure the reliability of the nuclear power plant control system. VMR implementation minimizes design changes to continue to use the commercially available redundant system. Also, the purpose of the VMR is to improve the efficiency and reliability in many ways, such as fault tolerant and fail-safe and cost. VMR guarantees a wide range of reliable fault recovery, fault tolerance, etc. It is prevented before it causes great damages due to the continuous failure of the two modules. The reliable communication speed is slow and also it has a small bandwidth. It is a great loss in the safety control system. However, VMR aims to avoid nuclear power plants that were suspended due to fail-safe. It is not for the purpose of commonly used. Application of VMR is actually expected to require a lot of research and trial and error until they adapt to the nuclear regulatory and standards.

  16. Performance Evaluation of the ISS Water Processor Multifiltration Beds

    Science.gov (United States)

    Bowman, Elizabeth M.; Carter, Layne; Wilson, Mark; Cole, Harold; Orozco, Nicole; Snowdon, Doug

    2012-01-01

    The ISS Water Processor Assembly (WPA) produces potable water from a waste stream containing humidity condensate and urine distillate. The primary treatment process is achieved in the Multifiltration Bed, which includes adsorbent media and ion exchange resin for the removal of dissolved organic and inorganic contaminants. The first Multifiltration Bed was replaced on ISS in July 2010 after initial indication of inorganic breakthrough. This bed was returned to ground in July 2011 for an engineering investigation. The water resident in the bed was analyzed for various parameters to evaluate adsorbent loading, performance of the ion exchange resin, microbial activity, and generation of leachates from the ion exchange resin. Portions of the adsorbent media and ion exchange resin were sampled and subsequently desorbed to identify the primary contaminants removed at various points in the bed. In addition, an unused Multifiltration Bed was evaluated after two years in storage to assess the generation of leachates during storage. This assessment was performed to evaluate the possibility that these leachates are impacting performance of the Catalytic Reactor located downstream of the Multifiltration Bed. The results of these investigations and implications to the operation of the WPA on ISS are documented in this paper.

  17. Updated Performance Evaluation of the ISS Water Processor Multifiltration Beds

    Science.gov (United States)

    Bowman, Elizabeth M.; Carter, Layne; Carpenter, Joyce; Orozco, Nicole; Weir, Natalee; Wilson, Mark

    2014-01-01

    The ISS Water Processor Assembly (WPA) produces potable water from a waste stream containing humidity condensate and urine distillate. The primary treatment process is achieved in the Multifiltration Beds, which include adsorbent media and ion exchange resin for the removal of dissolved organic and inorganic contaminants. Two Multifiltration Beds (MF Beds) were replaced on ISS in July 2010 after initial indication of inorganic breakthrough of the first bed and an increasing Total Organic Carbon (TOC) trend in the product water. The first bed was sampled and analyzed Sept 2011 through March 2012. The second MF Bed was sampled and analyzed June 2012 through August 2012. The water resident in the both beds was analyzed for various parameters to evaluate adsorbent loading, performance of the ion exchange resin, microbial activity, and generation of leachates from the ion exchange resin. Portions of the adsorbent media and ion exchange resin were sampled and subsequently desorbed to identify the primary contaminants removed at various points in the bed in addition to microbial analysis. Analysis of the second bed will be compared to results from the first bed to provide a comprehensive overview of how the Multifiltration Beds function on orbit. New data from the second bed supplements the analysis of the first bed (previously reported) and gives a more complete picture of breakthrough compounds, resin breakdown products, microbial activity, and difficult to remove compounds. The results of these investigations and implications to the operation of the WPA on ISS are documented in this paper.

  18. Real time continuous wavelet transform implementation on a DSP processor.

    Science.gov (United States)

    Patil, S; Abel, E W

    2009-01-01

    The continuous wavelet transform (CWT) is an effective tool when the emphasis is on the analysis of non-stationary signals and on localization and characterization of singularities in signals. We have used the B-spline based CWT, the Lipschitz Exponent (LE) and measures derived from it to detect and quantify the singularity characteristics of biomedical signals. In this article, a real-time implementation of a B-spline based CWT on a digital signal processor is presented, with the aim of providing quantitative information about the signal to a clinician as it is being recorded. A recursive algorithm implementation was shown to be too slow for real-time implementation so a parallel algorithm was considered. The use of a parallel algorithm involves redundancy in calculations at the boundary points. An optimization of numerical computation to remove redundancy in calculation was carried out. A formula has been derived to give an exact operation count for any integer scale m and any B-spline of order n (for the case where n is odd) to calculate the CWT for both the original and the optimized parallel methods. Experimental results show that the optimized method is 20-28% faster than the original method. As an example of applying this optimized method, a real-time implementation of the CWT with LE postprocessing has been achieved for an EMG Interference Pattern signal sampled at 50 kHz.

  19. An Optical Tomography System Using a Digital Signal Processor.

    Science.gov (United States)

    Rahim, Ruzairi Abdul; Thiam, Chiam Kok; Rahiman, Mohd Hafiz Fazalul

    2008-03-27

    The use of a personal computer together with a Data Acquisition System (DAQ) as the processing tool in optical tomography systems has been the norm ever since the beginning of process tomography. However, advancements in silicon fabrication technology allow nowadays the fabrication of powerful Digital Signal Processors (DSP) at a reasonable cost. This allows this technology to be used in an optical tomography system since data acquisition and processing can be performed within the DSP. Thus, the dependency on a personal computer and a DAQ to sample and process the external signals can be reduced or even eliminated. The DSP system was customized to control the data acquisition process of 16x16 optical sensor array, arranged in parallel beam projection. The data collected was used to reconstruct the cross sectional image of the pipeline conveyor. For image display purposes, the reconstructed image was sent to a personal computer via serial communication. This allows the use of a laptop to display the tomogram image besides performing any other offline analysis.

  20. On program restructuring, scheduling, and communication for parallel processor systems

    Energy Technology Data Exchange (ETDEWEB)

    Polychronopoulos, Constantine D. [Univ. of Illinois, Urbana, IL (United States)

    1986-08-01

    This dissertation discusses several software and hardware aspects of program execution on large-scale, high-performance parallel processor systems. The issues covered are program restructuring, partitioning, scheduling and interprocessor communication, synchronization, and hardware design issues of specialized units. All this work was performed focusing on a single goal: to maximize program speedup, or equivalently, to minimize parallel execution time. Parafrase, a Fortran restructuring compiler was used to transform programs in a parallel form and conduct experiments. Two new program restructuring techniques are presented, loop coalescing and subscript blocking. Compile-time and run-time scheduling schemes are covered extensively. Depending on the program construct, these algorithms generate optimal or near-optimal schedules. For the case of arbitrarily nested hybrid loops, two optimal scheduling algorithms for dynamic and static scheduling are presented. Simulation results are given for a new dynamic scheduling algorithm. The performance of this algorithm is compared to that of self-scheduling. Techniques for program partitioning and minimization of interprocessor communication for idealized program models and for real Fortran programs are also discussed. The close relationship between scheduling, interprocessor communication, and synchronization becomes apparent at several points in this work. Finally, the impact of various types of overhead on program speedup and experimental results are presented.

  1. Multi-threaded ATLAS simulation on Intel Knights Landing processors

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00014247; The ATLAS collaboration; Calafiura, Paolo; Leggett, Charles; Tsulaia, Vakhtang; Dotti, Andrea

    2017-01-01

    The Knights Landing (KNL) release of the Intel Many Integrated Core (MIC) Xeon Phi line of processors is a potential game changer for HEP computing. With 72 cores and deep vector registers, the KNL cards promise significant performance benefits for highly-parallel, compute-heavy applications. Cori, the newest supercomputer at the National Energy Research Scientific Computing Center (NERSC), was delivered to its users in two phases with the first phase online at the end of 2015 and the second phase now online at the end of 2016. Cori Phase 2 is based on the KNL architecture and contains over 9000 compute nodes with 96GB DDR4 memory. ATLAS simulation with the multithreaded Athena Framework (AthenaMT) is a good potential use-case for the KNL architecture and supercomputers like Cori. ATLAS simulation jobs have a high ratio of CPU computation to disk I/O and have been shown to scale well in multi-threading and across many nodes. In this paper we will give an overview of the ATLAS simulation application with detai...

  2. Multi-threaded ATLAS Simulation on Intel Knights Landing Processors

    CERN Document Server

    Farrell, Steven; The ATLAS collaboration; Calafiura, Paolo; Leggett, Charles

    2016-01-01

    The Knights Landing (KNL) release of the Intel Many Integrated Core (MIC) Xeon Phi line of processors is a potential game changer for HEP computing. With 72 cores and deep vector registers, the KNL cards promise significant performance benefits for highly-parallel, compute-heavy applications. Cori, the newest supercomputer at the National Energy Research Scientific Computing Center (NERSC), will be delivered to its users in two phases with the first phase online now and the second phase expected in mid-2016. Cori Phase 2 will be based on the KNL architecture and will contain over 9000 compute nodes with 96GB DDR4 memory. ATLAS simulation with the multithreaded Athena Framework (AthenaMT) is a great use-case for the KNL architecture and supercomputers like Cori. Simulation jobs have a high ratio of CPU computation to disk I/O and have been shown to scale well in multi-threading and across many nodes. In this presentation we will give an overview of the ATLAS simulation application with details on its multi-thr...

  3. Identification device

    Science.gov (United States)

    Lin, Jian-Shian; Su, Chih-Chieh; Chou, Ta-Hsin; Wu, Mount-Learn; Lai, Chieh-Lung; Hsu, Che-Lung; Lan, Hsiao-Chin; Huang, Hung-I.; Liu, Yung-Chih; Tu, Zong-Ru; Lee, Chien-Chieh; Chang, Jenq-Yang

    2007-09-01

    In this Letter, the identification device disclosed in the present invention is comprised of: a carrier and a plurality of pseudo-pixels; wherein each of the plural pseudo-pixels is formed on the carrier and is further comprised of at least a light grating composed of a plurality of light grids. In a preferred aspect, each of the plural light grids is formed on the carrier while spacing from each other by an interval ranged between 50nm and 900nm. As the aforesaid identification device can present specific colors and patterns while it is being viewed by naked eye with respect to a specific viewing angle, the identification device is preferred for security and anti-counterfeit applications since the specific colors and patterns will become invisible when it is viewed while deviating from the specific viewing angle.

  4. Devices and architectures for large-scale integrated silicon photonics circuits

    Science.gov (United States)

    Beausoleil, Raymond G.; Faraon, Andrei; Fattal, David; Fiorentino, Marco; Peng, Zhen; Santori, Charles

    2011-01-01

    We present DWDM nanophotonics architectures based on microring resonator modulators and detectors. We focus on two implementations: an on chip interconnect for multicore processor (Corona) and a high radix network switch (HyperX). Based on the requirements of these applications we discuss the key constraints on the photonic circuits' devices and fabrication techniques as well as strategies to improve their performance.

  5. Vectorization, parallelization and porting of nuclear codes (Parallelization on scalar processors). Progress report fiscal 1999

    Energy Technology Data Exchange (ETDEWEB)

    Yatake, Yo-ichi [Hitachi Ltd., Tokyo (Japan); Kume, Etsuo; Adachi, Masaaki; Ogasawara, Shinobu [Japan Atomic Energy Research Inst., Tokai, Ibaraki (Japan); Kawai, Wataru; Nemoto, Toshiyuki; Kawasaki, Nobuo; Ishizuki, Shigeru [Fujitsu Ltd., Tokyo (Japan)

    2000-12-01

    Several computer codes in the nuclear field have been vectorized, parallelized and transported on the FUJITSU VPP500 system, the AP3000 system, the SX-4 system and the Paragon system at Center for Promotion of Computational Science and Engineering in Japan Atomic Energy Research Institute. We dealt with 18 codes in fiscal 1999. These results are reported in 3 parts, i.e., the vectorization and the parallelization part on vector processors, the parallelization part on scalar processors and the porting part. In this report, we describe the parallelization on scalar processors. In this parallelization on scalar processors part, the parallelization of Nucleon Meson Transport Code (NMTC), Differential Algebraic VLASOV code (DA-VLASOV) and Monte Carlo N-Particle transport code (MCNP4B2) on the Paragon system are described. (author)

  6. Soft-core dataflow processor architecture optimised for radar signal processing: Article

    CSIR Research Space (South Africa)

    Broich, R

    2014-10-01

    Full Text Available an iterative design methodology to propose a novel softcore streaming processor architecture. The datapaths of this architecture are arranged in a circular pattern, with multiple operands simultaneously flowing between switching multiplexers and functional...

  7. An embedded laser marking controller based on ARM and FPGA processors

    National Research Council Canada - National Science Library

    Dongyun, Wang; Xinpiao, Ye

    2014-01-01

    .... Still, it cannot work outdoors or in other harsh environments. In order to compensate for the above mentioned disadvantages, this paper proposed an embedded laser marking controller based on ARM and FPGA processors...

  8. Design of a dataway processor for a parallel image signal processing system

    Science.gov (United States)

    Nomura, Mitsuru; Fujii, Tetsuro; Ono, Sadayasu

    1995-04-01

    Recently, demands for high-speed signal processing have been increasing especially in the field of image data compression, computer graphics, and medical imaging. To achieve sufficient power for real-time image processing, we have been developing parallel signal-processing systems. This paper describes a communication processor called 'dataway processor' designed for a new scalable parallel signal-processing system. The processor has six high-speed communication links (Dataways), a data-packet routing controller, a RISC CORE, and a DMA controller. Each communication link operates at 8-bit parallel in a full duplex mode at 50 MHz. Moreover, data routing, DMA, and CORE operations are processed in parallel. Therefore, sufficient throughput is available for high-speed digital video signals. The processor is designed in a top- down fashion using a CAD system called 'PARTHENON.' The hardware is fabricated using 0.5-micrometers CMOS technology, and its hardware is about 200 K gates.

  9. An Efficient Solution Method for Multibody Systems with Loops Using Multiple Processors

    Science.gov (United States)

    Ghosh, Tushar K.; Nguyen, Luong A.; Quiocho, Leslie J.

    2015-01-01

    This paper describes a multibody dynamics algorithm formulated for parallel implementation on multiprocessor computing platforms using the divide-and-conquer approach. The system of interest is a general topology of rigid and elastic articulated bodies with or without loops. The algorithm divides the multibody system into a number of smaller sets of bodies in chain or tree structures, called "branches" at convenient joints called "connection points", and uses an Order-N (O (N)) approach to formulate the dynamics of each branch in terms of the unknown spatial connection forces. The equations of motion for the branches, leaving the connection forces as unknowns, are implemented in separate processors in parallel for computational efficiency, and the equations for all the unknown connection forces are synthesized and solved in one or several processors. The performances of two implementations of this divide-and-conquer algorithm in multiple processors are compared with an existing method implemented on a single processor.

  10. Discrete Fourier transformation processor based on complex radix (−1 + j number system

    Directory of Open Access Journals (Sweden)

    Anidaphi Shadap

    2017-02-01

    Full Text Available Complex radix (−1 + j allows the arithmetic operations of complex numbers to be done without treating the divide and conquer rules, which offers the significant speed improvement of complex numbers computation circuitry. Design and hardware implementation of complex radix (−1 + j converter has been introduced in this paper. Extensive simulation results have been incorporated and an application of this converter towards the implementation of discrete Fourier transformation (DFT processor has been presented. The functionality of the DFT processor have been verified in Xilinx ISE design suite version 14.7 and performance parameters like propagation delay and dynamic switching power consumption have been calculated by Virtuoso platform in Cadence. The proposed DFT processor has been implemented through conversion, multiplication and addition. The performance parameter matrix in terms of delay and power consumption offered a significant improvement over other traditional implementation of DFT processor.

  11. NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

    National Research Council Canada - National Science Library

    Cheung, Kit; Schultz, Simon R; Luk, Wayne

    2015-01-01

    NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs...

  12. Advanced Hybrid On-Board Science Data Processor - SpaceCube 2.0

    Science.gov (United States)

    Flatley, Tom

    2010-01-01

    Topics include an overview of On-board science data processing, software upset mitigation, on-board data reduction, on-board products, HyspIRI demonstration testbed, SpaceCube 2.0 block diagram, and processor comparison.

  13. 78 FR 66899 - Proposed Information Collection; Comment Request; Commercial Fisheries Seafood Processor Survey

    Science.gov (United States)

    2013-11-07

    ... From the Federal Register Online via the Government Publishing Office DEPARTMENT OF COMMERCE National Oceanic and Atmospheric Administration Proposed Information Collection; Comment Request; Commercial Fisheries Seafood Processor Survey AGENCY: National Oceanic and Atmospheric Administration (NOAA...

  14. Food Manufacturers and Processors, US and Territories, 2015, EPA Region 9

    Data.gov (United States)

    U.S. Environmental Protection Agency — This GIS dataset contains point features that represent food manufacturers and processors associated with fifty-four NAICS codes. Establishment-specific information...

  15. Image processing system architecture using parallel arrays of digital signal processors

    Science.gov (United States)

    Kshirsagar, Shirish P.; Hobson, Clifford A.; Hartley, David A.; Harvey, David M.

    1993-10-01

    The paper describes the requirements of a high definition, high speed image processing system. Different types of parallel architectures were considered for the system. Advantages and limitations of SIMD and MIMD architectures are briefly discussed for image processing applications. A parallel image processing system based on MIMD architecture has been developed using multiple digital signal processors which can communicate with each other through an interconnection network. Texas Instruments TMS320C40 digital signal processors have been selected because they have a powerful floating point CPU supported by fast parallel communication ports, a DMA coprocessor and two memory interfaces. A five processor system is described in the paper. The EISA bus is used as the host interface and VISION bus is used to transfer images between the processors. The system is being used for automated non-contact inspection in which electro-optic signals are processed to identify manufacturing problems.

  16. Electrical Prototype Power Processor for the 30-cm Mercury electric propulsion engine

    Science.gov (United States)

    Biess, J. J.; Frye, R. J.

    1978-01-01

    An Electrical Prototpye Power Processor has been designed to the latest electrical and performance requirements for a flight-type 30-cm ion engine and includes all the necessary power, command, telemetry and control interfaces for a typical electric propulsion subsystem. The power processor was configured into seven separate mechanical modules that would allow subassembly fabrication, test and integration into a complete power processor unit assembly. The conceptual mechanical packaging of the electrical prototype power processor unit demonstrated the relative location of power, high voltage and control electronic components to minimize electrical interactions and to provide adequate thermal control in a vacuum environment. Thermal control was accomplished with a heat pipe simulator attached to the base of the modules.

  17. CuPIDS: An Exploration of Highly Focused, Co-Processor-Based Information System Protection

    National Research Council Canada - National Science Library

    Williams, Paul D; Spafford, Eugene H

    2005-01-01

    The Co-Processing Intrusion Detection System (CuPID S) project is exploring how torn improve information system security by dedicating computational resources to system security tasks in a shared resource, multi-processor (MP) architecture...

  18. Hyperspectral Imaging Sensor with Real-Time Processor Performing Principle Components Analyses for Gas Detection

    National Research Council Canada - National Science Library

    Hinnrichs, Michele

    2000-01-01

    .... With support from the US Air Force and Navy, Pacific Advanced Technology has developed a small man portable hyperspectral imaging sensor with an embedded DSP processor for real time processing...

  19. The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture

    OpenAIRE

    Biagioni, Andrea; Cicero, Francesca Lo; Lonardo, Alessandro; Paolucci, Pier Stanislao; Perra, Mersia; Rossetti, Davide; Sidore, Carlo; Simula, Francesco; Tosoratto, Laura; Vicini, Piero

    2012-01-01

    One of the most demanding challenges for the designers of parallel computing architectures is to deliver an efficient network infrastructure providing low latency, high bandwidth communications while preserving scalability. Besides off-chip communications between processors, recent multi-tile (i.e. multi-core) architectures face the challenge for an efficient on-chip interconnection network between processor's tiles. In this paper, we present a configurable and scalable architecture, based on...

  20. Interpreter composition issues in the formal verification of a processor-memory module

    Science.gov (United States)

    Fura, David A.; Cohen, Gerald C.

    1994-01-01

    This report describes interpreter composition techniques suitable for the formal specification and verification of a processor-memory module using the HOL theorem proving system. The processor-memory module is a multichip subsystem within a fault-tolerant embedded system under development within the Boeing Defense and Space Group. Modeling and verification methods were developed that permit provably secure composition at the transaction-level of specification, significantly reducing the complexity of the hierarchical verification of the system.