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Sample records for btev pixel readout

  1. FPIX2, the BTeV pixel readout chip

    CERN Document Server

    Christian, D C; Chiodini, G; Hoff, J; Kwan, S; Mekkaoui, A; Yarema, R; 10.1016/j.nima.2005.04.046

    2005-01-01

    A radiation tolerant pixel readout chip, FPIX2, has been developed at Fermilab for use by BTeV. Some of the requirements of the BTeV pixel readout chip are reviewed and contrasted with requirements for similar devices in LHC experiments. A description of the FPIX2 is given, and results of initial tests of its performance are presented, as is a summary of measurements planned for the coming year.

  2. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  3. Readout Architecture for Hybrid Pixel Readout Chips

    CERN Document Server

    AUTHOR|(SzGeCERN)694170; Westerlund, Tomi; Wyllie, Ken

    The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time...

  4. Digital column readout architectures for hybrid pixel detector readout chips

    International Nuclear Information System (INIS)

    Poikela, T; Plosila, J; Westerlund, T; Buytaert, J; Campbell, M; Gaspari, M De; Llopart, X; Wyllie, K; Gromov, V; Kluit, R; Beuzekom, M van; Zappon, F; Zivkovic, V; Brezina, C; Desch, K; Fu, Y; Kruth, A

    2014-01-01

    In this paper, two digital column architectures suitable for sparse readout of data from a pixel matrix in trigger-less applications are presented. Each architecture reads out a pixel matrix of 256 x 256 pixels with a pixel pitch of 55 μm. The first architecture has been implemented in the Timepix3 chip, and this is presented together with initial measurements. Simulation results and measured data are compared. The second architecture has been designed for Velopix, a readout chip planned for the LHCb VELO upgrade. Unlike Timepix3, this has to be tolerant to radiation-induced single-event effects. Results from post-layout simulations are shown with the circuit architectures

  5. Pixel readout electronics for LHC and biomedical applications

    CERN Document Server

    Blanquart, L; Comes, G; Delpierre, P A; Fischer, P; Hausmann, J C; Keil, M; Lindner, Manfred; Meuser, S; Wermes, N

    2000-01-01

    The demanding requirements for pixel readout electronics for high- energy physics experiments and biomedical applications are reviewed. Some examples of the measured analog performance of prototype chips are given. The readout architectures of the PIxel readout for the ATlas experiment (PIRATE) chip suited for LHC experiments and of the multi-picture element counter (MPEC) counting chip targeted for biomedical applications are presented. First results with complete chip-sensor assemblies are also shown. (12 refs).

  6. Bier and Pastis, a pixel readout prototype chip for LHC

    CERN Document Server

    Berg, C; Bonzom, V; Delpierre, P A; Desch, Klaus; Fischer, P; Keil, M; Meuser, S; Raith, B A; Wermes, N

    2000-01-01

    The 12*63 pixel readout prototype chip Bieu&Pastis, designed to cope with the environment imposed on a pixel detector by high-energy proton-proton collisions as expected at the Large Hadron Collider (LHC), is described. The chip contains the full pixel cell functionality, but not yet the full peripheral architecture for data transfer and readout with LHC speed. Design considerations and lab tests to characterize the performance as well as some test beam results are described. (7 refs).

  7. Pixel readout chip for the ATLAS experiment

    CERN Document Server

    Ackers, M; Blanquart, L; Bonzom, V; Comes, G; Fischer, P; Keil, M; Kühl, T; Meuser, S; Delpierre, P A; Treis, J; Raith, B A; Wermes, N

    1999-01-01

    Pixel detectors with a high granularity and a very large number of sensitive elements (cells) are a very recent development used for high precision particle detection. At the Large Hadron Collider LHC at CERN (Geneva) a pixel detector with 1.4*10/sup 8/ individual pixel cells is developed for the ATLAS detector. The concept is a hybrid detector. Consisting of a pixel sensor connected to a pixel electronics chip by bump and flip chip technology in one-to-one cell correspondence. The development and prototype results of the pixel front end chip are presented together with the physical and technical requirements to be met at LHC. Lab measurements are reported. (6 refs).

  8. Readout of TPC Tracking Chambers with GEMs and Pixel Chip

    Energy Technology Data Exchange (ETDEWEB)

    Kadyk, John; Kim, T.; Freytsis, M.; Button-Shafer, J.; Kadyk, J.; Vahsen, S.E.; Wenzel, W.A.

    2007-12-21

    Two layers of GEMs and the ATLAS Pixel Chip, FEI3, have been combined and tested as a prototype for Time Projection Chamber (TPC) readout at the International Linear Collider (ILC). The double-layer GEM system amplifies charge with gain sufficient to detect all track ionization. The suitability of three gas mixtures for this application was investigated, and gain measurements are presented. A large sample of cosmic ray tracks was reconstructed in 3D by using the simultaneous timing and 2D spatial information from the pixel chip. The chip provides pixel charge measurement as well as timing. These results demonstrate that a double GEM and pixel combination, with a suitably modified pixel ASIC, could meet the stringent readout requirements of the ILC.

  9. A pixelated charge readout for Liquid Argon Time Projection Chambers

    Science.gov (United States)

    Asaadi, J.; Auger, M.; Ereditato, A.; Goeldi, D.; Hänni, R.; Kose, U.; Kreslo, I.; Lorca, D.; Luethi, M.; von Rohr, C. Rudolf; Sinclair, J.; Stocker, F.; Tognina, C.; Weber, M.

    2018-02-01

    Liquid Argon Time Projection Chambers (LArTPCs) are ideally suited to perform long-baseline neutrino experiments aiming to measure CP violation in the lepton sector, and determine the ordering of the three neutrino mass eigenstates. LArTPCs have used projective wire readouts for charge detection since their conception in 1977. However, wire readouts are notoriously fragile and therefore a limiting factor in the design of any large mass detectors. Furthermore, a wire readout also introduces intrinsic ambiguities in event reconstruction. Within the ArgonCube concept—the liquid argon component of the DUNE near detector—we are developing a pixelated charge readout for LArTPCs. Pixelated charge readout systems represent the single largest advancement in the sensitivity of LArTPCs. They are mechanically robust and provide direct 3D readout, serving to minimise reconstruction ambiguities, enabling more advanced triggers, further reducing event pile-up and improving background rejection. This article presents first results from a pixelated LArTPC prototype built and operated in Bern.

  10. Digital Power Consumption Estimations for CHIPIX65 Pixel Readout Chip

    CERN Document Server

    Marcotulli, Andrea

    2016-01-01

    New hybrid pixel detectors with improved resolution capable of dealing with hit rates up to 3 GHz/cm2 will be required for future High Energy Physics experiments in the Large Hadron Collider (LHC) at CERN. Given this, the RD53 collaboration works on the design of the next generation pixel readout chip needed for both the ATLAS and CMS detector phase 2 pixel upgrades. For the RD53 demonstrator chip in 65nm CMOS technology, different architectures are considered. In particular the purpose of this work is estimating the power consumption of the digital architecture of the readout ASIC developed by CHIPIX65 project of the INFN National Scientific Committee. This has been done with modern chip design tools integrated with the VEPIX53 simulation framework that has been developed within the RD53 collaboration in order to assess the performance of the system in very high rate, high energy physics experiments.

  11. Sensor Development and Readout Prototyping for the STAR Pixel Detector

    Energy Technology Data Exchange (ETDEWEB)

    Greiner, L.; Anderssen, E.; Matis, H.S.; Ritter, H.G.; Stezelberger, T.; Szelezniak, M.; Sun, X.; Vu, C.; Wieman, H.

    2009-01-14

    The STAR experiment at the Relativistic Heavy Ion Collider (RHIC) is designing a new vertex detector. The purpose of this upgrade detector is to provide high resolution pointing to allow for the direct topological reconstruction of heavy flavor decays such as the D{sup 0} by finding vertices displaced from the collision vertex by greater than 60 microns. We are using Monolithic Active Pixel Sensor (MAPS) as the sensor technology and have a coupled sensor development and readout system plan that leads to a final detector with a <200 {micro}s integration time, 400 M pixels and a coverage of -1 < {eta} < 1. We present our coupled sensor and readout development plan and the status of the prototyping work that has been accomplished.

  12. Hexagonal pixel detector with time encoded binary readout

    International Nuclear Information System (INIS)

    Hoedlmoser, H.; Varner, G.; Cooney, M.

    2009-01-01

    The University of Hawaii is developing continuous acquisition pixel (CAP) detectors for vertexing applications in lepton colliding experiments such as SuperBelle or ILC. In parallel to the investigation of different technology options such as MAPS or SOI, both analog and binary readout concepts have been tested. First results with a binary readout scheme in which the hit information is time encoded by means of a signal shifting mechanism have recently been published. This paper explains the hit reconstruction for such a binary detector with an emphasis on fake hit reconstruction probabilities in order to evaluate the rate capability in a high background environment such as the planned SuperB factory at KEK. The results show that the binary concept is at least comparable to any analog readout strategy if not better in terms of occupancy. Furthermore, we present a completely new binary readout strategy in which the pixel cells are arranged in a hexagonal grid allowing the use of three independent output directions to reduce reconstruction ambiguities. The new concept uses the same signal shifting mechanism for time encoding, however, in dedicated transfer lines on the periphery of the detector, which enables higher shifting frequencies. Detailed Monte Carlo simulations of full size pixel matrices including hit and BG generation, signal generation, and data reconstruction show that by means of multiple signal transfer lines on the periphery the pixel can be made smaller (higher resolution), the number of output channels and the data volume per triggered event can be reduced dramatically, fake hit reconstruction is lowered to a minimum and the resulting effective occupancies are less than 10 -4 . A prototype detector has been designed in the AMS 0.35μm Opto process and is currently under fabrication.

  13. Monolithic pixels on moderate resistivity substrate and sparsifying readout architecture

    International Nuclear Information System (INIS)

    Giubilato, P.; Battaglia, M.; Bisello, D.; Caselle, M.; Chalmet, P.; Demaria, L.; Ikemoto, Y.; Kloukinas, K.; Mansuy, S.C.; Mattiazzo, S.; Marchioro, A.; Mugnier, H.; Pantano, D.; Potenza, A.; Rivetti, A.; Rousset, J.; Silvestrin, L.; Snoeys, W.

    2013-01-01

    The LePix projects aim realizing a new generation monolithic pixel detectors with improved performances at lesser cost with respect to both current state of the art monolithic and hybrid pixel sensors. The detector is built in a 90 nm CMOS process on a substrate of moderate resistivity. This allows charge collection by drift while maintaining the other advantages usually offered by MAPS, like having a single piece detector and using a standard CMOS production line. The collection by drift mechanism, coupled to the low capacitance design of the collecting node made possible by the monolithic approach, provides an excellent signal to noise ratio straight at the pixel cell together with a radiation tolerance far superior to conventional un-depleted MAPS. The excellent signal-to-noise performance is demonstrated by the device ability to separate the 6 keV 55 Fe double peak at room temperature. To achieve high granularity (10–20 µm pitch pixels) over large detector areas maintaining high readout speed, a completely new compressing architecture has been devised. This architecture departs from the mainstream hybrid pixel sparsification approach, which uses in-pixel logic to reduce data, by using topological compression to minimize pixel area and power consumption

  14. Towards a new generation of pixel detector readout chips

    CERN Document Server

    Campbell, M; Ballabriga, R.; Frojdh, E.; Heijne, E.; Llopart, X.; Poikela, T.; Tlustos, L.; Valerio, P.; Wong, W.

    2016-01-01

    The Medipix3 Collaboration has broken new ground in spectroscopic X-ray imaging and in single particle detection and tracking. This paper will review briefly the performance and limitations of the present generation of pixel detector readout chips developed by the Collaboration. Through Silicon Via technology has the potential to provide a significant improvement in the tile- ability and more flexibility in the choice of readout architecture. This has been explored in the context of 3 projects with CEA-LETI using Medipix3 and Timepix3 wafers. The next generation of chips will aim to provide improved spectroscopic imaging performance at rates compatible with human CT. It will also aim to provide full spectroscopic images with unprecedented energy and spatial resolution. Some of the opportunities and challenges posed by moving to a more dense CMOS process will be discussed.

  15. A prototype pixel readout chip for asynchronous detection applications

    International Nuclear Information System (INIS)

    Raymond, D.M.; Hall, G.; Lewis, A.J.; Sharp, P.H.

    1991-01-01

    A two-dimensional array of amplifier cells has been fabricated as a prototype readout system for a matching array of silicon diode detectors. Each cell contains a preamplifier, shaping amplifier, comparator and analogue signal storage in an area of 300 μmx320 μm using 3 μm CMOS technology. Full size chips will be bump bonded to pixel detector arrays. Low noise and asynchronous operation are novel design features. With noise levels of less than 250 rms electrons for input capacitances up to 600 fF, pixel detectors will be suitable for autoradiography, synchrotron X-ray and high energy particle detection applications. The design of the prototype chip is presented and future developments and prospects for applications are discussed. (orig.)

  16. Small-Scale Readout Systems Prototype for the STAR PIXEL Detector

    Energy Technology Data Exchange (ETDEWEB)

    Szelezniak, Michal A.; Besson, Auguste; Colledani, Claude; Dorokhov, Andrei; Dulinski, Wojciech; Greiner, Leo C.; Himmi, Abdelkader; Hu, Christine; Matis, Howard S.; Ritter, Hans Georg; Rose, Andrew; Shabetai, Alexandre; Stezelberger, Thorsten; Sun, Xiangming; Thomas, Jim H.; Valin, Isabelle; Vu, Chinh Q.; Wieman, Howard H.; Winter, Marc

    2008-10-01

    A prototype readout system for the STAR PIXEL detector in the Heavy Flavor Tracker (HFT) vertex detector upgrade is presented. The PIXEL detector is a Monolithic Active Pixel Sensor (MAPS) based silicon pixel vertex detector fabricated in a commercial CMOS process that integrates the detector and front-end electronics layers in one silicon die. Two generations ofMAPS prototypes designed specifically for the PIXEL are discussed. We have constructed a prototype telescope system consisting of three small MAPS sensors arranged in three parallel and coaxial planes with a readout system based on the readout architecture for PIXEL. This proposed readout architecture is simple and scales to the size required to readout the final detector. The real-time hit finding algorithm necessary for data rate reduction in the 400 million pixel detector is described, and aspects of the PIXEL system integration into the existing STAR framework are addressed. The complete system has been recently tested and shown to be fully functional.

  17. Monolithic pixels on moderate resistivity substrate and sparsifying readout architecture

    CERN Document Server

    Giubilato, P; Snoeys, W; Bisello, D; Marchioro, A; Battaglia, M; Demaria, L; Mansuy, S C; Pantano, D; Rousset, J; Mattiazzo, S; Kloukinas, K; Potenza, A; Ikemoto, Y; Rivetti, A; Chalmet, P; Mugnier, H; Silvestrin, L

    2013-01-01

    The LePix projects aim realizing a new generation monolithic pixel detectors with improved performances at lesser cost with respect to both current state of the art monolithic and hybrid pixel sensors. The detector is built in a 90 nm CMOS process on a substrate of moderate resistivity. This allows charge collection by drift while maintaining the other advantages usually offered by MAPS, like having a single piece detector and using a standard CMOS production line. The collection by drift mechanism, coupled to the low capacitance design of the collecting node made possible by the monolithic approach, provides an excellent signal to noise ratio straight at the pixel cell together with a radiation tolerance far superior to conventional un-depleted MAPS. The excellent signal-to-noise performance is demonstrated by the device ability to separate the 6 keV Fe-55 double peak at room temperature. To achieve high granularity (10-20 mu m pitch pixels) over large detector areas maintaining high readout speed, a complet...

  18. SPIDR, a general-purpose readout system for pixel ASICs

    International Nuclear Information System (INIS)

    Heijden, B. van der; Visser, J.; Beuzekom, M. van; Boterenbrood, H.; Munneke, B.; Schreuder, F.; Kulis, S.

    2017-01-01

    The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a 'soft core' CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four

  19. SPIDR, a general-purpose readout system for pixel ASICs

    Science.gov (United States)

    van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

    2017-02-01

    The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit

  20. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Document Server

    Garcia-Sciveres, M; CERN. Geneva. The LHC experiments Committee; LHCC

    2013-01-01

    Letter of Intent for RD Collaboration Proposal focused on development of a next generation pixel readout integrated circuits needed for high luminosity LHC detector upgrades. Brings together ATLAS and CMS pixel chip design communities.

  1. Pixel readout electronics development for the ALICE pixel vertex and LHCb RICH detector

    CERN Document Server

    Snoeys, W; Cantatore, E; Cencelli, V; Dinapoli, R; Heijne, Erik H M; Jarron, Pierre; Lamanna, P; Minervini, D; O'Shea, V; Quiquempoix, V; San Segundo-Bello, D; Van Koningsveld, B; Wyllie, Ken H

    2001-01-01

    The ALICE1LHCB pixel readout chip emerged from previous experience at CERN. The RD-19 collaboration provided the basis for the installation of a pixel system in the WA97 and NA57 experiments. Operation in these experiments was key in the understanding of the system issues. In parallel the RD-49 collaboration provided the basis to obtain radiation tolerance in commercial submicron CMOS through special circuit layout. The new ALICE1LMB chip was developed to serve two different applications: particle tracking in the ALICE Silicon Pixel Detector and particle identification in the LHCb Ring Imaging Cherenkov detector. To satisfy the different needs for these two experiments, the chip can be operated in two different modes. In tracking mode all the 50 mu m*435 mu m pixel cells in the 256*32 array are read out individually, whilst in particle identification mode they are combined in groups of 8 to form a 32*32 array of 400 mu m*425 mu m cells. The circuit is currently being manufactured in a commercial 0.25 mu m CMO...

  2. Development of hybrid photon detectors with integrated silicon pixel readout for the RICH counters of LHCb

    CERN Document Server

    Alemi, M; Formenti, F; Gys, Thierry; Piedigrossi, D; Puertolas, D; Rosso, E; Snoeys, W; Wyllie, Ken H

    1999-01-01

    We report on the ongoing work towards a hybrid photon detector with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment at the Large Hadron Collider at CERN. The photon detector is based $9 on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a fast, binary readout chip with matching pixel electronics. The $9 performance of a half-scale prototype is presented, together with the developments and tests of a full-scale tube with large active area. Specific requirements for pixel front-end and readout electronics in LHCb are outlined, and $9 recent results obtained from pixel chips applicable to hybrid photon detector design are summarized.

  3. Development of a customized SSC pixel detector readout for vertex tracking

    International Nuclear Information System (INIS)

    Barkan, O.; Atlas, E.L.; Marking, W.L.; Worley, S.; Yacoub, G.Y.; Kramer, G.; Arens, J.F.; Jernigan, J.G.; Shapiro, S.L.; Nygren, D.; Spieler, H.; Wright, M.

    1990-01-01

    The authors describe the readout architecture and progress to date in the development of hybrid PIN diode arrays for use as vertex detectors in the SSC environment. The architecture supports a self-timed mechanism for time stamping hit pixels, storing their xy coordinates and later selectively reading out only those pixels containing interesting data along with their coordinates. The peripheral logic resolves ambiguous pixel ghost locations and controls pixel neighbor readout to achieve high spatial resolution. A test lot containing 64 x 32 pixel arrays has been processed and is currently being tested. Each pixel contains 23 transistors and six capacitors consuming an area of 50μm by 150μm and dissipating about 20μW of power

  4. Development of a customized SSC pixel detector readout for vertex tracking

    International Nuclear Information System (INIS)

    Barkan, O.; Atlas, E.L.; Marking, W.L.; Worley, S.; Yacoub, G.Y.; Kramer, G.; Arens, J.F.; Jernigan, J.G.; Nygren, D.; Spieler, H.; Wright, M.

    1990-10-01

    We describe the readout architecture and progress to date in the development of hybrid PIN diode arrays for use as vertex detectors in the SSC environment. The architecture supports a self-timed mechanism for time stamping hit pixels, storing their xy coordinates and later selectively reading out only those pixels containing interesting data along with their coordinates. The peripheral logic resolves ambiguous pixel ghost locations and controls pixel neighbor readout to achieve high spatial resolution. A test lot containing 64 x 32 pixel arrays has been processed and is currently being tested. Each pixel contains 23 transistors and six capacitors consuming an area of 50 μm by 150 μm and dissipating about 20μW of power. 6 refs., 2 figs

  5. The ATLAS Pixel nSQP Readout Chain

    CERN Document Server

    Welch, S; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel New Service Quarter Panel (nSQP) project aims to deliver replacements for all on-detector services of the ATLAS Pixel Detector. The nSQPs will have replacements for the electro-optical converters. The replacement devices are LVDS transceiver boards (E-Boards) and they communicate with the existing ATLAS Pixel MCC chips over the original type 0 cables. In the other direction the E-Boards communicate over a 6.6 meter long transmission line with the VCSEL driver chips in the new electro-optical converters. These converters have been relocated to a region that is much more accessible.

  6. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Multimedia

    Liberali, V; Rizzi, A; Re, V; Minuti, M; Pangaud, P; Barbero, M B; Kluit, R; Hinchliffe, I; Manghisoni, M; Giubilato, P; Faccio, F; Pernegger, H; Krueger, H; Gensolen, F D; Bilei, G M; Da rocha rolo, M D; Prydderch, M L; Fanucci, L; Grillo, A A; Bellazzini, R; Palomo pinto, F R; Michelis, S; Huegging, F G; Kishishita, T; Marchiori, G; Christian, D C; Kaestli, H C; Meier, B; Andreazza, A; Key-charriere, M; Linssen, L; Dannheim, D; Conti, E; Hemperek, T; Menouni, M; Fougeron, D; Genat, J; Bomben, M; Marzocca, C; Demaria, N; Mazza, G; Van bakel, N A; Palla, F; Grippo, M T; Magazzu, G; Ratti, L; Abbaneo, D; Crescioli, F; Deptuch, G W; Neue, G; De robertis, G; Passeri, D; Placidi, P; Pacher, L; Gromov, V; Morsani, F; Paccagnella, A; Christiansen, J; Dho, E; Wermes, N; Rymaszewski, P; Rozanov, A; Wang, A; Lipton, R J; Havranek, M; Neviani, A; Marconi, S; Karagounis, M; Godiot, S; Calderini, G; Seidel, S C; Horisberger, R P; Garcia-sciveres, M A; Stabile, A; Beccherle, R; Bacchetta, N

    The present hybrid pixel detectors in operation at the LHC represent a major achievement. They deployed a new technology on an unprecedented scale and their success firmly established pixel tracking as indispensable for future HEP experiments. However, extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. We propose a new RD collaboration specifically focused on the development of pixel readout Integrated Circuits (IC). The IC challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm$^{2}$), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. We propose a collaboration to design the next generation of hybrid pixel readout chips to enable the ATLAS and CMS Phase 2 pixel upgrades. This does not imply that ATLAS and CMS must use the same exact pixel readout chip, as most of the dev...

  7. Digital column readout architecture for the ATLAS pixel 025 mum front end IC

    CERN Document Server

    Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

    2002-01-01

    A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

  8. Readout architecture for the Pixel-Strip module of the CMS Outer Tracker Phase-2 upgrade

    CERN Document Server

    Caratelli, Alessandro; Jan Kaplon; Kloukinas, Konstantinos; Simone Scarfi

    2016-01-01

    The Outer Tracker upgrade of the Compact Muon Solenoid (CMS) experiment at CERN introduces new challenges for the front-end readout electronics. In particular, the capability of identifying particles with high transverse momentum using modules with double sensor layers requires high speed real time interconnects between readout ASICs. The Pixel-Strip module combines a pixelated silicon layer with a silicon-strip layer. Consequently, it needs two different readout ASICs, namely the Short Strip ASIC (SSA) for the strip sensor and the Macro Pixel ASIC (MPA) for the pixelated sensor. The architecture proposed in this paper allows for a total data flow between readout ASICs of $\\sim$100\\,Gbps and reduces the output data flow from 1.3\\,Tbps to 30\\,Gbps per module while limiting the total power density to below 100\\,mW/cm$^2$. In addition a system-level simulation framework of all the front-end readout ASICs is developed in order to verify the data processing algorithm and the hardware implementation allowing mult...

  9. Readout board upgrade for the Pixel Detectors: reasons, status and results in ATLAS

    CERN Document Server

    Giangiacomi, Nico; The ATLAS collaboration

    2017-01-01

    The increase of luminosity in the LHC accelerator at CERN constitutes a challenge for the data readout since the rate of data to be transmitted depends on both pileup and trigger frequency. In the ATLAS experiment, the effect of the increased luminosity is most evident in the Pixel Detector, which is the detector closest to the beam pipe. In order to face the difficult experimental challenges, the readout system was upgraded during the last few years. The main purpose of the upgrade was to provide a higher bandwidth by exploiting more recent technologies. The new readout system is composed by two paired electronic boards named Back Of Crate (BOC) and ReadOut Driver (ROD). In this work the main readout limitation related to increased luminosity will be discussed as well as the strategy and the technological solutions adopted in order to cope with the future operational challenges. In addition the general progresses and achievements will be presented.

  10. Dead-time free pixel readout architecture for ATLAS front-end IC

    CERN Document Server

    Einsweiler, Kevin F; Kleinfelder, S A; Luo, L; Marchesini, R; Milgrome, O; Pengg, F X

    1999-01-01

    A low power sparse scan readout architecture has been developed for the ATLAS pixel front-end IC. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address $9 of the hits associating them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The $9 events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 mu HP process to meet the $9 requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC provides dead-time-less ambiguity free readout at 40 MHz data rate.

  11. ATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixels

    CERN Document Server

    Gabrielli, A; The ATLAS collaboration; Bruschi, M; D’Antone, I; Dopke, J; Falchieri, D; Flick, T; Gross-Kettner, J; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Polini, A; Rizzi, M; Christian Schroer, N; Travaglini, R; Zannoli, S; Zoccoli, A

    2010-01-01

    An additional inner layer for the existing ATLAS pixel detector, called Insertable B-Layer (IBL), is under design and it will be installed by LHCPHASE1. New front-end readout ASICs fabrication is ongoing and will replace the previous chips in this layer. The new system features higher readout speed - 160Mbit/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). The paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS DAQ system.

  12. A silicon pixel detector with routing for external VLSI read-out

    International Nuclear Information System (INIS)

    Thomas, S.L.; Seller, P.

    1988-07-01

    A silicon pixel detector with an array of 32 by 16 hexagonal pixels has been designed and is being built on high resistivity silicon. The detector elements are reverse biased diodes consisting of p-implants in an n-type substrate and are fully depleted from the front to the back of the wafer. They are intended to measure high energy ionising particles traversing the detector. The detailed design of the pixels, their layout and method of read-out are discussed. A number of test structures have been incorporated onto the wafer to enable measurements to be made on individual pixels together with a variety of active devices. The results will give a better understanding of the operation of the pixel array, and will allow testing of computer simulations of more elaborate structures for the future. (author)

  13. Design and realisation of integrated circuits for the readout of pixel sensors in high-energy physics and biomedical imaging

    International Nuclear Information System (INIS)

    Peric, I.

    2004-08-01

    Radiation tolerant pixel-readout chip for the ATLAS pixel detector has been designed, implemented in a deep-submicron CMOS technology and successfully tested. The chip contains readout-channels with complex analog and digital circuits. Chip for steering of the DEPFET active-pixel matrix has been implemented in a high-voltage CMOS technology. The chip contains channels which generate fast sequences of high-voltage signals. Detector containing this chip has been successfully tested. Pixel-readout test chip for an X-ray imaging pixel sensor has been designed, implemented in a CMOS technology and tested. Pixel-readout channels are able to simultaneously count the signals generated by passage of individual photons and to sum the total charge generated during exposure time. (orig.)

  14. High-speed readout of high-Z pixel detectors with the LAMBDA detector

    International Nuclear Information System (INIS)

    Pennicard, D.; Smoljanin, S.; Sheviakov, I.; Xia, Q.; Rothkirch, A.; Yu, Y.; Struth, B.; Hirsemann, H.; Graafsma, H.

    2014-01-01

    High-frame-rate X-ray pixel detectors make it possible to perform time-resolved experiments at synchrotron beamlines, and to make better use of these sources by shortening experiment times. LAMBDA is a photon-counting hybrid pixel detector based on the Medipix3 chip, designed to combine a small pixel size of 55 μm, a large tileable module design, high speed, and compatibility with ''high-Z'' sensors for hard X-ray detection. This technical paper focuses on LAMBDA's high-speed-readout functionality, which allows a frame rate of 2000 frames per second with no deadtime between successive images. This takes advantage of the Medipix3 chip's ''continuous read-write'' function and highly parallelised readout. The readout electronics serialise this data and send it back to a server PC over two 10 Gigabit Ethernet links. The server PC controls the detector and receives, processes and stores the data using software designed for the Tango control system. As a demonstration of high-speed readout of a high-Z sensor, a GaAs LAMBDA detector was used to make a high-speed X-ray video of a computer fan

  15. Fast Readout Architectures for Large Arrays of Digital Pixels: Examples and Applications

    Directory of Open Access Journals (Sweden)

    A. Gabrielli

    2014-01-01

    Full Text Available Modern pixel detectors, particularly those designed and constructed for applications and experiments for high-energy physics, are commonly built implementing general readout architectures, not specifically optimized in terms of speed. High-energy physics experiments use bidimensional matrices of sensitive elements located on a silicon die. Sensors are read out via other integrated circuits bump bonded over the sensor dies. The speed of the readout electronics can significantly increase the overall performance of the system, and so here novel forms of readout architectures are studied and described. These circuits have been investigated in terms of speed and are particularly suited for large monolithic, low-pitch pixel detectors. The idea is to have a small simple structure that may be expanded to fit large matrices without affecting the layout complexity of the chip, while maintaining a reasonably high readout speed. The solutions might be applied to devices for applications not only in physics but also to general-purpose pixel detectors whenever online fast data sparsification is required. The paper presents also simulations on the efficiencies of the systems as proof of concept for the proposed ideas.

  16. Fast Readout Architectures for Large Arrays of Digital Pixels: Examples and Applications

    Science.gov (United States)

    Gabrielli, A.

    2014-01-01

    Modern pixel detectors, particularly those designed and constructed for applications and experiments for high-energy physics, are commonly built implementing general readout architectures, not specifically optimized in terms of speed. High-energy physics experiments use bidimensional matrices of sensitive elements located on a silicon die. Sensors are read out via other integrated circuits bump bonded over the sensor dies. The speed of the readout electronics can significantly increase the overall performance of the system, and so here novel forms of readout architectures are studied and described. These circuits have been investigated in terms of speed and are particularly suited for large monolithic, low-pitch pixel detectors. The idea is to have a small simple structure that may be expanded to fit large matrices without affecting the layout complexity of the chip, while maintaining a reasonably high readout speed. The solutions might be applied to devices for applications not only in physics but also to general-purpose pixel detectors whenever online fast data sparsification is required. The paper presents also simulations on the efficiencies of the systems as proof of concept for the proposed ideas. PMID:24778588

  17. Silicon sensors with various pixel geometries adapted for a common readout ASIC

    Science.gov (United States)

    Milovanovic, M.; Burdin, S.; Dervan, P.; Buttar, C.; Bates, R.; Blue, A.; Doonan, K.; Wraight, K. G.; Mcmullen, T.; Stewart, A.; Pater, J.; Eisenhardt, S.; Mills, C.; Allport, P. P.; Matheson, J.; Lipp, J.; Sidiropoulos, G.; Ashby, J.; Doherty, F.; Mcewan, F.; Casse, G.; Forshaw, D. C.; Hayward, H.; Tsurin, I.; Wonsak, S.; Warmald, M.

    2014-11-01

    ATLAS is proposing to replace the entire tracking system for HL-LHC operation. The ``Letter of Intent'' baseline pixel size at higher radii was 50 × 250μm2 (varphi × η), based on the FE-I4 readout chip, and this was optimized for the central barrel region. The detector tracking performance in the end-cap pixel disks can benefit from enhanced resolution in the radial direction to improve the impact parameter resolution in z-coordinate (along the beam line) for high η tracks, which is critical in the high pile-up environment of the HL-LHC. So called ``strixel'' geometries, with long narrow pixels, can be proposed at higher z in the barrel where tracks pass through at large angles. Larger pixels may also be considered for an additional pixel layer if this could reduce the requirements, and therefore costs, for the outer part of the tracker. While ATLAS pixel upgrade plans are evolving, the demonstration of providing a variety of sensor pixel shapes and sizes for a common ASIC pixel geometry will be of general application, whatever the final ASIC design. This paper will report on the development and testing of pixel sensors with several different dimensions assembled into modules with the FE-I4 readout chip. Some of these were irradiated (with protons, 1015 neq/cm2) and evaluated at the DESY test beam. These, together with the test beam results with non-irradiated sensors, will be shown, as well as the results from laboratory characterization.

  18. The FE-I4 Pixel Readout Chip and the IBL Module

    Energy Technology Data Exchange (ETDEWEB)

    Barbero, Marlon; Arutinov, David; Backhaus, Malte; Fang, Xiao-Chao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Hans, Kruger; Kruth, Andre; Wermes, Norbert; /Bonn U.; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Alexander; /Marseille, CPPM; Beccherle, Roberto; Darbo, Giovanni; /INFN, Genoa; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; /LBL, Berkeley /NIKHEF, Amsterdam /Gottingen U. /SLAC

    2012-05-01

    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

  19. A MAPS based readout for Tera Pixel electromagnetic calorimeter at the ILC

    CERN Document Server

    Villani, E G; Tyndel, Mike; Apsimon, Robert

    2007-01-01

    A Monolithic Active Pixel Sensors (MAPS) based - option for the ILC ECAL will be presented. This novel design provides extremely fine granularity with integrated binary readout. This leads to a Tera-Pixel electromagnetic calorimeter system. An overview of the MAPS proposed solution will be given along with the advantages of this approach. A novel CMOS process used for the fabrication of the first MAPS prototype will be introduced and described. Device simulation results showing the expected detector performance will be shown. Initial preliminary reports from basic tests of the prototype will be given.

  20. Simulation of an efficiency measurement of the CMS pixel Read-Out Chip at high rates.

    CERN Document Server

    Delcourt, Martin

    2014-01-01

    My summer student project investigates the effects on the efficiency of out-of-sync events during a beam test at Fermilab on pixel detectors for the phase 1 upgrade of the CMS. While the best results of this project came from direct lab measurements, most of my work was focused on the development of a wider simulation to have a better understanding of the behaviour of the read-out chips during the beam test.

  1. Development of readout system for FE-I4 pixel module using SiTCP

    Science.gov (United States)

    Teoh, J. J.; Hanagaki, K.; Ikegami, Y.; Takubo, Y.; Terada, S.; Unno, Y.

    2013-12-01

    The ATLAS pixel detector will be replaced in the future High Luminosity-Large Hadron Collider (HL-LHC) upgrade to preserve or improve the detector performance at high luminosity environment. To meet the tight requirements of the upgrade, a new pixel Front-End (FE) Integrated Circuit (IC) called FE-I4 has been developed. We have then devised a readout system for the new FE IC. Our system incorporates Silicon Transmission Control Protocol (SiTCP) technology (Uchida, 2008 [1]) which utilizes the standard TCP/IP and UDP communication protocols. This technology allows direct data access and transfer between a readout hardware chain and PC via a high speed Ethernet. In addition, the communication protocols are small enough to be implemented in a single Field-Programable Gate Array (FPGA). Relying on this technology, we have been able to construct a very compact, versatile and fast readout system. We have developed a firmware and software together with the readout hardware chain. We also have established basic functionalities for reading out FE-I4.

  2. Medipix3: A 64 k pixel detector readout chip working in single photon counting mode with improved spectrometric performance

    CERN Document Server

    Ballabriga, R; Wong, W; Heijne, E; Campbell, M; Llopart, X

    2011-01-01

    Medipix3 is a 256 x 256 channel hybrid pixel detector readout chip working in a single photon counting mode with a new inter-pixel architecture, which aims to improve the energy resolution in pixelated detectors by mitigating the effects of charge sharing between channels. Charges are summed in all 2 x 2 pixel clusters on the chip and a given hit is allocated locally to the pixel summing circuit with the biggest total charge on an event-by-event basis. Each pixel contains also two 12-bit binary counters with programmable depth and overflow control. The chip is configurable such that either the dimensions of each detector pixel match those of one readout pixel or detector pixels are four times greater in area than the readout pixels. In the latter case, event-by-event summing is still possible between the larger pixels. Each pixel has around 1600 transistors and the analog static power consumption is below 15 mu W in the charge summing mode and 9 mu W in the single pixel mode. The chip has been built in an 8-m...

  3. Readout board upgrade for the Pixel Detectors: reasons, status and results in ATLAS

    CERN Document Server

    Giangiacomi, Nico; The ATLAS collaboration

    2017-01-01

    At LHC the design luminosity, 1034 cm -2 s -1 , has already been reached during Summer 2016. LHC is planning, in the short term future, to further enhance the luminosity, resulting in a higher trigger frequency and an increased pileup. These factors constitute a challenge for the data readout since the rate of data to be transmitted depends on both pileup and trigger frequency. In the ATLAS experiment, the effect of the increased luminosity is most evident in the Pixel Detector, which is the detector closest to the beam pipe. In order to face the difficult experimental challenges, the readout system was upgraded during the last few years. The main purpose of the upgrade was to provide a higher bandwidth by exploiting recent technologies. The new readout system is composed by two paired electronic boards, Back Of Crate (BOC) and ReadOut Driver (ROD). In this presentation the main readout limitation related to increased luminosity will be discussed as well as the strategy and the technological solutions adopted...

  4. Development of Micromegas-like gaseous detectors using a pixel readout chip as collecting anode

    International Nuclear Information System (INIS)

    Chefdeville, M.

    2009-01-01

    This thesis reports on the fabrication and test of a new gaseous detector with a very large number of readout channels. This detector is intended for measuring the tracks of charged particles with an unprecedented sensitivity to single electrons of almost 100 %. It combines a metal grid for signal amplification called the Micromegas with a pixel readout chip as signal collecting anode and is dubbed GridPix. GridPix is a potential candidate for a sub-detector at a future electron linear collider (ILC) foreseen to work in parallel with the LHC around 2020--2030. The tracking capability of GridPix is best exploited if the Micromegas is integrated on the pixel chip. This integrated grid is called InGrid and is precisely fabricated by wafer post-processing. The various steps of the fabrication process and the measurements of its gain, energy resolution and ion back-flow property are reported in this document. Studies of the response of the complete detector formed by an InGrid and a TimePix pixel chip to X-rays and cosmic particles are also presented. In particular, the efficiency for detecting single electrons and the point resolution in the pixel plane are measured. Implications for a GridPix detector at ILC are discussed. (author)

  5. The Layer 1 / Layer 2 readout upgrade for the ATLAS Pixel Detector

    CERN Document Server

    Mullier, Geoffrey; The ATLAS collaboration

    2016-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the Large Hadron Collider (LHC). The increase of instantaneous luminosity foreseen during the LHC Run 2, will lead to an increased detector occupancy that is expected to saturate the readout links of the outermost layers of the pixel detector: Layers 1 and 2. To ensure a smooth data taking under such conditions, the read out system of the recently installed fourth innermost pixel layer, the Insertable B-Layer, was modified to accomodate the needs of the older detector. The Layer 2 upgrade installation took place during the 2015 winter shutdown, with the Layer 1 installation scheduled for 2016. A report of the successful installation, together with the design of novel dedicated optical to electrical converters and the software and firmware updates will be presented.

  6. Fast Imaging Detector Readout Circuits with In-Pixel ADCs for Fourier Transform Imaging Spectrometers

    Science.gov (United States)

    Rider, D.; Blavier, J-F.; Cunningham, T.; Hancock, B.; Key, R.; Pannell, Z.; Sander, S.; Seshadri, S.; Sun, C.; Wrigley, C.

    2011-01-01

    Focal plane arrays (FPAs) with high frame rates and many pixels benefit several upcoming Earth science missions including GEO-CAPE, GACM, and ACE by enabling broader spatial coverage and higher spectral resolution. FPAs for the PanFTS, a high spatial resolution Fourier transform spectrometer and a candidate instrument for the GEO-CAPE mission are the focus of the developments reported here, but this FPA technology has the potential to enable a variety of future measurements and instruments. The ESTO ACT Program funded the developed of a fast readout integrated circuit (ROIC) based on an innovative in-pixel analog-to-digital converter (ADC). The 128 X 128 pixel ROIC features 60 ?m pixels, a 14-bit ADC in each pixel and operates at a continuous frame rate of 14 kHz consuming only 1.1 W of power. The ROIC outputs digitized data completely eliminating the bulky, power consuming signal chains needed by conventional FPAs. The 128 X 128 pixel ROIC has been fabricated in CMOS and tested at the Jet Propulsion Laboratory. The current version is designed to be hybridized with PIN photodiode arrays via indium bump bonding for light detection in the visible and ultraviolet spectral regions. However, the ROIC design incorporates a small photodiode in each cell to permit detailed characterization of the ROICperformance without the need for hybridization. We will describe the essential features of the ROIC design and present results of ROIC performance measurements.

  7. Development and simulation results of a sparsification and readout circuit for wide pixel matrices

    International Nuclear Information System (INIS)

    Gabrielli, A.; Giorgi, F.; Morsani, F.; Villa, M.

    2011-01-01

    In future collider experiments, the increasing luminosity and centre of mass energy are rising challenging problems in the design of new inner tracking systems. In this context we develop high-efficiency readout architectures for large binary pixel matrices that are meant to cope with the high-stressing conditions foreseen in the innermost layers of a tracker [The SuperB Conceptual Design Report, INFN/AE-07/02, SLAC-R-856, LAL 07-15, Available online at: (http://www.pi.infn.it/SuperB)]. We model and design digital readout circuits to be integrated on VLSI ASICs. These architectures can be realized with different technology processes and sensors: they can be implemented on the same silicon sensor substrate of a CMOS MAPS devices (Monolithic Active Pixel Sensor), on the CMOS tier of a hybrid pixel sensor or in a 3D chip where the digital layer is stacked on the sensor and the analog layers [V. Re et al., Nuc. Instr. and Meth. in Phys. Res. A, (doi:10.1016/j.nima.2010.05.039)]. In the presented work, we consider a data-push architecture designed for a sensor matrix of an area of about 1.3 cm 2 with a pitch of 50 microns. The readout circuit tries to take great advantage of the high density of in-pixel digital logic allowed by vertical integration. We aim at sustaining a rate density of 100 Mtrack . s -1 . cm -2 with a temporal resolution below 1 μs. We show how this architecture can cope with these stressing conditions presenting the results of Monte Carlo simulations.

  8. A Readout Chip for a 64 x 64 Pixel Matrix with 15-bit Single Photon Counting

    CERN Document Server

    Campbell, M; Meddeler, G; Pernigotti, E; Snoeys, W

    1998-01-01

    A single Photon Counting pixel detector readout Chip (PCC) has been derived from previous work in the CERN RD19 collaboration for particle physics tracking devices, recently developed for high energy physics experiments. The readout chip is a 64 x 64 matrix of identical 170mm x 170mm cells. It is to be bump-bonded to an equally segmented 1 cm2 matrix of semiconductor sensors, e.g. Si or GaAs. Each readout cell comprises a preamplifier, a discriminator and a 15-bit counter. The input noise is 170 e- rms. At the lowest nominal threshold of 1 400 e- (5.1 keV in Si) the cells exhibit a threshold di stribution with a spread before adjustment of 350 e- rms. Each cell has a 5-bit register which allows masking, test-enable and 3-bit individual threshold adjust. After adjustment the threshold spread is reduced to 80 e- rms. Absolute calibration of the electrically measured equivalent charge can be done once the readout chip is bump-bonded to a detector.

  9. submitter Development of the readout for the IBL upgrade project of the ATLAS Pixel Detector

    CERN Document Server

    Krieger, Nina

    The LHC luminosity is upgraded in several phases until 2022. The resulting higher occupancy degrades the detector performance of the current Pixel Detector. To provide a good performance during the LHC luminosity upgrade, a fourth pixel layer is inserted into the existing ATLAS Pixel Detector. A new FE-I4 readout chip and a new data acquisition chain are required to cope with the higher track rate and the resulting increased bandwidth. Among others, this includes a new readout board: the IBL ROD. One component of this board is the DSP which creates commands for the FE-I4 chip and has to be upgraded as well. In this thesis, the first tests of the IBL ROD prototype are presented. A correct communication of the DSP to its external memory is verified. Moreover, the implementations for an IBL DSP code are described and tested. This includes the first configuration of the FE-I4 with an IBL ROD. In addition, a working communication with the Histogrammer SDRAM and the Input FIFO on the IBL ROD are demonstrated.

  10. Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

    OpenAIRE

    Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.

    2017-01-01

    Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. Depleted fully monolithic CMOS pixels with fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which w...

  11. Studies and development of a readout ASIC for pixelated CdTe detectors for space applications

    International Nuclear Information System (INIS)

    Michalowska, A.

    2013-01-01

    The work presented in this thesis is part of a project where a new instrument is developed: a camera for hard X-rays imaging spectroscopy. It is dedicated to fundamental research for observations in astrophysics, at wavelengths which can only be observed using space-borne instruments. In this domain the spectroscopic accuracy as well as the imaging details are of high importance. This work has been realized at CEA/IRFU (Institut de Recherche sur les lois Fondamentales de l'Univers), which has a long-standing and successful experience in instruments for high energy physics and space physics instrumentation. The objective of this thesis is the design of the readout electronics for a pixelated CdTe detector, suitable for a stacked assembly. The principal parameters of this integrated circuit are a very low noise for reaching a good accuracy in X-ray energy measurement, very low power consumption, a critical parameter in space-borne applications, and a small dead area for the full system combining the detector and the readout electronics. In this work I have studied the limits of these three parameters in order to optimize the circuit. In terms of the spectral resolution, two categories of noise had to be distinguished to determine the final performance. The first is the Fano noise limit, related to detector interaction statistics, which cannot be eliminated. The second is the electronic noise, also unavoidable; however it can be minimized through optimization of the detection chain. Within the detector, establishing a small pixel pitch of 300 μm reduces the input capacitance and the dark current. This limits the effects of the electronic noise. Also in order to limit the input capacitance the future camera is designed as a stacked assembly of the detector with the readout ASIC. This allows to reach extremely good input parameters seen by the readout electronics: a capacitance in range of 0.3 pF-1 pF and a dark current below 5 pA. In the frame of this thesis I have

  12. Calibration of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

    CERN Document Server

    AUTHOR|(SzGeCERN)734627; Arfaoui, Samir; Benoit, Mathieu; Celeste, Damiano; Dannheim, Dominik; Pfleger, Florentina; Redford, Sophie

    2015-01-01

    In the framework of vertex detector R&D for a future Compact Linear Collider, the charac- terisation of ultra-thin hybrid pixel detector assemblies comprising 50 − 300 μm thick silicon sensors and Timepix readout ASICs is underway through beam tests at DESY and CERN. The work presented here supports the beam test data analysis by providing an energy calibra- tion of certain assemblies, so giving access to energy measurements in addition to recorded Time Over Threshold counts. Photons from a variety of radioactive sources and X-ray fluorescence are used to measure the response of the assemblies in the region of 3 − 60 keV. Threshold measurements are also performed. Global and pixel-by-pixel calibrations of the assemblies are parametrised and the uniformity of the response of the pixel matrices are discussed. Data samples recorded in beam tests are calibrated and the resulting energy spectra presented. For the first time calibration parameters are estimated for two 50 μm thick sensors which are forese...

  13. Results of FE65-P2 Pixel Readout Test Chip for High Luminosity LHC Upgrades

    CERN Document Server

    AUTHOR|(SzGeCERN)394193

    2016-01-01

    A pixel readout test chip called FE65-P2 has been fabricated on 65 nm CMOS technology. FE65-P2 contains a matrix of 64 x 64 pixels on 50 micron by 50 micron pitch, designed to read out a bump bonded sensor. The goals of FE65-P2 are to demonstrate excellent analog performance isolated from digital activity well enough to achieve 500 electron stable threshold, be radiation hard to at least 500 Mrad, and prove the novel concept of isolated analog front ends embedded in a flat digital design, dubbed “analog islands in a digital sea”. Experience from FE65-P2 and hybrid assemblies will be applied to the design for a large format readout chip, called RD53A, to be produced in a wafer run in early 2017 by the RD53 collaboration. We review the case for 65 nm technology and report on threshold stability test results for the FE65-P2.

  14. YARR - A PCIe based Readout Concept for Current and Future ATLAS Pixel Modules

    Science.gov (United States)

    Heim, Timon

    2017-10-01

    The Yet Another Rapid Readout (YARR) system is a DAQ system designed for the readout of current generation ATLAS Pixel FE-I4 and next generation chips. It utilises a commercial-off-the-shelf PCIe FPGA card as a reconfigurable I/O interface, which acts as a simple gateway to pipe all data from the Pixel modules via the high speed PCIe connection into the host system’s memory. Relying on modern CPU architectures, which enables the usage of parallelised processing in threads and commercial high speed interfaces in everyday computers, it is possible to perform all processing on a software level in the host CPU. Although FPGAs are very powerful at parallel signal processing their firmware is hard to maintain and constrained by their connected hardware. Software, on the other hand, is very portable and upgraded frequently with new features coming at no cost. A DAQ concept which does not rely on the underlying hardware for acceleration also eases the transition from prototyping in the laboratory to the full scale implementation in the experiment. The overall concept and data flow will be outlined, as well as the challenges and possible bottlenecks which can be encountered when moving the processing from hardware to software.

  15. A vertically integrated pixel readout device for the Vertex Detector at the International Linear Collider

    International Nuclear Information System (INIS)

    Deptuch, Grzegorz; Christian, David; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

    2008-01-01

    3D-Integrated Circuit technology enables higher densities of electronic circuitry per unit area without the use of nanoscale processes. It is advantageous for mixed mode design with precise analog circuitry because processes with conservative feature sizes typically present lower process dispersions and tolerate higher power supply voltages, resulting in larger separation of a signal from the noise floor. Heterogeneous wafers (different foundries or different process families) may be combined with some 3D integration methods, leading to the optimization of each tier in the 3D stack. Tracking and vertexing in future High-Energy Physics (HEP) experiments involves construction of detectors composed of up to a few billions of channels. Readout electronics must record the position and time of each measurement with the highest achievable precision. This paper reviews a prototype of the first 3D readout chip for HEP, designed for a vertex detector at the International Linear Collider. The prototype features 20 x 20 (micro)m 2 pixels, laid out in an array of 64 x 64 elements and was fabricated in a 3-tier 0.18 (micro)m Fully Depleted SOI CMOS process at MIT-Lincoln Laboratory. The tests showed correct functional operation of the structure. The chip performs a zero-suppressed readout. Successive submissions are planned in a commercial 3D bulk 0.13 (micro)m CMOS process to overcome some of the disadvantages of an FDSOI process

  16. Optimizing scanning array performance using gain normalization and timedelay and integrate pixel deselection during readout, hybrid, and focal plane testing

    Science.gov (United States)

    Adams, A. D.; Johnson, Greg A.; Jolivet, Noel D.; Metschuleit, Jeff L.

    1992-07-01

    When testing infrared readouts, detector-readout hybrid assemblies, or focal plane arrays (FPAs), performance optimization is usually limited to adjustment of biases or clock rails, or subtle changes in readout timing. These generally result in global changes to the characteristics of the entire array rather than affecting individual pixels and channels. Using a scanning system that incorporates per channel gain normalization and a redundant time delay and integrate (TDI) architecture in the readout, pixels can be enhanced or deselected using an on- chip static RAM according to user-defined criteria resulting in improved uniformity of performance. A series of tests can be run automatically that evaluate each pixel's behavior at the readout or the hybrid level. When compared to or compiled against array-wide averages or system specifications, a map of dead or degraded pixels is created, and the timing necessary to either normalize each channel from a gain standpoint or mask out individual pixels is applied to the device under test. This technique has been successfully applied to 480 X 6 (120 X 4 X 6 in TDI) scanning architectures in both InSb and HgCdTe systems as well as multiple-chip and dual-band configurations. This paper describes a methodology and details how readout devices were screened and selected for hybridization and FPA build. The chip architecture and control timing is discussed to show how normalization and deselection was accomplished with a minimum of clock lines involved. A software utility is presented that allowed easy graphical interface to the user for manipulating the functions of the device. Algorithms for optimizing performance are then discussed and evaluated. Trade-offs made in optimizing one parameter against another are analyzed. Finally, results are presented demonstrating improved performance, customized by pixel to suit application specifications.

  17. Study of Charge Diffusion in a Silicon Detector Using an Energy Sensitive Pixel Readout Chip

    CERN Document Server

    Schioppa, E. J.; van Beuzekom, M.; Visser, J.; Koffeman, E.; Heijne, E.; Engel, K. J.; Uher, J.

    2015-01-01

    A 300 μm thick thin p-on-n silicon sensor was connected to an energy sensitive pixel readout ASIC and exposed to a beam of highly energetic charged particles. By exploiting the spectral information and the fine segmentation of the detector, we were able to measure the evolution of the transverse profile of the charge carriers cloud in the sensor as a function of the drift distance from the point of generation. The result does not rely on model assumptions or electric field calculations. The data are also used to validate numerical simulations and to predict the detector spectral response to an X-ray fluorescence spectrum for applications in X-ray imaging.

  18. Test beam analysis of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

    CERN Document Server

    Alipour Tehrani, Niloufar; Dannheim, Dominik; Firu, Elena; Kulis, Szymon; Redford, Sophie; Sicking, Eva

    2016-01-01

    The requirements for the vertex detector at the proposed Compact Linear Collider imply a very small material budget: less than 0.2% of a radiation length per detection layer including services and mechanical supports. We present here a study using Timepix readout ASICs hybridised to pixel sensors of 50 − 500 μm thickness, including assemblies with 100 μm thick sensors bonded to thinned 100μm thick ASICs. Sensors from three producers (Advacam, Micron Semiconductor Ltd, Canberra) with different edge termination technologies (active edge, slim edge) were bonded to Timepix ASICs. These devices were characterised with the EUDET telescope at the DESY II test beam using 5.6 GeV electrons. Their performance for the detection and tracking of minimum ionising particles was evaluated in terms of charge sharing, detection efficiency, single-point resolution and energy deposition.

  19. A 10 MHz micropower CMOS front end for direct readout of pixel detectors

    International Nuclear Information System (INIS)

    Campbell, M.; Heijne, E.H.M.; Jarron, P.; Krummenacher, F.; Enz, C.C.; Declercq, M.; Vittoz, E.; Viertel, G.

    1990-01-01

    In the framework of the CERN-LAA project for detector R and D, a micropower circuit of 200 μmx200 μm with a current amplifier, a latched comparator and a digital memory element has been tested electrically and operated in connection with linear silicon detector arrays. The experimental direct-readout (DRO) chip comprises a matrix of 9x12 circuit cells and has been manufactured in a 3 μm CMOS technology. Particles and X-ray photons below 22 keV were detected, and thresholds can be set between 2000 and 20000 e - . The noise is less than 4 keV FWHM or 500 e - rms and the power dissipation per pixel element is 30 μW. The chip can be coupled to a detector matrix using bump bonding. (orig.)

  20. The BTeV Software Tutorial Suite

    Energy Technology Data Exchange (ETDEWEB)

    Robert K. Kutschke

    2004-02-20

    The BTeV Collaboration is starting to develop its C++ based offline software suite, an integral part of which is a series of tutorials. These tutorials are targeted at a diverse audience, including new graduate students, experienced physicists with little or no C++ experience, those with just enough C++ to be dangerous, and experts who need only an overview of the available tools. The tutorials must both teach C++ in general and the BTeV specific tools in particular. Finally, they must teach physicists how to find and use the detailed documentation. This report will review the status of the BTeV experiment, give an overview of the plans for and the state of the software and will then describe the plans for the tutorial suite.

  1. BTeV trigger/DAQ innovations

    Energy Technology Data Exchange (ETDEWEB)

    Votava, Margaret; /Fermilab

    2005-05-01

    BTeV was a proposed high-energy physics (HEP) collider experiment designed for the study of B-physics and CP Violation at the Tevatron at Fermilab. BTeV included a large-scale, high-speed trigger and data acquisition (DAQ) system, reading data from the detector at 500 Gbytes/sec and writing data to mass storage at a rate of 200 Mbytes/sec. The design of the trigger/DAQ system was innovative while remaining realistic in terms of technical feasibility, schedule and cost. This paper will give an overview of the BTeV trigger/DAQ architecture, highlight some of the technical challenges, and describe the approach that was used to solve these challenges.

  2. The BTeV Software Tutorial Suite

    International Nuclear Information System (INIS)

    Kutschke, Robert K.

    2004-01-01

    The BTeV Collaboration is starting to develop its C++ based offline software suite, an integral part of which is a series of tutorials. These tutorials are targeted at a diverse audience, including new graduate students, experienced physicists with little or no C++ experience, those with just enough C++ to be dangerous, and experts who need only an overview of the available tools. The tutorials must both teach C++ in general and the BTeV specific tools in particular. Finally, they must teach physicists how to find and use the detailed documentation. This report will review the status of the BTeV experiment, give an overview of the plans for and the state of the software and will then describe the plans for the tutorial suite

  3. A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications.

    Science.gov (United States)

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

    2015-10-01

    We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to digital converter (ADC), configuration registers, and a 4-state digital controller. For every detected photon, the pixel electronics provides the energy deposited in the detector with 10-bit resolution, and a fast trigger signal for time stamp. The ASIC contains the 16-pixel matrix electronics, a digital controller, five global voltage references, a TDC, a temperature sensor, and a band-gap based current reference. The ASIC has been fabricated with TSMC 0.25 μ m mixed-signal CMOS technology and occupies an area of 5.3 mm × 6.8 mm. The TDC shows a resolution of 95.5 ps, a precision of 600 ps at full width half maximum (FWHM), and a power consumption of 130 μ W. In acquisition mode, the total power consumption of every pixel is 200 μ W. An equivalent noise charge (ENC) of 160 e - RMS at maximum gain and negative polarity conditions has been measured at room temperature.

  4. First operation of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon pixel readout

    CERN Document Server

    Alemi, M; Gys, Thierry; Mikulec, B; Piedigrossi, D; Puertolas, D; Rosso, E; Schomaker, R; Snoeys, W; Wyllie, Ken H

    2000-01-01

    We report on the first operation of a hybrid photon detector prototype with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment. The photon detector is based on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a binary readout chip with matching pixel electronics. The prototype has been characterized using a low-intensity light-emitting diode operated in pulsed mode. Its performance in terms of single-photoelectron detection efficiency and imaging properties is presented. A model of photoelectron detection is proposed, and is shown to be in good agreement with the experimental data. It includes an estimate of the charge signal generated in the silicon detector, and the combined effects of the comparator threshold spread of the pixel readout chip, charge sharing at the pixel boundaries and back-scattering of the photoelectrons at the silicon detector surface...

  5. First operation of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon pixel readout

    International Nuclear Information System (INIS)

    Alemi, M.; Campbell, M.; Gys, T.; Mikulec, B.; Piedigrossi, D.; Puertolas, D.; Rosso, E.; Schomaker, R.; Snoeys, W.; Wyllie, K.

    2000-01-01

    We report on the first operation of a hybrid photon detector prototype with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment. The photon detector is based on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a binary readout chip with matching pixel electronics. The prototype has been characterized using a low-intensity light-emitting diode operated in pulsed mode. Its performance in terms of single-photoelectron detection efficiency and imaging properties is presented. A model of photoelectron detection is proposed, and is shown to be in good agreement with the experimental data. It includes an estimate of the charge signal generated in the silicon detector, and the combined effects of the comparator threshold spread of the pixel readout chip, charge sharing at the pixel boundaries and back-scattering of the photoelectrons at the silicon detector surface

  6. First operation of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon pixel readout

    Energy Technology Data Exchange (ETDEWEB)

    Alemi, M.; Campbell, M.; Gys, T. E-mail: thierry.gys@cern.ch; Mikulec, B.; Piedigrossi, D.; Puertolas, D.; Rosso, E.; Schomaker, R.; Snoeys, W.; Wyllie, K

    2000-07-11

    We report on the first operation of a hybrid photon detector prototype with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment. The photon detector is based on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a binary readout chip with matching pixel electronics. The prototype has been characterized using a low-intensity light-emitting diode operated in pulsed mode. Its performance in terms of single-photoelectron detection efficiency and imaging properties is presented. A model of photoelectron detection is proposed, and is shown to be in good agreement with the experimental data. It includes an estimate of the charge signal generated in the silicon detector, and the combined effects of the comparator threshold spread of the pixel readout chip, charge sharing at the pixel boundaries and back-scattering of the photoelectrons at the silicon detector surface.

  7. Macro Pixel ASIC (MPA): The readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

    CERN Document Server

    Ceresa, Davide; Kloukinas, Konstantinos; Jan Kaplon; Bialas, Wojciech; Re, Valerio; Traversi, Gianluca; Gaioni, Luigi; Ratti, Lodovico

    2014-01-01

    The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level\\,1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720\\,pixels and 1920\\,strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method i...

  8. ATLAS IBL: Integration of new HW/SW readout features for the additional layer of Pixel Detector

    CERN Document Server

    Bruni, G; D’Antone, I; Dopke, J; Falchieri, D; Flick, T; Gabrielli, A; Gross-Kettner, J; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Polini, A; Rizzi, M; Schroer, N C; Travaglini, R; Zannoli, S; Zoccoli, A

    2011-01-01

    An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design. The front-end electronics features a new readout ASIC, named FeI4, which requires new off-detector electronics, currently realized with two VME-based boards, which implement optical I/O functionality (BOC card) and data processing functionality (ROD card), plus a timing interface module (TIM). This paper presents a proposal for the IBL readout system, mainly focusing on the ROD board.

  9. Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

    Science.gov (United States)

    Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P. L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C. A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Puggioni, C.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Siddhanta, S.; Usai, G.; van Hoorne, J. W.; Yi, J.

    2015-06-01

    Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented.

  10. Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

    International Nuclear Information System (INIS)

    Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P.L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C.A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.

    2015-01-01

    Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented

  11. Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

    Energy Technology Data Exchange (ETDEWEB)

    Yang, P., E-mail: yangping0710@126.com [Central China Normal University, Wuhan (China); Aglieri, G.; Cavicchioli, C. [CERN, 1210 Geneva 23 (Switzerland); Chalmet, P.L. [MIND, Archamps (France); Chanlek, N. [Suranaree University of Technology, Nakhon Ratchasima (Thailand); Collu, A. [University of Cagliari, Cagliari (Italy); INFN (Italy); Gao, C. [Central China Normal University, Wuhan (China); Hillemanns, H.; Junique, A. [CERN, 1210 Geneva 23 (Switzerland); Kofarago, M. [CERN, 1210 Geneva 23 (Switzerland); University of Utrecht, Utrecht (Netherlands); Keil, M.; Kugathasan, T. [CERN, 1210 Geneva 23 (Switzerland); Kim, D. [Dongguk and Yonsei University, Seoul (Korea, Republic of); Kim, J. [Pusan National University, Busan (Korea, Republic of); Lattuca, A. [University of Torino, Torino (Italy); INFN (Italy); Marin Tobon, C.A. [CERN, 1210 Geneva 23 (Switzerland); Marras, D. [University of Cagliari, Cagliari (Italy); INFN (Italy); Mager, M.; Martinengo, P. [CERN, 1210 Geneva 23 (Switzerland); Mazza, G. [University of Torino, Torino (Italy); INFN (Italy); and others

    2015-06-11

    Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented.

  12. A 4k-Pixel CTIA Readout for Far IR Photodetector Arrays Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to design a low noise, two-side buttable, 64x64 readout multiplexer with the following key design features: 1- By far the largest readout array developed...

  13. Performance of hybrid photon detector prototypes with encapsulated silicon pixel detector and readout for the RICH counters of LHCb

    International Nuclear Information System (INIS)

    Campbell, M.; George, K.A.; Girone, M.; Gys, T.; Jolly, S.; Piedigrossi, D.; Riedler, P.; Rozema, P.; Snoeys, W.; Wyllie, K.

    2003-01-01

    These proceedings report on the performance of the latest prototype pixel hybrid photon detector in preparation for the LHCb Ring Imaging Cherenkov detectors. The prototype encapsulates a silicon pixel detector bump-bonded to a binary read-out chip with short (25 ns) peaking time and low ( - ) detection threshold. A brief description of the prototype is given, followed by the preliminary results of the characterisation of the prototype behaviour when tested using a low intensity pulsed light emitting diode. The results obtained are in good agreement with those obtained using previous prototypes. The proceedings conclude with a summary of the current status and future plans

  14. arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

    CERN Document Server

    Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

    The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

  15. arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

    CERN Document Server

    Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

    2018-02-02

    The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

  16. A High-Speed, Event-Driven, Active Pixel Sensor Readout for Photon-Counting Microchannel Plate Detectors

    Science.gov (United States)

    Kimble, Randy A.; Pain, Bedabrata; Norton, Timothy J.; Haas, J. Patrick; Oegerle, William R. (Technical Monitor)

    2002-01-01

    Silicon array readouts for microchannel plate intensifiers offer several attractive features. In this class of detector, the electron cloud output of the MCP intensifier is converted to visible light by a phosphor; that light is then fiber-optically coupled to the silicon array. In photon-counting mode, the resulting light splashes on the silicon array are recognized and centroided to fractional pixel accuracy by off-chip electronics. This process can result in very high (MCP-limited) spatial resolution while operating at a modest MCP gain (desirable for dynamic range and long term stability). The principal limitation of intensified CCD systems of this type is their severely limited local dynamic range, as accurate photon counting is achieved only if there are not overlapping event splashes within the frame time of the device. This problem can be ameliorated somewhat by processing events only in pre-selected windows of interest of by using an addressable charge injection device (CID) for the readout array. We are currently pursuing the development of an intriguing alternative readout concept based on using an event-driven CMOS Active Pixel Sensor. APS technology permits the incorporation of discriminator circuitry within each pixel. When coupled with suitable CMOS logic outside the array area, the discriminator circuitry can be used to trigger the readout of small sub-array windows only when and where an event splash has been detected, completely eliminating the local dynamic range problem, while achieving a high global count rate capability and maintaining high spatial resolution. We elaborate on this concept and present our progress toward implementing an event-driven APS readout.

  17. Development and characterization of diamond and 3D-silicon pixel detectors with ATLAS-pixel readout electronics

    Energy Technology Data Exchange (ETDEWEB)

    Mathes, Markus

    2008-12-15

    Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10{sup 16} particles per cm{sup 2} per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 x 50 {mu}m{sup 2} have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm{sup 2} and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 x 6 cm{sup 2}). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection inside a pixel cell as well as the charge sharing between adjacent pixels was studied using a high energy particle beam. (orig.)

  18. Development and characterization of diamond and 3D-silicon pixel detectors with ATLAS-pixel readout electronics

    International Nuclear Information System (INIS)

    Mathes, Markus

    2008-12-01

    Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10 16 particles per cm 2 per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 x 50 μm 2 have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm 2 and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 x 6 cm 2 ). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection inside a pixel cell as well as the charge sharing between adjacent pixels was studied using a high energy particle beam. (orig.)

  19. Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Trimpl, M.

    2005-12-15

    The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

  20. Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

    International Nuclear Information System (INIS)

    Trimpl, M.

    2005-12-01

    The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

  1. The BTeV main spectrometer

    International Nuclear Information System (INIS)

    Sheldon, P.D.

    2001-01-01

    BTeV is a second generation B-factory experiment that will use a double-arm, forward spectrometer in the C0 experimental hall at the Fermilab Tevatron. I will describe the motivation and design of the 'main spectrometer', consisting of a ring-imaging Cherenkov system for charged particle identification, an electromagnetic calorimeter of lead-tungstate crystals, a proportional tube muon system with magnetized filtering steel, and a straw-tube and silicon strip charged particle tracking system

  2. BTeV trigger/DAQ innovations

    International Nuclear Information System (INIS)

    Votava, Margaret

    2005-01-01

    The BTeV experiment was a collider based high energy physics (HEP) B-physics experiment proposed at Fermilab. It included a large-scale, high speed trigger/data acquisition (DAQ) system, reading data off the detector at 500 Gbytes/sec and writing to mass storage at 200 Mbytes/sec. The online design was considered to be highly credible in terms of technical feasibility, schedule and cost. This paper will give an overview of the overall trigger/DAQ architecture, highlight some of the challenges, and describe the BTeV approach to solving some of the technical challenges. At the time of termination in early 2005, the experiment had just passed its baseline review. Although not fully implemented, many of the architecture choices, design, and prototype work for the online system (both trigger and DAQ) were well on their way to completion. Other large, high-speed online systems may have interest in the some of the design choices and directions of BTeV, including (a) a commodity-based tracking trigger running asynchronously at full rate, (b) the hierarchical control and fault tolerance in a large real time environment, (c) a partitioning model that supports offline processing on the online farms during idle periods with plans for dynamic load balancing, and (d) an independent parallel highway architecture

  3. First functionality tests of a 64 × 64 pixel DSSC sensor module connected to the complete ladder readout

    Science.gov (United States)

    Donato, M.; Hansen, K.; Kalavakuru, P.; Kirchgessner, M.; Kuster, M.; Porro, M.; Reckleben, C.; Turcato, M.

    2017-03-01

    The European X-ray Free Electron Laser (XFEL.EU) will provide every 0.1 s a train of 2700 spatially coherent ultrashort X-ray pulses at 4.5 MHz repetition rate. The Small Quantum Systems (SQS) instrument and the Spectroscopy and Coherent Scattering instrument (SCS) operate with soft X-rays between 0.5 keV-6 keV. The DEPFET Sensor with Signal Compression (DSSC) detector is being developed to meet the requirements set by these two XFEL.EU instruments. The DSSC imager is a 1 mega-pixel camera able to store up to 800 single-pulse images per train. The so-called ladder is the basic unit of the DSSC detector. It is the single unit out of sixteen identical-units composing the DSSC-megapixel camera, containing all representative electronic components of the full-size system and allows testing the full electronic chain. Each DSSC ladder has a focal plane sensor with 128× 512 pixels. The read-out ASIC provides full-parallel readout of the sensor pixels. Every read-out channel contains an amplifier and an analog filter, an up-to 9 bit ADC and the digital memory. The ASIC amplifier have a double front-end to allow one to use either DEPFET sensors or Mini-SDD sensors. In the first case, the signal compression is a characteristic intrinsic of the sensor; in the second case, the compression is implemented at the first amplification stage. The goal of signal compression is to meet the requirement of single-photon detection capability and wide dynamic range. We present the first results of measurements obtained using a 64× 64 pixel DEPFET sensor attached to the full final electronic and data-acquisition chain.

  4. IRRADIATION MEASUREMENTS ON THE 0.25 micro m CMOS PIXEL READOUT TEST CHIP BY A 14 MEV NEUTRON FACILITY

    CERN Document Server

    Barbera, R; CERN. Geneva; Palmeri, A; Pappalardo, G S; Riggi, F; Di Liberto, S; Meddi, F; Sestito, S; Loi, D; Angelone, M; Badalà, A; Pillon, M

    2000-01-01

    ALICE-ITS-2000-24   Abstract   A test facility station with 14 MeV neutrons was arranged at the FNG-ENEA Laboratory in Frascati (Italy) for the characterization with respect to radiation tolerance of the prototype pixel readout chips in 0.25 m m IBM technology done in edgeless design. This facility could allow to test both the readout chips and the pilot chips for the pixel readout system. In fact, both ASICs will have to survive at the same radiation level foreseen for the innermost layer (r = 4 cm) of the Inner Tracker System (ITS) in the LHC-ALICE experiment. Two test chips were exposed to an overall flux of 1.3 x 1012 14 MeV neutrons/cm2, which is larger than the expected neutron flux in ALICE during 10 years data taking. No variation in the parameters defining the chip functionality (analog and digital currents, linearity, shapes of the signal, efficiency) was observed.

  5. Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

    Science.gov (United States)

    Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

    2018-03-01

    Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

  6. Performance and description of the upgraded readout with the new back-end electronics for the ATLAS Pixel detector

    CERN Document Server

    Yajima, Kazuki; The ATLAS collaboration

    2017-01-01

    LHC increased drastically its performance during the RUN2 data taking, starting from a peak instantaneous luminosity of up to $5\\times10^{33} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$ in 2015 to conclude with the record value of $1.4\\times10^{34} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$ in November 2016. The concurrent increase of the trigger rate and event size forced the ATLAS experiment to exploit its sub-detectors to the maximum, approaching and possibly overcoming the design parameters. The ATLAS Pixel data acquisition system was upgraded to avoid possible bandwidth limitations. Two upgrades of the read-out electronics have been done. The first one during 2015/16 YETS, when the outermost pixel layer (Layer-2) was upgraded and its bandwidth was doubled. This upgrade partly contributed to maintain the data taking efficiency of the Pixel detector at a relatively high level ($\\sim$99%) during the 2016 run. A similar upgrade of the read-out system for the middle layer (Layer-1) is ongoing during 2016/17 EYETS. The details o...

  7. A 4k-Pixel CTIA Readout for Far IR Photodetector Arrays, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to investigate the feasibility of developing a low noise, two-side buttable, 64x64 readout multiplexer with the following key design features: 1- By far...

  8. Comparison of three resistor network division circuits for the readout of 4×4 pixel SiPM arrays

    International Nuclear Information System (INIS)

    Stratos, David; Maria, Georgiou; Eleftherios, Fysikopoulos; George, Loudos

    2013-01-01

    The purpose of this study is to investigate the behavior of a flexible SensL's silicon photomultiplier array (SPMArray4) photodetector for possible applications in PET imaging. We have designed and evaluated three different resistor network division circuits to read out the signal outputs of a 4×4 pixel SiPM array. We have applied firstly (i) a symmetric resistive voltage division circuit, secondly (ii) a symmetric resistive charge division circuit and thirdly (iii) a charge division multiplexing resistor network reducing the 16 pixel outputs to 4 position signals. In the first circuit the SensL SPMArray4-A0 preamplification electronics and a SPMArray4-A1 evaluation board providing the 16 pixels voltage outputs were used, before the symmetric resistive voltage network. We reduced the 16 voltage signals firstly to 4X and 4Y coordinate signals. Then those signals were further reduced to 2X and 2Y position signals connected via a resistor network. In the second readout circuit we have used the same technique but without the preamplification stage. The third circuit is based on a discretized positioning circuit, which multiplexes the 16 signals from the SiPM array to 4 position signals. The 4 position signals (Xa, Xb, Yc and Yd) were digitized using a free running sampling technique. An FPGA (Spartan 6 LX16) was used for triggering and signal processing of the pulses. We acquired raw images and energy histograms of a BGO and a CsI:Na pixilated scintillator under 22 Na excitation. A clear visualization of the discrete 2×2×5 mm 3 pixilated BGO scintillator elements as well as the 1×1×5 mm 3 pixilated CsI:Na crystal array was achieved with all applied readout circuits. The symmetric resistive charge division circuit provides higher peak to valley ratio than the other readout circuits. Τhe sensitivity and the energy resolution remained almost constant for the three circuits

  9. The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    CERN Document Server

    Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

    2013-01-01

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

  10. A pixel readout chip for 10-30 MRad in standard 0.25 mu m CMOS

    CERN Document Server

    Campbell, M; Burns, M; Cantatore, E; Casagrande, L; Delmastro, M; Dinapoli, R; Faccio, F; Heijne, Erik H M; Jarron, Pierre; Lupták, M; Marchioro, A; Martinengo, P; Minervini, D; Morel, M; Pernigotti, E; Ropotar, I; Snoeys, W; Wyllie, Ken H

    1999-01-01

    A radiation tolerant pixel detector readout chip has been developed in a commercial 0.25 mu m CMOS process. The chip is a matrix of two columns of 65 identical cells. Each readout cell comprises a preamplifier, a shaper filter, a discriminator, a delay line and readout logic. The chip occupies 10 mm/sup 2/, and contains about 50000 transistors. Electronic noise (~220 e rms) and threshold dispersion (~160 e rms) allow operation at 1500 e average threshold. The radiation tolerance of this mixed mode analog-digital circuit has been enhanced by designing NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The chip, which was developed at CERN for the ALICE and LHCb experiments, was still operational after receiving 3.6*10/sup 13/ protons over an area of 2 mm *2 mm. Other chips were irradiated with X-rays and remained fully functional up to 30 Mrad(SiO2) with only minor changes in analog parameters. These results indicate that careful use of deep submicron CMOS technologies can lea...

  11. The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

    CERN Document Server

    Fu, Y et al.

    2014-01-01

    Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256×256 pixels organized in a square pixel-array with 55 µm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

  12. The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

    CERN Document Server

    Marconi, S.; Placidi, P.; Christiansen, J.; Hemperek, T.

    2014-01-01

    The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger late...

  13. Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

    International Nuclear Information System (INIS)

    Unno, Y.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.

    2017-01-01

    We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n + -in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

  14. A pixel unit-cell targeting 16 ns resolution and radiation hardness in a column read-out particle vertex detector

    International Nuclear Information System (INIS)

    Wright, M.; Millaud, J.; Nygren, D.

    1992-10-01

    A pixel unit cell (PUC) circuit architecture, optimized for a column read out architecture, is reported. Each PUC contains an integrator, active filter, comparator, and optional analog store. The time-over-threshold (TOT) discriminator allows an all-digital interface to the array periphery readout while passing an analog measure of collected charge. Use of (existing) radiation hard processes, to build a detector bump-bonded to a pixel readout array, is targeted. Here, emphasis is on a qualitative explanation of how the unique circuit implementation benefits operation for Super Collider (SSC) detector application

  15. Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

    CERN Document Server

    Snoeys, W; Burns, M; Campbell, M; Cantatore, E; Carrer, N; Casagrande, L; Cavagnoli, A; Dachs, C; Di Liberto, S; Formenti, F; Giraldo, A; Heijne, Erik H M; Jarron, Pierre; Letheren, M F; Marchioro, A; Martinengo, P; Meddi, F; Mikulec, B; Morando, M; Morel, M; Noah, E; Paccagnella, A; Ropotar, I; Saladino, S; Sansen, Willy; Santopietro, F; Scarlassara, F; Segato, G F; Signe, P M; Soramel, F; Vannucci, Luigi; Vleugels, K

    2000-01-01

    A new pixel readout prototype has been developed at CERN for high- energy physics applications. This full mixed mode circuit has been implemented in a commercial 0.5 mu m CMOS technology. Its radiation tolerance has been enhanced by designing all NMOS transistors in enclosed geometry and introducing guardrings wherever necessary. The technique is explained and its effectiveness demonstrated on various irradiation measurements on individual transistors and on the prototype. Circuit performance started to degrade only after a total dose of 600 krad-1.7 Mrad depending on the type of radiation. 10 keV X-rays, /sup 60/Co gamma-rays, 6.5 MeV protons, and minimum ionizing particles were used. Implications of this layout approach on the circuit design and perspectives for even deeper submicron technologies are discussed. (20 refs).

  16. LHC1: a semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

    International Nuclear Information System (INIS)

    Heijne, E.H.M.; Antinori, F.; Barberis, D.

    1996-01-01

    The Omega3/LHC1 pixel detector readout chip comprises a matrix of 128 x 16 readout cells of 50 μm x 500 μm and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking. First results have been obtained from electrical tests of a chip without detector as well as from source measurements. The electronic noise without detector is ∼100 e - rms. The lowest threshold setting is close to 2000 e - and non-uniformity has been measured to be better than 450 e - rms at 5000 e - threshold. A timewalk of <10 ns and a precision of <6 ns rms on a delay of 2 μs have been measured. The results may be improved by further optimization. (orig.)

  17. GridPix: An integrated readout system for gaseous detectors with a pixel chip as anode

    Energy Technology Data Exchange (ETDEWEB)

    Graaf, Harry van der [NIKHEF, Kruislaan 409, 1098 SJ Amsterdam (Netherlands)], E-mail: vdgraaf@nikhef.nl

    2007-10-01

    GridPix is a gas-filled detector in which a Micro Pattern Gas Detector is combined with a CMOS pixel chip. In a next step, a procedure to construct a grid onto a Si wafer, using chip production technology ('wafer post-processing'), has been developed. Protection against discharges are under study, and an ageing test of a Micromegas chamber has been carried out, after verifying the chamber's proportionality at a very high dose rate. The GridPix detector can be applied as X-ray imaging device. With a drift gap of only 1 mm, GridPix could be well applied as radiation hard, low power, (and therefore) low-mass vertex (track) detector. New developments in CMOS pixel chips, forming the core of the detector, are presented.

  18. Readout cross-talk for alpha-particle measurements in a pixelated sensor system

    International Nuclear Information System (INIS)

    Norlin, B.; Reza, S.; Krapohl, D.; Fröjdh, E.; Thungström, G.

    2015-01-01

    Simulations in Medici are performed to quantify crosstalk and charge sharing in a hybrid pixelated silicon detector. Crosstalk and charge sharing degrades the spatial and spectral resolution of single photon processing X-ray imaging systems. For typical medical X-ray imaging applications, the process is dominated by charge sharing between the pixels in the sensor. For heavier particles each impact generates a large amount of charge and the simulation seems to over predict the charge collection efficiency. This indicates that some type of non modelled degradation of the charge transport efficiency exists, like the plasma effect where the plasma might shield the generated charges from the electric field and hence distorts the charge transport process. Based on the simulations it can be reasoned that saturation of the amplifiers in the Timepix system might generate crosstalk that increases the charge spread measured from ion impact on the sensor

  19. Spectroscopy study of imaging devices based on silicon Pixel Array Detector coupled to VATAGP7 read-out chips

    International Nuclear Information System (INIS)

    Linhart, V; Lacasta, C; Llosa, G; Stankova, V; Burdette, D; Chessi, E; Cochran, E; Honscheid, K; Kagan, H; Weilhammer, P; Cindro, V; Grosicar, B; Mikuz, M; Studen, A; Zontar, D; Clinthorne, N H

    2011-01-01

    Spectroscopic and timing response studies have been conducted on a detector module consisting of a silicon Pixel Array Detector bonded on two VATAGP7 read-out chips manufactured by Gamma-Medica Ideas using laboratory gamma sources and the internal calibration facilities (the calibration system of the read-out chips). The performed tests have proven that the chips have (i) non-linear calibration curves which can be approximated by power functions, (ii) capability to measure the energy of photons with energy resolution better than 2 keV (exact range and resolution depend on experimental setup), (iii) the internal calibration facility which provides 6 out of 16 available internal calibration charges within our region of interest (spanning the Compton edge of 511 keV photons). The peaks induced by the internal calibration facility are suitable for a fit of the calibration curves. However, they are not suitable for measurements of equivalent noise charge because their full width at half maximum varies with their amplitude. These facts indicate that the VATAGP7 chips are useful and precise tools for a wide variety of spectroscopic devices. We have also explored time walk of the module and peaking time of the spectroscopy signals provided by the chips. We have observed that (iv) the time walk is caused partly by the peaking time of the signals provided by the fast shaper of the chips and partly by the timing uncertainty related to the varying position of the photon interaction, (v) the peaking time of the spectroscopy signals provided by the chips increases with increasing pulse height.

  20. Toward VIP-PIX: A Low Noise Readout ASIC for Pixelated CdTe Gamma-Ray Detectors for Use in the Next Generation of PET Scanners.

    Science.gov (United States)

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Puigdengoles, Carles; Lorenzo, Gianluca De; Martínez, Ricardo

    2013-08-01

    VIP-PIX will be a low noise and low power pixel readout electronics with digital output for pixelated Cadmium Telluride (CdTe) detectors. The proposed pixel will be part of a 2D pixel-array detector for various types of nuclear medicine imaging devices such as positron-emission tomography (PET) scanners, Compton gamma cameras, and positron-emission mammography (PEM) scanners. Each pixel will include a SAR ADC that provides the energy deposited with 10-bit resolution. Simultaneously, the self-triggered pixel which will be connected to a global time-to-digital converter (TDC) with 1 ns resolution will provide the event's time stamp. The analog part of the readout chain and the ADC have been fabricated with TSMC 0.25 μ m mixed-signal CMOS technology and characterized with an external test pulse. The power consumption of these parts is 200 μ W from a 2.5 V supply. It offers 4 switchable gains from ±10 mV/fC to ±40 mV/fC and an input charge dynamic range of up to ±70 fC for the minimum gain for both polarities. Based on noise measurements, the expected equivalent noise charge (ENC) is 65 e - RMS at room temperature.

  1. Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

    International Nuclear Information System (INIS)

    Erdinger, Florian

    2016-01-01

    The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

  2. FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

    2004-01-01

    A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

  3. The Read-Out Driver (ROD) card for the ATLAS experiment: commissioning for the IBL detector and upgrade studies for the Pixel Layers 1 and 2

    CERN Document Server

    Travaglini, R; The ATLAS collaboration; Bindi, M; Falchieri, D; Gabrielli, A; Lama, L; Chen, S P; Hsu, S C; Hauck, S; Kugel, A; Flick, T; Wensing, M

    2013-01-01

    The upgrade of the ATLAS experiment at LHC foresees the insertion of an innermost silicon layer, called Insertable B-layer (IBL). IBL read-out system will be equipped with new electronics. The Readout-Driver card (ROD) is a VME board devoted to data processing, configuration and control. A pre-production batch has been delivered in order to perform tests with instrumented slices of the overall acquisition chain, aiming to finalize strategies for system commissioning. In this contribution both setups and results will be described, as well as preliminary studies on changes in order to adopt the ROD for the ATLAS Pixel Layers 1 and 2.

  4. Submillisecond X-ray photon correlation spectroscopy?from a pixel array detector with fast?dual gating and no readout dead-time

    OpenAIRE

    Zhang, Qingteng; Dufresne, Eric M.; Grybos, Pawel; Kmon, Piotr; Maj, Piotr; Narayanan, Suresh; Deptuch, Grzegorz W.; Szczygiel, Robert; Sandy, Alec

    2016-01-01

    Small-angle scattering X-ray photon correlation spectroscopy (XPCS) studies were performed using a novel photon-counting pixel array detector with dual counters for each pixel. Each counter can be read out independently from the other to ensure there is no readout dead-time between the neighboring frames. A maximum frame rate of 11.8?kHz was achieved. Results on test samples show good agreement with simple diffusion. The potential of extending the time resolution of XPCS beyond the limit set ...

  5. Submillisecond X-ray photon correlation spectroscopy from a pixel array detector with fast dual gating and no readout dead-time.

    Science.gov (United States)

    Zhang, Qingteng; Dufresne, Eric M; Grybos, Pawel; Kmon, Piotr; Maj, Piotr; Narayanan, Suresh; Deptuch, Grzegorz W; Szczygiel, Robert; Sandy, Alec

    2016-05-01

    Small-angle scattering X-ray photon correlation spectroscopy (XPCS) studies were performed using a novel photon-counting pixel array detector with dual counters for each pixel. Each counter can be read out independently from the other to ensure there is no readout dead-time between the neighboring frames. A maximum frame rate of 11.8 kHz was achieved. Results on test samples show good agreement with simple diffusion. The potential of extending the time resolution of XPCS beyond the limit set by the detector frame rate using dual counters is also discussed.

  6. Performance of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon Pixel readout for Cherenkov ring detection

    CERN Document Server

    Alemi, M; Bibby, J H; Campbell, M; Duane, A; Easo, S; Gys, Thierry; Halley, A W; Piedigrossi, D; Puertolas, D; Rosso, E; Simmons, B; Snoeys, W; Websdale, David M; Wotton, S A; Wyllie, Ken H

    1999-01-01

    We report on the first test beam performance of a hybrid photon detector prototype, using binary readout electronics, intended for use in the ring imaging Cherenkov detectors of the LHCb experiment at the CERN Large Hadron Collider. The photon detector is based on a cross-focussed image intensifier tube geometry. The anode consists of a silicon pixel array bump-bonded to a binary readout chip with matching pixel electronics. The detector has been installed in a quarter-scale prototype vessel of the LHCb ring imaging Cherenkov system. Focussed ring images produced by 120 GeV/c negative pions traversing an air radiator have been recorded. The observed light yield and Cherenkov angle resolution are discussed.

  7. Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

    CERN Document Server

    Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

    2009-01-01

    In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

  8. Simulation of digital pixel readout chip architectures with the RD53 SystemVerilog-UVM verification environment using Monte Carlo physics data

    International Nuclear Information System (INIS)

    Conti, E.; Marconi, S.; Christiansen, J.; Placidi, P.; Hemperek, T.

    2016-01-01

    The simulation and verification framework developed by the RD53 collaboration is a powerful tool for global architecture optimization and design verification of next generation hybrid pixel readout chips. In this paper the framework is used for studying digital pixel chip architectures at behavioral level. This is carried out by simulating a dedicated, highly parameterized pixel chip description, which makes it possible to investigate different grouping strategies between pixels and different latency buffering and arbitration schemes. The pixel hit information used as simulation input can be either generated internally in the framework or imported from external Monte Carlo detector simulation data. The latter have been provided by both the CMS and ATLAS experiments, featuring HL-LHC operating conditions and the specifications related to the Phase 2 upgrade. Pixel regions and double columns were simulated using such Monte Carlo data as inputs: the performance of different latency buffering architectures was compared and the compliance of different link speeds with the expected column data rate was verified

  9. Fabrication and characterization of n-on-n silicon pixel detectors compatible with the Medipix2 readout chip

    International Nuclear Information System (INIS)

    Zorzi, N.; Bisogni, M.G.; Boscardin, M.; Dalla Betta, G.-F.; Gregori, P.; Novelli, M.; Piemonte, C.; Quattrocchi, M.; Ronchin, S.; Rosso, V.

    2005-01-01

    Pixel detectors for mammographic applications have been fabricated at ITC-irst on 800 μm thick silicon wafers adopting a double side n + -on-n fabrication technology. The activity aims at increasing the X-ray detection efficiency in the energy range of interest minimizing the risk of electrical discharges in hybrid systems operating at high voltages. The detectors, having a layout compatible with the Medipix2 photon counting chip, feature two different design solutions for the p-isolation between neighboring n + -pixels. We report on the characterization of the fabrication process and on preliminary results of electrical measurements on full detectors and pixel test structures. In particular, we found that the detectors can be reliably operated above the full depletion voltage regardless of the isolation design, that however, impacts the performances in terms of current-voltage characteristics, single pixel currents, inter-pixel resistances and inter-pixel capacitances

  10. Pixel readout chips in deep submicron CMOS for ALICE and LHCb tolerant to 10 Mrad and beyond

    NARCIS (Netherlands)

    Snoeys, W.; Burns, M.; Campbell, M.; Cantatore, E.; Cencelli, V.; Dinapoli, R.; Heijne, E.; Jarron, P.; Lamanna, P.; Minervini, D.; Morel, M.; O'shea, V.; Quiquempoix, V.; San Segundo Bello, D.; van Koningsveld, B.; Wyllie, K.

    The ALICE1LHCB chip is a mixed-mode integrated circuit designed to read out silicon pixel detectors for two different applications: particle tracking in the ALICE Silicon Pixel Detector and particle identification in the LHCb Ring Imaging Cherenkov detector. To satisfy the different needs for these

  11. Experimental characterization of the 192 channel Clear-PEM frontend ASIC coupled to a multi-pixel APD readout of LYSO:Ce crystals

    Energy Technology Data Exchange (ETDEWEB)

    Albuquerque, Edgar; Bexiga, Vasco [INESC-ID, Rua Alves Redol 9, 1000-129 Lisboa (Portugal); Bugalho, Ricardo; Carrico, Bruno; Ferreira, Claudia S.; Ferreira, Miguel [LIP, Avenida Elias Garcia 14-1, 1000-149 Lisboa (Portugal); Godinho, Joaquim [INOV, Rua Alves Redol 9, 1000-129 Lisboa (Portugal); Goncalves, Fernando; Leong, Carlos [INESC-ID, Rua Alves Redol 9, 1000-129 Lisboa (Portugal); Lousa, Pedro [INOV, Rua Alves Redol 9, 1000-129 Lisboa (Portugal); Machado, Pedro [INESC-ID, Rua Alves Redol 9, 1000-129 Lisboa (Portugal); Moura, Rui [LIP, Avenida Elias Garcia 14-1, 1000-149 Lisboa (Portugal); Neves, Pedro [INOV, Rua Alves Redol 9, 1000-129 Lisboa (Portugal); Ortigao, Catarina [LIP, Avenida Elias Garcia 14-1, 1000-149 Lisboa (Portugal); Piedade, Fernando [INOV, Rua Alves Redol 9, 1000-129 Lisboa (Portugal); Pinheiro, Joao F. [LIP, Avenida Elias Garcia 14-1, 1000-149 Lisboa (Portugal); Rego, Joel [INOV, Rua Alves Redol 9, 1000-129 Lisboa (Portugal); Rivetti, Angelo [INFN, Torino (Italy); Rodrigues, Pedro [LIP, Avenida Elias Garcia 14-1, 1000-149 Lisboa (Portugal)], E-mail: psilva@lip.pt; Silva, Jose C. [LIP, Avenida Elias Garcia 14-1, 1000-149 Lisboa (Portugal)] (and others)

    2009-01-21

    In the framework of the Clear-PEM project for the construction of a high-resolution scanner for breast cancer imaging, a very compact and dense frontend electronics system has been developed for readout of multi-pixel S8550 Hamamatsu APDs. The frontend electronics are instrumented with a mixed-signal Application-Specific Integrated Circuit (ASIC), which incorporates 192 low-noise charge pre-amplifiers, shapers, analog memory cells and digital control blocks. Pulses are continuously stored in memory cells at clock frequency. Channels above a common threshold voltage are readout for digitization by off-chip free-sampling ADCs. The ASIC has a size of 7.3x9.8mm{sup 2} and was implemented in a AMS 0.35{mu}m CMOS technology. In this paper the experimental characterization of the Clear-PEM frontend ASIC, reading out multi-pixel APDs coupled to LYSO:Ce crystal matrices, is presented. The chips were mounted on a custom test board connected to six APD arrays and to the data acquisition system. Six 32-pixel LYSO:Ce crystal matrices coupled on both sides to APD arrays were readout by two test boards. All 384 channels were operational. The chip power consumption is 660 mW (3.4 mW per channel). A very stable behavior of the chip was observed, with an estimated ENC of 1200-1300e{sup -} at APD gain 100. The inter-channel noise dispersion and mean baseline variation is less than 8% and 0.5%, respectively. The spread in the gain between different channels is found to be 1.5%. Energy resolution of 16.5% at 511 keV and 12.8% at 662 keV has been measured. Timing measurements between the two APDs that readout the same crystal is extracted and compared with detailed Monte Carlo simulations. At 511 keV the measured single photon time RMS resolution is 1.30 ns, in very good agreement with the expected value of 1.34 ns.

  12. An integrated readout system for drift chambers: the application of monolithic CMOS pixel sensors as segmented direct anode

    NARCIS (Netherlands)

    Campbell, M.; Heijne, E.H.M.; Llopart, X.; Chefdeville, M.A.; Colas, P.; Giomataris, Y.; Colijn, A.P.; Fornaini, A.; Fornaini, A.; van der Graaf, H.; Kluit, P.; Timmermans, J.; Timmermans, J.; Visschers, J.L.; Schmitz, Jurriaan

    2006-01-01

    A small TPC has been read out by means of a MediPix2 readout chip as direct anode. A Micromegas foil was placed 50 μm above the chip, and electron multiplication occurred in the gap. With a He/Isobutane 80/20 mixture, gas multiplication factors up to tens of thousands were achieved, resulting in an

  13. Performance of the Insertable B-Layer for the ATLAS Pixel Detector during Quality Assurance and a Novel Pixel Detector Readout Concept based on PCIe

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00356268; Pernegger, Heinz

    2016-07-27

    During the first long shutdown of the LHC the Pixel detector has been upgraded with a new 4th innermost layer, the Insertable B-Layer (IBL). The IBL will increase the tracking performance and help with higher than nominal luminosity the LHC will produce. The IBL is made up of 14 staves and in total 20 staves have been produced for the IBL. This thesis presents the results of the final quality tests performed on these staves in an detector-like environment, in order to select the 14 best of the 20 staves for integration onto the detector. The test setup as well as the testing procedure is introduced and typical results of each testing stage are shown and discussed. The overall performance of all staves is presented in regards to: tuning performance, radioactive source measurements, and number of failing pixels. Other measurement, which did not directly impact the selection of staves, but will be important for the operation of the detector or production of a future detector, are included. Based on the experienc...

  14. SiC 10um-Pitch UV Imaging Array and APD with Active Pixel Readout, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — CoolCAD Electronics, LLC, proposes to design and fabricate a SiC UV detector array with a 10μm pixel pitch, sensitive to EUV, VUV and Deep UV. SiC is a visible-blind...

  15. Development of depth encoding small animal PET detectors using dual-ended readout of pixelated scintillator arrays with SiPMs.

    Science.gov (United States)

    Kuang, Zhonghua; Sang, Ziru; Wang, Xiaohui; Fu, Xin; Ren, Ning; Zhang, Xianming; Zheng, Yunfei; Yang, Qian; Hu, Zhanli; Du, Junwei; Liang, Dong; Liu, Xin; Zheng, Hairong; Yang, Yongfeng

    2018-02-01

    The performance of current small animal PET scanners is mainly limited by the detector performance and depth encoding detectors are required to develop PET scanner to simultaneously achieve high spatial resolution and high sensitivity. Among all depth encoding PET detector approaches, dual-ended readout detector has the advantage to achieve the highest depth of interaction (DOI) resolution and spatial resolution. Silicon photomultiplier (SiPM) is believed to be the photodetector of the future for PET detector due to its excellent properties as compared to the traditional photodetectors such as photomultiplier tube (PMT) and avalanche photodiode (APD). The purpose of this work is to develop high resolution depth encoding small animal PET detector using dual-ended readout of finely pixelated scintillator arrays with SiPMs. Four lutetium-yttrium oxyorthosilicate (LYSO) arrays with 11 × 11 crystals and 11.6 × 11.6 × 20 mm 3 outside dimension were made using ESR, Toray and BaSO 4 reflectors. The LYSO arrays were read out with Hamamatsu 4 × 4 SiPM arrays from both ends. The SiPM array has a pixel size of 3 × 3 mm 2 , 0.2 mm gap in between the pixels and a total active area of 12.6 × 12.6 mm 2 . The flood histograms, DOI resolution, energy resolution and timing resolution of the four detector modules were measured and compared. All crystals can be clearly resolved from the measured flood histograms of all four arrays. The BaSO 4 arrays provide the best and the ESR array provides the worst flood histograms. The DOI resolution obtained from the DOI profiles of the individual crystals of the four array is from 2.1 to 2.35 mm for events with E > 350 keV. The DOI ratio variation among crystals is bigger for the BaSO 4 arrays as compared to both the ESR and Toray arrays. The BaSO 4 arrays provide worse detector based DOI resolution. The photopeak amplitude of the Toray array had the maximum change with depth, it provides the worst energy resolution of

  16. Detection of single electrons by means of a Micromegas-covered Medi Pix2 pixel CMOS readout circuit

    CERN Document Server

    Campbell, Michael; Colas, Paul; Colijn, Auke Pieter; Fornaini, Alessandro; Giomataris, Ioanis; Heijne, Erik H M; Kluit, Peter; Llopart-Cudie, Xavier; Schmitz, Jurriaan; Timmermans, J; Visschers, Jan L; Van der Graaf, Harry

    2005-01-01

    A small drift chamber was read out by means of a MediPix2 readout chip as a direct anode. A Micromegas foil was placed 50 mu m above the chip, and electron multiplication occurred in the gap. With a He /isobutane 80/20 mixture, gas multiplication factors up to tens of thousands were achieved, resulting in an efficiency for detecting single electrons of better than 90 %. We recorded many frames containing 2D images with tracks from cosmic muons. Along these tracks, electron clusters were observed, as well as delta -rays.

  17. 32k Channel Readout IC for Single Photon Counting Pixel Detectors with 75μm Pitch, Dead Time of 85 ns, 9 e- rms Offset Spread and 2% rms Gain Spread

    Science.gov (United States)

    Grybos, P.; Kmon, P.; Maj, P.; Szczygiel, R.

    2016-04-01

    This paper presents a readout integrated circuit called UFXC32k, designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The UFXC32k integrated circuit, designed in a CMOS 130 nm process, contains about 50 million transistors in the area of 9.64 mm × 20.15 mm. The core of the IC is a matrix of 128 × 256 square-shaped pixels of 75 μm pitch. Each pixel contains a charge sensitive amplifier, a shaper, two discriminators, and two 14-bit ripple counters. The analog front-end electronics allow processing of sensor signals of both polarities (holes and electrons). The UFXC32k chip is bumpbonded to a pixel silicon sensor and is fully characterized using X-ray radiation. The measured equivalent noise charge for the standard settings is equal to 123 e- rms (for the peaking time of 40 ns) and each pixel dissipates 26 μW. Thanks to the use of trim blocks working in each pixel independently, an effective offset spread calculated to the input is only 9 e- rms with a gain spread of 2%. The maximum count rate per pixel depends mainly on effective CSA feedback resistance. Dead time in the front end can be set as low as 85 ns. In the continuous readout mode, a user can select the number of bits read out from each pixel to optimize the UFXC32k frame rate, e.g., for a readout of 2 bits/pixel with 200 MHz clock, the frame rate is equal to 23 kHz.

  18. Distributed and/or grid-oriented approach to BTeV data analysis

    International Nuclear Information System (INIS)

    Joel N. Butler email = joel.butler@fnal.gov

    2002-01-01

    The BTeV collaboration will record approximately 2 petabytes of raw data per year. It plans to analyze this data using the distributed resources of the collaboration as well as dedicated resources, primarily residing in the very large BTeV trigger farm, and resources accessible through the developing world-wide data grid. The data analysis system is being designed from the very start with this approach in mind. In particular, we plan a fully disk-based data storage system with multiple copies of the data distributed across the collaboration to provide redundancy and to optimize access. We will also position ourself to take maximum advantage of shared systems, as well as dedicated systems, at our collaborating institutions

  19. The application of Tiny Triplet Finder (TTF) in BTeV pixel trigger

    International Nuclear Information System (INIS)

    Wu, Jin-Yuan; Wang, M.; Gottschalk, E.; Shi, Z.; Fermilab

    2006-01-01

    We describe a track segment recognition scheme called the Tiny Triplet Finder (TTF) that involves grouping of three hits satisfying a constraint such as forming of a straight line. The TTF performs this O(n 3 ) function in O(n) time, where n is number of hits in each detector plane. The word ''tiny'' reflects the fact that the FPGA resource usage is small. The number of logic elements needed for the TTF is O(Nlog(N)), where N is the number of bins in the coordinate considered, which for large N, is significantly smaller than O(N 2 ) needed for typical implementations of similar functions. The TTF is also suitable for software implementations as well as many other pattern recognition problems

  20. Operational Experience with the ATLAS Pixel Detector

    CERN Document Server

    Lantzsch, Kerstin; The ATLAS collaboration

    2016-01-01

    Run 2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). In addition the Pixel detector was refurbished with new service quarter panels to recover about 3% of defective modules lost during run 1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning, operation and performance of the 4-layer Pixel Detector will be presented.

  1. Status of the ATLAS pixel detector

    CERN Document Server

    Saavedra Aldo, F

    2005-01-01

    The ATLAS pixel detector is currently being constructed and will be installed in 2006 to be ready for commissioning at the Large Hadron Collider. The complete pixel detector is composed of three concentric barrels and six disks that are populated by 1744 ATLAS Pixel modules. The main components of the pixel module are the readout electronics and the silicon sensor whose active region is instrumented with rectangular pixels. The module has been designed to be able to survive 10 years of operation within the ATLAS detector. A brief description of the pixel detector will be presented with results and problems encountered during the production stage.

  2. DAQ Hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment was extended by about 12 million pixels with the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented by employing newly designed read-out hardware, which supports the full detector bandwidth even for calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  3. Development of radiation hardened pixel sensors for charged particle detection

    CERN Document Server

    Koziel, Michal

    2014-01-01

    CMOS Pixel Sensors are being developed since a few years to equip vertex detectors for future high-energy physics experiments with the crucial advantages of a low material budget and low production costs. The features simultaneously required are a short readout time, high granularity and high tolerance to radiation. This thesis mainly focuses on the radiation tolerance studies. To achieve the targeted readout time (tens of microseconds), the sensor pixel readout was organized in parallel columns restricting in addition the readout to pixels that had collected the signal charge. The pixels became then more complex, and consequently more sensitive to radiation. Different in-pixel architectures were studied and it was concluded that the tolerance to ionizing radiation was limited to 300 krad with the 0.35- m fabrication process currently used, while the targeted value was several Mrad. Improving this situation calls for implementation of the sensors in processes with a smaller feature size which naturally imp...

  4. Direct readout of gaseous detectors with tiled CMOS circuits

    International Nuclear Information System (INIS)

    Visschers, J.L.; Blanco Carballo, V.; Chefdeville, M.; Colas, P.; Graaf, H. van der; Schmitz, J.; Smits, S.; Timmermans, J.

    2007-01-01

    A coordinated design effort is underway, exploring the three-dimensional direct readout of gaseous detectors by an anode plate equipped with a tiled array of many CMOS pixel readout ASICs, having amplification grids integrated on their topsides and being contacted on their backside

  5. Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system

    Energy Technology Data Exchange (ETDEWEB)

    Jinyuan Wu et al.

    2003-11-05

    A hardware hash sorter for the Fermilab BTeV Level 1 trigger system will be presented. The has sorter examines track-segment data before the data are sent to a system comprised of 2500 Level 1 processors, and rearranges the data into bins based on the slope of track segments. They have found that by using the rearranged data, processing time is significantly reduced allowing the total number of processors required for the Level 1 trigger system to be reduced. The hash sorter can be implemented in an FPGA that is already included as part of the design of the trigger system. Hash sorting has potential applications in a broad area in trigger and DAQ systems. It is a simple O(n) process and is suitable for FPGA implementation. Several implementation strategies will also be discussed in this document.

  6. Pixel Experiments

    DEFF Research Database (Denmark)

    Søndergaard, Karin; Petersen, Kjell Yngve; Augustesen, Christina

    2015-01-01

    Pixel Experiments The term pixel is traditionally defined as any of the minute elements that together constitute a larger context or image. A pixel has its own form and is the smallest unit seen within a larger structure. In working with the potentials of LED technology in architectural lighting...... design it became relevant to investigate the use of LEDs as the physical equivalent of a pixel as a design approach. In this book our interest has been in identifying how the qualities of LEDs can be used in lighting applications. With experiences in the planning and implementation of architectural...... lighting design in practice, one quickly experiences and realises that there are untapped potentials in the attributes of LED technology. In this research, speculative studies have been made working with the attributes of LEDs in architectural contexts, with the ambition to ascertain new strategies...

  7. Pixel Experiments

    DEFF Research Database (Denmark)

    Petersen, Kjell Yngve; Søndergaard, Karin; Augustesen, Christina

    2015-01-01

    Pixel Experiments The term pixel is traditionally defined as any of the minute elements that together constitute a larger context or image. A pixel has its own form and is the smallest unit seen within a larger structure. In working with the potentials of LED technology in architectural lighting...... for using LED lighting in lighting design practice. The speculative experiments that have been set-up have aimed to clarify the variables that can be used as parameters in the design of lighting applications; including, for example, the structuring and software control of light. The experiments also...... elucidate and exemplify already well-known problems in relation to the experience of vertical and horizontal lighting. Pixel Experiments exist as a synergy between speculative test setups and lighting design in practice. This book is one of four books that is published in connection with the research...

  8. Development of a Timepix3 readout system based on the Merlin readout system

    International Nuclear Information System (INIS)

    Crevatin, G.; Carrato, S.; Horswell, I.; Omar, D.; Tartoni, N.; Cautero, G.

    2015-01-01

    Timepix3 chip is a new ASIC specifically designed to readout hybrid pixel detectors. The main purpose of Timepix3 is to measure the time of arrival of events. This characteristic can be exploited very effectively to develop detectors for time resolved experiments at synchrotron radiation facilities. In order to investigate how the ASIC can be applied to synchrotron experiments the Merlin readout system, developed at Diamond for the Medipix3 ASIC, has been adapted to readout the Timepix3 ASIC. The first tests of the ASIC with pulse injection and with alpha particles show that its behaviour is consistent with its nominal characteristics

  9. Performance of ATLAS pixel detector prototype modules

    CERN Document Server

    Andreazza, A

    2003-01-01

    The ATLAS silicon pixel detector is the innermost tracking device of the ATLAS experiment at the LHC consisting of more than 1600 modules for a total sensitive area of about 1.5m**2 and over 70 million pixel cells. The concept is a hybrid of FE-chips bump bonded to the pixel sensor. The elementary pixel cell has 50mum multiplied by 400mum size. Pulse height measurement is provided by the time over threshold technique. The main issue in the design is the radiation hardness of both the sensitive detector and the readout electronics. Assemblies of readout electronics in deep sub-micron technology and oxygenated silicon sensor have been irradiated up to a fluence of 10 **1**5n//e //q/cm**2 and a dose of 60Mrad. The resolution, charge collection and efficiency have been measured in test beams.

  10. Hybrid pixel detector development for medical radiography

    International Nuclear Information System (INIS)

    Midgley, S.; Berry, A.; Benci, N.; Morton, S.; Phillips, D.; Smith, P.; Troja, S.; Lewis, R.

    2007-01-01

    A 7-year project has been initiated to develop hybrid pixel detectors for medical radiography. Crystalline semiconductor will be bonded to a pixellated readout chip where individual integrated circuits process each event, transferring the position, energy and timing information to the data acquisition controller. Chips will be tiled to produce a large area detector, capable of energy dispersive photon counting at moderate spatial resolution. Preliminary results from studies examining the design features and operation of the device are presented

  11. 3D, Flash, Induced Current Readout for Silicon Sensors

    Energy Technology Data Exchange (ETDEWEB)

    Parker, Sherwood I. [Univ. of Hawaii, Honolulu, HI (United States)

    2014-06-07

    A new method for silicon microstrip and pixel detector readout using (1) 65 nm-technology current amplifers which can, for the first time with silicon microstrop and pixel detectors, have response times far shorter than the charge collection time (2) 3D trench electrodes large enough to subtend a reasonable solid angle at most track locations and so have adequate sensitivity over a substantial volume of pixel, (3) induced signals in addition to, or in place of, collected charge

  12. XAMPS Detectors Readout ASIC for LCLS

    Energy Technology Data Exchange (ETDEWEB)

    Dragone, A; /SLAC; Pratte, J.F.; Rehak, P.; /Brookhaven; Carini, G.A.; /BNL, NSLS; Herbst, R.; /SLAC; O' Connor, P.; /Brookhaven; Siddons, D.P.; /BNL, NSLS

    2008-12-18

    An ASIC for the readout of signals from X-ray Active Matrix Pixel Sensor (XAMPS) detectors to be used at the Linac Coherent Light Source (LCLS) is presented. The X-ray Pump Probe (XPP) instrument, for which the ASIC has been designed, requires a large input dynamic range on the order of 104 photons at 8 keV with a resolution of half a photon FWHM. Due to the size of the pixel and the length of the readout line, large input capacitance is expected, leading to stringent requirement on the noise optimization. Furthermore, the large number of pixels needed for a good position resolution and the fixed LCLS beam period impose limitations on the time available for the single pixel readout. Considering the periodic nature of the LCLS beam, the ASIC developed for this application is a time-variant system providing low-noise charge integration, filtering and correlated double sampling. In order to cope with the large input dynamic range a charge pump scheme implementing a zero-balance measurement method has been introduced. It provides an on chip 3-bit coarse digital conversion of the integrated charge. The residual charge is sampled using correlated double sampling into analog memory and measured with the required resolution. The first 64 channel prototype of the ASIC has been fabricated in TSMC CMOS 0.25 {micro}m technology. In this paper, the ASIC architecture and performances are presented.

  13. Simulation of the D{sub s} semileptonic decay with the PANDA detector and experimental verification of the Micro-Vertex-Detector pixel readout ASIC with proton test beam

    Energy Technology Data Exchange (ETDEWEB)

    Cao, Lu

    2016-07-14

    The PANDA experiment will study a wide range of physics topics with beams of antiprotons incident on fixed proton or complex nuclear targets. One issue is the D{sub s} semileptonic decay, which is governed by the weak and strong forces. The interaction can be parameterized by a transition form factor. The performance of PANDA to measure the decay form factor of D{sup +}{sub s}→ηe{sup +}ν{sub e} is evaluated via Monte Carlo simulation. This thesis concentrates on describing the software development and the evaluation of the expected precision. A preliminary estimate of the expected count rate is obtained. In this measurement, it is essential to reconstruct the D{sub s} semileptonic decay with high efficiency and purity in order to overcome the many orders of magnitude higher background. The Micro-Vertex-Detector plays an import role in the whole tracking system. The rate capability and tracking performance of the recent ASIC prototype for the readout of the MVD is tested using a beam of high-energy protons.

  14. The Young-Feynman two-slits experiment with single electrons: Build-up of the interference pattern and arrival-time distribution using a fast-readout pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Frabboni, Stefano [Department of Physics, University of Modena and Reggio Emilia, Via G. Campi 213/a, 41125 Modena (Italy); CNR-Institute of Nanoscience-S3, Via G. Campi 213/a, 41125 Modena (Italy); Gabrielli, Alessandro [Department of Physics, University of Bologna, Viale B. Pichat 6/2, 40127 Bologna (Italy); INFN, Viale B. Pichat 6/2, 40127 Bologna (Italy); Carlo Gazzadi, Gian [CNR-Institute of Nanoscience-S3, Via G. Campi 213/a, 41125 Modena (Italy); Giorgi, Filippo [Department of Physics, University of Bologna, Viale B. Pichat 6/2, 40127 Bologna (Italy); INFN, Viale B. Pichat 6/2, 40127 Bologna (Italy); Matteucci, Giorgio [Department of Physics, University of Bologna, Viale B. Pichat 6/2, 40127 Bologna (Italy); Pozzi, Giulio, E-mail: giulio.pozzi@unibo.it [Department of Physics, University of Bologna, Viale B. Pichat 6/2, 40127 Bologna (Italy); Cesari, Nicola Semprini; Villa, Mauro; Zoccoli, Antonio [Department of Physics, University of Bologna, Viale B. Pichat 6/2, 40127 Bologna (Italy); INFN, Viale B. Pichat 6/2, 40127 Bologna (Italy)

    2012-05-15

    The two-slits experiment for single electrons has been carried out by inserting in a conventional transmission electron microscope a thick sample with two nano-slits fabricated by Focused Ion Beam technique and a fast recording system able to measure the electron arrival-time. The detector, designed for experiments in future colliders, is based on a custom CMOS chip equipped with a fast readout chain able to manage up to 10{sup 6} frames per second. In this way, high statistic samples of single electron events can be collected within a time interval short enough to measure the distribution of the electron arrival-times and to observe the build-up of the interference pattern. -- Highlights: Black-Right-Pointing-Pointer We present the first results obtained regarding the two-slits Young-Feynman experiment with single electrons. Black-Right-Pointing-Pointer We use two nano-slits fabricated by Focused Ion Beam technique. Black-Right-Pointing-Pointer We insert in the transmission electron microscope a detector, designed for experiments in future colliders. Black-Right-Pointing-Pointer We record the build-up of high statistic single electron interference patterns. Black-Right-Pointing-Pointer We measure the time distribution of electron arrivals.

  15. Development of the ASICs for the NA62 pixel Gigatracker

    CERN Document Server

    Jarron, P

    2008-01-01

    We present the ASIC development for the readout electronics of the Gigatracker pixel detector of NA62. Specifications of this detector are challenging in terms of timing precision with a hit time stamp accuracy of 100 ps and a peak hit rate of 50 Mhits/cm2/s. A timing precision and hit rate are more than one order of magnitude faster than pixel LHC readout ASIC. The research for pixel cell design and the readout architectures are following two approaches, which are presented and discussed in this paper. Presently demonstrator prototypes are under development and SPICE simulation results of the frontend, the readout strategy and and the pixelcolumn are also presented and discussed.

  16. X-ray pixel detector for crystallography

    CERN Document Server

    Delpierre, P A; Blanquart, L; Caillot, B; Clemens, J C; Mouget, C

    2001-01-01

    For X-ray diffraction experiments, the required dynamic range is a challenge. The signal ranges usually over more than six orders of magnitude. To meet this requirement and to reduce the readout time with respect to the commonly used charge-coupled device camera, a dedicated hybrid pixel detector is under development. We have designed a new counting chip with pixel size of 330 mu m. The expected counting rate per pixel is 10/sup 7/ ph/s, and a continuous readout with time stamping will allow a dynamic range for up to 4*10 /sup 9/ (16-bit counter in each pixel and 16-bit counter per pixel in the readout boards). This chip has been submitted for fabrication and is under test. First results of this chip will be presented. As a first step, a small detector (4*1.6 cm/sup 2/) is being built, using a DELPHI(LEP/CERN) silicon array of diodes, which have good efficiency for collecting X-rays between 5 and 25 keV. After the electrical tests, the performance of this X-ray detector will be measured in the ESRF-D2AM beam ...

  17. X-ray pixel detector for crystallography

    CERN Document Server

    Delpierre, P A; Blanquart, L; Caillot, B; Clemens, J C; Mouget, C

    2000-01-01

    For X-rays diffraction experiments, the required dynamic is a challenge. The signal ranges usually over more than six orders of magnitude. To meet this requirement and to reduce the readout time with respect to the commonly used CCD camera a dedicated hybrid pixel detector is under fabrication. We have designed a new counting chip with pixel sizes of 330 mu m. The expected counting rate per pixel is 10/sup 7/ ph/s and a continuous readout with time stamping-will allow for up to 4*10/sup 9/ dynamics range (16-bit counter in each pixel and 16-bit counter per pixel in the readout boards). This chip has been submitted for fabrication and it is under test. We will show first results. As a first step a small detector (4* 1.6 cm/sup 2/) is being built, using a DELPHI (LEP/CERN) Si array of diodes which have good efficiency for collecting X-rays between 5 and 25 keV. After the electrical tests, the performances of this X-ray detector will be measured in the ESRF-D2AM beam line (Grenoble, France), scheduled in next De...

  18. MKID digital readout tuning with deep learning

    Science.gov (United States)

    Dodkins, R.; Mahashabde, S.; O'Brien, K.; Thatte, N.; Fruitwala, N.; Walter, A. B.; Meeker, S. R.; Szypryt, P.; Mazin, B. A.

    2018-04-01

    Microwave Kinetic Inductance Detector (MKID) devices offer inherent spectral resolution, simultaneous read out of thousands of pixels, and photon-limited sensitivity at optical wavelengths. Before taking observations the readout power and frequency of each pixel must be individually tuned, and if the equilibrium state of the pixels change, then the readout must be retuned. This process has previously been performed through manual inspection, and typically takes one hour per 500 resonators (20 h for a ten-kilo-pixel array). We present an algorithm based on a deep convolution neural network (CNN) architecture to determine the optimal bias power for each resonator. The bias point classifications from this CNN model, and those from alternative automated methods, are compared to those from human decisions, and the accuracy of each method is assessed. On a test feed-line dataset, the CNN achieves an accuracy of 90% within 1 dB of the designated optimal value, which is equivalent accuracy to a randomly selected human operator, and superior to the highest scoring alternative automated method by 10%. On a full ten-kilopixel array, the CNN performs the characterization in a matter of minutes - paving the way for future mega-pixel MKID arrays.

  19. Operational Experience with the ATLAS Pixel Detector

    CERN Document Server

    Djama, Fares; The ATLAS collaboration

    2017-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction imposed by the higher collision energy, pileup and luminosity that are being delivered. The ATLAS tracking performance relies critically on the Pixel Detector, therefore, in view of Run-2 of LHC, the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and an additional optical link per module was added to overcome in some layers the readout bandwidth limitation when LHC will exceed the nominal peak luminosity by almost a factor of 3. The key features and challenges met during the IBL project will be presented, as well as its operational experience and Pixel Detector performance in LHC.

  20. Characterization of a three side abuttable CMOS pixel sensor with digital pixel and data compression for charged particle tracking

    Science.gov (United States)

    Guilloux, F.; Değerli, Y.; Flouzat, C.; Lachkar, M.; Monmarthe, E.; Orsini, F.; Venault, P.

    2016-02-01

    CMOS monolithic pixel sensor technology has been chosen to equip the new ALICE trackers for HL-LHC . PIXAM is the final prototype from an R&D program specific to the Muon Forward Tracker which intends to push significantly forward the performances of the mature rolling shutter architecture. By implementing a digital pixel allowing to readout of a group of rows in parallel, the PIXAM sensor increases the rolling shutter readout speed while keeping the same power consumption as that of analogue pixel sensors. This paper will describe shortly the ASIC architecture and will focus on the analogue and digital performances of the sensor, obtained from laboratory measurements.

  1. Proposal for an Experiment to Measure Mixing, CP Violation and Rare Decays in Charm and Beauty Particle Decays at the Fermilab Collider - BTeV

    Energy Technology Data Exchange (ETDEWEB)

    Kulyavtsev, A. [Carnegie Mellon Univ., Pittsburgh, PA (United States); Procario, M. [Carnegie Mellon Univ., Pittsburgh, PA (United States); Russ, J. [Carnegie Mellon Univ., Pittsburgh, PA (United States); You, J. [Carnegie Mellon Univ., Pittsburgh, PA (United States); Cumalat, J. [Univ. of Colorado, Boulder, CO (United States); Appel, J. A. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Brown, C. N. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Butler, J. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Cheung, H. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Christian, D. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States). et al.

    2000-05-01

    This proposal consists of five parts and two appendices. The first part provides a detailed physics justification for the BTe V experiment. The second part presents the considerations that drive the detector design, followed by a description of the detector itself. The third part summarizes our simulation results which demonstrate that the design does enable us to achieve our physics goals. The fourth part compares BTeV's physics reach to that of other experiments which will be active in B physics in the same time period. The fifth part gives a very brief, high level summary of the cost estimate for BTeV. Appendix A has additional technical details about many of the detector subsystems and R&D plans; it is intended to be read primarily by experts in each area. Appendix B contains a roadmap which describes the location in the proposal of the answers to questions posed to the BTeV collaboration by the Fermilab Program Advisory Committee in June of 1999.

  2. Status of the CMS Phase I Pixel Detector Upgrade

    CERN Document Server

    Spannagel, Simon

    2016-09-21

    A new pixel detector for the CMS experiment is being built, owing to the instantaneous luminosities anticipated for the Phase~I Upgrade of the LHC. The new CMS pixel detector provides four-hit tracking while featuring a significantly reduced material budget as well as new cooling and powering schemes. A new front-end readout chip mitigates buffering and bandwidth limitations, and comprises a low-threshold comparator. These improvements allow the new pixel detector to sustain and improve the efficiency of the current pixel tracker at the increased requirements imposed by high luminosities and pile-up. This contribution gives an overview of the design of the upgraded pixel detector and the status of the upgrade project, and presents test beam performance measurements of the production read-out chip.

  3. Performance of 4096 pixel photon counting chip

    CERN Document Server

    Bisogni, M G; Conti, M; Delogu, P; Fantacci, M E; Heijne, Erik H M; Maestro, P; Magistrati, G; Marzulli, V M; Meddeler, G; Mikulec, B; Pernigotti, E; Rosso, V; Schwarz, C; Snoeys, W; Stumbo, S; Watt, J

    1998-01-01

    A 4096 pixel Photon Counting Chip (PCC) has been developed and tested. It is aimed primarily at medical imaging although it can be used for other applications involving particle counting. The readout chip consists of a matrix of 64 x 64 identical square pixels, whose side measures 170 mm and is bump-bonded to a similar matrix of GaAs or Si pixel diodes covering a sensitive area of 1.18 cm . The electronics in each cell comprises a preamplifier, a discriminator with variable threshold and a 3-bit threshold tune as well as 15-bit counter. Each pixel can be individually addressed for electrical test or masked during acquisition. A shutter allows for switching between the counting and the readout modes and the use of a static logic in the counter enables long data taking periods. Electrical tests of the chip have shown a maximum counting rate of up to 2 MHz in each pixel. The minimum reachable threshold is 1400 e with a variation of 350 e rms that can be reduced to 80 e rms after tuning with the 3-bit adjustment....

  4. Monolithic pixel detectors for high energy physics

    CERN Document Server

    Snoeys, W

    2013-01-01

    Monolithic pixel detectors integrating sensor matrix and readout in one piece of silicon have revolutionized imaging for consumer applications, but despite years of research they have not yet been widely adopted for high energy physics. Two major requirements for this application, radiation tolerance and low power consumption, require charge collection by drift for the most extreme radiation levels and an optimization of the collected signal charge over input capacitance ratio ( Q / C ). It is shown that monolithic detectors can achieve Q / C for low analog power consumption and even carryout the promise to practically eliminate analog power consumption, but combining suf fi cient Q / C , collection by drift, and integration of readout circuitry within the pixel remains a challenge. An overview is given of different approaches to address this challenge, with possible advantages and disadvantages.

  5. Spectroscopic X-ray imaging with photon counting pixel detectors

    CERN Document Server

    Tlustos, L

    2010-01-01

    Single particle counting hybrid pixel detectors simultaneously provide low noise, high granularity and high readout speed and make it possible to build detector systems offering high spatial resolution paired with good energy resolution. A limiting factor for the spectroscopic performance of such detector systems is charge sharing between neighbouring pixels in the sensor part of the detector. The signal spectrum at the collection electrodes of the readout electronics deviates significantly from the photonic spectrum when planar segmented sensor geometries are used. The Medipix3 implements a novel, distributed signal processing architecture linking neighbouring pixels and aims at eliminating the spectral distortion produced in the sensor by charge sharing and at reducing the impact of fluorescence photons generated in the sensor itself. Preliminary results from the very first Medipix3 readouts bump bonded to 300 pm Si sensor are presented. Material reconstruction is a possible future application of spectrosco...

  6. Online calibrations and performance of the ATLAS Pixel Detector

    CERN Document Server

    Keil, M; The ATLAS collaboration

    2010-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 M electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. The talk will give an overview of the calibration and performance of both the detector and its optical readout. The most basic parameter to be tuned and calibrated for the detector electronics is the readout threshold of the individual pixel channels. These need to be carefully tuned to optimise position resolution a...

  7. Production chain of CMS pixel modules

    CERN Multimedia

    2006-01-01

    The pictures show the production chain of pixel modules for the CMS detector. Fig.1: overview of the assembly procedure. Fig.2: bump bonding with ReadOut Chip (ROC) connected to the sensor. Fig.3: glueing a raw module onto the baseplate strips. Fig.4: glueing of the High Density Interconnect (HDI) onto a raw module. Fig.5: pull test after heat reflow. Fig.6: wafer sensor processing, Indium evaporation.

  8. Studies on the Optical Readout for the ATLAS Pixel Detector

    CERN Document Server

    Flick, Tobias

    The particle physics is concentrating on the research of the structure of the matter which is observable in our world. How is this world built. Which particles exist, which are necessary to build up the world? How is this matter kept together, what are the interactions between the known particles? The answers to these questions are obtained by observing the known particles, to study their properties, and to search new for particles. Models are developed to describe all the observations. Experiments are performed to proove the models. The best prooven model to describe many of the observations is the Standard Model. The Standard Model is elucidated in Chapter 1. It is tested very precisely by experimental measurements in the last years, but cannot explain all phenomena of nature. To discover the last not observed particle of the Standard Model, the Higgs boson, and to extend the model further experiments are needed. To study the elementary particles machines and instruments are necessary to produce and measur...

  9. CMS Forward Pixel Upgrade Electronics and System Testing

    CERN Document Server

    Weber, Hannsjorg Artur

    2016-01-01

    This note discusses results of electronics and system testing of the CMS forward pixel (FPIX) detector upgrade for Phase 1. The FPIX detector is comprised of four stand-alone half cylinders, each of which contains frontend readout electronic boards, power regulators, cables and fibers in addition to the pixel modules. All of the components undergo rigorous testing and quality assurance before assembly into the half cylinders. Afterwards, we perform full system tests on the completely assembled half cylinders, including calibrations at final operating temperatures, characterization of the realistic readout chain, and system grounding and noise studies. The results from all these tests are discussed.

  10. ATLAS Phase-II Upgrade Pixel Data Transmission Development

    CERN Document Server

    Nielsen, Jason; The ATLAS collaboration

    2017-01-01

    The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per data link is necessary. Due to radiation levels, the first part of transmission has to be implemented electrically. System simulation and test results of cable candidates will be presented.

  11. ATLAS Phase-II-Upgrade Pixel Data Transmission Development

    CERN Document Server

    AUTHOR|(SzGeCERN)732982; The ATLAS collaboration

    2016-01-01

    The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per data link is necessary. Due to radiation levels, the first part of transmission has to be implemented electrically. System simulation and test results of cable candidates will be presented.

  12. ATLAS Phase-II-Upgrade Pixel data transmission development

    Science.gov (United States)

    Wensing, M.

    2017-01-01

    The ATLAS tracking system will be replaced by an all-silicon detector in the course of the planned upgrade of the Large Hadron Collider around 2025. The readout of the new pixel system will be most challenging in terms of data rate and readout speed. Simulations of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbit/s per data link is necessary. Due to radiation levels, the first part of transmission has to be implemented electrically. System simulation and test results of cable candidates will be presented.

  13. Single-Readout High-Density Memristor Crossbar

    KAUST Repository

    Zidan, M. A.

    2016-01-07

    High-density memristor-crossbar architecture is a very promising technology for future computing systems. The simplicity of the gateless-crossbar structure is both its principal advantage and the source of undesired sneak-paths of current. This parasitic current could consume an enormous amount of energy and ruin the readout process. We introduce new adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer-memory system to address the sneak-paths problem. The proposed methods require a single memory access per pixel for an array readout. Besides, the memristive crossbar consumes an order of magnitude less power than state-of-the-art readout techniques.

  14. Status of the digital pixel array detector for protein crystallography

    CERN Document Server

    Datte, P; Beuville, E; Endres, N; Druillole, F; Luo, L; Millaud, J E; Xuong, N H

    1999-01-01

    A two-dimensional photon counting digital pixel array detector is being designed for static and time resolved protein crystallography. The room temperature detector will significantly enhance monochromatic and polychromatic protein crystallographic through-put data rates by more than three orders of magnitude. The detector has an almost infinite photon counting dynamic range and exhibits superior spatial resolution when compared to present crystallographic phosphor imaging plates or phosphor coupled CCD detectors. The detector is a high resistivity N-type Si with a pixel pitch of 150x150 mu m, and a thickness of 300 mu m, and is bump bonded to an application specific integrated circuit. The event driven readout of the detector is based on the column architecture and allows an independent pixel hit rate above 1 million photons/s/pixel. The device provides energy discrimination and sparse data readout which yields minimal dead-time. This type of architecture allows a continuous (frameless) data acquisition, a f...

  15. The Level 0 Pixel Trigger system for the ALICE experiment

    International Nuclear Information System (INIS)

    Rinella, G Aglieri; Kluge, A; Krivda, M

    2007-01-01

    The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor targeting a latency of 800 ns. The system is compact, modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms. The system uses advanced 12-channel parallel optical fiber modules operating at 1310 nm as optical receivers and 12 deserializer chips closely packed in small area receiver boards. Alternative solutions with multi-channel G-Link deserializers implemented directly in programmable hardware devices were investigated. The design of the system and the progress of the ALICE Pixel Trigger project are described in this paper

  16. A silicon pixel detector prototype for the CLIC vertex detector

    CERN Multimedia

    Vicente Barreto Pinto, Mateus

    2017-01-01

    A silicon pixel detector prototype for CLIC, currently under study for the innermost detector surrounding the collision point. The detector is made of a High-Voltage CMOS sensor (top) and a CLICpix2 readout chip (bottom) that are glued to each other. Both parts have a size of 3.3 x 4.0 $mm^2$ and consist of an array of 128 x 128 pixels of 25 x 25 $\\micro m^2$ size.

  17. New results on diamond pixel sensors using ATLAS frontend electronics

    CERN Document Server

    Keil, Markus; Berdermann, E; Bergonzo, P; de Boer, Wim; Bogani, F; Borchi, E; Brambilla, A; Bruzzi, Mara; Colledani, C; Conway, J; D'Angelo, P; Dabrowski, W; Delpierre, P A; Dulinski, W

    2003-01-01

    Diamond is a promising sensor material for future collider experiments due to its radiation hardness. Diamond pixel sensors have been bump bonded to an ATLAS pixel readout chip using PbSn solder bumps. Single chip devices have been characterised by lab measurements and in a high-energy pion beam at CERN. Results on charge collection, spatial resolution, efficiency and the charge carrier lifetime are presented.

  18. Design Methodology: ASICs with complex in-pixel processing for Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Fahim, Farah [Fermilab

    2014-10-31

    The development of Application Specific Integrated Circuits (ASIC) for pixel detectors with complex in-pixel processing using Computer Aided Design (CAD) tools that are, themselves, mainly developed for the design of conventional digital circuits requires a specialized approach. Mixed signal pixels often require parasitically aware detailed analog front-ends and extremely compact digital back-ends with more than 1000 transistors in small areas below 100μm x 100μm. These pixels are tiled to create large arrays, which have the same clock distribution and data readout speed constraints as in, for example, micro-processors. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout.

  19. Update to Proposal for an Experiment to Measure Mixing, CP Violation and Rare Decays in Charm and Beauty Particle Decays at the Fermilab Collider - BTeV

    Energy Technology Data Exchange (ETDEWEB)

    Butler, Joel [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Stone, Sheldon [Syracuse Univ., NY (United States)

    2002-03-01

    We have been requested to submit an update of the BTeV plan to the Fermilab Physics Advisory Committee, where to save money the detector has only one arm and there is no new interaction region magnet construction planned. These are to come from a currently running collider experiment at the appropriate time. The "Physics Case" section is complete and updated with the section on the "New Physics" capabilites of BTeV greatly expanded. We show that precise measurements of rare flavor-changing neutral current processes and CP violation are and will be complementary to the Tevatron and LHC in unraveling the electroweak breaking puzzle. We include a revised summary of the physics sensitivities for the one-arm detector, which are not simply taking our proposal numbers and dividing by two, because of additional improvements. One important change resulted from an improved understanding of just how important the RJCH detector is to muon and electron identification, that we can indeed separate electrons from pions and muons from pions, especially at relatively large angles beyond the physical aperture of the EM calorimeter or the Muon Detector. This is documented in the "Physics Sensitivities" section. The section on the detector includes the motivation for doing b and c physics at a hadron collider, and shows the changes in the detector since the proposal based on our ongoing R&D program. We do not here include a detailed description of the entire detector. That is available in the May, 2000 proposal. We include a summary of our R&D activities for the entire experiment. Finally, we also include a fully updated cost estimate for the one-arm system.

  20. Novel integrated CMOS pixel structures for vertex detectors

    Energy Technology Data Exchange (ETDEWEB)

    Kleinfelder, Stuart; Bieser, Fred; Chen, Yandong; Gareus, Robin; Matis, Howard S.; Oldenburg, Markus; Retiere, Fabrice; Ritter, Hans Georg; Wieman, Howard H.; Yamamoto, Eugene

    2003-10-29

    Novel CMOS active pixel structures for vertex detector applications have been designed and tested. The overriding goal of this work is to increase the signal to noise ratio of the sensors and readout circuits. A large-area native epitaxial silicon photogate was designed with the aim of increasing the charge collected per struck pixel and to reduce charge diffusion to neighboring pixels. The photogate then transfers the charge to a low capacitance readout node to maintain a high charge to voltage conversion gain. Two techniques for noise reduction are also presented. The first is a per-pixel kT/C noise reduction circuit that produces results similar to traditional correlated double sampling (CDS). It has the advantage of requiring only one read, as compared to two for CDS, and no external storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5, to 12.8 e{sup -}. Finally, a column-level active reset technique is explored that suppresses kT/C noise during pixel reset. In tests, noise was reduced by a factor of 7.6 times, to an estimated 5.1 e{sup -} input-referred noise. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21 in our tests. The latter feature may possibly reduce pixel-by-pixel pedestal differences to levels low enough to permit sparse data scan without per-pixel offset corrections.

  1. Novel concept of TDI readout circuit for LWIR detector

    Science.gov (United States)

    Kim, Byunghyuck; Yoon, Nanyoung; Lee, Hee Chul; Kim, Choong-Ki

    2000-07-01

    Noise property is the prime consideration in readout circuit design. The output noise caused by the photon noise, which dominates total noise in BLIP detectors, is limited by the integration time that an element looks at a specific point in the scene. Large integration time leads to a low noise performance. Time-delay integration (TDI) is used to effectively increase the integration time and reduce the photon noise. However, it increases the number of dead pixels and requires large integration capacitors and low noise output stage of the readout circuit. In this paper, to solve these problems, we propose a new concept of readout circuit, which performs background suppression, cell-to-cell background current non-uniformity compensation, and dead pixel correction using memory, ADC, DAC, and current copier cell. In simulation results, comparing with the conventional TDI readout circuit, the integration capacitor size can be reduced to 1/5 and trans-impedance gain can be increased by five times. Therefore, the new TDI readout circuit does not require large area and low noise output stage. And the error of skimming current is less than 2%, and the fixed pattern noise induced by cell-to-cell background current variation is reduced to less than 1%.

  2. Operational Experience and Performance with the ATLAS Pixel detector

    CERN Document Server

    Yang, Hongtao; The ATLAS collaboration

    2018-01-01

    In this presentation, I will discuss the operation of ATLAS Pixel Detector during Run 2 proton-proton data-taking at √s=13 TeV in 2017. The topics to be covered include 1) the bandwidth issue and how it is mitigated through readout upgrade and threshold adjustment; 2) the auto-corrective actions; 3) monitoring of radiation effects.

  3. ATLAS Phase-II upgrade pixel data transmission development

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00111400; The ATLAS collaboration

    2017-01-01

    The current tracking system of the ATLAS experiment will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics indicates that the planned trigger rate of 1 MHz will require readout speeds up to 5.12 Gb/s per data link. The high-radiation environment precludes optical data transmission, so the first part of the data transmission has to be implemented electrically, over a 6-m distance between the pixel modules and the optical transceivers. Several high-speed electrical data transmission solutions involving small-gauge wire cables or flexible circuits have been prototyped and characterized. A combination of carefully-selected physical layers and aggressive signal conditioning are required to achieve the proposed specifications.

  4. Readout electronic for multichannel detectors

    CERN Document Server

    Kulibaba, V I; Naumov, S V

    2001-01-01

    Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) sup 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc.

  5. Diamond and silicon pixel detectors in high radiation environments

    Energy Technology Data Exchange (ETDEWEB)

    Tsung, Jieh-Wen

    2012-10-15

    Diamond pixel detector is a promising candidate for tracking of collider experiments because of the good radiation tolerance of diamond. The diamond pixel detector must withstand the radiation damage from 10{sup 16} particles per cm{sup 2}, which is the expected total fluence in High Luminosity Large Hadron Collider. The performance of diamond and silicon pixel detectors are evaluated in this research in terms of the signal-to-noise ratio (SNR). Single-crystal diamond pixel detectors with the most recent readout chip ATLAS FE-I4 are produced and characterized. Based on the results of the measurement, the SNR of diamond pixel detector is evaluated as a function of radiation fluence, and compared to that of planar-silicon ones. The deterioration of signal due to radiation damage is formulated using the mean free path of charge carriers in the sensor. The noise from the pixel readout circuit is simulated and calculated with leakage current and input capacitance to the amplifier as important parameters. The measured SNR shows good agreement with the calculated and simulated results, proving that the performance of diamond pixel detectors can exceed the silicon ones if the particle fluence is more than 10{sup 15} particles per cm{sup 2}.

  6. Sensor Development for the CMS Pixel Detector

    CERN Document Server

    Rohe, T; Chiochia, V; Cremaldi, L M; Cucciarelli, S; Dorkhov, A; Konecki, M; Prokofiev, K; Regenfus, C; Sanders, D A; Son, S; Speer, T; Swartz, M

    2003-01-01

    This paper reports on a current R&D activity for the sensor part of the CMS pixel detector. Devices featuring several design and technology options have been irradiated up to a proton fluence of 1E15 (1MeV Neutron)/cm**2 at the CERN PS. Afterwards they have been bump bonded to unirradiated readout chips. The chip allows a non zero suppressed full analogue readout and therefore a good characterization of the sensors in terms of noise and charge collection properties. The samples have been tested using high energy pions in the H2 beam line of the CERN SPS in June and September 2003. The results of this test beam are presented and the differences between the sensor options are discussed.

  7. Preliminary Assessment of Microwave Readout Multiplexing Factor

    Energy Technology Data Exchange (ETDEWEB)

    Croce, Mark Philip [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Koehler, Katrina Elizabeth [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Rabin, Michael W. [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Bennett, D. A. [National Inst. of Standards and Technology (NIST), Boulder, CO (United States); Mates, J. A. B. [National Inst. of Standards and Technology (NIST), Boulder, CO (United States); Gard, J. D. [National Inst. of Standards and Technology (NIST), Boulder, CO (United States); Becker, D. [National Inst. of Standards and Technology (NIST), Boulder, CO (United States); Schmidt, D. R. [National Inst. of Standards and Technology (NIST), Boulder, CO (United States); Ullom, J. N. [National Inst. of Standards and Technology (NIST), Boulder, CO (United States)

    2017-01-23

    Ultra-high resolution microcalorimeter gamma spectroscopy is a new non-destructive assay technology for measurement of plutonium isotopic composition, with the potential to reduce total measurement uncertainty to a level competitive with destructive analysis methods [1-4]. Achieving this level of performance in practical applications requires not only the energy resolution now routinely achieved with transition-edge sensor microcalorimeter arrays (an order of magnitude better than for germanium detectors) but also high throughput. Microcalorimeter gamma spectrometers have not yet achieved detection efficiency and count rate capability that is comparable to germanium detectors, largely because of limits from existing readout technology. Microcalorimeter detectors must be operated at low temperature to achieve their exceptional energy resolution. Although the typical 100 mK operating temperatures can be achieved with reliable, cryogen-free systems, the cryogenic complexity and heat load from individual readout channels for large sensor arrays is prohibitive. Multiplexing is required for practical systems. The most mature multiplexing technology at present is time-division multiplexing (TDM) [3, 5-6]. In TDM, the sensor outputs are switched by applying bias current to one SQUID amplifier at a time. Transition-edge sensor (TES) microcalorimeter arrays as large as 256 pixels have been developed for X-ray and gamma-ray spectroscopy using TDM technology. Due to bandwidth limits and noise scaling, TDM is limited to a maximum multiplexing factor of approximately 32-40 sensors on one readout line [8]. Increasing the size of microcalorimeter arrays above the kilopixel scale, required to match the throughput of germanium detectors, requires the development of a new readout technology with a much higher multiplexing factor.

  8. The STAR Heavy Flavor Tracker PXL detector readout electronics

    International Nuclear Information System (INIS)

    Schambach, J.; Contin, G.; Greiner, L.; Stezelberger, T.; Vu, C.; Sun, X.; Szelezniak, M.

    2016-01-01

    The Heavy Flavor Tracker (HFT) is a recently installed micro-vertex detector upgrade to the STAR experiment at RHIC, consisting of three subsystems with various technologies of silicon sensors arranged in 4 concentric cylinders. The two innermost layers of the HFT close to the beam pipe, the Pixel ('PXL') subsystem, employ CMOS Monolithic Active Pixel Sensor (MAPS) technology that integrate the sensor, front-end electronics, and zero-suppression circuitry in one silicon die. This paper presents selected characteristics of the PXL detector part of the HFT and the hardware, firmware and software associated with the readout system for this detector

  9. Sensor readout detector circuit

    Science.gov (United States)

    Chu, D.D.; Thelen, D.C. Jr.

    1998-08-11

    A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

  10. The phase II ATLAS Pixel upgrade: the Inner Tracker (ITk)

    Science.gov (United States)

    Flick, T.

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the ITk (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. Several layout options are being investigated. All of these include a barrel part and ring-shaped supports in the endcap regions. All structures will be based on low mass, highly stable and highly thermally conductive carbon-based materials cooled by evaporative carbon dioxide. Different designs of planar, 3D, and CMOS sensors are being investigated to identify the optimal technology for the different pixel layers. While the RD53 Collaboration is developing the new readout chip, the pixel off-detector readout electronics will be implemented in the framework of the general ATLAS trigger and DAQ system. A readout speed of up to 5 Gbit/s per data link (FE-chip) will be needed in the innermost layers going down to 640 Mbit/s for the outermost. This paper presents an overview of the different components of the ITk and the current status of the developments.

  11. Imaging by photon counting with 256 x 256 pixel matrix

    CERN Document Server

    Tlustos, Lukas; Heijne, Erik H M; Llopart-Cudie, Xavier

    2004-01-01

    Using 0.25 mum standard CMOS we have developed 2-D semiconductor matrix detectors with sophisticated functionality integrated inside each pixel of a hybrid sensor module. One of these sensor modules is a matrix of 256 multiplied by 256 square 55mum pixels intended for X- ray imaging. This device is called 'Medipix2' and features a fast amplifier and two-level discrimination for signals between 1000 and 100000 equivalent electrons, with overall signal noise similar to 150 e- rms. Signal polarity and comparator thresholds are programmable. A maximum count rate of nearly 1 MHz per pixel can be achieved, which corresponds to an average flux of 3 multiplied by 10exp10 photons per cm2. The selected signals can be accumulated in each pixel in a 13- bit register. The serial readout takes 5-10 ms. A parallel readout of similar to 300 mus could also be used. Housekeeping functions such as local dark current compensation, test pulse generation, silencing of noisy pixels and threshold tuning in each pixel contribute to t...

  12. New smart readout technique performing edge detection designed to control vision sensors dataflow

    Science.gov (United States)

    Amhaz, Hawraa; Sicard, Gilles

    2012-03-01

    In this paper, a new readout strategy for CMOS image sensors is presented. It aims to overcome the excessive output dataflow bottleneck; this challenge is becoming more and more crucial along with the technology miniaturization. This strategy is based on the spatial redundancies suppression. It leads the sensor to perform edge detection and eventually provide binary image. One of the main advantages of this readout technique compared to other techniques, existing in the literature, is that it does not affect the in-pixel circuitry. This means that all the analogue processing circuitry is implemented outside the pixel, which keeps the pixel area and Fill Factor unchanged. The main analogue block used in this technique is an event detector developed and designed in the CMOS 0.35μm technology from Austria Micro Systems. The simulation results of this block as well as the simulation results of a test bench composed of several pixels and column amplifiers using this readout mode show the capability of this readout mode to reduce dataflow by controlling the ADCs. We must mention that this readout strategy is applicable on sensors that use a linear operating pixel element as well as for those based on logarithmic operating pixels. This readout technique is emulated by a MATLAB model which gives an idea about the expected functionalities and dataflow reduction rates (DRR). Emulation results are shown lately by giving the pre and post processed images as well as the DRR. This last cited does not have a fix value since it depends on the spatial frequency of the filmed scenes and the chosen threshold value.

  13. PixelLearn

    Science.gov (United States)

    Mazzoni, Dominic; Wagstaff, Kiri; Bornstein, Benjamin; Tang, Nghia; Roden, Joseph

    2006-01-01

    PixelLearn is an integrated user-interface computer program for classifying pixels in scientific images. Heretofore, training a machine-learning algorithm to classify pixels in images has been tedious and difficult. PixelLearn provides a graphical user interface that makes it faster and more intuitive, leading to more interactive exploration of image data sets. PixelLearn also provides image-enhancement controls to make it easier to see subtle details in images. PixelLearn opens images or sets of images in a variety of common scientific file formats and enables the user to interact with several supervised or unsupervised machine-learning pixel-classifying algorithms while the user continues to browse through the images. The machinelearning algorithms in PixelLearn use advanced clustering and classification methods that enable accuracy much higher than is achievable by most other software previously available for this purpose. PixelLearn is written in portable C++ and runs natively on computers running Linux, Windows, or Mac OS X.

  14. A Cherenkov camera with integrated electronics based on the 'Smart Pixel' concept

    International Nuclear Information System (INIS)

    Bulian, Norbert; Hirsch, Thomas; Hofmann, Werner; Kihm, Thomas; Kohnle, Antje; Panter, Michael; Stein, Michael

    2000-01-01

    An option for the cameras of the HESS telescopes, the concept of a modular camera based on 'Smart Pixels' was developed. A Smart Pixel contains the photomultiplier, the high voltage supply for the photomultiplier, a dual-gain sample-and-hold circuit with a 14 bit dynamic range, a time-to-voltage converter, a trigger discriminator, trigger logic to detect a coincidence of X=1...7 neighboring pixels, and an analog ratemeter. The Smart Pixels plug into a common backplane which provides power, communicates trigger signals between neighboring pixels, and holds a digital control bus as well as an analog bus for multiplexed readout of pixel signals. The performance of the Smart Pixels has been studied using a 19-pixel test camera

  15. Module and Electronics Developments for the ATLAS ITK Pixel System

    CERN Document Server

    Rummler, Andr{e}; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown around 2025 by an all-silicon detector (Inner Tracker, ITk). The pixel detector will be composed by the five innermost layers, instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m^2, depending on the final layout choice that is expected to take place in early 2017. Different designs of planar, 3D, CMOS sensors are being investigated to identify the optimal technology for the different pixel layers. In parallel sensor-chip interconnection options are evaluated in collaboration with industrial partners to identify reliable technologies when employing 100-150 μm thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off detector read-out electronics will be implemented in the frame...

  16. Multi-Anode Photomultplier (MAPMT) readout for High Granularity Calorimeters

    CERN Document Server

    Mkrtchyan, Tigran; The ATLAS collaboration

    2017-01-01

    Hadron calorimeter high performance in jet sub-structure measurements can be achieved for objects with $p_{T}$ greater than 1 TeV if the readout geometry is finely segmented in $\\Delta\\eta \\times \\Delta\\phi$. A feasibility study to increase the readout granularity of TileCal, the central hadron calorimeter of the ATLAS detector, is presented. We show a preliminary study exploring the possibility to increase by a factor 4 the present readout granularity of the inner layer cells of TileCal (0.1->0.025 in $\\Delta\\eta$) and to split into two layers the intermediate section of TileCal. The proposed solution is designed to cope with mechanical and readout bandwidth and power constraints. Assuming that the mechanics of the Tile modules cannot be changed, Multi-Anode PMTs with same boundary geometry of the present single-anode PMTs are considered to readout WLS bers, ideally one per pixel, carrying the signals from the individual scintillating tiles of each detector cells. The discussed challenges of the design are: ...

  17. Automatic readout micrometer

    Science.gov (United States)

    Lauritzen, T.

    A measuring system is described for surveying and very accurately positioning objects with respect to a reference line. A principle use of this surveying system is for accurately aligning the electromagnets which direct a particle beam emitted from a particle accelerator. Prior art surveying systems require highly skilled surveyors. Prior art systems include, for example, optical surveying systems which are susceptible to operator reading errors, and celestial navigation-type surveying systems, with their inherent complexities. The present invention provides an automatic readout micrometer which can very accurately measure distances. The invention has a simplicity of operation which practically eliminates the possibilities of operator optical reading error, owning to the elimination of traditional optical alignments for making measurements. The invention has an extendable arm which carries a laser surveying target. The extendable arm can be continuously positioned over its entire length of travel by either a coarse of fine adjustment without having the fine adjustment outrun the coarse adjustment until a reference laser beam is centered on the target as indicated by a digital readout. The length of the micrometer can then be accurately and automatically read by a computer and compared with a standardized set of alignment measurements. Due to its construction, the micrometer eliminates any errors due to temperature changes when the system is operated within a standard operating temperature range.

  18. Pixel detector modules performance for ATLAS IBL and future pixel detectors

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00355104; Pernegger, Heinz

    2015-11-06

    The ATLAS Detector is one of the four big particle physics experiments at CERN’s LHC. Its innermost tracking system consisted of the 3-Layer silicon Pixel Detector (~80M readout channels) in the first run (2010-2012). Over the past two years it was refurbished and equipped with new services as well as a new beam monitor. The major upgrade, however, was the Insertable B-Layer (IBL). It adds ~12M readout channels for improved vertexing, tracking robustness and b-tagging performance for the upcoming runs, before the high luminosity upgrade of the LHC will take place. This thesis covers two main aspects of Pixel detector performance studies: The main work was the planning, commissioning and operation of a test bench that meets the requirements of current pixel detector components. Each newly built ATLAS IBL stave was thoroughly tested, following a specifically developed procedure, and initially calibrated in that setup. A variety of production accompanying measurements as well as preliminary results after integ...

  19. Pixel hybrid photon detectors for the ring imaging Cherenkov detectors of LHCb

    CERN Document Server

    Somerville, L

    2005-01-01

    A Pixel Hybrid Photon Detector (pixel HPD) has been developed for the LHCb Ring Imaging Cherenkov (RICH) detectors. The pixel HPD is a vacuum tube with a multi-alkali photocathode, high-voltage cross- focused electron optics and an anode consisting of a silicon pixel detector bump-bonded to a CMOS readout chip; the readout chip is thus fully encapsulated in the device. The pixel HPD fulfils the stringent requirements for the RICH detectors of LHCb, combining single photon sensitivity, high signal-to-noise ratio and fast readout with an ~8cm diameter active area and an effective pixel size of 2.5mm 2.5mm at the photocathode. The performance and characteristics of two prototype pixel HPDs have been studied in laboratory measurements and in recent beam tests. The results of all measurements agree with expectations and fulfil the LHCb RICH requirements. In readiness for production of the ~500pixel HPDs for the RICH detectors, a test programme was designed and implemented to ensure component quality control at eac...

  20. Semiconductor detectors with proximity signal readout

    International Nuclear Information System (INIS)

    Asztalos, Stephen J.

    2012-01-01

    Semiconductor-based radiation detectors are routinely used for the detection, imaging, and spectroscopy of x-rays, gamma rays, and charged particles for applications in the areas of nuclear and medical physics, astrophysics, environmental remediation, nuclear nonproliferation, and homeland security. Detectors used for imaging and particle tracking are more complex in that they typically must also measure the location of the radiation interaction in addition to the deposited energy. In such detectors, the position measurement is often achieved by dividing or segmenting the electrodes into many strips or pixels and then reading out the signals from all of the electrode segments. Fine electrode segmentation is problematic for many of the standard semiconductor detector technologies. Clearly there is a need for a semiconductor-based radiation detector technology that can achieve fine position resolution while maintaining the excellent energy resolution intrinsic to semiconductor detectors, can be fabricated through simple processes, does not require complex electrical interconnections to the detector, and can reduce the number of required channels of readout electronics. Proximity electrode signal readout (PESR), in which the electrodes are not in physical contact with the detector surface, satisfies this need

  1. The Phase-1 Upgrade of the CMS Pixel Detector

    CERN Document Server

    Lipinski, Martin

    2017-01-01

    The innermost tracking device of the CMS experiment is a silicon pixel detector. It has to cope with high particle fluxes and radiation damage, and was built to withstand the LHC design luminosity of 1$\\times10^{34}$ cm$^{-2}$s$^{-1}$. This luminosity was already exceeded in 2016 and it is foreseen that it will increase further, potentially reaching two times the design value before 2018. Under such conditions the inefficiencies due to a limited readout bandwidth will increase by as much as 16\\% in the innermost layer. To maintain high tracking efficiency, the CMS collaboration has built a new pixel detector that was installed in March 2017. In this paper, the design of this so-called Phase-1 pixel detector is summarised, the production and the qualification of the pixel modules is described and the current status of the project is reported.

  2. Readout of silicon strip detectors

    CERN Document Server

    Dabrowski, W

    2003-01-01

    Various architectural and technological options of readout electronics for silicon strip detectors in vertex and tracking applications are discussed briefly. The ABCD3T ASIC for the readout of silicon strip detectors in the ATLAS semiconductor tracker is presented. The architecture of the chip, some design issues and radiation effects are discussed.

  3. ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

    Science.gov (United States)

    Vasile, Stefan; Lipson, Jerold

    2012-01-01

    The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

  4. Compensated digital readout family

    Science.gov (United States)

    Ludwig, David E.; Skow, Michael

    1991-11-01

    ISC has completed test on an IC which has 32 channels of amplifiers, low pass anti-aliasing filters, 13-bit analog-to-digital (A/D) converters with non-uniformity correction per channel and a digital multiplexer. The single slope class of A/D conversion is described, as are the unique variations required for incorporation of this technique for use with on-focal plane detector readout electronics. This paper describes the architecture used to implement the digital on-focal plane signal processing functions. Results from measured data on a test IC are presented for a circuit containing these functions operating at a sensor frame rate of 1000 hertz.

  5. Study of the CMS Phase-1 Pixel Pilot Blade Reconstruction

    CERN Document Server

    Vami, Tamas Almos

    2017-01-01

    The Compact Muon Solenoid (CMS) detector is one of two general-purpose detectors that measure the products of high energy particle interactions in the Large Hadron Collider (LHC) at CERN. The silicon pixel detector is the innermost component of the CMS tracking system. The detector which was in operation between 2009 and 2016 has now been replaced with an upgraded one in the beginning of 2017. During the previous shutdown period of the LHC, a prototype readout system and a third disk was inserted into the old forward pixel detector with eight prototype blades constructed using the new digital read-out chips. Testing the performance of these pilot modules enabled us to gain operational experience with the upgraded detector. In this paper, the reconstruction and analysis of the data taken with the new modules are presented including information on the calibration of the reconstruction software. The hit finding efficiency and track-hit residual distributions are also shown.

  6. Study of the CMS Phase 1 Pixel Pilot Blade Reconstruction

    CERN Document Server

    CMS Collaboration

    2017-01-01

    The silicon pixel detector is the innermost component of the CMS tracking system. It was replaced in March 2017 with an upgraded one, called the Phase 1 upgrade detector. During Long Shutdown 1, a third disk was inserted into the present forward pixel detector with eight prototype blades constructed using a new digital read-out chip architecture and a prototype readout chain. Testing the performance of these pilot modules enabled us to gain experience with the Phase 1 upgrade modules. In this document, the data reconstruction with the pilot system is presented. The hit finding efficiency and residual of these new modules is also shown, and how these observables were used to adjust the timing of the pilot blades.

  7. Module and electronics developments for the ATLAS ITk pixel system

    Science.gov (United States)

    Muñoz, F. J.

    2018-03-01

    The ATLAS experiment is preparing for an extensive modification of its detectors in the course of the planned HL-LHC accelerator upgrade around 2025. The ATLAS upgrade includes the replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will be a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in 2018. In this paper an overview of the ongoing R&D activities on modules and electronics for the ATLAS ITk is given including the main developments and achievements in silicon planar and 3D sensor technologies, readout and power challenges.

  8. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Munoz Sanchez, Francisca Javiela; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is preparing for an extensive modification of its detectors in the course of the planned HL-LHC accelerator upgrade around 2025. The ATLAS upgrade includes the replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will be a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in 2017. In this paper an overview of the ongoing R\\&D activities on modules and electronics for the ATLAS ITk is given including the main developments and achievements in silicon planar and 3D sensor technologies, readout and power challenges.

  9. An asynchronous data-driven readout prototype for CEPC vertex detector

    Science.gov (United States)

    Yang, Ping; Sun, Xiangming; Huang, Guangming; Xiao, Le; Gao, Chaosong; Huang, Xing; Zhou, Wei; Ren, Weiping; Li, Yashu; Liu, Jianchao; You, Bihui; Zhang, Li

    2017-12-01

    The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 μm. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back.

  10. Performance studies of pixel hybrid photon detectors for the LHCb RICH counters

    CERN Document Server

    Aglieri-Rinella, G; Piedigrossi, D; Van Lysebetten, A

    2006-01-01

    The Pixel Hybrid Photon Detector is a vacuum tube with a multi-alkali photo cathode, high voltage cross-focused electron optics and an anode consisting of a silicon pixel detector bump-bonded to a readout CMOS electronic chip fully encapsulated in the device. The Pixel HPD fulfils the requirements of the Ring Imaging Cherenkov counters of the LHCb experiment at LHC. The performances of the Pixel HPD will be discussed with reference to laboratory measurements, Cherenkov light imaging in recent beam tests, image distortions due to a magnetic field.

  11. Performance Studies of Pixel Hybrid Photon Detectors for the LHCb RICH Counters

    CERN Document Server

    Aglieri Rinella, G; Piedigrossi, D; Van Lysebetten, A

    2004-01-01

    The Pixel Hybrid Photon Detector is a vacuum tube with a multi-alkali photo cathode, high voltage cross-focused electron optics and an anode consisting of a silicon pixel detector bump-bonded to a readout CMOS electronic chip fully encapsulated in the device. The Pixel HPD fulfils the requirements of the Ring Imaging Cherenkov counters of the LHCb experiment at LHC. The performances of the Pixel HPD will be discussed with reference to laboratory measurements, Cherenkov light imaging in recent beam tests, image distortions due to a magnetic field.

  12. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  13. The pixelated detector

    CERN Multimedia

    Sutton, C

    1990-01-01

    "Collecting data as patterns of light or subatomic particles is vitally important in all the sciences. The new generation of solid-state detectors called pixel devices could transform experimental research at all levels" (4 pages).

  14. Readout of two-kilopixel transition-edge sensor arrays for Advanced ACTPol

    Science.gov (United States)

    Henderson, Shawn W.; Stevens, Jason R.; Amiri, Mandana; Austermann, Jason; Beall, James A.; Chaudhuri, Saptarshi; Cho, Hsiao-Mei; Choi, Steve K.; Cothard, Nicholas F.; Crowley, Kevin T.; Duff, Shannon M.; Fitzgerald, Colin P.; Gallardo, Patricio A.; Halpern, Mark; Hasselfield, Matthew; Hilton, Gene; Ho, Shuay-Pwu Patty; Hubmayr, Johannes; Irwin, Kent D.; Koopman, Brian J.; Li, Dale; Li, Yaqiong; McMahon, Jeff; Nati, Federico; Niemack, Michael; Reintsema, Carl D.; Salatino, Maria; Schillaci, Alessandro; Schmitt, Benjamin L.; Simon, Sara M.; Staggs, Suzanne T.; Vavagiakis, Eve M.; Ward, Jonathan T.

    2016-07-01

    Advanced ACTPol is an instrument upgrade for the six-meter Atacama Cosmology Telescope (ACT) designed to measure the cosmic microwave background (CMB) temperature and polarization with arcminute-scale angular resolution. To achieve its science goals, Advanced ACTPol utilizes a larger readout multiplexing factor than any previous CMB experiment to measure detector arrays with approximately two thousand transition-edge sensor (TES) bolometers in each 150 mm detector wafer. We present the implementation and testing of the Advanced ACTPol time-division multiplexing readout architecture with a 64-row multiplexing factor. This includes testing of individual multichroic detector pixels and superconducting quantum interference device (SQUID) multiplexing chips as well as testing and optimizing of the integrated readout electronics. In particular, we describe the new automated multiplexing SQUID tuning procedure developed to select and optimize the thousands of SQUID parameters required to readout each Advanced ACTPol array. The multichroic detector pixels in each array use separate channels for each polarization and each of the two frequencies, such that four TESes must be read out per pixel. Challenges addressed include doubling the number of detectors per multiplexed readout channel compared to ACTPol and optimizing the Nyquist inductance to minimize detector and SQUID noise aliasing.

  15. Timing and Readout Contorl in the LHCb Upgraded Readout System

    CERN Document Server

    Alessio, Federico

    2016-01-01

    In 2019, the LHCb experiment at CERN will undergo a major upgrade where its detectors electronics and entire readout system will be changed to read-out events at the full LHC rate of 40 MHz. In this paper, the new timing, trigger and readout control system for such upgrade is reviewed. Particular attention is given to the distribution of the clock, timing and synchronization information across the entire readout system using generic FTTH technology like Passive Optical Networks. Moreover the system will be responsible to generically control the Front-End electronics by transmitting configuration data and receiving monitoring data, offloading the software control system from the heavy task of manipulating complex protocols of thousands of Front-End electronics devices. The way in which this was implemented is here reviewed with a description of results from first implementations of the system, including usages in test-benches, implementation of techniques for timing distribution and latency control."

  16. A generic readout system for astrophysical detectors

    Science.gov (United States)

    Doumayrou, E.; Lortholary, M.

    2012-09-01

    We have developed a generic digital platform to fulfill the needs for the development of new detectors in astrophysics, which is used in lab, for ground-based telescopes instruments and also in prototype versions for space instruments development. This system is based on hardware FPGA electronic board (called MISE) together with software on a PC computer (called BEAR). The MISE board generates the fast clocking which reads the detectors thanks to a programmable digital sequencer and performs data acquisition, buffering of digitalized pixels outputs and interfaces with others boards. The data are then sent to the PC via a SpaceWire or Usb link. The BEAR software sets the MISE board up, makes data acquisition and enables the visualization, processing and the storage of data in line. These software tools are made of C++ and Labview (NI) on a Linux OS. MISE and BEAR make a generic acquisition architecture, on which dedicated analog boards are plugged, so that to accommodate with detectors specificity: number of pixels, the readout channels and frequency, analog bias and clock interfaces. We have used this concept to build a camera for the P-ARTEMIS project including a 256 pixels sub-millimeter bolometer detector at 10Kpixel/s (SPIE 7741-12 (2010)). For the EUCLID project, a lab camera is now working for the test of CCDs 4Mpixels at 4*200Kpixel/s. Another is working for the testing of new near infrared detectors (NIR LFSA for the ESA TRP program) 110Kpixels at 2*100Kpixels/s. Other projects are in progress for the space missions PLATO and SPICA.

  17. Pixel electronics for the ATLAS experiment

    International Nuclear Information System (INIS)

    Fischer, P.

    2001-01-01

    The ATLAS experiment at LHC will use 3 barrel layers and 2x5 disks of silicon pixel detectors as the innermost elements of the semiconductor tracker. The basic building blocks are pixel modules with an active area of 16.4 mmx60.8 mm which include an n + on n-type silicon sensor and 16 VLSI front-end (FE) chips. Every FE chip contains a low power, high speed charge sensitive preamplifier, a fast discriminator, and a readout system which operates at the 40 MHz rate of LHC. The addresses of hit pixels (as well as a low resolution pulse height information) are stored on the FE chips until arrival of a level 1 trigger signal. Hits are then transferred to a module controller chip (MCC) which collects the data of all 16 FE chips, builds complete events and sends the data through two optical links to the data acquisition system. The MCC receives clock and data through an additional optical link and provides timing and configuration information for the FE chips. Two additional chips are used to amplify and decode the pin diode signal and to drive the VCSEL laser diodes of the optical links

  18. Cool Timepix - Electronic noise of the Timepix readout chip down to -125 sub o C

    NARCIS (Netherlands)

    Schön, R.; Alfonsi, M.; van Bakel, N.; van Beuzekom, M.; Koffeman, E.

    2015-01-01

    The Timepix readout chip with its 65k pixels on a sensitive area of 14 mm×14 mm provides a fine spatial resolution for particle tracking or medical imaging. We explore the operation of Timepix in a dual-phase xenon environment (around −110 °C). Used in dual-phase xenon time projection chambers, e.g.

  19. FE-I4 pixel chip characterization with USBpix3 test system

    Energy Technology Data Exchange (ETDEWEB)

    Filimonov, Viacheslav; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [University of Bonn, Bonn (Germany)

    2015-07-01

    The USBpix readout system is a small and light weighting test system for the ATLAS pixel readout chips. It is widely used to operate and characterize FE-I4 pixel modules in lab and test beam environments. For multi-chip modules the resources on the Multi-IO board, that is the central control unit of the readout system, are coming to their limits, which makes the simultaneous readout of more than one chip at a time challenging. Therefore an upgrade of the current USBpix system has been developed. The upgraded system is called USBpix3 - the main focus of the talk. Characterization of single chip FE-I4 modules was performed with USBpix3 prototype (digital, analog, threshold and source scans; tuning). PyBAR (Bonn ATLAS Readout in Python scripting language) was used as readout software. PyBAR consists of FEI4 DAQ and Data Analysis Libraries in Python. The presentation describes the USBpix3 system, results of FE-I4 modules characterization and preparation for the multi-chip module and multi-module readout with USBpix3.

  20. Thermopile Area Array Readout Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NASA/JPL thermopile detector linear arrays, wire bonded to Black Forest Engineering (BFE) CMOS readout integrated circuits (ROICs), have been utilized in NASA...

  1. Performance study of new pixel hybrid photon detector prototypes for the LHCb RICH counters

    CERN Document Server

    Moritz, M; Allebone, L; Campbell, M; Gys, Thierry; Newby, C; Pickford, A; Piedigrossi, D; Wyllie, K

    2004-01-01

    A pixel Hybrid Photon Detector was developed according to the specific requirements of the LHCb ring imaging Cerenkov counters. This detector comprises a silicon pixel detector bump-bonded to a binary readout chip to achieve a 25 ns fast readout and a high signal-to-noise ratio. The detector performance was characterized by varying the pixel threshold, the tube high voltage, the silicon bias voltage and by the determination of the photoelectron detection efficiency. Furthermore accelerated aging and high pixel occupancy tests were performed to verify the long term stability. The results were obtained using Cerenkov light and a fast pulsed light emitting diode. All measurements results are within the expectations and fulfill the design goals. (8 refs).

  2. Module Production and Qualification for the Phase I Upgrade of the CMS Pixel Detector

    CERN Document Server

    AUTHOR|(CDS)2086689

    2015-01-01

    After consolidation of the LHC in 2013/14 its centre-of-mass energy will increase to 13TeV and the luminosity will reach $2 \\cdot 10^{34}\\, \\textnormal{cm}^{-2} \\textnormal{s}^{-1}$, which is twice the design luminosity. The latter will result in more simultaneous particle collisions, which would significantly increase the dead time of the current readout chip of the CMS pixel detector. Therefore the entire CMS pixel detector is replaced in 2016/17 and a new digital readout with larger buffers will be used to handle increasing pixel hit rates. An additional fourth barrel-layer provides more space points to improve track reconstruction. Half of the required modules for layer four is being produced at Karlsruhe Institute of Technology (KIT). This poster deals with the smallest discrete subunit of the pixel detector, the module and its assembly process. Moreover first production experience will be shown.

  3. Module and Electronics Developments for the ATLAS ITK Pixel System

    CERN Document Server

    Nellist, Clara; The ATLAS collaboration

    2016-01-01

    ATLAS is preparing for an extensive modification of its detector in the course of the planned HL-LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m$^{2}$, depending on the final layout choice that is expected to take place in early 2017. An intense R\\&D activity is taking place in the field of planar, 3D, CMOS sensors to identify the optimal technology for the different pixel layers. In parallel various sensor-chip interconnection options are explored to identify reliable technologies when employing 100-150~$\\mu$m thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off de...

  4. An EUDET/AIDA Pixel Beam Telescope for Detector Development

    CERN Document Server

    Rubinskiy, I

    2015-01-01

    A high resolution (σ∼2μm) beam telescope based on monolithic active pixel sensors (MAPS) was developed within the EUDET collaboration. The telescope consists of six monolithic active pixel sensor planes (Mimosa26) with a pixel pitch of 18.4 \\mu m and thinned down to 50 \\mu m. The excellent resolution, readout rate and DAQ integration capabilities made the telescope a primary test beam tool for many groups including several CERN based experiments. Within the European detector infrastructure project AIDA the test beam telescope is being further extended in terms of cooling and powering infrastructure, read-out speed, area of acceptance, and precision. In order to provide a system optimized for the different requirements by the user community a combination of various state-of-the-art pixel technologies is foreseen. Furthermore, new central dead-time-free trigger logic unit (TLU) has been developed to provide LHC-speed response with one-trigger-per-particle operating mode and a synchronous clock for all conn...

  5. An EUDET/AIDA Pixel Beam Telescope for Detector Development

    CERN Document Server

    Perrey, Hanno

    2013-01-01

    A high resolution ($\\sigma 2 \\sim \\mu$) beam telescope based on monolithic active pixel sensors (MAPS) was developed within the EUDET collaboration. The telescope consists of six sensor planes using Mimosa26 MAPS with a pixel pitch of $18.4 \\mu$ and thinned down to $50 \\mu$. The excellent resolution, readout rate and DAQ integration capabilities made the telescope a primary test beam tool for many groups including several CERN based experiments. Within the new European detector infrastructure project AIDA the test beam telescope will be further extended in terms of cooling infrastructure, readout speed and precision. In order to provide a system optimized for the different requirements by the user community, a combination of various pixel technologies is foreseen. In this report the design of this even more flexible telescope with three different pixel technologies (TimePix, Mimosa, ATLAS FE-I4) will be presented. First test beam results with the HitOR signal provided by the FE-I4 integrated into the trigger...

  6. Performance of the CMS Phase 1 Pixel Detector

    CERN Document Server

    Akgun, Bora

    2018-01-01

    It is anticipated that the LHC accelerator will reach and exceed the luminosity of L = 2$\\times$10$^{34}$cm$^{-2}$s$^{-1}$ during the LHC Run 2 period until 2023. At this higher luminosity and increased hit occupancies the CMS phase-0 pixel detector would have been subjected to severe dead time and inefficiencies introduced by limited buffers in the analog read-out chip and effects of radiation damage in the sensors. Therefore a new pixel detector has been built and replaced the phase-0 detector in the 2016/17 LHC extended year-end technical stop. The CMS phase-1 pixel detector features four central barrel layers and three end-cap disks in forward and backward direction for robust tracking performance, and a significantly reduced overall material budget including new cooling and powering schemes. The design of the new front-end readout chip comprises larger data buffers, an increased transmission bandwidth, and low-threshold comparators. These improvements allow the new pixel detector to sustain and improve t...

  7. Semiconductor micropattern pixel detectors: a review of the beginnings

    International Nuclear Information System (INIS)

    Heijne, E.H.M.

    2001-01-01

    The innovation in monolithic and hybrid semiconductor 'micropattern' or 'reactive' pixel detectors for tracking in particle physics was actually to fit logic and pulse processing electronics with μW power on a pixel area of less than 0.04 mm 2 , retaining the characteristics of a traditional nuclear amplifier chain. The ns timing precision in conjunction with local memory and logic operations allowed event selection at >10 MHz rates with unambiguous track reconstruction even at particle multiplicities >10 cm -2 . The noise in a channel was ∼100e - rms and enabled binary operation with random noise 'hits' at a level -8 . Rectangular pixels from 75 μmx500 μm down to 34 μmx125 μm have been used by different teams. In binary mode a tracking precision from 6 to 14 μm was obtained, and using analog interpolation one came close to 1 μm. Earlier work, still based on charge integrating imaging circuits, provided a starting point. Two systems each with more than 1 million sensor + readout channels have been built, for WA97-NA57 and for the Delphi very forward tracker. The use of 0.5 μm and 0.25 μm CMOS and enclosed geometry for the transistors in the pixel readout chips resulted in radiation hardness of ∼2 Mrad, respectively, >30 Mrad

  8. Phase 1 upgrade of the CMS Pixel Detector

    CERN Document Server

    Saha, Anirban

    2016-01-01

    The pixel tracker of the Compact Muon Solenoid (CMS) experiment is the innermost sub-detector, located close to the collision point, and is used for reconstruction of the tracks and vertices of charged particles. The present pixel detector was designed to work efficiently with the maximum instantaneous luminosity of $\\rm 1 \\times 10^{34}$ cm$^{-2}$ s$^{-1}$. In 2017 the Large Hadron Collider (LHC) is expected to deliver a peak luminosity reaching up to $\\rm 2\\times10^{34} cm^{-2}s^{-1}$, increasing the mean number of primary vertices to 50. Due to the radiation damage and significant data losses due to high occupancy in the readout chip of the pixel detector, the present system must be replaced by a new one in an extended end-of-year shutdown during winter 2016/2017 in order to maintain the excellent tracking and other physics performances. The main new features of the upgraded pixel detector are the a ultra-light mechanical design with four barrel layers and three end-cap disks, digital readout chip with hi...

  9. Electron imaging with Medipix2 hybrid pixel detector

    CERN Document Server

    McMullan, G; Chen, S; Henderson, R; Llopart, X; Summerfield, C; Tlustos, L; Faruqi, A R

    2007-01-01

    The electron imaging performance of Medipix2 is described. Medipix2 is a hybrid pixel detector composed of two layers. It has a sensor layer and a layer of readout electronics, in which each 55 μm×55 μm pixel has upper and lower energy discrimination and MHz rate counting. The sensor layer consists of a 300 μm slab of pixellated monolithic silicon and this is bonded to the readout chip. Experimental measurement of the detective quantum efficiency, DQE(0) at 120 keV shows that it can reach 85% independent of electron exposure, since the detector has zero noise, and the DQE(Nyquist) can reach 35% of that expected for a perfect detector (4/π2). Experimental measurement of the modulation transfer function (MTF) at Nyquist resolution for 120 keV electrons using a 60 keV lower energy threshold, yields a value that is 50% of that expected for a perfect detector (2/π). Finally, Monte Carlo simulations of electron tracks and energy deposited in adjacent pixels have been performed and used to calculate expected v...

  10. Proposal for a readout driver card for the ATLAS Insertable B-Layer

    CERN Document Server

    Falchieri, D; The ATLAS collaboration; Bruschi, M; D'Antone, I; Dopke, J; Flick, T; Gabrielli, A; Grosse-Knetter, J; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Polini, A; Rizzi, M; Schroer, N C; Travaglini, R; Zannoli, S; Zoccoli, A

    2010-01-01

    An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design and it will be installed by LHC-PHASE1. New front-end readout ASICs fabrication (FE-I4) will replace the previous chips in this layer. The new system features higher readout speed - 160Mb/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). The poster presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS TDAQ system.

  11. Proposal for a readout driver card for the ATLAS Insertable B-Layer

    CERN Document Server

    Falchieri, D; The ATLAS collaboration; Bruschi, M; D'Antone, I; Dopke, J; Flick, T; Gabrielli, A; Grosse-Knetter, J; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Polini, A; Rizzi, M; Schroer, N; Travaglini, R; Zannoli, S; Zoccoli, A

    2010-01-01

    An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design and it will be installed by Phase 1. New front-end readout ASICs fabrication (FE-I4) will replace the previous chips in this layer. The new system features higher readout speed - 160Mb/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). This paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS TDAQ system.

  12. Characterization of Pixel Sensors

    CERN Document Server

    Oliveira, Felipe Ferraz

    2017-01-01

    It was commissioned at CERN ATLAS pixel group a fluorescence setup for characterization of pixel sensors. The idea is to measure the energies of different targets to calibrate your sensor. It was measured four matrices (80, 95, 98 and 106) of the Investigator1 sensor with different deep PW using copper, iron and titanium as target materials. The matrix 80 has a higher gain (0.065 ± 0.002) and matrix 106 has a better energy resolution (0.05 ± 0.04). The noise of the setup is around 3.6 mV .

  13. Review of results for the NA62 gigatracker read-out prototype

    Science.gov (United States)

    Martin, E.; Aglieri Rinella, G.; Carassiti, V.; Ceccucci, A.; Cortina Gil, E.; Cotta Ramusino, A.; Dellacasa, G.; Fiorini, M.; Garbolino, S.; Jarron, P.; Kaplon, J.; Kluge, A.; Marchetto, F.; Mapelli, A.; Mazza, G.; Morel, M.; Noy, M.; Nuessle, G.; Petagna, P.; Petrucci, F.; Perktold, L.; Riedler, P.; Rivetti, A.; Statera, M.; Velghe, B.

    2012-03-01

    The Gigatracker (GTK) is a hybrid silicon pixel detector developed for NA62, an experiment studying ultra-rare kaon decays at the CERN SPS. The main characteristics are a time-tagging resoluion of 150ps, with low material budget per station (0.5% X0) and a fluence comparable to the one expected for the inner trackers of LHC detectors in 10 years of operation. To compensate the time-walk, two read-out architectures have been designed and produced. The first architecture is based on a Constant Fraction Discriminator (CFD) followed by an on-pixel Time-to-Digital-Converter (TDC). The second architecture is based on a on-pixel group shared TDC. The GTK system developments are described: the integration steps (assembly and cooling) and the results obtained from the prototypes fabricated for the two read-out architectures.

  14. Planar Pixel Sensors for the ATLAS Upgrade: Beam Tests results

    CERN Document Server

    Weingarten, J

    2012-01-01

    The performance of planar silicon pixel sensors, in development for the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades, has been examined in a series of beam tests at the CERN SPS facilities since 2009. Salient results are reported on the key parameters, including the spatial resolution, the charge collection and the charge sharing between adjacent cells, for different bulk materials and sensor geometries. Measurements are presented for n+-in-n pixel sensors irradiated with a range of fluences and for p-type silicon sensors with various layouts from different vendors. All tested sensors were connected via bump-bonding to the ATLAS Pixel read-out chip. The tests reveal that both n-type and p-type planar sensors are able to collect significant charge even after the lifetime fluence expected at the HL-LHC.

  15. Integration of the CMS Phase 1 Pixel Detector

    CERN Document Server

    Kornmayer, Andreas

    2018-01-01

    During the extended year-end technical stop 2016/17 the CMS Pixel Detector has been replaced. The new Phase 1 Pixel Detector is designed for a luminosity that could exceed $\\text{L} = 2x10^{34} cm^{−2}s^{−1}$. With one additional layer in the barrel and the forward region of the new detector, combined with the higher hit rates as the LHC luminosity increases, these conditions called for an upgrade of the data acquisition system, which was realised based on the $\\mu$TCA standard. This contribution focuses on the experiences with integration of the new detector readout and control system and reports on the operational performance of the CMS Pixel detector.

  16. Vertex measurement at a hadron collider. The ATLAS pixel detector

    International Nuclear Information System (INIS)

    Grosse-Knetter, J.

    2008-03-01

    The ATLAS Pixel Detector is the innermost layer of the ATLAS tracking system and will contribute significantly to the ATLAS track and vertex reconstruction. The detector consists of identical sensor-chip-hybrid modules, arranged in three barrels in the centre and three disks on either side for the forward region. The position of the Pixel Detector near the interaction point requires excellent radiation hardness, fast read-out, mechanical and thermal robustness, good long-term stability, all combined with a low material budget. The new design concepts used to meet the challenging requirements are discussed with their realisation in the Pixel Detector, followed by a description of a refined and extensive set of measurements to assess the detector performance during and after its construction. (orig.)

  17. New pixelized Micromegas detector for the COMPASS experiment

    CERN Document Server

    Neyret, Damien; Bedfer, Yann; Burtin, Etienne; d'Hose, Nicole; Giganon, Arnaud; Ketzer, Bernhard; Konorov, Igor; Kunne, Fabienne; Magnon, Alain; Marchand, Claude; Paul, Bernard; Platchkov, Stephane; Vandenbroucke, Maxence

    2009-01-01

    New Micromegas (Micro-mesh gaseous detectors) are being developed in view of the future physics projects planned by the COMPASS collaboration at CERN. Several major upgrades compared to present detectors are being studied: detectors standing five times higher luminosity with hadron beams, detection of beam particles (flux up to a few hundred of kHz/mm^2, 10 times larger than for the present detectors) with pixelized read-out in the central part, light and integrated electronics, and improved robustness. Studies were done with the present detectors moved in the beam, and two first pixelized prototypes are being tested with muon and hadron beams in real conditions at COMPASS. We present here this new project and report on two series of tests, with old detectors moved into the beam and with pixelized prototypes operated in real data taking condition with both muon and hadron beams.

  18. Tracking performance of a single-crystal and a polycrystalline diamond pixel-detector

    Energy Technology Data Exchange (ETDEWEB)

    Menasce, D.; et al.

    2013-06-01

    We present a comparative characterization of the performance of a single-crystal and a polycrystalline diamond pixel-detector employing the standard CMS pixel readout chips. Measurements were carried out at the Fermilab Test Beam Facility, FTBF, using protons of momentum 120 GeV/c tracked by a high-resolution pixel telescope. Particular attention was directed to the study of the charge-collection, the charge-sharing among adjacent pixels and the achievable position resolution. The performance of the single-crystal detector was excellent and comparable to the best available silicon pixel-detectors. The measured average detection-efficiency was near unity, ε = 0.99860±0.00006, and the position-resolution for shared hits was about 6 μm. On the other hand, the performance of the polycrystalline detector was hampered by its lower charge collection distance and the readout chip threshold. A new readout chip, capable of operating at much lower threshold (around 1 ke$-$), would be required to fully exploit the potential performance of the polycrystalline diamond pixel-detector.

  19. Challenges of small-pixel infrared detectors: a review.

    Science.gov (United States)

    Rogalski, A; Martyniuk, P; Kopytko, M

    2016-04-01

    In the last two decades, several new concepts for improving the performance of infrared detectors have been proposed. These new concepts particularly address the drive towards the so-called high operating temperature focal plane arrays (FPAs), aiming to increase detector operating temperatures, and as a consequence reduce the cost of infrared systems. In imaging systems with the above megapixel formats, pixel dimension plays a crucial role in determining critical system attributes such as system size, weight and power consumption (SWaP). The advent of smaller pixels has also resulted in the superior spatial and temperature resolution of these systems. Optimum pixel dimensions are limited by diffraction effects from the aperture, and are in turn wavelength-dependent. In this paper, the key challenges in realizing optimum pixel dimensions in FPA design including dark current, pixel hybridization, pixel delineation, and unit cell readout capacity are outlined to achieve a sufficiently adequate modulation transfer function for the ultra-small pitches involved. Both photon and thermal detectors have been considered. Concerning infrared photon detectors, the trade-offs between two types of competing technology-HgCdTe material systems and III-V materials (mainly barrier detectors)-have been investigated.

  20. ALICE Silicon Pixel Detector

    CERN Multimedia

    Manzari, V

    2013-01-01

    The Silicon Pixel Detector (SPD) forms the innermost two layers of the 6-layer barrel Inner Tracking System (ITS). The SPD plays a key role in the determination of the position of the primary collision and in the reconstruction of the secondary vertices from particle decays.

  1. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Benoit, Mathieu; The ATLAS collaboration

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the “ITk” (Inner Tracker). The innermost portion of the ITk will consist of a pixel detector with stave-like support structures in the most central region and ring-shaped supports in the endcap regions; there may also be novel inclined support structures in the barrel-endcap overlap regions. The new detector could have as much as 14 m2 of sensitive silicon. Support structures will be based on low mass, highly stable and highly thermally conductive carbon-based materials cooled by evaporative carbon dioxide. The ITk will be instrumented with new sensors and readout electronics to provide improved tracking performance compared to the current detector. All the module components must be performant enough and robust enough to cope with the expected high particle multiplicity and severe radiation background of the High-Luminosity LHC. Readout...

  2. Optimization of CMOS active pixels for high resolution digital radiography

    International Nuclear Information System (INIS)

    Kim, Young Soo

    2007-02-01

    CMOS image sensors have poorer performance compared to conventional charge coupled devices (CCDs). Since CMOS Active Pixel Sensors (APSs) in general have higher temporal noise, higher dark current, smaller full well charge capacitance, and lower spectral response, they cannot provide the same wide dynamic range and superior signal-to-noise ratio as CCDs. In view of electronic noise, the main source for the CMOS APS is the pixel, along with other signal processing blocks such as row and column decoder, analog signal processor (ASP), analog-to-digital converter (ADC), and timing and control logic circuitry. Therefore, it is important and necessary to characterize noise of the active pixels in CMOS APSs. We developed our theoretical noise model to account for the temporal noise in active pixels, and then found out the optimum design parameters such as fill actor, each size of the three transistors (source follower, row selection transistor, bias transistor) comprising active pixels, bias current, and load capacitance that can have the maximum signal-to-noise ratio. To develop the theoretical noise model in active pixels, we considered the integration noise of the photodiode and the readout noise of the transistors related to readout. During integration, the shot noise due to the dark current and photocurrent, during readout, the thermal and flicker noise were considered. The developed model can take the input variables such as photocurrent, capacitance of the photodiode, integration time, transconductance of the transistors, channel resistance of the transistors, gate-to-source capacitance of the follower, and load capacitance etc. To validate our noise model, two types of test structures have been realized. Firstly, four types of photodiodes (n diffusion /p substrate , n well /p substrate , n diffusion /p epitaxial /p substrate , n well /p epitaxial /p substrate ) used in CMOS active pixels were fabricated in order to choose the photodiode type having the best SNR

  3. An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process

    OpenAIRE

    Isao Takayanagi; Norio Yoshimura; Kazuya Mori; Shinichiro Matsuo; Shunsuke Tanaka; Hirofumi Abe; Naoto Yasuda; Kenichiro Ishikawa; Shunsuke Okura; Shinji Ohsawa; Toshinori Otaka

    2018-01-01

    To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke−. Readout noise under the highest pixel gain condition is 1 e− with a low noise readout circu...

  4. Development of telescope readout system based on FELIX for testbeam experiments

    CERN Document Server

    Wu, Weihao; Chen, Hucheng; Chen, Kai; Lacobucci, Giuseppe; Lanni, Francessco; Liu, Hongbin; Barrero Pinto, Mateus Vicente; Xu, Lailin

    2017-01-01

    The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration in the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. A testbeam telescope, based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, has been built to characterize the HV-CMOS sensor prototypes. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between front-ends and the commodity switched network in the different detectors of the ATLAS upgrade. A FELIX based readout system has been developed for the readout of the testbeam telescope, which includes a Telescope Readout FMC Card as interface between the IBL DC (double-chip) modules and a Xilinx ZC706 evaluation board. The test results show that the FELIX based telescope readout system is capable of sensor calibration and readout of a high-density pixel detector in test beam experiments in an effective way.

  5. Alpine Pixel Detector Layout

    CERN Document Server

    Delebecque, P; The ATLAS collaboration; Geffroy, N; Massol, N; Rambure, T; Todorov, T

    2013-01-01

    A description of an optimized layout of pixel sensors based on a stave that combines both barrel and endcap module orientations. The mechanical stiffness of the structure is provided by carbon fiber shells spaced by carbon foam. The cooling of the modules is provided by two-phase $CO_{2}$ flowing in a thin titanium pipe glued inside the carbon fiber foam. The electrical services of all modules are provided by a single stave flex. This layout eliminates the need for separate barrel and endcap detector structures, and therefore the barrel services material in front of the endcap. The transition from barrel to endcap module orientation is optimized separately for each layer in order to minimize the active pixel area and the traversed material. The sparse module spacing in the endcap part of the stave allows for multiple fixation points, and for a stiff overall structure composed only of staves interconnected by stiff disks.

  6. CMS pixel upgrade project

    CERN Document Server

    Kaestli, Hans-Christian

    2010-01-01

    The LHC machine at CERN finished its first year of pp collisions at a center of mass energy of 7~TeV. While the commissioning to exploit its full potential is still ongoing, there are plans to upgrade its components to reach instantaneous luminosities beyond the initial design value after 2016. A corresponding upgrade of the innermost part of the CMS detector, the pixel detector, is needed. A full replacement of the pixel detector is planned in 2016. It will not only address limitations of the present system at higher data rates, but will aggressively lower the amount of material inside the fiducial tracking volume which will lead to better tracking and b-tagging performance. This article gives an overview of the project and illuminates the motivations and expected improvements in the detector performance.

  7. CMS pixel upgrade project

    CERN Document Server

    INSPIRE-00575876

    2011-01-01

    The LHC machine at CERN finished its first year of pp collisions at a center of mass energy of 7 TeV. While the commissioning to exploit its full potential is still ongoing, there are plans to upgrade its components to reach instantaneous luminosities beyond the initial design value after 2016. A corresponding upgrade of the innermost part of the CMS detector, the pixel detector, is needed. A full replacement of the pixel detector is planned in 2016. It will not only address limitations of the present system at higher data rates, but will aggressively lower the amount of material inside the fiducial tracking volume which will lead to better tracking and b-tagging performance. This article gives an overview of the project and illuminates the motivations and expected improvements in the detector performance.

  8. Design and test of clock distribution circuits for the Macro Pixel ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L., E-mail: luigi.gaioni@unibg.it [Università di Bergamo, I-24044 Dalmine (Italy); De Canio, F. [Università di Pavia, I-27100 Pavia (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Manghisoni, M. [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Ratti, L. [Università di Pavia, I-27100 Pavia (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Re, V.; Traversi, G. [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy)

    2016-07-11

    Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the High Luminosity LHC. A test chip including low power clock distribution circuits of the MPA has been designed in a 65 nm CMOS technology and thoroughly tested. This work summarizes the experimental results relevant to the prototype chip, focusing particularly on the power and speed performance and compares such results with those coming from circuit simulations.

  9. Low-power clock distribution circuits for the Macro Pixel ASIC

    Science.gov (United States)

    Gaioni, L.; De Canio, F.; Manghisoni, M.; Ratti, L.; Re, V.; Traversi, G.; Marchioro, A.; Kloukinas, K.

    2015-01-01

    Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the HL-LHC. This work reviews different CMOS circuit architectures envisioned for low power clock distribution in the MPA. Two main topologies will be discussed, based on standard supply voltage and on auxiliary, reduced supply. Circuit performance, in terms of power consumption and speed, is evaluated for each of the proposed solutions and compared with that relevant to standard CMOS drivers.

  10. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Flick, Tobias; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the “ITk” (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to |eta| < 3.2 and two to |eta| < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions...

  11. The Phase II ATLAS ITk Pixel Upgrade

    CERN Document Server

    Terzo, Stefano; The ATLAS collaboration

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the "ITk" (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and and ring-shaped supports in the endcap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m$^2$ , depending on the final layout choice, which is expected to take place in early 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel-endcap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as $|\\eta| < 4$. Supporting structures will be ...

  12. Fabrication of a high-density MCM-D for a pixel detector system using a BCB/Cu technology

    CERN Document Server

    Topper, M; Engelmann, G; Fehlberg, S; Gerlach, P; Wolf, J; Ehrmann, O; Becks, K H; Reichl, H

    1999-01-01

    The MCM-D which is described here is a prototype for a pixel detector system for the planned Large Hadron Collider (LHC) at CERN, Geneva. The project is within the ATLAS experiment. The module consists of a sensor tile with an active area of 16.4 mm*60.4 mm, 16 readout chips, each serving 24*160 pixel unit cells, a module controller chip, an optical transceiver and the local signal interconnection and power distribution buses. The extremely high wiring density which is necessary to interconnect the readout chips was achieved using a thin film copper/photo-BCB process above the pixel array. The bumping of the readout chips was done by PbSn electroplating. All dice are then attached by flip-chip assembly to the sensor diodes and the local buses. The focus of this paper is a detailed description of the technologies for the fabrication of this advanced MCM-D. (10 refs).

  13. DAQ architecture and read-out protocole

    CERN Document Server

    Harris, F; Jost, B; Mato, P; Mato, Pere

    1998-01-01

    The proposed LHCb readout architecture is overviewed, followed by discussion and comparison of two candidate readout protocols, namely the 'Full Readout' and'Phased Readout' protocols.The philosophy of the Full Readout protocol is to send all of the event data to a processor before commencing the high level trigger algorithms.This results in simplicity in the protocol at the cost of the bandwidth requirement for the readout network. This is our preferred approach if the network costs are not prohibitive. Using the Phased Readout protocol the event data is sent in portions according to the demands of the trigger algorithms. This results in a more complex protocol, but in a reduction on the readout network bandwidth requirement.The effect of transmission errors on the behaviour of the system, and the implementation of system partitioning, are also discussed.1

  14. Detector Performance and Upgrade Plans of the Pixel Luminosity Telescope for Online per-Bunch Luminosity Measurement at CMS

    CERN Document Server

    CMS Collaboration

    2017-01-01

    The Pixel Luminosity Telescope (PLT) is a dedicated system for luminosity measurement at the CMS experiment using silicon pixel sensors. It was installed during LS1 and has been providing luminosity measurements throughout Run 2. The online bunch-by-bunch luminosity measurement employs the "fast-or" capability of the pixel readout chip (PSI46) to quickly identify likely tracks at the full 40MHz interaction rate. In addition, the full pixel information is read out at a lower rate, allowing for more detailed offline analysis. In this talk, we will present details of the commissioning, performance and operational history of the currently installed hardware and upgrade plans for LS2.

  15. SPAD array chips with full frame readout for crystal characterization

    Energy Technology Data Exchange (ETDEWEB)

    Fischer, Peter; Blanco, Roberto; Sacco, Ilaria; Ritzert, Michael [Heidelberg University (Germany); Weyers, Sascha [Fraunhofer Institute for Microelectronic Circuits and Systems (Germany)

    2015-05-18

    We present single photon sensitive 2D camera chips containing 88x88 avalanche photo diodes which can be read out in full frame mode with up to 400.000 frames per second. The sensors have an imaging area of ~5mm x 5mm covered by square pixels of ~56µm x 56µm with a ~55% fill factor in the latest chip generation. The chips contain a self triggering logic with selectable (column) multiplicities of up to >=4 hits within an adjustable coincidence time window. The photon accumulation time window is programmable as well. First prototypes have demonstrated low dark count rates of <50kHz/mm2 (SPAD area) at 10 degree C for 10% masked pixels. One chip version contains an automated readout of the photon cluster position. The readout of the detailed photon distribution for single events allows the characterization of light sharing, optical crosstalk etc., in crystals or crystal arrays as they are used in PET instrumentation. This knowledge could lead to improvements in spatial or temporal resolution.

  16. Pixel electronic noise as a function of position in an active matrix flat panel imaging array

    Science.gov (United States)

    Yazdandoost, Mohammad Y.; Wu, Dali; Karim, Karim S.

    2010-04-01

    We present an analysis of output referred pixel electronic noise as a function of position in the active matrix array for both active and passive pixel architectures. Three different noise sources for Active Pixel Sensor (APS) arrays are considered: readout period noise, reset period noise and leakage current noise of the reset TFT during readout. For the state-of-the-art Passive Pixel Sensor (PPS) array, the readout noise of the TFT switch is considered. Measured noise results are obtained by modeling the array connections with RC ladders on a small in-house fabricated prototype. The results indicate that the pixels in the rows located in the middle part of the array have less random electronic noise at the output of the off-panel charge amplifier compared to the ones in rows at the two edges of the array. These results can help optimize for clearer images as well as help define the region-of-interest with the best signal-to-noise ratio in an active matrix digital flat panel imaging array.

  17. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Nellist, Clara; The ATLAS collaboration

    2016-01-01

    Summary ATLAS is preparing for an extensive modification of its detector in the course of the planned HL‐ LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all‐silicon detector (Inner Tracker, ITk). A revised trigger and data taking system is foreseen with triggers expected at lowest level at an average rate of 1 MHz. The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL‐LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in early 2017. A new on‐detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on‐going R&D within the ATLAS ITK project towards the new pixel modules and the off‐detector electronics. Pla...

  18. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Munoz Sanchez, Francisca Javiela; The ATLAS collaboration

    2017-01-01

    ATLAS is preparing for an extensive modification of its detector in the course of the planned HL-LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in 2017. A new on-detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on-going R&D within the ATLAS ITK project towards the new pixel modules and the off-detector electronics. Planar and 3D sensors are being re-designed with cell sizes of 50x50 or 25x100 μm2, compatible with the RD53 chip. A sensor thickness equal or less th...

  19. Status of the CMS Phase 1 Pixel Upgrade

    CERN Document Server

    Mattig, Stefan

    2014-01-01

    The silicon pixel detector is the innermost component of the CMS tracking system, providing high precision space point measurements of charged particle trajectories. Before 2018 the instantaneous luminosity of the LHC is expected to reach 2\\,$\\times 10^{34}\\,{\\rm cm^{-2}s^{-1}}$, which will significantly increase the number of interactions per bunch crossing. The current pixel detector of CMS was not designed to work efficiently in such a high occupancy environment and will be degraded by substantial data-loss introduced by buffer filling in the analog Read-Out Chip (ROC) and effects of radiation damage in the sensors, built up over the operational period. To maintain a high tracking efficiency, CMS has planned to replace the current pixel system during ``Phase 1'' (2016/17) by a new lightweight detector, equipped with an additional 4th layer in the barrel, and one additional forward/backward disk. A new digital ROC has been designed, with increased buffers to minimize data-loss, and a digital read-out protoc...

  20. GigaTracker, a Thin and Fast Silicon Pixels Tracker

    CERN Document Server

    Velghe, Bob; Bonacini, Sandro; Ceccucci, Augusto; Kaplon, Jan; Kluge, Alexander; Mapelli, Alessandro; Morel, Michel; Noël, Jérôme; Noy, Matthew; Perktold, Lukas; Petagna, Paolo; Poltorak, Karolina; Riedler, Petra; Romagnoli, Giulia; Chiozzi, Stefano; Cotta Ramusino, Angelo; Fiorini, Massimiliano; Gianoli, Alberto; Petrucci, Ferruccio; Wahl, Heinrich; Arcidiacono, Roberta; Jarron, Pierre; Marchetto, Flavio; Gil, Eduardo Cortina; Nuessle, Georg; Szilasi, Nicolas

    2014-01-01

    GigaTracker, the NA62’s upstream spectrometer, plays a key role in the kinematically constrained background suppression for the study of the K + ! p + n ̄ n decay. It is made of three independent stations, each of which is a six by three cm 2 hybrid silicon pixels detector. To meet the NA62 physics goals, GigaTracker has to address challenging requirements. The hit time resolution must be better than 200 ps while keeping the total thickness of the sensor to less than 0.5 mm silicon equivalent. The 200 μm thick sensor is divided into 18000 300 μm 300 μm pixels bump-bounded to ten independent read-out chips. The chips use an end-of-column architecture and rely on time-over- threshold discriminators. A station can handle a crossing rate of 750 MHz. Microchannel cooling technology will be used to cool the assembly. It allows us to keep the sensor close to 0 C with 130 μm of silicon in the beam area. The sensor and read-out chip performance were validated using a 45 pixel demonstrator with a laser test setu...

  1. FED Firmware Interface Testing with Pixel Phase 1 Emulator

    CERN Document Server

    Kilpatrick, Matthew

    2017-01-01

    A hardware emulation of the CMS pixel detector phase 1 upgrade front-end electronics has been developed to test and validate the architecture of the back-end electronics (FED) firmware. The emulation is implemented on a Virtex 6 FPGA on the CERN GLIB uTCA platform, utilizing an 8-way SFP FPGA Mezzanine Card to drive compatible optical transmitters to the back-end electronics at \\mbox{400 Mbps}. The firmware emulates the complex functions of the phase 1 pixel readout chips (PSI46digv2 and PROC600) and token bit manager ASICs and allows for possible abnormalities that can occur in the output data stream. The emulation implements both fixed data patterns that are used as test vectors and realistic simulated data to drive the readout of the FED at the expected data and trigger rates. Testing software was developed to control the emulator and verify correct transmission of data and exception handling in the FED. An installation has been integrated into the pixel DAQ test system at CMS to be used for fast validatio...

  2. FED firmware interface testing with pixel phase 1 emulator

    CERN Document Server

    Kilpatrick, Matthew

    2017-01-01

    A hardware emulation of the CMS pixel detector phase 1 upgrade front-end electronics has been developed to test and validate the architecture of the back-end electronics (FED) firmware. The emulation is implemented on a Virtex 6 FPGA on the CERN GLIB uTCA platform, utilizing an 8-way SFP FPGA Mezzanine Card to drive compatible optical transmitters to the back-end electronics at 400 bps. The firmware emulates the complex functions of the phase 1 pixel readout chips (PSI46digv2 and PROC600) and token bit manager ASICs and allows for possible abnormalities that can occur in the output data stream. The emulation implements both fixed data patterns that are used as test vectors and realistic simulated data to drive the readout of the FED at the expected data and trigger rates. Testing software was developed to control the emulator and verify correct transmission of data and exception handling in the FED. An installation has been integrated into the pixel DAQ test system at CMS to be used for fast validation of F...

  3. High Dynamic Range X-Ray Detector Pixel Architectures Utilizing Charge Removal

    Science.gov (United States)

    Weiss, Joel T.; Shanks, Katherine S.; Philipp, Hugh T.; Becker, Julian; Chamberlain, Darol; Purohit, Prafull; Tate, Mark W.; Gruner, Sol M.

    2017-04-01

    Several charge integrating CMOS pixel front ends utilizing charge removal techniques have been fabricated to extend dynamic range for X-ray diffraction applications at synchrotron sourcesand X-ray free electron lasers (XFELs). The pixels described herein build on the mixed mode pixel array detector (MM-PAD) framework, developed previously by our group to perform high dynamic range imaging. These new pixels boast several orders of magnitude improvement in maximum flux over the MM-PAD, which is capable of measuring a sustained flux in excess of 108 X-rays/pixel/s while maintaining sensitivity to smaller signals, down to single X-rays. To extend dynamic range, charge is removed from the integration node of the frontend amplifier without interrupting integration. The number of times this process occurs is recorded by a digital counter in the pixel. The parameter limiting full well is, thereby, shifted from the size of an integration capacitor to the depth of a digital counter. The result is similar to that achieved by counting pixel array detectors, but the integrators presented here are designed to tolerate a sustained flux > 1011 X-rays/pixel/s. Pixel front-end linearity was evaluated by direct current injection and results are presented. A small-scale readout ASIC utilizing these pixel architectures has been fabricated and the use of these architectures to increase single X-ray pulse dynamic range at XFELs is discussed briefly.

  4. The pixel hybrid photon detectors for the LHCb-RICH project

    CERN Document Server

    Gys, Thierry

    2001-01-01

    This paper describes a hybrid photon detector with integrated silicon pixel readout to be used in the ring imaging Cherenkov detectors of the LHCb experiment. The photon detector is based on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 5. The anode consists of a silicon pixel array, bump-bonded to a binary readout chip with matching pixel electronics. The paper starts with the general specification of the baseline option. Followed by a summary of the main results achieved so far during the R&D phase. It concludes with a description of the remaining work towards the final photon detector. (17 refs).

  5. Development and characterization of a DEPFET pixel prototype system for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Kohrs, Robert

    2008-09-15

    For the future TeV-scale linear collider ILC (International Linear Collider) a vertex detector of unprecedented performance is needed to fully exploit its physics potential. By incorporating a field effect transistor into a fully depleted sensor substrate the DEPFET (Depleted Field Effect Transistor) sensor combines radiation detection and in-pixel amplification. For the operation at a linear collider the excellent noise performance of DEPFET pixels allows building very thin detectors with a high spatial resolution and a low power consumption. With this thesis a prototype system consisting of a 64 x 128 pixels sensor, dedicated steering and readout ASICs and a data acquisition board has been developed and successfully operated in the laboratory and under realistic conditions in beam test environments at DESY and CERN. A DEPFET matrix has been successfully read out using the on-chip zero-suppression of the readout chip CURO 2. The results of the system characterization and beam test results are presented. (orig.)

  6. A 1006 element hybrid silicon pixel detector with stobed binary output

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Aspell, P.; Beusch, W.; Campbell, M.; Chesi, E.; Glaser, M.; Gys, T.; Heijne, E.H.M.; Jarron, P.; Lemeilleur, F.

    1992-01-01

    An asynchronous version of a binary pixel readout circuit has been implemented in an array with 16 columns at 500 μm pitch and 63 rows at 75 μm pitch. This readout chip has been bonded with solder bumps to a silicon detector with matching pixel elements. event information in a pixel can be strobed into a local memory by a trigger signal and subsequently read out. Without a strobe the information in this memory is continuously cleared. The complete hybrid detector has been successfully tested with ionizing particles from a radioactive source. Three such devices have been put in the CERN heavy ion experiment WA94 in the Omega spectrometer where they recorded particle tracks form high multiplicity 32 S interactions

  7. Development and characterization of a DEPFET pixel prototype system for the ILC vertex detector

    International Nuclear Information System (INIS)

    Kohrs, Robert

    2008-09-01

    For the future TeV-scale linear collider ILC (International Linear Collider) a vertex detector of unprecedented performance is needed to fully exploit its physics potential. By incorporating a field effect transistor into a fully depleted sensor substrate the DEPFET (Depleted Field Effect Transistor) sensor combines radiation detection and in-pixel amplification. For the operation at a linear collider the excellent noise performance of DEPFET pixels allows building very thin detectors with a high spatial resolution and a low power consumption. With this thesis a prototype system consisting of a 64 x 128 pixels sensor, dedicated steering and readout ASICs and a data acquisition board has been developed and successfully operated in the laboratory and under realistic conditions in beam test environments at DESY and CERN. A DEPFET matrix has been successfully read out using the on-chip zero-suppression of the readout chip CURO 2. The results of the system characterization and beam test results are presented. (orig.)

  8. Neural network based cluster creation in the ATLAS silicon pixel detector

    CERN Document Server

    Selbach, K E; The ATLAS collaboration

    2012-01-01

    The read-out from individual pixels on planar semi-conductor sensors are grouped into clusters to reconstruct the location where a charged particle passed through the sensor. The resolution given by individual pixel sizes is significantly improved by using the information from the charge sharing between pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years to obtain an excellent performance. However, in dense environments, such as those inside high-energy jets, clusters have an increased probability of merging the charge deposited by multiple particles. Recently, a neural network based algorithm which estimates both the cluster position and whether a cluster should be split has been developed for the ATLAS pixel detector. The algorithm significantly reduces ambiguities in the assignment of pixel detector measurement to tracks within jets and improves the position accuracy with respect to standard interpolation techniques by taking into account the 2-dimensional ...

  9. Neural network based cluster creation in the ATLAS silicon Pixel Detector

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2013-01-01

    The read-out from individual pixels on planar semi-conductor sensors are grouped into clusters to reconstruct the location where a charged particle passed through the sensor. The resolution given by individual pixel sizes is significantly improved by using the information from the charge sharing between pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years to obtain an excellent performance. However, in dense environments, such as those inside high-energy jets, clusters have an increased probability of merging the charge deposited by multiple particles. Recently, a neural network based algorithm which estimates both the cluster position and whether a cluster should be split has been developed for the ATLAS Pixel Detector. The algorithm significantly reduces ambiguities in the assignment of pixel detector measurement to tracks within jets and improves the position accuracy with respect to standard interpolation techniques by taking into account the 2-dimensional ...

  10. Commissioning of the upgraded ATLAS Pixel Detector for Run2 at LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00016406

    2016-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL), a fourth layer of pixel detectors, installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. An overview of the refurbishing of the Pixel Detector and of the IBL project as well as early performance tests using cosmic rays and beam data will be presented.

  11. The ALICE Pixel Detector

    International Nuclear Information System (INIS)

    Mercado-Perez, Jorge

    2002-01-01

    The present document is a brief summary of the performed activities during the 2001 Summer Student Programme at CERN under the Scientific Summer at Foreign Laboratories Program organized by the Particles and Fields Division of the Mexican Physical Society (Sociedad Mexicana de Fisica). In this case, the activities were related with the ALICE Pixel Group of the EP-AIT Division, under the supervision of Jeroen van Hunen, research fellow in this group. First, I give an introduction and overview to the ALICE experiment; followed by a description of wafer probing. A brief summary of the test beam that we had from July 13th to July 25th is given as well

  12. A novel radiation hard pixel design for space applications

    Science.gov (United States)

    Aurora, A. M.; Marochkin, V. V.; Tuuva, T.

    2017-11-01

    We have developed a novel radiation hard photon detector concept based on Modified Internal Gate Field Effect Transistor (MIGFET) wherein a buried Modified Internal Gate (MIG) is implanted underneath a channel of a FET. In between the MIG and the channel of the FET there is depleted semiconductor material forming a potential barrier between charges in the channel and similar type signal charges located in the MIG. The signal charges in the MIG have a measurable effect on the conductance of the channel. In this paper a radiation hard double MIGFET pixel is investigated comprising two MIGFETs. By transferring the signal charges between the two MIGs Non-Destructive Correlated Double Sampling Readout (NDCDSR) is enabled. The radiation hardness of the proposed double MIGFET structure stems from the fact that interface related issues can be considerably mitigated. The reason for this is, first of all, that interface generated dark noise can be completely avoided and secondly, that interface generated 1/f noise can be considerably reduced due to a deep buried channel readout configuration. Electrical parameters of the double MIGFET pixel have been evaluated by 3D TCAD simulation study. Simulation results show the absence of interface generated dark noise, significantly reduced interface generated 1/f noise, well performing NDCDSR operation, and blooming protection due to an inherent vertical anti-blooming structure. In addition, the backside illuminated thick fully depleted pixel design results in low crosstalk due to lack of diffusion and good quantum efficiency from visible to Near Infra-Red (NIR) light. These facts result in excellent Signal-to-Noise Ratio (SNR) and very low crosstalk enabling thus excellent image quality. The simulation demonstrates the charge to current conversion gain for source current read-out to be 1.4 nA/e.

  13. Characterisation of the NA62 GigaTracker end of column readout ASIC

    CERN Document Server

    Noy, M; Perktold, L; Rinella, G A; Riedler, P; Morel, M; Kluge, A; Kaplon, J; Martin, E; Jarron, P

    2011-01-01

    The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 mu m pitch position information and operate with a dead-time of 1\\% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

  14. Operational experience of ATLAS SCT and Pixel Detector

    CERN Document Server

    Kocian, Martin; The ATLAS collaboration

    2017-01-01

    The ATLAS Inner Detector based on silicon sensors is consisting of a strip detector (SCT) and a pixel detector. It is the crucial component for vertexing and tracking in the ATLAS experiment. With the excellent performance of the LHC well beyond the original specification the silicon tracking detectors are facing substantial challenges in terms of data acquisition, radiation damage to the sensors, and SEUs in the readout ASICs. The approaches on how the detector systems cope with the demands of high luminosity operation while maintaining excellent performance through hardware upgrades, software and firmware algorithms, and operational settings, are presented.

  15. Power distribution and substrate noise coupling investigations on the behavioral level for photon counting imaging readout circuits

    International Nuclear Information System (INIS)

    Lundgren, Jan; Abdalla, Suliman; O'Nils, Mattias; Oelmann, Bengt

    2007-01-01

    In modern mixed-signal system design, there are increasing problems associated with noise coupling caused by switching digital parts to sensitive analog parts. As a consequence, there is a growing necessity to understand these problems. In order to avoid costly design iterations, noise coupling simulations should be initiated as early as possible in the design chain. The problems associated with on-chip noise coupling have been discovered in photon counting pixel detector readout systems, where the level of integration of analog and digital circuits is very high on a very small area, and it would appear that these problems will continue to increase for future system designs in this field. This paper deals with the functionality of utilizing behavioral level models for simulating noise coupling in these readout systems. The methods and models are described and simulation results are shown for a photon counting pixel detector readout system

  16. Transputer-based readout controller

    International Nuclear Information System (INIS)

    Belusevic, R.; Nixon, G.

    1989-01-01

    A bus-oriented readout controller is described that uses a transputer both as a direct memory access (DMA) device and a crate processor. It achieves data transfer rates of up to 13 Mbytes/s, yet is very simple in design. Data transfer is reduced to moving arrays within memory, which eliminates the need for bus arbitration and interfacing logic. A trivial extension of the basic design results in a twofold increase in the maximum data transfer speed, to 27 Mbytes/s. A second transputer, added to the crate controller for extra flexibility and processing power, enables it to form part of a second level data acquisition system, with a total of 8 links (maximum link speed 20 Mbits/s) available for intercrate communications. This design was developed for the readout system of the ZEUS Central Tracking Detector. (orig.)

  17. Transputer-based readout controller

    Energy Technology Data Exchange (ETDEWEB)

    Belusevic, R.; Nixon, G.

    1989-05-01

    A bus-oriented readout controller is described that uses a transputer both as a direct memory access (DMA) device and a crate processor. It achieves data transfer rates of up to 13 Mbytes/s, yet is very simple in design. Data transfer is reduced to moving arrays within memory, which eliminates the need for bus arbitration and interfacing logic. A trivial extension of the basic design results in a twofold increase in the maximum data transfer speed, to 27 Mbytes/s. A second transputer, added to the crate controller for extra flexibility and processing power, enables it to form part of a second level data acquisition system, with a total of 8 links (maximum link speed 20 Mbits/s) available for intercrate communications. This design was developed for the readout system of the ZEUS Central Tracking Detector.

  18. Integration of the Omega-3 readout chip into a high energy physics experimental data acquisition system

    Energy Technology Data Exchange (ETDEWEB)

    Beker, H.; Chesi, E.; Martinengo, P. [European Organization for Nuclear Research, Geneva (Switzerland)

    1997-08-21

    The Omega-3 readout chip is presented in detail elsewhere in the same proceedings. We here describe the integration of the chip into present and future experiments describing both hardware and software aspects. We cover preliminary tests in the laboratory and on the beam. The WA97 experiment has already used a pixel telescope in the past and intends to upgrade to the Omega-3 chip. A newly proposed experiment at CERN studying strangeness production in heavy ion collisions also plans to use a similar telescope. Finally, we give an outlook on the ongoing developments in the pixel readout architecture in the context of ALICE, the heavy ion experiment at the LHC collider. (orig.). 11 refs.

  19. Readout circuit design of the retina-like CMOS image sensor

    Science.gov (United States)

    Cao, Fengmei; Song, Shengyu; Bai, Tingzhu; Cao, Nan

    2015-02-01

    Readout circuit is designed for a special retina-like CMOS image sensor. To realize the pixels timing drive and readout of the sensor, the Altera's Cyclone II FPGA is used as a control chip. The voltage of the sensor is supported by a voltage chip initialized by SPI with AVR MCU system. The analog image signal outputted by the sensor is converted to digital image data by 12-bits A/D converter ADS807 and the digital data is memorized in the SRAM. Using the Camera-link image grabber, the data stored in SRAM is transformed to image shown on PC. Experimental results show the circuit works well on retina-like CMOS timing drive and image readout and images can be displayed properly on the PC.

  20. CMS Pixel Detector design for HL-LHC

    CERN Document Server

    Migliore, Ernesto

    2016-01-01

    The LHC machine is planning an upgrade program which will smoothly bring the luminosity to about 7.5$\\times$10$^{34}$cm$^{-2}$s$^{-1}$ in 2028, to possibly reach an integrated luminosity of 3000 fb$^{-1}$ by the end of 2037. This High Luminosity scenario, HL-LHC, will present new challenges in higher data rates and increased radiation.In order to maintain its physics reach the CMS Collaboration has undertaken a preparation program of the detector known as Phase-2 upgrade. The CMS Phase-2 Pixel upgrade will require a high bandwidth readout system and high radiation tolerance for sensors and on-detector ASICs. Several technologies for the upgrade sensors are being studied. Serial powering schemes are under consideration to accommodate significant constraints on the system. These prospective designs, as well as new layout geometries that include very forward pixel discs, will be presented together with performance estimations.

  1. Online Calibration and Performance of the ATLAS Pixel Detector

    CERN Document Server

    Keil, M

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 million electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. This paper describes the tuning and calibration of the optical links and the detector modules, including measurements of threshold, noise, charge measurement, timing performance and the sensor leakage current.

  2. Test-beam results of a SOI pixel detector prototype

    CERN Document Server

    Bugiel, Roma; Dannheim, Dominik; Fiergolski, Adrian; Hynds, Daniel; Idzik, Marek; Kapusta, P; Kucewicz, Wojciech; Munker, Ruth Magdalena; Nurnberg, Andreas Matthias

    2018-01-01

    This paper presents the test-beam results of a monolithic pixel-detector prototype fabricated in 200 nm Silicon-On-Insulator (SOI) CMOS technology. The SOI detector was tested at the CERN SPS H6 beam line. The detector is fabricated on a 500 μm thick high-resistivity float- zone n-type (FZ-n) wafer. The pixel size is 30 μm × 30 μm and its readout uses a source- follower configuration. The test-beam data are analysed in order to compute the spatial resolution and detector efficiency. The analysis chain includes pedestal and noise calculation, cluster reconstruction, as well as alignment and η-correction for non-linear charge sharing. The results show a spatial resolution of about 4.3 μm.

  3. An EUDET/AIDA Pixel Beam Telescope for Detector Development

    CERN Document Server

    Rubinskiy, I

    2015-01-01

    Ahigh resolution(σ< 2 μm) beam telescope based on monolithic active pixel sensors (MAPS) was developed within the EUDET collaboration. EUDET was a coordinated detector R&D programme for the future International Linear Collider providing test beam infrastructure to detector R&D groups. The telescope consists of six sensor planes with a pixel pitch of either 18.4 μm or 10 μmand canbe operated insidea solenoidal magnetic fieldofupto1.2T.Ageneral purpose cooling, positioning, data acquisition (DAQ) and offine data analysis tools are available for the users. The excellent resolution, readout rate andDAQintegration capabilities made the telescopea primary beam tests tool also for several CERN based experiments. In this report the performance of the final telescope is presented. The plans for an even more flexible telescope with three differentpixel technologies(ATLASPixel, Mimosa,Timepix) withinthenew European detector infrastructure project AIDA are presented.

  4. Capacitively coupled hybrid pixel assemblies for the CLIC vertex detector

    CERN Document Server

    AUTHOR|(SzGeCERN)734627; Benoit, Mathieu; Dannheim, Dominik; Dette, Karola; Hynds, Daniel; Kulis, Szymon; Peric, Ivan; Petric, Marko; Redford, Sophie; Sicking, Eva; Valerio, Pierpaolo

    2016-01-01

    The vertex detector at the proposed CLIC multi-TeV linear e+e- collider must have minimal material content and high spatial resolution, combined with accurate time-stamping to cope with the expected high rate of beam-induced backgrounds. One of the options being considered is the use of active sensors implemented in a commercial high-voltage CMOS process, capacitively coupled to hybrid pixel ASICs. A prototype of such an assembly, using two custom designed chips (CCPDv3 as active sensor glued to a CLICpix readout chip), has been characterised both in the lab and in beam tests at the CERN SPS using 120 GeV/c positively charged hadrons. Results of these characterisation studies are presented both for single and dual amplification stages in the active sensor. Pixel cross-coupling results are also presented, showing the sensitivity to placement precision and planarity of the glue layer.

  5. The Datura Pixel Beam Telescope - Setup and first results

    Energy Technology Data Exchange (ETDEWEB)

    Eckstein, Doris; Eichhorn, Thomas; Gregor, Ingrid-Maria; Rubinskiy, Igor; Perrey, Hanno [DESY (Germany)

    2013-07-01

    The Datura pixel telescope is an upgraded version of the original Eudet beam telescope. It consists of six planes of Mimosa 26 monolithic active pixel sensors, mounted on two lever arms with three planes each. The sensor positioning is flexible and there is the possibility of including a central device under test (DUT). With the telescope, a pointing precision of under 3 μm at the DUT can be achieved. Cooling of sensors and DUT, positioning and read-out infrastructure are included. The telescope provides a flexible and general purpose testing environment for various sensor technologies. In this talk telescope resolution measurements at the low energy DESY e{sup +}/e{sup -} test beam are presented.

  6. The ALICE pixel detector

    CERN Document Server

    Mercado Perez, J

    2002-01-01

    The present document is a brief summary of the performed activities during the 2001 Summer Student Programme at CERN under the Scientific Summer at Foreign Laboratories Program organized by the Particles and Fields Division of the Mexican Physical Society (Sociedad Mexicana de Fisica). In this case, the activities were related with the ALICE Pixel Group of the EP-AIT Division, under the supervision of Jeroen van Hunen, research fellow in this group. First, I give an introduction and overview to the ALICE experiment; followed by a description of wafer probing. A brief summary of the test beam that we had from July 13th to July 25th is given as well. (3 refs).

  7. The Upgraded Pixel Detector of the ATLAS Experiment for Run-2

    CERN Document Server

    Ferrere, Didier; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented, using collision data.

  8. Simulation and laboratory test results of 3D CMS pixel detectors for HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Alagoz, E. [Purdue U.; Bubna, M. [Purdue U.; Krzywda, A. [Purdue U.; Dalla Betta, G. F. [Trento U.; Povoli, M. [Trento U.; Obertino, M. M. [INFN, Turin; Solano, A. [INFN, Turin; Vilela Pereira, A. [Rio de Janeiro State U.; Arndt, K. [Purdue U.; Bolla, G. [Purdue U.; Bortoletto, D. [Purdue U.; Boscardin, M. [Fond. Bruno Kessler, Povo; Kwan, S. [Fermilab; Rivera, R. [Fermilab; Shipsey, I. [Purdue U.; Uplegger, L. [Fermilab

    2012-08-01

    The CMS pixel detector is the innermost tracking device at the LHC, reconstructing interaction vertices and charged particle trajectories. The current planar sensors located in the innermost layer of the pixel detector will be exposed to very high fluences which will degrade their performances. As a possible replacement for planar pixel sensors in the High Luminosity-LHC (HL-LHC), 3D silicon technology is under consideration due to its expected good performance in harsh radiation environments. Studies are also in progress for using 3D silicon pixel detectors in near-beam proton spectrometers at the LHC. Deep Reactive Ion Etching (DRIE) plays a key role in fabricating 3D silicon detectors in which readout and ohmic electrodes are processed through the silicon substrate instead of being implanted on the silicon surface. 3D pixel devices considered in this study were processed at FBK (Trento, Italy), bump bonded to the CMS pixel readout chip, and characterized in the laboratory. Numerical simulations were also carried out. We report on selected results from laboratory measurements and TCAD simulations.

  9. Study of FPGA and GPU based pixel calibration for ATLAS IBL

    CERN Document Server

    Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Grosse-Knetter, J; Krieger, N; Kugel, A; Polini, A; Schroer, N

    2010-01-01

    The insertable B-layer (IBL) is a new stage of the ATLAS pixel detector to be installed around 2014. 12 million pixel are attached to new FE-I4 readout ASICs, each controlling 26680 pixel. Compared to the existing FE-I3 based detector the new system features higher readout speed of 160Mbit/s per ASIC and simplified control. For calibration defined charges are applied to all pixels and the resulting time-over-threshold values are evaluated. In the present system multiple sets of two custom VME cards which employ a combination of FPGA and DSP technology are used for I/O interfacing, formatting and processing. The execution time of 51s to perform a threshold scan on a FE-I3 module of 46080 pixel is composed of 8s control, 29s transfer, 7.5s histogramming and 7s analysis. Extrapolating to FE-I4 the times per module of 53760 pixels are 12ms, 5.8s, 9.4s and 8.3s, a total of 23.5s. We present a proposal for a novel approach to the dominant tasks for FE-I4: histogramming and ananlysis. An FPGA-based histogramming uni...

  10. The Upgraded Pixel Detector of the ATLAS Experiment for Run-2 at the LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00084948; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130 nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented using collision data.

  11. The upgraded Pixel Detector of the ATLAS experiment for Run-2 at the Large Hadron Collider

    CERN Document Server

    Giordani, MarioPaolo; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented, using collision data.

  12. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    Backhaus, Malte; The ATLAS collaboration

    2015-01-01

    Run-2 of the LHC will provide new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been developed as well as a new read-out chip within CMOS 130nm technology and with larger area, smaller pixel size and faster readout capability. The new detector is the first large scale application of of 3D detectors and CMOS 130nm technology. An overview of the lessons learned during the IBL project will be presented, focusing on the challenges and highlighting the issues met during the productio...

  13. Si and gaas pixel detectors for medical imaging applications

    International Nuclear Information System (INIS)

    Bisogni, M. G.

    2001-01-01

    As the use of digital radiographic equipment in the morphological imaging field is becoming the more and more diffuse, the research of new and more performing devices from public institutions and industrial companies is in constant progress. Most of these devices are based on solid-state detectors as X-ray sensors. Semiconductor pixel detectors, originally developed in the high energy physics environment, have been then proposed as digital detector for medical imaging applications. In this paper a digital single photon counting device, based on silicon and GaAs pixel detector, is presented. The detector is a thin slab of semiconductor crystal where an array of 64 by 64 square pixels, 170- m side, has been built on one side. The data read-out is performed by a VLSI integrated circuit named Photon Counting Chip (PCC), developed within the MEDIPIX collaboration. Each chip cell geometrically matches the sensor pixel. It contains a charge preamplifier, a threshold comparator and a 15 bits pseudo-random counter and it is coupled to the detector by means of bump bonding. Most important advantages of such system, with respect to a traditional X-rays film/screen device, are the wider linear dynamic range (3x104) and the higher performance in terms of MTF and DQE. Besides the single photon counting architecture allows to detect image contrasts lower than 3%. Electronics read-out performance as well as imaging capabilities of the digital device will be presented. Images of mammographic phantoms acquired with a standard Mammographic tube will be compared with radiographs obtained with traditional film/screen systems

  14. Adaptive Digital Scan Variable Pixels

    OpenAIRE

    Sugathan, Sherin; Scaria, Reshma; James, Alex Pappachen

    2015-01-01

    The square and rectangular shape of the pixels in the digital images for sensing and display purposes introduces several inaccuracies in the representation of digital images. The major disadvantage of square pixel shapes is the inability to accurately capture and display the details in the objects having variable orientations to edges, shapes and regions. This effect can be observed by the inaccurate representation of diagonal edges in low resolution square pixel images. This paper explores a...

  15. The ALICE Silicon Pixel Detector

    International Nuclear Information System (INIS)

    Kluge, A.; Rinella, G. Aglieri; Anelli, G.; Antinori, F.; Badala, A.; Burns, M.; Cali, I.A.; Campbell, M.; Caselle, M.; Ceresa, S.; Chochula, P.; Dima, R.; Elias, D.; Fabris, D.; Fini, R.A.; Formenti, F.; Krivda, M.; Lenti, V.; Librizzi, F.; Manzari, V.

    2007-01-01

    The ALICE Silicon Pixel Detector (SPD) forms the two innermost layers of the ALICE inner tracker system. It contains 9.8x10 6 pixels with a material budget of less than 1% of X 0 per layer. It is based on hybrid pixel technology. The space and material budget constraints have severe impact on the design. The ALICE SPD detector system components are discussed

  16. Study of micro pixel photon counters for a high granularity scintillator-based hadron calorimeter

    International Nuclear Information System (INIS)

    D'Ascenzo, N.; Eggemann, A.; Garutti, E.

    2007-11-01

    A new Geiger mode avalanche photodiode, the Micro Pixel Photon Counter (MPPC), was recently released by Hamamatsu. It has a high photo-detection efficiency in the 420 nm spectral region. This product can represent an elegant candidate for the design of a high granularity scintillator based hadron calorimeter for the International Linear Collider. In fact, the direct readout of the blue scintillation photons with a MPPC is a feasible techological solution. The readout of a plastic scintillator by a MPPC, both mediated by the traditional wavelength shifting fiber, and directly coupled, has been systematically studied. (orig.)

  17. Spectral characterisation and noise performance of Vanilla—an active pixel sensor

    Science.gov (United States)

    Blue, Andrew; Bates, R.; Bohndiek, S. E.; Clark, A.; Arvanitis, Costas D.; Greenshaw, T.; Laing, A.; Maneuski, D.; Turchetta, R.; O'Shea, V.

    2008-06-01

    This work will report on the characterisation of a new active pixel sensor, Vanilla. The Vanilla comprises of 512×512 (25μm 2) pixels. The sensor has a 12 bit digital output for full-frame mode, although it can also be readout in analogue mode, whereby it can also be read in a fully programmable region-of-interest (ROI) mode. In full frame, the sensor can operate at a readout rate of more than 100 frames per second (fps), while in ROI mode, the speed depends on the size, shape and number of ROIs. For example, an ROI of 6×6 pixels can be read at 20,000 fps in analogue mode. Using photon transfer curve (PTC) measurements allowed for the calculation of the read noise, shot noise, full-well capacity and camera gain constant of the sensor. Spectral response measurements detailed the quantum efficiency (QE) of the detector through the UV and visible region. Analysis of the ROI readout mode was also performed. Such measurements suggest that the Vanilla APS (active pixel sensor) will be suitable for a wide range of applications including particle physics and medical imaging.

  18. Self-adjusting threshold mechanism for pixel detectors

    Science.gov (United States)

    Heim, Timon; Garcia-Sciveres, Maurice

    2017-09-01

    Readout chips of hybrid pixel detectors use a low power amplifier and threshold discrimination to process charge deposited in semiconductor sensors. Due to transistor mismatch each pixel circuit needs to be calibrated individually to achieve response uniformity. Traditionally this is addressed by programmable threshold trimming in each pixel, but requires robustness against radiation effects, temperature, and time. In this paper a self-adjusting threshold mechanism is presented, which corrects the threshold for both spatial inequality and time variation and maintains a constant response. It exploits the electrical noise as relative measure for the threshold and automatically adjust the threshold of each pixel to always achieve a uniform frequency of noise hits. A digital implementation of the method in the form of an up/down counter and combinatorial logic filter is presented. The behavior of this circuit has been simulated to evaluate its performance and compare it to traditional calibration results. The simulation results show that this mechanism can perform equally well, but eliminates instability over time and is immune to single event upsets.

  19. Diamond pixel modules

    CERN Document Server

    Gan, K K; Robichaud, A; Potenza, R; Kuleshov, S; Kagan, H; Kass, R; Wermes, N; Dulinski, W; Eremin, V; Smith, S; Sopko, B; Olivero, P; Gorisek, A; Chren, D; Kramberger, G; Schnetzer, S; Weilhammer, P; Martemyanov, A; Hugging, F; Pernegger, H; Lagomarsino, S; Manfredotti, C; Mishina, M; Trischuk, W; Dobos, D; Cindro, V; Belyaev, V; Duris, J; Claus, G; Wallny, R; Furgeri, A; Tuve, C; Goldstein, J; Sciortino, S; Sutera, C; Asner, D; Mikuz, M; Lo Giudice, A; Velthuis, J; Hits, D; Griesmayer, E; Oakham, G; Frais-Kolbl, H; Bellini, V; D'Alessandro, R; Cristinziani, M; Barbero, M; Schaffner, D; Costa, S; Goffe, M; La Rosa, A; Bruzzi, M; Schreiner, T; de Boer, W; Parrini, G; Roe, S; Randrianarivony, K; Dolenc, I; Moss, J; Brom, J M; Golubev, A; Mathes, M; Eusebi, R; Grigoriev, E; Tsung, J W; Mueller, S; Mandic, I; Stone, R; Menichelli, D

    2011-01-01

    With the commissioning of the LHC in 2010 and upgrades expected in 2015, ATLAS and CMS are planning to upgrade their innermost tracking layers with radiation hard technologies. Chemical Vapor Deposition diamond has been used extensively in beam conditions monitors as the innermost detectors in the highest radiation areas of BaBar, Belle, CDF and all LHC experiments. This material is now being considered as a sensor material for use very close to the interaction region where the most extreme radiation conditions exist Recently the RD42 collaboration constructed, irradiated and tested polycrystalline and single-crystal chemical vapor deposition diamond sensors to the highest fluences expected at the super-LHC. We present beam test results of chemical vapor deposition diamond up to fluences of 1.8 x 10(16) protons/cm(2) illustrating that both polycrystalline and single-crystal chemical vapor deposition diamonds follow a single damage curve. We also present beam test results of irradiated complete diamond pixel m...

  20. Pixel hybrid photon detector magnetic distortions characterization and compensation

    CERN Document Server

    Aglieri-Rinella, G; D'Ambrosio, Carmelo; Forty, Roger W; Gys, Thierry; Patel, Mitesh; Piedigrossi, Didier; Van Lysebetten, Ann

    2004-01-01

    The LHCb experiment requires positive kaon identification in the momentum range 2-100 GeV/c. This is provided by two ring imaging Cherenkov detectors. The stringent requirements on the photon detectors are fully satisfied by the novel pixel hybrid photon detector, HPD. The HPD is a vacuum tube with a quartz window, S20 photo-cathode, cross-focusing electron optics and a silicon anode encapsulated within the tube. The anode is a 32*256 pixels hybrid detector, with a silicon sensor bump-bonded onto a readout chip containing 8192 channels with analogue front-end and digital read-out circuitry. An external magnetic field influences the trajectory of the photoelectrons and could thereby degrade the inherent excellent space resolution of the HPD. The HPDs must be operational in the fringe magnetic field of the LHCb magnet. This paper reports on an extensive experimental characterization of the distortion effects. The characterization has allowed the development of parameterisations and of a compensation algorithm. ...

  1. A 128 pixel linear array for radiotherapy quality assurance

    Energy Technology Data Exchange (ETDEWEB)

    Franco, L. [Departmento de Fisica de Particulas, Facultade de Fisica, Universidade de Santiago, campus sur s/n, 15782 Santiago de Compostela (Spain); Gomez, F. [Departmento de Fisica de Particulas, Facultade de Fisica, Universidade de Santiago, campus sur s/n, 15782 Santiago de Compostela (Spain)]. E-mail: faustgr@usc.es; Iglesias, A. [Departmento de Fisica de Particulas, Facultade de Fisica, Universidade de Santiago, campus sur s/n, 15782 Santiago de Compostela (Spain); Lobato, R. [Hospital Clinico Universitario de Santiago, 15706 Santiago (Spain); Marin, J. [CIEMAT, Laboratorio de Electronica y Automatica, 28040 Madrid Spain (Spain); Mosquera, J. [Hospital Clinico Universitario de Santiago, 15706 Santiago (Spain); Pardo, J. [Departmento de Fisica de Particulas, Facultade de Fisica, Universidade de Santiago, campus sur s/n, 15782 Santiago de Compostela (Spain)]. E-mail: juanpm@usc.es; Pazos, A. [Departmento de Fisica de Particulas, Facultade de Fisica, Universidade de Santiago, campus sur s/n, 15782 Santiago de Compostela (Spain); Pena, J. [Departmento de Fisica de Particulas, Facultade de Fisica, Universidade de Santiago, campus sur s/n, 15782 Santiago de Compostela (Spain); Pombar, M. [Hospital Clinico Universitario de Santiago, 15706 Santiago (Spain); Rodriguez, A. [Departmento de Fisica de Particulas, Facultade de Fisica, Universidade de Santiago, campus sur s/n, 15782 Santiago de Compostela (Spain); Saavedra, D. [Universidade da Coruna, Dpto. de Enxeneria Industrial II, 15403 Ferrol Spain (Spain); Sendon, J. [Hospital Clinico Universitario de Santiago, 15706 Santiago (Spain); Yanez, A. [Universidade da Coruna, Dpto. de Enxeneria Industrial II, 15403 Ferrol Spain (Spain)

    2004-12-11

    New radiotherapy techniques require detectors able to verify and monitor the clinical beam with high spatial resolution and fast response. Room temperature organic liquid ionization detectors are becoming an alternative to standard air ionization chambers, due to their tissue equivalent behavior, their sensibility and small directional dependence. A liquid isooctane filled ionization linear array for radiotherapy quality assurance has been designed, built and tested. The detector consists of 128 pixels, each of them with an area of 1.7mmx1.7mm and a gap of 0.5mm. The small pixel size makes the detector ideal for high gradient beam profiles like those present in Intensity Modulated Radiation Therapy. The gap and the polarization voltage have been chosen in order to guarantee a linear relationship between the dose rate and the readout signal at high dose rates. As readout electronics we use the X-ray Data Acquisition System with the Xchip developed by the CCLRC.In the first device tests we have confirmed linearity up to a 6.7Gy/min dose rate with a deviation less than 1%. A profile with a signal-to-noise ratio around 500 can be obtained for a 4Gy/min dose rate with a 10 ms integration time.

  2. A 128 pixel linear array for radiotherapy quality assurance

    International Nuclear Information System (INIS)

    Franco, L.; Gomez, F.; Iglesias, A.; Lobato, R.; Marin, J.; Mosquera, J.; Pardo, J.; Pazos, A.; Pena, J.; Pombar, M.; Rodriguez, A.; Saavedra, D.; Sendon, J.; Yanez, A.

    2004-01-01

    New radiotherapy techniques require detectors able to verify and monitor the clinical beam with high spatial resolution and fast response. Room temperature organic liquid ionization detectors are becoming an alternative to standard air ionization chambers, due to their tissue equivalent behavior, their sensibility and small directional dependence. A liquid isooctane filled ionization linear array for radiotherapy quality assurance has been designed, built and tested. The detector consists of 128 pixels, each of them with an area of 1.7mmx1.7mm and a gap of 0.5mm. The small pixel size makes the detector ideal for high gradient beam profiles like those present in Intensity Modulated Radiation Therapy. The gap and the polarization voltage have been chosen in order to guarantee a linear relationship between the dose rate and the readout signal at high dose rates. As readout electronics we use the X-ray Data Acquisition System with the Xchip developed by the CCLRC.In the first device tests we have confirmed linearity up to a 6.7Gy/min dose rate with a deviation less than 1%. A profile with a signal-to-noise ratio around 500 can be obtained for a 4Gy/min dose rate with a 10 ms integration time

  3. R and D of MPGD-readout TPC for the International Linear Collider experiment

    International Nuclear Information System (INIS)

    Yonamine, R

    2012-01-01

    A Time Projection Chamber (TPC) is chosen for the central tracker of the ILD detector, one of two detector concepts planned for the International Linear Collider (ILC). Physics goals at the ILC will require a TPC with a position resolution of 100 μm and superior track separation, which are not achievable with a conventional Multi-Wire Proportional Chamber (MWPC) readout. A MPGD readout offers improved position resolution and track separation due to measuring the signal at the anode and minimization of E × B effect. For several years, the LC TPC collaboration has been developing a MPGD readout using various small TPC prototypes and the Large Prototype TPC that is operated in a test beam at DESY. The MPGD technologies being tested are GEM and Micromegas with resistive charge broadening, with both traditional pad and CMOS pixel readout. Readout modules with both GEM and Micromegas gas amplification have achieved a position resolution on the order of 100 μm at B = 1 T. In this paper we report on the recent R and D toward the ILD TPC.

  4. ATLAS Pixel Detector Operational Experience

    CERN Document Server

    Di Girolamo, B; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.9% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  5. Fully depleted CMOS pixel sensor development and potential applications

    Energy Technology Data Exchange (ETDEWEB)

    Baudot, J.; Kachel, M. [Universite de Strasbourg, IPHC, 23 rue du Loess 67037 Strasbourg (France); CNRS, UMR7178, 67037 Strasbourg (France)

    2015-07-01

    low noise figure. Especially, an energy resolution of about 400 eV for 5 keV X-rays was obtained for single pixels. The prototypes have then been exposed to gradually increased fluences of neutrons, from 10{sup 13} to 5x10{sup 14} neq/cm{sup 2}. Again laboratory tests allowed to evaluate the signal over noise persistence on the different pixels implemented. Currently our development mostly targets the detection of soft X-rays, with the ambition to develop a pixel sensor matching counting rates as affordable with hybrid pixel sensors, but with an extended sensitivity to low energy and finer pixel about 25 x 25 μm{sup 2}. The original readout architecture proposed relies on a two tiers chip. The first tier consists of a sensor with a modest dynamic in order to insure low noise performances required by sensitivity. The interconnected second tier chip enhances the read-out speed by introducing massive parallelization. Performances reachable with this strategy combining counting and integration will be detailed. (authors)

  6. X-ray imaging characterization of active edge silicon pixel sensors

    International Nuclear Information System (INIS)

    Ponchut, C; Ruat, M; Kalliopuska, J

    2014-01-01

    The aim of this work was the experimental characterization of edge effects in active-edge silicon pixel sensors, in the frame of X-ray pixel detectors developments for synchrotron experiments. We produced a set of active edge pixel sensors with 300 to 500 μm thickness, edge widths ranging from 100 μm to 150 μm, and n or p pixel contact types. The sensors with 256 × 256 pixels and 55 × 55 μm 2 pixel pitch were then bump-bonded to Timepix readout chips for X-ray imaging measurements. The reduced edge widths makes the edge pixels more sensitive to the electrical field distribution at the sensor boundaries. We characterized this effect by mapping the spatial response of the sensor edges with a finely focused X-ray synchrotron beam. One of the samples showed a distortion-free response on all four edges, whereas others showed variable degrees of distortions extending at maximum to 300 micron from the sensor edge. An application of active edge pixel sensors to coherent diffraction imaging with synchrotron beams is described

  7. The ALICE silicon pixel detector system

    International Nuclear Information System (INIS)

    Kapusta, S.

    2009-01-01

    The Large Hadron Collider (LHC) is again reaching its startup phase at the European Organization for Particle Physics (CERN). The LHC started its operation on the 10 th of September, 2008 with huge success managing to sent the the first beam successfully around the entire ring in less than an hour after the first injection in one direction, and later that day in the opposite direction. Unfortunately, on the 19 th of September, an accident occurred during the 5.5 TeV magnet commissioning in Sector 34, which will significantly delay the operation of the LHC. The ALICE experiment will exploit the collisions of accelerated ions produced at the LHC to study strongly interacting matter at extreme densities and high temperatures. e ALICE Silicon Pixel Detector (SPD) represents the two innermost layers of the ALICE Inner Traing System (ITS) located at radii of 3.9 cm and 7.6 cm from the Interaction Point (IP). One of the main tasks of the SPD is to provide precise traing information. is information is fundamental for the study of weak decays of heavy flavor particles, since the corresponding signature is a secondary vertex separated from the primary vertex only by a few hundred micrometers. e tra density could be as high as 80 tracks per cm 2 in the innermost SPD layer as a consequence of a heavy ion collision. The SPD will provide a spatial resolution of around ≅12 μm in the rφ direction and ≅70 μm in the z direction. The expected occupancy of the SPD ranges from 0.4% to 1.5% which makes it an excellent charged particle multiplicity detector in the pseudorapidity region |η| < 2. Furthermore, by combining all possible hits in the SPD, one can get a rough estimate of the position of the primary interaction. One of the challenges is the tight material budget constraint (<1% radiation length per layer) in order to limit the scattering of the traversing particles. e silicon sensor and its readout chip have a total thickness of only 350 μm and the signal lines from the

  8. Planar Pixel Sensors for the ATLAS tracker upgrade at HL-LHC

    CERN Document Server

    Gallrapp, Christian

    2013-01-01

    The ATLAS Planar Pixel Sensor R&D Project is a collaboration of 17 institutes and more than 80 scientists. Their goal is to explore the operation of planar pixel sensors for the tracker upgrade at the High Luminosity-Large Hadron Collider (HL-LHC). This work will give a summary of the achievements on radiation studies with n-in-n and n-in-p pixel sensors, bump-bonded to ATLAS FE-I3 and FE-I4 readout chips. The summary includes results from tests with radioactive sources and tracking efficiencies extracted from test beam measurements. Analysis results of ${2\\cdot10^{16}} \\text{n}_{\\text{eq}}\\text{cm}^{-2}$ and ${1\\cdot10^{16}} \\text{n}_{\\text{eq}}\\text{cm}^{-2}$ ($1 \\text{MeV}$ neutron equivalent) irradiated n-in-n and n-in-p modules confirm the operation of planar pixel sensors for future applications.

  9. Performance of the Pixel Luminosity Telescope for Luminosity Measurement at CMS during Run2

    CERN Document Server

    Lujan, Paul Joseph

    2017-01-01

    The Pixel Luminosity Telescope (PLT) is a dedicated system for luminosity measurement at the CMS experiment using silicon pixel sensors arranged into telescopes, each consisting of three sensor planes. It was installed in CMS at the beginning of 2015 and has been providing online and offline luminosity measurements throughout Run 2 of the LHC. The online bunch-by-bunch luminosity measurement employs the fast-or capability of the pixel readout chip to identify events where a hit is registered in all three sensors in a telescope, corresponding primarily to tracks originating from the interaction point. In addition, the full pixel information is read out at a lower rate, allowing for the calculation of corrections to the online luminosity from effects such as the miscounting of tracks not originating from the interaction point and detector efficiency. This paper presents results from the 2016 running of the PLT, including commissioning and operational history, luminosity calibration using Van der Meer scans, and...

  10. Performance of the Pixel Luminosity Telescope for Luminosity Measurement at CMS during Run 2

    CERN Document Server

    CMS Collaboration

    2017-01-01

    The Pixel Luminosity Telescope (PLT) is a dedicated system for luminosity measurement at the CMS experiment using silicon pixel sensors arranged into "telescopes", each consisting of three planes. It was installed during LS1 at the beginning of 2015 and has been providing online and offline luminosity measurements throughout Run 2. The online bunch-by-bunch luminosity measurement employs the "fast-or" capability of the pixel readout chip (PSI46) to identify events where a hit is registered in all three sensors in a telescope corresponding primarily to tracks originating from the interaction point. In addition, the full pixel information is read out at a lower rate, allowing for the calculation of corrections to the online luminosity from effects such as the miscounting of tracks not originating from the interaction point and detector efficiency. In this talk, we will present results from 2016 running and preliminary 2017 results, including commissioning and operational history, luminosity calibration using Va...

  11. Investigation of DEPFET as vertex detector at ILC. Intrinsic properties, radiation hardness and alternative readout schemes

    Energy Technology Data Exchange (ETDEWEB)

    Rummel, Stefan

    2009-07-20

    The International Linear Collider (ILC) is supposed to be the next generation lepton collider. The detectors at ILC are intended to be precision instruments improving the performance in impact parameter (IP), momentum and energy resolution significantly compared to previous detectors at lepton colliders. To achieve this goal it is necessary to develop new detector technologies or pushing existing technologies to their technological edges. Regarding the Vertex detector (VTX) this implies challenges in resolution, material budget, power consumption and readout speed. A promising technology for the Vertex detector is the Depleted Field Effect Transistor (DEPFET). The DEPFET is a semiconductor device with in-pixel ampli cation integrated on a fully depleted bulk. This allows building detectors with intrinsically high SNR due to the large sensitive volume and the small input capacitance at the rst ampli er. To reach the ambitious performance goals it is important to understand its various features: clear performance, internal amplification, noise and radiation hardness. The intrinsic noise is analyzed, showing that the contribution of the DEPFET is below 50 e{sup -} at the required speed. Moreover it is possible to show that the internal ampli cation could be further improved to more than 1nA/e{sup -} using the standard DEPFET technology. The clear performance is investigated on matrix level utilizing a dedicated setup for single pixel testing which allows direct insight into the DEPFET operation, without the complexity of the full readout system. It is possible to show that a full clear could be achieved with a voltage pulse of 10 V. Furthermore a novel clear concept - the capacitive coupled clear gate - is demonstrated. The radiation hardness is studied with respect to the system performance utilizing various irradiations with ionizing and non ionizing particles. The impact on the bulk as well as the interface damage is investigated. Up to now the readout is performed

  12. Hardware solutions for the 65k pixel X-ray camera module of 75 μm pixel size

    Science.gov (United States)

    Kasinski, K.; Maj, P.; Grybos, P.; Koziol, A.

    2016-02-01

    We present three hardware solutions designed for a detector module built with a 2 cm × 2 cm hybrid pixel detector built from a single 320 or 450 μ m thick silicon sensor designed and fabricated by Hamamatsu and two UFXC32k readout integrated circuits (128 × 256 pixels with 75μ m pitch, designed in CMOS 130 nm at AGH-UST). The chips work in a single photon counting mode and provide ultra-fast X-ray imaging. The presented hardware modules are designed according to requirements of various tests and applications: ṡDevice A: a fast and flexible system for tests with various radiation sources. ṡDevice B: a standalone, all-in-one imaging device providing three standard interfaces (USB 2.0, Ethernet, Camera Link) and up to 640 MB/s bandwidth. ṡDevice C: a prototype large-area imaging system. The paper shows the readout system structure for each case with highlighted circuit board designs with details on power distribution and cooling on both FR4 and LTCC (low temperature co-fired ceramic) based circuits.

  13. Research and Development of Monolithic Active Pixel Sensors for the Detection of the Elementary Particles

    International Nuclear Information System (INIS)

    Li, Y.

    2007-09-01

    In order to develop high spatial resolution and readout speed vertex detectors for the future International Linear Collider (ILC), fast CMOS Monolithic Active Pixel Sensors (MAPS) are studied on this work. Two prototypes of MAPS, MIMOSA 8 and MIMOSA 16, based on the same micro-electronic architecture were developed in CMOS processes with different thickness of epitaxial layer. The size of pixel matrix is 32 x 128: 8 columns of the pixel array are readout directly with analog outputs and the other 24 columns are connected to the column level auto-zero discriminators. The Correlated Double Sampling (CDS) structures are successfully implemented inside pixel and discriminator. The photo diode type pixels with different diode sizes are used in these prototypes. With a 55 Fe X-ray radioactive source, the important parameters, such as Temporal Noise, Fixed Pattern Noise (FPN), Signal-to-Noise Ratio (SNR), Charge-to-Voltage conversion Factor (CVF) and Charge Collection Efficiency (CCE), are studied as function of readout speed and diode size. For MIMOSA 8, the effect of fast neutrons irradiation is also. Two beam tests campaigns were made: at DESY with a 5 GeV electrons beam and at CERN with a 180 GeV pions beam. Detection Efficiency and Spatial Resolution are studied in function of the discriminator threshold. For these two parameters, the influences of diode size and SNR of the central pixel of a cluster are also discussed. In order to improve the spatial resolution of the digital outputs, a very compact (25 μm x 1 mm) and low consumption (300 μW) column level ADC is designed in AMS 0.35 μm OPTO process. Based on successive approximation architecture, the auto-offset cancellation structure is integrated. A new column level auto-zero discriminator using static latch is also designed. (author)

  14. Finite-element simulations of coupling capacitances in capacitively coupled pixel detectors

    CERN Document Server

    AUTHOR|(SzGeCERN)755510

    2017-01-01

    Capacitively coupled hybrid silicon pixel-detector assemblies are under study for the vertex detector at the proposed future CLIC linear electron-positron collider. The assemblies consist of active CCPDv3 sensors, with 25 μm pixel pitch implemented in a 180 nm High- Voltage CMOS process, which are glued to the CLICpix readout ASIC, with the same pixel pitch and processed in a commercial 65 nm CMOS technology. The signal created in the silicon bulk of the active sensors passes a two-stage amplifier, in each pixel, and gets transferred as a voltage pulse to metal pads facing the readout chip (ROC). The coupling of the signal to the metal pads on the ROC side proceeds through the capacitors formed between the two chips by a thin layer of epoxy glue. The coupling strength and the amount of unwanted cross coupling to neighbouring pixels depends critically on the uniformity of the glue layer, its thickness and on the alignment precision during the flip-chip assembly process. Finite-element calculations of the coup...

  15. Novel Silicon n-in-p Pixel Sensors for the future ATLAS Upgrades

    CERN Document Server

    La Rosa, A; Macchiolo, A; Nisius, R; Pernegger, H; Richter,R H; Weigell, P

    2013-01-01

    In view of the LHC upgrade phases towards HL-LHC the ATLAS experiment plans to upgrade the Inner Detector with an all silicon system. The n-in-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost eectiveness, that allow for enlarging the area instrumented with pixel detectors. We present the characterization and performance of novel n-in-p planar pixel sensors produced by CiS (Germany) connected by bump bonding to the ATLAS readout chip FE-I3. These results are obtained before and after irradiation up to a fluence of 1016 1-MeV $n_{eq}cm^{-2}$, and prove the operability of this kind of sensors in the harsh radiation environment foreseen for the pixel system at HL-LHC. We also present an overview of the new pixel production, which is on-going at CiS for sensors compatible with the new ATLAS readout chip FE-I4.

  16. Commissioning and first results from the CMS phase-1 upgrade pixel detector

    CERN Document Server

    Sonneveld, Jorine Mirjam

    2017-01-01

    The phase~1 upgrade of the CMS pixel detector has been designed to maintain the tracking performance at instantaneous luminosities of $2 \\times 10^{34} \\mathrm{~cm}^{-2} \\mathrm{~s}^{-1}$. Both barrel and endcap disk systems now feature one extra layer (4 barrel layers and 3 endcap disks), and a digital readout that provides a large enough bandwidth to read out its 124M pixel channels (87.7 percent more pixels compared to the previous system). The backend control and readout systems have been upgraded accordingly from VME-based to micro-TCA-based ones. The detector is now also fitted with a bi-phase CO$_2$ cooling system that reduces the material budget in the tracking region. The detector has been installed inside CMS at the start of 2017 and is now taking data. These proceedings discuss experiences in the commissioning and operation of the CMS phase~1 pixel detector. The first results from the CMS phase~1 pixel detector with this year's LHC proton-proton collision data are presented. ...

  17. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    Mullier, Geoffrey Andre; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL), a fourth layer of pixel detectors, installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been developed. A new readout chip has been developed within CMOS 130nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical performan...

  18. Characterisation of Vanilla—A novel active pixel sensor for radiation detection

    Science.gov (United States)

    Blue, A.; Bates, R.; Laing, A.; Maneuski, D.; O'Shea, V.; Clark, A.; Prydderch, M.; Turchetta, R.; Arvanitis, C.; Bohndiek, S.

    2007-10-01

    Novel features of a new monolithic active pixel sensor, Vanilla, with 520×520 pixels ( 25 μm square) has been characterised for the first time. Optimisation of the sensor operation was made through variation of frame rates, integration times and on-chip biases and voltages. Features such as flushed reset operation, ROI capturing and readout modes have been fully tested. Stability measurements were performed to test its suitablility for long-term applications. These results suggest the Vanilla sensor—along with bio-medical and space applications—is suitable for use in particle physics experiments.

  19. Modelling of the over-exposed pixel area of CCD cameras caused by laser dazzling

    OpenAIRE

    Benoist, K.W.; Schleijpen, R.M.A.

    2014-01-01

    A simple model has been developed and implemented in Matlab code, predicting the over-exposed pixel area of cameras caused by laser dazzling. Inputs of this model are the laser irradiance on the front optics of the camera, the Point Spread Function (PSF) of the used optics, the integration time of the camera, and camera sensor specifications like pixel size, quantum efficiency and full well capacity. Effects of the read-out circuit of the camera are not incorporated. The model was evaluated w...

  20. arXiv Study of the CMS Phase-1 Pixel Pilot Blade Reconstruction

    CERN Document Server

    Vami, Tamas Almos

    The Compact Muon Solenoid (CMS) detector is one of two general-purpose detectors that measure the products of high energy particle interactions in the Large Hadron Collider (LHC) at CERN. The silicon pixel detector is the innermost component of the CMS tracking system. The detector which was in operation between 2009 and 2016 has now been replaced with an upgraded one in the beginning of 2017. During the previous shutdown period of the LHC, a prototype readout system and a third disk was inserted into the old forward pixel detector with eight prototype blades constructed using the new digital read-out chips. Testing the performance of these pilot modules enabled us to gain operational experience with the upgraded detector. In this paper, the reconstruction and analysis of the data taken with the new modules are presented including information on the calibration of the reconstruction software. The hit finding efficiency and track-hit residual distributions are also shown.

  1. New pixelized Micromegas detector with low discharge rate for the COMPASS experiment

    CERN Document Server

    Neyret, D.; Anfreville, M.; Bedfer, Y.; Burtin, E.; Coquelet, C.; d'Hose, N.; Desforge, D.; Giganon, A.; Jourde, D.; Kunne, F.; Magnon, A.; Makke, N.; Marchand, C.; Paul, B.; Platchkov, S.; Thibaud, F.; Usseglio, M.; Vandenbroucke, M.

    2012-01-01

    New Micromegas (Micro-mesh gaseous detectors) are being developed in view of the future physics projects planned by the COMPASS collaboration at CERN. Several major upgrades compared to present detectors are being studied: detectors standing five times higher luminosity with hadron beams, detection of beam particles (flux up to a few hundred of kHz/mm^{2}, 10 times larger than for the present Micromegas detectors) with pixelized read-out in the central part, light and integrated electronics, and improved robustness. Two solutions of reduction of discharge impact have been studied, with Micromegas detectors using resistive layers and using an additional GEM foil. Performance of such detectors has also been measured. A large size prototypes with nominal active area and pixelized read-out has been produced and installed at COMPASS in 2010. In 2011 prototypes featuring an additional GEM foil, as well as an resistive prototype, are installed at COMPASS and preliminary results from those detectors presented very go...

  2. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    CERN Document Server

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  3. ATLAS Pixel Detector ROD card from IBL towards Layers 2 and 1

    Science.gov (United States)

    Balbi, G.; Falchieri, D.; Gabrielli, A.; Lama, L.; Giangiacomi, N.; Travaglini, R.

    2016-01-01

    The incoming and future upgrades of LHC will require better performance by the data acquisition system, especially in terms of throughput due to the higher luminosity that is expected. For this reason, during the first shutdown of the LHC collider in 2013/14, the ATLAS Pixel Detector has been equipped with a fourth layer— the Insertable B-Layer or IBL—located at a radius smaller than the present three layers. To read out the new layer of pixels, with a smaller pixel size with respect to the other outer layers, a front end ASIC (FE-I4) was designed as well as a new off-detector read-out chain. The latter, accordingly to the structure of the other layers of pixels, is composed mainly of two 9U-VME read-out off-detector cards called the Back-Of-Crate (BOC) and Read-Out Driver (ROD). The ROD is used for data and event formatting and for configuration and control of the overall read-out electronics. After some prototyping samples were completed, a pre-production batch of 5 ROD cards was delivered with the final layout. Another production of 15 ROD cards was done in Fall 2013, and commissioning was completed in 2014. Altogether 14 cards are necessary for the 14 staves of the IBL detector, one additional card is required by the Diamond Beam Monitor (DBM), and additional spare ROD cards were produced for a total initial batch of 20 boards. This paper describes some integration tests that were performed and our plan to install the new DAQ chain for the layer 2, which is the outermost, and layer 1, which is external to the B-layer. This latter is the only layer that will not be upgraded to a higher readout speed. Rather, it will be switched off in the near future as it has too many damaged sensors that were not possible to rework. To do that, slices of the IBL read-out chain have been instrumented, and ROD performance is verified on a test bench mimicking a small-sized final setup. Thus, this contribution reports also how the adoption of the IBL ROD for ATLAS Pixel

  4. Deployment of the CMS Tracker AMC as Backend for the CMS Pixel Detector

    CERN Document Server

    AUTHOR|(CDS)2079000

    2016-01-01

    The silicon pixel detector of the CMS experiment at CERN will be replaced with an upgraded version at the beginning of 2017 with the new detector featuring an additional barrel- and end-cap layer resulting in an increased number of fully digital read-out links running at 400Mb/s. New versions of the PSI46 Read-Out Chip and Token Bit Manager have been developed to operate at higher rates and reduce data loss. Front-End Controller and Front-End Driver boards, based on the {\\textmu}TCA compatible CMS Tracker AMC, a variant of the FC7 card, are being developed using different mezzanines to host the optical links for the digital read-out and control system. An overview of the system architecture is presented, with details on the implementation, and first results obtained from test systems.

  5. The Phase-II ATLAS ITk pixel upgrade

    Science.gov (United States)

    Terzo, S.

    2017-07-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase-II shutdown (foreseen to take place around 2025) by an all-silicon detector called the ``ITk'' (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and ring-shaped supports in the end-cap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation levels. The new pixel system could include up to 14 m2 of silicon, depending on the final layout, which is expected to be decided in 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel end-cap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as |eta| ATLAS trigger and DAQ system. A readout speed of up to 5 Gb/s per data link will be needed in the innermost layers going down to 640 Mb/s for the outermost. Because of the very high radiation level inside the detector, the first part of the transmission has to be implemented electrically, with signals converted for optical transmission at larger radii. Extensive tests are being carried out to prove the feasibility of implementing serial powering, which has been chosen as the baseline for the ITk pixel system due to the reduced material in the servicing cables foreseen for this option.

  6. CMOS Hybrid Pixel Detectors for Scientific, Industrial and Medical Applications

    Science.gov (United States)

    Broennimann, Christian

    2009-03-01

    Crystallography is the principal technique for determining macromolecular structures at atomic resolution and uses advantageously the high intensity of 3rd generation synchrotron X-ray sources . Macromolecular crystallography experiments benefit from excellent beamline equipment, recent software advances and modern X-ray detectors. However, the latter do not take full advantage of the brightness of modern synchrotron sources. CMOS Hybrid pixel array detectors, originally developed for high energy physics experiments, meet these requirements. X-rays are recorded in single photon counting mode and data thus are stored digitally at the earliest possible stage. This architecture leads to several advantages over current detectors: No detector noise is added to the signal. Readout time is reduced to a few milliseconds. The counting rates are matched to beam intensities at protein crystallography beamlines at 3rd generation synchrotrons. The detector is not sensitive to X-rays during readout; therefore no mechanical shutter is required. The detector has a very sharp point spread function (PSF) of one pixel, which allows better resolution of adjacent reflections. Low energy X-rays can be suppressed by the comparator At the Paul Scherrer Institute (PSI) in Switzerland the first and largest array based on this technology was constructed: The Pilatus 6M detector. The detector covers an area of 43.1 x 44.8 cm2 , has 6 million pixels and is read out noise free in 3.7 ms. Since June 2007 the detector is in routine operation at the beamline 6S of the Swiss Light Source (SLS). The company DETCRIS Ltd, has licensed the technology from PSI and is commercially offering the PILATUS detectors. Examples of the wide application range of the detectors will be shown.

  7. GEM scintillation readout with avalanche photodiodes

    CERN Document Server

    Conceição, A S; Fernandes, L M P; Monteiro, C M B; Coelho, L C C; Azevedo, C D R; Veloso, J F C A; Lopesac, J A M; dos Santosa, J M F

    2007-01-01

    The use of the scintillation produced in the charge avalanches in GEM holes as signal amplification and readout is investigated for xenon. A VUV-sensitive avalanche photodiode has been used as photosensor. Detector gains of about 4 × 104 are achieved in scintillation readout mode, for GEM voltages of 490 V and for a photosensor gain of 150. Those gains are more than one order of magnitude larger than what is obtained using charge readout. In addition, the energy resolutions achieved with the scintillation readout are lower than those achieved with charge readout. The GEM scintillation yield in xenon was measured as a function of GEM voltage, presenting values that are about a half of those achieved for the charge yield, and reach about 730 photons per primary electron at GEM voltages of 490 V.

  8. Results from a prototype MAPS sensor telescope and readout system with zero suppression for the heavy flavor tracker at STAR

    International Nuclear Information System (INIS)

    Greiner, L.; Matis, H.S.; Ritter, H.G.; Rose, A.; Stezelberger, T.; Sun, X.; Szelezniak, M.; Thomas, J.; Vu, C.; Wieman, H.

    2008-01-01

    We describe a three Mimostar-2 Monolithic Active Pixel Sensor (MAPS) sensor telescope prototype with an accompanying readout system incorporating on-the-fly data sparsification. The system has been characterized and we report on the measured performance of the sensor telescope and readout system in beam tests conducted both at the Advanced Light Source (ALS) at Lawrence Berkeley National Laboratory (LBNL) and in the STAR experiment at the Relativistic Heavy Ion Collider (RHIC). This effort is part of the development and prototyping work that will lead to a vertex detector for the STAR experiment

  9. Single Pixel Characterization of X-Ray TES Microcalorimeter Under AC Bias at MHz Frequencies

    Science.gov (United States)

    Gottardi, L.; Blandler, S. R.; Porter, F. S.; Sadleir, J. E.; Kilbourne, C. A.; Bailey, C. N.; Finkbeiner, F. M.; Chervenak, J. A.; Adams, J. S.; Eckart, M. E.; hide

    2012-01-01

    In this paper we present the progress made at SRON in the read-out of GSFC x-ray transition-edge sensor (TES) micro-calorimeters in the frequency domain. The experiments reported so far, whose aim was to demonstrate an energy resolution of 2eV at 6 keV with a TES acting as a modulator, were carried out at frequencies below 700 kHz using a standard flux locked loop (FLL) SQUID read-out scheme. The TES read-out suffered from the use of sub-optimal circuit components, large parasitic inductances, low quality factor resonators and poor magnetic field shielding. We have developed a novel experimental set-up, which allows us to test several read-out schemes in a single cryogenic run. In this set-up, the TES pixels are coupled via superconducting transformers to 18 high-Q lithographic LC filters with resonant frequencies ranging between 2 and 5 MHz. The signal is amplified by a two-stage SQUID current sensor and baseband feedback is used to overcome the limited SQUID dynamic range. We study the single pixel performance as a function of TES bias frequency, voltage and perpendicular magnetic field.

  10. Common Readout System in ALICE

    CERN Document Server

    Jubin, Mitra

    2016-01-01

    The ALICE experiment at the CERN Large Hadron Collider is going for a major physics upgrade in 2018. This upgrade is necessary for getting high statistics and high precision measurement for probing into rare physics channels needed to understand the dynamics of the condensed phase of QCD. The high interaction rate and the large event size in the upgraded detectors will result in an experimental data flow traffic of about 1 TB/s from the detectors to the on-line computing system. A dedicated Common Readout Unit (CRU) is proposed for data concentration, multiplexing, and trigger distribution. CRU, as common interface unit, handles timing, data and control signals between on-detector systems and online-offline computing system. An overview of the CRU architecture is presented in this manuscript.

  11. A support note for the use of pixel hybrid photon detectors in the RICH counters of LHCb

    CERN Document Server

    Gys, Thierry

    2001-01-01

    This document is a proposal for the use of a hybrid photon detector with integrated silicon pixel readout in the ring imaging Cherenkov detectors of the LHCb experiment. The photon detector is based on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 5. The anode consists of a silicon pixel array, bump-bonded to a binary readout chip with matching pixel electronics. The document starts with the general specification of the baseline option, followed by a summary of the main results achieved so far during the R&D phase. A future R&D programme and its related time table is also presented. The document concludes with the description of a photon detector production scheme and time schedule.

  12. System test and noise performance studies at the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Weingarten, J.

    2007-09-15

    The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the end-caps in both forward directions. The innermost barrel layer is mounted at a distance of about 5 cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator. (orig.)

  13. System test and noise performance studies at the ATLAS pixel detector

    International Nuclear Information System (INIS)

    Weingarten, J.

    2007-09-01

    The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the end-caps in both forward directions. The innermost barrel layer is mounted at a distance of about 5 cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator. (orig.)

  14. CMOS Active Pixel Sensors as energy-range detectors for proton Computed Tomography

    International Nuclear Information System (INIS)

    Esposito, M.; Waltham, C.; Allinson, N.M.; Anaxagoras, T.; Evans, P.M.; Poludniowski, G.; Green, S.; Parker, D.J.; Price, T.; Manolopoulos, S.; Nieto-Camero, J.

    2015-01-01

    Since the first proof of concept in the early 70s, a number of technologies has been proposed to perform proton CT (pCT), as a means of mapping tissue stopping power for accurate treatment planning in proton therapy. Previous prototypes of energy-range detectors for pCT have been mainly based on the use of scintillator-based calorimeters, to measure proton residual energy after passing through the patient. However, such an approach is limited by the need for only a single proton passing through the energy-range detector in a read-out cycle. A novel approach to this problem could be the use of pixelated detectors, where the independent read-out of each pixel allows to measure simultaneously the residual energy of a number of protons in the same read-out cycle, facilitating a faster and more efficient pCT scan. This paper investigates the suitability of CMOS Active Pixel Sensors (APSs) to track individual protons as they go through a number of CMOS layers, forming an energy-range telescope. Measurements performed at the iThemba Laboratories will be presented and analysed in terms of correlation, to confirm capability of proton tracking for CMOS APSs

  15. CMOS Active Pixel Sensors as energy-range detectors for proton Computed Tomography.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Evans, P M; Green, S; Manolopoulos, S; Nieto-Camero, J; Parker, D J; Poludniowski, G; Price, T; Waltham, C; Allinson, N M

    2015-06-03

    Since the first proof of concept in the early 70s, a number of technologies has been proposed to perform proton CT (pCT), as a means of mapping tissue stopping power for accurate treatment planning in proton therapy. Previous prototypes of energy-range detectors for pCT have been mainly based on the use of scintillator-based calorimeters, to measure proton residual energy after passing through the patient. However, such an approach is limited by the need for only a single proton passing through the energy-range detector in a read-out cycle. A novel approach to this problem could be the use of pixelated detectors, where the independent read-out of each pixel allows to measure simultaneously the residual energy of a number of protons in the same read-out cycle, facilitating a faster and more efficient pCT scan. This paper investigates the suitability of CMOS Active Pixel Sensors (APSs) to track individual protons as they go through a number of CMOS layers, forming an energy-range telescope. Measurements performed at the iThemba Laboratories will be presented and analysed in terms of correlation, to confirm capability of proton tracking for CMOS APSs.

  16. The Binary Offset Effect in CCDs: an Anomalous Readout Artifact Affecting Most Astronomical CCDs in Use

    Science.gov (United States)

    Boone, Kyle Robert; Aldering, Gregory; Copin, Yannick; Dixon, Samantha; Domagalski, Rachel; Gangler, Emmanuel; Pecontal, Emmanuel; Perlmutter, Saul; Nearby Supernova Factory Collaboration

    2018-01-01

    We discovered an anomalous behavior of CCD readout electronics that affects their use in many astronomical applications, which we call the “binary offset effect”. Due to feedback in the readout electronics, an offset is introduced in the values read out for each pixel that depends on the binary encoding of the previously read-out pixel values. One consequence of this effect is that a pathological local background offset can be introduced in images that only appears where science data are present on the CCD. The amplitude of this introduced offset does not scale monotonically with the amplitude of the objects in the image, and can be up to 4.5 ADU per pixel for certain instruments. Additionally, this background offset will be shifted by several pixels from the science data, potentially distorting the shape of objects in the image. We tested 22 instruments for signs of the binary offset effect and found evidence of it in 16 of them, including LRIS and DEIMOS on the Keck telescopes, WFC3-UVIS and STIS on HST, MegaCam on CFHT, SNIFS on the UH88 telescope, GMOS on the Gemini telescopes, HSC on Subaru, and FORS on VLT. A large amount of archival data is therefore affected by the binary offset effect, and conventional methods of reducing CCD images do not measure or remove the introduced offsets. As a demonstration of how to correct for the binary offset effect, we have developed a model that can accurately predict and remove the introduced offsets for the SNIFS instrument on the UH88 telescope. Accounting for the binary offset effect is essential for precision low-count astronomical observations with CCDs.

  17. 3D track reconstruction capability of a silicon hybrid active pixel detector

    Science.gov (United States)

    Bergmann, Benedikt; Pichotka, Martin; Pospisil, Stanislav; Vycpalek, Jiri; Burian, Petr; Broulim, Pavel; Jakubek, Jan

    2017-06-01

    Timepix3 detectors are the latest generation of hybrid active pixel detectors of the Medipix/Timepix family. Such detectors consist of an active sensor layer which is connected to the readout ASIC (application specific integrated circuit), segmenting the detector into a square matrix of 256 × 256 pixels (pixel pitch 55 μm). Particles interacting in the active sensor material create charge carriers, which drift towards the pixelated electrode, where they are collected. In each pixel, the time of the interaction (time resolution 1.56 ns) and the amount of created charge carriers are measured. Such a device was employed in an experiment in a 120 GeV/c pion beam. It is demonstrated, how the drift time information can be used for "4D" particle tracking, with the three spatial dimensions and the energy losses along the particle trajectory (dE/dx). Since the coordinates in the detector plane are given by the pixelation ( x, y), the x- and y-resolution is determined by the pixel pitch (55 μm). A z-resolution of 50.4 μm could be achieved (for a 500 μm thick silicon sensor at 130 V bias), whereby the drift time model independent z-resolution was found to be 28.5 μm.

  18. 3D track reconstruction capability of a silicon hybrid active pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Bergmann, Benedikt; Pichotka, Martin; Pospisil, Stanislav; Vycpalek, Jiri [Czech Technical University in Prague, Institute of Experimental and Applied Physics, Praha (Czech Republic); Burian, Petr; Broulim, Pavel [Czech Technical University in Prague, Institute of Experimental and Applied Physics, Praha (Czech Republic); University of West Bohemia, Faculty of Electrical Engineering, Pilsen (Czech Republic); Jakubek, Jan [Advacam s.r.o., Praha (Czech Republic)

    2017-06-15

    Timepix3 detectors are the latest generation of hybrid active pixel detectors of the Medipix/Timepix family. Such detectors consist of an active sensor layer which is connected to the readout ASIC (application specific integrated circuit), segmenting the detector into a square matrix of 256 x 256 pixels (pixel pitch 55 μm). Particles interacting in the active sensor material create charge carriers, which drift towards the pixelated electrode, where they are collected. In each pixel, the time of the interaction (time resolution 1.56 ns) and the amount of created charge carriers are measured. Such a device was employed in an experiment in a 120 GeV/c pion beam. It is demonstrated, how the drift time information can be used for ''4D'' particle tracking, with the three spatial dimensions and the energy losses along the particle trajectory (dE/dx). Since the coordinates in the detector plane are given by the pixelation (x,y), the x- and y-resolution is determined by the pixel pitch (55 μm). A z-resolution of 50.4 μm could be achieved (for a 500 μm thick silicon sensor at 130 V bias), whereby the drift time model independent z-resolution was found to be 28.5 μm. (orig.)

  19. The Pixels find their way to the heart of ATLAS

    CERN Multimedia

    Kevin Einsweiler

    Since the last e-news article on the Pixel Detector in December 2006, there has been much progress. At that time, we were just about to receive the Beryllium beampipe, and to integrate the innermost layer of the Pixel Detector around it. This innermost layer is referred to as the B-layer because of the powerful role it plays in finding the secondary vertices that are the key signature for the presence of b-quarks, and with somewhat greater difficulty, c-quarks and tau leptons. The integration of the central 7m long beampipe into the Pixel Detector was completed in December, and the B-layer was successfully integrated around it. In January this year, we had largely completed the central 1.5m long detector, including the three barrel layers and the three disk layers on each end of the barrel. Although this region contains all of the 80 million readout channels, it cannot be integrated into the Inner Detector without additional services and infrastructure. Therefore, the next step was to add the Service Panels...

  20. Silicon Sensors for the Upgrades of the CMS Pixel Detector

    CERN Document Server

    Centis Vignali, Matteo; Schleper, Peter

    2015-01-01

    The Compact Muon Solenoid (CMS) is a general purpose detector at the Large Hadron Collider (LHC). The LHC luminosity is constantly increased through upgrades of the accel- erator and its injection chain. Two major upgrades will take place in the next years. The rst upgrade involves the LHC injector chain and allows the collider to achieve a luminosity of about 2 10 34 cm-2 s-1 A further upgrade of the LHC foreseen for 2025 will boost its luminosity to 5 10 34 cm-2 s1. As a consequence of the increased luminosity, the detectors need to be upgraded. In particular, the CMS pixel detector will undergo two upgrades in the next years. The rst upgrade (phase I) consists in the substitution of the current pixel detector in winter 2016/2017. The upgraded pixel detector will implement new readout elec- tronics that allow ecient data taking up to a luminosity of 2 10 34 cm-2s-1,twice as much as the LHC design luminosity. The modules that will constitute the upgraded detector are being produced at dierent institutes. Ham...

  1. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    CERN Document Server

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  2. High-speed imaging at high x-ray energy: CdTe sensors coupled to charge-integrating pixel array detectors

    Energy Technology Data Exchange (ETDEWEB)

    Becker, Julian; Tate, Mark W.; Shanks, Katherine S.; Philipp, Hugh T.; Weiss, Joel T.; Purohit, Prafull [Laboratory of Atomic and Solid State Physics, Cornell University, Ithaca, NY 14853 (United States); Chamberlain, Darol [Cornell High Energy Synchrotron Source (CHESS), Cornell University, Ithaca, NY 14853 (United States); Gruner, Sol M., E-mail: smg26@cornell.edu [Laboratory of Atomic and Solid State Physics, Cornell University, Ithaca, NY 14853 (United States); Cornell High Energy Synchrotron Source (CHESS), Cornell University, Ithaca, NY 14853 (United States)

    2016-07-27

    Pixel Array Detectors (PADs) consist of an x-ray sensor layer bonded pixel-by-pixel to an underlying readout chip. This approach allows both the sensor and the custom pixel electronics to be tailored independently to best match the x-ray imaging requirements. Here we describe the hybridization of CdTe sensors to two different charge-integrating readout chips, the Keck PAD and the Mixed-Mode PAD (MM-PAD), both developed previously in our laboratory. The charge-integrating architecture of each of these PADs extends the instantaneous counting rate by many orders of magnitude beyond that obtainable with photon counting architectures. The Keck PAD chip consists of rapid, 8-frame, in-pixel storage elements with framing periods <150 ns. The second detector, the MM-PAD, has an extended dynamic range by utilizing an in-pixel overflow counter coupled with charge removal circuitry activated at each overflow. This allows the recording of signals from the single-photon level to tens of millions of x-rays/pixel/frame while framing at 1 kHz. Both detector chips consist of a 128×128 pixel array with (150 µm){sup 2} pixels.

  3. High-speed imaging at high x-ray energy: CdTe sensors coupled to charge-integrating pixel array detectors

    International Nuclear Information System (INIS)

    Becker, Julian; Tate, Mark W.; Shanks, Katherine S.; Philipp, Hugh T.; Weiss, Joel T.; Purohit, Prafull; Chamberlain, Darol; Gruner, Sol M.

    2016-01-01

    Pixel Array Detectors (PADs) consist of an x-ray sensor layer bonded pixel-by-pixel to an underlying readout chip. This approach allows both the sensor and the custom pixel electronics to be tailored independently to best match the x-ray imaging requirements. Here we describe the hybridization of CdTe sensors to two different charge-integrating readout chips, the Keck PAD and the Mixed-Mode PAD (MM-PAD), both developed previously in our laboratory. The charge-integrating architecture of each of these PADs extends the instantaneous counting rate by many orders of magnitude beyond that obtainable with photon counting architectures. The Keck PAD chip consists of rapid, 8-frame, in-pixel storage elements with framing periods <150 ns. The second detector, the MM-PAD, has an extended dynamic range by utilizing an in-pixel overflow counter coupled with charge removal circuitry activated at each overflow. This allows the recording of signals from the single-photon level to tens of millions of x-rays/pixel/frame while framing at 1 kHz. Both detector chips consist of a 128×128 pixel array with (150 µm) 2 pixels.

  4. High-speed X-ray imaging pixel array detector for synchrotron bunch isolation

    International Nuclear Information System (INIS)

    Philipp, Hugh T.; Tate, Mark W.; Purohit, Prafull; Shanks, Katherine S.; Weiss, Joel T.; Gruner, Sol M.

    2016-01-01

    A high-speed pixel array detector for time-resolved X-ray imaging at synchrotrons has been developed. The ability to isolate single synchrotron bunches makes it ideal for time-resolved dynamical studies. A wide-dynamic-range imaging X-ray detector designed for recording successive frames at rates up to 10 MHz is described. X-ray imaging with frame rates of up to 6.5 MHz have been experimentally verified. The pixel design allows for up to 8–12 frames to be stored internally at high speed before readout, which occurs at a 1 kHz frame rate. An additional mode of operation allows the integration capacitors to be re-addressed repeatedly before readout which can enhance the signal-to-noise ratio of cyclical processes. This detector, along with modern storage ring sources which provide short (10–100 ps) and intense X-ray pulses at megahertz rates, opens new avenues for the study of rapid structural changes in materials. The detector consists of hybridized modules, each of which is comprised of a 500 µm-thick silicon X-ray sensor solder bump-bonded, pixel by pixel, to an application-specific integrated circuit. The format of each module is 128 × 128 pixels with a pixel pitch of 150 µm. In the prototype detector described here, the three-side buttable modules are tiled in a 3 × 2 array with a full format of 256 × 384 pixels. The characteristics, operation, testing and application of the detector are detailed

  5. Design and characterization of novel monolithic pixel sensors for the ALICE ITS upgrade

    Science.gov (United States)

    Cavicchioli, C.; Chalmet, P. L.; Giubilato, P.; Hillemanns, H.; Junique, A.; Kugathasan, T.; Mager, M.; Marin Tobon, C. A.; Martinengo, P.; Mattiazzo, S.; Mugnier, H.; Musa, L.; Pantano, D.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Van Hoorne, J. W.; Yang, P.

    2014-11-01

    Within the R&D activities for the upgrade of the ALICE Inner Tracking System (ITS), Monolithic Active Pixel Sensors (MAPS) are being developed and studied, due to their lower material budget ( 0.3 %X0 in total for each inner layer) and higher granularity ( 20 μm × 20 μm pixels) with respect to the present pixel detector. This paper presents the design and characterization results of the Explorer0 chip, manufactured in the TowerJazz 180 nm CMOS Imaging Sensor process, based on a wafer with high-resistivity (ρ > 1 kΩ cm) and 18 μm thick epitaxial layer. The chip is organized in two sub-matrices with different pixel pitches (20 μm and 30 μm), each of them containing several pixel designs. The collection electrode size and shape, as well as the distance between the electrode and the surrounding electronics, are varied; the chip also offers the possibility to decouple the charge integration time from the readout time, and to change the sensor bias. The charge collection properties of the different pixel variants implemented in Explorer0 have been studied using a 55Fe X-ray source and 1-5 GeV/c electrons and positrons. The sensor capacitance has been estimated, and the effect of the sensor bias has also been examined in detail. A second version of the Explorer0 chip (called Explorer1) has been submitted for production in March 2013, together with a novel circuit with in-pixel discrimination and a sparsified readout. Results from these submissions are also presented.

  6. Design and characterization of novel monolithic pixel sensors for the ALICE ITS upgrade

    International Nuclear Information System (INIS)

    Cavicchioli, C.; Chalmet, P.L.; Giubilato, P.; Hillemanns, H.; Junique, A.; Kugathasan, T.; Mager, M.; Marin Tobon, C.A.; Martinengo, P.; Mattiazzo, S.; Mugnier, H.; Musa, L.; Pantano, D.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Van Hoorne, J.W.; Yang, P.

    2014-01-01

    Within the R and D activities for the upgrade of the ALICE Inner Tracking System (ITS), Monolithic Active Pixel Sensors (MAPS) are being developed and studied, due to their lower material budget (∼0.3%X 0 in total for each inner layer) and higher granularity (∼20μm×20μm pixels) with respect to the present pixel detector. This paper presents the design and characterization results of the Explorer0 chip, manufactured in the TowerJazz 180 nm CMOS Imaging Sensor process, based on a wafer with high-resistivity (ρ>1kΩcm) and 18 μm thick epitaxial layer. The chip is organized in two sub-matrices with different pixel pitches (20 μm and 30 μm), each of them containing several pixel designs. The collection electrode size and shape, as well as the distance between the electrode and the surrounding electronics, are varied; the chip also offers the possibility to decouple the charge integration time from the readout time, and to change the sensor bias. The charge collection properties of the different pixel variants implemented in Explorer0 have been studied using a 55 Fe X-ray source and 1–5 GeV/c electrons and positrons. The sensor capacitance has been estimated, and the effect of the sensor bias has also been examined in detail. A second version of the Explorer0 chip (called Explorer1) has been submitted for production in March 2013, together with a novel circuit with in-pixel discrimination and a sparsified readout. Results from these submissions are also presented

  7. High-resolution photon spectroscopy with a microwave-multiplexed 4-pixel transition edge sensor array

    Science.gov (United States)

    Guss, Paul; Rabin, Michael; Croce, Mark; Hoteling, Nathan; Schwellenbach, David; Kruschwitz, Craig; Mocko, Veronika; Mukhopadhyay, Sanjoy

    2017-09-01

    We demonstrate very high-resolution photon spectroscopy with a microwave-multiplexed 4-pixel transition edge sensor (TES) array. The readout circuit consists of superconducting microwave resonators coupled to radio frequency superconducting-quantum-interference devices (RF-SQUIDs) and transduces changes in input current to changes in phase of a microwave signal. We used a flux-ramp modulation to linearize the response and avoid low-frequency noise. The result is a very high-resolution photon spectroscopy with a microwave-multiplexed 4-pixel transition edge sensor array. We performed and validated a small-scale demonstration and test of all the components of our concept system, which encompassed microcalorimetry, microwave multiplexing, RF-SQUIDs, and software-defined radio (SDR). We shall display data we acquired in the first simultaneous combination of all key innovations in a 4-pixel demonstration, including microcalorimetry, microwave multiplexing, RF-SQUIDs, and SDR. We present the energy spectrum of a gadolinium-153 (153Gd) source we measured using our 4-pixel TES array and the RF-SQUID multiplexer. For each pixel, one can observe the two 97.4 and 103.2 keV photopeaks. We measured the 153Gd photon source with an achieved energy resolution of 70 eV, full width half maximum (FWHM) at 100 keV, and an equivalent readout system noise of 90 pA/pHz at the TES. This demonstration establishes a path for the readout of cryogenic x-ray and gamma ray sensor arrays with more elements and spectral resolving powers. We believe this project has improved capabilities and substantively advanced the science useful for missions such as nuclear forensics, emergency response, and treaty verification through the explored TES developments.

  8. Development of the digital read-out system for the CERN Alice pixel detector

    CERN Document Server

    Grassi, Tullio

    In order to gain new experimental insight at the TeV energy scale, CERN (Geneva) will build the Large Hadron Collider (LHC), a new collider machine operating at a maximum center-of-mass energy of 14 TeV (in the p+/p+ interactions). The accelerator can operate in a heavy ion collision mode achieving a center-of-mass energy of ~5.5 TeV. The experimental environment at LHC is characterized by a high crossing rate of the particle bunches (one every 25 ns for p+/p+) and high levels of radiation. Therefore stringent requirements are imposed on the performance of detectors at LHC. Such a particle physics environment calls for dedicated hardware/software solutions with specific constraints, such as radiation tolerance, limited amount of material and limited power dissipation. One of the particle physics experiments carried out in LHC is ALICE (A Large Ion Collider Experiment). The ALICE detector will face a very high density of tracks of particles (a multiplicity of 8000 charged particles per unit of rapidity, that i...

  9. Modular pixelated detector system with the spectroscopic capability and fast parallel read-out

    Czech Academy of Sciences Publication Activity Database

    Vavřík, Daniel; Holík, M.; Jakůbek, J.; Jakůbek, M.; Kraus, V.; Krejčí, F.; Soukup, P.; Tureček, D.; Vacík, Jiří; Žemlička, J.

    2014-01-01

    Roč. 9, June (2014), C06006 ISSN 1748-0221. [International workshop on radiation imaging detectors /15./. Paris, 23.06.2013-27.06.2013] R&D Projects: GA MŠk(CZ) LO1219; GA TA ČR(CZ) TA01010237 Institutional support: RVO:68378297 ; RVO:61389005 Keywords : particle tracking detectors * X-ray detectors * modular electronics * neutron detectors * solid- state detectors Subject RIV: JN - Civil Engineering; BM - Solid Matter Physics ; Magnetism (UJF-V) Impact factor: 1.399, year: 2014 http://iopscience.iop.org/1748-0221/9/06/C06006

  10. A two-dimensional position sensitive gas chamber with scanned charge transfer readout

    Energy Technology Data Exchange (ETDEWEB)

    Gomez, F. E-mail: faustgr@usc.es; Iglesias, A.; Lobato, R.; Mosquera, J.; Pardo, J.; Pena, J.; Pazos, A.; Pombar, M.; Rodriguez, A

    2003-10-21

    We have constructed and tested a two-dimensional position sensitive parallel-plate gas ionization chamber with scanned charge transfer readout. The scan readout method described here is based on the development of a new position-dependent charge transfer technique. It has been implemented by using gate strips perpendicularly oriented to the collector strips. This solution reduces considerably the number of electronic readout channels needed to cover large detector areas. The use of a 25 {mu}m thick kapton etched circuit allows high charge transfer efficiency with a low gating voltage, consequently needing a very simple commutating circuit. The present prototype covers 8x8 cm{sup 2} with a pixel size of 1.27x1.27 mm{sup 2}. Depending on the intended use and beam characteristics a smaller effective pixel is feasible and larger active areas are possible. This detector can be used for X-ray or other continuous beam intensity profile monitoring.

  11. The readout system for the ArTeMis camera

    Science.gov (United States)

    Doumayrou, E.; Lortholary, M.; Dumaye, L.; Hamon, G.

    2014-07-01

    During ArTeMiS observations at the APEX telescope (Chajnantor, Chile), 5760 bolometric pixels from 20 arrays at 300mK, corresponding to 3 submillimeter focal planes at 450μm, 350μm and 200μm, have to be read out simultaneously at 40Hz. The read out system, made of electronics and software, is the full chain from the cryostat to the telescope. The readout electronics consists of cryogenic buffers at 4K (NABU), based on CMOS technology, and of warm electronic acquisition systems called BOLERO. The bolometric signal given by each pixel has to be amplified, sampled, converted, time stamped and formatted in data packets by the BOLERO electronics. The time stamping is obtained by the decoding of an IRIG-B signal given by APEX and is key to ensure the synchronization of the data with the telescope. Specifically developed for ArTeMiS, BOLERO is an assembly of analogue and digital FPGA boards connected directly on the top of the cryostat. Two detectors arrays (18*16 pixels), one NABU and one BOLERO interconnected by ribbon cables constitute the unit of the electronic architecture of ArTeMiS. In total, the 20 detectors for the tree focal planes are read by 10 BOLEROs. The software is working on a Linux operating system, it runs on 2 back-end computers (called BEAR) which are small and robust PCs with solid state disks. They gather the 10 BOLEROs data fluxes, and reconstruct the focal planes images. When the telescope scans the sky, the acquisitions are triggered thanks to a specific network protocol. This interface with APEX enables to synchronize the acquisition with the observations on sky: the time stamped data packets are sent during the scans to the APEX software that builds the observation FITS files. A graphical user interface enables the setting of the camera and the real time display of the focal plane images, which is essential in laboratory and commissioning phases. The software is a set of C++, Labview and Python, the qualities of which are respectively used

  12. Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Savic, N., E-mail: natascha.savic@mpp.mpg.de; Bergbreiter, L.; Breuer, J.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Terzo, S.

    2017-02-11

    The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270 μm. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150 μm and a novel design with the optimized biasing structure and small pixel cells (50×50 and 25×100 μm{sup 2}). These dimensions are foreseen for the new ATLAS read-out chip in 65 nm CMOS technology and the fine segmentation will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. To predict the performance of 50×50 μm{sup 2} pixels at high η, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle with respect to the short pixel direction. Results on cluster shapes, charge collection- and hit efficiency will be shown.

  13. Development of a super B-factory monolithic active pixel detector-the Continuous Acquisition Pixel (CAP) prototypes

    International Nuclear Information System (INIS)

    Varner, G.; Barbero, M.; Bozek, A.; Browder, T.; Fang, F.; Hazumi, M.; Igarashi, A.; Iwaida, S.; Kennedy, J.; Kent, N.; Olsen, S.; Palka, H.; Rosen, M.; Ruckman, L.; Stanic, S.; Trabelsi, K.; Tsuboyama, T.; Uchida, K.

    2005-01-01

    Over the last few years great progress has been made in the technological development of Monolithic Active Pixel Sensors (MAPS) such that upgrades to existing vertex detectors using this technology are now actively being considered. Future vertex detection at an upgraded KEK-B factory, already the highest luminosity collider in the world, will require a detector technology capable of withstanding the increased track densities and larger radiation exposures. Near the beam pipe the current silicon strip detectors have projected occupancies in excess of 100%. Deep sub-micron MAPS look very promising to address this problem. In the context of an upgrade to the Belle vertex detector, the major obstacles to realizing such a device have been concerns about radiation hardness and readout speed. Two prototypes implemented in the TSMC 0.35 μm process have been developed to address these issues. Denoted the Continuous Acquisition Pixel, or CAP, the two variants of this architecture are distinguished in that CAP2 includes an 8-deep sampling pipeline within each 22.5 μm 2 pixel. Preliminary test results and remaining R and D issues are presented

  14. Design and development of the IBL-BOC firmware for the ATLAS Pixel IBL optical datalink system

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00356268

    The Insertable $b$-Layer (IBL) is the first upgrade of the ATLAS Pixel detector at the LHC. It will be installed in the Pixel detector in 2013. The IBL will use a new sensor and readout technology, therefore the readout components of the current Pixel detector are redesigned for the readout of the IBL. In this diploma thesis the design and development of the firmware for the new IBL Back-of-Crate card (IBL-BOC) are described. The IBL-BOC is located on the off-detector side of the readout and performs the optical-electrical conversion and vice versa for the optical connection to and from the detector. To process the data transmitted to and received from the detector, the IBL-BOC uses multiple Field Programmable Gate Arrays (FPGA). The transmitted signal is a 40~Mb/s BiPhase Mark (BPM) encoded data stream, providing the timing, trigger and control to the detector. The received signal is a 160~Mb/s 8b10b encoded data stream, containing data from the detector. The IBL-BOC encodes and decodes these data streams. T...

  15. A Gigabit per second read-out system for Medipix Quads

    International Nuclear Information System (INIS)

    Visser, Jan; Heijden, B. van der; Weijers, S.J.A.; Vries, R. de; Visschers, J.L.

    2011-01-01

    A system to read-out images from four photon-counting Medipix chips at one Gigabit per second has been constructed in a bilateral collaboration between Nikhef and PANalytical. The system consists of two printed circuit boards. One board supports the four Medipix readout ASICs, flip-chipped to a single pixellized semiconducting sensor on top. This board is mounted perpendicular on the Relaxd read-out board. This Relaxd board supplies the necessary voltages to the Medipix readout ASICs, controls all signals to and from these chips via a low-power Field Programmable Gate Array (FPGA, Lattice SC series) and communicates with a PC through a standard one Gigabit per second Ethernet connection (GbE). The T-shaped mechanical topology allows multiple modules to be mounted adjacent to each other in all directions (2D tiling) and to minimise the insensitive area between separate Relaxd modules. An overview of the system layout and the functionality is presented as well as the first test results.

  16. A Gigabit per second read-out system for Medipix Quads

    Energy Technology Data Exchange (ETDEWEB)

    Visser, Jan, E-mail: jan.visser@nikhef.nl [Netherlands Institute for Subatomic Physics, Nikhef, Science Park 103, 1098XG Amsterdam (Netherlands); Heijden, B. van der [Netherlands Institute for Subatomic Physics, Nikhef, Science Park 103, 1098XG Amsterdam (Netherlands); Weijers, S.J.A.; Vries, R. de [PANalytical, Lelyweg 1, 7602EA Almelo (Netherlands); Visschers, J.L. [Netherlands Institute for Subatomic Physics, Nikhef, Science Park 103, 1098XG Amsterdam (Netherlands)

    2011-05-15

    A system to read-out images from four photon-counting Medipix chips at one Gigabit per second has been constructed in a bilateral collaboration between Nikhef and PANalytical. The system consists of two printed circuit boards. One board supports the four Medipix readout ASICs, flip-chipped to a single pixellized semiconducting sensor on top. This board is mounted perpendicular on the Relaxd read-out board. This Relaxd board supplies the necessary voltages to the Medipix readout ASICs, controls all signals to and from these chips via a low-power Field Programmable Gate Array (FPGA, Lattice SC series) and communicates with a PC through a standard one Gigabit per second Ethernet connection (GbE). The T-shaped mechanical topology allows multiple modules to be mounted adjacent to each other in all directions (2D tiling) and to minimise the insensitive area between separate Relaxd modules. An overview of the system layout and the functionality is presented as well as the first test results.

  17. A Full Parallel Event Driven Readout Technique for Area Array SPAD FLIM Image Sensors

    Directory of Open Access Journals (Sweden)

    Kaiming Nie

    2016-01-01

    Full Text Available This paper presents a full parallel event driven readout method which is implemented in an area array single-photon avalanche diode (SPAD image sensor for high-speed fluorescence lifetime imaging microscopy (FLIM. The sensor only records and reads out effective time and position information by adopting full parallel event driven readout method, aiming at reducing the amount of data. The image sensor includes four 8 × 8 pixel arrays. In each array, four time-to-digital converters (TDCs are used to quantize the time of photons’ arrival, and two address record modules are used to record the column and row information. In this work, Monte Carlo simulations were performed in Matlab in terms of the pile-up effect induced by the readout method. The sensor’s resolution is 16 × 16. The time resolution of TDCs is 97.6 ps and the quantization range is 100 ns. The readout frame rate is 10 Mfps, and the maximum imaging frame rate is 100 fps. The chip’s output bandwidth is 720 MHz with an average power of 15 mW. The lifetime resolvability range is 5–20 ns, and the average error of estimated fluorescence lifetimes is below 1% by employing CMM to estimate lifetimes.

  18. A position- and time-sensitive photon-counting detector with delay- line read-out

    Science.gov (United States)

    Jagutzki, Ottmar; Dangendorf, Volker; Lauck, Ronald; Czasch, Achim; Milnes, James

    2007-05-01

    We have developed image intensifier tubes with delay-anode read-out for time- and position-sensitive photon counting. The timing precision is better than 1 ns with 1000x1000 pixels position resolution and up to one megacounts/s processing rate. Large format detectors of 40 and 75 mm active diameter with internal helical-wire delay-line anodes have been produced and specified. A different type of 40 and 25 mm tubes with semi-conducting screen for image charge read-out allow for an economic and robust tube design and for placing the read-out anodes outside the sealed housing. Two types of external delay-line anodes, i.e. pick-up electrodes for the image charge, have been tested. We present tests of the detector and anode performance. Due to the low background this technique is well suited for applications with very low light intensity and especially if a precise time tagging for each photon is required. As an example we present the application of scintillator read-out in time-of-flight (TOF) neutron radiography. Further applications so far are Fluorescence Life-time Microscopy (FLIM) and Astronomy.

  19. A Full Parallel Event Driven Readout Technique for Area Array SPAD FLIM Image Sensors.

    Science.gov (United States)

    Nie, Kaiming; Wang, Xinlei; Qiao, Jun; Xu, Jiangtao

    2016-01-27

    This paper presents a full parallel event driven readout method which is implemented in an area array single-photon avalanche diode (SPAD) image sensor for high-speed fluorescence lifetime imaging microscopy (FLIM). The sensor only records and reads out effective time and position information by adopting full parallel event driven readout method, aiming at reducing the amount of data. The image sensor includes four 8 × 8 pixel arrays. In each array, four time-to-digital converters (TDCs) are used to quantize the time of photons' arrival, and two address record modules are used to record the column and row information. In this work, Monte Carlo simulations were performed in Matlab in terms of the pile-up effect induced by the readout method. The sensor's resolution is 16 × 16. The time resolution of TDCs is 97.6 ps and the quantization range is 100 ns. The readout frame rate is 10 Mfps, and the maximum imaging frame rate is 100 fps. The chip's output bandwidth is 720 MHz with an average power of 15 mW. The lifetime resolvability range is 5-20 ns, and the average error of estimated fluorescence lifetimes is below 1% by employing CMM to estimate lifetimes.

  20. Readout Driver Firmware Development for the ATLAS Insertable B-Layer

    CERN Document Server

    Chen, Shaw-Pin; Hsu, Shih-Chieh

    During the Large Hadron Collider shutdown from 2013 to 2014 a fourth silicon layer, called the Insertable-B Layer (IBL), was inserted inside the existing ATLAS Pixel Detector. The IBL uses the state-of-the-art FE-I4 front-end readout ASICs for enhanced detector readout efficiency during upcoming LHC runs at higher energy and luminosity. The control and data acquisition (DAQ) of the IBL requires the commissioning of new off-detector readout electronics, mainly consisting of Field-Programmable Gate Array (FPGA)-based Readout Driver (ROD) and Back-of-Crate (BOC) Cards. This thesis focuses on the architecture, implementation, simulation, and hardware test results of the new IBL ROD datapath firmware. Characterization of the IBL detector front-end and an overview of ATLAS Trigger DAQ (TDAQ) system are provided in the first chapters of the thesis. IBL ROD datapath firmware was designed and simulated in a ModelSim testbench with a realistic HDL FE-I4 model as source of data. The hardware tests using both real and em...

  1. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider -- Plot Approval (Pixel, IBL) : This is a submission of plot approval request for Pixel+IBL, facing on a talk at ICHEP 2014 conference

    CERN Document Server

    Mandelli, B; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and will be installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project as well as the ...

  2. The LAMBDA photon-counting pixel detector and high-Z sensor development

    Science.gov (United States)

    Pennicard, D.; Smoljanin, S.; Struth, B.; Hirsemann, H.; Fauler, A.; Fiederle, M.; Tolbanov, O.; Zarubin, A.; Tyazhev, A.; Shelkov, G.; Graafsma, H.

    2014-12-01

    Many X-ray experiments at third-generation synchrotrons benefit from using single-photon-counting detectors, due to their high signal-to-noise ratio and potential for high-speed measurements. LAMBDA (Large Area Medipix3-Based Detector Array) is a pixel detector system based on the Medipix3 readout chip. It combines the features of Medipix3, such as a small pixel size of 55 μm and flexible functionality, with a large tileable module design consisting of 12 chips (1536 × 512 pixels) and a high-speed readout system capable of running at 2000 frames per second. To enable high-speed experiments with hard X-rays, the LAMBDA system has been combined with different high-Z sensor materials. Room-temperature systems using GaAs and CdTe systems have been produced and tested with X-ray tubes and at synchrotron beamlines. Both detector materials show nonuniformities in their raw image response, but the pixel yield is high and the uniformity can be improved by flat-field correction, particularly in the case of GaAs. High-frame-rate experiments show that useful information can be gained on millisecond timescales in synchrotron experiments with these sensors.

  3. Silicon sensors for the upgrades of the CMS pixel detector

    International Nuclear Information System (INIS)

    Centis Vignali, Matteo

    2015-12-01

    The Compact Muon Solenoid (CMS) is a general purpose detector at the Large Hadron Collider (LHC). The LHC luminosity is constantly increased through upgrades of the accelerator and its injection chain. Two major upgrades will take place in the next years. The first upgrade involves the LHC injector chain and allows the collider to achieve a luminosity of about 2.10 34 cm -2 s -1 . A further upgrade of the LHC foreseen for 2025 will boost its luminosity to 5.10 34 cm -2 s -1 . As a consequence of the increased luminosity, the detectors need to be upgraded. In particular, the CMS pixel detector will undergo two upgrades in the next years. The first upgrade (phase I) consists in the substitution of the current pixel detector in winter 2016/2017. The upgraded pixel detector will implement new readout electronics that allow efficient data taking up to a luminosity of 2.10 34 cm -2 s -1 , twice as much as the LHC design luminosity. The modules that will constitute the upgraded detector are being produced at different institutes. Hamburg (University and DESY) is responsible for the production of 350 pixel modules. The second upgrade (phase II) of the pixel detector is foreseen for 2025. The innermost pixel layer of the upgraded detector will accumulate a radiation damage corresponding to an equivalent fluence of Φ eq =2.10 16 cm -2 and a dose of ∼10 MGy after an integrated luminosity of 3000 fb -1 . Several groups are investigating sensor designs and configurations able to withstand such high doses and fluences. This work is divided into two parts related to important aspects of the upgrades of the CMS pixel detector. For the phase I upgrade, a setup has been developed to provide an absolute energy calibration of the pixel modules that will constitute the detector. The calibration is obtained using monochromatic X-rays. The same setup is used to test the buffering capabilities of the modules' readout chip. The maximum rate experienced by the modules produced in

  4. Very forward calorimeters readout and machine interface

    Indian Academy of Sciences (India)

    Abstract. The paper describes the requirements for the readout electronics and DAQ for the instrumentation of the forward region of the future detector at the international linear collider. The preliminary design is discussed.

  5. Very forward calorimeters readout and machine interface

    Indian Academy of Sciences (India)

    . Abstract. The paper describes the requirements for the readout electronics and DAQ for the instrumentation of the forward region of the future detector at the international linear collider. The preliminary design is discussed. Keywords. LumiCal ...

  6. Common Bias Readout for TES Array on Scanning Transmission Electron Microscope

    Science.gov (United States)

    Yamamoto, R.; Sakai, K.; Maehisa, K.; Nagayoshi, K.; Hayashi, T.; Muramatsu, H.; Nakashima, Y.; Mitsuda, K.; Yamasaki, N. Y.; Takei, Y.; Hidaka, M.; Nagasawa, S.; Maehata, K.; Hara, T.

    2016-07-01

    A transition edge sensor (TES) microcalorimeter array as an X-ray sensor for a scanning transmission electron microscope system is being developed. The technical challenge of this system is a high count rate of ˜ 5000 counts/second/array. We adopted a 64 pixel array with a parallel readout. Common SQUID bias, and common TES bias are planned to reduce the number of wires and the resources of a room temperature circuit. The reduction rate of wires is 44 % when a 64 pixel array is read out by a common bias of 8 channels. The possible degradation of the energy resolution has been investigated by simulations and experiments. The bias fluctuation effects of a series connection are less than those of a parallel connection. Simple calculations expect that the fluctuations of the common SQUID bias and common TES bias in a series connection are 10^{-7} and 10^{-3}, respectively. We constructed 8 SQUIDs which are connected to 8 TES outputs and a room temperature circuit for common bias readout and evaluated experimentally. Our simulation of crosstalk indicates that at an X-ray event rate of 500 cps/pixel, crosstalk will broaden a monochromatic line by about 0.01 %, or about 1.5 eV at 15 keV. Thus, our design goal of 10 eV energy resolution across the 0.5-15 keV band should be achievable.

  7. High dynamic range low-noise focal plane readout for VLWIR applications implemented with current mode background subtraction

    Science.gov (United States)

    Yang, Guang; Sun, Chao; Shaw, Timothy; Wrigley, Chris; Peddada, Pavani; Blazejewski, Edward R.; Pain, Bedabrata

    1998-09-01

    Design and operation of a low noise CMOS focal pa;ne readout circuit with ultra-high charge handling capacity is presented. Designed for high-background, VLWIR detector readout, each readout unit cell use an accurate dynamic current memory for automatic subtraction of the dark pedestal in current domain enabling measurement of small signals 85 dB below the dark level. The redout circuit operates with low-power dissipation, high linearity, and is capable of handling pedestal currents up to 300 nA. Measurements indicate an effective charge handling capacity of over 5 X 10(superscript 9) charges/pixel with less than 10(superscript 5) electrons of input referred noise.

  8. Readout control for high luminosity accelerators

    International Nuclear Information System (INIS)

    Belusevic, R.; Nixon, G.

    1991-01-01

    In this article we discuss some aspects of data acquisition at high luminosities and offer a set of design principles concerning readout control electronics and related software. As an example we include a brief description of a data transfer and processing system for future hadron colliders, featuring a transputer-based crate controller and a set of readout cards. This is a simplified and more efficient version of our design recently published in Nuclear Instruments and Methods. (orig.)

  9. Readout control for high luminosity accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Belusevic, R.; Nixon, G. (University Coll., London (UK). Dept. of Physics and Astronomy)

    1991-09-15

    In this article we discuss some aspects of data acquisition at high luminosities and offer a set of design principles concerning readout control electronics and related software. As an example we include a brief description of a data transfer and processing system for future hadron colliders, featuring a transputer-based crate controller and a set of readout cards. This is a simplified and more efficient version of our design recently published in Nuclear Instruments and Methods. (orig.).

  10. Readout control for high luminosity accelerators

    Science.gov (United States)

    Belusevic, R.; Nixon, G.

    1991-09-01

    In this article we discuss some aspects of data acquisition at high luminosities and offer a set of design principles concerning readout control electronics and related software. As an example we include a brief description of a data transfer and processing system for future hadron colliders, featuring a transputer-based crate controller and a set of readout cards. This is a simplified and more efficient version of our design recently published in Nuclear Instruments and Methods. [A295 (1991) 391].

  11. Performance verification of the CMS Phase-1 Upgrade Pixel detector

    Science.gov (United States)

    Veszpremi, V.

    2017-12-01

    The CMS tracker consists of two tracking systems utilizing semiconductor technology: the inner pixel and the outer strip detectors. The tracker detectors occupy the volume around the beam interaction region between 3 cm and 110 cm in radius and up to 280 cm along the beam axis. The pixel detector consists of 124 million pixels, corresponding to about 2 m 2 total area. It plays a vital role in the seeding of the track reconstruction algorithms and in the reconstruction of primary interactions and secondary decay vertices. It is surrounded by the strip tracker with 10 million read-out channels, corresponding to 200 m 2 total area. The tracker is operated in a high-occupancy and high-radiation environment established by particle collisions in the LHC . The current strip detector continues to perform very well. The pixel detector that has been used in Run 1 and in the first half of Run 2 was, however, replaced with the so-called Phase-1 Upgrade detector. The new system is better suited to match the increased instantaneous luminosity the LHC would reach before 2023. It was built to operate at an instantaneous luminosity of around 2×1034 cm-2s-1. The detector's new layout has an additional inner layer with respect to the previous one; it allows for more efficient tracking with smaller fake rate at higher event pile-up. The paper focuses on the first results obtained during the commissioning of the new detector. It also includes challenges faced during the first data taking to reach the optimal measurement efficiency. Details will be given on the performance at high occupancy with respect to observables such as data-rate, hit reconstruction efficiency, and resolution.

  12. CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

    Science.gov (United States)

    Domingues, Suzana; Perenzoni, Daniele; Perenzoni, Matteo; Stoppa, David

    2017-06-01

    In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm2 and 36 μW).

  13. ERICA: an energy resolving photon counting readout ASIC for X-ray in-line cameras

    Science.gov (United States)

    Macias-Montero, J.-G.; Sarraj, M.; Chmeissani, M.; Moore, T.; Casanova, R.; Martinez, R.; Puigdengoles, C.; Prats, X.; Kolstein, M.

    2016-12-01

    We present ERICA (Energy Resolving Inline X-ray Camera) a photon-counting readout ASIC, with 6 energy bins. The ASIC is composed of a matrix of 8 × 20 pixels controlled by a global digital controller and biased with 7 independent digital to analog converters (DACs) and a band-gap current reference. The pixel analog front-end includes a charge sensitive amplifier with 16 mV/ke- gain and dynamic range of 45 ke-. ERICA has programmable pulse width, an adjustable constant current feedback resistor, a linear test pulse generator, and six discriminators with 6-bit local threshold adjustment. The pixel digital back-end includes the digital controller, 8 counters of 8-bit depth, half-full buffer flag for any of the 8 counters, a 74-bit shadow/shift register, a 74-bit configuration latch, and charge sharing compensation processing to perform the energy classification and counting operations of every detected photon in 1 μ s. The pixel size is 330 μm × 330 μm and its average consumption is 150 μW. Implemented in TSMC 0.25 μm CMOS process, the ASIC pixel's equivalent noise charge (ENC) is 90 e- RMS connected to a 1 mm thickness matching CdTe detector biased at -300 V with a total leakage current of 20 nA.

  14. Design and testing of monolithic active pixel sensors for charged particle tracking, pt. 1

    CERN Document Server

    Deptuch, G; Claus, G; Colledani, C; Dulinski, W; Goerlach, U; Gomoushkin, Yu; Hu, Y; Husson, D; Orazi, G; Turchetta, R; Riester, J L; Winter, M

    2000-01-01

    A Monolithic Active Pixel Sensor (MAPS) for charged particle tracking based on a novel detector structure was proposed, simulated, fabricated and tested. The detector designed accordingly to this idea is inseparable from the readout electronics, since both of them are integrated onto the same, standard for a CMOS process, low- resistivity silicon wafer. The individual pixel is comprised of only 3 MOS transistors and a photodiode collecting the charge created in a thin undepleted epitaxial layer. This approach provides the whole detector surface sensitive to radiation (100% fill factor) with reduced pixel pitch (very high spatial resolution). This yields a low cost, high resolution and thin detecting device. The detailed device simulations using ISE-TCAD package have been carried out in order to study a charge collection mechanism and to validate the proposed idea. Consequently, two prototype chips have been fabricated using 0.6 mu m and 0.35 mu m CMOS processes. Special radiation tolerant layout techniques we...

  15. Synchrotron applications of pixel and strip detectors at Diamond Light Source

    International Nuclear Information System (INIS)

    Marchal, J.; Tartoni, N.; Nave, C.

    2009-01-01

    A wide range of position-sensitive X-ray detectors have been commissioned on the synchrotron X-ray beamlines operating at the Diamond Light Source in UK. In addition to mature technologies such as image-plates, CCD-based detectors, multi-wire and micro-strip gas detectors, more recent detectors based on semiconductor pixel or strip sensors coupled to CMOS read-out chips are also in use for routine synchrotron X-ray diffraction and scattering experiments. The performance of several commercial and developmental pixel/strip detectors for synchrotron studies are discussed with emphasis on the image quality achieved with these devices. Examples of pixel or strip detector applications at Diamond Light Source as well as the status of the commissioning of these detectors on the beamlines are presented. Finally, priorities and ideas for future developments are discussed.

  16. Studies for an upgrade of ALICE Inner Tracking System: Pixel chip characterization

    Directory of Open Access Journals (Sweden)

    Park Jonghan

    2017-01-01

    Full Text Available Inner Tracking System (ITS of ALICE is used for vertex determination and tracking. Future heavy-ion program at the LHC aims to run with high luminosity. To address this challenge, upgrade program of ITS is underway, which aims at better position resolution (factor of 3, high detection efficiency (>99%, high-rate readout capabilities (100 kHz for Pb-Pb and moderate radiation hardness (> 700 krad. The new ITS will be composed with 7 layers of silicon pixel chip based on Monolithic Active Pixel Sensor (MAPS technology. The characterization test of various version of prototype chips at different phases of development has been performed. This contribution will provide the main characterization results obtained from the measurements performed at laboratories and using test beam for finalizing the pixel chip specification.

  17. Realization and application of a 111 million pixel backside-illuminated detector and camera

    Science.gov (United States)

    Zacharias, Norbert; Dorland, Bryan; Bredthauer, Richard; Boggs, Kasey; Bredthauer, Greg; Lesser, Mike

    2007-09-01

    A full-wafer, 10,580 × 10,560 pixel (95 × 95 mm) CCD was designed and tested at Semiconductor Technology Associates (STA) with 9 μm square pixels and 16 outputs. The chip was successfully fabricated in 2006 at DALSA and some performance results are presented here. This program was funded by the Office of Naval Research through a Small Business Innovation in Research (SBIR) program requested by the U.S. Naval Observatory for its next generation astrometric sky survey programs. Using Leach electronics, low read-noise output of the 111 million pixels requires 16 seconds at 0.9 MHz. Alternative electronics developed at STA allow readout at 20 MHz. Some modifications of the design to include anti-blooming features, a larger number of outputs, and use of p-channel material for space applications are discussed.

  18. Characterization of a 512x512-pixel 8-output full-frame CCD for high-speed imaging

    Science.gov (United States)

    Graeve, Thorsten; Dereniak, Eustace L.

    1993-01-01

    The characterization of a 512 by 512 pixel, eight-output full frame CCD manufactured by English Electric Valve under part number CCD13 is discussed. This device is a high- resolution Silicon-based array designed for visible imaging applications at readout periods as low as two milliseconds. The characterization of the device includes mean-variance analysis to determine read noise and dynamic range, as well as charge transfer efficiency, MTF, and quantum efficiency measurements. Dark current and non-uniformity issues on a pixel-to-pixel basis and between individual outputs are also examined. The characterization of the device is restricted by hardware limitations to a one MHz pixel rate, corresponding to a 40 ms readout time. However, subsections of the device have been operated at up to an equivalent 100 frames per second. To maximize the frame rate, the CCD is illuminated by a synchronized strobe flash in between frame readouts. The effects of the strobe illumination on the imagery obtained from the device is discussed.

  19. The LHCb Vertex Locator (VELO) Pixel Detector Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00536755

    2017-01-01

    The LHCb experiment is designed to perform high-precision measurements of CP violation and the decays of beauty and charm hadrons at the Large Hadron Collider (LHC) at CERN. There is a planned upgrade during Long Shutdown 2 (LS2), expected in 2019, which will allow the detector to run at higher luminosities by transforming the entire readout to a trigger-less system. This will include a substantial upgrade of the Vertex Locator (VELO), the silicon tracker that surrounds the LHCb interaction region. The VELO is moving from silicon strip technology to hybrid pixel sensors, where silicon sensors are bonded to VeloPix ASICs. Sensor prototypes have undergone rigorous testing using the Timepix3 Telescope at the SPS, CERN. The main components of the upgrade are summarised and testbeam results presented.

  20. X-ray Characterization of a Multichannel Smart-Pixel Array Detector

    Energy Technology Data Exchange (ETDEWEB)

    Ross, Steve; Haji-Sheikh, Michael; Huntington, Andrew; Kline, David; Lee, Adam; Li, Yuelin; Rhee, Jehyuk; Tarpley, Mary; Walko, Donald A.; Westberg, Gregg; Williams, George; Zou, Haifeng; Landahl, Eric

    2016-01-01

    The Voxtel VX-798 is a prototype X-ray pixel array detector (PAD) featuring a silicon sensor photodiode array of 48 x 48 pixels, each 130 mu m x 130 mu m x 520 mu m thick, coupled to a CMOS readout application specific integrated circuit (ASIC). The first synchrotron X-ray characterization of this detector is presented, and its ability to selectively count individual X-rays within two independent arrival time windows, a programmable energy range, and localized to a single pixel is demonstrated. During our first trial run at Argonne National Laboratory's Advance Photon Source, the detector achieved a 60 ns gating time and 700 eV full width at half-maximum energy resolution in agreement with design parameters. Each pixel of the PAD holds two independent digital counters, and the discriminator for X-ray energy features both an upper and lower threshold to window the energy of interest discarding unwanted background. This smart-pixel technology allows energy and time resolution to be set and optimized in software. It is found that the detector linearity follows an isolated dead-time model, implying that megahertz count rates should be possible in each pixel. Measurement of the line and point spread functions showed negligible spatial blurring. When combined with the timing structure of the synchrotron storage ring, it is demonstrated that the area detector can perform both picosecond time-resolved X-ray diffraction and fluorescence spectroscopy measurements.

  1. The high dynamic range pixel array detector (HDR-PAD): Concept and design

    Energy Technology Data Exchange (ETDEWEB)

    Shanks, Katherine S.; Philipp, Hugh T.; Weiss, Joel T.; Becker, Julian; Tate, Mark W. [Laboratory of Atomic and Solid State Physics, Cornell University, Ithaca, NY 14853 (United States); Gruner, Sol M., E-mail: smg26@cornell.edu [Laboratory of Atomic and Solid State Physics, Cornell University, Ithaca, NY 14853 (United States); Cornell High Energy Synchrotron Source (CHESS), Cornell University, Ithaca, NY 14853 (United States)

    2016-07-27

    Experiments at storage ring light sources as well as at next-generation light sources increasingly require detectors capable of high dynamic range operation, combining low-noise detection of single photons with large pixel well depth. XFEL sources in particular provide pulse intensities sufficiently high that a purely photon-counting approach is impractical. The High Dynamic Range Pixel Array Detector (HDR-PAD) project aims to provide a dynamic range extending from single-photon sensitivity to 10{sup 6} photons/pixel in a single XFEL pulse while maintaining the ability to tolerate a sustained flux of 10{sup 11} ph/s/pixel at a storage ring source. Achieving these goals involves the development of fast pixel front-end electronics as well as, in the XFEL case, leveraging the delayed charge collection due to plasma effects in the sensor. A first prototype of essential electronic components of the HDR-PAD readout ASIC, exploring different options for the pixel front-end, has been fabricated. Here, the HDR-PAD concept and preliminary design will be described.

  2. All-passive pixel super-resolution of time-stretch imaging

    Science.gov (United States)

    Chan, Antony C. S.; Ng, Ho-Cheung; Bogaraju, Sharat C. V.; So, Hayden K. H.; Lam, Edmund Y.; Tsia, Kevin K.

    2017-03-01

    Based on image encoding in a serial-temporal format, optical time-stretch imaging entails a stringent requirement of state-of-the-art fast data acquisition unit in order to preserve high image resolution at an ultrahigh frame rate — hampering the widespread utilities of such technology. Here, we propose a pixel super-resolution (pixel-SR) technique tailored for time-stretch imaging that preserves pixel resolution at a relaxed sampling rate. It harnesses the subpixel shifts between image frames inherently introduced by asynchronous digital sampling of the continuous time-stretch imaging process. Precise pixel registration is thus accomplished without any active opto-mechanical subpixel-shift control or other additional hardware. Here, we present the experimental pixel-SR image reconstruction pipeline that restores high-resolution time-stretch images of microparticles and biological cells (phytoplankton) at a relaxed sampling rate (≈2-5 GSa/s)—more than four times lower than the originally required readout rate (20 GSa/s) — is thus effective for high-throughput label-free, morphology-based cellular classification down to single-cell precision. Upon integration with the high-throughput image processing technology, this pixel-SR time-stretch imaging technique represents a cost-effective and practical solution for large scale cell-based phenotypic screening in biomedical diagnosis and machine vision for quality control in manufacturing.

  3. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    Takubo, Y; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair the modules and to ease installation of the Insertable B-Layer (IBL). The IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using light weight staves and CO$_{2}$ based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and the IBL pr...

  4. Commissioning of the upgraded ATLAS Pixel Detector for Run2 at LHC

    CERN Document Server

    ATLAS Pixel Collaboration; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as ...

  5. The Pixel Detector of the ATLAS Experiment for LHC Run-2

    CERN Document Server

    Pernegger, H; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as ...

  6. The ATLAS Pixel Detector for Run II at the Large Hadron Collider

    CERN Document Server

    Marx, Marilyn; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as ...

  7. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    INSPIRE-00237659

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detect or and of the IBL project as...

  8. Acceleration of single pixel imaging

    Science.gov (United States)

    Nitta, K.

    2018-01-01

    A method for single pixel imaging (SPI) is introduced. The method is proposed to accelerate optical measurement. The method is also useful for high-definition imaging. The processing procedure of the method is described and some features of the based on the proposed method is described.

  9. Microwave SQUID Multiplexing of Metallic Magnetic Calorimeters: Status of Multiplexer Performance and Room-Temperature Readout Electronics Development

    Science.gov (United States)

    Wegner, M.; Karcher, N.; Krömer, O.; Richter, D.; Ahrens, F.; Sander, O.; Kempf, S.; Weber, M.; Enss, C.

    2018-02-01

    To our present best knowledge, microwave SQUID multiplexing (μ MUXing) is the most suitable technique for reading out large-scale low-temperature microcalorimeter arrays that consist of hundreds or thousands of individual pixels which require a large readout bandwidth per pixel. For this reason, the present readout strategy for metallic magnetic calorimeter (MMC) arrays combining an intrinsic fast signal rise time, an excellent energy resolution, a large energy dynamic range, a quantum efficiency close to 100% as well as a highly linear detector response is based on μ MUXing. Within this paper, we summarize the state of the art in MMC μ MUXing and discuss the most recent results. This particularly includes the discussion of the performance of a 64-pixel detector array with integrated, on-chip microwave SQUID multiplexer, the progress in flux ramp modulation of MMCs as well as the status of the development of a software-defined radio-based room-temperature electronics which is specifically optimized for MMC readout.

  10. Katherine: Ethernet Embedded Readout Interface for Timepix3

    Science.gov (United States)

    Burian, P.; Broulím, P.; Jára, M.; Georgiev, V.; Bergmann, B.

    2017-11-01

    The Timepix3—the latest generation of hybrid particle pixel detectors of Medipix family—yields a lot of new possibilities, i.e. a high hit-rate, a time resolution of 1.56 ns, event data-driven readout mode, and the capability of measuring the Time-over-Threshold (ToT - energy) and the Time-of-Arrival (ToA) simultaneously. This paper introduces a newly developed readout device for the Timepix3, called "Katherine", featuring a Gigabit Ethernet interface. The primary benefit of the Katherine is the operation of Timepix3 at long distance (up to 100 m) from computer or server, which is advantageous for the installation at beam lines, where the access is difficult or where radiation levels are too high for human interventions. The maximal hit-rate is limited by the bandwidth of the Ethernet connection (peer-to-peer connection; up to 16 Mhit/s). Since the Katherine interface is equipped with a processor of high computational power (ARM Cortex-A9 dual-core processor), it permits the use as a stand-alone (autonomous) radiation detector. The key features of the device are described in detail. These are the implemented high voltage power supply offering both polarities of bias voltage (up to ± 300 V), the automatic data sending to a sever via SSH, the automatic compensation of ToA values from columns with shifted matrix clock, etc. A dedicated control software was developed, which can be used for the detector preparation (sensor equalization, the DACs dependency scan, and the THL scan) and measurement control. Measured energy spectra from photon fields are shown.

  11. Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment

    Science.gov (United States)

    Berdalovic, I.; Bates, R.; Buttar, C.; Cardella, R.; Egidos Plaja, N.; Hemperek, T.; Hiti, B.; van Hoorne, J. W.; Kugathasan, T.; Mandic, I.; Maneuski, D.; Marin Tobon, C. A.; Moustakas, K.; Musa, L.; Pernegger, H.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E. J.; Sharma, A.; Snoeys, W.; Solans Sanchez, C.; Wang, T.; Wermes, N.

    2018-01-01

    The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging process implemented in the TowerJazz 180 nm CMOS process in the framework of the monolithic sensor development for the ALICE experiment. Sensors fabricated in this modified process feature full depletion of the sensitive layer, a sensor capacitance of only a few fF and radiation tolerance up to 1015 neq/cm2. This paper summarises the measurements of charge collection properties in beam tests and in the laboratory using radioactive sources and edge TCT. The results of these measurements show significantly improved radiation hardness obtained for sensors manufactured using the modified process. This has opened the way to the design of two large scale demonstrators for the ATLAS ITk. To achieve a design compatible with the requirements of the outer pixel layers of the tracker, a charge sensitive front-end taking 500 nA from a 1.8 V supply is combined with a fast digital readout architecture. The low-power front-end with a 25 ns time resolution exploits the low sensor capacitance to reduce noise and analogue power, while the implemented readout architectures minimise power by reducing the digital activity.

  12. THE CONTROLLED DRIFT DETECTOR : CHARACTERISATION OF THE READOUT MECHANISM AND OF THE CHARGE HANDLING CAPABILITY.

    Energy Technology Data Exchange (ETDEWEB)

    CASTOLDI,A.; GATTI,E.; GUAZZONI,C.; LONGONI,A.; REHAK,P.; STRUDER,L.

    1998-11-08

    A new position-sensing X-ray detector operated in integrate-readout mode has been recently designed and characterized. Due to the peculiar working principle of the new detector, the charge handling capability, that is the maximum charge that can be stored in a pixel, is related to the operating conditions of the device. In particular the amplitude of the barriers that confine the signal electrons during the integration phase depends on the applied drift field and on the field perturbation superposed to it. A detailed experimental characterization of the charge handling capability as a function of these parameters has been carried out.

  13. Radiation induced effects in the \\\\ATLAS Insertable B-Layer readout chip

    CERN Document Server

    The ATLAS collaboration

    2017-01-01

    The ATLAS Insertable B-Layer is the innermost pixel barrel layer of the ATLAS detector installed in 2014. During the first year of $pp$ collisions at $\\sqrt{s} = 13~{\\rm TeV}$ in 2015, an unusual increase was observed in the low voltage currents of the readout chips. This increase was found to be due to radiation damage to the chips. The dependence of the current on the total ionising dose and temperature has been studied using X-ray and proton beam sources, and will be presented in this note together with its possible parametrisation and operation guidelines for the detector.

  14. [Evaluation of Image Quality of Readout Segmented EPI with Readout Partial Fourier Technique].

    Science.gov (United States)

    Yoshimura, Yuuki; Suzuki, Daisuke; Miyahara, Kanae

    Readout segmented EPI (readout segmentation of long variable echo-trains: RESOLVE) segmented k-space in the readout direction. By using the partial Fourier method in the readout direction, the imaging time was shortened. However, the influence on image quality due to insufficient data sampling is concerned. The setting of the partial Fourier method in the readout direction in each segment was changed. Then, we examined signal-to-noise ratio (SNR), contrast-to-noise ratio (CNR), and distortion ratio for changes in image quality due to differences in data sampling. As the number of sampling segments decreased, SNR and CNR showed a low value. In addition, the distortion ratio did not change. The image quality of minimum sampling segments is greatly different from full data sampling, and caution is required when using it.

  15. LHCb: Fast Readout Control for the upgraded readout architecture of the LHCb experiment at CERN

    CERN Document Server

    Alessio, F

    2013-01-01

    The LHCb experiment at CERN has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity with an upgraded LHCb detector. As a consequence, the various LHCb sub-systems in the readout architecture will be upgraded to cope with higher sub-detector occupancies, higher rate, and higher readout load. The new architecture, new functionalities, and the first hardware implementation of a new LHCb Readout Control system (commonly referred to as S-TFC) for the upgraded LHCb experiment is here presented. Our attention is focused in describing solutions for the distribution of clock and timing information to control the entire upgraded readout architecture by profiting of a bidirectional optical network and powerful FPGAs, including a real-time mechanism to synchronize the entire system. Solutions and implementations are presented, together with first results on the simulation and the validation of the system.

  16. Merlin: a fast versatile readout system for Medipix3

    International Nuclear Information System (INIS)

    Plackett, R; Horswell, I; Gimenez, E N; Marchal, J; Omar, D; Tartoni, N

    2013-01-01

    This contribution reports on the development of a new high rate readout system for the Medipix3 hybrid pixel ASIC developed by the Detector Group at Diamond Light Source. It details the current functionality of the system and initial results from tests on Diamond's B16 beamline. The Merlin system is based on a National Instruments PXI/FlexRIO system running a Xilinx Virtex5 FPGA. It is capable of recording Medipix3 256 by 256 by 12 bit data frames at over 1 kHz in bursts of 1200 frames and running at over 100 Hz continuously to disk or over a TCP/IP link. It is compatible with the standard Medipix3 single chipboards developed at CERN and is capable of driving them over cable lengths of up to 10 m depending on the data rate required. In addition to a standalone graphical interface, a system of remote TCP/IP control and data transfer has been developed to allow easy integration with third party control systems and scripting languages. Two Merlin systems are being deployed on the B16 and I16 beamlines at Diamond and the system has been integrated with the EPICS/GDA control systems used. Results from trigger synchronisation, fast burst and high rate tests made on B16 in March are reported and demonstrate an encouraging reliability and timing accuracy. In addition to normal high resolution imaging applications of Medipix3, the results indicate the system could profitably be used in 'pump and probe' style experiments, where a very accurate, high frame rate is especially beneficial. In addition to these two systems, Merlin is being used by the Detector Group to test the Excalibur 16 chip hybrid modules, and by the LHCb VELO Pixel Upgrade group in their forthcoming testbeams. Additionally the contribution looks forward to further developments and improvements in the system, including full rate quad chip readout capability, multi-FPGA support, long distance optical communication and further functionality enhancements built on the capabilities of the Medipix3 chips.

  17. Merlin: a fast versatile readout system for Medipix3

    Science.gov (United States)

    Plackett, R.; Horswell, I.; Gimenez, E. N.; Marchal, J.; Omar, D.; Tartoni, N.

    2013-01-01

    This contribution reports on the development of a new high rate readout system for the Medipix3 hybrid pixel ASIC developed by the Detector Group at Diamond Light Source. It details the current functionality of the system and initial results from tests on Diamond's B16 beamline. The Merlin system is based on a National Instruments PXI/FlexRIO system running a Xilinx Virtex5 FPGA. It is capable of recording Medipix3 256 by 256 by 12 bit data frames at over 1 kHz in bursts of 1200 frames and running at over 100 Hz continuously to disk or over a TCP/IP link. It is compatible with the standard Medipix3 single chipboards developed at CERN and is capable of driving them over cable lengths of up to 10 m depending on the data rate required. In addition to a standalone graphical interface, a system of remote TCP/IP control and data transfer has been developed to allow easy integration with third party control systems and scripting languages. Two Merlin systems are being deployed on the B16 and I16 beamlines at Diamond and the system has been integrated with the EPICS/GDA control systems used. Results from trigger synchronisation, fast burst and high rate tests made on B16 in March are reported and demonstrate an encouraging reliability and timing accuracy. In addition to normal high resolution imaging applications of Medipix3, the results indicate the system could profitably be used in `pump and probe' style experiments, where a very accurate, high frame rate is especially beneficial. In addition to these two systems, Merlin is being used by the Detector Group to test the Excalibur 16 chip hybrid modules, and by the LHCb VELO Pixel Upgrade group in their forthcoming testbeams. Additionally the contribution looks forward to further developments and improvements in the system, including full rate quad chip readout capability, multi-FPGA support, long distance optical communication and further functionality enhancements built on the capabilities of the Medipix3 chips.

  18. A monolithic pixel sensor (TRAPPISTe-2) for particle physics instrumentation in OKI 0.2μm SOI technology

    Science.gov (United States)

    Soung Yee, L.; Alvarez, P.; Martin, E.; Cortina, E.; Ferrer, C.

    2012-12-01

    A monolithic active pixel sensor for charged particle tracking has been developed within the frame of a research and development project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology). TRAPPISTe aims to study the feasibility of developing a monolithic pixel sensor with SOI technology. TRAPPISTe-2 is the second prototype in this series and was fabricated with an OKI 0.20μm fully depleted (FD-SOI) CMOS process. This device contains test transistors and amplifiers, as well as two pixel matrices with integrated 3-transistor and amplifier readout electronics. The results presented are based on the first electrical measurements performed on the test structures and laser measurements on the pixel matrices.

  19. Construction and commissioning of the Phase 1 upgrade of the CMS pixel detector

    CERN Document Server

    Bartek, Rachel

    2017-01-01

    The Phase 1 upgrade of the CMS pixel detector, installed by the CMS collaboration during the recent extended end-of-year technical stop, is built out of four barrel layers (BPIX) and three forward disks in each endcap (FPIX). It comprises a total of 124M pixel channels, in 1,856 modules and it is designed to withstand instantaneous luminosities of up to $2 \\rm{x} 10^{34} \\rm{cm}^{-2} \\rm{s}^{-1}$ with increased detector acceptance and additional redundancy for the tracking, while at the same time reducing the material budget. These goals are achieved using a new readout chip and modified powering and readout schemes, one additional tracking layer both in the barrel and in the disks, and new detector supports including a $\\rm{CO}_2$ based evaporative cooling system. Different parts of the detector have been assembled over the last year and later brought to CERN for installation inside the CMS tracker. At various stages during the assembly tests have been performed to ensure that the readout and power electro...

  20. Development of Fast and High Precision CMOS Pixel Sensors for an ILC Vertex Detector

    CERN Document Server

    Hu-Guo, Christine

    2010-01-01

    The development of CMOS pixel sensors with column parallel read-out and integrated zero-suppression has resulted in a full size, nearly 1 Megapixel, prototype with ~100 \\mu s read-out time. Its performances are quite close to the ILD vertex detector specifications, showing that the sensor architecture can presumably be evolved to meet these specifications exactly. Starting from the existing architecture and achieved performances, the paper will expose the details of how the sensor will be evolved in the coming 2-3 years in perspective of the ILD Detector Baseline Document, to be delivered in 2012. Two different devices are foreseen for this objective, one being optimized for the inner layers and their fast read-out requirement, while the other exploits the dimmed background in the outer layers to reduce the power consumption. The sensor evolution relies on a high resistivity epitaxial layer, on the use of an advanced CMOS process and on the combination of column-level ADCs with a pixel array. The paper will p...

  1. Three-dimensional cross point readout detector design for including depth information

    Science.gov (United States)

    Lee, Seung-Jae; Baek, Cheol-Ha

    2018-04-01

    We designed a depth-encoding positron emission tomography (PET) detector using a cross point readout method with wavelength-shifting (WLS) fibers. To evaluate the characteristics of the novel detector module and the PET system, we used the DETECT2000 to perform optical photon transport in the crystal array. The GATE was also used. The detector module is made up of four layers of scintillator arrays, the five layers of WLS fiber arrays, and two sensor arrays. The WLS fiber arrays in each layer cross each other to transport light to each sensor array. The two sensor arrays are coupled to the forward and left sides of the WLS fiber array, respectively. The identification of three-dimensional pixels was determined using a digital positioning algorithm. All pixels were well decoded, with the system resolution ranging from 2.11 mm to 2.29 mm at full width at half maximum (FWHM).

  2. The Phase-II ATLAS ITk Pixel Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00349918; The ATLAS collaboration

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase~2 shutdown (foreseen to take place around 2025) by an all-silicon detector called the ``ITk'' (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and ring-shaped supports in the end-cap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation levels. The new pixel system could include up to 14 $\\mathrm{m^2}$ of silicon, depending on the final layout, which is expected to be decided in 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel end-cap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as |eta| $<4$. Supporting structures will be based on low mass, highly stabl...

  3. The CMS Silicon Pixel detector for HL-LHC

    CERN Document Server

    Steinbrueck, Georg

    2016-01-01

    The LHC is planning an upgrade program which will bring the luminosity to about 5~$\\times10^{34}$~cm$^{-2}$s$^{-1}$ in 2026, with the goal of an integrated luminosity of 3000 fb$^{-1}$ by the end of 2037. This High Luminosity scenario, HL-LHC, will present new challenges of higher data rates and increased radiation. To maintain its physics potential in this harsh environment, the CMS detector will undergo a major upgrade program known as the Phase II upgrade. The new Phase II pixel detector will require a high bandwidth readout system and highly radiation tolerant sensors and on-detector ASICs. Several technologies for the sensors are being studied. Serial powering schemes are under consideration to accommodate significant constraints on the system. These prospective designs, as well as new layout geometries that include very forward pixel discs with acceptance extended from $\\vert\\eta\\vert<2.4$ to $\\vert\\eta\\vert<4$, are presented together with performance estimates.

  4. Novel micropixel avalanche photodiodes (MAPD) with super high pixel density

    International Nuclear Information System (INIS)

    Anfimov, N.; Chirikov-Zorin, I.; Dovlatov, A.; Gavrishchuk, O.; Guskov, A.; Khovanskiy, N.; Krumshtein, Z.; Leitner, R.; Meshcheryakov, G.; Nagaytsev, A.; Olchevski, A.; Rezinko, T.; Sadovskiy, A.; Sadygov, Z.; Savin, I.; Tchalyshev, V.; Tyapkin, I.; Yarygin, G.; Zerrouk, F.

    2011-01-01

    In many detectors based on scintillators the photomultiplier tubes (PMTs) are used as photodetectors. At present photodiodes are finding wide application. Solid state photodetectors allow operation in strong magnetic fields that are often present in applications, e.g. some calorimeters operating near magnets, combined PET and MRT, etc. The photon detection efficiency (PDE) of photodiodes may reach values a few times higher than that of PMTs. Also, they are rigid, compact and have relatively low operating voltage. In the last few years Micropixel Avalanche PhotoDiodes (MAPD) have been developed and started to be used. The MAPD combines a lot of advantages of semiconductor photodetectors and has a high gain, which is close to that of the PMT. Yet, they have some disadvantages, and one of them is a limited dynamic range that corresponds to a total number of pixels. The novel deep microwell MAPD with high pixel density produced by the Zecotek Company partially avoids this disadvantage. In this paper characteristics of these photodetectors are presented in comparison with the PMT characteristics. The results refer to measurements of the gain, PDE, cross-talks, photon counting and applications: beam test results of two different 'Shashlyk' EM calorimeters for COMPASS (CERN) and NICA-MPD (JINR) with the MAPD readout and a possibility of using the MAPD in PET.

  5. The Phase II ATLAS Pixel Upgrade: The Inner Tracker (ITk)

    CERN Document Server

    Flick, Tobias; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the ITk (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m^2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to eta < 3.2 and two to eta < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions. Support...

  6. A CMOS Active Pixel Sensor for Charged Particle Detection

    Energy Technology Data Exchange (ETDEWEB)

    Matis, Howard S.; Bieser, Fred; Kleinfelder, Stuart; Rai, Gulshan; Retiere, Fabrice; Ritter, Hans George; Singh, Kunal; Wurzel, Samuel E.; Wieman, Howard; Yamamoto, Eugene

    2002-12-02

    Active Pixel Sensor (APS) technology has shown promise for next-generation vertex detectors. This paper discusses the design and testing of two generations of APS chips. Both are arrays of 128 by 128 pixels, each 20 by 20 {micro}m. Each array is divided into sub-arrays in which different sensor structures (4 in the first version and 16 in the second) and/or readout circuits are employed. Measurements of several of these structures under Fe{sup 55} exposure are reported. The sensors have also been irradiated by 55 MeV protons to test for radiation damage. The radiation increased the noise and reduced the signal. The noise can be explained by shot noise from the increased leakage current and the reduction in signal is due to charge being trapped in the epi layer. Nevertheless, the radiation effect is small for the expected exposures at RHIC and RHIC II. Finally, we describe our concept for mechanically supporting a thin silicon wafer in an actual detector.

  7. A gas pixel detector for x-ray polarimetry

    International Nuclear Information System (INIS)

    Baldini, L.; Angelini, F.; Bellazzini, R.; Bitti, F.; Brez, A.; Latronico, L.; Massai, M.M.; Minuti, M.; Omodei, N.; Razzano, M.; Sgro, C.; Spandre, G.; Costa, E.; Soffitta, P.; Pacciani, L.

    2006-01-01

    Even though lacking of solid experimental verifications, X-ray polarimetry is strongly established as a deep diagnostic tool for probing the emission mechanisms in astronomical sources of high energy radiation. The recent development of new, more efficient instrumentation, as well as the renewed interest of the theoreticians, has drawn a significant attention to the field. Particularly, the exploitation of the photoelectric effect for deriving polarization information seems to promise a great advance in sensitivity with respect to the conventional techniques. To this aim we have designed, produced and tested a CMOS VLSI array of 2101 pixels (with 80 μm pitch), to be directly used as the charge collecting anode of a Gas Electron Multiplier (GEM). Each pixel is fully covered by a hexagonal metal electrode and each of these electrodes is individually connected to a full electronics chain, built immediately below it; in this sense detector and read-out electronics become virtually the same thing. Even though we focus our attention on the polarimetric applications, our achievements are highly significant for the whole field of development of gas detectors, which for the first time reach the level of integration and resolution typical of solid state detectors

  8. The FPGA Pixel Array Detector

    International Nuclear Information System (INIS)

    Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

    2013-01-01

    A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

  9. SAR Image Complex Pixel Representations

    Energy Technology Data Exchange (ETDEWEB)

    Doerry, Armin W. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2015-03-01

    Complex pixel values for Synthetic Aperture Radar (SAR) images of uniform distributed clutter can be represented as either real/imaginary (also known as I/Q) values, or as Magnitude/Phase values. Generally, these component values are integers with limited number of bits. For clutter energy well below full-scale, Magnitude/Phase offers lower quantization noise than I/Q representation. Further improvement can be had with companding of the Magnitude value.

  10. D-Zero muon readout electronics design

    International Nuclear Information System (INIS)

    Baldin, B.; Hansen, S.; Los, S.; Matveev, M.; Vaniev, V.

    1996-11-01

    The readout electronics designed for the D null Muon Upgrade are described. These electronics serve three detector subsystems and one trigger system. The front-ends and readout hardware are synchronized by means of timing signals broadcast from the D null Trigger Framework. The front-end electronics have continuously running digitizers and two levels of buffering resulting in nearly deadtimeless operation. The raw data is corrected and formatted by 16- bit fixed point DSP processors. These processors also perform control of the data buffering. The data transfer from the front-end electronics located on the detector platform is performed by serial links running at 160 Mbit/s. The design and test results of the subsystem readout electronics and system interface are discussed

  11. A readout system for plastic scintillating fibers

    Science.gov (United States)

    Akbari, H.; Bao, J.; Chien, C.-Y.; Fenker, H.; Fitzgerald, R.; Fisher, P.; Glaubman, M.; Grimes, A.; Hofer, H.; Horvath, I.; Kaplan, D.; Lanius, K.; Leedom, I.; Macdermott, M.; Mnich, J.; Newman, D.; Orndorff, J.; Pevsner, A.; Reucroft, S.; Rose, J.; Spangler, J.; Spartiotis, C.; Tonisch, F.; Viertel, G.; Waldmeier, S.; Zehnder, L.

    1991-05-01

    A readout system for plastic scintillating fibers has been developed using a multi-anode microchannel photomultiplier tube operated in a 5 kG magnetic field and the CMOS MX4 microplexer chip. The microchannel photomultiplier tube with an anode array of 10×10 is coupled to an array of fibers using a precise alignment procedure. Each readout unit is capable of sampling signals from 100 fibers simultaneously and multiplexing the analog signals serially with rates of up to 5 MHz. The analog signals are subsequently digitized and subtracted from the pedestals previously stored using a specially designed analog to digital VME module. Such a readout system has many applications in high energy physics, solid state physics, and other fields where a large number of fibers must be read out in short times and at relatively high rates.

  12. The upgraded Pixel Detector of the ATLAS Experiment for Run-II at the Large Hadron Collider

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00407702

    2016-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the LHC. Taking advantage of the detector development period 2013 – 2014, the detector was extracted from the experiment and brought to surface to equip it with new service panels and to repair modules furthermore this helped with the installation of the Insertable B-Layer (IBL), fourth layer of pixel, installed in between the existing Pixel Detector and a new beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been used. A new readout chip has been designed with CMOS 130nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical perfor...

  13. Evaluation of Polarization Effects of e(-) Collection Schottky CdTe Medipix3RX Hybrid Pixel Detector

    OpenAIRE

    Astromskas, V; Gimenez, EN; Lohstroh, A; Tartoni, N

    2016-01-01

    This paper focuses on the evaluation of operational conditions such as temperature, exposure time and flux on the polarization of a Schottky electron collection CdTe detector. A Schottky e- collection CdTe Medipix3RX hybrid pixel detector was developed as a part of the CALIPSO-HIZPAD2 EU project. The 128 ×128 pixel matrix and 0.75 mm thick CdTe sensor bump-bonded to Medipix3RX readout chips enabled the study of the polarization effects. Single and quad module Medipix3RX chips were used which ...

  14. First generation of deep n-well CMOS MAPS with in-pixel sparsification for the ILC vertex detector

    International Nuclear Information System (INIS)

    Traversi, Gianluca; Bulgheroni, Antonio; Caccia, Massimo; Jastrzab, Marcin; Manghisoni, Massimo; Pozzati, Enrico; Ratti, Lodovico; Re, Valerio

    2009-01-01

    In this paper we present the characterization results relevant to a deep n-well (DNW) CMOS active pixel sensor chip designed for vertexing applications at the International Linear Collider. In this chip, named sparsified digital readout (SDR0), for the first time we implemented a sparsification logic at the pixel level. The DNW available in deep submicron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. In this work, the experimental characterization of the SDR0 chip, including data from radioactive source ( 55 Fe) tests, will be presented.

  15. Mapping Electrical Crosstalk in Pixelated Sensor Arrays

    Science.gov (United States)

    Seshadri, Suresh (Inventor); Cole, David (Inventor); Smith, Roger M. (Inventor); Hancock, Bruce R. (Inventor)

    2017-01-01

    The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.

  16. Conception de la gestion de l'alimentation à faible bruit, de petite taille et sur-puce pleinement pour les capteurs à pixels CMOS dans des expériences en physique des hautes énergies

    OpenAIRE

    Wang, Jia

    2012-01-01

    What are the elementary particles and how did the universe originate are the main driving forces in the high energy physics. In order to further demonstrate the standard model and discover new physics, several detectors are built for the high energy physics experiments. CMOS pixel sensors (CPS) can achieve an attractive tradeoff among many performance parameters, such as readout speed, granularity, material budget, power dissipation, radiation tolerance and integrating readout circuitry on th...

  17. CMS has a heart of pixels

    CERN Multimedia

    2003-01-01

    In the immediate vicinity of the collision point, CMS will be equipped with pixel detectors consisting of no fewer than 50 million pixels measuring 150 microns along each side. Each of the pixels, which receive the signal, is connected to its own electronic circuit by a tiny sphere (seen here in the electron microscope image) measuring 15 to 20 microns in diameter.

  18. Conception and characterization of a virtual coplanar grid for a 11×11 pixelated CZT detector

    Energy Technology Data Exchange (ETDEWEB)

    Espagnet, Romain; Frezza, Andrea [Department of Physics, Engineering Physics and Optics and Cancer Research Center, Université Laval, Quebec city, QC, Canada G1R 0A6 (Canada); Martin, Jean-Pierre; Hamel, Louis-André [Department of Physics, Université de Montréal, C.P. 6128 Montréal QC, Canada H3C 3J7 (Canada); Després, Philippe, E-mail: philippe.despres@phy.ulaval.ca [Department of Physics, Engineering Physics and Optics and Cancer Research Center, Université Laval, Quebec city, QC, Canada G1R 0A6 (Canada); Department of Radiation Oncology and Research Center of CHU de Québec - Université Laval, Quebec city, QC Canada G1R 2J6 (Canada)

    2017-07-11

    Due to the low mobility of holes in CZT, commercially available detectors with a relatively large volume typically use a pixelated anode structure. They are mostly used in imaging applications and often require a dense electronic readout scheme. These large volume detectors are also interesting for high-sensitivity applications and a CZT-based blood gamma counter was developed from a 20×20×15 mm{sup 3} crystal available commercially and having a 11×11 pixelated readout scheme. A method is proposed here to reduce the number of channels required to use the crystal in a high-sensitivity counting application, dedicated to pharmacokinetic modelling in PET and SPECT. Inspired by a classic coplanar anode, an implementation of a virtual coplanar grid was done by connecting the 121 pixels of the detector to form intercalated bands. The layout, the front-end electronics and the characterization of the detector in this 2-channel anode geometry is presented. The coefficients required to compensate for electron trapping in CZT were determined experimentally to improve the performance. The resulting virtual coplanar detector has an intrinsic efficiency of 34% and an energy resolution of 8% at 662 keV. The detector's response was linear between 80 keV and 1372 keV. This suggests that large CZT crystals offer an excellent alternative to scintillation detectors for some applications, especially those where high-sensitivity and compactness are required.

  19. High bandwidth pixel detector modules for the ATLAS Insertable B-Layer

    International Nuclear Information System (INIS)

    Backhaus, Malte

    2014-01-01

    The investigation of the nature of the recently discovered electro-weak symmetry breaking mechanism of the standard model of particle physics as well as the search for physics beyond the standard model with the LHC require to collect even more data. To achieve this goal, the luminosity of the LHC will be increased in two steps. The increased luminosity results in serious challenges for the inner tracking systems of the experiments at the LHC. The ATLAS pixel detector will also be upgraded in a two stage program. During the shutdown in 2013 and 2014 a fourth hybrid pixel detector layer, the socalled Insertable B-Layer (IBL) is inserted inside the existing pixel detector. This thesis focuses on the characterization, performance measurement, and production quality assurance of the central sensitive elements of the IBL, the modules. This includes a full characterization of the readout chip (FE-I4) and of the assembled modules. A completely new inner tracking system is mandatory in ATLAS after the second luminosity increase in the shutdown of 2022 and 2023. The final chapter of this thesis introduces a new module concept that uses an industrial high voltage CMOS technology as sensor layer, which is capacitively coupled to the FE-I4 readout chip.

  20. Prototypes and system test stands for the Phase1 upgrade of the CMS pixel detector

    CERN Document Server

    AUTHOR|(CDS)2073564

    2015-01-01

    The CMS pixel phase-1 upgrade project replaces the current pixel detector with an upgraded system with faster readout electronics during the extended year-end technical stop of 2016/17. New electronics prototypes for the system have been developed, and tests in a realistic environment for a comprehensive evaluation are needed. A full readout test stand with either the same hardware as used in the current CMS pixel detector or the latest prototypes of upgrade electronics has been built. The setup enables the observation and investigation of a jitter increase in the data line as the trigger rate increase. This increase is due to the way in which the clock and trigger distribution is implemented in CMS. A new prototype of the electronics with a PLL based on a voltage controlled quartz crystal oscillator (QPLL), which works as jitter filter, in the clock distribution path was produced. With the test stand, it was confirmed that the jitter increase is not seen with the prototype, and also good performance was conf...

  1. New generation of monolithic active pixel sensors for charged particle detection

    International Nuclear Information System (INIS)

    Deptuch, G.

    2002-09-01

    Vertex detectors are of great importance in particle physics experiments, as the knowledge of the event flavour is becoming an issue for the physics programme at Future Linear Colliders. Monolithic Active Pixel Sensors (MAPS) based on a novel detector structure have been proposed. Their fabrication is compatible with a standard CMOS process. The sensor is inseparable from the readout electronics, since both of them are integrated on the same, low-resistivity silicon wafer. The basic pixel configuration comprises only three MOS transistors and a diode collecting the charge through thermal diffusion. The charge is generated in the thin non-depleted epitaxial layer underneath the readout electronics. This approach provides, at low cost, a high resolution and thin device with the whole area sensitive to radiation. Device simulations using the ISE-TCAD package have been carried out to study the charge collection mechanism. In order to demonstrate the viability of the technique, four prototype chips have been fabricated using different submicrometer CMOS processes. The pixel gain has been calibrated using a 55 Fe source and the Poisson sequence method. The prototypes have been exposed to high-energy particle beams at CERN. The tests proved excellent detection performances expressed in a single-track spatial resolution of 1.5 μm and detection efficiency close to 100%, resulting from a SNR ratio of more than 30. Irradiation tests showed immunity of MAPS to a level of a few times 10 12 n/cm 2 and a few hundred kRad of ionising radiation. The ideas for future work, including on-pixel signal amplification, double sampling operation and current mode pixel design are present as well. (author)

  2. Characterisation of the NA62 GigaTracker end of column readout ASIC

    International Nuclear Information System (INIS)

    Noy, M; Rinella, G Aglieri; Fiorini, M; Jarron, P; Kaplon, J; Kluge, A; Morel, M; Perktold, L; Riedler, P; Martin, E

    2011-01-01

    The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 μm pitch position information and operate with a dead-time of 1% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

  3. Characterisation of the high dynamic range Large Pixel Detector (LPD) and its use at X-ray free electron laser sources

    Science.gov (United States)

    Veale, M. C.; Adkin, P.; Booker, P.; Coughlan, J.; French, M. J.; Hart, M.; Nicholls, T.; Schneider, A.; Seller, P.; Pape, I.; Sawhney, K.; Carini, G. A.; Hart, P. A.

    2017-12-01

    The STFC Rutherford Appleton Laboratory have delivered the Large Pixel Detector (LPD) for MHz frame rate imaging at the European XFEL. The detector system has an active area of 0.5 m × 0.5 m and consists of a million pixels on a 500 μm pitch. Sensors have been produced from 500 μm thick Hammamatsu silicon tiles that have been bump bonded to the readout ASIC using a silver epoxy and gold stud technique. Each pixel of the detector system is capable of measuring 105 12 keV photons per image readout at 4.5 MHz. In this paper results from the testing of these detectors at the Diamond Light Source and the Linac Coherent Light Source (LCLS) are presented. The performance of the detector in terms of linearity, spatial uniformity and the performance of the different ASIC gain stages is characterised.

  4. FE-I4 Firmware Development and Integration with FELIX for the Pixel Detector

    CERN Document Server

    Yadav, Amitabh; Sharma, Abhishek; CERN. Geneva. EP Department

    2017-01-01

    CERN has planned a series of upgrades for the LHC. The last in this current series of planned upgrades is designated the HL-LHC. At the same time, the ATLAS Experiment will be extensively changed to meet the challenges of this upgrade (termed as the “Phase-II” upgrade). The Inner Detector will be completely rebuilt for the phase-II. The TRT, SCT and Pixel will be replaced by the all-silicon tracker, termed as the Inner Tracker (ITk). The read-out of this future ITk detector is an engineering challenge for the routing of services and quality of the data. This document describes the FPGA firmware development that integrates the GBT, Elink and Rx-Tx Cores for communication between the FE-I4 modules and the FELIX read-out system.

  5. A 400 KHz line rate 2048-pixel stitched SWIR linear array

    Science.gov (United States)

    Anchlia, Ankur; Vinella, Rosa M.; Gielen, Daphne; Wouters, Kristof; Vervenne, Vincent; Hooylaerts, Peter; Deroo, Pieter; Ruythooren, Wouter; De Gaspari, Danny; Das, Jo; Merken, Patrick

    2016-05-01

    Xenics has developed a family of stitched SWIR long linear arrays that operate up to 400 KHz of line rate. These arrays serve medical and industrial applications that require high line rates as well as space applications that require long linear arrays. The arrays are based on a modular ROIC design concept: modules of 512 pixels are stitched during fabrication to achieve 512, 1024 and 2048 pixel arrays. Each 512-pixel module has its own on-chip digital sequencer, analog readout chain and 4 output buffers. This modular concept enables a long array to run at a high line rates irrespective of the array length, which limits the line rate in a traditional linear array. The ROIC is flip-chipped with InGaAs detector arrays. The FPA has a pixel pitch of 12.5μm and has two pixel flavors: square (12.5μm) and rectangular (250μm). The frontend circuit is based on Capacitive Trans-impedance Amplifier (CTIA) to attain stable detector bias, and good linearity and signal integrity, especially at high speeds. The CTIA has an input auto-zero mechanism that allows to have low detector bias (clock rate of 60MHz and a minimum integration time of 1.4μs, achieves the highest line rate of 400 KHz. In this paper, design details and measurements results are presented in order to demonstrate the array performance.

  6. A new generation of small pixel pitch/SWaP cooled infrared detectors

    Science.gov (United States)

    Espuno, L.; Pacaud, O.; Reibel, Y.; Rubaldo, L.; Kerlain, A.; Péré-Laperne, N.; Dariel, A.; Roumegoux, J.; Brunner, A.; Kessler, A.; Gravrand, O.; Castelein, P.

    2015-10-01

    Following clear technological trends, the cooled IR detectors market is now in demand for smaller, more efficient and higher performance products. This demand pushes products developments towards constant innovations on detectors, read-out circuits, proximity electronics boards, and coolers. Sofradir was first to show a 10μm focal plane array (FPA) at DSS 2012, and announced the DAPHNIS 10μm product line back in 2014. This pixel pitch is a key enabler for infrared detectors with increased resolution. Sofradir recently achieved outstanding products demonstrations at this pixel pitch, which clearly demonstrate the benefits of adopting 10μm pixel pitch focal plane array-based detectors. Both HD and XGA Daphnis 10μm products also benefit from a global video datapath efficiency improvement by transitioning to digital video interfaces. Moreover, innovative smart pixels functionalities drastically increase product versatility. In addition to this strong push towards a higher pixels density, Sofradir acknowledges the need for smaller and lower power cooled infrared detector. Together with straightforward system interfaces and better overall performances, latest technological advances on SWAP-C (Size, Weight, Power and Cost) Sofradir products enable the advent of a new generation of high performance portable and agile systems (handheld thermal imagers, unmanned aerial vehicles, light gimbals etc...). This paper focuses on those features and performances that can make an actual difference in the field.

  7. Characterization of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade

    CERN Document Server

    Backhaus, Malte

    2012-01-01

    The ATLAS Insertable B-Layer (IBL) collaboration plans to insert a fourth pixel layer inside the present Pixel Detector to recover from eventual failures in the current pixel system, especially the b-layer. Additionally the IBL will ensure excellent tracking, vertexing and b-tagging performance during the LHC phase I and add robustness in tracking with high luminosity pile-up. The expected peak luminosity for IBL is 2 to 3centerdot1034 cm-2s-1 and IBL is designed for an integrated luminosity of 700 fb-1. This corresponds to an expected fluence of 5centerdot1015 1 MeV neqcm-2 and a total ionizing dose of 250 MRad. In order to cope with these requirements, two new module concepts are under investigation, both based on a new front end IC, called FE-I4. This IC was designed as readout chip for future ATLAS Pixel Detectors and its first application will be the IBL. The planar pixel sensor (PPS) based module concept benefits from its well understood design, which is kept as similar as possible to the design of the ...

  8. Characterization of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade

    CERN Document Server

    Backhaus, M

    2012-01-01

    The ATLAS Insertable B-Layer (IBL) collaboration plans to insert a fourth pixel layer inside the present Pixel Detector to recover from eventual failures in the current pixel system, especially the b-layer. Additionally the IBL will ensure excellent tracking, vertexing and b-tagging performance during the LHC phase I and add robustness in tracking with high luminosity pile-up. The expected peak luminosity for IBL is 2 to 3•10^34 cm^−2 s^ −1 and IBL is designed for an integrated luminosity of 700 fb^−1 . This corresponds to an expected fluence of 5 • 10^15 1 MeV n_eqcm^−2 and a total ionizing dose of 250 MRad. In order to cope with these requirements, two new module concepts are under investigation, both based on a new front end IC, called FE-I4. This IC was designed as readout chip for future ATLAS Pixel Detectors and its first application will be the IBL. The planar pixel sensor (PPS) based module concept benefits from its well understood design, which is kept as similar as possible to the design...

  9. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00235789; The ATLAS collaboration

    2016-01-01

    During Run-1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This includes the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3 cm the IBL is located extremely close to the interaction point. Therefore a new readout chip and two new sensor technologies (planar and 3D) are used in IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanic...

  10. The Pixel Detector of the ATLAS Experiment for LHC Run-2

    CERN Document Server

    Pernegger, Heinz; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and hit occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as we...

  11. The Pixel Detector of the ATLAS Experiment for the Run 2 at the Large Hadron Collider

    CERN Document Server

    Mandelli, B; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run 1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). The IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO$_2$ based cooling system have been adopted. The IBL construction and installation in the ATLAS Experiment has been completed very successfu...

  12. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    Oide, H; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and will be installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project as well as the ...

  13. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    Mandelli, B; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and will be installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project as well as the ...

  14. The Pixel Detector of the ATLAS experiment for the Run 2 at the Large Hadron Collider

    CERN Document Server

    Oide, H; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run 1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). The IBL is the fourth layer of the Run 2 Pixel Detector, and it was installed in May 2014 between the existing Pixel Detector and the new smaller-radius beam pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project...

  15. Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

    CERN Document Server

    Llopart Cudie, Xavier; Campbell, M

    2007-01-01

    Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each...

  16. Design and characterization of novel monolithic pixel sensors for the ALICE ITS upgrade

    CERN Document Server

    Cavicchioli, C; Giubilato, P; Hillemanns, H; Junique, A; Kugathasan, T; Mager, M; Marin Tobon, C A; Martinengo, P; Mattiazzo, S; Mugnier, H; Musa, L; Pantano, D; Rousset, J; Reidt, F; Riedler, P; Snoeys, W; Van Hoorne, J W; Yang, P

    2014-01-01

    Within the R&D activities for the upgrade of the ALICE Inner Tracking System (ITS), Monolithic Active Pixel Sensors (MAPS) are being developed and studied, due to their lower material budget (~0.3%X0~0.3%X0 in total for each inner layer) and higher granularity (View the MathML source~20μm×20μm pixels) with respect to the present pixel detector. This paper presents the design and characterization results of the Explorer0 chip, manufactured in the TowerJazz 180 nm CMOS Imaging Sensor process, based on a wafer with high-resistivity View the MathML source(ρ>1kΩcm) and 18 μm thick epitaxial layer. The chip is organized in two sub-matrices with different pixel pitches (20 μm and 30 μm), each of them containing several pixel designs. The collection electrode size and shape, as well as the distance between the electrode and the surrounding electronics, are varied; the chip also offers the possibility to decouple the charge integration time from the readout time, and to change the sensor bias. The charge c...

  17. Performance of novel silicon n-in-p planar Pixel Sensors

    CERN Document Server

    Gallrapp, C; Macchiolo, A; Nisius, R; Pernegger, H; Richter, R H; Weigell, P

    2012-01-01

    The performance of novel n-in-p planar pixel detectors, designed for future upgrades of the ATLAS Pixel system is presented. The n-in-p silicon sensors technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness, that allow for enlarging the area instrumented with pixel detectors. The n-in-p modules presented here, are composed of pixel sensors produced by CiS connected by bump-bonding to the ATLAS readout chip FE-I3. The characterization of these devices has been performed before and after irradiation up to a fluence of 5 x 10**15 neq/cm2 . Charge collection measurements carried out with radioactive sources have proven the functioning of this technology up to these particle fluences. First results from beam test data with a 120 GeV/c pion beam at the CERN-SPS are also discussed, demonstrating a high tracking efficiency before irradiation, and a high collected charge for a device irradiated at a fluence of 5 x 10**15 neq/cm2 .

  18. Pixel-by-pixel mean transit time without deconvolution.

    Science.gov (United States)

    Dobbeleir, Andre A; Piepsz, Amy; Ham, Hamphrey R

    2008-04-01

    Mean transit time (MTT) within a kidney is given by the integral of the renal activity on a well-corrected renogram between time zero and time t divided by the integral of the plasma activity between zero and t, providing that t is close to infinity. However, as the data acquisition of a renogram is finite, the MTT calculated using this approach might result in the underestimation of the true MTT. To evaluate the degree of this underestimation we conducted a simulation study. One thousand renograms were created by convoluting various plasma curves obtained from patients with different renal clearance levels with simulated retentions curves having different shapes and mean transit times. For a 20 min renogram, the calculated MTT started to underestimate the MTT when the MTT was higher than 6 min. The longer the MTT, the greater was the underestimation. Up to a MTT value of 6 min, the error on the MTT estimation is negligible. As normal cortical transit is less than 2 min, this approach is used for patients to calculate pixel-to-pixel cortical mean transit time and to create a MTT parametric image without deconvolution.

  19. Comparison between two possible CMS Barrel Muon Readout Architectures

    International Nuclear Information System (INIS)

    Aguayo, P.; Barcala, J.M.; Molinero, A.; Pablos, J.L.; Willmott, C.; Alberdi, J.; Marin, J.; Navarrete, J.; Romero, L.

    1997-01-01

    A comparison between two possible readout arquitectures for the CMS muon barrel readout electronics is presented, including various aspects like costs, reliability, installation, staging and maintenance. A review of the present baseline architecture is given in the appendix. (Author)

  20. PANDA straw tube detectors and readout

    Science.gov (United States)

    Strzempek, P.; PANDA Collaboration

    2016-07-01

    PANDA is a detector under construction dedicated to studies of production and interaction of particles in the charmonium mass range using antiproton beams in the momentum range of 1.5 - 15 GeV/c at the Facility for Antiproton and Ion Research (FAIR) in Darmstadt. PANDA consists of two spectrometers: a Target Spectrometer with a superconducting solenoid and a Forward Spectrometer using a large dipole magnet and covering the most forward angles (Θ < 10 °). In both spectrometers, the particle's trajectories in the magnetic field are measured using self-supporting straw tube detectors. The expected high count rates, reaching up to 1 MHz/straw, are one of the main challenges for the detectors and associated readout electronics. The paper presents the readout chain of the tracking system and the results of tests performed with realistic prototype setups. The readout chain consists of a newly developed ASIC chip (PASTTREC 〈 PANDASTTReadoutChip 〉) with amplification, signal shaping, tail cancellation, discriminator stages and Time Readout Boards as digitizer boards.

  1. Very forward calorimeters readout and machine interface

    Indian Academy of Sciences (India)

    The paper describes the requirements for the readout electronics and DAQ for the instrumentation of the forward region of the future detector at the international linear collider. The preliminary design is discussed. Author Affiliations. Wojciech Wierba1 on behalf of the FCAL Collaboration. The Henryk Niewodniczański ...

  2. Evolution of the dual-readout calorimeter

    Indian Academy of Sciences (India)

    Measuring the energy of hadronic jets with high precision is essential at present and future colliders, in particular at ILC. The 4th concept design is built upon calorimetry criteria that result in the DREAM prototype, read-out via two different types of longitudinal fibers, scintillator and quartz respectively, and therefore capable ...

  3. Very forward calorimeters readout and machine interface

    Indian Academy of Sciences (India)

    group of channels (probably every 10 channels will have one ADC) is foreseen. The digital link based on LVDS chips will transmit data to the DAQ. Proposed solution is shown in figure 2. For the BeamCal a similar readout scheme will be needed. LumiCal has to provide a raw luminosity measurement every minute. The MC.

  4. Evolution of the dual-readout calorimeter

    Indian Academy of Sciences (India)

    Measuring the energy of hadronic jets with high precision is essential at present and future colliders, ... binding energy losses in nuclear break-up (measuring neutrons of few MeV energy). Keywords. International ... demonstration that a dual readout calorimeter is feasible and offers several benefits. 3. DREAM performance.

  5. Latest generation of ASICs for photodetector readout

    International Nuclear Information System (INIS)

    Seguin-Moreau, N.

    2013-01-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips

  6. Rutherford X-ray spectrometer readout

    International Nuclear Information System (INIS)

    Bateman, J.E.

    1978-07-01

    Rutherford electronic X-ray spectrometer readout is based on the combination of two established techniques (a) the detection and location of soft X-rays by means of multichannel electron multiplier arrays (MCP's), and (b) the electronic readout of charge distributions (generally in multi-wire proportional counters) by means of the delay line techniques. In order for the latter device to function well a charge signal of approximately 10 6 electrons must be available to the delay line wand. This is achieved in the present device by means of two cascaded MCP's which can produce electron gains up to approximately 10 8 , and so operate the delay line from the single electron pulses generated at the front face of an MCP by a soft X-ray. The delay line readout technique was chosen because of its simplicity (both in terms of the necessary hardware and the associated electronics), robustness, and ease of implementation. In order to achieve the target spatial resolution of 50 μm (fwhm) or 20 μm (standard deviation) it was necessary to adapt the charge collection system so that the readout takes place from a length of delay line 200 mm long. The general layout of the system and the functions of the electronic circuits are described. Performance testing, setting up procedures and trouble shooting of the system are discussed. (U.K.)

  7. Evolution of the dual-readout calorimeter

    Indian Academy of Sciences (India)

    The 4th concept design is built upon calorimetry criteria that result in the DREAM prototype, read-out via two different types of longitudinal fibers, scintillator and quartz respectively, and therefore capable of determining for each shower the corresponding electromagnetic fraction, thus eliminating the strong effect of ...

  8. A readout unit for high rate applications

    CERN Document Server

    Toledo, J; Domínguez, D; Guirao-Elias, A; Müller, H

    2002-01-01

    The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low- overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via the PCI bus, which is hosted by a networked microprocessor card. Its main tasks are remote FPGA configuration and initialization of the PCI cards. The RU hardware architecture has been optimized for a throughput of up to 200 MB/s at a 1 MHz trigger rate, as required by the most demanding application, the LHCb level-1 trig...

  9. Microwave multiplex readout for superconducting sensors

    Energy Technology Data Exchange (ETDEWEB)

    Ferri, E., E-mail: elena.ferri@mib.infn.it [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Becker, D.; Bennett, D. [NIST, Boulder, CO (United States); Faverzani, M. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Fowler, J.; Gard, J. [NIST, Boulder, CO (United States); Giachero, A. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Hays-Wehle, J.; Hilton, G. [NIST, Boulder, CO (United States); Maino, M. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Mates, J. [NIST, Boulder, CO (United States); Puiu, A.; Nucciotti, A. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Reintsema, C.; Schmidt, D.; Swetz, D.; Ullom, J.; Vale, L. [NIST, Boulder, CO (United States)

    2016-07-11

    The absolute neutrino mass scale is still an outstanding challenge in both particle physics and cosmology. The calorimetric measurement of the energy released in a nuclear beta decay is a powerful tool to determine the effective electron-neutrino mass. In the last years, the progress on low temperature detector technologies has allowed to design large scale experiments aiming at pushing down the sensitivity on the neutrino mass below 1 eV. Even with outstanding performances in both energy (~ eV on keV) and time resolution (~ 1 μs) on the single channel, a large number of detectors working in parallel is required to reach a sub-eV sensitivity. Microwave frequency domain readout is the best available technique to readout large array of low temperature detectors, such as Transition Edge Sensors (TESs) or Microwave Kinetic Inductance Detectors (MKIDs). In this way a multiplex factor of the order of thousands can be reached, limited only by the bandwidth of the available commercial fast digitizers. This microwave multiplexing system will be used to readout the HOLMES detectors, an array of 1000 microcalorimeters based on TES sensors in which the {sup 163}Ho will be implanted. HOLMES is a new experiment for measuring the electron neutrino mass by means of the electron capture (EC) decay of {sup 163}Ho. We present here the microwave frequency multiplex which will be used in the HOLMES experiment and the microwave frequency multiplex used to readout the MKID detectors developed in Milan as well.

  10. Development of high performance readout ASICs for silicon photomultipliers (SiPMs)

    International Nuclear Information System (INIS)

    Shen, Wei

    2012-01-01

    Silicon Photomultipliers (SiPMs) are novel kind of solid state photon detectors with extremely high photon detection resolution. They are composed of hundreds or thousands of avalanche photon diode pixels connected in parallel. These avalanche photon diodes are operated in Geiger Mode. SiPMs have the same magnitude of multiplication gain compared to the conventional photomultipliers (PMTs). Moreover, they have a lot of advantages such as compactness, relatively low bias voltage and magnetic field immunity etc. Special readout electronics are required to preserve the high performance of the detector. KLauS and STiC are two CMOS ASIC chips designed in particular for SiPMs. KLauS is used for SiPM charge readout applications. Since SiPMs have a much larger detector capacitance compared to other solid state photon detectors such as PIN diodes and APDs, a few special techniques are used inside the chip to make sure a descent signal to noise ratio for pixel charge signal can be obtained. STiC is a chip dedicated to SiPM time-of-flight applications. High bandwidth and low jitter design schemes are mandatory for such applications where time jitter less than tens of picoseconds is required. Design schemes and error analysis as well as measurement results are presented in the thesis.

  11. Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

    International Nuclear Information System (INIS)

    Fabbri, A; Notaristefani, F De; Galasso, M; Cencelli, V Orsolini; Falco, M D; Marinelli, M; Tortora, L; Verona, C; Rinati, G Verona

    2013-01-01

    This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ''Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

  12. USB 3.0 readout and time-walk correction method for Timepix3 detector

    Science.gov (United States)

    Turecek, D.; Jakubek, J.; Soukup, P.

    2016-12-01

    The hybrid particle counting pixel detectors of Medipix family are well known. In this contribution we present new USB 3.0 based interface AdvaDAQ for Timepix3 detector. The AdvaDAQ interface is designed with a maximal emphasis to the flexibility. It is successor of FitPIX interface developed in IEAP CTU in Prague. Its modular architecture supports all Medipix/Timepix chips and all their different readout modes: Medipix2, Timepix (serial and parallel), Medipix3 and Timepix3. The high bandwidth of USB 3.0 permits readout of 1700 full frames per second with Timepix or 8 channel data acquisition from Timepix3 at frequency of 320 MHz. The control and data acquisition is integrated in a multiplatform PiXet software (MS Windows, Mac OS, Linux). In the second part of the publication a new method for correction of the time-walk effect in Timepix3 is described. Moreover, a fully spectroscopic X-ray imaging with Timepix3 detector operated in the ToT mode (Time-over-Threshold) is presented. It is shown that the AdvaDAQ's readout speed is sufficient to perform spectroscopic measurement at full intensity of radiographic setups equipped with nano- or micro-focus X-ray tubes.

  13. Development of X-ray CCD camera system with high readout rate using ASIC

    International Nuclear Information System (INIS)

    Nakajima, Hiroshi; Matsuura, Daisuke; Anabuki, Naohisa; Miyata, Emi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Katayama, Haruyoshi

    2009-01-01

    We report on the development of an X-ray charge-coupled device (CCD) camera system with high readout rate using application-specific integrated circuit (ASIC) and Camera Link standard. The distinctive ΔΣ type analog-to-digital converter is introduced into the chip to achieve effective noise shaping and to obtain a high resolution with relatively simple circuits. The unit test proved moderately low equivalent input noise of 70μV with a high readout pixel rate of 625 kHz, while the entire chip consumes only 100 mW. The Camera Link standard was applied for the connectivity between the camera system and frame grabbers. In the initial test of the whole system, we adopted a P-channel CCD with a thick depletion layer developed for X-ray CCD camera onboard the next Japanese X-ray astronomical satellite. The characteristic X-rays from 109 Cd were successfully read out resulting in the energy resolution of 379(±7)eV (FWHM) at 22.1 keV, that is, ΔE/E=1.7% with a readout rate of 44 kHz.

  14. Influence of electromagnetic interference on the analog part of hybrid Pixel detectors

    International Nuclear Information System (INIS)

    Holik, M; Kraus, V; Granja, C; Jakubek, J; Georgiev, V; Hromadka, M; Skala, J; Kubik, Z

    2011-01-01

    The analog signal from the sensor of hybrid semiconductor pixel detectors is prone to electro-magnetic interference. The study and diagnosis of induced and common electro-magnetic coupling between the analog part and digital part of these devices is required. The influence of electro-magnetic interference was tested on the setup with a pixel detector Timepix or Medipix and a FITPix read-out interface. Measurements were carried out of external as well as internal interference. We evaluated the influence of both sources of electro-magnetic interference to the noise recorded by pixels. We measured the local spatial intensity distribution and frequency spectrum of the electro-magnetic field originating inside the readout chip during its own operation. In context of this test we exposed the detector chip to a locally generated artificial electro-magnetic field evaluating its sensitivity to induced interference. Consequently, the whole setup of the detector and read-out interface was exposed to a distant source of electro-magnetic radiation, during which we tested efficiency of the electro-magnetic shielding of various arrangements. Further, tests measured the coupling over power supply lines. In particular, the noise generated by the operation of the detector itself was determined. In addition, the detector sensitivity to deliberately induced noise was evaluated. By means of these tests weak points of the setup sensitive to the intrusion of electro-magnetic interference are revealed. When locations of susceptible places are identified proper methods can be applied to increase immunity of the detector setup against the electro-magnetic interference. Experiences gained are planned to be used in development of the EMI shielded version of the FITPIX interface shielded to electro-magnetic interference.

  15. A fast embedded readout system for large-area Medipix and Timepix systems

    Science.gov (United States)

    Brogna, A. S.; Balzer, M.; Smale, S.; Hartmann, J.; Bormann, D.; Hamann, E.; Cecilia, A.; Zuber, M.; Koenig, T.; Zwerger, A.; Weber, M.; Fiederle, M.; Baumbach, T.

    2014-05-01

    In this work we present a novel readout electronics for an X-ray sensor based on a Si crystal bump-bonded to an array of 3 × 2 Medipix ASICs. The pixel size is 55 μm × 55 μm with a total number of ~ 400k pixels and a sensitive area of 42 mm × 28 mm. The readout electronics operate Medipix-2 MXR or Timepix ASICs with a clock speed of 125 MHz. The data acquisition system is centered around an FPGA and each of the six ASICs has a dedicated I/O port for simultaneous data acquisition. The settings of the auxiliary devices (ADCs and DACs) are also processed in the FPGA. Moreover, a high-resolution timer operates the electronic shutter to select the exposure time from 8 ns to several milliseconds. A sophisticated trigger is available in hardware and software to synchronize the acquisition with external electro-mechanical motors. The system includes a diagnostic subsystem to check the sensor temperature and to control the cooling Peltier cells and a programmable high-voltage generator to bias the crystal. A network cable transfers the data, encapsulated into the UDP protocol and streamed at 1 Gb/s. Therefore most notebooks or personal computers are able to process the data and to program the system without a dedicated interface. The data readout software is compatible with the well-known Pixelman 2.x running both on Windows and GNU/Linux. Furthermore the open architecture encourages users to write their own applications. With a low-level interface library which implements all the basic features, a MATLAB or Python script can be implemented for special manipulations of the raw data. In this paper we present selected images taken with a microfocus X-ray tube to demonstrate the capability to collect the data at rates up to 120 fps corresponding to 0.76 Gb/s.

  16. Predicting human gaze beyond pixels.

    Science.gov (United States)

    Xu, Juan; Jiang, Ming; Wang, Shuo; Kankanhalli, Mohan S; Zhao, Qi

    2014-01-28

    A large body of previous models to predict where people look in natural scenes focused on pixel-level image attributes. To bridge the semantic gap between the predictive power of computational saliency models and human behavior, we propose a new saliency architecture that incorporates information at three layers: pixel-level image attributes, object-level attributes, and semantic-level attributes. Object- and semantic-level information is frequently ignored, or only a few sample object categories are discussed where scaling to a large number of object categories is not feasible nor neurally plausible. To address this problem, this work constructs a principled vocabulary of basic attributes to describe object- and semantic-level information thus not restricting to a limited number of object categories. We build a new dataset of 700 images with eye-tracking data of 15 viewers and annotation data of 5,551 segmented objects with fine contours and 12 semantic attributes (publicly available with the paper). Experimental results demonstrate the importance of the object- and semantic-level information in the prediction of visual attention.

  17. Fast single-photon imager acquires 1024 pixels at 100 kframe/s

    Science.gov (United States)

    Guerrieri, Fabrizio; Tisa, Simone; Zappa, Franco

    2009-02-01

    We present the design and we discuss in depth the operating conditions of a two-dimensional (2-D) imaging array of single-photon detectors that provides a total of 1024 pixels, laid out in 32 rows by 32 columns array, integrated within a monolithic silicon chip with dimensions of 3.5 mm x 3.5 mm. We employed a standard high-voltage 0.35μm CMOS fabrication technology, with no need of any custom processing. Each pixel consists of one Single-Photon Avalanche Diode (SPAD) and a compact front-end analog electronics followed by a digital processing circuitry. The in-pixel front-end electronics senses the ignition of the avalanche, quenches the detector, provides a pulse and restores the detector for detecting a subsequent photon. The processing circuitry counts events (both photon and unwelcome "noise" ignition) within user-selectable integration time-slots and stores the count into an in-pixel memory cell, which is read-out in 10 ns/pixel. Such a two-levels pipeline architecture allows to acquire the actual frame while contemporary reading out the previous one, thus achieving a very high free-running frame rate, with negligible inter-frame dead-time. Each pixel is therefore a completely independent photon-counter. The measured Photo Detection Efficiency (PDE) tops 43% at 5V excess-bias, while the Dark-Counting Rate (DCR) is below 4kcps (counts per second) at room temperature. The maximum frame-rate depends on the system clock; with a convenient 100MHz system clock we achieved a free-running speed of 100 kframe/s from the all 1024 pixels.

  18. Evaluation of Polarization Effects of e- Collection Schottky CdTe Medipix3RX Hybrid Pixel Detector

    Science.gov (United States)

    Astromskas, Vytautas; Gimenez, Eva N.; Lohstroh, Annika; Tartoni, Nicola

    2016-02-01

    This paper focuses on the evaluation of operational conditions such as temperature, exposure time and flux on the polarization of a Schottky electron collection CdTe detector. A Schottky e- collection CdTe Medipix3RX hybrid pixel detector was developed as a part of the CALIPSO-HIZPAD2 EU project. The 128 ×128 pixel matrix and 0.75 mm thick CdTe sensor bump-bonded to Medipix3RX readout chips enabled the study of the polarization effects. Single and quad module Medipix3RX chips were used which had 128 ×128 and 256 ×256 pixel matrices, respectively. This study reports the sensor-level and pixel-level polarization effects of the detector obtained from a laboratory X-ray source. We report that the sensor-level polarization is highly dependent on temperature, flux and exposure time. Furthermore, the study of pixel-level polarization effects led to identification of a new type of pixel behaviour that is characterised by three distinct phases and, thus, named “tri-phase” (3-P) pixels. The 3-P pixels were the dominant cause of degradation of the flat-field image uniformity under high flux operation. A new method of identifying the optimum operational conditions that utilises a criterion related to the 3-P pixels is proposed. A generated optimum operational conditions chart under the new method is reported. The criterion is used for bias voltage reset depolarization of the detector. The method successfully represented the dependency of polarization on temperature, flux and exposure time and was reproducible for multiple sensors. Operating the detector under the 3-P pixel criterion resulted in the total efficiency not falling below 95%.

  19. Development of CMOS Pixel Sensors fully adapted to the ILD Vertex Detector Requirements

    CERN Document Server

    Winter, Marc; Besson, Auguste; Claus, Gilles; Dorokhov, Andrei; Goffe, Mathieu; Hu-Guo, Christine; Morel, Frederic; Valin, Isabelle; Voutsinas, Georgios; Zhang, Liang

    2012-01-01

    CMOS Pixel Sensors are making steady progress towards the specifications of the ILD vertex detector. Recent developments are summarised, which show that these devices are close to comply with all major requirements, in particular the read-out speed needed to cope with the beam related background. This achievement is grounded on the double- sided ladder concept, which allows combining signals generated by a single particle in two different sensors, one devoted to spatial resolution and the other to time stamp, both assembled on the same mechanical support. The status of the development is overviewed as well as the plans to finalise it using an advanced CMOS process.

  20. Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

    Science.gov (United States)

    Kawahito, Shoji; Seo, Min-Woong

    2016-01-01

    This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC). The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median): 0.29 e−rms) when compared with the CMS gain of two (2.4 e−rms), or 16 (1.1 e−rms). PMID:27827972

  1. Tests of CMS Hadron Forward Calorimeter Upgrade Readout Box Prototype

    CERN Document Server

    Chatrchyan, Sergey; Sirunyan, Albert; Tumasyan, Armen; Mossolov, Vladimir; Shumeiko, Nikolai; Cornelis, Tom; Ochesanu, Silvia; Roland, Benoit Florent; Staykova, Zlatka; Van Haevermaet, Hans; Van Mechelen, Pierre; Van Spilbeeck, Alex; Alves, Gilvan Augusto; Martins, Thiago Dos Reis; Pol, Maria Elena; Vaz Da Silva Filho, Mario; Alda Junior, Walter Luiz; Carvalho, Wagner De Paula; Chinellato, Jose Augusto; De Oliveira Martins, Carley Pedro; Figueiredo, Diego Matos; Tonelli Manganote, Edmilson Jose; Molina Insfran, Jorge Andres; Mundim, Luiz; Nogima, Helio; Prado Da Silva, Wanda Lucia; Santoro, Alberto; Rosa Lopes Zachi, Alessandro; Finger, Miroslav; Finger, Michael; Tsamalaidze, Zviad; Borras, Kerstin; Gunnellini, Paolo; Jung, Hannes; Knutsson, Albert Hans; Lutz, Benjamin; Ribeiro Cipriano, Pedro Miguel; Sen, Niladri; Baus, Colin; Katkov, Igor; Ulrich, Ralf Matthias; Wohrmann, H; Panagiotou, Apostolos; Bencze, Gyorgy; Horvath, D; Bala, Suman; Gupta, Ruchi; Jindal, M; Lal, Manjit Kaur; Nishu, Nishu; Saini, Lovedeep Kaur; Banerjee, Sunanda; Bhattacharya, S; Gomber, Bhawna; Jain, Shilpi; Khurana, Raman; Sharan, Manoj Kumar; Aziz, Tariq; Maity, Manas; Majumder, Gobinda; Mazumdar, Kajari; Mohanty, Gagan Bihari; Katta, Sudhakar; Banerjee, Sudeshna; Dugad, Shashikant Raichand; Etesami, Seyed Mohsen; Fahim, Ali; Jafari, Abideh; Paktinat Mehdiabadi, Saeid; Zeinali, Maryam; Penzo, Aldo; Afanasyev, A; Bunin, Pavel; Ershov, Yuri; Fedoseev, Oleg; Gavrilenko, Mikhail; Golutvin, Igor; Gorbunov, Ilya; Konoplynikov, V; Malakhov, Alexander; Moisenz, Petr; Smirnov, Vitaly; Volodko, Anton; Zarubin, Anatoly; Andreev, Yuri; Dermenev, Alexander; Krasnikov, Nikolay; Pashenkov, Anatoli; Tlisov, Danila; Toropin, A; Epshteyn, Vladimir; Erofeeva, Maria; Gavrilov, Vladimir; Kosov, Mikhail Vladimirovich; Kudinov, Ilya; Lychkovskaya, Natalia; Popov, V; Safronov, Grigory; Semenov, Sergey; Stolin, Viatcheslav; Vlassov, Evgueni; Zhokin, Alexander; Belyaev, A; Boos, Eduard; Dubinin, Mikhail; Dudko, Lev; Ershov, Alexander; Gribushin, Andrey; Klyukhin, Vyacheslav; Kodolova, Olga; Korotkikh, Vladimir; Lokhtin, Igor; Markina, Anastasia; Obraztsov, Stepan; Perfilov, Maxim; Petrushanko, Sergey; Popov, Andrey; Savrin, Victor; Snigirev, Alexander; Vardanyan, Irina; Andreev, V; Azarkin, Maksim; Dremin, Igor; Kirakosyan, Martin; Leonidov, Andrey; Mesyats, Gennady; Vinogradov, Alexey; Bayshev, Igor; Bityukov, Sergey; Grishin, Viatcheslav; Kryshkin, Victor; Petrov, V; Ryutin, Roman; Sobol, Andrey; Turchanovich, Leonid; Troshin, Sergey; Uzunyan, Andrey; Volkov, Alexey; Santanastasio, Francesco; Adiguzel, Aytul; Bakirci, Numan Mustafa; Cerci, Salim; Dozen, Candan; Dumanoglu, Isa; Eskut, Eda; Girgis, Semiray; G�kbulut, Gul; Gurpinar, Emine; Hos, Ilknur; Kangal, Evrim Ersin; Karapinar, Guler; Kayis Topaksu, Aysel; Onengut, Gulsen; Ozdemir, Kadri; Ozturk, Sertac; Polatoz, Ayse; Sogut, Kenan; Sunar Cerci, Deniz; Tali, Bayram; Topakli, Huseyin; Vergili, Latife Nukhet; Vergili, Mehmet; Aliyev, Takhmasib; Deniz, Muhammed; Guler, Ali Murat; Ozpineci, Altug; Serin, Meltem; Sever, Ramazan; Zeyrek, Mehmet; Deliomeroglu, Mehmet; Gulmez, Erhan; Isildak, Bora; Kaya, Mithat; Kaya, Ozlem; Ozkorucuklu, Suat; Sonmez, Nasuf; Cankocak, Kerem; Levchuk, Leonid; Hatakeyama, Kenichi; Liu, H; Scarborough, Tara Ann; Rumerio, Paolo; Heister, Arno; Hill, C; Lawson, Philip Daniel; Lazic, Dragoslav; Rohlf, James; St. John, Jason; Sulak, Lawrence; Gennadiy, G; Laird, Edward; Landsberg, Greg; Narain, Meenakshi; Sinthuprasith, Tutanon; Tsang, Ka Vang; Long, Owen Rosser; Nguyen, Harold; Paramesvaran, Sudarshan; Sturdy, Jared; Stuart, David; To, Wing; West, Christopher Alan; Apresyan, Artur; Chen, Y; Mott, Alexander Robert; Spiropulu, Maria; Winn, David; Abdoulline, Salavat; Anderson, J; Chlebana, Frank; Freeman, James; Green, Daniel; Hanlon, J; Hirschauer, James Francis; Joshi, Umeshwar; Kunori, Shuichi; Musienko, Yuri; Sharma, Seema; Spalding, William Jeffrey; Tkaczyk, Slawomir; Vidal, Richard; Whitmore, Juliana; Wu, W; Gaultney, Vanessa; Linn, Stephan; Markowitz, Pete Edward; Martinez, German Ruben; Gleyzer, Sergei; Hagopian, Sharon Lee; Hagopian, Vasken; Jenkins, Charles Merrill; Baarmand, Marc M; Dorney, Brian L; Vodopiyanov, Igor; Akgun, Ugur; Albayrak, Elif Asli; Bilki, Burak; Clarida, Warren James; Duru, Firdevs; Merlo, Jean-Pierre; Mermerkaya, Hamit; Mestvirishvili, Alexi; Moeller, Anthony Richard; Nachtman, Jane; Newsom, Charles Ray; Norbeck, John Edwin; Olson, Jonathan Edward; Onel, Yasar; Ozok, Ferhat; Sen, Sercan; Schmidt, Ianos; Tiras, Emrah; Yetkin, Taylan; Yi, Kai; Kenny, Raymond Patrick; Murray, Michael Joseph; Wood, Jeffrey Scott; Baden, Andrew; Calvert, Brian Michael; Eno, Sarah Catherine; Gomez, Jaime Arturo; Grassi, Tullio; Hadley, Nicholas John; Kellogg, Richard; Kolberg, Ted; Lu, Y; Marionneau, Matthieu; Mignerey, Alice Louise Cox; Peterman, Alison Marie; Skuja, Andris; Temple, Jeffrey; Tonjes, Marguerite Belt; Kao, Shih-Chuan; Klapoetke, Kevin Humphrey; Mans, Jeremiah Michael; Pastika, Nathaniel Joseph; Kroeger, Robert; Rahmat, Rahmat; Sanders, David; Cremaldi, Lucien Marcus; Jain, S; Anastassov, Anton; Velasco, Mayda Marie; Won, Steven; Heering, Adriaan; Karmgard, Daniel; Pearson, Tessa Jae; Ruchti, Randal; Berry, Edmund A; Halyo, Valerie; Hebda, Philip; Hunt, Adam Paul; Lujan, Paul Joseph; Marlow, Daniel; Medvedeva, Tatiana; Saka, Halil; Tully, Christopher; Zuranski, Andrzej Maciej; Barnes, Virgil Everett; Laasanen, Alvin; Bodek, Arie; Chung, Yeon Sei; de Barbaro, Pawel Jan; Eshaq, Yossof; Garcia-bellido, Aran Angel; Goldenzweig, Pablo David; Han, Ji Yeon; Harel, Amnon; Miner, Daniel Carl; Vishnevskiy, Dmitry; Zielinski, Marek; Bhatti, Anwar; Ciesielski, Robert Adam; Flanagan, Will Hogan; Kamon, Teruki; Montalvo, Roy Joaquin; Sakuma, Tai; Akchurin, Nural; Damgov, Jordan; Dudero, Phillip Russell; Kovitanggoon, Kittikul; Lee, Sung Won; Libeiro, Terence; Volobouev, Igor; Gurrola, Alfredo; Milstene, Caroline

    2012-01-01

    A readout box prototype for CMS Hadron Forward calorimeter upgrade is built and tested in CERN H2 beamline. The prototype is designed to enable simultaneous tests of different readout options for the four anode upgrade PMTs, new front-end electronics design and new cabling. The response of the PMTs with different readout options is uniform and the background response is minimal. Multi-channel readout options further enhance the background elimination. Passing all the electronics, mechanical and physics tests, the readout box proves to be capable of providing the forward hadron calorimeter operations requirements in the upgrade era.

  2. Development of a multiplexed readout with high position resolution for positron emission tomography

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Sangwon; Choi, Yong [Molecular Imaging Research & Education (MiRe) Laboratory, Department of Electronic Engineering, Sogang University, Seoul 04107 (Korea, Republic of); Kang, Jihoon [Department of Biomedical Engineering, Chonnam National University, Yeosu 550-749 (Korea, Republic of); Jung, Jin Ho [Molecular Imaging Research & Education (MiRe) Laboratory, Department of Electronic Engineering, Sogang University, Seoul 04107 (Korea, Republic of)

    2017-04-01

    Detector signals for positron emission tomography (PET) are commonly multiplexed to reduce the number of digital processing channels so that the system can remain cost effective while also maintaining imaging performance. In this work, a multiplexed readout combining Anger position estimation algorithm and position decoder circuit (PDC) was developed to reduce the number of readout channels by a factor of 24, 96-to-4. The data acquisition module consisted of a TDC (50 ps resolution), 4-channel ADCs (12 bit, 105 MHz sampling rate), 2 GB SDRAM and USB3.0. The performance of the multiplexed readout was assessed with a high-resolution PET detector block composed of 2×3 detector modules, each consisting of an 8×8 array of 1.52×1.52×6 mm{sup 3} LYSO, a 4×4 array of 3×3 mm{sup 2} silicon photomultiplier (SiPM) and 13.4×13.4 mm{sup 2} light guide with 0.7 mm thickness. The acquired flood histogram showed that all 384 crystals could be resolved. The average energy resolution at 511 keV was 13.7±1.6% full-width-at-half-maximum (FWHM) and the peak-to-valley ratios of the flood histogram on the horizontal and vertical lines were 18.8±0.8 and 22.8±1.3, respectively. The coincidence resolving time of a pair of detector blocks was 6.2 ns FWHM. The reconstructed phantom image showed that rods down to a diameter of 1.6 mm could be resolved. The results of this study indicate that the multiplexed readout would be useful in developing a PET with a spatial resolution less than the pixel size of the photosensor, such as a SiPM array.

  3. DEPFET active pixel detectors for a future linear $e^+e^-$ collider

    CERN Document Server

    Alonso, O; Dieguez, A; Dingfelder, J; Hemperek, T; Kishishita, T; Kleinohl, T; Koch, M; Krueger, H; Lemarenko, M; Luetticke, F; Marinas, C; Schnell, M; Wermes, N; Campbell, A; Ferber, T; Kleinwort, C; Niebuhr, C; Soloviev, Y; Steder, M; Volkenborn, R; Yaschenko, S; Fischer, P; Kreidl, C; Peric, I; Knopf, J; Ritzert, M; Curras, E; Lopez-Virto, A; Moya, D; Vila, I; Boronat, M; Esperante, D; Fuster, J; Garcia Garcia, I; Lacasta, C; Oyanguren, A; Ruiz, P; Timon, G; Vos, M; Gessler, T; Kuehn, W; Lange, S; Muenchow, D; Spruck, B; Frey, A; Geisler, C; Schwenker, B; Wilk, F; Barvich, T; Heck, M; Heindl, S; Lutz, O; Mueller, Th; Pulvermacher, C; Simonis, H.J; Weiler, T; Krausser, T; Lipsky, O; Rummel, S; Schieck, J; Schlueter, T; Ackermann, K; Andricek, L; Chekelian, V; Chobanova, V; Dalseno, J; Kiesling, C; Koffmane, C; Gioi, L.Li; Moll, A; Moser, H.G; Mueller, F; Nedelkovska, E; Ninkovic, J; Petrovics, S; Prothmann, K; Richter, R; Ritter, A; Ritter, M; Simon, F; Vanhoefer, P; Wassatsch, A; Dolezal, Z; Drasal, Z; Kodys, P; Kvasnicka, P; Scheirich, J

    2013-01-01

    The DEPFET collaboration develops highly granular, ultra-transparent active pixel detectors for high-performance vertex reconstruction at future collider experiments. The characterization of detector prototypes has proven that the key principle, the integration of a first amplification stage in a detector-grade sensor material, can provide a comfortable signal to noise ratio of over 40 for a sensor thickness of 50-75 $\\mathrm{\\mathbf{\\mu m}}$. ASICs have been designed and produced to operate a DEPFET pixel detector with the required read-out speed. A complete detector concept is being developed, including solutions for mechanical support, cooling and services. In this paper the status of DEPFET R & D project is reviewed in the light of the requirements of the vertex detector at a future linear $\\mathbf{e^+ e^-}$ collider.

  4. Characterisation of the NA62 GigaTracker End of Column Demonstrator Hybrid Pixel Detector

    Science.gov (United States)

    Noy, M.; Aglieri Rinella, G.; Cotta Ramusino, A.; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Perktold, L.; Poltorak, K.; Riedler, P.

    2011-11-01

    The architecture and characterisation of the NA62 GigaTracker End of Column Demonstrator Hybrid Pixel Detector (HPD) are presented. This detector must perform time stamping to 200 ps (RMS) or better, provide 300 μm pitch position information and operate with a dead time of 1% or less for 800 MHz-1 GHz beam rate. The demonstrator HPD Assembly comprises a readout chip with a test column of 45 pixels, alongside other test structures, bump bonded to a p-in-n detector 200 μm in thickness. Validation of the performance of the HPD and the time-over-threshold timewalk compensation mechanism with both beam particles and a high precision laser system was performed and is presented. Confirmation of better than the required time stamping precision has been demonstrated and subsequent work on the design of the full-scale ASIC, dubbed TDCPix, is underway. An overview of the TDCPix architecure is given.

  5. Characterization of proton irradiated 3D-DDTC pixel sensor prototypes fabricated at FBK

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, A., E-mail: alessandro.larosa@cern.ch [CERN, Geneva 23, CH-1211 (Switzerland); Boscardin, M. [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy); Cobal, M. [Universita degli Studi di Udine and INFN Trieste, Gruppo Collegato di Udine, Via delle Scienze 208, I-33100 Udine (Italy); Dalla Betta, G.-F. [DISI, Universita degli Studi di Trento and INFN Padova, Gruppo Collegato d Trento, Via Sommarive 14, I-38123 Trento (Italy); Da Via, C. [School of Physics and Astronomy, University of Manchester, Oxford Road, Manchester M13 9PL (United Kingdom); Darbo, G. [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Gallrapp, C. [CERN, Geneva 23, CH-1211 (Switzerland); Gemme, C. [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Huegging, F.; Janssen, J. [Physikalisches Institut, Universitaet Bonn, Nussallee 12, D-53115 Bonn (Germany); Micelli, A. [Universita degli Studi di Udine and INFN Trieste, Gruppo Collegato di Udine, Via delle Scienze 208, I-33100 Udine (Italy); Pernegger, H. [CERN, Geneva 23, CH-1211 (Switzerland); Povoli, M. [DISI, Universita degli Studi di Trento and INFN Padova, Gruppo Collegato d Trento, Via Sommarive 14, I-38123 Trento (Italy); Wermes, N. [Physikalisches Institut, Universitaet Bonn, Nussallee 12, D-53115 Bonn (Germany); Zorzi, N. [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy)

    2012-07-21

    In this paper we discuss results relevant to 3D Double-Side Double Type Column (3D-DDTC) pixel sensors fabricated at FBK (Trento, Italy) and oriented to the ATLAS upgrade. Some assemblies of these sensors featuring different columnar electrode configurations (2, 3, or 4 columns per pixel) and coupled to the ATLAS FEI3 read-out chip were irradiated up to large proton fluences and tested in laboratory with radioactive sources. In spite of the non-optimized columnar electrode overlap, sensors exhibit reasonably good charge collection properties up to an irradiation fluence of 2 Multiplication-Sign 10{sup 15}n{sub eq}cm{sup -2}, while requiring bias voltages in the order of 100 V. Sensor operation is further investigated by means of TCAD simulations which can effectively explain the basic mechanisms responsible for charge loss after irradiation.

  6. Development of 3D-DDTC pixel detectors for the ATLAS upgrade

    International Nuclear Information System (INIS)

    Dalla Betta, Gian-Franco; Boscardin, Maurizio; Darbo, Giovanni; Gemme, Claudia; La Rosa, Alessandro; Pernegger, Heinz; Piemonte, Claudio; Povoli, Marco; Ronchin, Sabina; Zoboli, Andrea; Zorzi, Nicola

    2011-01-01

    We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrical and functional characterization with radioactive sources are discussed here.

  7. Development of 3D-DDTC pixel detectors for the ATLAS upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Dalla Betta, Gian-Franco, E-mail: dallabe@disi.unitn.it [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Boscardin, Maurizio [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Darbo, Giovanni; Gemme, Claudia [INFN, Sezione di Genova, Via Dodecaneso 33, 16146 Genova (Italy); La Rosa, Alessandro; Pernegger, Heinz [CERN-PH, CH-1211 Geneve 23 (Switzerland); Piemonte, Claudio [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Povoli, Marco [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Ronchin, Sabina [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Zoboli, Andrea [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Zorzi, Nicola [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy)

    2011-04-21

    We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrical and functional characterization with radioactive sources are discussed here.

  8. A Medipix2-based imaging system for digital mammography with silicon pixel detectors

    CERN Document Server

    Bisogni, M G; Fantacci, M E; Mettivier, G; Montesi, M C; Novelli, M; Quattrocchi, M; Rosso, V; Russo, P; Stefanini, A

    2004-01-01

    In this paper we present the first tests of a digital imaging system based on a silicon pixel detector bump-bonded to an integrated circuit operating in single photon counting mode. The X-rays sensor is a 300 mu m thick silicon, 14 by 14 mm/sup 2/, upon which a matrix of 256 * 256 pixels has been built. The read-out chip, named MEDIPIX2, has been developed at CERN within the MEDIPIX2 Collaboration and it is composed by a matrix of 256 * 256 cells, 55 * 55 mu m/sup 2/. The spatial resolution properties of the system have been assessed by measuring the square wave resolution function (SWRF) and first images of a standard mammographic phantom were acquired using a radiographic tube in the clinical irradiation condition. (5 refs).

  9. DEPFET: A silicon pixel detector for future colliders. Fundamentals, characterization and performance

    CERN Document Server

    Marinas Pardo, Carlos Manuel; Vos, Marcel Andre

    2011-01-01

    The future electron-positron colliders, either breaking the energy frontier (like ILC or CLIC) or the luminosity frontier (SuperKEKB), impose unprecedented constraints over the new generation of detectors that will be operated in those facilities. In particular, the vertex detectors must be designed for an efficient flavour tagging and excellent vertex reconstruction. To cope with these requirements, highly pixelated sensors with a fast readout, very low material budget and low power consumption must be developed. Although the combination of these factors is a substantial challenge, the DEPFET Collaboration has developed a new generation of sensors that can be operated in such a harsh environment. The DEpleted P-channel Field Effect Transistor (DEPFET) is a pixel sensor that combines detection and internal amplification at the same time. With such configuration, thin detectors with good signal-to-noise ratio and low power consumption can be produced. In this thesis, the optimization and performance of two gen...

  10. A new concept of monolithic silicon pixel detectors Hydrogenated amorphous silicon on ASIC

    CERN Document Server

    Anelli, G; Despeisse, M; Dissertori, G; Jarron, P; Miazza, C; Moraes, D; Shah, A; Viertel, Gert M; Wyrsch, N

    2004-01-01

    A new concept of a monolithic pixel radiation detector is presented. It is based on the deposition of a film of hydrogenated amorphous silicon (a-Si:H) on an Application Specific Integrated Circuit (ASIC) . For almost 20 years, several research groups tried to demonstrate that a-Si:H material could be used to build radiation detectors for particle physics applications. A novel approach is made by the deposition of a-Si:H directly on the readout ASIC. This technique is similar to the concept of monolithic pixel detectors, but offers considerable advantages. We present first results from tests of a n- i-p a-Si:H diode array deposited on a glass substrate and on the a- Si:H above ASIC prototype detector.

  11. CMS pixel module qualification and Monte-Carlo study of $H \\to \\tau^{+}\\tau^{-} \\to l^{+}l^{-}ET$

    CERN Document Server

    Trüb, Peter; Pauss, F

    2008-01-01

    The first part of this work reports on the development of test and calibration algorithms for the qualification of the barrel modules of the CMS pixel detector. Several algorithms to test the hardware functionality and performance have been developed and implemented into an object-oriented software framework. Examples are the pixel readout test, the bump bonding test or the noise measurement. The qualification procedure also includes calibration routines. For instance the gain of each pixel or the temperature sensors of the readout chips have to be calibrated. Furthermore, an algorithm to unify the thresholds of all pixels was developed. According to specific quality criteria, each module is graded into one of three categories. Out of 981 tested modules, 806 were qualified for the usage in the detector. The second part of this work deals with a Monte-Carlo study of the Higgs decay channel $H\\to \\tau^{+}\\tau^{-} \\to l^{+}l^{-}Et$ with a jet balancing the large transverse momentum of the Higgs boson. In contras...

  12. Tests of small X-ray Active Matrix Pixel Sensor prototypes at the National Synchrotron Light Source

    Science.gov (United States)

    Carini, G. A.; Chen, W.; Dragone, A.; Fried, J.; Jakoncic, J.; Kuczweski, A.; Li, Z.; Mead, J.; Michta, R.; Pratte, J.-F.; Rehak, P.; Siddons, D. P.

    2009-03-01

    X-ray Active Matrix Pixel Sensors (XAMPS) were designed and fabricated at Brookhaven National Laboratory. Devices based on J-FET technology were produced on 100 mm high-resistivity silicon, typically 400 μm-thick. The prototypes are square matrices with n rows and n columns with n = 16, 32, 64, 128, 256, 512. Each pixel of the matrix is 90 × 90 μm2 and contains a JFET switch to control the charge readout. The XAMPS is a position sensitive ionization detector made on high resistivity silicon. It consists of a pixel array detector with integrated switches. Pixels are isolated from each other by a potential barrier and the device is fully depleted by applying a high voltage bias to the junction on the entrance window of the sensor. The small features of the design presented some technological challenges fully addressed during this production. The first prototypes were tested at the National Synchrotron Light Source (NSLS) with a monochromatic beam of 8 keV and millisecond readout and exhibit good performances at room temperature.

  13. Tests of small X-ray Active Matrix Pixel Sensor prototypes at the National Synchrotron Light Source

    Energy Technology Data Exchange (ETDEWEB)

    Carini, G A; Chen, W; Fried, J; Jakoncic, J; Kuczweski, A; Li, Z; Mead, J; Michta, R; Pratte, J-F; Rehak, P; Siddons, D P [Brookhaven National Laboratory, Upton, 11973 NY (United States); Dragone, A [SLAC National Accelerator Center, Menlo Park, 94025 CA (United States)], E-mail: carini@bnl.gov

    2009-03-15

    X-ray Active Matrix Pixel Sensors (XAMPS) were designed and fabricated at Brookhaven National Laboratory. Devices based on J-FET technology were produced on 100 mm high-resistivity silicon, typically 400 {mu}m-thick. The prototypes are square matrices with n rows and n columns with n = 16, 32, 64, 128, 256, 512. Each pixel of the matrix is 90 x 90 {mu}m{sup 2} and contains a JFET switch to control the charge readout. The XAMPS is a position sensitive ionization detector made on high resistivity silicon. It consists of a pixel array detector with integrated switches. Pixels are isolated from each other by a potential barrier and the device is fully depleted by applying a high voltage bias to the junction on the entrance window of the sensor. The small features of the design presented some technological challenges fully addressed during this production. The first prototypes were tested at the National Synchrotron Light Source (NSLS) with a monochromatic beam of 8 keV and millisecond readout and exhibit good performances at room temperature.

  14. R and D on monolithic active pixel sensors (MAPS): Towards large-area CMOS sensors for particle physics

    International Nuclear Information System (INIS)

    Allport, P.P.; Bates, R.; Casse, G.; Crooks, J.; Evans, A.; Jones, L.; O'Shea, V.; Turchetta, R.; Tyndel, M.; Velthuis, J.J.; Villani, G.; Zakopoulos, F.

    2007-01-01

    We are developing CMOS Monolithic Active Pixel Sensors for particle physics. A family of sensors, RAL H EPAPS, has been developed. The first three sensors of this family were parametric test sensors, on which different types of pixel architectures were integrated. These sensors were designed, manufactured and tested and recent results obtained by our collaboration will be briefly reviewed. The latest sensor in the family, RAL H EPAPS4, is the first step towards a large-area sensor as required for particle physics. It has 1026x384 pixels with a pixel pitch of 15 μm, for a total sensing area of 15.39x5.76 mm 2 . The line rate can be in excess of 5 MHz, which, for column parallel readout, would yield an equivalent 76 μs full frame readout time. Three different versions of the RAL H EPAPS4 were produced, with the same global architecture but with different diode structures. The design and simulated performances will be reviewed

  15. High-QE fast-readout wavefront sensor with analog phase reconstruction

    Science.gov (United States)

    Baker, Jeffrey T.; Loos, Gary C.; Restaino, Sergio R.; Percheron, Isabelle; Finkner, Lyle G.

    1998-09-01

    The contradiction inherent in high temporal bandwidth adaptive optics wavefront sensing at low-light-levels (LLL) has driven many researchers to consider the use of high bandwidth high quantum efficiency (QE) CCD cameras with the lowest possible readout noise levels. Unfortunately, the performance of these relatively expensive and low production volume devices in the photon counting regime is inevitably limited by readout noise, no matter how arbitrarily close to zero that specification may be reduced. Our alternative approach is to optically couple a new and relatively inexpensive Ultra Blue Gen III image intensifier to an also relatively inexpensive high bandwidth CCD camera with only moderate QE and high rad noise. The result is a high bandwidth broad spectral response image intensifier with a gain of 55,000 at 560 nm. Use of an appropriately selected lenslet array together with coupling optics generates 16 X 16 Shack-Hartmann type subapertures on the image intensifier photocathode, which is imaged onto the fast CCD camera. An integral A/D converter in the camera sends the image data pixel by pixel to a computer data acquisition system for analysis, storage and display. Timing signals are used to decode which pixel is being rad out and the wavefront is calculated in an analog fashion using a least square fit to both x and y tilt data for all wavefront sensor subapertures. Finally, we present system level performance comparisons of these new concept wavefront sensors versus the more standard low noise CCD camera based designs in the low-light-level limit.

  16. STAR PIXEL detector mechanical design

    International Nuclear Information System (INIS)

    Wieman, H H; Anderssen, E; Greiner, L; Matis, H S; Ritter, H G; Sun, X; Szelezniak, M

    2009-01-01

    A high resolution pixel detector is being designed for the STAR [1] experiment at RHIC. This device will use MAPS as the detector element and will have a pointing accuracy of ∼25 microns. We will be reporting on the mechanical design required to support this resolution. The radiation length of the first layer (∼0.3% X 0 ) and its distance from the interaction point (2.5 cm) determines the resolution. The design makes use of air cooling and thin carbon composite structures to limit the radiation length. The mechanics are being developed to achieve spatial calibrations and stability to 20 microns and to permit rapid detector replacement in event of radiation damage or other potential failures from operation near the beam.

  17. FROM IMAGE CONTOURS TO PIXELS

    Directory of Open Access Journals (Sweden)

    G. Scarmana

    2012-07-01

    Full Text Available This paper relates to the reconstruction of digital images using their contour representations. The process involves determining the pixel intensity value which would exist at the intersections of a regular grid using the nodes of randomly spaced contour locations. The reconstruction of digital images from their contour maps may also be used as a tool for image compression. This reconstruction process may provide for more accurate results and improved visual details than existing compressed versions of the same image, while requiring similar memory space for storage and speed of transmission over digital links. For the class of images investigated in this work, the contour approach to image reconstruction and compression requires contour data to be filtered and eliminated from the reconstruction process. Statistical tests which validate the proposed process conclude this paper.

  18. Dead pixel replacement in LWIR microgrid polarimeters.

    Science.gov (United States)

    Ratliff, Bradley M; Tyo, J Scott; Boger, James K; Black, Wiley T; Bowers, David L; Fetrow, Matthew P

    2007-06-11

    LWIR imaging arrays are often affected by nonresponsive pixels, or "dead pixels." These dead pixels can severely degrade the quality of imagery and often have to be replaced before subsequent image processing and display of the imagery data. For LWIR arrays that are integrated with arrays of micropolarizers, the problem of dead pixels is amplified. Conventional dead pixel replacement (DPR) strategies cannot be employed since neighboring pixels are of different polarizations. In this paper we present two DPR schemes. The first is a modified nearest-neighbor replacement method. The second is a method based on redundancy in the polarization measurements.We find that the redundancy-based DPR scheme provides an order-of-magnitude better performance for typical LWIR polarimetric data.

  19. Development of pixellated Ir-TESs

    International Nuclear Information System (INIS)

    Zen, Nobuyuki; Takahashi, Hiroyuki; Kunieda, Yuichi; Dayanthi, Rathnayaka M.T.; Mori, Fumiakira; Fujita, Kaoru; Nakazawa, Masaharu; Fukuda, Daiji; Ohkubo, Masataka

    2006-01-01

    We have been developing Ir-based pixellated superconducting transition edge sensors (TESs). In the area of material or astronomical applications, the sensor with few eV energy resolution and over 1000 pixels imaging property is desired. In order to achieve this goal, we have been analyzing signals from pixellated TESs. In the case of a 20 pixel array of Ir-TESs, with 45 μmx45 μm pixel sizes, the incident X-ray signals have been classified into 16 groups. We have applied numerical signal analysis. On the one hand, the energy resolution of our pixellated TES is strongly degraded. However, using pulse shape analysis, we can dramatically improve the resolution. Thus, we consider that the pulse signal analysis will lead this device to be used as a practical photon incident position identifying TES

  20. LYSO crystal calorimeter readout with silicon photomultipliers

    Energy Technology Data Exchange (ETDEWEB)

    Berra, A., E-mail: alessandro.berra@gmail.com [Università degli Studi dell' Insubria (Italy); INFN sezione di Milano Bicocca (Italy); Bonvicini, V. [INFN sezione di Trieste (Italy); Cecchi, C.; Germani, S. [INFN sezione di Perugia (Italy); Guffanti, D. [Università degli Studi dell' Insubria (Italy); Lietti, D. [Università degli Studi dell' Insubria (Italy); INFN sezione di Milano Bicocca (Italy); Lubrano, P.; Manoni, E. [INFN sezione di Perugia (Italy); Prest, M. [Università degli Studi dell' Insubria (Italy); INFN sezione di Milano Bicocca (Italy); Rossi, A. [INFN sezione di Perugia (Italy); Vallazza, E. [INFN sezione di Trieste (Italy)

    2014-11-01

    Large area Silicon PhotoMultipliers (SiPMs) are the new frontier of the development of readout systems for scintillating detectors. A SiPM consists of a matrix of parallel-connected silicon micropixels operating in limited Geiger–Muller avalanche mode, and thus working as independent photon counters with a very high gain (∼10{sup 6}). This contribution presents the performance in terms of linearity and energy resolution of an electromagnetic homogeneous calorimeter composed of 9∼18X{sub 0} LYSO crystals. The crystals were readout by 36 4×4 mm{sup 2} SiPMs (4 for each crystal) produced by FBK-irst. This calorimeter was tested at the Beam Test Facility at the INFN laboratories in Frascati with a single- and multi-particle electron beam in the 100–500 MeV energy range.

  1. Detector Readout of Analog Quantum Simulators

    Science.gov (United States)

    Schwenk, Iris; Tian, Lin; Marthaler, Michael

    An important step in quantum simulation is to measure the many-body correlations of the simulated model. For a practical quantum simulator composed of a finite number of qubits and cavities, in contrast to many-body systems in the thermodynamic limit, a measurement device can generate strong backaction on the simulator, which could prevent the accurate readout of the correlation functions. Here we calculate the readout of a detector coupled to analog quantum simulators. We show that reliable characterization of the many-body correlations of the simulators can be achieved when the coupling operators obey the Wick's theorem. Our results are illustrated with two examples: a simulator for an harmonic oscillator and a simulator for the free electron gas. We also present a method, which under certain constraints, allows for the reconstruction of the ideal correlators from the measurements on a perturbed quantum simulator. This work is in part supported by the National Science Foundation under Award Number 0956064.

  2. Slim edge studies, design and quality control of planar ATLAS IBL pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Wittig, Tobias

    2013-05-08

    One of the four large experiments at the LHC at CERN is the ATLAS detector, a multi purpose detector. Its pixel detector, composed of three layers, is the innermost part of the tracker. As it is closest to the interaction point, it represents a basic part of the track reconstruction. Besides the requested high resolution one main requirement is the radiation hardness. In the coming years the radiation damage will cause deteriorations of the detector performance. With the planned increase of the luminosity, especially after the upgrade to the High Luminosity LHC, this radiation damage will be even intensified. This circumstance necessitates a new pixel detector featuring improved radiation hard sensors and read-out chips. The present shutdown of the LHC is already utilized to insert an additional b-layer (IBL) into the existing ATLAS pixel detector. The current n-in-n pixel sensor design had to be adapted to the new read-out chip and the module specifications. The new stave geometry requests a reduction of the inactive sensor edge. In a prototype wafer production all modifications have been implemented. The sensor quality control was supervised which led to the decision of the final sensor thickness. In order to evaluate the performance of the sensor chip assemblies with an innovative slim edge design, they have been operated in test beam setups before and after irradiation. Furthermore, the quality control of the planar IBL sensor wafer production was supervised from the stage of wafer delivery to that before the flip chip process to ensure a sufficient amount of functional sensors for the module production.

  3. Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

    Science.gov (United States)

    Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

    2013-09-01

    A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

  4. The pipelined readout for the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Hervas, L.

    1991-01-01

    The electron-proton storage ring complex HERA under construction at DESY in Hamburg is the first machine of a new generation of colliders. Since physics to be studied at HERA (covered in chapter 2) base on the precise measurement of kinematic variables over a very large range of energies, a foremost emphasis is set in calorimetry. After long studies and an ambitious test program, the ZEUS collaboration has built a high resolution depleted uranium-scintillator calorimeter with photomultiplier readout, the state of the art in detectors of this type. In chapter 3 the principles of calorimetry are reviewed and the construction of the ZEUS calorimeter is described. Mainly due to the large dynamic range and the short bunch crossing times a novel concept for the readout in an analog pipelined fashion had to be designed. This concept is explained in chapter 4. The solid state implementation of the pipeline required two integrated circuits which were developed specially for the ZEUS calorimeter in collaboration with an electronics research institute and produced by industry. The design and construction of these devices and the detailed testing which has been performed for properties critical in the readout is covered in chapters 5 and 6. The whole pipelined readout is a complicated setup with many steps and collaborating systems. Its implementation and the information to operate it are covered in chapter 7. Finally the concepts presented and the applications discussed have been installed and tested on a test beam calibration experiment. There, the modules of the calorimeter have been calibrated. Chapter 8 presents results from these measurements which show excellent performance of the electronics as well as optimal properties of the calorimeter modules. (orig./HSI)

  5. LSST camera readout chip ASPIC: test tools

    Science.gov (United States)

    Antilogus, P.; Bailly, Ph; Jeglot, J.; Juramy, C.; Lebbolo, H.; Martin, D.; Moniez, M.; Tocut, V.; Wicek, F.

    2012-02-01

    The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

  6. Performance of MSGC with analog pipeline readout

    Energy Technology Data Exchange (ETDEWEB)

    Gomez, F. [Universidad de Santiago de Compostela (Spain); Adeva, B. [Universidad de Santiago de Compostela (Spain); Gracia, G. [Universidad de Santiago de Compostela (Spain); Lopez, M.A. [Universidad de Santiago de Compostela (Spain); Nunez, T. [Universidad de Santiago de Compostela (Spain); Pazos, A. [Universidad de Santiago de Compostela (Spain); Plo, M. [Universidad de Santiago de Compostela (Spain); Rodriguez, A. [Universidad de Santiago de Compostela (Spain); Santamarina, C. [Universidad de Santiago de Compostela (Spain); Vazquez, P. [Universidad de Santiago de Compostela (Spain)

    1997-01-01

    We analyse some of the performance characteristics of a chromium MSGC operated with Ar-DME 50%-50% in a test beam at CERN. Excellent signal-to-noise ratio and efficiency has been achieved with this gas mixture using cathode analog pipeline readout. We also determine optimal parameters for the sampling algorithm in order to work in a random trigger experiment (fixed target). (orig.).

  7. Performance of MSGC with analog pipeline readout

    International Nuclear Information System (INIS)

    Gomez, F.; Adeva, B.; Gracia, G.; Lopez, M.A.; Nunez, T.; Pazos, A.; Plo, M.; Rodriguez, A.; Santamarina, C.; Vazquez, P.

    1997-01-01

    We analyse some of the performance characteristics of a chromium MSGC operated with Ar-DME 50%-50% in a test beam at CERN. Excellent signal-to-noise ratio and efficiency has been achieved with this gas mixture using cathode analog pipeline readout. We also determine optimal parameters for the sampling algorithm in order to work in a random trigger experiment (fixed target). (orig.)

  8. Signal processing for distributed readout using TESs

    International Nuclear Information System (INIS)

    Smith, Stephen J.; Whitford, Chris H.; Fraser, George W.

    2006-01-01

    We describe optimal filtering algorithms for determining energy and position resolution in position-sensitive Transition Edge Sensor (TES) Distributed Read-Out Imaging Devices (DROIDs). Improved algorithms, developed using a small-signal finite-element model, are based on least-squares minimisation of the total noise power in the correlated dual TES DROID. Through numerical simulations we show that significant improvements in energy and position resolution are theoretically possible over existing methods

  9. Towards wireless data readout of particle detectors

    Energy Technology Data Exchange (ETDEWEB)

    Dittmeier, Sebastian; Schoening, Andre; Wiedner, Dirk; Berger, Niklaus; Petersen, Jens; Hugle, Thomas [Physikalisches Institut, Universitaet Heidelberg (Germany)

    2013-07-01

    Today's high energy physics experiments produce large amounts of data in a short time. The fast readout of this data is a big challenge. The license-free 60 GHz band allows for short distance applications with high data rates of the order of several Gb/s. The transceivers can be produced in SiGe HBT BiCMOS technology. As we are dealing with mm-waves, even antennas, which increase the directivity of the transmission, can be built in small structures. So, this technique seems very promising for the readout of particle detectors. For example, it can be used for the readout of the upgraded ATLAS silicon micro-strip tracker and make a first level track trigger feasible. We present first results of our tests with semi-commercially available 60 GHz transceivers regarding the usage in a high energy physics experiment. We examined the intensity of the carrier signal regarding reflectivity and absorption using graphite foam. Moreover, we tested the directivity of a horn antenna made from Kapton. We furthermore investigated the quality of a modulated signal with respect to bit errors using pseudo-random data as well as real data files.

  10. Embedded controller for GEM detector readout system

    Science.gov (United States)

    Zabołotny, Wojciech M.; Byszuk, Adrian; Chernyshova, Maryna; Cieszewski, Radosław; Czarski, Tomasz; Dominik, Wojciech; Jakubowska, Katarzyna L.; Kasprowicz, Grzegorz; Poźniak, Krzysztof; Rzadkiewicz, Jacek; Scholz, Marek

    2013-10-01

    This paper describes the embedded controller used for the multichannel readout system for the GEM detector. The controller is based on the embedded Mini ITX mainboard, running the GNU/Linux operating system. The controller offers two interfaces to communicate with the FPGA based readout system. FPGA configuration and diagnostics is controlled via low speed USB based interface, while high-speed setup of the readout parameters and reception of the measured data is handled by the PCI Express (PCIe) interface. Hardware access is synchronized by the dedicated server written in C. Multiple clients may connect to this server via TCP/IP network, and different priority is assigned to individual clients. Specialized protocols have been implemented both for low level access on register level and for high level access with transfer of structured data with "msgpack" protocol. High level functionalities have been split between multiple TCP/IP servers for parallel operation. Status of the system may be checked, and basic maintenance may be performed via web interface, while the expert access is possible via SSH server. System was designed with reliability and flexibility in mind.

  11. GOSSIPO-4: Evaluation of a Novel PLL-Based TDC-Technique for the Readout of GridPix-Detectors

    CERN Document Server

    Brezina, C; Zappon, F; Van Beuzekom, M; Campbell, M; Desch, K; Van der Graaf, H; Gromov, V; Kluit, R; Llopart, X; Poikela, T; Zivkovic, V

    2014-01-01

    The direct readout of Micro-Pattern Gaseous Detectors (MPGDs) with bare pixel chips introduces the need for a new generation of readout electronics featuring a high spatial granularity as well as a highly accurate time measurement in each pixel. GOSSIPO-4, fabricated in a 130 nm CMOS technology, is a demonstrator ASIC investigating the potential of a new TDC-concept that is based on a chip-wide 40 MHz clock which is complemented by an additional 640 MHz clock. The latter is created upon demand by local oscillators distributed across the pixel matrix. PLL tuning of the local oscillators allows for automatic compensation of frequency fluctuations caused by process parameter, supply voltage and temperature variations. The developed PLL locks within s and achieves a duty cycle of 50.75% with a time interval error of only 23.4 ps. Mean DNL and INL of the TDC are less than 20% of the time bin size of 1.56 ns under all anticipated conditions.

  12. Production and characterization of SLID interconnected n-in-p pixel modules with 75 micron thin silicon sensors

    CERN Document Server

    Andricek, L; Macchiolo, A; Moser, H.G; Nisius, R; Richter, R.H; Terzo, S; Weigell, P

    2014-01-01

    The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. T...

  13. Production and Characterisation of SLID Interconnected n-in-p Pixel Modules with 75 Micrometer Thin Silicon Sensors

    CERN Document Server

    Andricek, L; Macchiolo, A.; Moser, H.-G.; Nisius, R.; Richter, R.H.; Terzo, S.; Weigell, P.

    2014-01-01

    The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tunability, charge collection, cluster sizes and hit efficiencies. Targeting at ...

  14. An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process †

    Science.gov (United States)

    Takayanagi, Isao; Yoshimura, Norio; Mori, Kazuya; Matsuo, Shinichiro; Tanaka, Shunsuke; Abe, Hirofumi; Yasuda, Naoto; Ishikawa, Kenichiro; Okura, Shunsuke; Ohsawa, Shinji; Otaka, Toshinori

    2018-01-01

    To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke−. Readout noise under the highest pixel gain condition is 1 e− with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7”, 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach. PMID:29329210

  15. An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process.

    Science.gov (United States)

    Takayanagi, Isao; Yoshimura, Norio; Mori, Kazuya; Matsuo, Shinichiro; Tanaka, Shunsuke; Abe, Hirofumi; Yasuda, Naoto; Ishikawa, Kenichiro; Okura, Shunsuke; Ohsawa, Shinji; Otaka, Toshinori

    2018-01-12

    To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke - . Readout noise under the highest pixel gain condition is 1 e - with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR) signal is obtained. Using this technology, a 1/2.7", 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR) approach.

  16. An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process

    Directory of Open Access Journals (Sweden)

    Isao Takayanagi

    2018-01-01

    Full Text Available To respond to the high demand for high dynamic range imaging suitable for moving objects with few artifacts, we have developed a single-exposure dynamic range image sensor by introducing a triple-gain pixel and a low noise dual-gain readout circuit. The developed 3 μm pixel is capable of having three conversion gains. Introducing a new split-pinned photodiode structure, linear full well reaches 40 ke−. Readout noise under the highest pixel gain condition is 1 e− with a low noise readout circuit. Merging two signals, one with high pixel gain and high analog gain, and the other with low pixel gain and low analog gain, a single exposure dynamic rage (SEHDR signal is obtained. Using this technology, a 1/2.7”, 2M-pixel CMOS image sensor has been developed and characterized. The image sensor also employs an on-chip linearization function, yielding a 16-bit linear signal at 60 fps, and an intra-scene dynamic range of higher than 90 dB was successfully demonstrated. This SEHDR approach inherently mitigates the artifacts from moving objects or time-varying light sources that can appear in the multiple exposure high dynamic range (MEHDR approach.

  17. arXiv Performance verification of the CMS Phase-1 Upgrade Pixel detector

    CERN Document Server

    Veszpremi, Viktor

    2017-12-04

    The CMS tracker consists of two tracking systems utilizing semiconductor technology: the inner pixel and the outer strip detectors. The tracker detectors occupy the volume around the beam interaction region between 3 cm and 110 cm in radius and up to 280 cm along the beam axis. The pixel detector consists of 124 million pixels, corresponding to about 2 m 2 total area. It plays a vital role in the seeding of the track reconstruction algorithms and in the reconstruction of primary interactions and secondary decay vertices. It is surrounded by the strip tracker with 10 million read-out channels, corresponding to 200 m 2 total area. The tracker is operated in a high-occupancy and high-radiation environment established by particle collisions in the LHC . The current strip detector continues to perform very well. The pixel detector that has been used in Run 1 and in the first half of Run 2 was, however, replaced with the so-called Phase-1 Upgrade detector. The new system is better suited to match the increased inst...

  18. ATLAS SemiConductor Tracker and Pixel Detector: Status and Performance

    CERN Document Server

    Reeves, K; The ATLAS collaboration

    2012-01-01

    The Semi-Conductor Tracker (SCT) and the Pixel Detector are the key precision tracking devices in the Inner Detector of the ATLAS experiment at CERN LHC. The SCT is a silicon strip detector and is constructed of 4088 silicon detector modules for a total of 6.3 million strips. Each module is designed, constructed and tested to operate as a stand-alone unit, mechanically, electrically, optically and thermally. The SCT silicon micro-strip sensors are processed in the planar p-in-n technology. The signals from the strips are processed in the front-end ASICS ABCD3TA, working in the binary readout mode. The Pixel Detector consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In the talk the current status of the SCT and Pixel Detector will be reviewed. We will report on the operation of the detectors including an overview of the issues we encountered and the observation of significant increases in leakage currents (as expected) from bulk ...

  19. Test Beam Performance Measurements for the Phase I Upgrade of the CMS Pixel Detector

    CERN Document Server

    Dragicevic, M.; Hrubec, J.; Steininger, H.; Gädda, A.; Härkönen, J.; Lampén, T.; Luukka, P.; Peltola, T.; Tuominen, E.; Tuovinen, E.; Winkler, A.; Eerola, P.; Tuuva, T.; Baulieu, G.; Boudoul, G.; Caponetto, L.; Combaret, C.; Contardo, D.; Dupasquier, T.; Gallbit, G.; Lumb, N.; Mirabito, L.; Perries, S.; Donckt, M.Vander; Viret, S.; Bonnin, C.; Charles, L.; Gross, L.; Hosselet, J.; Tromson, D.; Feld, L.; Karpinski, W.; Klein, K.; Lipinski, M.; Pierschel, G.; Preuten, M.; Rauch, M.; Wlochal, M.; Aldaya, M.; Asawatangtrakuldee, C.; Beernaert, K.; Bertsche, D.; Contreras-Campana, C.; Eckerlin, G.; Eckstein, D.; Eichhorn, T.; Gallo, E.; Garcia, J.Garay; Hansen, K.; Haranko, M.; Harb, A.; Hauk, J.; Keaveney, J.; Kalogeropoulos, A.; Kleinwort, C.; Lohmann, W.; Mankel, R.; Maser, H.; Mittag, G.; Muhl, C.; Mussgiller, A.; Pitzl, D.; Reichelt, O.; Savitskyi, M.; Schütze, P.; Sola, V.; Spannagel, S.; Walsh, R.; Zuber, A.; Biskop, H.; Buhmann, P.; Centis-Vignali, M.; Garutti, E.; Haller, J.; Hoffmann, M.; Klanner, R.; Lapsien, T.; Matysek, M.; Perieanu, A.; Scharf, Ch.; Schleper, P.; Schmidt, A.; Schwandt, J.; Sonneveld, J.; Steinbrück, G.; Vormwald, B.; Wellhausen, J.; Abbas, M.; Amstutz, C.; Barvich, T.; Barth, Ch.; Boegelspacher, F.; Boer, W.De; Butz, E.; Casele, M.; Colombo, F.; Dierlamm, A.; Freund, B.; Hartmann, F.; Heindl, S.; Husemann, U.; Kornmeyer, A.; Kudella, S.; Muller, Th.; Simonis, H.J.; Steck, P.; Weber, M.; Weiler, Th.; Kiss, T.; Siklér, F.; Tölyhi, T.; Veszprémi, V.; Cariola, P.; Creanza, D.; Palma, M.De; Robertis, G.De; Fiore, L.; Franco, M.; Loddo, F.; Sala, G.; Silvestris, L.; Maggi, G.; My, S.; Selvaggi, G.; Albergo, S.; Cappello, G.; Costa, S.; Mattia, A.Di; Giordano, F.; Potenza, R.; Saizu, M.A.; Tricomi, A.; Tuve, C.; Focardi, E.; Dinardo, M.E.; Fiorendi, S.; Gennai, S.; Malvezzi, S.; Manzoni, R.A.; Menasce, D.; Moroni, L.; Pedrini, D.; Azzi, P.; Bacchetta, N.; Bisello, D.; Dall'Osso, M.; Pozzobon, N.; Tosi, M.; Solestizi, L.Alunni; Biasini, M.; Bilei, G.M.; Cecchi, C.; Checcucci, B.; Ciangottini, D.; Fanò, L.; Gentsos, C.; Ionica, M.; Leonardi, R.; Manoni, E.; Mantovani, G.; Marconi, S.; Mariani, V.; Menichelli, M.; Modak, A.; Morozzi, A.; Moscatelli, F.; Passeri, D.; Placidi, P.; Postolache, V.; Rossi, A.; Saha, A.; Santocchia, A.; Storchi, L.; Spiga, D.; Androsov, K.; Azzurri, P.; Bagliesi, G.; Basti, A.; Boccali, T.; Borrello, L.; Bosi, F.; Castaldi, R.; Ceccanti, M.; Ciocci, M.A.; Dell'Orso, R.; Donato, S.; Fedi, G.; Giassi, A.; Grippo, M.T.; Ligabue, F.; Magazzu, G.; Mammini, P.; Mariani, F.; Mazzoni, E.; Messineo, A.; Moggi, A.; Morsani, F.; Palla, F.; Palmonari, F.; Profeti, A.; Raffaelli, F.; Ragonesi, A.; Rizzi, A.; Soldani, A.; Spagnolo, P.; Tenchini, R.; Tonelli, G.; Venturi, A.; Verdini, P.G.; Abbaneo, D.; Ahmed, I.; Albert, E.; Auzinger, G.; Berruti, G.; Bonnaud, J.; Daguin, J.; D'Auria, A.; Detraz, S.; Dondelewski, O.; Engegaard, B.; Faccio, F.; Frank, N.; Gill, K.; Honma, A.; Kornmayer, A.; Labaza, A.; Manolescu, F.; McGill, I.; Mersi, S.; Michelis, S.; Onnela, A.; Ostrega, M.; Pavis, S.; Peisert, A.; Pernot, J.F.; Petagna, P.; Postema, H.; Rapacz, K.; Sigaud, C.; Tropea, P.; Troska, J.; Tsirou, A.; Vasey, F.; Verlaat, B.; Vichoudis, P.; Zwalinski, L.; Bachmair, F.; Becker, R.; di Calafiori, D.; Casal, B.; Berger, P.; Djambazov, L.; Donega, M.; Grab, C.; Hits, D.; Hoss, J.; Kasieczka, G.; Lustermann, W.; Mangano, B.; Marionneau, M.; Arbol, P.Martinez Ruiz del; Masciovecchio, M.; Meinhard, M.; Perozzi, L.; Roeser, U.; Starodumov, A.; Tavolaro, V.; Wallny, R.; Zhu, D.; Amsler, C.; Bösiger, K.; Caminada, L.; Canelli, F.; Chiochia, V.; de Cosa, A.; Galloni, C.; Hreus, T.; Kilminster, B.; Lange, C.; Maier, R.; Ngadiuba, J.; Pinna, D.; Robmann, P.; Taroni, S.; Yang, Y.; Bertl, W.; Deiters, K.; Erdmann, W.; Horisberger, R.; Kaestli, H.C.; Kotlinski, D.; Langenegger, U.; Meier, B.; Rohe, T.; Streuli, S.; Chen, P.H.; Dietz, C.; Fiori, F.; Grundler, U.; Hou, W.S.; Lu, R.S.; Moya, M.; Tsai, J.F.; Tzeng, Y.M.; Cussans, D.; Goldstein, J.; Grimes, M.; Newbold, D.; Hobson, P.; Reid, I.D.; Auzinger, G.; Bainbridge, R.; Dauncey, P.; Hall, G.; James, T.; Magnan, A.M.; Pesaresi, M.; Raymond, D.M.; Uchida, K.; Durkin, T.; Harder, K.; Shepherd-Themistocleous, C.; Chertok, M.; Conway, J.; Conway, R.; Flores, C.; Lander, R.; Pellett, D.; Ricci-Tam, F.; Squires, M.; Thomson, J.; Yohay, R.; Burt, K.; Ellison, J.; Hanson, G.; Olmedo, M.; Si, W.; Yates, B.R.; Dominguez, A.; Bartek, R.; Bentele, B.; Cumalat, J.P.; Ford, W.T.; Jensen, F.; Johnson, A.; Krohn, M.; Leontsinis, S.; Mulholland, T.; Stenson, K.; Wagner, S.R.; Apresyan, A.; Bolla, G.; Burkett, K.; Butler, J.N.; Canepa, A.; Cheung, H.W.K.; Christian, D.; Cooper, W.E.; Deptuch, G.; Derylo, G.; Gingu, C.; Grünendahl, S.; Hasegawa, S.; Hoff, J.; Howell, J.; Hrycyk, M.; Jindariani, S.; Johnson, M.; Kahlid, F.; Kwan, S.; Lei, C.M.; Lipton, R.; Sá, R.Lopes De; Liu, T.; Los, S.; Matulik, M.; Merkel, P.; Nahn, S.; Prosser, A.; Rivera, R.; Schneider, B.; Sellberg, G.; Shenai, A.; Siehl, K.; Spiegel, L.; Tran, N.; Uplegger, L.; Voirin, E.; Berry, D.R.; Chen, X.; Ennesser, L.; Evdokimov, A.; Gerber, C.E.; Makauda, S.; Mills, C.; Gonzalez, I.D.Sandoval; Alimena, J.; Antonelli, L.J.; Francis, B.; Hart, A.; Hill, C.S.; Parashar, N.; Stupak, J.; Bortoletto, D.; Bubna, M.; Hinton, N.; Jones, M.; Miller, D.H.; Shi, X.; Baringer, P.; Bean, A.; Khalil, S.; Kropivnitskaya, A.; Majumder, D.; Schmitz, E.; Wilson, G.; Ivanov, A.; Mendis, R.; Mitchell, T.; Skhirtladze, N.; Taylor, R.; Anderson, I.; Fehling, D.; Gritsan, A.; Maksimovic, P.; Martin, C.; Nash, K.; Osherson, M.; Swartz, M.; Xiao, M.; Acosta, J.G.; Cremaldi, L.M.; Oliveros, S.; Perera, L.; Summers, D.; Bloom, K.; Claes, D.R.; Fangmeier, C.; Suarez, R.Gonzalez; Monroy, J.; Siado, J.; Bartz, E.; Gershtein, Y.; Halkiadakis, E.; Kyriacou, S.; Lath, A.; Nash, K.; Osherson, M.; Schnetzer, S.; Stone, R.; Walker, M.; Malik, S.; Norberg, S.; Vargas, J.E.Ramirez; Alyari, M.; Dolen, J.; Godshalk, A.; Harrington, C.; Iashvili, I.; Kharchilava, A.; Nguyen, D.; Parker, A.; Rappoccio, S.; Roozbahani, B.; Alexander, J.; Chaves, J.; Chu, J.; Dittmer, S.; McDermott, K.; Mirman, N.; Rinkevicius, A.; Ryd, A.; Salvati, E.; Skinnari, L.; Soffi, L.; Tao, Z.; Thom, J.; Tucker, J.; Zientek, M.; Akgün, B.; Ecklund, K.M.; Kilpatrick, M.; Nussbaum, T.; Zabel, J.; D'Angelo, P.; Johns, W.; Rose, K.

    2017-05-30

    A new pixel detector for the CMS experiment is being built, owing to the instantaneous luminosities anticipated for the Phase I Upgrade of the LHC. The new CMS pixel detector provides four-hit tracking while featuring a reduced material budget as well as new cooling and powering schemes. A new front-end readout chip mitigates buffering and bandwidth limitations, and comprises a low-threshold comparator. These upgrades allow the new pixel detector to sustain and improve the efficiency of the current pixel tracker at the increased requirements imposed by high luminosities and pile-up. In this paper, comprehensive test beam studies are presented which have been conducted to verify the design and to quantify the performance of the new detector assemblies in terms of tracking efficiency and spatial resolution. Under optimal conditions, the tracking efficiency has been determined to be ($99.95 \\pm 0.05$) \\%, while the intrinsic spatial resolution has been measured to be ($4.80 \\pm 0.25$) $\\mu$m and ($7.99 \\pm 0.21$...

  20. Radiation resistance of double-type double-sided 3D pixel sensors

    CERN Document Server

    Fernandez, M; Lozano, M; Munoz, F.J; Pellegrini, G; Quirion, D; Rohe, T; Vila, I

    2013-01-01

    The proposed high-luminosity upgrade of the Large Hadron Collider is expected to increase the instantaneous luminosity at the experiments' interaction points by a factor of ten. The vertex detector will be the subsystem most affected by the luminosity increase, raising substantially their occupancy and radiation-induced damage. To preserve the vertex physics performance under these new conditions, current pixel technologies have to be improved. Hybrid pixel sensors with double-sided double-type vertical electrodes (3D sensors) are becoming a mature technology for the detector layers closest to the interaction point due to their intrinsic radiation hardness. In addition, the double-sided implementation of the 3D pixel technology provides some additional technical advantages with respect to the single-sided implementation. For this study, 3D pixel sensors manufactured at the Centro Nacional de Microelectrónica of Barcelona (IMB-CNM) have been bonded to the PSI46 readout chip currently used by the Compact Muon ...

  1. Testbeam results of irradiated ams H18 HV-CMOS pixel sensor prototypes

    Science.gov (United States)

    Benoit, M.; Braccini, S.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F. A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Kiehn, M.; Lanni, F.; Liu, H.; Meng, L.; Merlassino, C.; Miucci, A.; Muenstermann, D.; Nessi, M.; Okawa, H.; Perić, I.; Rimoldi, M.; Ristić, B.; Barrero Pinto, M. Vicente; Vossebeld, J.; Weber, M.; Weston, T.; Wu, W.; Xu, L.; Zaffaroni, E.

    2018-02-01

    HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the 4th generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between 1× 1014 and 5× 1015 1-MeV- neq. The sensors were glued to ATLAS FE-I4 pixel readout chips and measured at the CERN SPS H8 beamline using the FE-I4 beam telescope. Results for all fluences are very encouraging with all hit efficiencies being better than 97% for bias voltages of 85 V. The sample irradiated to a fluence of 1× 1015 neq—a relevant value for a large volume of the upgraded tracker—exhibited 99.7% average hit efficiency. The results give strong evidence for the radiation tolerance of HV-CMOS sensors and their suitability as sensors for the experimental HL-LHC upgrades and future large-area silicon-based tracking detectors in high-radiation environments.

  2. X-CSIT: a toolkit for simulating 2D pixel detectors

    Science.gov (United States)

    Joy, A.; Wing, M.; Hauf, S.; Kuster, M.; Rüter, T.

    2015-04-01

    A new, modular toolkit for creating simulations of 2D X-ray pixel detectors, X-CSIT (X-ray Camera SImulation Toolkit), is being developed. The toolkit uses three sequential simulations of detector processes which model photon interactions, electron charge cloud spreading with a high charge density plasma model and common electronic components used in detector readout. In addition, because of the wide variety in pixel detector design, X-CSIT has been designed as a modular platform so that existing functions can be modified or additional functionality added if the specific design of a detector demands it. X-CSIT will be used to create simulations of the detectors at the European XFEL, including three bespoke 2D detectors: the Adaptive Gain Integrating Pixel Detector (AGIPD), Large Pixel Detector (LPD) and DePFET Sensor with Signal Compression (DSSC). These simulations will be used by the detector group at the European XFEL for detector characterisation and calibration. For this purpose, X-CSIT has been integrated into the European XFEL's software framework, Karabo. This will further make it available to users to aid with the planning of experiments and analysis of data. In addition, X-CSIT will be released as a standalone, open source version for other users, collaborations and groups intending to create simulations of their own detectors.

  3. Testing and Integration of the Service Cylinders for the CMS Phase 1 pixel detector

    CERN Document Server

    Ngadiuba, Jennifer

    2016-01-01

    The present 3-layer CMS pixel detector will be replaced with a new 4-layer pixel system, referred to as Phase~1 upgrade, during the LHC extended technical stop in winter 2016/2017. The upgraded detector will allow to maintain the excellent tracking performance of CMS at the upcoming higher luminosity conditions at the LHC. The addition of an extra layer, closer to the beam pipe, demands a complete redesign of its services. The barrel pixel detector is attached to four half cylinders which carry the services along the beam pipe, accommodate the cooling lines and house the electronics for detector readout and control. The service cylinders are a complex system in design as well as in production due to the large number of channels and tight space requirements. In this document we present the design of the system and discuss the construction and testing of the service cylinders for the barrel pixel detector. Furthermore, we present results of the testing and calibrations carried out with a set of new digital dete...

  4. Ultrahigh-speed, high-sensitivity color camera with 300,000-pixel single CCD

    Science.gov (United States)

    Kitamura, K.; Arai, T.; Yonai, J.; Hayashida, T.; Ohtake, H.; Kurita, T.; Tanioka, K.; Maruyama, H.; Namiki, J.; Yanagi, T.; Yoshida, T.; van Kuijk, H.; Bosiers, Jan T.; Etoh, T. G.

    2007-01-01

    We have developed an ultrahigh-speed, high-sensitivity portable color camera with a new 300,000-pixel single CCD. The 300,000-pixel CCD, which has four times the number of pixels of our initial model, was developed by seamlessly joining two 150,000-pixel CCDs. A green-red-green-blue (GRGB) Bayer filter is used to realize a color camera with the single-chip CCD. The camera is capable of ultrahigh-speed video recording at up to 1,000,000 frames/sec, and small enough to be handheld. We also developed a technology for dividing the CCD output signal to enable parallel, highspeed readout and recording in external memory; this makes possible long, continuous shots up to 1,000 frames/second. As a result of an experiment, video footage was imaged at an athletics meet. Because of high-speed shooting, even detailed movements of athletes' muscles were captured. This camera can capture clear slow-motion videos, so it enables previously impossible live footage to be imaged for various TV broadcasting programs.

  5. 3D silicon pixel detectors for the High-Luminosity LHC

    CERN Document Server

    Lange, J.

    2016-01-01

    3D silicon pixel detectors have been investigated as radiation-hard candidates for the innermost layers of the HL-LHC upgrade of the ATLAS pixel detector. 3D detectors are already in use today in the ATLAS IBL and AFP experiments. These are based on 50x250 um2 large pixels connected to the FE-I4 readout chip. Detectors of this generation were irradiated to HL-LHC fluences and demonstrated excellent radiation hardness with operational voltages as low as 180 V and power dissipation of 12--15 mW/cm2 at a fluence of about 1e16 neq/cm2, measured at -25 degree C. Moreover, to cope with the higher occupancies expected at the HL-LHC, a first run of a new generation of 3D detectors designed for the HL-LHC was produced at CNM with small pixel sizes of 50x50 and 25x100 um2, matched to the FE-I4 chip. They demonstrated a good performance in the laboratory and in beam tests with hit efficiencies of about 97% at already 1--2V before irradiation.

  6. Preliminary test of an imaging probe for nuclear medicine using hybrid pixel detectors

    CERN Document Server

    Bertolucci, Ennio; Mettivier, G; Montesi, M C; Russo, P

    2002-01-01

    We are investigating the feasibility of an intraoperative imaging probe for lymphoscintigraphy with Tc-99m tracer, for sentinel node radioguided surgery, using the Medipix series of hybrid detectors coupled to a collimator. These detectors are pixelated semiconductor detectors bump-bonded to the Medipix1 photon counting read-out chip (64x64 pixel, 170 mu m pitch) or to the Medipix2 chip (256x256 pixel, 55 mu m pitch), developed by the European Medipix collaboration. The pixel detector we plan to use in the final version of the probe is a semi-insulating GaAs detector or a 1-2 mm thick CdZnTe detector. For the preliminary tests presented here, we used 300-mu m thick silicon detectors, hybridized via bump-bonding to the Medipix1 chip. We used a tungsten parallel-hole collimator (7 mm thick, matrix array of 64x64 100 mu m circular holes with 170 mu m pitch), and a 22, 60 and 122 keV point-like (1 mm diameter) radioactive sources, placed at various distances from the detector. These tests were conducted in order ...

  7. The construction of the phase 1 upgrade of the CMS pixel detector

    CERN Document Server

    Weber, Hannsjorg Artur

    2017-01-01

    The innermost layers of the original CMS tracker were built out of pixel detectors arranged in three barrel layers and two forward disks in each endcap. The original CMS detector was designed for the nominal instantaneous LHC luminosity of $1\\times10^{34}\\,\\text{cm}^{-2}\\text{s}^{-1}$. Under the conditions expected in the coming years, which will see an increase of a factor two of the instantaneous luminosity, the CMS pixel detector would have seen a dynamic inefficiency caused by data losses due to buffer overflows. For this reason the CMS collaboration has installed during the recent extended end of year shutdown a replacement pixel detector. The phase-1 upgrade of the CMS pixel detector will operate at high efficiency at an instantaneous luminosity of $2\\times10^{34}\\,\\text{cm}^{-2}\\text{s}^{-1}$ with increased detector acceptance and additional redundancy for the tracking, while at the same time reducing the material budget. These goals are achieved using a new read-out chip and modified powering and rea...

  8. Testbeam results of irradiated ams H18 HV-CMOS pixel sensor prototypes

    CERN Document Server

    Benoit, M.; Casse, G.; Chen, H.; Chen, K.; Bello, F.A.Di; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Kiehn, M.; Lanni, F.; Liu, H.; Meng, L.; Merlassino, C.; Miucci, A.; Muenstermann, D.; Nessi, M.; Okawa, H.; Peric, I.; Rimoldi, M.; Ristic, B.; Vicente Barrero Pinto, M.; Vossebeld, J.; Weber, M.; Weston, T.; Wu, W.; Xu, L.; Zaffaroni, E.

    2018-02-08

    HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the $4^{\\mathrm{th}}$ generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between $1\\cdot 10^{14}$ and $5\\cdot 10^{15}$ 1-MeV-n$_\\textrm{eq}$/cm$^2$. The sensors were glued to ATLAS FE-I4 pixel readout chips and measured at the CERN SPS H8 beamline using the FE-I4 beam telescope. Results for all fluences are very encouraging with all hit efficiencies being better than 97% for bias voltages of $85\\,$V. The sample irradiated to a fluence of $1\\cdot 10^{15}$ n$_\\textrm{eq}$/cm$^2$ - a relevant value for a large volume of the upgraded tracker - exhibited 99.7% average hit ...

  9. Evaluation of testing strategies for the radiation tolerant ATLAS n **+-in-n pixel sensor

    CERN Document Server

    Klaiber Lodewigs, Jonas M

    2003-01-01

    The development of particle tracker systems for high fluence environments in new high-energy physics experiments raises new challenges for the development, manufacturing and reliable testing of radiation tolerant components. The ATLAS pixel detector for use at the LHC, CERN, is designed to cover an active sensor area of 1.8 m**2 with 1.1 multiplied by 10 **8 read-out channels usable for a particle fluence up to 10 **1**5 cm**-**2 (1 MeV neutron equivalent) and an ionization dose up to 500 kGy of mainly charged hadron radiation. To cope with such a harsh environment the ATLAS Pixel Collaboration has developed a radiation hard n **+-in-n silicon pixel cell design with a standard cell size of 50 multiplied by 400 mum**2. Using this design on an oxygenated silicon substrate, sensor production has started in 2001. This contribution describes results gained during the development of testing procedures of the ATLAS pixel sensor and evaluates quality assurance procedures regarding their relevance for detector operati...

  10. Characterization of a module with pixelated CdTe detectors for possible PET, PEM and compton camera applications

    Science.gov (United States)

    Ariño-Estrada, G.; Chmeissani, M.; de Lorenzo, G.; Puigdengoles, C.; Martínez, R.; Cabruja, E.

    2014-05-01

    We present the measurement of the energy resolution and the impact of charge sharing for a pixel CdTe detector. This detector will be used in a novel conceptual design for diagnostic systems in the field of nuclear medicine such as positron emission tomography (PET), positron emission mammography (PEM) and Compton camera. The detector dimensions are 10 mm × 10 mm × 2 mm and with a pixel pitch of 1 mm × 1 mm. The pixel CdTe detector is a Schottky diode and it was tested at a bias of -1000 V. The VATAGP7.1 frontend ASIC was used for the readout of the pixel detector and the corresponding single channel electronic noise was found to be σ < 2 keV for all the pixels. We have achieved an energy resolution, FWHM/Epeak, of 7.1%, 4.5% and 0.98% for 59.5, 122 and 511 keV respectively. The study of the charge sharing shows that 16% of the events deposit part of their energy in the adjacent pixel.

  11. Characterisation of edgeless technologies for pixellated and strip silicon detectors with a micro-focused X-ray beam

    Science.gov (United States)

    Bates, R.; Blue, A.; Christophersen, M.; Eklund, L.; Ely, S.; Fadeyev, V.; Gimenez, E.; Kachkanov, V.; Kalliopuska, J.; Macchiolo, A.; Maneuski, D.; Phlips, B. F.; Sadrozinski, H. F.-W.; Stewart, G.; Tartoni, N.; Zain, R. M.

    2013-01-01

    Reduced edge or ``edgeless'' detector design offers seamless tileability of sensors for a wide range of applications from particle physics to synchrotron and free election laser (FEL) facilities and medical imaging. Combined with through-silicon-via (TSV) technology, this would allow reduced material trackers for particle physics and an increase in the active area for synchrotron and FEL pixel detector systems. In order to quantify the performance of different edgeless fabrication methods, 2 edgeless detectors were characterized at the Diamond Light Source using an 11 μm FWHM 15 keV micro-focused X-ray beam. The devices under test were: a 150 μm thick silicon active edge pixel sensor fabricated at VTT and bump-bonded to a Medipix2 ROIC; and a 300 μm thick silicon strip sensor fabricated at CIS with edge reduction performed by SCIPP and the NRL and wire bonded to an ALiBaVa readout system. Sub-pixel resolution of the 55 μm active edge pixels was achieved. Further scans showed no drop in charge collection recorded between the centre and edge pixels, with a maximum deviation of 5% in charge collection between scanned edge pixels. Scans across the cleaved and standard guard ring edges of the strip detector also show no reduction in charge collection. These results indicate techniques such as the scribe, cleave and passivate (SCP) and active edge processes offer real potential for reduced edge, tiled sensors for imaging detection applications.

  12. Firmware development and testing of the ATLAS IBL Readout Driver card

    CERN Document Server

    Chen, S; The ATLAS collaboration

    2014-01-01

    The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector is inserting an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBLROD firmware development focused on migrating and tailoring HDL code blocks from PixelROD to ensure modular compatibility in future ROD upgrades, in which a unified code version will interface with IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBLDAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBLROD data path implementation, tested in testbench and on ROD prototypes, will be report...

  13. Firmware development and testing of the ATLAS IBL Read-Out Driver card

    CERN Document Server

    Chen, S-P; The ATLAS collaboration; Falchieri, D; Gabrielli, A; Hauck, S; Hsu, S-C; Kretz, M; Kugel, A; Travaglini, R; Wensing, M

    2014-01-01

    The ATLAS Experiment is reworking and upgrading systems during the current LHC shutdown. In particular, the Pixel detector is inserting an additional inner layer called Insertable B-Layer (IBL). The Read-Out Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBL ROD firmware development focused on migrating and tailoring HDL code blocks from Pixel ROD to ensure modular compatibility in future ROD upgrades, in which a unified code version will interface with IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ testbench using a realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data path implementation, tested in testbench and on ROD prototypes, will be ...

  14. Results from the NA62 Gigatracker Prototype: A Low-Mass and sub-ns Time Resolution Silicon Pixel Detector

    Science.gov (United States)

    Fiorini, M.; Rinella, G. Aglieri; Carassiti, V.; Ceccucci, A.; Gil, E. Cortina; Ramusino, A. Cotta; Dellacasa, G.; Garbolino, S.; Jarron, P.; Kaplon, J.; Kluge, A.; Marchetto, F.; Mapelli, A.; Martin, E.; Mazza, G.; Morel, M.; Noy, M.; Nuessle, G.; Petagna, P.; Petrucci, F.; Perktold, L.; Riedler, P.; Rivetti, A.; Statera, M.; Velghe, B.

    The Gigatracker (GTK) is a hybrid silicon pixel detector developed for NA62, the experiment aimed at studying ultra-rare kaon decays at the CERN SPS. Three GTK stations will provide precise momentum and angular measurements on every track of the high intensity NA62 hadron beam with a time-tagging resolution of 150 ps. Multiple scattering and hadronic interactions of beam particles in the GTK have to be minimized to keep background events at acceptable levels, hence the total material budget is fixed to 0.5% X0 per station. In addition the calculated fluence for 100 days of running is 2×1014 1 MeV neq/cm2, comparable to the one expected for the inner trackers of LHC detectors in 10 years of operation. These requirements pose challenges for the development of an efficient and low-mass cooling system, to be operated in vacuum, and on the thinning of read-out chips to 100 μm or less. The most challenging requirement is represented by the time resolution, which can be achieved by carefully compensating for the discriminator time-walk. For this purpose, two complementary read-out architectures have been designed and produced as small-scale prototypes: the first is based on the use of a Time-over-Threshold circuit followed by a TDC shared by a group of pixels, while the other uses a constant-fraction discriminator followed by an on-pixel TDC. The readout pixel ASICs are produced in 130 nm IBM CMOS technology and bump-bonded to 200 μm thick silicon sensors. The Gigatracker detector system is described with particular emphasis on recent experimental results obtained from laboratory and beam tests of prototype bump-bonded assemblies, which show a time resolution of less than 200 ps for single hits.

  15. Precision scans of the Pixel cell response of double sided 3D Pixel detectors to pion and X-ray beams

    CERN Document Server

    Mac Raighne, A; Crossley, M; Alianelli, L; Lozano, M; Dumps, R; Fleta, C; Collins, P; Rodrigues, E; Sawhney, K J S; Tlustos, L; Pennicard, D; Buytaert, J; Stewart, G; Parkes, C; Eklund, L; Campbell, M; Marchal, J; Akiba, K; Pellegrini, G; Llopart, X; Plackett, R; Maneuski, D; Gligorov, V V; Tartoni, N; Nicol, M; Bates, R; Gallas, A; Gimenez, E N; van Beuzekom, M; John, M

    2011-01-01

    Three-dimensional (3D) silicon sensors offer potential advantages over standard planar sensors for radiation hardness in future high energy physics experiments and reduced charge-sharing for X-ray applications, but may introduce inefficiencies due to the columnar electrodes. These inefficiencies are probed by studying variations in response across a unit pixel cell in a 55 m m pitch double-sided 3D pixel sensor bump bonded to TimePix and Medipix2 readout ASICs. Two complementary characterisation techniques are discussed: the first uses a custom built telescope and a 120GeV pion beam from the Super Proton Synchrotron (SPS) at CERN; the second employs a novel technique to illuminate the sensor with a micro-focused synchrotron X-ray beam at the Diamond Light Source, UK. For a pion beam incident perpendicular to the sensor plane an overall pixel efficiency of 93.0 +/- 0.5\\% is measured. After a 10 degrees rotation of the device the effect of the columnar region becomes negligible and the overall efficiency rises ...

  16. ISPA (imaging silicon pixel array) experiment

    CERN Multimedia

    Patrice Loïez

    2002-01-01

    The bump-bonded silicon pixel detector, developed at CERN by the EP-MIC group, is shown here in its ceramic carrier. Both represent the ISPA-tube anode. The chip features between 1024 (called OMEGA-1) and 8196 (ALICE-1) active pixels.

  17. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Rossi, Leonardo Paolo; The ATLAS collaboration

    2018-01-01

    The upgrade of the ATLAS experiment for the operation at the High Luminosity Large Hadron Collider requires a new and more performant inner tracker, the ITk. The innermost part of this tracker will be built using silicon pixel detectors. This paper describes the ITk pixel project, which, after few years of design and test e ort, is now defined in detail.

  18. A new family of pixel detectors for high frame rate X-ray applications

    International Nuclear Information System (INIS)

    Dinapoli, Roberto; Bergamaschi, Anna; Henrich, Beat; Horisberger, Roland; Johnson, Ian; Kraft, Philipp; Mozzanica, Aldo; Schmitt, Bernd; Shi, Xintian; Suter, Dominic

    2010-01-01

    We are developing a new family of hybrid, single photon counting X-ray detectors for very high frame rate applications. A dedicated readout chip was designed, to be used as building block for detectors up to 9 Mpixel and about 550cm 2 area. It has an area of 19.3x20.0mm 2 and contains 256x256 pixels of 75x75μm 2 , resulting in an active region of 19.2x19.2mm 2 . Each pixel contains a 12 bit counter with double buffering for continuous image acquisition. Moreover, it allows a partial readout (4, 8 or 12 bits) with corresponding frame rates up to 24, 12 and 8 kHz. The chip is designed with Hardening By Design techniques , to obtain high radiation tolerance from a standard commercial 0.25μm CMOS technology. The chip was recently received from fabrication and it is at present under test.

  19. Three Generations of FPGA DAQ Development for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(CDS)2091916; Hsu, Shih-Chieh; Hauck, Scott Alan

    The Large Hadron Collider (LHC) at the European Center for Nuclear Research (CERN) tracks a schedule of long physics runs, followed by periods of inactivity known as Long Shutdowns (LS). During these LS phases both the LHC, and the experiments around its ring, undergo maintenance and upgrades. For the LHC these upgrades improve their ability to create data for physicists; the more data the LHC can create the more opportunities there are for rare events to appear that physicists will be interested in. The experiments upgrade so they can record the data and ensure the event won’t be missed. Currently the LHC is in Run 2 having completed the first LS of three. This thesis focuses on the development of Field-Programmable Gate Array (FPGA)-based readout systems that span across three major tasks of the ATLAS Pixel data acquisition (DAQ) system. The evolution of Pixel DAQ’s Readout Driver (ROD) card is presented. Starting from improvements made to the new Insertable B-Layer (IBL) ROD design, which was part of t...

  20. A new Data Acquisition System for the CMS Phase 1 Pixel Detector

    CERN Document Server

    Kornmayer, Andreas

    2016-01-01

    A new pixel detector will be installed in the CMS experiment during the extended technical stop of the LHC at the beginning of 2017. The new pixel detector, built from four layers in the barrel region and three layers on each end of the forward region, is equipped with upgraded front-end readout electronics, specifically designed to handle the high particle hit rates created in the LHC environment. The DAQ back-end was entirely redesigned to handle the increased number of readout channels, the higher data rates per channel and the new digital data format. Based entirely on the microTCA standard, new front-end controller (FEC) and front-end driver (FED) cards have been developed, prototyped and produced with custom optical link mezzanines mounted on the FC7 AMC and custom firmware. At the same time as the new detector is being assembled, the DAQ system is set up and its integration into the CMS central DAQ system tested by running the pilot blade detector already installed in CMS. This work describes the DAQ s...