WorldWideScience

Sample records for bioreporter integrated circuit

  1. Remote sensing of microbial volatile organic compounds with a bioluminescent bioreporter integrated circuit

    Science.gov (United States)

    Ripp, Steven A.; Daumer, Kathleen A.; Garland, Jay L.; Simpson, Michael L.; Sayler, Gary S.

    2004-03-01

    As a means towards advanced, early-warning detection of microbial growth in enclosed structures, we have constructed a bioluminescent bioreporter for the detection of the microbial volatile organic compound (MVOC) p-cymene. MVOCs are produced as metabolic by-products of bacteria and fungi and are detectable before any visible signs of microbial growth appear, thereby serving as very early indicators of potential biocontamination problems. The bioreporter, designated Pseudomonas putida UT93, contains a Vibrio fischeri luxCDABE gene fusion to a p-cymene/p-cumate inducible promoter. Exposure of strain UT93 to p-cymene from approximately 0.02 to 850 ppm produced self-generated bioluminescence in less than 1.5 hours. The bioreporter was also interfaced with an integrated circuit microluminometer to create a miniaturized hybrid sensor for remote monitoring of p-cymene signatures. This bioluminescent bioreporter integrated circuit (BBIC) device was capable of detecting fungal presence within approximately 3.5 hours of initial exposure to Penicillium roqueforti.

  2. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    Science.gov (United States)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  3. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  4. Photonic Integrated Circuits

    Science.gov (United States)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  5. Semiconductor integrated circuits

    International Nuclear Information System (INIS)

    Michel, A.E.; Schwenker, R.O.; Ziegler, J.F.

    1979-01-01

    An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

  6. Linear integrated circuits

    CERN Document Server

    Carr, Joseph

    1996-01-01

    The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

  7. Thermionic integrated circuits: electronics for hostile environments

    International Nuclear Information System (INIS)

    Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

    1985-01-01

    Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments

  8. The Evolution of the Bacterial Luciferase Gene Cassette (lux as a Real-Time Bioreporter

    Directory of Open Access Journals (Sweden)

    Gary Sayler

    2012-01-01

    Full Text Available The bacterial luciferase gene cassette (lux is unique among bioluminescent bioreporter systems due to its ability to synthesize and/or scavenge all of the substrate compounds required for its production of light. As a result, the lux system has the unique ability to autonomously produce a luminescent signal, either continuously or in response to the presence of a specific trigger, across a wide array of organismal hosts. While originally employed extensively as a bacterial bioreporter system for the detection of specific chemical signals in environmental samples, the use of lux as a bioreporter technology has continuously expanded over the last 30 years to include expression in eukaryotic cells such as Saccharomyces cerevisiae and even human cell lines as well. Under these conditions, the lux system has been developed for use as a biomedical detection tool for toxicity screening and visualization of tumors in small animal models. As the technologies for lux signal detection continue to improve, it is poised to become one of the first fully implantable detection systems for intra-organismal optical detection through direct marriage to an implantable photon-detecting digital chip. This review presents the basic biochemical background that allows the lux system to continuously autobioluminesce and highlights the important milestones in the use of lux-based bioreporters as they have evolved from chemical detection platforms in prokaryotic bacteria to rodent-based tumorigenesis study targets. In addition, the future of lux imaging using integrated circuit microluminometry to image directly within a living host in real-time will be introduced and its role in the development of dose/response therapeutic systems will be highlighted.

  9. Integrated circuit cooled turbine blade

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.; Holloman, Harry; Koester, Steven

    2017-08-29

    A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channel connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.

  10. Illuminating the detection chain of bacterial bioreporters

    NARCIS (Netherlands)

    Meer, J.R. van der; Tropel, D.; Jaspers, M.

    2004-01-01

    Engineering bacteria for measuring chemicals of environmental or toxicological concern (bioreporter bacteria) has grown slowly into a mature research area. Despite many potential advantages, current bioreporters do not perform well enough to comply with environmental detection standards. Basically,

  11. Integrated circuits for multimedia applications

    DEFF Research Database (Denmark)

    Vandi, Luca

    2007-01-01

    This work presents several key aspects in the design of RF integrated circuits for portable multimedia devices. One chapter is dedicated to the application of negative-feedback topologies to receiver frontends. A novel feedback technique suitable for common multiplier-based mixers is described...

  12. Integrated Circuit Electromagnetic Immunity Handbook

    Science.gov (United States)

    Sketoe, J. G.

    2000-08-01

    This handbook presents the results of the Boeing Company effort for NASA under contract NAS8-98217. Immunity level data for certain integrated circuit parts are discussed herein, along with analytical techniques for applying the data to electronics systems. This handbook is built heavily on the one produced in the seventies by McDonnell Douglas Astronautics Company (MDAC, MDC Report E1929 of 1 August 1978, entitled Integrated Circuit Electromagnetic Susceptibility Handbook, known commonly as the ICES Handbook, which has served countless systems designers for over 20 years). Sections 2 and 3 supplement the device susceptibility data presented in section 4 by presenting information on related material required to use the IC susceptibility information. Section 2 concerns itself with electromagnetic susceptibility analysis and serves as a guide in using the information contained in the rest of the handbook. A suggested system hardening requirements is presented in this chapter. Section 3 briefly discusses coupling and shielding considerations. For conservatism and simplicity, a worst case approach is advocated to determine the maximum amount of RF power picked up from a given field. This handbook expands the scope of the immunity data in this Handbook is to of 10 MHz to 10 GHz. However, the analytical techniques provided are applicable to much higher frequencies as well. It is expected however, that the upper frequency limit of concern is near 10 GHz. This is due to two factors; the pickup of microwave energy on system cables and wiring falls off as the square of the wavelength, and component response falls off at a rapid rate due to the effects of parasitic shunt paths for the RF energy. It should be noted also that the pickup on wires and cables does not approach infinity as the frequency decreases (as would be expected by extrapolating the square law dependence of the high frequency roll-off to lower frequencies) but levels off due to mismatch effects.

  13. Design of analog integrated circuits and systems

    CERN Document Server

    Laker, Kenneth R

    1994-01-01

    This text is designed for senior or graduate level courses in analog integrated circuits or design of analog integrated circuits. This book combines consideration of CMOS and bipolar circuits into a unified treatment. Also included are CMOS-bipolar circuits made possible by BiCMOS technology. The text progresses from MOS and bipolar device modelling to simple one and two transistor building block circuits. The final two chapters present a unified coverage of sample-data and continuous-time signal processing systems.

  14. A monolithically integrated magneto-optoelectronic circuit

    Science.gov (United States)

    Saha, D.; Basu, D.; Bhattacharya, P.

    2008-11-01

    The monolithic integration of a spin valve, an amplifier, and a light emitting diode to form a magneto-optoelectronic integrated circuit on GaAs is demonstrated. The circuit converts the spin polarization information in the channel of the spin valve to an amplified change in light intensity with a gain of 20. The monolithic circuit therefore operates as a magnetoelectronic switch which modulates the light intensity of the light emitting diode.

  15. Active components for integrated plasmonic circuits

    DEFF Research Database (Denmark)

    Krasavin, A.V.; Bolger, P.M.; Zayats, A.V.

    2009-01-01

    We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides.......We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides....

  16. Radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Hughes, R.C.

    1977-01-01

    Electronic circuits that operate properly after exposure to ionizing radiation are necessary for nuclear weapon systems, satellites, and apparatus designed for use in radiation environments. The program to develop and theoretically model radiation-tolerant integrated circuit components has resulted in devices that show an improvement in hardness up to a factor of ten thousand over earlier devices. An inverter circuit produced functions properly after an exposure of 10 6 Gy (Si) which, as far as is known, is the record for an integrated circuit

  17. Silicon integrated circuits part A : supplement 2

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

  18. Semiconductors integrated circuit design for manufacturability

    CERN Document Server

    Balasinki, Artur

    2011-01-01

    Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

  19. Lateral power transistors in integrated circuits

    CERN Document Server

    Erlbacher, Tobias

    2014-01-01

    This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

  20. Latch-up in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Estreich, D.B.; Dutton, R.W.

    1978-04-01

    An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

  1. Radio-frequency integrated-circuit engineering

    CERN Document Server

    Nguyen, Cam

    2015-01-01

    Radio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC's using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. Provide

  2. Materials issues in silicon integrated circuit processing

    International Nuclear Information System (INIS)

    Wittmer, M.; Stimmell, J.; Strathman, M.

    1986-01-01

    The symposium on ''Materials Issues in Integrated Circuit Processing'' sought to bring together all of the materials issued pertinent to modern integrated circuit processing. The inherent properties of the materials are becoming an important concern in integrated circuit manufacturing and accordingly research in materials science is vital for the successful implementation of modern integrated circuit technology. The session on Silicon Materials Science revealed the advanced stage of knowledge which topics such as point defects, intrinsic and extrinsic gettering and diffusion kinetics have achieved. Adaption of this knowledge to specific integrated circuit processing technologies is beginning to be addressed. The session on Epitaxy included invited papers on epitaxial insulators and IR detectors. Heteroepitaxy on silicon is receiving great attention and the results presented in this session suggest that 3-d integrated structures are an increasingly realistic possibility. Progress in low temperature silicon epitaxy and epitaxy of thin films with abrupt interfaces was also reported. Diffusion and Ion Implantation were well presented. Regrowth of implant-damaged layers and the nature of the defects which remain after regrowth were discussed in no less than seven papers. Substantial progress was also reported in the understanding of amorphising boron implants and the use of gallium implants for the formation of shallow p/sup +/ -layers

  3. A fast charge integrating and shaping circuit

    International Nuclear Information System (INIS)

    Kulka, Z.; Szoncso, F.

    1990-01-01

    The development of a low cost fast charge integrating and shaping circuit (FCISC) was motivated by the need for an interface between the photomultipliers of an existing hadronic calorimeter and recently developed new readout electronics designed to match the output of small ionization chambers for the upgraded UA1 detector at the CERN proton-antiproton collider. This paper describes the design principles of gated and ungated charge integrating and shaping circuits. An FCISC prototype using discrete components was made and its properties were determined with a computerized test setup. Finally an SMD implementation of the FCISC is presented and the performance is reported. (orig.)

  4. Moessbauer spectrometer on integrated circuits

    International Nuclear Information System (INIS)

    Tomov, T.; Spasov, A.; Kunov, B.

    1978-01-01

    Two versions of the small-size high-quality Moessbauer spectrometer for 57 Fe spectroscopy are developed. The first version includes a proportion counter, a preamplifier, a one-chennel analyzer, a timer, and a scaler. The spectrometer is intended for measuring characteristic points of the Moessbauer-spectra and operates at constant velocities. The spectrometer parameters are as follows: integral non-linearity of the entire channel about 1%, maximum load for 14 keV line 8x10 4 pulse/s. The second version uses a multichannel time analyzer as a recording device. The spectrometer operates in the saw-toothed velocity modulation, the integral nonlinearity of the modulation being at least 0.1%

  5. Silicon Photonic Integrated Circuit Mode Multiplexer

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ou, Haiyan; Xu, Jing

    2013-01-01

    We propose and demonstrate a novel silicon photonic integrated circuit enabling multiplexing of orthogonal modes in a few-mode fiber (FMF). By selectively launching light to four vertical grating couplers, all six orthogonal spatial and polarization modes supported by the FMF are successfully exc...

  6. CLASSICS Invention of the Integrated Circuit

    Indian Academy of Sciences (India)

    IAS Admin

    CLASSICS. Jack Kilby demonstrated the working of the world's first integrated circuit in September 1958. He was awarded ... bility was established. In the early 1950's, Robert Henry of this group, working under ..... to the Air Force a small working computer complete with a few hundred bits of semiconductor memory, and. 1.

  7. LC Quadrature Generation in Integrated Circuits

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    Today quadrature signals for IQ demodulation are provided through RC polyphase networks, quadrature oscillators or double frequency VCOs. This paper presents a new method for generating quadrature signals in integrated circuits using only inductors and capacitors. This LC quadrature generation...... method enables significantly reduced noise and power consumption....

  8. Power management techniques for integrated circuit design

    CERN Document Server

    Chen, Ke-Horng

    2016-01-01

    This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

  9. Development of 3D integrated circuits for HEP

    International Nuclear Information System (INIS)

    Yarema, R.; Fermilab

    2006-01-01

    Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented

  10. Applying analog integrated circuits for HERO protection

    Science.gov (United States)

    Willis, Kenneth E.; Blachowski, Thomas J.

    1994-01-01

    One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

  11. Reverse Engineering Integrated Circuits Using Finite State Machine Analysis

    Energy Technology Data Exchange (ETDEWEB)

    Oler, Kiri J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Miller, Carl H. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2016-04-12

    In this paper, we present a methodology for reverse engineering integrated circuits, including a mathematical verification of a scalable algorithm used to generate minimal finite state machine representations of integrated circuits.

  12. Very High Speed Integrated Circuits (VHSIC).

    Science.gov (United States)

    1987-12-31

    will be chosen in January 1988. N_% The X-ray mask fabrication problems of adhesion , absorber uniformity and wall % slopes, membrane stresses, and...extent practical, the advances made in integrated circuit technology in the design of new and re-engineered sistems . Also included are coordinator’s...glass, -" metal, or ceramic (or combinations of these) packages. No organic or polymeric materials such as lacquers, varnishes, coatings, adhesives

  13. Viewing Integrated-Circuit Interconnections By SEM

    Science.gov (United States)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  14. High-frequency analog integrated circuit design

    CERN Document Server

    1995-01-01

    To learn more about designing analog integrated circuits (ICs) at microwave frequencies using GaAs materials, turn to this text and reference. It addresses GaAs MESFET-based IC processing. Describes the newfound ability to apply silicon analog design techniques to reliable GaAs materials and devices which, until now, was only available through technical papers scattered throughout hundred of articles in dozens of professional journals.

  15. The RD53A Integrated Circuit

    CERN Document Server

    Garcia-Sciveres, Maurice

    2017-01-01

    Implementation details for the RD53A pixel readout integrated circuit designed by the RD53 Collaboration. This is a companion to the specifications document and will eventually become a reference for chip users. RD53A is not intended to be a final production IC for use in an experiment, and contains design variations for testing purposes, making the pixel matrix non-uniform. The chip size is 20.0 mm by 11.8 mm.

  16. Very High Speed Integrated Circuits (VHSIC)

    Science.gov (United States)

    1990-09-01

    This report presents a description and final account of the VHSIC program during its ten years of successfully developing advanced integrated circuit technologies and products for military systems. The new technologies and the products that VHSIC has produced have steadily found their way not only in defense systems but also into the commercial industrial base. They provide the reservoir from which new system capabilities are emerging and a foundation upon which continual further advances are being made. Over the course of the past decade, the VHSIC program has been active in the development of new materials, new circuit design concepts, advanced fabrication processes, new manufacturing equipment, higher levels of radiation harding, new data interface standards and specifications, and improved techniques for built-in-test maintainability. The VHSIC Hardware Description Language and other design automation tools have broken through major integrated circuit complexity barriers and will decrease the cost and development time of modern electronic systems. The resulting achievements have helped to produce a new level of system design and fabrication - one that approaches an integrated concept-to-system capability.

  17. Progress in radiation immune thermionic integrated circuits

    International Nuclear Information System (INIS)

    Lynn, D.K.; McCormick, J.B.

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs

  18. High transition temperature superconducting integrated circuit

    International Nuclear Information System (INIS)

    DiIorio, M.S.

    1985-01-01

    This thesis describes the design and fabrication of the first superconducting integrated circuit capable of operating at over 10K. The primary component of the circuit is a dc SQUID (Superconducting QUantum Interference Device) which is extremely sensitive to magnetic fields. The dc SQUID consists of two superconductor-normal metal-superconductor (SNS) Josephson microbridges that are fabricated using a novel step-edge process which permits the use of high transition temperature superconductors. By utilizing electron-beam lithography in conjunction with ion-beam etching, very small microbridges can be produced. Such microbridges lead to high performance dc SQUIDs with products of the critical current and normal resistance reaching 1 mV at 4.2 K. These SQUIDs have been extensively characterized, and exhibit excellent electrical characteristics over a wide temperature range. In order to couple electrical signals into the SQUID in a practical fashion, a planar input coil was integrated for efficient coupling. A process was developed to incorporate the technologically important high transition temperature superconducting materials, Nb-Sn and Nb-Ge, using integrated circuit techniques. The primary obstacles were presented by the metallurgical idiosyncrasies of the various materials, such as the need to deposit the superconductors at elevated temperatures, 800-900 0 C, in order to achieve a high transition temperature

  19. Power system with an integrated lubrication circuit

    Science.gov (United States)

    Hoff, Brian D [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL; Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Lane, William H [Chillicothe, IL

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  20. Bioluminescent bioreporter for assessment of arsenic contamination ...

    Indian Academy of Sciences (India)

    The bioreporter sensor system developed in this study can measure the estimated range of 0.74–60 g of As/L and is both specific and selective for sensing bioavailable As. The constructed bacterial biosensor was further used for the determination of arsenic ion concentration in different environmental samples of India.

  1. Integrated Circuits for Analog Signal Processing

    CERN Document Server

    2013-01-01

      This book presents theory, design methods and novel applications for integrated circuits for analog signal processing.  The discussion covers a wide variety of active devices, active elements and amplifiers, working in voltage mode, current mode and mixed mode.  This includes voltage operational amplifiers, current operational amplifiers, operational transconductance amplifiers, operational transresistance amplifiers, current conveyors, current differencing transconductance amplifiers, etc.  Design methods and challenges posed by nanometer technology are discussed and applications described, including signal amplification, filtering, data acquisition systems such as neural recording, sensor conditioning such as biomedical implants, actuator conditioning, noise generators, oscillators, mixers, etc.   Presents analysis and synthesis methods to generate all circuit topologies from which the designer can select the best one for the desired application; Includes design guidelines for active devices/elements...

  2. Accelerating functional verification of an integrated circuit

    Science.gov (United States)

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

    2015-10-27

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  3. Thermoelectricity from wasted heat of integrated circuits

    KAUST Repository

    Fahad, Hossain M.

    2012-05-22

    We demonstrate that waste heat from integrated circuits especially computer microprocessors can be recycled as valuable electricity to power up a portion of the circuitry or other important accessories such as on-chip cooling modules, etc. This gives a positive spin to a negative effect of ever increasing heat dissipation associated with increased power consumption aligned with shrinking down trend of transistor dimension. This concept can also be used as an important vehicle for self-powered systemson- chip. We provide theoretical analysis supported by simulation data followed by experimental verification of on-chip thermoelectricity generation from dissipated (otherwise wasted) heat of a microprocessor.

  4. Integrated circuit failure mechanism detected by IMMA

    International Nuclear Information System (INIS)

    Crooke, M.

    1981-01-01

    Unanticipated lateral field effect transistor (FET) action was observed between parts of an integrated circuit (IC) during electrical probing. Although comprehensive electrical investigation lead to the identification of potentially suspect areas, and reduced the possible origins of the problem to three, it was only after application of the technique of ion microprobe mass analysis (IMMA) in the suspect areas that the problem was unambiguously identified. Based on this, a mechanism of failure was proposed which was subsequently confirmed by direct observation of the critical event

  5. Continuous surveillance of reactor coolant circuit integrity

    International Nuclear Information System (INIS)

    1986-01-01

    Continuous surveillance is important to assuring the integrity of a reactor coolant circuit. It can give pre-warning of structural degradation and indicate where off-line inspection should be focussed. These proceedings describe the state of development of several techniques which may be used. These involve measuring structural vibration, core neutron noise, acoustic emission from cracks, coolant leakage, or operating parameters such as coolant temperature and pressure. Twenty three papers have been abstracted and indexed separately for inclusion in the data base

  6. Organic membrane photonic integrated circuits (OMPICs).

    Science.gov (United States)

    Amemiya, Tomohiro; Kanazawa, Toru; Hiratani, Takuo; Inoue, Daisuke; Gu, Zhichen; Yamasaki, Satoshi; Urakami, Tatsuhiro; Arai, Shigehisa

    2017-08-07

    We propose the concept of organic membrane photonic integrated circuits (OMPICs), which incorporate various functions needed for optical signal processing into a flexible organic membrane. We describe the structure of several devices used within the proposed OMPICs (e.g., transmission lines, I/O couplers, phase shifters, photodetectors, modulators), and theoretically investigate their characteristics. We then present a method of fabricating the photonic devices monolithically in an organic membrane and demonstrate the operation of transmission lines and I/O couplers, the most basic elements of OMPICs.

  7. 3D packaging for integrated circuit systems

    Energy Technology Data Exchange (ETDEWEB)

    Chu, D.; Palmer, D.W. [eds.

    1996-11-01

    A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

  8. Photonic integrated circuits: new challenges for lithography

    Science.gov (United States)

    Bolten, Jens; Wahlbrink, Thorsten; Prinzen, Andreas; Porschatis, Caroline; Lerch, Holger; Giesecke, Anna Lena

    2016-10-01

    In this work routes towards the fabrication of photonic integrated circuits (PICs) and the challenges their fabrication poses on lithography, such as large differences in feature dimension of adjacent device features, non-Manhattan-type features, high aspect ratios and significant topographic steps as well as tight lithographic requirements with respect to critical dimension control, line edge roughness and other key figures of merit not only for very small but also for relatively large features, are highlighted. Several ways those challenges are faced in today's low-volume fabrication of PICs, including the concept multi project wafer runs and mix and match approaches, are presented and possible paths towards a real market uptake of PICs are discussed.

  9. Parallel Jacobi EVD Methods on Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Chi-Chia Sun

    2014-01-01

    Full Text Available Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation.

  10. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  11. Integrated devices in digital circuit design

    Science.gov (United States)

    Hope, G. S.

    Aspects of combinational design are examined, taking into account logical operations, truth tables, Karnaugh maps as input output expressions, minimum forms, maximum forms, minterm forms, symbols, fundamental relationships, Karnaugh maps as design tools, the implementation of logic functions, logic and implementation, logic nor implementation, implementation examples, the exclusive or function, symmetrical forms, reduction, and practical circuits. Multiplexers and demultiplexers in combinational circuits are considered along with fundamental mode circuits, event-driven sequential circuits, event-driven circuit implementation using multiplexers, clock-driven sequential circuits, counters and multiplexers in clock-driven sequential circuits, state diagram construction, registers in logic design, a digital system, programming and programming aids, input and output techniques, operation and configuration of independent systems, and a definition of a Boolean algebra. Attention is also given to Intel's and Motorola's executable instructions.

  12. Topology Optimization of Building Blocks for Photonic Integrated Circuits

    DEFF Research Database (Denmark)

    Jensen, Jakob Søndergaard; Sigmund, Ole

    2005-01-01

    Photonic integrated circuits are likely candidates as high speed replacements for the standard electrical integrated circuits of today. However, in order to obtain a satisfactorily performance many design prob- lems that up until now have resulted in too high losses must be resolved. In this work...... we demonstrate how the method of topology optimization can be used to design a variety of high performance building blocks for the future circuits....

  13. Counterfeit integrated circuits detection and avoidance

    CERN Document Server

    Tehranipoor, Mark (Mohammad); Forte, Domenic

    2015-01-01

    This timely and exhaustive study offers a much-needed examination of the scope and consequences of the electronic counterfeit trade.  The authors describe a variety of shortcomings and vulnerabilities in the electronic component supply chain, which can result in counterfeit integrated circuits (ICs).  Not only does this book provide an assessment of the current counterfeiting problems facing both the public and private sectors, it also offers practical, real-world solutions for combatting this substantial threat.   ·      Helps beginners and practitioners in the field by providing a comprehensive background on the counterfeiting problem; ·      Presents innovative taxonomies for counterfeit types, test methods, and counterfeit defects, which allows for a detailed analysis of counterfeiting and its mitigation; ·      Provides step-by-step solutions for detecting different types of counterfeit ICs; ·      Offers pragmatic and practice-oriented, realistic solutions to counterfeit IC d...

  14. Securing Health Sensing Using Integrated Circuit Metric

    Directory of Open Access Journals (Sweden)

    Ruhma Tahir

    2015-10-01

    Full Text Available Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware “fingerprints”. The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner.

  15. Designing TSVs for 3D Integrated Circuits

    CERN Document Server

    Khan, Nauman

    2013-01-01

    This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits.  It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks.  Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available....

  16. Integrated differential high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Farch, Kjartan

    2015-01-01

    In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order...... to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption...

  17. Whole-Cell Bioreporters for the Detection of Bioavailable Metals

    Science.gov (United States)

    Hynninen, Anu; Virta, Marko

    Whole-cell bioreporters are living microorganisms that produce a specific, quantifiable output in response to target chemicals. Typically, whole-cell bioreporters combine a sensor element for the substance of interest and a reporter element coding for an easily detectable protein. The sensor element is responsible for recognizing the presence of an analyte. In the case of metal bioreporters, the sensor element consists of a DNA promoter region for a metal-binding transcription factor fused to a promoterless reporter gene that encodes a signal-producing protein. In this review, we provide an overview of specific whole-cell bioreporters for heavy metals. Because the sensing of metals by bioreporter microorganisms is usually based on heavy metal resistance/homeostasis mechanisms, the basis of these mechanisms will also be discussed. The goal here is not to present a comprehensive summary of individual metal-specific bioreporters that have been constructed, but rather to express views on the theory and applications of metal-specific bioreporters and identify some directions for future research and development.

  18. Design of 3D integrated circuits and systems

    CERN Document Server

    Sharma, Rohit

    2014-01-01

    Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

  19. Application specific integrated circuits and hybrid micro circuits for nuclear instrumentation

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sukhwani, Menka; Mukhopadhyay, P.K.; Shastrakar, R.S.; Sudheer, M.; Shedam, V.; Keni, Anubha

    2009-01-01

    Rapid development in semiconductor technology, sensors, detectors and requirements of high energy physics experiments as well as advances in commercially available nuclear instruments have lead to challenges for instrumentation. These challenges are met with development of Application Specific Integrated Circuits and Hybrid Micro Circuits. This paper discusses various activities in ASIC and HMC development in Bhabha Atomic Research Centre. (author)

  20. Parallel sparse direct solver for integrated circuit simulation

    CERN Document Server

    Chen, Xiaoming; Yang, Huazhong

    2017-01-01

    This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques. · Introduces complicated algorithms of sparse linear solvers, using concise principles and simple examples, without complex theory or lengthy derivations; · Describes a parallel sparse direct solver that can be adopted to accelerate any SPICE-like integrated circuit simulato...

  1. Wireless Luminescence Integrated Sensors (WLIS)

    Energy Technology Data Exchange (ETDEWEB)

    Simpson, M.L.; Sayler, G.S. (Univ. Tennessee)

    2003-11-10

    The goal of this project was the development of a family of wireless, single-chip, luminescence-sensing devices to solve a number of difficult distributed measurement problems in areas ranging from environmental monitoring and assessment to high-throughput screening of combinatorial chemistry libraries. These wireless luminescence integrated sensors (WLIS) consist of a microluminometer, wireless data transmitter, and RF power input circuit all realized in a standard integrated circuit (IC) process with genetically engineered, whole-cell, bioluminescent bioreporters encapsulated and deposited on the IC. The end product is a family of compact, low-power, rugged, low-cost sensors. As part of this program they developed an integrated photodiode/signal-processing scheme with an rms noise level of 175 electrons/second for a 13-minute integration time, and a quantum efficiency of 66% at the 490-nm bioluminescent wavelength. this performance provided a detection limit of < 1000 photons/second. Although sol-gel has previously been used to encapsulate yeast cells, the reaction conditions necessary for polymerization (primarily low pH) have beforehand proven too harsh for bacterial cell immobilizations. Utilizing sonication methods, they have were able to initiate polymerization under pH conditions conductive to cell survival. both a toluene bioreporter (Pseudomonas putida TVA8) and a naphthalene bioreporter (Pseudomonas fluorescens HK44) were successfully encapsulated in sol-gel and shown to produce a fairly significant bioluminescent response. In addition to the previously developed naphthalene- and toluene-sensitive bioreporters, they developed a yeast-based xenoestrogen reporter. This technology has been licensed by Micro Systems Technologies, a startup company in Dayton, Ohio for applications in environmental containments monitoring, and for detecting weapons of mass destruction (i.e. homeland security).

  2. Gate array type integrated circuits: technology and reliability

    International Nuclear Information System (INIS)

    Kumurdjian, P.

    1984-03-01

    This paper summarizes a study on a logical C-MOS circuit. After a short presentation, the technical parameters and performance desired are given. On this basis, the dispersion of measurements, according to the series, is examined. The processes of personalization are then analyzed. Finally, some results on the burn-in and aging of circuits are presented. This paper concludes with the methods adopted to obtain a reliable integrated circuit [fr

  3. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

    DEFF Research Database (Denmark)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

    2016-01-01

    -division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-oninsulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7x7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror......, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained...

  4. Integrated neuron circuit for implementing neuromorphic system with synaptic device

    Science.gov (United States)

    Lee, Jeong-Jun; Park, Jungjin; Kwon, Min-Woo; Hwang, Sungmin; Kim, Hyungjin; Park, Byung-Gook

    2018-02-01

    In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

  5. Carbon Nanotubes as Vertical Interconnects in 3D Integrated Circuits

    NARCIS (Netherlands)

    Vollebregt, S.

    2014-01-01

    Interconnects in integrated circuits (IC) are the major cause of power dissipation and delay. 3D integration has been proposed as a method to reduce these issues. For this 3D integration, fabrication of high aspect ratio reliable vertical interconnects (vias) are required. For this new materials,

  6. Integrating Neural Circuits Controlling Female Sexual Behavior

    Directory of Open Access Journals (Sweden)

    Paul E. Micevych

    2017-06-01

    Full Text Available The hypothalamus is most often associated with innate behaviors such as is hunger, thirst and sex. While the expression of these behaviors important for survival of the individual or the species is nested within the hypothalamus, the desire (i.e., motivation for them is centered within the mesolimbic reward circuitry. In this review, we will use female sexual behavior as a model to examine the interaction of these circuits. We will examine the evidence for a hypothalamic circuit that regulates consummatory aspects of reproductive behavior, i.e., lordosis behavior, a measure of sexual receptivity that involves estradiol membrane-initiated signaling in the arcuate nucleus (ARH, activating β-endorphin projections to the medial preoptic nucleus (MPN, which in turn modulate ventromedial hypothalamic nucleus (VMH activity—the common output from the hypothalamus. Estradiol modulates not only a series of neuropeptides, transmitters and receptors but induces dendritic spines that are for estrogenic induction of lordosis behavior. Simultaneously, in the nucleus accumbens of the mesolimbic system, the mating experience produces long term changes in dopamine signaling and structure. Sexual experience sensitizes the response of nucleus accumbens neurons to dopamine signaling through the induction of a long lasting early immediate gene. While estrogen alone increases spines in the ARH, sexual experience increases dendritic spine density in the nucleus accumbens. These two circuits appear to converge onto the medial preoptic area where there is a reciprocal influence of motivational circuits on consummatory behavior and vice versa. While it has not been formally demonstrated in the human, such circuitry is generally highly conserved and thus, understanding the anatomy, neurochemistry and physiology can provide useful insight into the motivation for sexual behavior and other innate behaviors in humans.

  7. Micro-relay technology for energy-efficient integrated circuits

    CERN Document Server

    Kam, Hei

    2015-01-01

    This book describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers and highlights the importance of co-design across design hierarchies when optimizing system performance (in this case, energy-efficiency). This book is ideal for researchers and engineers focused on semiconductors, integrated circuits, and energy efficient electronics. This book also: ·         Covers microsystem fabrication, MEMS device design, circuit design, circuit micro-architecture, and CAD ·         Describes work previously done in the field and also lays the groundwork and criteria for future energy-efficient device and system design ·         Maximizes reader insights into the design and modeling of micro-relay, micro-relay reliability, integrated circuit design with micro-relays, and more

  8. Integrated digital superconducting logic circuits for the quantum synthesizer. Report

    International Nuclear Information System (INIS)

    Buchholz, F.I.; Kohlmann, J.; Khabipov, M.; Brandt, C.M.; Hagedorn, D.; Balashov, D.; Maibaum, F.; Tolkacheva, E.; Niemeyer, J.

    2006-11-01

    This report presents the results, which were reached in the framework of the BMBF cooperative plan ''Quantum Synthesizer'' in the partial plan ''Integrated Digital Superconducting Logic Circuits''. As essential goal of the plan a novel instrument on the base of quantum-coherent superconducting circuits should be developed. which allows to generate praxis-relevant wave forms with quantum accuracy, the quantum synthesizer. The main topics of development of the reported partial plan lied at the one hand in the development of integrated, digital, superconducting circuit in rapid-single-flux (RSFQ) quantum logics for the pattern generator of the quantum synthesizer, at the other hand in the further development of the fabrication technology for the aiming of high circuit complexity. In order to fulfil these requirements at the PTB a new design system was implemented, based on the software of Cadence. Together with the required RSFQ extensions for the design of digital superconducting circuits was a platform generated, on which the reachable circuit complexity is exclusively limited by the technology parameters of the available fabrication technology: Physical simulations are with PSCAN up to a complexity of more than 1000 circuit elements possible; furthermore VHDL allows the verification of arbitrarily large circuit architectures. In accordance for this the production line at the PTB was brought to a level, which allows in Nb/Al-Al x O y /Nb SIS technology implementation the fabrication of highly integrable RSFQ circuit architectures. The developed and fabricated basic circuits of the pattern generator have proved correct functionality and reliability in the measuring operation. Thereby for the circular RSFQ shift registers a key role as local memories in the construction of the pattern generator is devolved upon. The registers were realized with the aimed bit lengths up to 128 bit and with reachable signal-processing speeds of above 10 GHz. At the interface RSFQ

  9. Integrated Reconfigurable High-Voltage Transmitting Circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2014-01-01

    In this paper a full high-voltage transmitting cir- cuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in ultrasound medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The CMUT is single-ended driven. The design is taped......-out and measurements are performed on the integrated circuit. The transmitting circuit is reconfigurable externally making it able to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes, pulse voltages up to 100 V, maximum pulse range of 50 V and frequencies up to 5 MHz. The area...

  10. Nano-Power Integrated Circuits for Energy Harvesting

    OpenAIRE

    Dini, Michele

    2015-01-01

    The energy harvesting research field has grown considerably in the last decade due to increasing interests in energy autonomous sensing systems, which require smart and efficient interfaces for extracting power from energy source and power management (PM) circuits. This thesis investigates the design trade-offs for minimizing the intrinsic power of PM circuits, in order to allow operation with very weak energy sources. For validation purposes, three different integrated power converter and PM...

  11. Molecular annotation of integrative feeding neural circuits.

    Science.gov (United States)

    Pérez, Cristian A; Stanley, Sarah A; Wysocki, Robert W; Havranova, Jana; Ahrens-Nicklas, Rebecca; Onyimba, Frances; Friedman, Jeffrey M

    2011-02-02

    The identity of higher-order neurons and circuits playing an associative role to control feeding is unknown. We injected pseudorabies virus, a retrograde tracer, into masseter muscle, salivary gland, and tongue of BAC-transgenic mice expressing GFP in specific neural populations and identified several CNS regions that project multisynaptically to the periphery. MCH and orexin neurons were identified in the lateral hypothalamus, and Nurr1 and Cnr1 in the amygdala and insular/rhinal cortices. Cholera toxin β tracing showed that insular Nurr1(+) and Cnr1(+) neurons project to the amygdala or lateral hypothalamus, respectively. Finally, we show that cortical Cnr1(+) neurons show increased Cnr1 mRNA and c-Fos expression after fasting, consistent with a possible role for Cnr1(+) neurons in feeding. Overall, these studies define a general approach for identifying specific molecular markers for neurons in complex neural circuits. These markers now provide a means for functional studies of specific neuronal populations in feeding or other complex behaviors. Copyright © 2011 Elsevier Inc. All rights reserved.

  12. Dielectric isolation for power integrated circuits; Isolation dielectrique enterree pour les circuits integres de puissance

    Energy Technology Data Exchange (ETDEWEB)

    Zerrouk, D.

    1997-07-18

    Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called `smart power` devices use either self isolation, junction isolation or Silicon-On-Insulator (SOI) to integrate low voltage elements with vertical power devices. Dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Thesis work consists of the study of the feasibility of a dielectric technology based on the melting and the solidification in a Rapid Thermal Processing furnace (RTP), of thick polysilicon films deposited on oxide. The purpose of this technique is to obtain substrate with localized SOI structures for smart power applications. SOI technology offers significant potential advantages, such as non-occurrence of latch-up in CMOS structures, high packaging density, low parasitic capacitance and the possibility of 3D structures. In addition, SOI technology using thick silicon films (10-100 {mu}m) offers special advantages for high voltage integrated circuits. Several techniques have been developed to form SOI films. Zone melting recrystallization is one of the most promising for localized SOI. The SOI structures have first been analyzed in term of extended defects. N-channel MOSFET`s transistors have also been fabricated in the SOI substrates and electrically characterized (threshold voltages, off-state leakage current, mobilities,...). The SOI transistors exhibit good characteristics, although inferior to witness transistors. The recrystallized silicon films are therefore found to be suitable for the fabrication of SOI devices. (author) 106 refs.

  13. Process Variations and Probabilistic Integrated Circuit Design

    CERN Document Server

    Haase, Joachim

    2012-01-01

    Uncertainty in key parameters within a chip and between different chips in the deep sub micron era plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process.  Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development.   This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits.  Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.  Trains IC designers to recognize problems caused by parameter variations during manufacturing and to choose the best methods available to mitigate these issues during the design process; Offers both qual...

  14. Radiation effects in semiconductors: technologies for hardened integrated circuits

    International Nuclear Information System (INIS)

    Charlot, J.M.

    1983-09-01

    Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technologie or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented

  15. Radiation effects in semiconductors: technologies for hardened integrated circuits

    International Nuclear Information System (INIS)

    Charlot, J.M.

    1984-01-01

    Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technology or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented. (author)

  16. Photonic integrated circuits based on silica and polymer PLC

    Science.gov (United States)

    Izuhara, T.; Fujita, J.; Gerhardt, R.; Sui, B.; Lin, W.; Grek, B.

    2013-03-01

    Various methods of hybrid integration of photonic circuits are discussed focusing on merits and challenges. Material platforms discussed in this report are mainly polymer and silica. We categorize the hybridization methods using silica and polymer waveguides into two types, chip-to-chip and on-chip integration. General reviews of these hybridization technologies from the past works are reviewed. An example for each method is discussed in details. We also discuss current status of our silica PLC hybrid integration technology.

  17. 3D circuit integration for Vertex and other detectors

    Energy Technology Data Exchange (ETDEWEB)

    Yarema, Ray; /Fermilab

    2007-09-01

    High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

  18. Analysis of failure during the manufacturing of integrated circuits

    Science.gov (United States)

    Damm, C.; Sirot, N.

    1982-09-01

    To maintain the electrical output of integrated circuits at a high and stable level, a special analysis of failure techniques is systematically applied to plates of integrated circuits that have abnormal output. Aspects discussed include: a synoptic table of operations for failure analysis; methodology; preliminary data; visual analysis of defects; demonstration of crystal defects; and electrical analysis. Some examples illustrate the advantages of the method which are the reduction of fabrication cost, and improvement of the quality and reliability of products in a comprehensive, controlled procedure.

  19. Silicon integrated circuits advances in materials and device research

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Silicon Integrated Circuits, Part B covers the special considerations needed to achieve high-power Si-integrated circuits. The book presents articles about the most important operations needed for the high-power circuitry, namely impurity diffusion and oxidation; crystal defects under thermal equilibrium in silicon and the development of high-power device physics; and associated technology. The text also describes the ever-evolving processing technology and the most promising approaches, along with the understanding of processing-related areas of physics and chemistry. Physicists, chemists, an

  20. Programmable delay unit incorporating a semi-custom integrated circuit

    International Nuclear Information System (INIS)

    Linstadt, E.

    1985-04-01

    The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

  1. Integrated circuits for particle physics experiments

    CERN Document Server

    Snoeys, W; Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Toifl, Thomas H; Wyllie, Ken H

    2000-01-01

    High energy particle physics experiments investigate the nature of matter through the identification of subatomic particles produced in collisions of protons, electrons, or heavy ions which have been accelerated to very high energies. Future experiments will have hundreds of millions of detector channels to observe the interaction region where collisions take place at a 40 MHz rate. This paper gives an overview of the electronics requirements for such experiments and explains how data reduction, timing distribution, and radiation tolerance in commercial CMOS circuits are achieved for these big systems. As a detailed example, the electronics for the innermost layers of the future tracking detector, the pixel vertex detector, is discussed with special attention to system aspects. A small-scale prototype (130 channels) implemented in standard 0.25 mu m CMOS remains fully functional after a 30 Mrad(SiO/sub 2/) irradiation. A full-scale pixel readout chip containing 8000 readout channels in a 14 by 16 mm/sup 2/ ar...

  2. Biochips: The Integrated Circuit of Biology

    DEFF Research Database (Denmark)

    Madsen, Jan

    2012-01-01

    Microfluidic biochips integrate different biochemical analysis functionalities (e.g., dispensers, filters, mixers, separators, detectors) on-chip, miniaturizing the macroscopic chemical and biological processes often processed by lab-robots, to a sub-millimeter scale. These microsystems offer...... the conventional biochemical analyzers, and areable to integrate on-chip all the necessary functions for biochemical analysis. Microfluidic biochips have an immense potential in multiple application areas, such as clinical diagnostics, advanced sequencing, drug discovery, and environmental monitoring, to name...... several advantages over the conventional biochemical analyzers, e.g., reduced sample and reagent volumes, speeded up biochemical reactions, ultra-sensitive detection and higher system throughput, with several assays being integrated on the same chip. Hence, microfluidic biochips are replacing...

  3. Printed organic thin-film transistor-based integrated circuits

    International Nuclear Information System (INIS)

    Mandal, Saumen; Noh, Yong-Young

    2015-01-01

    Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted. (paper)

  4. Photonic integrated circuits for NG-EPON

    Science.gov (United States)

    Rodrigues, Carla; Rodrigues, Francisco; Lima, Mário; Teixeira, António

    2017-08-01

    This paper intends to propose a monolithic photonic integrated InP transceiver for Next Generation of Ethernet Passive Optical Network (NG-EPON). The presented architecture was designed as an Optical Network Unit (ONU). The concept behind the suggested transceiver architecture is here presented together with the steps necessary to deploy the proposed solution.

  5. 77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

    Science.gov (United States)

    2012-05-01

    ... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit... States after importation of certain semiconductor integrated circuit devices and products containing same... importation, or the sale within the United States after importation of certain semiconductor integrated...

  6. Novel technique for reliability testing of silicon integrated circuits

    NARCIS (Netherlands)

    Le Minh, P.; Wallinga, Hans; Woerlee, P.H.; van den Berg, Albert; Holleman, J.

    2001-01-01

    We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon

  7. Performance of digital integrated circuit technologies at very high temperatures

    Energy Technology Data Exchange (ETDEWEB)

    Prince, J.L.; Draper, B.L.; Rapp, E.A.; Kromberg, J.N.; Fitch, L.T.

    1980-01-01

    Results of investigations of the performance and reliability of digital bipolar and CMOS integrated circuits over the 25 to 340/sup 0/C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results of experimental simulations of dielectrically isolated CMOS are also discussed. It was found that commercial Schottky clamped TTL, and dielectrically isolated, low power Schottky-clamped TTL, functioned to junction temperatures in excess of 325/sup 0/C. Standard gold doped TTL functioned only to 250/sup 0/C, while commercial, isolated I/sup 2/L functioned to the range 250/sup 0/C to 275/sup 0/C. Commercial junction isolated CMOS, buffered and unbuffered, functioned to the range 280/sup 0/C to 310/sup 0/C/sup +/, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340/sup 0/C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious life limiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated ciruits at temperatures in excess of 300/sup 0/C has been found.

  8. Classical Conditioning with Pulsed Integrated Neural Networks: Circuits and System

    DEFF Research Database (Denmark)

    Lehmann, Torsten

    1998-01-01

    In this paper we investigate on-chip learning for pulsed, integrated neural networks. We discuss the implementational problems the technology imposes on learning systems and we find that abiologically inspired approach using simple circuit structures is most likely to bring success. We develop a ...... chip to solve simple classical conditioning tasks, thus verifying the design methodologies put forward in the paper....

  9. Printed Circuit Board Integrated Toroidal Radio Frequency Inductors

    DEFF Research Database (Denmark)

    Kamby, Peter; Knott, Arnold; Andersen, Michael A. E.

    2012-01-01

    implemented as solenoids, either in spiral or cylindrical form. Those have the disadvantage of excessive stray fields, which can cause losses and disturbances in adjacent circuitry. Therefore this paper presents the analysis, design and realization of a printed circuit board (PCB) integrated inductor under...

  10. Applications of carbon nanotubes on integrated circuits

    Science.gov (United States)

    Zhang, Min

    The microelectronics technology falls within the boundaries of that definition. Carbon nanotube (CNT) is a promising alternative material for the future nanoelectronics. Owing to the unique properties of CNTs and the maturity of CMOS IC technology, the integration of the two technologies will take advantages of both. In this work, we demonstrate a new local silicon-gate carbon nanotube field-effect transistor (CNFET) by combining the in situ CNT growth technology and the SOI technology. The proposed CNFET structure has realized individual device operation, batch fabrication, low parasitics and better compatibility to the CMOS process at the same time. The configuration proposes a feasible approach to integrate the CNTs to CMOS platform for the first time, which makes CNT a step closer to application. The CNFETs show advanced DC characteristics. The ambipolar conductance and the scaling effect of the CNFETs have been analyzed based on the SB modulated conductance mechanism. Investigation of radio-frequency (RF) characteristics of CNTs is essential for their application. RF transmission characteristics of the semiconducting and metallic CNTs are investigated to the frequency of 12 GHz using the full two-port S-parameter methodology for the first time. Without the effect of the parasitics, the signal transmission capability of the CNTs maintains at a constant level and shows no degeneration even at a high frequency of 12 GHz. An empirical RLC element model has been proposed to fit the RF response of the CNT array. Capacitive contact is reported between the CNTs and the metal electrodes. We also explore the high-frequency properties of the local silicon-gate CNFET as an active device by measuring its S parameters using a common-source configuration. In addition, we demonstrate the application of CNT as via/contact filler to solve the problems of copper vias used in ICs nowadays. We have optimized the fabrication process for the CNT via integration. The CNT vias with

  11. Design of Integrated Circuits Approaching Terahertz Frequencies

    DEFF Research Database (Denmark)

    Yan, Lei

    are designed based on the monolithic membrane supported Schottky diodes, which is under development at Chalmers University of Technology, Sweden. To simplify the baseband circuitry, the received IF signal from the subharmonic mixer is further amplified and downconverted to the DC range with a low noise...... heterodyne receivers with requirements of room temperature operation, low system complexity, and high sensitivity, monolithic integrated Schottky diode technology is chosen for the implementation of submillimeterwave components. The corresponding subharmonic mixer and multiplier for a THz radiometer system...

  12. Laser Integration on Silicon Photonic Circuits Through Transfer Printing

    Science.gov (United States)

    2017-03-10

    silicon transfer printed single wavelength laser . Introduction Silicon has long offered promise as the ultimate platform for realizing compact photonic...the field has faced a big stumbling block: the lack of an integrated laser source. Thus far, silicon-photonics applications have had to rely on...AFRL-AFOSR-UK-TR-2017-0019 Laser integration on silicon photonic circuits through transfer printing Gunther Roelkens UNIVERSITEIT GENT VZW Final

  13. Radiation hardening of integrated circuits technologies

    International Nuclear Information System (INIS)

    Auberton-Herve, A.J.; Leray, J.L.

    1991-01-01

    The radiation hardening studies started in the mid decade -1960-1970. To survive the different military or space radiative environment, a new engineering science borned, to understand the degradation of electronics components. The different solutions to improve the electronic behavior in such environment, have been named radiation hardening of the technologies. Improvement of existing technologies, and qualification method have been widely studied. However, at the other hand, specific technologies was developped : The Silicon On Insulator technologies for CMOS or Bipolar. The HSOI3HD technology (supported by DGA-CEA DAM and LETI with THOMSON TMS) offers today the highest hardening level for the integration density of hundreds of thousand transistors on the same silicon. Full complex systems would be realized on a single die with a technological radiation hardening and no more system hardening

  14. Digital integrated circuit design using Verilog and SystemVerilog

    CERN Document Server

    Mehler, Ronald W

    2014-01-01

    For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

  15. Silicon compiler design of combinational and pipeline adder integrated circuits

    Science.gov (United States)

    Froede, A. O., III

    1985-06-01

    The architecture and structures used by the MacPitts silicon compiler to design integrated circuits are described, and the capabilities and limitations of the compiler are discussed. The performance of several combinational and pipeline adders designed by MacPitts and a hand-crafted pipeline adder are compared. Several different MacPitts design errors are documented. Tutorial material is presented to aid in using the MacPitts interpreter and to illustrate timing analysis of MacPitts-designed circuits using the program Crystal.

  16. Classical Conditioning with Pulsed Integrated Neural Networks: Circuits and System

    DEFF Research Database (Denmark)

    Lehmann, Torsten

    1998-01-01

    In this paper we investigate on-chip learning for pulsed, integrated neural networks. We discuss the implementational problems the technology imposes on learning systems and we find that abiologically inspired approach using simple circuit structures is most likely to bring success. We develop...... a suitable learning algorithm -- a continuous-time version of a temporal differential Hebbian learning algorithm for pulsed neural systems with non-linear synapses -- as well as circuits for the electronic implementation. Measurements from an experimental CMOS chip are presented. Finally, we use our test...

  17. RF and microwave integrated circuit development technology, packaging and testing

    CERN Document Server

    Gamand, Patrice; Kelma, Christophe

    2018-01-01

    RF and Microwave Integrated Circuit Development bridges the gap between existing literature, which focus mainly on the 'front-end' part of a product development (system, architecture, design techniques), by providing the reader with an insight into the 'back-end' part of product development. In addition, the authors provide practical answers and solutions regarding the choice of technology, the packaging solutions and the effects on the performance on the circuit and to the industrial testing strategy. It will also discuss future trends and challenges and includes case studies to illustrate examples. * Offers an overview of the challenges in RF/microwave product design * Provides practical answers to packaging issues and evaluates its effect on the performance of the circuit * Includes industrial testing strategies * Examines relevant RF MIC technologies and the factors which affect the choice of technology for a particular application, e.g. technical performance and cost * Discusses future trends and challen...

  18. Bioreporter Pseudomonas fluorescens HK44 Immobilized in a Silica Matrix

    Czech Academy of Sciences Publication Activity Database

    Trögl, Josef; Ripp, S.; Kuncová, Gabriela; Sayler, G. S.; Demnerová, K.

    2003-01-01

    Roč. 57, č. 12 (2003), s. 596-599 ISSN 0354-7531 R&D Projects: GA ČR GA104/01/0461 Institutional research plan: CEZ:AV0Z4072921 Keywords : bioluminescence bioreporter * optical sensor * naphthalene detection Subject RIV: CE - Biochemistry

  19. Detection of Buried Human Remains Using Bioreporter Fluorescence

    Energy Technology Data Exchange (ETDEWEB)

    Vass, A. Dr.; Singleton, G. B.

    2001-10-01

    The search for buried human remains is a difficult, laborious and time-consuming task for law enforcement agencies. This study was conducted as a proof of principle demonstration to test the concept of using bioreporter microorganisms as a means to cover large areas in such a search. These bioreporter microorganisms are affected by a particular component of decaying organic matter that is distinct from decaying vegetation. The diamino compounds cadaverine and putrescine were selected as target compounds for the proof-of-principle investigation, and a search for microorganisms and genes that are responsive to either of these compounds was conducted. One recombinant clone was singled out for characterization based on its response to putrescine. The study results show that small concentrations of putrescine increased expression from this bioreporter construct. Although the level of increase was small (making it difficult to distinguish the signal from background), the results demonstrate the principle that bioreporters can be used to detect compounds resulting from decaying human remains and suggest that a wider search for target compounds should be conducted.

  20. Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

    Science.gov (United States)

    Liu, Yuanda; Ang, Kah-Wee

    2017-07-25

    Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10 3 . Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

  1. Trends in integrated circuit design for particle physics experiments

    International Nuclear Information System (INIS)

    Atkin, E V

    2017-01-01

    Integrated circuits are one of the key complex units available to designers of multichannel detector setups. A whole number of factors makes Application Specific Integrated Circuits (ASICs) valuable for Particle Physics and Astrophysics experiments. Among them the most important ones are: integration scale, low power dissipation, radiation tolerance. In order to make possible future experiments in the intensity, cosmic, and energy frontiers today ASICs should provide new level of functionality at a new set of constraints and trade-offs, like low-noise high-dynamic range amplification and pulse shaping, high-speed waveform sampling, low power digitization, fast digital data processing, serialization and data transmission. All integrated circuits, necessary for physical instrumentation, should be radiation tolerant at an earlier not reached level (hundreds of Mrad) of total ionizing dose and allow minute almost 3D assemblies. The paper is based on literary source analysis and presents an overview of the state of the art and trends in nowadays chip design, using partially own ASIC lab experience. That shows a next stage of ising micro- and nanoelectronics in physical instrumentation. (paper)

  2. 77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

    Science.gov (United States)

    2012-10-04

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of Commission Determination Not To Review an Initial... certain semiconductor integrated circuit devices and products containing same by reason of infringement of...

  3. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Science.gov (United States)

    2012-03-29

    ... INTERNATIONAL TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated Circuit Devices and... the U.S. International Trade Commission has received a complaint entitled Certain Semiconductor... importation of certain semiconductor integrated circuit devices and products containing same. The complaint...

  4. 77 FR 39510 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not...

    Science.gov (United States)

    2012-07-03

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-840] Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not To Review an Initial Determination... certain semiconductor integrated circuit devices and products containing same by reason of infringement of...

  5. 75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

    Science.gov (United States)

    2010-02-04

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-665] In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice of Commission Determination To Review in... importation of certain semiconductor integrated circuits and products containing same by reason of...

  6. Status of readout integrated circuits for radiation detector

    International Nuclear Information System (INIS)

    Moon, B. S.; Hong, S. B.; Cheng, J. E. and others

    2001-09-01

    In this report, we describe the current status of readout integrated circuits developed for radiation detectors, along with new technologies being applied to this field. The current status of ASCIC chip development related to the readout electronics is also included in this report. Major sources of this report are from product catalogs and web sites of the related industries. In the field of semiconductor process technology in Korea, the current status of the multi-project wafer(MPW) of IDEC, the multi-project chip(MPC) of ISRC and other domestic semiconductor process industries is described. In the case of other countries, the status of the MPW of MOSIS in USA and the MPW of EUROPRACTICE in Europe is studied. This report also describes the technologies and products of readout integrated circuits of industries worldwide

  7. Design techniques for low-voltage analog integrated circuits

    Science.gov (United States)

    Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

    2017-08-01

    In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

  8. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    Science.gov (United States)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  9. Study of integrated circuits in natural space environment

    International Nuclear Information System (INIS)

    Karoui, S.

    1993-11-01

    In this thesis we study one of the critical phenomena induced by the radiation of integrated circuits in the natural space environment: the so-called upset phenomenon. This phenomenon, caused by a heavy-ion strike on circuit sensitive areas, result in the modification of the information stored in a memory element. Upsets may then perturb the functioning of satellite-borne complex processors with serious consequences on the control of equipments operating in space. As commonly used processes or design hardening techniques cannot guarantee a total immunity against upsets, provisional methods are generally adopted to select the less sensitive circuits among components to be used in a space application. These methods consist in the simulation of the irradiated environment by means of particle accelerators, to get experimental figures about the upset sensitivity of the considered circuit, and the use of these measures to estimate the in orbit circuit vulnerability. To implement such experiments on different processor types, we have designed and developed a dedicated test system, the FUTE 16 tester. This tester has been used in several test experiments where irradiated environment was simulated by means of particle accelerators. The activity of the target circuit during the irradiation could have a great influence on the measured upset sensitivity. Generally used test sequences so-called ''register test'', consist on the initialization of accessible registers with known data, and the observation of their content after a given delay to detect errors due to upsets. The main goal of this thesis is to compare in orbit error rate estimations obtained with register tests, to those obtained with ''application like'' test sequences. Both kinds of test sequences have been used during heavy-ion test experiments performed on commercially available CISC and RISC processors. The results obtained clearly show that using ''register tests'' may lead to wrong decisions in the selections

  10. Optimization of Segmentation Quality of Integrated Circuit Images

    Directory of Open Access Journals (Sweden)

    Gintautas Mušketas

    2012-04-01

    Full Text Available The paper presents investigation into the application of genetic algorithms for the segmentation of the active regions of integrated circuit images. This article is dedicated to a theoretical examination of the applied methods (morphological dilation, erosion, hit-and-miss, threshold and describes genetic algorithms, image segmentation as optimization problem. The genetic optimization of the predefined filter sequence parameters is carried out. Improvement to segmentation accuracy using a non optimized filter sequence makes 6%.Artcile in Lithuanian

  11. Integrated biocircuits: engineering functional multicellular circuits and devices

    Science.gov (United States)

    Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

    2018-04-01

    Objective. Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. Approach. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. Main results. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. Significance. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

  12. Arbitrary modeling of TSVs for 3D integrated circuits

    CERN Document Server

    Salah, Khaled; El-Rouby, Alaa

    2014-01-01

    This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor?and inductive-based

  13. Pneumatic oscillator circuits for timing and control of integrated microfluidics.

    Science.gov (United States)

    Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

    2013-11-05

    Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

  14. Integrating anatomy and function for zebrafish circuit analysis.

    Science.gov (United States)

    Arrenberg, Aristides B; Driever, Wolfgang

    2013-01-01

    Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties-e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function.

  15. Fully integrated circuit chip of microelectronic neural bridge

    Science.gov (United States)

    Xiaoyan, Shen; Zhigong, Wang

    2014-09-01

    Nerve tracts interruption is one of the major reasons for dysfunction after spiral cord injury. The microelectronic neural bridge is a method to restore function of interrupted neural pathways, by making use of microelectronic chips to bypass the injured nerve tracts. A low-power fully integrated microelectronic neural bridge chip is designed, using CSMC 0.5-μm CMOS technology. The structure and the key points in the circuit design will be introduced in detail. In order to meet the requirement for implantation, the circuit was modified to avoid the use of off-chip components, and fully monolithic integration is achieved. The operating voltage of the circuit is ±2.5 V, and the chip area is 1.21 × 1.18 mm2. According to the characteristic of neural signal, the time-domain method is used in testing. The pass bandwidth of the microelectronic neural bridge system covers the whole frequency range of the neural signal, power consumption is 4.33 mW, and the gain is adjustable. The design goals are achieved.

  16. Generation of optical vortices in an integrated optical circuit

    Science.gov (United States)

    Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

    2017-09-01

    In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = ‑1.

  17. 75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...

    Science.gov (United States)

    2010-12-06

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-648] Certain Semiconductor Integration... semiconductor integrated circuits using tungsten metallization and products containing the same by reason of...

  18. Integrated diode circuits for greater than 1 THz

    Science.gov (United States)

    Schoenthal, Gerhard Siegbert

    The terahertz frequency band, spanning from roughly 100 GHz to 10 THz, forms the transition from electronics to photonics. This band is often referred to as the "terahertz technology gap" because it lacks typical microwave and optical components. The deficit of terahertz devices makes it difficult to conduct important scientific measurements that are exclusive to this band in fields such as radio astronomy and chemical spectroscopy. In addition, a number of scientific, military and commercial applications will become more practical when a suitable terahertz technology is developed. UVa's Applied Electrophysics Laboratory has extended non-linear microwave diode technology into the terahertz region. Initial success was achieved with whisker-contacted diodes and then discrete planar Schottky diodes soldered onto quartz circuits. Work at UVa and the Jet Propulsion Laboratory succeeded in integrating this diode technology onto low dielectric substrates, thereby producing more practical components with greater yield and improved performance. However, the development of circuit integration technologies for greater than 1 THz and the development of broadly tunable sources of terahertz power remain as major research goals. Meeting these critical needs is the primary motivation for this research. To achieve this goal and demonstrate a useful prototype for one of our sponsors, this research project has focused on the development of a Sideband Generator at 1.6 THz. This component allows use of a fixed narrow band source as a tunable power source for terahertz spectroscopy and compact range radar. To prove the new fabrication and circuit technologies, initial devices were fabricated and tested at 200 and 600 GHz. These circuits included non-ohmic cathodes, air-bridged fingers, oxideless anode formation, and improved quartz integration processes. The excellent performance of these components validated these new concepts. The prototype process was then further optimized to

  19. Cell-based bioreporter assay coupled to HPLC micro-fractionation in the evaluation of antimicrobial properties of the basidiomycete fungus Pycnoporus cinnabarinus.

    Science.gov (United States)

    Järvinen, Päivi; Nybond, Susanna; Marcourt, Laurence; Ferreira Queiroz, Emerson; Wolfender, Jean-Luc; Mettälä, Aila; Karp, Matti; Vuorela, Heikki; Vuorela, Pia; Hatakka, Annele; Tammela, Päivi

    2016-01-01

    Identification of bioactive components from complex natural product extracts can be a tedious process that aggravates the use of natural products in drug discovery campaigns. This study presents a new approach for screening antimicrobial potential of natural product extracts by employing a bioreporter assay amenable to HPLC-based activity profiling. A library of 116 crude extracts was prepared from fungal culture filtrates by liquid-liquid extraction with ethyl acetate, lyophilised, and screened against Escherichia coli using TLC bioautography. Active extracts were studied further with a broth microdilution assay, which was, however, too insensitive for identifying the active microfractions after HPLC separation. Therefore, an assay based on bioluminescent E. coli K-12 (pTetLux1) strain was coupled with HPLC micro-fractionation. Preliminary screening yielded six fungal extracts with potential antimicrobial activity. A crude extract from a culture filtrate of the wood-rotting fungus, Pycnoporus cinnabarinus (Jacq.) P. Karst. (Polyporaceae), was selected for evaluating the functionality of the bioreporter assay in HPLC-based activity profiling. In the bioreporter assay, the IC50 value for the crude extract was 0.10 mg/mL. By integrating the bioreporter assay with HPLC micro-fractionation, the antimicrobial activity was linked to LC-UV peak of a compound in the chromatogram of the extract. This compound was isolated and identified as a fungal pigment phlebiarubrone. HPLC-based activity profiling using the bioreporter-based approach is a valuable tool for identifying antimicrobial compound(s) from complex crude extracts, and offers improved sensitivity and speed compared with traditional antimicrobial assays, such as the turbidimetric measurement.

  20. A novel readout integrated circuit for ferroelectric FPA detector

    Science.gov (United States)

    Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

    2017-11-01

    Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

  1. Thermionic integrated circuit technology for high power space applications

    International Nuclear Information System (INIS)

    Yadavalli, S.R.

    1984-01-01

    Thermionic triode and integrated circuit technology is in its infancy and it is emerging. The Thermionic triode can operate at relatively high voltages (up to 2000V) and at least tens of amperes. These devices, including their use in integrated circuitry, operate at high temperatures (800 0 C) and are very tolerant to nuclear and other radiations. These properties can be very useful in large space power applications such as that represented by the SP-100 system which uses a nuclear reactor. This paper presents an assessment of the application of thermionic integrated circuitry with space nuclear power system technology. A comparison is made with conventional semiconductor circuitry considering a dissipative shunt regulator for SP-100 type nuclear power system rated at 100 kW. The particular advantages of thermionic circuitry are significant reductions in size and mass of heat dissipation and radiation shield subsystems

  2. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  3. Investigation of Optimal Integrated Circuit Raster Image Vectorization Method

    Directory of Open Access Journals (Sweden)

    Leonas Jasevičius

    2011-03-01

    Full Text Available Visual analysis of integrated circuit layer requires raster image vectorization stage to extract layer topology data to CAD tools. In this paper vectorization problems of raster IC layer images are presented. Various line extraction from raster images algorithms and their properties are discussed. Optimal raster image vectorization method was developed which allows utilization of common vectorization algorithms to achieve the best possible extracted vector data match with perfect manual vectorization results. To develop the optimal method, vectorized data quality dependence on initial raster image skeleton filter selection was assessed.Article in Lithuanian

  4. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  5. Inspection of integrated circuits through the microfocus radiography technique

    International Nuclear Information System (INIS)

    Scofano, Carmelo Fabio; Staszczak, Eduardo Jose; Rebello, Joao Marcos Alcoforado

    1995-01-01

    The application of microfocus radiography technique for integrated circuits inspection is evaluated. The experiments were performed according to the international standards for micro-electronic components. In order to define the operational parameters, factors such as contrast and image definition were considered, and by varying the voltage and amperage applied to the X-ray apparatus it was tried to obtain radiographic images with an adequate resolution. the results show that this technique is a promising tool for evaluating these components. 17 refs., 16 figs., 2 tabs

  6. RELATIONAL THEORY APPLICATION FOR OPTIMAL DESIGN OF INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    D. V. Demidov

    2014-09-01

    Full Text Available This paper deals with a method of relational theory adaptation for integrated circuits CAD systems. A new algorithm is worked out for optimal search of implicit Don’t Care values for combinational multiple-level digital circuits. The algorithm is described in terms of the adapted relational theory that gives the possibility for a very simple algorithm description for both intuitive understanding and formal analysis. The proposed method makes it possible to apply progressive experience of relational databases in efficient implementation of relational algebra operations (including distributed ones. Comparative analysis of the proposed algorithm and a classic one for optimal search of implicit Don’t Cares is carried out. The analysis has proved formal correctness of the proposed algorithm and its considerably less worst-case complexity. The search of implicit Don’t Care values in the integrated circuits design makes it easier to optimize such characteristics of IC as chip area, power, verifiability and reliability. However, the classic algorithm for optimal search of implicit Don’t Care values is not used in practice due to its very high computational complexity. Application of algorithms for sub-optimal search doesn’t give the possibility to realize the potential of IC optimization to the full. Implementation of the proposed algorithm in IC CAD (a.k.a., EDA systems is adequate due to much lower computational complexity, and potentially makes it possible to improve the quality-development time ratio of IC (chip area, power, verifiability and reliability. Developed method gives the possibility for creation of distributed EDA system with higher computational power and, consequently, for design automation of more complex IC.

  7. TUTORIAL: Integrated circuit amplifiers for multi-electrode intracortical recording

    Science.gov (United States)

    Jochum, Thomas; Denison, Timothy; Wolf, Patrick

    2009-02-01

    Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

  8. Integrated circuit amplifiers for multi-electrode intracortical recording.

    Science.gov (United States)

    Jochum, Thomas; Denison, Timothy; Wolf, Patrick

    2009-02-01

    Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

  9. Development of optical packet and circuit integrated ring network testbed.

    Science.gov (United States)

    Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

    2011-12-12

    We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated. © 2011 Optical Society of America

  10. Mixed signal custom integrated circuit development for physics instrumentation

    Energy Technology Data Exchange (ETDEWEB)

    Britton, C.L. Jr.; Bryan, W.L.; Emery, M.S. [and others

    1998-10-01

    The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented.

  11. Integrated optoelectronic materials and circuits for optical interconnects

    International Nuclear Information System (INIS)

    Hutcheson, L.D.

    1988-01-01

    Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

  12. Numerical counting ratemeter with variable time constant and integrated circuits

    International Nuclear Information System (INIS)

    Kaiser, J.; Fuan, J.

    1967-01-01

    We present here the prototype of a numerical counting ratemeter which is a special version of variable time-constant frequency meter (1). The originality of this work lies in the fact that the change in the time constant is carried out automatically. Since the criterion for this change is the accuracy in the annunciated result, the integration time is varied as a function of the frequency. For the prototype described in this report, the time constant varies from 1 sec to 1 millisec. for frequencies in the range 10 Hz to 10 MHz. This prototype is built entirely of MECL-type integrated circuits from Motorola and is thus contained in two relatively small boxes. (authors) [fr

  13. Control technology for integrated circuit fabrication at Micro-Circuit Engineering, Incorporated, West Palm Beach, Florida

    Science.gov (United States)

    Mihlan, G. I.; Mitchell, R. I.; Smith, R. K.

    1984-07-01

    A survey to assess control technology for integrated circuit fabrication was conducted. Engineering controls included local and general exhaust ventilation, shielding, and personal protective equipment. Devices or work stations that contained toxic materials that were potentially dangerous were controlled by local exhaust ventilation. Less hazardous areas were controlled by general exhaust ventilation. Process isolation was used in the plasma etching, low pressure chemical vapor deposition, and metallization operations. Shielding was used in ion implantation units to control X-ray emissions, in contact mask alignes to limit ultraviolet (UV) emissions, and in plasma etching units to control radiofrequency and UV emissions. Most operations were automated. Use of personal protective equipment varied by job function.

  14. Perspective: The future of quantum dot photonic integrated circuits

    Directory of Open Access Journals (Sweden)

    Justin C. Norman

    2018-03-01

    Full Text Available Direct epitaxial integration of III-V materials on Si offers substantial manufacturing cost and scalability advantages over heterogeneous integration. The challenge is that epitaxial growth introduces high densities of crystalline defects that limit device performance and lifetime. Quantum dot lasers, amplifiers, modulators, and photodetectors epitaxially grown on Si are showing promise for achieving low-cost, scalable integration with silicon photonics. The unique electrical confinement properties of quantum dots provide reduced sensitivity to the crystalline defects that result from III-V/Si growth, while their unique gain dynamics show promise for improved performance and new functionalities relative to their quantum well counterparts in many devices. Clear advantages for using quantum dot active layers for lasers and amplifiers on and off Si have already been demonstrated, and results for quantum dot based photodetectors and modulators look promising. Laser performance on Si is improving rapidly with continuous-wave threshold currents below 1 mA, injection efficiencies of 87%, and output powers of 175 mW at 20 °C. 1500-h reliability tests at 35 °C showed an extrapolated mean-time-to-failure of more than ten million hours. This represents a significant stride toward efficient, scalable, and reliable III-V lasers on on-axis Si substrates for photonic integrate circuits that are fully compatible with complementary metal-oxide-semiconductor (CMOS foundries.

  15. Perspective: The future of quantum dot photonic integrated circuits

    Science.gov (United States)

    Norman, Justin C.; Jung, Daehwan; Wan, Yating; Bowers, John E.

    2018-03-01

    Direct epitaxial integration of III-V materials on Si offers substantial manufacturing cost and scalability advantages over heterogeneous integration. The challenge is that epitaxial growth introduces high densities of crystalline defects that limit device performance and lifetime. Quantum dot lasers, amplifiers, modulators, and photodetectors epitaxially grown on Si are showing promise for achieving low-cost, scalable integration with silicon photonics. The unique electrical confinement properties of quantum dots provide reduced sensitivity to the crystalline defects that result from III-V/Si growth, while their unique gain dynamics show promise for improved performance and new functionalities relative to their quantum well counterparts in many devices. Clear advantages for using quantum dot active layers for lasers and amplifiers on and off Si have already been demonstrated, and results for quantum dot based photodetectors and modulators look promising. Laser performance on Si is improving rapidly with continuous-wave threshold currents below 1 mA, injection efficiencies of 87%, and output powers of 175 mW at 20 °C. 1500-h reliability tests at 35 °C showed an extrapolated mean-time-to-failure of more than ten million hours. This represents a significant stride toward efficient, scalable, and reliable III-V lasers on on-axis Si substrates for photonic integrate circuits that are fully compatible with complementary metal-oxide-semiconductor (CMOS) foundries.

  16. Integrated Circuit Design in US High-Energy Physics

    Energy Technology Data Exchange (ETDEWEB)

    Geronimo, G. D. [Brookhaven National Lab. (BNL), Upton, NY (United States); Christian, D. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Bebek, C. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Garcia-Sciveres, M. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Lippe, H. V. D. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Haller, G. [SLAC National Accelerator Lab., Menlo Park, CA (United States); Grillo, AA [Univ. of California, Santa Cruz, CA (United States); Newcomer, M [Univ. of Pennsylvania, Philadelphia, PA (United States)

    2013-07-10

    This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies; Outlook of future technologies including 2.5D and 3D; Survey of ICs used in current experiments and ICs targeted for approved or proposed experiments; IC design at US institutes and recommendations for collaboration in the future.

  17. A neural circuit architecture for angular integration in Drosophila.

    Science.gov (United States)

    Green, Jonathan; Adachi, Atsuko; Shah, Kunal K; Hirokawa, Jonathan D; Magani, Pablo S; Maimon, Gaby

    2017-06-01

    Many animals keep track of their angular heading over time while navigating through their environment. However, a neural-circuit architecture for computing heading has not been experimentally defined in any species. Here we describe a set of clockwise- and anticlockwise-shifting neurons in the Drosophila central complex whose wiring and physiology provide a means to rotate an angular heading estimate based on the fly's angular velocity. We show that each class of shifting neurons exists in two subtypes, with spatiotemporal activity profiles that suggest different roles for each subtype at the start and end of tethered-walking turns. Shifting neurons are required for the heading system to properly track the fly's heading in the dark, and stimulation of these neurons induces predictable shifts in the heading signal. The central features of this biological circuit are analogous to those of computational models proposed for head-direction cells in rodents and may shed light on how neural systems, in general, perform integration.

  18. A computer system for the analysis of integrated circuit reliability

    Science.gov (United States)

    Mauri, P.

    1989-12-01

    The formulation of total reliability assessment of integrated circuits involves an increasing amount of knowledge and data and hence it requires increasing computerized assistance. To perform this an information system has been designed and implemented. Following engineering practice, the key features of the system are (1) the collection of different types of data, e.g. electrical parameter measurements and qualitative description of the mode and the mechanism of failure and (2) the implementation of procedures coming from methods often applied, e.g. statistical or new approaches, such as formalization of cause-effect chains as studied for artificial intelligence applications. The system architecture has been designed so as to allow direct user maintenance, and hence a quick updating of reliability knowledge and information. Furthermore, its modularity eases the implementation of new procedures. Computer support improves the quality of data analysis and allows for the application of new methods and models.

  19. Two multichannel integrated circuits for neural recording and signal processing.

    Science.gov (United States)

    Obeid, Iyad; Morizio, James C; Moxon, Karen A; Nicolelis, Miguel A L; Wolf, Patrick D

    2003-02-01

    We have developed, manufactured, and tested two analog CMOS integrated circuit "neurochips" for recording from arrays of densely packed neural electrodes. Device A is a 16-channel buffer consisting of parallel noninverting amplifiers with a gain of 2 V/V. Device B is a 16-channel two-stage analog signal processor with differential amplification and high-pass filtering. It features selectable gains of 250 and 500 V/V as well as reference channel selection. The resulting amplifiers on Device A had a mean gain of 1.99 V/V with an equivalent input noise of 10 microV(rms). Those on Device B had mean gains of 53.4 and 47.4 dB with a high-pass filter pole at 211 Hz and an equivalent input noise of 4.4 microV(rms). Both devices were tested in vivo with electrode arrays implanted in the somatosensory cortex.

  20. Custom Integrated Circuit Design for Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere

    plane and the signals received from each transmit burst area summed. Each receiving channel is required to individually amplify and delay its signal in order to correctly pre-beamform. The handheld probe delivers the data to a processing unit digitally, hence, analog to digital converters (ADCs...... of evaluating the feasibility of the transmitting and receiving circuitry of a handheld probe for portable ultrasound scanners, three integrated circuit prototypes have been fabricated. Measurements have been performed on all of them with satisfactory results. The first part of this project is focused......-sigma analog-to-digital converter (CTDS ADC) operating at a sampling frequency of 320 MHz, a SNR of 45 dB, occupying an area of 0.0175 mm2 and a power consumption of 0.594 mW. The CTDS ADC digitizes the signal before the pre-beamform summing is applied. The SNR of the ADC is directly linked to the picture...

  1. Enabling the Internet of Things from integrated circuits to integrated systems

    CERN Document Server

    2017-01-01

    This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a fresh perspective on how the IoT will evolve based on recent and foreseeable trends in the semiconductor industry, highlighting the key challenges, as well as the opportunities for circuit and system innovation to address them. This book describes what the IoT really means from the design point of view, and how the constraints imposed by applications translate into integrated circuit requirements and design guidelines. Chapter contributions equally come from industry and academia. After providing a system perspective on IoT nodes, this book focuses on state-of-the-art design techniques for IoT applications, encompassing the fundamental sub-systems encountered in Systems on Chip for IoT: ultra-low power digital architectures and circuits low- and zero-leakage memories (including emerging technologies) circuits for hardwar...

  2. SDN architecture for optical packet and circuit integrated networks

    Science.gov (United States)

    Furukawa, Hideaki; Miyazawa, Takaya

    2016-02-01

    We have been developing an optical packet and circuit integrated (OPCI) network, which realizes dynamic optical path, high-density packet multiplexing, and flexible wavelength resource allocation. In the OPCI networks, a best-effort service and a QoS-guaranteed service are provided by employing optical packet switching (OPS) and optical circuit switching (OCS) respectively, and users can select these services. Different wavelength resources are assigned for OPS and OCS links, and the amount of their wavelength resources are dynamically changed in accordance with the service usage conditions. To apply OPCI networks into wide-area (core/metro) networks, we have developed an OPCI node with a distributed control mechanism. Moreover, our OPCI node works with a centralized control mechanism as well as a distributed one. It is therefore possible to realize SDN-based OPCI networks, where resource requests and a centralized configuration are carried out. In this paper, we show our SDN architecture for an OPS system that configures mapping tables between IP addresses and optical packet addresses and switching tables according to the requests from multiple users via a web interface. While OpenFlow-based centralized control protocol is coming into widespread use especially for single-administrative, small-area (LAN/data-center) networks. Here, we also show an interworking mechanism between OpenFlow-based networks (OFNs) and the OPCI network for constructing a wide-area network, and a control method of wavelength resource selection to automatically transfer diversified flows from OFNs to the OPCI network.

  3. 77 FR 66481 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice...

    Science.gov (United States)

    2012-11-05

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions; Notice..., and the sale within the United States after importation of certain integrated circuits, chipsets, and... the following as respondents: MediaTek Inc. of Hsinchu City, Taiwan; Zoran Corporation of Sunnyvale...

  4. 77 FR 57589 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Science.gov (United States)

    2012-09-18

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions... Inc. of Hsinchu City, Taiwan (``MediaTek''); and Zoran Corporation of Sunnyvale, California (``Zoran... found that those Zoran products that were adjudicated in Integrated Circuits I are precluded under the...

  5. Integrated reconfigurable high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2015-01-01

    In this paper a high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in scanners for medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The transmitting circuit is reconfigurable externally making it able...... to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes with voltages up to 100 V, maximum pulse range of 50 V, frequencies up to 5 MHz and different driving slew rates. Measurements are performed on the circuit in order to assess its functionality and power consumption...

  6. Design structure for in-system redundant array repair in integrated circuits

    Science.gov (United States)

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

    2008-11-25

    A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  7. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    Science.gov (United States)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  8. Graphene-on-silicon hybrid plasmonic-photonic integrated circuits

    Science.gov (United States)

    Xiao, Ting-Hui; Cheng, Zhenzhou; Goda, Keisuke

    2017-06-01

    Graphene surface plasmons (GSPs) have shown great potential in biochemical sensing, thermal imaging, and optoelectronics. To excite GSPs, several methods based on the near-field optical microscope and graphene nanostructures have been developed in the past few years. However, these methods suffer from their bulky setups and low GSP-excitation efficiency due to the short interaction length between free-space vertical excitation light and the atomic layer of graphene. Here we present a CMOS-compatible design of graphene-on-silicon hybrid plasmonic-photonic integrated circuits that achieve the in-plane excitation of GSP polaritons as well as localized surface plasmon (SP) resonance. By employing a suspended membrane slot waveguide, our design is able to excite GSP polaritons on a chip. Moreover, by utilizing a graphene nanoribbon array, we engineer the transmission spectrum of the waveguide by excitation of localized SP resonance. Our theoretical and computational study paves a new avenue to enable, modulate, and monitor GSPs on a chip, potentially applicable for the development of on-chip electro-optic devices.

  9. PETRIC - A positron emission tomography readout integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

    2000-11-05

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

  10. Mathematical model of an integrated circuit cooling through cylindrical rods

    Directory of Open Access Journals (Sweden)

    Beltrán-Prieto Luis Antonio

    2017-01-01

    Full Text Available One of the main challenges in integrated circuits development is to propose alternatives to handle the extreme heat generated by high frequency of electrons moving in a reduced space that cause overheating and reduce the lifespan of the device. The use of cooling fins offers an alternative to enhance the heat transfer using combined a conduction-convection systems. Mathematical model of such process is important for parametric design and also to gain information about temperature distribution along the surface of the transistor. In this paper, we aim to obtain the equations for heat transfer along the chip and the fin by performing energy balance and heat transfer by conduction from the chip to the rod, followed by dissipation to the surrounding by convection. Newton's law of cooling and Fourier law were used to obtain the equations that describe the profile temperature in the rod and the surface of the chip. Ordinary differential equations were obtained and the respective analytical solutions were derived after consideration of boundary conditions. The temperature along the rod decreased considerably from the initial temperature (in contatct with the chip surface. This indicates the benefit of using a cilindrical rod to distribute the heat generated in the chip.

  11. Integrated circuits and electrode interfaces for noninvasive physiological monitoring.

    Science.gov (United States)

    Ha, Sohmyung; Kim, Chul; Chi, Yu M; Akinin, Abraham; Maier, Christoph; Ueno, Akinori; Cauwenberghs, Gert

    2014-05-01

    This paper presents an overview of the fundamentals and state of the-art in noninvasive physiological monitoring instrumentation with a focus on electrode and optrode interfaces to the body, and micropower-integrated circuit design for unobtrusive wearable applications. Since the electrode/optrode-body interface is a performance limiting factor in noninvasive monitoring systems, practical interface configurations are offered for biopotential acquisition, electrode-tissue impedance measurement, and optical biosignal sensing. A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-the-art IAs. Furthermore, fundamental principles and state-of-the-art technologies for electrode-tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission. Examples are presented of practical dry-contact and noncontact cardiac, respiratory, muscle and brain monitoring systems, and their clinical applications.

  12. Reactor protection system design using application specific integrated circuits

    International Nuclear Information System (INIS)

    Battle, R.E.; Bryan, W.L.; Kisner, R.A.; Wilson, T.L. Jr.

    1992-01-01

    Implementing reactor protection systems (RPS) or other engineering safeguard systems with application specific integrated circuits (ASICs) offers significant advantages over conventional analog or software based RPSs. Conventional analog RPSs suffer from setpoints drifts and large numbers of discrete analog electronics, hardware logic, and relays which reduce reliability because of the large number of potential failures of components or interconnections. To resolve problems associated with conventional discrete RPSs and proposed software based RPS systems, a hybrid analog and digital RPS system implemented with custom ASICs is proposed. The actual design of the ASIC RPS resembles a software based RPS but the programmable software portion of each channel is implemented in a fixed digital logic design including any input variable computations. Set point drifts are zero as in proposed software systems, but the verification and validation of the computations is made easier since the computational logic an be exhaustively tested. The functionality is assured fixed because there can be no future changes to the ASIC without redesign and fabrication. Subtle error conditions caused by out of order evaluation or time dependent evaluation of system variables against protection criteria are eliminated by implementing all evaluation computations in parallel for simultaneous results. On- chip redundancy within each RPS channel and continuous self-testing of all channels provided enhanced assurance that a particular channel is available and faults are identified as soon as possible for corrective actions. The use of highly integrated ASICs to implement channel electronics rather than the use of discrete electronics greatly reduces the total number of components and interconnections in the RPS to further increase system reliability. A prototype ASIC RPS channel design and the design environment used for ASIC RPS systems design is discussed

  13. Thermoreflectance temperature imaging of integrated circuits: calibration technique and quantitative comparison with integrated sensors and simulations

    International Nuclear Information System (INIS)

    Tessier, G; Polignano, M-L; Pavageau, S; Filloy, C; Fournier, D; Cerutti, F; Mica, I

    2006-01-01

    Camera-based thermoreflectance microscopy is a unique tool for high spatial resolution thermal imaging of working integrated circuits. However, a calibration is necessary to obtain quantitative temperatures on the complex surface of integrated circuits. The spatial and temperature resolutions reached by thermoreflectance are excellent (360 nm and 2.5 x 10 -2 K in 1 min here), but the precision is more difficult to assess, notably due to the lack of comparable thermal techniques at submicron scales. We propose here a Peltier element control of the whole package temperature in order to obtain calibration coefficients simultaneously on several materials visible on the surface of the circuit. Under high magnifications, movements associated with thermal expansion are corrected using a piezo electric displacement and a software image shift. This calibration method has been validated by comparison with temperatures measured using integrated thermistors and diodes and by a finite volume simulation. We show that thermoreflectance measurements agree within a precision of ±2.3% with the on-chip sensors measurements. The diode temperature is found to underestimate the actual temperature of the active area by almost 70% due to the thermal contact of the diode with the substrate, acting as a heat sink

  14. High-speed Integrated Circuits for electrical/Optical Interfaces

    DEFF Research Database (Denmark)

    Jespersen, Christoffer Felix

    2008-01-01

    circuits at the receiver interface, though VCOs are also found in the transmitter where a multitude of independent sources have to be mutually synchronized before multiplexing. The circuits are based on an InP DHBT process (VIP-2) supplied by Vitesse and made publicly available as MPW. The VIP-2 process...

  15. Preconcentration and Detection of Mercury with Bioluminescent Bioreporter E. coli ARL1.

    Czech Academy of Sciences Publication Activity Database

    Solovyev, Andrey; Koštejn, Martin; Kuncová, Gabriela; Dostálek, P.; Rohovec, Jan; Navrátil, Tomáš

    2015-01-01

    Roč. 99, č. 20 (2015), s. 8793-8802 ISSN 0175-7598 Institutional support: RVO:67985858 ; RVO:67985831 Keywords : mercury detection * bioreporters * biosorbents Subject RIV: CC - Organic Chemistry Impact factor: 3.376, year: 2015

  16. Silicon-based photonic integrated circuit for label-free biosensing

    OpenAIRE

    Samusenko, Alina

    2016-01-01

    Silicon-based Photonic Integrated Circuit (PIC) is a device that integrates several optical components using the mature semiconductor technology platform, developed through years for the needs of electronic integrated circuits. In recent years, silicon PICs have been demonstrated as a powerful platform for biosensing systems - devices which play an omnipresent role in such essential life aspects as health care, environmental monitoring, food safety, etc. The growing importance of silicon phot...

  17. Test results of a 90 MHz integrated circuit sixteen channel analog pipeline for SSC detector calorimetry

    International Nuclear Information System (INIS)

    Kleinfelder, S.; Levi, M.; Milgrome, O.

    1990-01-01

    A sixteen channel analog transient recorder with 128 cells per channel has been fabricated as an integrated circuit and tested at speeds of up to 90 MHz. The circuit uses a switched capacitor array technology to achieve a simultaneous read and write capability and twelve bit dynamic range. The high performance of this part should satisfy the demanding electronics requirements of calorimeter detectors at the SSC. The circuit parameters and test results are presented

  18. Miniaturized ultrasound imaging probes enabled by CMUT arrays with integrated frontend electronic circuits.

    Science.gov (United States)

    Khuri-Yakub, B T; Oralkan, Omer; Nikoozadeh, Amin; Wygant, Ira O; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O'Donnell, Matthew; Truong, Uyen; Sahn, David J

    2010-01-01

    Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics.

  19. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    Directory of Open Access Journals (Sweden)

    Heck Martijn J.R.

    2016-06-01

    Full Text Available Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  20. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    Science.gov (United States)

    Heck, Martijn J. R.

    2017-01-01

    Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  1. Ultra low-power integrated circuit design for wireless neural interfaces

    CERN Document Server

    Holleman, Jeremy; Otis, Brian

    2014-01-01

    Presenting results from real prototype systems, this volume provides an overview of ultra low-power integrated circuits and systems for neural signal processing and wireless communication. Topics include analog, radio, and signal processing theory and design for ultra low-power circuits.

  2. Prediction of ionizing radiation effects in integrated circuits using black-box models

    International Nuclear Information System (INIS)

    Williamson, P.W.

    1976-10-01

    A method is described which allows general black-box modelling of integrated circuits as distinct from the existing method of deriving the radiation induced response of the model from actual terminal measurements on the device during irradiation. Both digital and linear circuits are discussed. (author)

  3. Bioreporter pseudomonas fluorescens HK44 immobilized in a silica matrix

    Directory of Open Access Journals (Sweden)

    Trogl J.

    2003-01-01

    Full Text Available The bioluminescent bioreporter Pseudomonas fluorescens HK44, the whole cell bacterial biosensor that responds to naphthalene and its metabolites via the production of visible light, was immobilized into a silica matrix by the sol-gel technique. The bioluminescence intensities were measured in the maximum of the bioluminescence band at X = 500 nm. The immobilized cells (>105 cells per g silica matrix produced light after induction by salicylate (cone. > 10 g/l, naphthalene and aminobenzoic acid. The bioluminescence intensities induced by 2,3-dihydroxynaphthalene 3-hydroxybenzoic acid and 4-hydroxybenzoic acid were comparable to a negative control. The cells in the silica layers on glass slides produced light in response to the presence of an inductor at least 8 months after immobilization, and >50 induction cycles. The results showed that these test slides could be used as assays for the multiple determination of water pollution.

  4. Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator.

    Science.gov (United States)

    Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

    2016-01-01

    The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex.

  5. Waveguide Phase Modulator for Integrated Planar Lightwave Circuits in KTP Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This SBIR Phase II effort proposes the development and integration of a Planar Lightwave Circuit (PLC) into an all fiber-based seed laser system used in high...

  6. A review of the technology and process on integrated circuits failure analysis applied in communications products

    Science.gov (United States)

    Ming, Zhimao; Ling, Xiaodong; Bai, Xiaoshu; Zong, Bo

    2016-02-01

    The failure analysis of integrated circuits plays a very important role in the improvement of the reliability in communications products. This paper intends to mainly introduce the failure analysis technology and process of integrated circuits applied in the communication products. There are many technologies for failure analysis, include optical microscopic analysis, infrared microscopic analysis, acoustic microscopy analysis, liquid crystal hot spot detection technology, optical microscopic analysis technology, micro analysis technology, electrical measurement, microprobe technology, chemical etching technology and ion etching technology. The integrated circuit failure analysis depends on the accurate confirmation and analysis of chip failure mode, the search of the root failure cause, the summary of failure mechanism and the implement of the improvement measures. Through the failure analysis, the reliability of integrated circuit and rate of good products can improve.

  7. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Document Server

    Garcia-Sciveres, M; CERN. Geneva. The LHC experiments Committee; LHCC

    2013-01-01

    Letter of Intent for RD Collaboration Proposal focused on development of a next generation pixel readout integrated circuits needed for high luminosity LHC detector upgrades. Brings together ATLAS and CMS pixel chip design communities.

  8. Experimental Demonstration of 7 Tb/s Switching Using Novel Silicon Photonic Integrated Circuit

    DEFF Research Database (Denmark)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

    2016-01-01

    We demonstrate BER performance <10^-9 for a 1 Tb/s/core transmission over 7-core fiber and SDM switching using a novel silicon photonic integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers.......We demonstrate BER performance Tb/s/core transmission over 7-core fiber and SDM switching using a novel silicon photonic integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers....

  9. On-Board Memory Extension on Reconfigurable Integrated Circuits using External DDR3 Memory

    OpenAIRE

    Lodaya, Bhaveen

    2018-01-01

    User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio o...

  10. Design of a semi-custom integrated circuit for the SLAC SLC timing control system

    International Nuclear Information System (INIS)

    Linstadt, E.

    1984-10-01

    A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given

  11. Integrated-Circuit Controller For Brushless dc Motor

    Science.gov (United States)

    Le, Dong Tuan

    1994-01-01

    Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

  12. Principal working group 3 on primary circuit integrity

    International Nuclear Information System (INIS)

    1992-01-01

    The main themes of this conference (13 papers) are: operating experience on leakages and failures in nuclear power plant piping, coolant circuits and steam generator tubes, probabilistic estimation and risk assessment, system failure analysis, leakage events and frequency, leak rate models and crack propagation mechanics, damage mechanisms and rupture probability

  13. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  14. Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

    Directory of Open Access Journals (Sweden)

    Yuharu Shinki

    2017-08-01

    Full Text Available This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

  15. V-band low-noise integrated circuit receiver. [for space communication systems

    Science.gov (United States)

    Chang, K.; Louie, K.; Grote, A. J.; Tahim, R. S.; Mlinar, M. J.; Hayashibara, G. M.; Sun, C.

    1983-01-01

    A compact low-noise V-band integrated circuit receiver has been developed for space communication systems. The receiver accepts an RF input of 60-63 GHz and generates an IF output of 3-6 GHz. A Gunn oscillator at 57 GHz is phaselocked to a low-frequency reference source to achieve high stability and low FM noise. The receiver has an overall single sideband noise figure of less than 10.5 dB and an RF to IF gain of 40 dB over a 3-GHz RF bandwidth. All RF circuits are fabricated in integrated circuits on a Duroid substrate.

  16. Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Lun Li

    2006-04-01

    Full Text Available The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stages can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses upon a technique that integrates the best characteristics of both simulation and formal verification methods to provide an effective design validation tool, referred as Integrated Design Validation (IDV. The novelty in this approach consists of three components, circuit complexity analysis, partitioning based on design hierarchy, and coverage analysis. The circuit complexity analyzer and partitioning decompose a large design into sub-components and feed sub-components to different verification and/or simulation tools based upon known existing strengths of modern verification and simulation tools. The coverage analysis unit computes the coverage of design validation and improves the coverage by further partitioning. Various simulation and verification tools comprising IDV are evaluated and an example is used to illustrate the overall validation process. The overall process successfully validates the example to a high coverage rate within a short time. The experimental result shows that our approach is a very promising design validation method.

  17. Physical and electrical characterization of corundum substrates and epitaxial silicon layers in view of fabricating integrated circuits

    International Nuclear Information System (INIS)

    Trilhe, J.; Legal, H.; Rolland, G.

    1975-01-01

    The S.O.S. technology (silicon on insulating substrate) allows compact, radiation hard, fast integrated circuits to be fabricated. It is noticeable that complex integrated circuits on corundum substrates obtained with various fabrication processes have various electrical characteristics. Possible correlations between the macroscopic defects of the substrate and the electrical characteristics of the circuit were investigated [fr

  18. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  19. Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

    Science.gov (United States)

    Buehler, M. G. (Inventor)

    1985-01-01

    An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

  20. Stochastic Simulation of Integrated Circuits with Nonlinear Black-Box Components via Augmented Deterministic Equivalents

    Directory of Open Access Journals (Sweden)

    MANFREDI, P.

    2014-11-01

    Full Text Available This paper extends recent literature results concerning the statistical simulation of circuits affected by random electrical parameters by means of the polynomial chaos framework. With respect to previous implementations, based on the generation and simulation of augmented and deterministic circuit equivalents, the modeling is extended to generic and ?black-box? multi-terminal nonlinear subcircuits describing complex devices, like those found in integrated circuits. Moreover, based on recently-published works in this field, a more effective approach to generate the deterministic circuit equivalents is implemented, thus yielding more compact and efficient models for nonlinear components. The approach is fully compatible with commercial (e.g., SPICE-type circuit simulators and is thoroughly validated through the statistical analysis of a realistic interconnect structure with a 16-bit memory chip. The accuracy and the comparison against previous approaches are also carefully established.

  1. Scalable Testing Platform for CMOS Read In Integrated Circuits

    Science.gov (United States)

    2016-03-31

    to the test RIIC. The critical feature of the BRT board is a zero insertion force (ZIF) DIP socket that sits in the middle, which allows us to modify...PGA) package because it has a PGA socket that breaks out all of the necessary RIIC signals. This allows the control signals from the computer to be...One is programmed to do voltage sweeps of the pixel circuits in the RIIC (7 in Figure 1), and the other Keithley measures the output super-lattice

  2. Monolithic integration of photonic and electronic circuits in a CMOS process

    Science.gov (United States)

    Mekis, Attila; Abdalla, Sherif; Analui, Behnam; Gloeckner, Steffen; Guckenberger, Andrew; Koumans, Roger; Kucharski, Daniel; Liang, Yi; Masini, Gianlorenzo; Mirsaidi, Sina; Narasimha, Adithyaram; Pinguet, Thierry; Sadagopan, Vikram; Welch, Brian; White, Joe; Witzens, Jeremy

    2008-02-01

    We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission speed and report on its performance.

  3. Analog Integrated Circuit Design for Spike Time Dependent Encoder and Reservoir in Reservoir Computing Processors

    Science.gov (United States)

    2018-01-01

    nonlinear function was modeled [50] with three fabricated analog multipliers (AD633) [51] and multiple operational amplifiers (op- amp ) (AD712) [52...output signals of these electronic circuit are usually limited to several hundred nanovolts. An op- amp with a finite gain of 109 is normally required to...Op- AMPs ) are not necessary. This project resulted in the design of an agile analog integrated circuit implementation of a spike-time encoding

  4. Thermal Management in Fine-Grained 3-D Integrated Circuits

    OpenAIRE

    Iqbal, Md Arif; Macha, Naveen Kumar; Danesh, Wafi; Hossain, Sehtab; Rahman, Mostafizur

    2018-01-01

    For beyond 2-D CMOS logic, various 3-D integration approaches specially transistor based 3-D integrations such as monolithic 3-D [1], Skybridge [2], SN3D [3] holds most promise. However, such 3D architectures within small form factor increase hotspots and demand careful consideration of thermal management at all levels of integration [4] as stacked transistors are detached from the substrate (i.e., heat sink). Traditional system level approaches such as liquid cooling [5], heat spreader [6], ...

  5. Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

    Science.gov (United States)

    Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

    2012-10-21

    Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

  6. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    Science.gov (United States)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  7. Method and apparatus for in-system redundant array repair on integrated circuits

    Science.gov (United States)

    Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

    2008-07-08

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  8. Data Transformation in a Three Dimensional Integrated Circuit Implementation

    Science.gov (United States)

    2012-03-01

    enforcing data integrity is cryptographical hash functions. • Authentication is the process that verifies the identity of a specific entity involved in a...Using this primitive, the integrity of data can be enforced . It is feasible for any entity to reproduce the message digest from the same stream of...14th Annual IEEE International ASIC /SOC Conference, Sept. 2001. [17] B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D

  9. Integrated equipment for increasing and maintaining coolant pressure in primary circuit of PWR nuclear power plant

    International Nuclear Information System (INIS)

    Sykora, D.

    1986-01-01

    An open heat pump circuit is claimed connected to the primary circuit. The pump circuit consists of a steam pressurizer with a built-in steam distributor, a compressor, an expander, a reducing valve, an auxiliary pump, and of water and steam pipes. The operation is described and a block diagram is shown of integrated equipment for increasing and maintaining pressure in the nuclear power plant primary circuit. The appropriate entropy diagram is also shown. The advantage of the open pump circuit consists in reducing the electric power input and electric power consumption for the steam pressurizers, removing entropy loss in heat transfer with high temperature gradient, in the possibility of inserting, between the expander and the auxiliary pump, a primary circuit coolant treatment station, in simplified design and manufacture of the high-pressure steam pressurizer vessel, reducing the weight of the steam pressurizer by changing its shape from cylindrical to spherical, increasing the rate of pressure growth in the primary circuit. (E.S.)

  10. Printed Circuit Board Signal Integrity Analysis at CERN: POSTER 1/2 Workshop

    CERN Document Server

    Evans, John

    2001-01-01

    Printed circuit board (PCB) design layout for digital circuits has become a critical issue due to increasing clock frequencies and faster signal switching times. The Cadence SPECCTRAQuest package allows the detailed signal integrity (SI) analysis of designs from the schematic-entry phase to the board level. It is fully integrated into the Cadence PCB design flow and can be used to reduce prototype iterations and improve production robustness. Examples are given on how the tool can help engineers to make design choices and how to optimise board layout for electrical performance. Case studies of work done for LHC detectors are presented.

  11. Printed Circuit Board Signal Integrity Analysis at CERN: POSTER 2/2 Workshop

    CERN Document Server

    Evans, John

    2001-01-01

    Printed circuit board (PCB) design layout for digital circuits has become a critical issue due to increasing clock frequencies and faster signal switching times. The Cadence SPECCTRAQuest package allows the detailed signal integrity (SI) analysis of designs from the schematic-entry phase to the board level. It is fully integrated into the Cadence PCB design flow and can be used to reduce prototype iterations and improve production robustness. Examples are given on how the tool can help engineers to make design choices and how to optimise board layout for electrical performance. Case studies of work done for LHC detectors are presented.

  12. A study of Latchup phenomenon induced in integrated circuits subject to an radiation field environment

    International Nuclear Information System (INIS)

    Merabtine, Nadjim; Sadaoui, Djaouida; Benslama, Malek

    2007-01-01

    [Text of English abstract is entered here]. The electronic equipment operated in hostile environment can undergo beside failures due to the normal component aging, degradation due to the environmental conditions of functioning. The interaction of the particles composing a radiation environment with materials within an integrated circuit can induce failures perturbing its functioning or eventually its destruction. The study of the radiation effects on integrated circuits particularly of the Latchup effect aims at evaluating the reliability of electronic systems subject to radiation. The objective of this work will be focused especially upon the Latchup phenomenon induced in the implied components. (authors) [fr

  13. Method for Evaluating the Corrosion Resistance of Aluminum Metallization of Integrated Circuits under Multifactorial Influence

    Science.gov (United States)

    Kolomiets, V. I.

    2018-03-01

    The influence of complex influence of climatic factors (temperature, humidity) and electric mode (supply voltage) on the corrosion resistance of metallization of integrated circuits has been considered. The regression dependence of the average time of trouble-free operation t on the mentioned factors has been established in the form of a modified Arrhenius equation that is adequate in a wide range of factor values and is suitable for selecting accelerated test modes. A technique for evaluating the corrosion resistance of aluminum metallization of depressurized CMOS integrated circuits has been proposed.

  14. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  15. Integrated circuit failure analysis by low-energy charge-induced voltage alteration

    Science.gov (United States)

    Cole, Jr., Edward I.

    1996-01-01

    A scanning electron microscope apparatus and method are described for detecting and imaging open-circuit defects in an integrated circuit (IC). The invention uses a low-energy high-current focused electron beam that is scanned over a device surface of the IC to generate a charge-induced voltage alteration (CIVA) signal at the location of any open-circuit defects. The low-energy CIVA signal may be used to generate an image of the IC showing the location of any open-circuit defects. A low electron beam energy is used to prevent electrical breakdown in any passivation layers in the IC and to minimize radiation damage to the IC. The invention has uses for IC failure analysis, for production-line inspection of ICs, and for qualification of ICs.

  16. An integrated energy-efficient capacitive sensor digital interface circuit

    KAUST Repository

    Omran, Hesham

    2014-06-19

    In this paper, we propose an energy-efficient 13-bit capacitive sensor interface circuit. The proposed design fully relies on successive approximation algorithm, which eliminates the need for oversampling and digital decimation filtering, and thus low-power consumption is achieved. The proposed architecture employs a charge amplifier stage to acheive parasitic insensitive operation and fine absolute resolution. Moreover, the output code is not affected by offset voltages or charge injection. The successive approximation algorithm is implemented in the capacitance-domain using a coarse-fine programmable capacitor array, which allows digitizing wide capacitance range in compact area. Analysis for the maximum achievable resolution due to mismatch is provided. The proposed design is insensitive to any reference voltage or current which translates to low temperature sensitivity. The operation of a prototype fabricated in a standard CMOS technology is experimentally verified using both on-chip and off-chip capacitive sensors. Compared to similar prior work, the fabricated prototype achieves and excellent energy efficiency of 34 pJ/step.

  17. An integrated circuit for wireless ambulatory arrhythmia monitoring systems.

    Science.gov (United States)

    Kim, Hyejung; Yazicioglu, Refet Firat; Torfs, Tom; Merken, Patrick; Van Hoof, Chris; Yoo, Hoi-Jun

    2009-01-01

    An ECG signal processor (ESP) is proposed for the low energy wireless ambulatory arrhythmia monitoring system. The ECG processor mainly performs filtering, compression, classification and encryption. The data compression flow consisting of skeleton and modified Huffman coding is the essential function to reduce the transmission energy consumption and the memory capacity, which are the most energy consuming part. The classification flow performs the arrhythmia analysis to alert the abnormality. The proposed ESP IC is implemented in 0.18-microm CMOS process and integrated into the wireless arrhythmia monitoring sensor platform. By integration of the ESP, the total system energy reduction is evaluated by 95.6%.

  18. Integrative Strategy for Effective Teaching of Alternating Circuits in ...

    African Journals Online (AJOL)

    One of the reasons advanced for the low enrolment and achievement of students in Physics at both secondary and post-secondary schools is poor teaching strategies used by teachers of Physics particularly in teaching Physics concepts classified by students as being difficult. In this paper, integrative strategy for effective ...

  19. W-band Phased Array Systems using Silicon Integrated Circuits

    Science.gov (United States)

    Kim, Sang Young

    This thesis presents the silicon-based on-chip W-band phased array systems. An improved quadrature all-pass filter (QAF) and its implementation in 60--80 GHz active phase shifter using 0.13 microm SiGe BiCMOS technology is presented. It is demonstrated that with the inclusion of an Rs/R in the high Q branches of C and L, the sensitivity to the loading capacitance, therefore the I/Q phase and amplitude errors are minimized. This technique is especially suited for wideband millimeter-wave circuits where the loading capacitance (CL) is comparable to the filter capacitance (C). A prototype 60--80 GHz active phased shifter using the improved QAF is demonstrated. The overall chip size is 1.15 x 0.92 mm2 with the power consumption of 108 mW. The measured S11 and S22 are pass pi-network. The chip size is 0.45 x 0.3 mm2 without pads and consumes virtually no power. The measured S11 and S22 is 8 dBm and the simulated IIP3 is > 22 dBm. A low-power 76--84 GHz 4-element phased array receiver using the designed passive phase shifter is presented. The power consumption is minimized by using a single-ended design and alternating the amplifiers and phase shifter cells to result in a low noise figure at a low power consumption. A variable gain amplifier and the 11° phase shifter are used to correct for the rms gain and phase errors at different operating frequencies. The overall chip size is 2.0 x 2.7 mm2 with the current consumption of 18 mA/channel with 1.8 V supply voltage. The measured S11 and S 22 is circuits are designed differentially to result in less sensitivity to packaging effect and high channel-to-channel isolation. The overall chip size is 5.0 x 5.8 mm 2 with the power consumption of 500--600 mA from 2 V supply voltage. The measured S11 and S22 for all 16 phase states is 10 dB for 76.4--90 GHz with the rms gain error of -45 dB. The measured NF is 11.2--13 dB at 77--87 GHz at the maximum gain state. And the measured input P1dB is 20 dBm at 77 GHz and -25.8 dBm at the

  20. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    Energy Technology Data Exchange (ETDEWEB)

    Arefin, Md Shamsul, E-mail: md.arefin@monash.edu; Redoute, Jean-Michel; Rasit Yuce, Mehmet [Electrical and Computer Systems Engineering, Monash University, Melbourne (Australia); Bulut Coskun, M.; Alan, Tuncay; Neild, Adrian [Mechanical and Aerospace Engineering, Monash University, Melbourne (Australia)

    2014-06-02

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  1. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    International Nuclear Information System (INIS)

    Arefin, Md Shamsul; Redoute, Jean-Michel; Rasit Yuce, Mehmet; Bulut Coskun, M.; Alan, Tuncay; Neild, Adrian

    2014-01-01

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  2. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    Science.gov (United States)

    Arefin, Md Shamsul; Bulut Coskun, M.; Alan, Tuncay; Redoute, Jean-Michel; Neild, Adrian; Rasit Yuce, Mehmet

    2014-06-01

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0-5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  3. Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability.

    Science.gov (United States)

    Lu, Zeqin; Jhoja, Jaspreet; Klein, Jackson; Wang, Xu; Liu, Amy; Flueckiger, Jonas; Pond, James; Chrostowski, Lukas

    2017-05-01

    This work develops an enhanced Monte Carlo (MC) simulation methodology to predict the impacts of layout-dependent correlated manufacturing variations on the performance of photonics integrated circuits (PICs). First, to enable such performance prediction, we demonstrate a simple method with sub-nanometer accuracy to characterize photonics manufacturing variations, where the width and height for a fabricated waveguide can be extracted from the spectral response of a racetrack resonator. By measuring the spectral responses for a large number of identical resonators spread over a wafer, statistical results for the variations of waveguide width and height can be obtained. Second, we develop models for the layout-dependent enhanced MC simulation. Our models use netlist extraction to transfer physical layouts into circuit simulators. Spatially correlated physical variations across the PICs are simulated on a discrete grid and are mapped to each circuit component, so that the performance for each component can be updated according to its obtained variations, and therefore, circuit simulations take the correlated variations between components into account. The simulation flow and theoretical models for our layout-dependent enhanced MC simulation are detailed in this paper. As examples, several ring-resonator filter circuits are studied using the developed enhanced MC simulation, and statistical results from the simulations can predict both common-mode and differential-mode variations of the circuit performance.

  4. Experimentally verified inductance extraction and parameter study for superconductive integrated circuit wires crossing ground plane holes

    International Nuclear Information System (INIS)

    Fourie, Coenrad J; Wetzstein, Olaf; Kunert, Juergen; Meyer, Hans-Georg; Toepfer, Hannes

    2013-01-01

    As the complexity of rapid single flux quantum (RSFQ) circuits increases, both current and power consumption of the circuits become important design criteria. Various new concepts such as inductive biasing for energy efficient RSFQ circuits and inductively coupled RSFQ cells for current recycling have been proposed to overcome increasingly severe design problems. Both of these techniques use ground plane holes to increase the inductance or coupling factor of superconducting integrated circuit wires. New design tools are consequently required to handle the new topographies. One important issue in such circuit design is the accurate calculation of networks of inductances even in the presence of finite holes in the ground plane. We show how a fast network extraction method using InductEx, which is a pre- and post-processor for the magnetoquasistatic field solver FastHenry, is used to calculate the inductances of a set of SQUIDs (superconducting quantum interference devices) with ground plane holes of different sizes. The results are compared to measurements of physical structures fabricated with the IPHT Jena 1 kA cm −2 RSFQ niobium process to verify accuracy. We then do a parameter study and derive empirical equations for fast and useful estimation of the inductance of wires surrounded by ground plane holes. We also investigate practical circuits and show excellent accuracy. (paper)

  5. 77 FR 42764 - Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions; Notice...

    Science.gov (United States)

    2012-07-20

    ..., Chipsets, & Products Containing Same Including Televisions; Notice of Request for Statements on the Public... against certain integrated circuits, chipsets, and products containing the same including televisions...'') in a prominent place on the cover page and/or the first page. (See Handbook for Electronic Filing...

  6. SPICE Modeling of Body Bias Effect in 4H-SiC Integrated Circuit Resistors

    Science.gov (United States)

    Neudeck, Philip G.

    2017-01-01

    The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

  7. The Hybrid Integrated Circuit of the ALICE Inner Tracking System upgrade

    CERN Document Server

    Fiorenza, G; Pastore, C; Valentino, V

    2016-01-01

    The upgrade of the Inner Tracking System scheduled during the second long shutdown is an important milestone of the ALICE upgrade and it will provide a high improvement of its performances. In this contribution the smallest operator unit of the detector, the Hybrid Integrated Circuits, is presented.

  8. Wideband Monolithic Microwave Integrated Circuit Frequency Converters with GaAs mHEMT Technology

    DEFF Research Database (Denmark)

    Krozer, Viktor; Johansen, Tom Keinicke; Djurhuus, Torsten

    2005-01-01

    We present monolithic microwave integrated circuit (MMIC) frequency converter, which can be used for up and down conversion, due to the large RF and IF port bandwidth. The MMIC converters are based on commercially available GaAs mHEMT technology and are comprised of a Gilbert mixer cell core...

  9. Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6

    NARCIS (Netherlands)

    Roozeboom, F.; Narayanan, V.; Kakushima, K.; Timans, P.J.; Gusev, E.P.; Karim, Z.; Gendt, S. De

    2016-01-01

    The topics of this annual symposium continue to describe the evolution of traditional scaling in CMOS integrated circuit manufacturing (More Moore for short), combined with the opportunities from growing diversification and embedded functionality (More than Moore). Once again, the main objective was

  10. 78 FR 35051 - Certain Encapsulated Integrated Circuit Devices and Products Containing Same; Commission...

    Science.gov (United States)

    2013-06-11

    ...., Washington, DC 20436, telephone (202) 205-3115. Copies of non- confidential documents filed in connection... encapsulated integrated circuit devices and products containing same in connection with claims 1-4, 7, 17, 18... `277 patent are invalid under 35 U.S.C. 102(b) as anticipated by certain prior art references, but...

  11. Diffusion barriers for Cu metallisation in Si integrated circuits : deposition and related thin film properties

    NARCIS (Netherlands)

    van Nieuwkasteele-Bystrova, Svetlana Nikolajevna

    2004-01-01

    In modern integrated circuits with Cu interconnects a diffusion barrier is used between the dielectric and Cu in order to prevent diffusion of Cu through the dielectrics. The choice of such a barrier requires a material exploration and a study of the material reactivity with both Cu and the

  12. CMOS-based carbon nanotube pass-transistor logic integrated circuits

    Science.gov (United States)

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-01-01

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

  13. Study and realization of ultra-rapid logic circuits in middle scale integration

    International Nuclear Information System (INIS)

    Verhaeghe, Michel

    1972-01-01

    We associate middle scale integration with sub-nanosecond logic in order to realize ultra-rapid logic circuits, characterized by a 40 gates complexity for a dissipation lower than 1 watt. For this purpose, we must find a high special and low power gates family. With use of current mode logic, and sharing of the logic circuit between an internal part and interfaces, mean dissipation can be lowered to 20 mW while mean propagation time is 1 ns by gate. So, circuits present a speed-power product of 20 mW x ns giving to them one of the best places among the other types of ultra-rapid logic. Another interesting aspect of the work is the use of diffused components master slice including specialized integrated cells, fitting well complex circuits. With this master slice and the different gates, settlement of mean complexity circuits family is foreseen. The elements of this family would be able to reply to the main needs of rapid electronics. (author) [fr

  14. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit

    Directory of Open Access Journals (Sweden)

    Zong Yao

    2016-06-01

    Full Text Available This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of −50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts, the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor’s output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

  15. High-voltage integrated transmitting circuit with differential driving for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz

    2016-01-01

    In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... pulses at differential voltage levels of 60, 80 and 100 V, a frequency up to 5 MHz and a measured driving strength of 2.03 V/ns with the CMUT electrical model connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption at the ultrasound scanner operation...

  16. Design and Verification of Application Specific Integrated Circuits in a Network of Online Labs

    Directory of Open Access Journals (Sweden)

    A.Y. Al-Zoubi

    2009-08-01

    Full Text Available A solution to implement a remote laboratory for testing and designing analog Application-Specific Integrated Circuits of the type (ispPAC10 is presented. The application allows electrical engineering students to access and perform measurements and conduct analog electronics experiments over the internet. PAC-Designer software, running on a Citrix server, is used in the circuit design in which the signals are generated and the responses are acquired by a data acquisition board controlled by LabVIEW. Three interconnected remote labs located in three different continents will be implementing the proposed system.

  17. Measurements of complex impedance in microwave high power systems with a new bluetooth integrated circuit.

    Science.gov (United States)

    Roussy, Georges; Dichtel, Bernard; Chaabane, Haykel

    2003-01-01

    By using a new integrated circuit, which is marketed for bluetooth applications, it is possible to simplify the method of measuring the complex impedance, complex reflection coefficient and complex transmission coefficient in an industrial microwave setup. The Analog Devices circuit AD 8302, which measures gain and phase up to 2.7 GHz, operates with variable level input signals and is less sensitive to both amplitude and frequency fluctuations of the industrial magnetrons than are mixers and AM crystal detectors. Therefore, accurate gain and phase measurements can be performed with low stability generators. A mechanical setup with an AD 8302 is described; the calibration procedure and its performance are presented.

  18. Microfluidic valve array control system integrating a fluid demultiplexer circuit

    International Nuclear Information System (INIS)

    Kawai, Kentaro; Shoji, Shuichi; Arima, Kenta; Morita, Mizuho

    2015-01-01

    This paper proposes an efficient control method for the large-scale integration of microvalves in microfluidic systems. The proposed method can control 2 n individual microvalves with 2n + 2 control lines (where n is an integer). The on-chip valves are closed by applying pressure to a control line, similar to conventional pneumatic microvalves. Another control line closes gate valves between the control line to the on-chip valves and the on-chip valves themselves, to preserve the state of the on-chip valves. The remaining control lines select an activated gate valve. While the addressed gate valve is selected by the other control lines, the corresponding on-chip valve is actuated by applying input pressure to the control line to the on-chip valves. Using this method would substantially reduce the number of world-to-chip connectors and off-chip valve controllers. Experiments conducted using a fabricated 2 8 microvalve array device, comprising 256 individual on-chip valves controlled with 18 (2   ×   8 + 2) control lines, yielded switching speeds for the selected on-chip valve under 90 ms. (paper)

  19. Towards Large-Scale Fast Reprogrammable SOA-Based Photonic Integrated Switch Circuits

    Directory of Open Access Journals (Sweden)

    Ripalta Stabile

    2017-09-01

    Full Text Available Due to the exponentially increasing connectivity and bandwidth demand from the Internet, the most advanced examples of medium-scale fast reconfigurable photonic integrated switch circuits are offered by research carried out for data- and computer-communication applications, where network flexibility at a high speed and high connectivity are provided to suit network demand. Recently we have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip for high connectivity. In this paper, the current status of fast reconfigurable medium-scale indium phosphide (InP integrated photonic switch matrices based on the use of semiconductor optical amplifier (SOA gates is reviewed, focusing on broadband and cross-connecting monolithic implementations, granting a connectivity of up to sixteen input ports, sixteen output ports, and sixty-four channels, respectively. The opportunities for increasing connectivity, enabling nanosecond order reconfigurability, and introducing distributed optical power monitoring at the physical layer are highlighted. Complementary architecture based on resonant switching elements on the same material platform are also discussed for power efficient switching. Performance projections related to the physical layer are presented and strategies for improvements are discussed in view of opening a route towards large-scale power efficient fast reprogrammable photonic integrated switching circuits.

  20. CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

    Science.gov (United States)

    Domingues, Suzana; Perenzoni, Daniele; Perenzoni, Matteo; Stoppa, David

    2017-06-01

    In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm2 and 36 μW).

  1. Test and verification of a reactor protection system application-specific integrated circuit

    International Nuclear Information System (INIS)

    Battle, R.E.; Turner, G.W.; Vandermolen, R.I.; Vitalbo, C.

    1997-01-01

    Application-specific integrated circuits (ASICs) were utilized in the design of nuclear plant safety systems because they have certain advantages over software-based systems and analog-based systems. An advantage they have over software-based systems is that an ASIC design can be simple enough to not include branch statements and also can be thoroughly tested. A circuit card on which an ASIC is mounted can be configured to replace various versions of older analog equipment with fewer design types required. The approach to design and testing of ASICs for safety system applications is discussed in this paper. Included are discussions of the ASIC architecture, how it is structured to assist testing, and of the functional and enhanced circuit testing

  2. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

    Science.gov (United States)

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-02-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

  3. Moving the boundary between wavelength resources in optical packet and circuit integrated ring network.

    Science.gov (United States)

    Furukawa, Hideaki; Miyazawa, Takaya; Wada, Naoya; Harai, Hiroaki

    2014-01-13

    Optical packet and circuit integrated (OPCI) networks provide both optical packet switching (OPS) and optical circuit switching (OCS) links on the same physical infrastructure using a wavelength multiplexing technique in order to deal with best-effort services and quality-guaranteed services. To immediately respond to changes in user demand for OPS and OCS links, OPCI networks should dynamically adjust the amount of wavelength resources for each link. We propose a resource-adjustable hybrid optical packet/circuit switch and transponder. We also verify that distributed control of resource adjustments can be applied to the OPCI ring network testbed we developed. In cooperation with the resource adjustment mechanism and the hybrid switch and transponder, we demonstrate that automatically allocating a shared resource and moving the wavelength resource boundary between OPS and OCS links can be successfully executed, depending on the number of optical paths in use.

  4. Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

    Science.gov (United States)

    Geier, Michael

    Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and

  5. Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

    Science.gov (United States)

    McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

    2017-03-28

    Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

  6. Design and analysis of CMOS single photon counting avalanche photodiodes integrated with active quenching circuits

    International Nuclear Information System (INIS)

    Kim, Kwang Hyun; Kim, Young Soo

    2008-01-01

    The CMOS SPADs (Single Photon Avalanche Diodes) integrated with active quenching circuits were fabricated on same chip using AMIS 0.7 μm high voltage CMOS process without any process modifications. The SPADs have N+/P-substrate structure and their diameter of photo sensing area are 25 μm, 50 μm, 100 μm, 400 μm, and 800 μm. The avalanche multiplication is occurred at 10.7 V, and the photocurrent gain at 11 V reverse bias voltage is about 1000. In zero bias condition, the maximum quantum efficiency appears at 650 nm wavelength, and it corresponds to around 30%. The active quenching circuit is composed to a comparator, three monostable, and two MOS switch. As a circuit simulation results, the comparator and the monostable generate ∼22 nsec and ∼1 nsec delayed output pulse, respectively. The dead time of the active quenching circuits integrated with SPADs is about 100 nsec as a measured result. (author)

  7. Improvement of bioreporter bacteria-based test systems for the analysis of arsenic in drinking water and the rhizosphere

    International Nuclear Information System (INIS)

    Kuppardt, Anke

    2010-01-01

    Contamination of drinking water with arsenic can be measured in laboratories with atom absorption spectrometry (AAS), mass spectrometry with inductive coupled plasma (ICP-MS) or atom fluorescence spectrometry (AFS) at the relevant concentrations below 50 μg/L. Field test kits which easily and reliably measure arsenic concentrations are not yet available. Test systems on the basis of bioreporter bacteria offer an alternative. Based on the natural resistance mechanism of bacteria against arsenic compounds toxic for humans, bioreporter bacteria can be constructed that display arsenic concentrations with light emission (luminescence or fluorescence) or colour reactions. This is achieved by coupling the gene for the ArsR-protein and arsenic regulated promoters with suitable reporter genes. The resulting bioreporter bacteria report bioavailable arsenic in a dose dependent manner at the toxicologically relevant level of 2 to 80 μg/L and are therewith suitable both for the guideline levels of the WHO of 10 μg/L and for the national standards in South East Asia of 50 μg/L. This alternative method has the advantage of being independent from sophisticated apparatus as by eye detection is feasible and offers the possibility of measuring directly the bioavailable fraction. Bioreporter bacteria are also suitable for in situ research. Yet, in order to apply such bioreporter bacteria as a low-cost analytical tool in a regular manner, open questions exist regarding the preservation of the specific activity, the vitality of bioreporter bacteria and the improvement of bioreporter test systems for layman. The aim of this thesis hence was to optimize and improve bioreporter based test systems to allow easy conservation, storage and transport, and also an application without the need of a sophisticated infrastructure. For that purpose it was intended (i) to develop and validate a method that allows arsenic detection without external calibration (chapter 2) and (ii) to improve the

  8. Improvement of bioreporter bacteria-based test systems for the analysis of arsenic in drinking water and the rhizosphere

    Energy Technology Data Exchange (ETDEWEB)

    Kuppardt, Anke

    2010-02-05

    Contamination of drinking water with arsenic can be measured in laboratories with atom absorption spectrometry (AAS), mass spectrometry with inductive coupled plasma (ICP-MS) or atom fluorescence spectrometry (AFS) at the relevant concentrations below 50 {mu}g/L. Field test kits which easily and reliably measure arsenic concentrations are not yet available. Test systems on the basis of bioreporter bacteria offer an alternative. Based on the natural resistance mechanism of bacteria against arsenic compounds toxic for humans, bioreporter bacteria can be constructed that display arsenic concentrations with light emission (luminescence or fluorescence) or colour reactions. This is achieved by coupling the gene for the ArsR-protein and arsenic regulated promoters with suitable reporter genes. The resulting bioreporter bacteria report bioavailable arsenic in a dose dependent manner at the toxicologically relevant level of 2 to 80 {mu}g/L and are therewith suitable both for the guideline levels of the WHO of 10 {mu}g/L and for the national standards in South East Asia of 50 {mu}g/L. This alternative method has the advantage of being independent from sophisticated apparatus as by eye detection is feasible and offers the possibility of measuring directly the bioavailable fraction. Bioreporter bacteria are also suitable for in situ research. Yet, in order to apply such bioreporter bacteria as a low-cost analytical tool in a regular manner, open questions exist regarding the preservation of the specific activity, the vitality of bioreporter bacteria and the improvement of bioreporter test systems for layman. The aim of this thesis hence was to optimize and improve bioreporter based test systems to allow easy conservation, storage and transport, and also an application without the need of a sophisticated infrastructure. For that purpose it was intended (i) to develop and validate a method that allows arsenic detection without external calibration (chapter 2) and (ii) to

  9. Polymer optical circuits technology for large-scale integration of passive functions

    Science.gov (United States)

    Maalouf, Azar; Bosc, Dominique; Henrio, Frédéric; Haesaert, Séverine; Grosso, Philippe; Hardy, Isabelle; Gadonna, Michel

    2006-04-01

    Polymers are attractive to realize integrated circuits specially because they are very simple to process and are promising for low cost devices. Moreover, beside low cost technology, the large possible range of refractive index, could lead to large scale of integration, lowering the fabrication costs. In some cases, it could be an alternative solution to semiconductor or inorganic dielectric technologies. With usual UV photolithography technology, this work shows that it is possible to perform small guides in order to provide relatively high circuit densification. The refractive index contrast, between optical core and cladding, can be as high as 0.07 instead of 0.02 for the higher contrast in silica Ge doped waveguides. Recently, this contrast has been increased to 0.11 at the wavelength of 1550nm. These materials make possible the patterning of guides having radius of curvature smaller than 200μm. Such curvatures open the way to functions based on microrings that potentially lead to compact wavelength multiplexers. With the view to control the fabrication of polymer waveguides, some features of the process are reported here. For example, shortcomings such as unsuitable film worm aspects are described and solutions are given with requirements assigned to rough materials. Mechanical and thermal properties of polymers have to be adjusted to withstand integrated circuit processing. This paper also presents results concerning the realization of integrated passive microring resonators with this technology.

  10. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  11. Localization and Imaging of Integrated Circuit Defect Using Simple Optical Feedback Detection

    Directory of Open Access Journals (Sweden)

    Vernon Julius Cemine

    2004-12-01

    Full Text Available High-contrast microscopy of semiconductor and metal edifices in integrated circuits is demonstrated by combining laser-scanning confocal reflectance microscopy, one-photon optical-beam-induced current (1P-OBIC imaging, and optical feedback detection via a commercially available semiconductor laser that also serves as the excitation source. The confocal microscope has a compact in-line arrangement with no external photodetector. Confocal and 1P-OBIC images are obtained simultaneously from the same focused beam that is scanned across the sample plane. Image pairs are processed to generate exclusive high-contrast distributions of the semiconductor, metal, and dielectric sites in a GaAs photodiode array sample. The method is then utilized to demonstrate defect localization and imaging in an integrated circuit.

  12. Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

    Science.gov (United States)

    Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

    2016-09-19

    Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

  13. High-dimensional quantum key distribution based on multicore fiber using silicon photonic integrated circuits

    DEFF Research Database (Denmark)

    Ding, Yunhong; Bacco, Davide; Dalgaard, Kjeld

    2017-01-01

    is intrinsically limited to 1 bit/photon. Here we propose and experimentally demonstrate, for the first time, a high-dimensional quantum key distribution protocol based on space division multiplexing in multicore fiber using silicon photonic integrated lightwave circuits. We successfully realized three mutually......-dimensional quantum states, and enables breaking the information efficiency limit of traditional quantum key distribution protocols. In addition, the silicon photonic circuits used in our work integrate variable optical attenuators, highly efficient multicore fiber couplers, and Mach-Zehnder interferometers, enabling...... manipulating high-dimensional quantum states in a compact and stable manner. Our demonstration paves the way to utilize state-of-the-art multicore fibers for noise tolerance high-dimensional quantum key distribution, and boost silicon photonics for high information efficiency quantum communications....

  14. Advances in gallium arsenide monolithic microwave integrated-circuit technology for space communications systems

    Science.gov (United States)

    Bhasin, K. B.; Connolly, D. J.

    1986-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. In this paper, current developments in GaAs MMIC technology are described, and the status and prospects of the technology are assessed.

  15. Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

    KAUST Repository

    Hanna, Amir

    2015-12-04

    High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

  16. A multi-ring optical packet and circuit integrated network with optical buffering.

    Science.gov (United States)

    Furukawa, Hideaki; Shinada, Satoshi; Miyazawa, Takaya; Harai, Hiroaki; Kawasaki, Wataru; Saito, Tatsuhiko; Matsunaga, Koji; Toyozumi, Tatuya; Wada, Naoya

    2012-12-17

    We newly developed a 3 × 3 integrated optical packet and circuit switch-node. Optical buffers and burst-mode erbium-doped fiber amplifiers with the gain flatness are installed in the 3 × 3 switch-node. The optical buffer can prevent packet collisions and decrease packet loss. We constructed a multi-ring optical packet and circuit integrated network testbed connecting two single-ring networks and a client network by the 3 × 3 switch-node. For the first time, we demonstrated 244 km fiber transmission and 5-node hopping of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10 Gigabit Ethernet frames on the testbed. Error-free (frame error rate optical packets of various packet lengths. In addition, successful avoidance of packet collisions by optical buffers was confirmed.

  17. Advanced field-solver techniques for RC extraction of integrated circuits

    CERN Document Server

    Yu, Wenjian

    2014-01-01

    Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering, as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of ...

  18. Integrated genomic and gene expression profiling identifies two major genomic circuits in urothelial carcinoma.

    Directory of Open Access Journals (Sweden)

    David Lindgren

    Full Text Available Similar to other malignancies, urothelial carcinoma (UC is characterized by specific recurrent chromosomal aberrations and gene mutations. However, the interconnection between specific genomic alterations, and how patterns of chromosomal alterations adhere to different molecular subgroups of UC, is less clear. We applied tiling resolution array CGH to 146 cases of UC and identified a number of regions harboring recurrent focal genomic amplifications and deletions. Several potential oncogenes were included in the amplified regions, including known oncogenes like E2F3, CCND1, and CCNE1, as well as new candidate genes, such as SETDB1 (1q21, and BCL2L1 (20q11. We next combined genome profiling with global gene expression, gene mutation, and protein expression data and identified two major genomic circuits operating in urothelial carcinoma. The first circuit was characterized by FGFR3 alterations, overexpression of CCND1, and 9q and CDKN2A deletions. The second circuit was defined by E3F3 amplifications and RB1 deletions, as well as gains of 5p, deletions at PTEN and 2q36, 16q, 20q, and elevated CDKN2A levels. TP53/MDM2 alterations were common for advanced tumors within the two circuits. Our data also suggest a possible RAS/RAF circuit. The tumors with worst prognosis showed a gene expression profile that indicated a keratinized phenotype. Taken together, our integrative approach revealed at least two separate networks of genomic alterations linked to the molecular diversity seen in UC, and that these circuits may reflect distinct pathways of tumor development.

  19. Gallium Nitride Monolithic Microwave Integrated Circuit Designs Using 0.25-micro m Qorvo Process

    Science.gov (United States)

    2017-07-27

    ARL-TN-0836 ● July 2017 US Army Research Laboratory Gallium Nitride Monolithic Microwave Integrated Circuit Designs Using 0.25...findings in this report are not to be construed as an official Department of the Army position unless so designated by other authorized documents...Citation of manufacturer’s or trade names does not constitute an official endorsement or approval of the use thereof. Destroy this report when it is no

  20. Self-organized mapping of R&D activities: bibliometric cartography of integrated circuit design testing

    OpenAIRE

    A F J van Raan; J G M van der Velde

    1992-01-01

    An exploratory bibliometric analysis of an R&D field (integrated circuit design testing) had the aim of visualizing the field's knowledge structure, and changes over time. It used bibliometric cartography based on co-word analysis. The basic approach and its relation with self-organizing systems are outlined; this includes the techniques for defining the field, drawing on publications (there being few patents for inclusion). Copyright , Beech Tree Publishing.

  1. SiGe Integrated Circuit Developments for SQUID/TES Readout

    Science.gov (United States)

    Prêle, D.; Voisin, F.; Beillimaz, C.; Chen, S.; Piat, M.; Goldwurm, A.; Laurent, P.

    2018-03-01

    SiGe integrated circuits dedicated to the readout of superconducting bolometer arrays for astrophysics have been developed since more than 10 years at APC. Whether for Cosmic Microwave Background (CMB) observations with the QUBIC ground-based experiment (Aumont et al. in astro-ph.IM, 2016. arXiv:1609.04372) or for the Hot and Energetic Universe science theme with the X-IFU instrument on-board of the ATHENA space mission (Barret et al. in SPIE 9905, space telescopes & instrumentation 2016: UV to γ Ray, 2016. https://doi.org/10.1117/12.2232432), several kinds of Transition Edge Sensor (TES) (Irwin and Hilton, in ENSS (ed) Cryogenic particle detection, Springer, Berlin, 2005) arrays have been investigated. To readout such superconducting detector arrays, we use time or frequency domain multiplexers (TDM, FDM) (Prêle in JINST 10:C08015, 2016. https://doi.org/10.1088/1748-0221/10/08/C08015) with Superconducting QUantum Interference Devices (SQUID). In addition to the SQUID devices, low-noise biasing and amplification are needed. These last functions can be obtained by using BiCMOS SiGe technology in an Application Specific Integrated Circuit (ASIC). ASIC technology allows integration of highly optimised circuits specifically designed for a unique application. Moreover, we could reach very low-noise and wide band amplification using SiGe bipolar transistor either at room or cryogenic temperatures (Cressler in J Phys IV 04(C6):C6-101, 1994. https://doi.org/10.1051/jp4:1994616). This paper discusses the use of SiGe integrated circuits for SQUID/TES readout and gives an update of the last developments dedicated to the QUBIC telescope and to the X-IFU instrument. Both ASIC called SQmux128 and AwaXe are described showing the interest of such SiGe technology for SQUID multiplexer controls.

  2. Application-specific integrated circuit design for a typical pressurized water reactor pressure channel trip

    International Nuclear Information System (INIS)

    Battle, R.E.; Manges, W.W.; Emery, M.S.; Vendermolen, R.I.; Bhatt, S.

    1994-01-01

    This article discusses the use of application-specific integrated circuits (ASICs) in nuclear plant safety systems. ASICs have certain advantages over software-based systems because they can be simple enough to be thoroughly tested, and they can be tailored to replace existing equipment. An architecture to replace a pressurized water reactor pressure channel trip is presented. Methods of implementing digital algorithms are also discussed

  3. Basic Consecutive System Consisted of Design, Process and Estimation of a Fundamental Integrated Circuit Education System

    Science.gov (United States)

    Kataoka, Hiroyuki; Yamada, Akihiro; Kamizono, Hiroki; Ando, Hideyuki; Tanaka, Takeshi

    The progress of integrated-circuits technology in recent years has enabled a large performance-increase of system LSI. As it is needed long time to study the knowledge of the system LSI such as design, semiconductor process, and estimation of device, it is hard to study system LSI technology for company man and students. The basic consecutive system consisted of design, process and estimation of a fundamental IC system was studied.

  4. Integrated cascade of photovoltaic cells as a power supply for integrated circuits

    NARCIS (Netherlands)

    Mouthaan, A.J.

    1984-01-01

    ICs can be powered directly when a supply voltage source capable of generating a multiple of the open circuit voltage of one pn-junction is available on a chip. Two schemes have been investigated for cascading photovoltaic cells on the chip. The structures can be made compatible with standard

  5. System Modeling of a MEMS Vibratory Gyroscope and Integration to Circuit Simulation.

    Science.gov (United States)

    Kwon, Hyukjin J; Seok, Seyeong; Lim, Geunbae

    2017-11-18

    Recently, consumer applications have dramatically created the demand for low-cost and compact gyroscopes. Therefore, on the basis of microelectromechanical systems (MEMS) technology, many gyroscopes have been developed and successfully commercialized. A MEMS gyroscope consists of a MEMS device and an electrical circuit for self-oscillation and angular-rate detection. Since the MEMS device and circuit are interactively related, the entire system should be analyzed together to design or test the gyroscope. In this study, a MEMS vibratory gyroscope is analyzed based on the system dynamic modeling; thus, it can be mathematically expressed and integrated into a circuit simulator. A behavioral simulation of the entire system was conducted to prove the self-oscillation and angular-rate detection and to determine the circuit parameters to be optimized. From the simulation, the operating characteristic according to the vacuum pressure and scale factor was obtained, which indicated similar trends compared with those of the experimental results. The simulation method presented in this paper can be generalized to a wide range of MEMS devices.

  6. A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

    Directory of Open Access Journals (Sweden)

    Daniel Pacheco Bautista

    2007-09-01

    Full Text Available The clock recovery circuit (CRC plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC wor-king at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL, current mode logic (MCML and a novel two stage ring-based voltage controlled oscillator (VCO. The design used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

  7. The functional significance of newly born neurons integrated into olfactory bulb circuits

    Directory of Open Access Journals (Sweden)

    Masayuki eSakamoto

    2014-05-01

    Full Text Available The olfactory bulb (OB is the first central processing center for olfactory information connecting with higher areas in the brain, and this neuronal circuitry mediates a variety of odor-evoked behavioral responses. In the adult mammalian brain, continuous neurogenesis occurs in two restricted regions, the subventricular zone (SVZ of the lateral ventricle and the hippocampal dentate gyrus. New neurons born in the SVZ migrate through the rostral migratory stream and are integrated into the neuronal circuits of the OB throughout life. The significance of this continuous supply of new neurons in the OB has been implicated in plasticity and memory regulation. Two decades of huge investigation in adult neurogenesis revealed the biological importance of integration of new neurons into the olfactory circuits. In this review, we highlight the recent findings about the physiological functions of newly generated neurons in rodent OB circuits and then discuss the contribution of neurogenesis in the brain function. Finally, we introduce cutting edge technologies to monitor and manipulate the activity of new neurons.

  8. A contact lens with integrated telecommunication circuit and sensors for wireless and continuous tear glucose monitoring

    International Nuclear Information System (INIS)

    Yao, H; Liao, Y; Lingley, A R; Afanasiev, A; Lähdesmäki, I; Otis, B P; Parviz, B A

    2012-01-01

    We present an integrated functional contact lens, composed of a differential glucose sensor module, metal interconnects, sensor read-out circuit, antenna and telecommunication circuit, to monitor tear glucose levels wirelessly, continuously and non-invasively. The electrochemical differential sensor module is based on immobilization of activated and de-activated glucose oxidase. We characterized the sensor on a model polymer eye and determined that it showed good repeatability, molecular interference rejection and linearity in the range of 0–2 mM glucose, covering normal tear glucose concentrations (0.1–0.6 mM). We also report the temperature, ageing and protein-fouling sensitivity of the sensor. We report the design and implementation of a low-power (3 µW) sensor read-out and telecommunication circuit to deliver wireless power and transmit data for the sensor module. Using this small chip (0.36 mm 2 ), we produced an integrated contact lens with sensors and demonstrated wireless operation of the system and glucose read-out over the distance of several centimeters. (paper)

  9. IRIS (Integrity and Reliability in Integrated Circuits) Test Article Generation (ITAG)

    Science.gov (United States)

    2015-03-31

    the device is working as expected. Our in-circuit testing approach assumes that the FPGA Device Under Test (DUT) is mounted on a PCB, and that...is mounted on a PCB, and that special test access to external FPGA I/O pins is not available. This precludes the use of clock, reset, control, and...andler. The primary exception handler tch registers. Processor context is saved, on handlers . Information specifi to the ed in a fi ed-location memory

  10. Gallium arsenide digital integrated circuits for controlling SLAC CW-RF systems

    International Nuclear Information System (INIS)

    Ronan, M.T.; Lee, K.L.; Corredoura, P.; Judkins, J.G.

    1989-01-01

    In order to fill the PEP and SPEAR storage rings with beams from the SLC linac and damping rings, precise control of the linac subharmonic buncher and the damping ring RF is required. Recently several companies have developed resettable GaAs master/slave D-type flip-flops which are capable of operating at frequencies of 3 GHz and higher. Using these digital devices as frequency dividers, one can phase shift the SLAC CW-RF systems to optimize the timing for filling the storage rings. The authors have evaluated the performance of integrated circuits from two vendors for our particular application. Using microstrip circuit techniques, they have built and operated in the accelerator several chassis to synchronize a reset signal from the storage rings to the SLAC 2.856 GHz RF and to phase shift divide-by-four and divide-by-sixteen frequency dividers to the nearest 350 psec bucket required for filling

  11. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  12. Active component modeling for analog integrated circuit design. Model parametrization and implementation in the SPICE-PAC circuit simulator

    International Nuclear Information System (INIS)

    Marchal, Xavier

    1992-01-01

    In order to use CAD efficiently in the analysis and design of electronic Integrated circuits, adequate modeling of active non-linear devices such as MOSFET transistors must be available to the designer. Many mathematical forms can be given to those models, such as explicit relations, or implicit equations to be solved. A major requirement in developing MOS transistor models for IC simulation is the availability of electrical characteristic curves over a wide range of channel width and length, including the sub-micrometer range. To account in a convenient way for bulk charge influence on I DS = f(V DS , V GS , v BS ) device characteristics, all 3 standard SPICE MOS models use an empirical fitting parameter called the 'charge sharing factor'. Unfortunately, this formulation produces models which only describe correctly either some of the short channel phenomena, or some particular operating conditions (low injection, avalanche effect, etc.). We present here a cellular model (CDM = Charge Distributed Model) implemented in the open modular SPICE-PAC Simulator; this model is derived from the 4-terminal WANG charge controlled MOSFET model, using the charge sheet approximation. The CDM model describes device characteristics in ail operating regions without introducing drain current discontinuities and without requiring a 'charge sharing factor'. A usual problem to be faced by designers when they simulate MOS ICs is to find a reliable source of model parameters. Though most models have a physical basis, some of their parameters cannot be easily estimated from physical considerations. It can also happen that physically determined parameters values do not produce a good fit to measured device characteristics. Thus it is generally necessary to extract model parameters from measured transistor data, to ensure that model equations approximate measured curves accurately enough. Model parameters extraction can be done in 2 different ways, exposed in this

  13. Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

    Science.gov (United States)

    Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

    2013-09-01

    A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

  14. Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays

    OpenAIRE

    Çiçek, İhsan; Cicek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

    2005-01-01

    Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMU...

  15. Design and characterization of radiation resistant integrated circuits for the LHC particle detectors using deep sub-micron CMOS technologies

    International Nuclear Information System (INIS)

    Anelli, Giovanni Maria

    2000-01-01

    The electronic circuits associated with the particle detectors of the CERN Large Hadron Collider (LHC) have to work in a highly radioactive environment. This work proposes a methodology allowing the design of radiation resistant integrated circuits using the commercial sub-micron CMOS technology. This method uses the intrinsic radiation resistance of ultra-thin grid oxides, the technology of enclosed layout transistors (ELT), and the protection rings to avoid the radio-induced creation of leakage currents. In order to check the radiation tolerance level, several test structures have been designed and tested with different radiation sources. These tests have permitted to study the physical phenomena responsible for the damages induced by the radiations and the possible remedies. Then, the particular characteristics of ELT transistors and their influence on the design of complex integrated circuits has been explored. The modeling of the W/L ratio, the asymmetries (for instance in the output conductance) and the performance of ELT couplings have never been studied yet. The noise performance of the 0.25 μ CMOS technology, used in the design of several integrated circuits of the LHC detectors, has been characterized before and after irradiation. Finally, two integrated circuits designed using the proposed method are presented. The first one is an analogic memory and the other is a circuit used for the reading of the signals of one of the LHC detectors. Both circuits were irradiated and have endured very high doses practically without any sign of performance degradation. (J.S.)

  16. QIE10: a new front-end custom integrated circuit for high-rate experiments

    International Nuclear Information System (INIS)

    Baumbaugh, A; Monte, L Dal; Freeman, J; Hare, D; Los, S; Shaw, T; Vidal, R; Whitmore, J; Zimmerman, T; Drake, G; Proudfoot, J; Rojas, H Hernandez; Hughes, E; Mendez, D Mendez; Tully, C

    2014-01-01

    We present results on a new version of the QIE (Charge Integrator and Encoder), a custom Application Specific Integrated Circuit (ASIC) designed at Fermilab. Developed specifically for the measurement of charge from photo-detectors in high-rate environments, this most recent addition to the QIE family features 3 fC sensitivity, 17-bits of dynamic range with logarithmic response, a Time-to-Digital Converter (TDC) with sub-nanosecond resolution, and internal charge injection. The device is capable of dead-timeless operation at 40 MHz, making it ideal for calorimetry at the Large hadron Collider (LHC). We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and plans for deployment in the Atlas and CMS detectors as part of the Phase 1 and Phase 2 upgrades

  17. Multi-channel integrated circuits for the detection and measurement of ionizing radiation

    International Nuclear Information System (INIS)

    Engel, G.L.; Duggireddi, N.; Vangapally, V.; Elson, J.M.; Sobotka, L.G.; Charity, R.J.

    2011-01-01

    The Integrated Circuits (IC) Design Research Laboratory at Southern Illinois University Edwardsville (SIUE) has collaborated with the Nuclear Reactions Group at Washington University (WU) to develop a family of multi-channel integrated circuits. To date, the collaboration has successfully produced two micro-chips. The first was an analog shaped and peak sensing chip with on-board constant-fraction discriminators and sparsified readout. This chip is known as Heavy-Ion Nuclear Physics-16 Channel (HINP16C). The second chip, christened PSD8C, was designed to logically complement (in terms of detector types) the HINP16C chip. Pulse Shape Discrimination-8 Channel (PSD8C), featuring three settable charge integration windows per channel, performs pulse shape discrimination (PSD). This paper summarizes the design, capabilities, and features of the HINP16C and PSD8C ICs. It proceeds to discuss the modifications, made to the ICs and their associated systems, which have attempted to improve ease of use, increase performance, and extend capabilities. The paper concludes with a brief discussion of what may be the next chip (employing a multi-sampling scheme) to be added to our CMOS ASIC 'tool box' for radiation detection instrumentation.

  18. Wiring Together Synthetic Bacterial Consortia to Create a Biological Integrated Circuit.

    Science.gov (United States)

    Perry, Nicolas; Nelson, Edward M; Timp, Gregory

    2016-12-16

    The promise of adapting biology to information processing will not be realized until engineered gene circuits, operating in different cell populations, can be wired together to express a predictable function. Here, elementary biological integrated circuits (BICs), consisting of two sets of transmitter and receiver gene circuit modules with embedded memory placed in separate cell populations, were meticulously assembled using live cell lithography and wired together by the mass transport of quorum-sensing (QS) signal molecules to form two isolated communication links (comlinks). The comlink dynamics were tested by broadcasting "clock" pulses of inducers into the networks and measuring the responses of functionally linked fluorescent reporters, and then modeled through simulations that realistically captured the protein production and molecular transport. These results show that the comlinks were isolated and each mimicked aspects of the synchronous, sequential networks used in digital computing. The observations about the flow conditions, derived from numerical simulations, and the biofilm architectures that foster or silence cell-to-cell communications have implications for everything from decontamination of drinking water to bacterial virulence.

  19. A Bistable Circuit Involving SCARECROW-RETINOBLASTOMA Integrates Cues to Inform Asymmetric Stem Cell Division

    Science.gov (United States)

    Cruz-Ramírez, Alfredo; Díaz-Triviño, Sara; Blilou, Ikram; Grieneisen, Verônica A.; Sozzani, Rosangela; Zamioudis, Christos; Miskolczi, Pál; Nieuwland, Jeroen; Benjamins, René; Dhonukshe, Pankaj; Caballero-Pérez, Juan; Horvath, Beatrix; Long, Yuchen; Mähönen, Ari Pekka; Zhang, Hongtao; Xu, Jian; Murray, James A.H.; Benfey, Philip N.; Bako, Laszlo; Marée, Athanasius F.M.; Scheres, Ben

    2012-01-01

    SUMMARY In plants, where cells cannot migrate, asymmetric cell divisions (ACDs) must be confined to the appropriate spatial context. We investigate tissue-generating asymmetric divisions in a stem cell daughter within the Arabidopsis root. Spatial restriction of these divisions requires physical binding of the stem cell regulator SCARECROW (SCR) by the RETINOBLASTOMA-RELATED (RBR) protein. In the stem cell niche, SCR activity is counteracted by phosphorylation of RBR through a cyclinD6;1-CDK complex. This cyclin is itself under transcriptional control of SCR and its partner SHORT ROOT (SHR), creating a robust bistable circuit with either high or low SHR-SCR complex activity. Auxin biases this circuit by promoting CYCD6;1 transcription. Mathematical modeling shows that ACDs are only switched on after integration of radial and longitudinal information, determined by SHR and auxin distribution, respectively. Coupling of cell-cycle progression to protein degradation resets the circuit, resulting in a “flip flop” that constrains asymmetric cell division to the stem cell region. PMID:22921914

  20. Integrated plasticity at inhibitory and excitatory synapses in the cerebellar circuit

    Directory of Open Access Journals (Sweden)

    Lisa eMapelli

    2015-05-01

    Full Text Available The way long-term potentiation (LTP and depression (LTD are integrated within the different synapses of brain neuronal circuits is poorly understood. In order to progress beyond the identification of specific molecular mechanisms, a system in which multiple forms of plasticity can be correlated with large-scale neural processing is required. In this paper we take as an example the cerebellar network , in which extensive investigations have revealed LTP and LTD at several excitatory and inhibitory synapses. Cerebellar LTP and LTD occur in all three main cerebellar subcircuits (granular layer, molecular layer, deep cerebellar nuclei and correspondingly regulate the function of their three main neurons: granule cells (GrCs, Purkinje cells (PCs and deep cerebellar nuclear (DCN cells. All these neurons, in addition to be excited, are reached by feed-forward and feed-back inhibitory connections, in which LTP and LTD may either operate synergistically or homeostatically in order to control information flow through the circuit. Although the investigation of individual synaptic plasticities in vitro is essential to prove their existence and mechanisms, it is insufficient to generate a coherent view of their impact on network functioning in vivo. Recent computational models and cell-specific genetic mutations in mice are shedding light on how plasticity at multiple excitatory and inhibitory synapses might regulate neuronal activities in the cerebellar circuit and contribute to learning and memory and behavioral control.

  1. Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

    Science.gov (United States)

    Kim, Hyungseup; Park, Yunjong; Ko, Youngwoon; Mun, Yeongjin; Lee, Sangmin; Ko, Hyoungho

    2017-10-13

    Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

  2. SEM analysis of ionizing radiation effects in linear integrated circuits. [Scanning Electron Microscope

    Science.gov (United States)

    Stanley, A. G.; Gauthier, M. K.

    1977-01-01

    A successful diagnostic technique was developed using a scanning electron microscope (SEM) as a precision tool to determine ionization effects in integrated circuits. Previous SEM methods radiated the entire semiconductor chip or major areas. The large area exposure methods do not reveal the exact components which are sensitive to radiation. To locate these sensitive components a new method was developed, which consisted in successively irradiating selected components on the device chip with equal doses of electrons /10 to the 6th rad (Si)/, while the whole device was subjected to representative bias conditions. A suitable device parameter was measured in situ after each successive irradiation with the beam off.

  3. Non-invasive current and voltage imaging techniques for integrated circuits using scanning probe microscopy

    Science.gov (United States)

    Campbell, A. N.; Cole, E. I., Jr.; Tangyunyong, Paiboon

    1995-06-01

    This report describes the first practical, non-invasive technique for detecting and imaging currents internal to operating integrated circuits (IC's). This technique is based on magnetic force microscopy and was developed under Sandia National Laboratories' LDRD (Laboratory Directed Research and Development) program during FY 93 and FY 94. LDRD funds were also used to explore a related technique, charge force microscopy, for voltage probing of IC's. This report describes the technical work performed under this LDRD as well as the outcomes of the project in terms of publications and awards, intellectual property and licensing, synergistic work, potential future work, hiring of additional permanent staff, and benefits to DOE's defense programs (DP).

  4. Water cooling in nuclear reactors by using panels of integrated circuits

    International Nuclear Information System (INIS)

    Dominique, P.; Letissier, R.

    1977-01-01

    In view of the drawbacks of wet cooling towers, EDF is searching for another approach to the problem. A self-cleaning device is now envisaged, that consists in some exchanger plates, 30 to 40m height (max. 60m) capable of being hiden in the lanscape behind high trees. The plates would be rather smooth and the air circulated by natural convection. The prototype is composed of 960 aluminium panels of integrated circuits mounted on three modules made of tubular elements working as supporting and collecting means together [fr

  5. MeV He microbeam analysis of a semiconductor integrated circuit

    International Nuclear Information System (INIS)

    Zhu Peiran; Liu Jiarui; Zhang Jinping; Yin Shiduan

    1989-01-01

    An MeV He + microbeam has been used to analyse a microscale semiconductor structure. The 2 MeV He + ion beam is limited to 25 μm diameter by a set of diaphragms and is further focused by a quadrupole quadruplet to 3μm diameter. The incident beam current on the sample is about 0.3 nA. The Rutherford backscattering (RBS) technique is applied to the measurement of the composition and depth profile in the near-surface region of a semiconductor integrated circuit. (author)

  6. All-fiber hybrid photon-plasmon circuits: integrating nanowire plasmonics with fiber optics.

    Science.gov (United States)

    Li, Xiyuan; Li, Wei; Guo, Xin; Lou, Jingyi; Tong, Limin

    2013-07-01

    We demonstrate all-fiber hybrid photon-plasmon circuits by integrating Ag nanowires with optical fibers. Relying on near-field coupling, we realize a photon-to-plasmon conversion efficiency up to 92% in a fiber-based nanowire plasmonic probe. Around optical communication band, we assemble an all-fiber resonator and a Mach-Zehnder interferometer (MZI) with Q-factor of 6 × 10(6) and extinction ratio up to 30 dB, respectively. Using the MZI, we demonstrate fiber-compatible plasmonic sensing with high sensitivity and low optical power.

  7. Report on the Minisession ''New developments in Flash ADC integrated circuits''

    International Nuclear Information System (INIS)

    Dhawan, S.K.

    1984-01-01

    New developments are taking place in the Flash Analog to Digital Converter marketplace. The big news is the digitization of VIDEO. It is expected to be a very large market and the merchant semiconductor and consumer electronics companies will be competing in selling these devices. The companies expect the initial selling price to be in the range of $ 7 - $15 for quantities of 10,000 units or more. This session was organized to expose the community to the new developments in FADC integrated circuits and the needs of physics instrumentation

  8. Performance evaluation of a burst-mode EDFA in an optical packet and circuit integrated network.

    Science.gov (United States)

    Shiraiwa, Masaki; Awaji, Yoshinari; Furukawa, Hideaki; Shinada, Satoshi; Puttnam, Benjamin J; Wada, Naoya

    2013-12-30

    We experimentally investigate the performance of burst-mode EDFA in an optical packet and circuit integrated system. In such networks, packets and light paths can be dynamically assigned to the same fibers, resulting in gain transients in EDFAs throughout the network that can limit network performance. Here, we compare the performance of a 'burst-mode' EDFA (BM-EDFA), employing transient suppression techniques and optical feedback, with conventional EDFAs, and those using automatic gain control and previous BM-EDFA implementations. We first measure gain transients and other impairments in a simplified set-up before making frame error-rate measurements in a network demonstration.

  9. Toolbox for the design of LiNbO3-based passive and active integrated quantum circuits

    Science.gov (United States)

    Sharapova, P. R.; Luo, K. H.; Herrmann, H.; Reichelt, M.; Meier, T.; Silberhorn, C.

    2017-12-01

    We present and discuss perspectives of current developments on advanced quantum optical circuits monolithically integrated in the lithium niobate platform. A set of basic components comprising photon pair sources based on parametric down conversion (PDC), passive routing elements and active electro-optically controllable switches and polarisation converters are building blocks of a toolbox which is the basis for a broad range of diverse quantum circuits. We review the state-of-the-art of these components and provide models that properly describe their performance in quantum circuits. As an example for applications of these models we discuss design issues for a circuit providing on-chip two-photon interference. The circuit comprises a PDC section for photon pair generation followed by an actively controllable modified mach–Zehnder structure for observing Hong–Ou–Mandel interference. The performance of such a chip is simulated theoretically by taking even imperfections of the properties of the individual components into account.

  10. Integration issues of a photonic layer on top of a CMOS circuit

    Science.gov (United States)

    Fedeli, J. M.; Orobtchouk, R.; Seassal, C.; Vivien, L.

    2006-02-01

    Photonics on CMOS is the integration of CMOS technology and optics components to enable either improved functionality of the electronic circuit (e.g. optical clock distribution) or as a means to miniaturize optical functions (e.g. miniaturised transceiver). The Near Infra Red (NIR) wavelength range (1.3 or 1.55μm) was chosen for this to minimise the impact the light on the behaviour of the microelectronic components. The integration of a photonic layer on a CMOS circuit can be seen in different ways: A combined fabrication at the front end level, the wafer bonding of an SOI photonic circuit at the back-end level, or the insertion of an embedded photonic layer between metallization schemes. For combined fabrication, a silicon on insulator rib technology has been developed with low (0.4dB/cm) propagation loss, ultra-high speed Ge-on-Si photodetector and SiGe/Si modulators.. In the metal-semiconductor-metal (MSM) configuration, bandwith of 35 GHz at 1.3 μm and 1.55μm has been measured. In the second approach, a wafer bonding of silicon rib and stripe technologies was achieved above the metallization layers of a CMOS wafer. For the third method, direct fabrication of a photonic layer at the back-end level was achieved using low temperature processes. Waveguide technologies such as SiNx (loss 2dB/cm) or amorphous silicon (loss 5dB/cm) were developed and were followed by the molecular bonding of InP die, these were needed to create the optoelectronic components (sources and detectors). Using an InP microdisk, 50% coupling was achieved to a stripe silicon waveguide.

  11. Laser Direct Writing and Selective Metallization of Metallic Circuits for Integrated Wireless Devices.

    Science.gov (United States)

    Cai, Jinguang; Lv, Chao; Watanabe, Akira

    2018-01-10

    Portable and wearable devices have attracted wide research attention due to their intimate relations with human daily life. As basic structures in the devices, the preparation of high-conductive metallic circuits or micro-circuits on flexible substrates should be facile, cost-effective, and easily integrated with other electronic units. In this work, high-conductive carbon/Ni composite structures were prepared by using a facile laser direct writing method, followed by an electroless Ni plating process, which exhibit a 3-order lower sheet resistance of less than 0.1 ohm/sq compared to original structures before plating, showing the potential for practical use. The carbon/Ni composite structures exhibited a certain flexibility and excellent anti-scratch property due to the tight deposition of Ni layers on carbon surfaces. On the basis of this approach, a wireless charging and storage device on a polyimide film was demonstrated by integrating an outer rectangle carbon/Ni composite coil for harvesting electromagnetic waves and an inner carbon micro-supercapacitor for energy storage, which can be fast charged wirelessly by a commercial wireless charger. Furthermore, a near-field communication (NFC) tag was prepared by combining a carbon/Ni composite coil for harvesting signals and a commercial IC chip for data storage, which can be used as an NFC tag for practical application.

  12. Three-dimensional multi-terminal superconductive integrated circuit inductance extraction

    International Nuclear Information System (INIS)

    Fourie, Coenrad J; Wetzstein, Olaf; Kunert, Jürgen; Ortlepp, Thomas

    2011-01-01

    Accurate inductance calculations are critical for the design of both digital and analogue superconductive integrated circuits, and three-dimensional calculations are gaining importance with the advent of inductive biasing, inductive coupling and sky plane shielding for RSFQ cells. InductEx, an extraction programme based on the three-dimensional calculation software FastHenry, was proposed earlier. InductEx uses segmentation techniques designed to accurately model the geometries of superconductive integrated circuit structures. Inductance extraction for complex multi-terminal three-dimensional structures from current distributions calculated by FastHenry is discussed. Results for both a reflection plane modelling an infinite ground plane and a finite segmented ground plane that allows inductive elements to extend over holes in the ground plane are shown. Several SQUIDs were designed for and fabricated with IPHT's 1 kA cm −2 RSFQ1D niobium process. These SQUIDs implement a number of loop structures that span different layers, include vias, inductively coupled control lines and ground plane holes. We measured the loop inductance of these SQUIDs and show how the results are used to calibrate the layer parameters in InductEx and verify the extraction accuracy. We also show that, with proper modelling, FastHenry can be fast enough to be used for the extraction of typical RSFQ cell inductances.

  13. A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

    Directory of Open Access Journals (Sweden)

    Kyeonghwan Park

    2017-04-01

    Full Text Available This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

  14. Operational Excellence through Schedule Optimization and Production Simulation of Application Specific Integrated Circuits.

    Energy Technology Data Exchange (ETDEWEB)

    Flory, John Andrew [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Padilla, Denise D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Gauthier, John H. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Zwerneman, April Marie [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Miller, Steven P [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2016-05-01

    Upcoming weapon programs require an aggressive increase in Application Specific Integrated Circuit (ASIC) production at Sandia National Laboratories (SNL). SNL has developed unique modeling and optimization tools that have been instrumental in improving ASIC production productivity and efficiency, identifying optimal operational and tactical execution plans under resource constraints, and providing confidence in successful mission execution. With ten products and unprecedented levels of demand, a single set of shared resources, highly variable processes, and the need for external supplier task synchronization, scheduling is an integral part of successful manufacturing. The scheduler uses an iterative multi-objective genetic algorithm and a multi-dimensional performance evaluator. Schedule feasibility is assessed using a discrete event simulation (DES) that incorporates operational uncertainty, variability, and resource availability. The tools provide rapid scenario assessments and responses to variances in the operational environment, and have been used to inform major equipment investments and workforce planning decisions in multiple SNL facilities.

  15. Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    Cheng-Yang Liu

    2009-12-01

    Full Text Available The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa.

  16. Capacitive micro pressure sensor integrated with a ring oscillator circuit on chip.

    Science.gov (United States)

    Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

    2009-01-01

    The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0-300 kPa.

  17. Multisensory integration for odor tracking by flying Drosophila: Behavior, circuits and speculation.

    Science.gov (United States)

    Duistermars, Brian J; Frye, Mark A

    2010-01-01

    Many see fruit flies as an annoyance, invading our homes with a nagging persistence and efficiency. Yet from a scientific perspective, these tiny animals are a wonder of multisensory integration, capable of tracking fragmented odor plumes amidst turbulent winds and constantly varying visual conditions. The peripheral olfactory, mechanosensory, and visual systems of the fruit fly, Drosophila melanogaster, have been studied in great detail;1-4 however, the mechanisms by which fly brains integrate information from multiple sensory modalities to facilitate robust odor tracking remain elusive. Our studies on olfactory orientation by flying flies reveal that these animals do not simply follow their "nose"; rather, fruit flies require mechanosensory and visual input to track odors in flight.5,6 Collectively, these results shed light on the neural circuits involved in odor localization by fruit flies in the wild and illuminate the elegant complexity underlying a behavior to which the annoyed and amazed are familiar.

  18. On the Basis of Synaptic Integration Constancy during Growth of a Neuronal Circuit

    Directory of Open Access Journals (Sweden)

    Adriana De-La-Rosa Tovar

    2016-08-01

    Full Text Available We studied how a neuronal circuit composed of two neuron types connected by chemical and electrical synapses maintains constant its integrative capacities as neurons grow. For this we combined electrophysiological experiments with mathematical modeling in pairs of electrically-coupled Retzius neurons from postnatal to adult leeches. The electrically-coupled dendrites of both Retzius neurons receive a common chemical input, which produces excitatory postsynaptic potentials (EPSPs with varying amplitudes. Each EPSP spreads to the soma, but also crosses the electrical synapse to arrive at the soma of the coupled neuron. The leak of synaptic current across the electrical synapse reduces the amplitude of the EPSPs in proportion to the coupling ratio. In addition, summation of EPSPs generated in both neurons generates the baseline action potentials of these serotonergic neurons. To study how integration is adjusted as neurons grow, we first studied the characteristics of the chemical and electrical connections onto the coupled dendrites of neuron pairs with soma diameters ranging from 21 to 75 μm. Then by feeding a mathematical model with the neuronal voltage responses to pseudorandom noise currents we obtained the values of the coupling ratio, the membrane resistance of the soma (rm and dendrites (rdend, the space constant (λ and the characteristic dendritic length (L = l/λ. We found that the EPSPs recorded from the somata were similar regardless on the neuron size. However, the amplitude of the EPSPs and the firing frequency of the neurons were inversely proportional to the coupling ratio of the neuron pair, which also was independent from the neuronal size. This data indicated that the integrative constancy relied on the passive membrane properties. We show that the growth of Retzius neurons was compensated by increasing the membrane resistance of the dendrites and therefore the λ value. By solely increasing the dendrite resistance this circuit

  19. Integrating integrated circuit chips on paper substrates using inkjet printed electronics

    CSIR Research Space (South Africa)

    Bezuidenhout, Petrone H

    2016-11-01

    Full Text Available This paper investigates the integration of silicon and paper substrates using rapid prototyping inkjet printed electronics. Various Dimatix DMP-2831 material printer settings and adhesives are investigated. The aim is to robustly and effectively...

  20. Design and performance of a multi-channel, multi-sampling, PSD-enabling integrated circuit

    International Nuclear Information System (INIS)

    Engel, G.L.; Hall, M.J.; Proctor, J.M.; Elson, J.M.; Sobotka, L.G.; Shane, R.; Charity, R.J.

    2009-01-01

    This paper presents the design and test results of an eight-channel prototype integrated circuit chip intended to greatly simplify the pulse-processing electronics needed for large arrays of scintillation detectors. Because the chip design employs (user-controlled) multi-region charge integration, particle identification is incorporated into the basic design. Each channel on the chip also contains a time-to-voltage converter which provides relative time information. The pulse-height integrals and the relative time are all stored on capacitors and are either reset, after a user controlled time, or sequentially read out if acquisition of the event is desired. Each of the three pulse-height sub-channels consists of a gated integrator with eight programmable charging rates and an externally programmable gate generator that defines the start (with four time ranges) and width (with four time ranges) of the gate relative to an external discriminator signal. The chip supports three triggering modes, two time ranges, two power modes, and produces four sparsified analog pulse trains (three for the integrators and another for the time) with synchronized addresses for off-chip digitization with a pipelined ADC. The eight-channel prototype chip occupies an area of 2.8 mmx5.7 mm, dissipates 60 mW (low-power mode), and was fabricated in the AMI 0.5-μm process (C5N).

  1. A Higher Brain Circuit for Immediate Integration of Conflicting Sensory Information in Drosophila.

    Science.gov (United States)

    Lewis, Laurence P C; Siju, K P; Aso, Yoshinori; Friedrich, Anja B; Bulteel, Alexander J B; Rubin, Gerald M; Grunwald Kadow, Ilona C

    2015-08-31

    Animals continuously evaluate sensory information to decide on their next action. Different sensory cues, however, often demand opposing behavioral responses. How does the brain process conflicting sensory information during decision making? Here, we show that flies use neural substrates attributed to odor learning and memory, including the mushroom body (MB), for immediate sensory integration and modulation of innate behavior. Drosophila melanogaster must integrate contradictory sensory information during feeding on fermenting fruit that releases both food odor and the innately aversive odor CO2. Here, using this framework, we examine the neural basis for this integration. We have identified a local circuit consisting of specific glutamatergic output and PAM dopaminergic input neurons with overlapping innervation in the MB-β'2 lobe region, which integrates food odor and suppresses innate avoidance. Activation of food odor-responsive dopaminergic neurons reduces innate avoidance mediated by CO2-responsive MB output neurons. We hypothesize that the MB, in addition to its long recognized role in learning and memory, serves as the insect's brain center for immediate sensory integration during instantaneous decision making. Copyright © 2015 Elsevier Ltd. All rights reserved.

  2. Test and diagnosis of analogue, mixed-signal and RF integrated circuits the system on chip approach

    CERN Document Server

    Sun, Yichuang

    2008-01-01

    This book provides a comprehensive discussion of automatic testing, diagnosis and tuning of analogue, mixed-signal and RF integrated circuits, and systems in a single source. The book contains eleven chapters written by leading researchers worldwide. As well as fundamental concepts and techniques, the book reports systematically the state of the arts and future research directions of these areas. A complete range of circuit components are covered and test issues are also addressed from the SoC perspective.

  3. Sparse gallium arsenide to silicon metal waferbonding for heterogeneous monolithic microwave integrated circuits

    Science.gov (United States)

    Bickford, Justin Robert

    Waferbonding is a technique that integrates different semiconductors together, in order to obtain hybrid structures that exploit the strengths of each material. Work was done at the University of California at San Diego to investigate the waferbonding of III/V compound semiconductors to silicon using a metal interface. GaAs and other III/V compound semiconductors surpass silicon in their ability to create high performance microwave devices, while silicon offers an inexpensive platform with a proven digital architecture that can interface with microwave devices and support passive components and driver circuitry. Intimate integration of the two will be required, as mixed RF/digital and optical/digital systems for communications devices such as cell phones, wi-fi, and optical communications systems are pushed smaller, faster, and to higher power. The metalbonding implementation of a proposed heterogeneous monolithic microwave integrated circuit (HMMIC) system was investigated, and was shown to extend the capabilities of existing homogeneous monolithic microwave integrated circuit (MMIC) systems. The main goals of this work were two-fold; first to implement a robust heterogeneous integration technique, and second, to show that this approach uniquely improves upon existing microwave integration technology. The metalbonding technique investigated sparsely integrated GaAs structures onto silicon, in pursuit of this HMMIC scheme. Both bottom-up and top-down fabrication methods were implemented. These approaches required the development of a myriad of meticulously designed fabrication procedures capable of avoiding the many incompatibilities between the compound semiconductor, bondmetal, and silicon materials. The bondmetal interface, provided by these techniques, broadens the scope of existing monolithic microwave integrated circuit technology design possibilities. Essential bond interface properties were measured to establish the performance of this heterogeneous

  4. Sensors, Circuits, and Satellites - NGSS at it's best: the integration of three dimensions with NASA science

    Science.gov (United States)

    Butcher, G. J.; Roberts-Harris, D.

    2013-12-01

    A set of innovative classroom lessons were developed based on informal learning activities in the 'Sensors, Circuits, and Satellites' kit manufactured by littleBits™ Electronics that are designed to lead students through a logical science content storyline about energy using sound and light and fully implements an integrated approach to the three dimensions of the Next Generation of Science Standards (NGSS). This session will illustrate the integration of NGSS into curriculum by deconstructing lesson design to parse out the unique elements of the 3 dimensions of NGSS. We will demonstrate ways in which we have incorporated the NGSS as we believe they were intended. According to the NGSS, 'The real innovation in the NGSS is the requirement that students are required to operate at the intersection of practice, content, and connection. Performance expectations are the right way to integrate the three dimensions. It provides specificity for educators, but it also sets the tone for how science instruction should look in classrooms. (p. 3). The 'Sensors, Circuits, and Satellites' series of lessons accomplishes this by going beyond just focusing on the conceptual knowledge (the disciplinary core ideas) - traditionally approached by mapping lessons to standards. These lessons incorporate the other 2 dimensions -cross-cutting concepts and the 8-practices of Sciences and Engineering-via an authentic and exciting connection to NASA science, thus implementing the NGSS in the way they were designed to be used: practices and content with the crosscutting concepts. When the NGSS are properly integrated, students are engaged in science and engineering content through the coupling of practice, content and connection. In the past, these two dimensions have been separated as distinct entities. We know now that coupling content and practices better demonstrates what goes on in real world science and engineering. We set out to accomplish what is called for in NGSS by integrating these

  5. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

  6. A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

    Science.gov (United States)

    Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

    2014-10-01

    This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

  7. Gallium arsenide digital integrated circuits for controlling SLAC CW-RF systems

    International Nuclear Information System (INIS)

    Ronan, M.T.; Lee, K.L.; Corredoura, P.; Judkins, J.G.

    1988-10-01

    In order to fill the PEP and SPEAR storage rings with beams from the SLC linac and damping rings, precise control of the linac subharmonic buncher and the damping ring RF is required. Recently several companies have developed resettable GaAs master/slave D-type flip-flops which are capable of operating at frequencies of 3 GHz and higher. Using these digital devices as frequency dividers, one can phase shift the SLAC CW-RF systems to optimize the timing for filling the storage rings. We have evaluated the performance of integrated circuits from two vendors for our particular application. Using microstrip circuit techniques, we have built and operated in the accelerator several chassis to synchronize a reset signal from the storage rings to the SLAC 2.856 GHz RF and to phase shift divide-by-four and divide-by-sixteen frequency dividers to the nearest 350 psec bucket required for filling. 4 refs., 4 figs., 2 tabs

  8. Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  9. Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations.

    Science.gov (United States)

    Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A

    2008-12-02

    Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.

  10. Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations

    Science.gov (United States)

    Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y.; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A.

    2008-01-01

    Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ≈1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ≈140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

  11. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    De-Hao Lu

    2010-11-01

    Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  12. Rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC)

    Science.gov (United States)

    Li, Xiuling; Huang, Wen

    2015-04-28

    A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.

  13. Development of high speed integrated circuit for very high resolution timing measurements

    International Nuclear Information System (INIS)

    Mester, Christian

    2009-10-01

    A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described. The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40 MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption. (orig.)

  14. Effects of plasma-deposited silicon nitride passivation on the radiation hardness of CMOS integrated circuits

    International Nuclear Information System (INIS)

    Clement, J.J.

    1980-01-01

    The use of plasma-deposited silicon nitride as a final passivation over metal-gate CMOS integrated circuits degrades the radiation hardness of these devices. The hardness degradation is manifested by increased radiation-induced threshold voltage shifts caused principally by the charging of new interface states and, to a lesser extent, by the trapping of holes created upon exposure to ionizing radiation. The threshold voltage shifts are a strong function of the deposition temperature, and show very little dependence on thickness for films deposited at 300 0 C. There is some correlation between the threshold voltage shifts and the hydrogen content of the PECVD silicon nitride films used as the final passivation layer as a function of deposition temperature. The mechanism by which the hydrogen contained in these films may react with the Si/SiO 2 interface is not clear at this point

  15. Integrated circuits from mobile phones as possible emergency OSL/TL dosimeters

    International Nuclear Information System (INIS)

    Sholom, S.; McKeever, S.W.S.

    2016-01-01

    In this article, optically stimulated luminescence (OSL) data are presented from integrated circuits (ICs) extracted from mobile phones. The purpose is to evaluate the potential of using OSL from components in personal electronic devices such as smart phones as a means of emergency dosimetry in the event of a large-scale radiological incident. ICs were extracted from five different makes and models of mobile phone. Sample preparation procedures are described, and OSL from the IC samples following irradiation using a 90 Sr/ 90 Y source is presented. Repeatability, sensitivity, dose responses, minimum measurable doses, stability and fading data were examined and are described. A protocol for measuring absorbed dose is presented, and it was concluded that OSL from these components is a viable method for assessing dose in the days following a radiological incident. (authors)

  16. Emerging materials and devices in spintronic integrated circuits for energy-smart mobile computing and connectivity

    International Nuclear Information System (INIS)

    Kang, S.H.; Lee, K.

    2013-01-01

    A spintronic integrated circuit (IC) is made of a combination of a semiconductor IC and a dense array of nanometer-scale magnetic tunnel junctions. This emerging field is of growing scientific and engineering interest, owing to its potential to bring disruptive device innovation to the world of electronics. This technology is currently being pursued not only for scalable non-volatile spin-transfer-torque magnetoresistive random access memory, but also for various forms of non-volatile logic (Spin-Logic). This paper reviews recent advances in spintronic IC. Key discoveries and breakthroughs in materials and devices are highlighted in light of the broader perspective of their application in low-energy mobile computing and connectivity systems, which have emerged as leading drivers for the prevailing electronics ecosystem

  17. Laser-induced extreme UV radiation sources for manufacturing next-generation integrated circuits

    International Nuclear Information System (INIS)

    Borisov, V M; Vinokhodov, A Yu; Ivanov, A S; Kiryukhin, Yu B; Mishchenko, V A; Prokof'ev, A V; Khristoforov, O B

    2009-01-01

    The development of high-power discharge sources emitting in the 13.5±0.135-nm spectral band is of current interest because they are promising for applications in industrial EUV (extreme ultraviolet) lithography for manufacturing integrated circuits according to technological precision standards of 22 nm and smaller. The parameters of EUV sources based on a laser-induced discharge in tin vapours between rotating disc electrodes are investigated. The properties of the discharge initiation by laser radiation at different wavelengths are established and the laser pulse parameters providing the maximum energy characteristics of the EUV source are determined. The EUV source developed in the study emits an average power of 276 W in the 13.5±0.135-nm spectral band on conversion to the solid angle 2π sr in the stationary regime at a pulse repetition rate of 3000 Hz. (laser applications and other topics in quantum electronics)

  18. Integrated circuit test-port architecture and method and apparatus of test-port generation

    Science.gov (United States)

    Teifel, John

    2016-04-12

    A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code.

  19. Photonic Integrated Circuits for Cost-Effective, High Port Density, and Higher Capacity Optical Communications Systems

    Science.gov (United States)

    Chiappa, Pierangelo

    Bandwidth-hungry services, such as higher speed Internet, voice over IP (VoIP), and IPTV, allow people to exchange and store huge amounts of data among worldwide locations. In the age of global communications, domestic users, companies, and organizations around the world generate new contents making bandwidth needs grow exponentially, along with the need for new services. These bandwidth and connectivity demands represent a concern for operators who require innovative technologies to be ready for scaling. To respond efficiently to these demands, Alcatel-Lucent is fast moving toward photonic integration circuits technologies as the key to address best performances at the lowest "bit per second" cost. This article describes Alcatel-Lucent's contribution in strategic directions or achievements, as well as possible new developments.

  20. Issues of verification and validation of application-specific integrated circuits in reactor trip systems

    International Nuclear Information System (INIS)

    Battle, R.E.; Alley, G.T.

    1993-01-01

    Concepts of using application-specific integrated circuits (ASICs) in nuclear reactor safety systems are evaluated. The motivation for this evaluation stems from the difficulty of proving that software-based protection systems are adequately reliable. Important issues concerning the reliability of computers and software are identified and used to evaluate features of ASICS. These concepts indicate that ASICs have several advantages over software for simple systems. The primary advantage of ASICs over software is that verification and validation (V ampersand V) of ASICs can be done with much higher confidence than can be done with software. A method of performing this V ampersand V on ASICS is being developed at Oak Ridge National Laboratory. The purpose of the method's being developed is to help eliminate design and fabrication errors. It will not solve problems with incorrect requirements or specifications

  1. Investigation of Planar Waveguides and Components for Millimeter-Wave Integrated Circuits.

    Science.gov (United States)

    1985-03-01

    cntant of fin-line in a WR-28 shield. ..................................... 1A 16 rmodea. 3 .C am - - *’% *jrrode 2 0 M0 e I 2.8. . .4 8.0 3.8 4.6...line with a WR-62 shield. I1 L2- 7.773 mm, 2d -0.254 mm, e,. -2.2, 2b -3.95 mm w1 3 mm, m -17, n -33. 66 0. am - char. fn. 𔃺 0. am 0.36 0.35 6.40...communication trasmitter and receiver system using dielectric waveguide integrated circuits," IEEE Trans. Microwave Theory Tech, vol. M’T-24, pp. 797-803, Nov

  2. A study on the recycling of scrap integrated circuits by leaching.

    Science.gov (United States)

    Lee, Ching-Hwa; Tang, Li-Wen; Popuri, Srinivasa R

    2011-07-01

    In order to minimize the problem of pollution and to conserve limited natural resources, a method to recover the valuable metals such as gold, silver and copper) present in the scrap integrated circuits (ICs) was developed in the present study. Roasting, grinding, screening, magnetic separation, melting and leaching were adopted to investigate the efficiency of recovery of gold, silver and copper from scrap ICs. The collected scrap IC samples were roasted at 850 °C to destroy their plastic resin sealing material, followed by screening and magnetic separation to separate the metals from the resin residue. The non-ferrous materials (0.840 mm) were mainly composed of copper and could be melted into a copper alloy. Non-ferrous materials containing gold (860.05 ppm), silver (1323.12 ppm) and copper (37259.7 ppm) (size less than 50 mesh) were recovered 100% by a leaching process and thiourea was used as a leaching reagent.

  3. Device-level and module-level three-dimensional integrated circuits created using oblique processing

    Science.gov (United States)

    Burckel, D. Bruce

    2016-07-01

    This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

  4. Reducing image noise in computed tomography (CT) colonography: effect of an integrated circuit CT detector.

    Science.gov (United States)

    Liu, Yu; Leng, Shuai; Michalak, Gregory J; Vrieze, Thomas J; Duan, Xinhui; Qu, Mingliang; Shiung, Maria M; McCollough, Cynthia H; Fletcher, Joel G

    2014-01-01

    To investigate whether the integrated circuit (IC) detector results in reduced noise in computed tomography (CT) colonography (CTC). Three hundred sixty-six consecutive patients underwent clinically indicated CTC using the same CT scanner system, except for a difference in CT detectors (IC or conventional). Image noise, patient size, and scanner radiation output (volume CT dose index) were quantitatively compared between patient cohorts using each detector system, with separate comparisons for the abdomen and pelvis. For the abdomen and pelvis, despite significantly larger patient sizes in the IC detector cohort (both P noise was significantly lower (both P 0.18). Based on the observed image noise reduction, radiation dose could alternatively be reduced by approximately 20% to result in similar levels of image noise. Computed tomography colonography images acquired using the IC detector had significantly lower noise than images acquired using the conventional detector. This noise reduction can permit further radiation dose reduction in CTC.

  5. Development of high speed integrated circuit for very high resolution timing measurements

    Energy Technology Data Exchange (ETDEWEB)

    Mester, Christian

    2009-10-15

    A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described. The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40 MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption. (orig.)

  6. Methods and tools for the evaluation of the sensitivity to natural radiations of advanced integrated circuits

    International Nuclear Information System (INIS)

    Peronnard, P.

    2009-10-01

    Atmospheric neutrons, whose fluxes and energies dependent on the altitude, the sun activity and the geographic coordinates, have been identified as being capable to provoke SEE (Single Event Effects), by indirect ionisation, in integrated devices issued from advanced manufacturing processes (nano-metric devices). This concerns not only avionics but also applications operating at ground level. The evaluation of the sensitivity to SEE provoked by natural radiation becomes thus a mandatory step during the selection of devices devoted to be included in applications requiring high reliability. The sensitivity to SEE can be mitigated by different approaches at different levels from manufacturing level (use of particular process technologies such as SOI - Silicon On Isolator -) to the system level (hardware/software redundancy). Independently of the adopted hardening approach, the so-called radiation ground testing are mandatory to evaluate the error rates of a device or a system. During such tests, the DUT (Device Under Test) is exposed to a flux of particles while it performs a given activity. For SEU (Single Event Upsets) radiation ground testing, two main strategies exist: static test: the circuit areas which are supposed to be sensitive to SEUs (registers, memories,...) are initialized with a reference pattern. The content of the sensitive area is periodically compared to the reference pattern to identify potential SEU. Dynamic test: the DUT performs an activity representative of the one it will execute during the final application. Static test: strategies are frequently adopted as they provide the intrinsic sensitivity, in terms of the average number of particles needed to provoke an SEU, of different sensitive areas of the device. From such a strategy can thus be obtained a 'worst case estimation' of the device sensitivity. This thesis aims at giving a description and validating the methodologies required to estimate the sensitivity to radiations of two types of

  7. Design and testing of an all-digital readout integrated circuit for infrared focal plane arrays

    Science.gov (United States)

    Kelly, Michael; Berger, Robert; Colonero, Curtis; Gregg, Mark; Model, Joshua; Mooney, Daniel; Ringdahl, Eric

    2005-08-01

    The digital focal plane array (DFPA) project demonstrates the enabling technologies necessary to build readout integrated circuits for very large infrared focal plane arrays (IR FPAs). Large and fast FPAs are needed for a new class of spectrally diverse sensors. Because of the requirement for high-resolution (low noise) sampling, and because of the sample rate needed for rapid acquisition of high-resolution spectra, it is highly desirable to perform analog-to-digital (A/D) conversion right at the pixel level. A dedicated A/D converter located under every pixel in a one-million-plus element array, and all-digital readout integrated circuits will enable multi- and hyper-spectral imaging systems with unprecedented spatial and spectral resolution and wide area coverage. DFPAs provide similar benefits to standard IR imaging systems as well. We have addressed the key enabling technologies for realizing the DFPA architecture in this work. Our effort concentrated on demonstrating a 60-micron footprint, 14-bit A/D converter and 2.5 Gbps, 16:1 digital multiplexer, the most basic components of the sensor. The silicon test chip was fabricated in a 0.18-micron CMOS process, and was designed to operate with HgxCd1-xTe detectors at cryogenic temperatures. Two A/D designs, one using static logic and one using dynamic logic, were built and tested for performance and power dissipation. Structures for evaluating the bit-error-rate of the multiplexer on-chip and through a differential output driver were implemented for a complete performance assessment. A unique IC probe card with fixtures to mount into an evacuated, closed-cycle helium dewar were also designed for testing up to 2.5 Gbps at temperatures as low as 50 K.

  8. Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

    Science.gov (United States)

    Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

    2015-11-01

    We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80-120%, with respect to the designed bias currents.

  9. Toxicity assessment and modelling of Moringa oleifera seeds in water purification by whole cell bioreporter.

    Science.gov (United States)

    Al-Anizi, Ali Adnan; Hellyer, Maria Theresa; Zhang, Dayi

    2014-06-01

    Moringa oleifera has been used as a coagulation reagent for drinking water purification, especially in developing countries such as Malawi. This research revealed the cytoxicity and genotoxicity of M. oleifera by Acinetobacter bioreporter. The results indicated that significant cytoxicity effects were observed when the powdered M. oleifera seeds concentration is from 1 to 50 mg/L. Through direct contact, ethanolic-water extraction and hexane extraction, the toxic effects of hydrophobic and hydrophilic components in M. oleifera seeds were distinguished. It suggested that the hydrophobic lipids contributed to the dominant cytoxicity, consequently resulting in the dominant genotoxicity in the water-soluble fraction due to limited dissolution when the M. oleifera seeds granule concentration was from 10 to 1000 mg/L. Based on cytoxicity and genotoxicity model, the LC50 and LC90 of M. oleifera seeds were 8.5 mg/L and 300 mg/L respectively and their genotoxicity was equivalent to 8.3 mg mitomycin C per 1.0 g dry M. oleifera seed. The toxicity of M. oleifera has also remarkable synergistic effects, suggesting whole cell bioreporter as an appropriate and complementary tool to chemical analysis for environmental toxicity assessment. Copyright © 2014 Elsevier Ltd. All rights reserved.

  10. Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

    Science.gov (United States)

    Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

    2005-12-01

    Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

  11. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    Science.gov (United States)

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

  12. Whole-cell bioreporters and risk assessment of environmental pollution: A proof-of-concept study using lead.

    Science.gov (United States)

    Zhang, Xiaokai; Qin, Boqiang; Deng, Jianming; Wells, Mona

    2017-10-01

    As the world burden of environmental contamination increases, it is of the utmost importance to develop streamlined approaches to environmental risk assessment in order to prioritize mitigation measures. Whole-cell biosensors or bioreporters and speciation modeling have both become of increasing interest to determine the bioavailability of pollutants, as bioavailability is increasingly in use as an indicator of risk. Herein, we examine whether bioreporter results are able to reflect expectations based on chemical reactivity and speciation modeling, with the hope to extend the research into a wider framework of risk assessment. We study a specific test case concerning the bioavailability of lead (Pb) in aqueous environments containing Pb-complexing ligands. Ligands studied include ethylene diamine tetra-acetic acid (EDTA), meso-2,3 dimercaptosuccinic acid (DMSA), leucine, methionine, cysteine, glutathione, and humic acid (HA), and we also performed experiments using natural water samples from Lake Tai (Taihu), the third largest lake in China. We find that EDTA, DMSA, cysteine, glutathione, and HA amendment significantly reduced Pb bioavailability with increasing ligand concentration according to a log-sigmoid trend. Increasing dissolved organic carbon in Taihu water also had the same effect, whereas leucine and methionine had no notable effect on bioavailability at the concentrations tested. We find that bioreporter results are in accord with the reduction of aqueous Pb 2+ that we expect from the relative complexation affinities of the different ligands tested. For EDTA and HA, for which reasonably accurate ionization and complexation constants are known, speciation modeling is in agreement with bioreporter response to within the level of uncertainty recognised as reasonable by the United States Environmental Protection Agency for speciation-based risk assessment applications. These findings represent a first step toward using bioreporter technology to streamline

  13. Construction of a self- luminescent cyanobacterial bioreporter that detects a broad range of bioavailable heavy metals in aquatic environments

    Directory of Open Access Journals (Sweden)

    Keila eMartin-Betancor

    2015-03-01

    Full Text Available A self-luminescent bioreporter strain of the unicellular cyanobacterium Synechococcus sp. PCC 7942 was constructed by fusing the promoter region of the smt locus (encoding the transcriptional repressor SmtB and the metallothionein SmtA to luxCDABE from Photorhabdus luminescens; the sensor smtB gene controlling the expression of smtA was cloned in the same vector. The bioreporter performance was tested with a range of heavy metals and was shown to respond linearly to divalent Zn, Cd, Cu, Co, Hg and monovalent Ag. Chemical modelling was used to link bioreporter response with metal speciation and bioavailability. Limits of Detection (LODs, Maximum Permissive Concentrations (MPCs and dynamic ranges for each metal were calculated in terms of free ion concentrations. The ranges of detection varied from 11 to 72 pM for Hg2+ (the ion to which the bioreporter was most sensitive to 1.54-5.35 µM for Cd2+ with an order of decreasing sensitivity as follows: Hg2+ >> Cu2+ >> Ag+ > Co2+ ≥ Zn2+ > Cd2+. However, the maximum induction factor reached 75-fold in the case of Zn2+ and 56-fold in the case of Cd2+, implying that Zn2+ is the preferred metal in vivo for the SmtB sensor, followed by Cd2+, Ag+ and Cu2+ (around 45-50-fold induction, Hg2+ (30-fold and finally Co2+ (20-fold. The bioreporter performance was tested in real environmental samples with different water matrix complexity artificially contaminated with increasing concentrations of Zn, Cd, Ag and Cu, confirming its validity as a sensor of free heavy metal cations bioavailability in aquatic environments.

  14. Study of an automatic readout integrated circuit for the signal shaping of the ATLAS electromagnetic calorimeter; Etude d`un circuit integre de commutation automatique de gain pour le circuit de mise en forme du signal du calorimetre electromagnetique d`ATLAS

    Energy Technology Data Exchange (ETDEWEB)

    Bussat, J.M. [Laboratoire d`Annecy-le-Vieux de Physique des Particules, 74 - Annecy-le-Vieux (France)

    1996-12-01

    This paper describes the present state of the development of an automatic readout integrated circuit that can be used, connected to the four gain shaper of LAL, at the ATLAS electromagnetic calorimeter.

  15. A fast charge-integrating sample-and-hold circuit for fast decision-making with calorimeter arrays

    International Nuclear Information System (INIS)

    Schuler, G.

    1982-01-01

    This paper describes a fast charge-integrating sample-and-hold circuit, particularly suited to the fast trigger electronics used with large arrays of photomultipliers in total-energy measurements of high-energy particles interactions. During a gate logic pulse, the circuit charges a capacitor with the current fed into the signal input. The output voltage is equal to the voltage developed across the capacitor, which is held until a fast clear discharges the capacitor. The main characteristics of the fast-charge-integrating sample-and-hold circuit are: i) a conversion factor of 1 V/220 pC; ii) a droop rate of 4 mV/μs for a 50 Ω load; and iii) a 1 μs fast-clear time. (orig.)

  16. Radiation effects for high-energy protons and X-ray in integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Silveira, M.A.G.; Santos, R.B.B. [Centro Universitario da FEI, Sao Bernardo do Campo, SP (Brazil); Medina, N.H.; Added, N.; Tabacniks, M.H. [Universidade de Sao Paulo (IF/USP), SP (Brazil). Inst. de Fisica; Lima, J.A. de [Universidade Federal de Santa Catarina (UFSC), Florianopolis, SC (Brazil); Cirne, K.H. [Empresa Brasileira de Aeronautica S.A. (EMBRAER), Sao Jose dos Campos, SP (Brazil)

    2012-07-01

    Full text: Electronic circuits are strongly influenced by ionizing radiation. The necessity to develop integrated circuits (IC's) featuring radiation hardness is largely growing to meet the stringent environment in space electronics [1]. This work aims to development a test platform to qualify electronic devices under the influence of high radiation dose, for aerospace applications. To understand the physical phenomena responsible for changes in devices exposed to ionizing radiation several kinds of radiation should then be considered, among them heavy ions, alpha particles, protons, gamma and X-rays. Radiation effects on the ICs are usually divided into three categories: Total Ionizing Dose (TID), a cumulative dose that shifts the threshold voltage and increases transistor's off-state current; Single Events Effects (SEE), a transient effect which can deposit charge directly into the device and disturb the properties of electronic circuits and Displacement Damage (DD) which can change the arrangement of the atoms in the lattice [2]. In this study we are investigating the radiation effects in rectangular-gate and circular-gate MOSFETs, manufactured with standard CMOS fabrication process, using particle beams produced in electrostatic tandem accelerators and X-rays. Initial tests for TID effects were performed using the 1.7 MV 5SDH tandem Pelletron accelerator of the Instituto de Fisica da USP with a proton beam of 2.6 MeV. The devices were exposed to different doses, varying the beam current, and irradiation time with the accumulated dose reaching up to Grad. To study the effect of X-rays on the electronic devices, an XRD-7000 (Shimadzu) X-ray setup was used as a primary X-ray source. The devices were irradiated with a total dose from krad to Grad using different dose rates. The results indicate that changes of the I-V characteristic curve are strongly dependents on the geometry of the devices. [1] Duzellier, S., Aerospace Science and Technology 9, p. 93

  17. A microfluidic microprocessor: controlling biomimetic containers and cells using hybrid integrated circuit/microfluidic chips.

    Science.gov (United States)

    Issadore, David; Franke, Thomas; Brown, Keith A; Westervelt, Robert M

    2010-11-07

    We present an integrated platform for performing biological and chemical experiments on a chip based on standard CMOS technology. We have developed a hybrid integrated circuit (IC)/microfluidic chip that can simultaneously control thousands of living cells and pL volumes of fluid, enabling a wide variety of chemical and biological tasks. Taking inspiration from cellular biology, phospholipid bilayer vesicles are used as robust picolitre containers for reagents on the chip. The hybrid chip can be programmed to trap, move, and porate individual living cells and vesicles and fuse and deform vesicles using electric fields. The IC spatially patterns electric fields in a microfluidic chamber using 128 × 256 (32,768) 11 × 11 μm(2) metal pixels, each of which can be individually driven with a radio frequency (RF) voltage. The chip's basic functions can be combined in series to perform complex biological and chemical tasks and can be performed in parallel on the chip's many pixels for high-throughput operations. The hybrid chip operates in two distinct modes, defined by the frequency of the RF voltage applied to the pixels: Voltages at MHz frequencies are used to trap, move, and deform objects using dielectrophoresis and voltages at frequencies below 1 kHz are used for electroporation and electrofusion. This work represents an important step towards miniaturizing the complex chemical and biological experiments used for diagnostics and research onto automated and inexpensive chips.

  18. Soft, smart contact lenses with integrations of wireless circuits, glucose sensors, and displays.

    Science.gov (United States)

    Park, Jihun; Kim, Joohee; Kim, So-Yun; Cheong, Woon Hyung; Jang, Jiuk; Park, Young-Geun; Na, Kyungmin; Kim, Yun-Tae; Heo, Jun Hyuk; Lee, Chang Young; Lee, Jung Heon; Bien, Franklin; Park, Jang-Ung

    2018-01-01

    Recent advances in wearable electronics combined with wireless communications are essential to the realization of medical applications through health monitoring technologies. For example, a smart contact lens, which is capable of monitoring the physiological information of the eye and tear fluid, could provide real-time, noninvasive medical diagnostics. However, previous reports concerning the smart contact lens have indicated that opaque and brittle components have been used to enable the operation of the electronic device, and this could block the user's vision and potentially damage the eye. In addition, the use of expensive and bulky equipment to measure signals from the contact lens sensors could interfere with the user's external activities. Thus, we report an unconventional approach for the fabrication of a soft, smart contact lens in which glucose sensors, wireless power transfer circuits, and display pixels to visualize sensing signals in real time are fully integrated using transparent and stretchable nanostructures. The integration of this display into the smart lens eliminates the need for additional, bulky measurement equipment. This soft, smart contact lens can be transparent, providing a clear view by matching the refractive indices of its locally patterned areas. The resulting soft, smart contact lens provides real-time, wireless operation, and there are in vivo tests to monitor the glucose concentration in tears (suitable for determining the fasting glucose level in the tears of diabetic patients) and, simultaneously, to provide sensing results through the contact lens display.

  19. Measurement of the Boltzmann constant by Johnson noise thermometry using a superconducting integrated circuit

    Science.gov (United States)

    Urano, C.; Yamazawa, K.; Kaneko, N.-H.

    2017-12-01

    We report on our measurement of the Boltzmann constant by Johnson noise thermometry (JNT) using an integrated quantum voltage noise source (IQVNS) that is fully implemented with superconducting integrated circuit technology. The IQVNS generates calculable pseudo white noise voltages to calibrate the JNT system. The thermal noise of a sensing resistor placed at the temperature of the triple point of water was measured precisely by the IQVNS-based JNT. We accumulated data of more than 429 200 s in total (over 6 d) and used the Akaike information criterion to estimate the fitting frequency range for the quadratic model to calculate the Boltzmann constant. Upon detailed evaluation of the uncertainty components, the experimentally obtained Boltzmann constant was k=1.380 6436× {{10}-23} J K-1 with a relative combined uncertainty of 10.22× {{10}-6} . The value of k is relatively -3.56× {{10}-6} lower than the CODATA 2014 value (Mohr et al 2016 Rev. Mod. Phys. 88 035009).

  20. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

    CERN Document Server

    Lim, Sung Kyu

    2013-01-01

    This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits.  It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs.  Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process. Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability. Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the e...

  1. Synaptic and intrinsic homeostasis cooperate to optimize single neuron response properties and tune integrator circuits

    Science.gov (United States)

    2016-01-01

    Homeostatic processes that provide negative feedback to regulate neuronal firing rate are essential for normal brain function, and observations suggest that multiple such processes may operate simultaneously in the same network. We pose two questions: why might a diversity of homeostatic pathways be necessary, and how can they operate in concert without opposing and undermining each other? To address these questions, we perform a computational and analytical study of cell-intrinsic homeostasis and synaptic homeostasis in single-neuron and recurrent circuit models. We demonstrate analytically and in simulation that when two such mechanisms are controlled on a long time scale by firing rate via simple and general feedback rules, they can robustly operate in tandem to tune the mean and variance of single neuron's firing rate to desired goals. This property allows the system to recover desired behavior after chronic changes in input statistics. We illustrate the power of this homeostatic tuning scheme by using it to regain high mutual information between neuronal input and output after major changes in input statistics. We then show that such dual homeostasis can be applied to tune the behavior of a neural integrator, a system that is notoriously sensitive to variation in parameters. These results are robust to variation in goals and model parameters. We argue that a set of homeostatic processes that appear to redundantly regulate mean firing rate may work together to control firing rate mean and variance and thus maintain performance in a parameter-sensitive task such as integration. PMID:27306675

  2. An integrated circuit/microsystem/nano-enhanced four species radiation sensor for inexpensive fissionable material detection

    Science.gov (United States)

    Waguespack, Randy Paul

    2011-12-01

    Small scale radiation detectors sensitive to alpha, beta, electromagnetic, neutron radiation are needed to combat the threat of nuclear terrorism and maintain national security. There are many types of radiation detectors on the market, and the type of detector chosen is usually determined by the type of particle to be detected. In the case of fissionable material, an ideal detector needs to detect all four types of radiation, which is not the focus of many detectors. For fissionable materials, the two main types of radiation that must be detected are gamma rays and neutrons. Our detector uses a glass or quartz scintillator doped with 10B nanoparticles to detect all four types of radiation particles. Boron-10 has a thermal neutron cross section of 3,840 barns. The interaction between the neutron and boron results in a secondary charge particle in the form of an alpha particle to be emitted, which is detectable by the scintillator. Radiation impinging on the scintillator matrix produces varying optical pulses dependent on the energy of the particles. The optical pulses are then detected by a photomultiplier (PM) tube, creating a current proportional to the energy of the particle. Current pulses from the PM tube are differentiated by on-chip pulse height spectroscopy, allowing for source discrimination. The pulse height circuitry has been fabricated with discrete circuits and designed into an integrated circuit package. The ability to replace traditional PM tubes with a smaller, less expensive photomultiplier will further reduce the size of the device and enhance the cost effectiveness and portability of the detector.

  3. Inclusion of Body-Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

    Science.gov (United States)

    Neudeck, Philip G.

    2017-01-01

    The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

  4. Inclusion of Body Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

    Science.gov (United States)

    Neudeck, Philip G.

    2017-01-01

    The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 degrees Celsius durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

  5. Printed Circuit Boards with Integrated Heat Carrier Channels for Deep Geothermal Resources

    Science.gov (United States)

    Krühn, T.; Overmeyer, L.

    2012-04-01

    The exploration of deep geothermal resources is still very expensive. A large amount of these costs is caused by the drilling process. The high price results from a high failure risk, slow drilling progress and a large amount of manual work. To develop deep heat mining to a sizeable contribution to the European energy portfolio, the exploration process has to become a lot cheaper. One step to achieve lower costs is to monitor and automate the drilling process. Therefore, electronic components such as sensors and data processing units must be integrated into the Bottom Hole Assembly (BHA). The integration of electronics into the BHA faces the challenge of high ambient temperatures. The project "Packaging of Electronic Components for High Temperature Applications" within the "Geothermal Energy and High Performance-Drilling Collaborative Research Program (gebo)" develops a system of heat carrier channels integrated in printed circuit boards (PCB). These channels can be perfused with fluids such as water, oil or gas and provide high heat convection rates. Such PCBs will be able to withstand high ambient temperatures up to 250 °C. We have simulated, manufactured and are currently testing prototype boards with integrated heat carrier channels featuring a thickness of only 1.6 mm. As a simulation scenario, we chose a board measuring 25 mm x 100 mm, dimensions suitable for integration into a BHA. An ambient temperature of 250 °C was used. The simulation results presented in this contribution illustrate that cooling of the whole board as well as cooling of hotspots is possible. The cooling channel layout being the key for high convection rates was meticulously studied and optimized. Parameters such as necessary flow rate and fluid pressure were adjusted accordingly. Preliminary experiments validate the demonstrated and discussed simulation results. With the proposed cooling system, it is possible to integrate microelectronic components into the BHA for drilling

  6. Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

    Science.gov (United States)

    Alt, Shannon

    2016-01-01

    Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

  7. Exploring the Technological Collaboration Characteristics of the Global Integrated Circuit Manufacturing Industry

    Directory of Open Access Journals (Sweden)

    Yun Liu

    2018-01-01

    Full Text Available With the intensification of international competition, there are many international technological collaborations in the integrated circuit manufacturing (ICM industry. The importance of improving the level of international technological collaboration is becoming more and more prominent. Therefore, it is vital for a country, a region, or an institution to understand the international technological collaboration characteristics of the ICM industry and, thus, to know how to enhance its own international technological collaboration. This paper depicts the international technological collaboration characteristics of the ICM industry based on patent analysis. Four aspects, which include collaboration patterns, collaboration networks, collaboration institutions, and collaboration impacts, are analyzed by utilizing patent association analysis and social network analysis. The findings include the following: first, in regard to international technological collaboration, the USA has the highest level, while Germany has great potential for future development; second, Asia and Europe have already formed clusters, respectively, in the cooperative network; last, but not least, research institutions, colleges, and universities should also actively participate in international collaboration. In general, this study provides an objective reference for policy making, competitiveness, and sustainability in the ICM industry. The framework presented in this paper could be applied to examine other industrial international technological collaborations.

  8. Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

    Science.gov (United States)

    Chen, Meng; Lei, Jiefeng; Huang, Shengxiang; Liao, Congwei; Deng, Lianwen

    2017-06-01

    A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive {V}{TH} shift within 0.4 V and negative {V}{TH} shift within -1.2 V and it is robust and promising for high-resolution display. Project supported by the Science and Technology Project of Hunan Province, China (No. 2015JC3401)

  9. Corrosion of silicon integrated circuits and lifetime predictions in implantable electronic devices

    Science.gov (United States)

    Vanhoestenberghe, A.; Donaldson, N.

    2013-06-01

    Corrosion is a prime concern for active implantable devices. In this paper we review the principles underlying the concepts of hermetic packages and encapsulation, used to protect implanted electronics, some of which remain widely overlooked. We discuss how technological advances have created a need to update the way we evaluate the suitability of both protection methods. We demonstrate how lifetime predictability is lost for very small hermetic packages and introduce a single parameter to compare different packages, with an equation to calculate the minimum sensitivity required from a test method to guarantee a given lifetime. In the second part of this paper, we review the literature on the corrosion of encapsulated integrated circuits (ICs) and, following a new analysis of published data, we propose an equation for the pre-corrosion lifetime of implanted ICs, and discuss the influence of the temperature, relative humidity, encapsulation and field-strength. As any new protection will be tested under accelerated conditions, we demonstrate the sensitivity of acceleration factors to some inaccurately known parameters. These results are relevant for any application of electronics working in a moist environment. Our comparison of encapsulation and hermetic packages suggests that both concepts may be suitable for future implants.

  10. Metamaterial CRLH Antennas on Silicon Substrate for Millimeter-Wave Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Gheorghe Ioan Sajin

    2012-01-01

    Full Text Available The paper presents two composite right/left-handed (CRLH coplanar waveguide (CPW zeroth-order resonant (ZOR antennas which were designed, processed, and electrically characterized for applications in the millimetric wave frequency range. Two CRLH antennas were developed for f=27 GHz and f=38.5, GHz, respectively. The CRLH antenna on f=27 GHz shows a return loss of RL<−18.78 dB at f=26.88 GHz. The −3 dB radiation characteristic beamwidth was approximately 37° and the gain was Gi=2.82 dBi. The CRLH antenna on f=38.5 GHz has a return loss of RL<−38.5 dB at f=38.82 GHz and the −3 dB radiation characteristic beamwidth of approximately 17°. The gains were Gi=1.08 dBi at f=38 GHz and Gi=1.2 dBi at f=38.6 GHz. The maximum measured gain was Gi=1.75 dBi at f=38.2 GHz. It is, upon the authors' knowledge, the first report of millimeter wave CRLH antennas on silicon substrate in CPW technique for use in mm-wave monolithic integrated circuit.

  11. Development of high-performance printed organic field-effect transistors and integrated circuits.

    Science.gov (United States)

    Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

    2015-10-28

    Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications.

  12. Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

    Science.gov (United States)

    Bellofatto, Ralph E [Ridgefield, CT; Ellavsky, Matthew R [Rochester, MN; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Gooding, Thomas M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Hehenberger, Lance G [Leander, TX; Ohmacht, Martin [Yorktown Heights, NY

    2012-03-20

    An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

  13. High figure-of-merit SOI power LDMOS for power integrated circuits

    Directory of Open Access Journals (Sweden)

    Yashvir Singh

    2015-06-01

    Full Text Available The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS are carried out to improve the breakdown voltage, on-resistance, gate-charge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two separate trenches build in the drift region and single source and drain contacts are taken on the top. The trench structure reduces the electric field inside the drift region and allow increased drift layer doping concentration leading to higher breakdown voltage, lower specific on-resistance, reduced gate-drain charge, and substantial improvement in the figure-of-merits. Using two-dimensional simulations, the performance of the proposed LDMOS is optimized and results are compared with the conventional LDMOS. Our simulation results show that the proposed device exhibits 110% higher breakdown voltage, 40% reduction in cell pitch, 19% lower specific on-resistance, 30% lower gate-to-drain charge leading to 5.5 times improvement in Baliga's figure-of-merit and 43% reduction in dynamic figure-of-merit over the conventional device.

  14. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Multimedia

    Liberali, V; Rizzi, A; Re, V; Minuti, M; Pangaud, P; Barbero, M B; Kluit, R; Hinchliffe, I; Manghisoni, M; Giubilato, P; Faccio, F; Pernegger, H; Krueger, H; Gensolen, F D; Bilei, G M; Da rocha rolo, M D; Prydderch, M L; Fanucci, L; Grillo, A A; Bellazzini, R; Palomo pinto, F R; Michelis, S; Huegging, F G; Kishishita, T; Marchiori, G; Christian, D C; Kaestli, H C; Meier, B; Andreazza, A; Key-charriere, M; Linssen, L; Dannheim, D; Conti, E; Hemperek, T; Menouni, M; Fougeron, D; Genat, J; Bomben, M; Marzocca, C; Demaria, N; Mazza, G; Van bakel, N A; Palla, F; Grippo, M T; Magazzu, G; Ratti, L; Abbaneo, D; Crescioli, F; Deptuch, G W; Neue, G; De robertis, G; Passeri, D; Placidi, P; Pacher, L; Gromov, V; Morsani, F; Paccagnella, A; Christiansen, J; Dho, E; Wermes, N; Rymaszewski, P; Rozanov, A; Wang, A; Lipton, R J; Havranek, M; Neviani, A; Marconi, S; Karagounis, M; Godiot, S; Calderini, G; Seidel, S C; Horisberger, R P; Garcia-sciveres, M A; Stabile, A; Beccherle, R; Bacchetta, N

    The present hybrid pixel detectors in operation at the LHC represent a major achievement. They deployed a new technology on an unprecedented scale and their success firmly established pixel tracking as indispensable for future HEP experiments. However, extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. We propose a new RD collaboration specifically focused on the development of pixel readout Integrated Circuits (IC). The IC challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm$^{2}$), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. We propose a collaboration to design the next generation of hybrid pixel readout chips to enable the ATLAS and CMS Phase 2 pixel upgrades. This does not imply that ATLAS and CMS must use the same exact pixel readout chip, as most of the dev...

  15. A bipolar analog front-end integrated circuit for the SDC silicon tracker

    International Nuclear Information System (INIS)

    Kipnis, I.; Spieler, H.; Collins, T.

    1993-11-01

    A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using AT ampersand T's CBIC-U2, 4 GHz f T complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 μm pitch double-sided silicon strip detector. The chip measures 6.8 mm x 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a Φ=10 14 protons/cm 2 have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process

  16. Testing of interposer-based 2.5D integrated circuits

    CERN Document Server

    Wang, Ran

    2017-01-01

    This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and dela...

  17. Geometrical tuning art for entirely subwavelength grating waveguide based integrated photonics circuits.

    Science.gov (United States)

    Wang, Zheng; Xu, Xiaochuan; Fan, Donglei; Wang, Yaguo; Subbaraman, Harish; Chen, Ray T

    2016-05-05

    Subwavelength grating (SWG) waveguide is an intriguing alternative to conventional optical waveguides due to the extra degree of freedom it offers in tuning a few important waveguide properties, such as dispersion and refractive index. Devices based on SWG waveguides have demonstrated impressive performances compared to conventional waveguides. However, the high loss of SWG waveguide bends jeopardizes their applications in integrated photonic circuits. In this work, we propose a geometrical tuning art, which realizes a pre-distorted refractive index profile in SWG waveguide bends. The pre-distorted refractive index profile can effectively reduce the mode mismatch and radiation loss simultaneously, thus significantly reduce the bend loss. This geometry tuning art has been numerically optimized and experimentally demonstrated in present study. Through such tuning, the average insertion loss of a 5 μm SWG waveguide bend is reduced drastically from 5.43 dB to 1.10 dB per 90° bend for quasi-TE polarization. In the future, the proposed scheme will be utilized to enhance performance of a wide range of SWG waveguide based photonics devices.

  18. DCal: A custom integrated circuit for calorimetry at the International Linear Collider

    Energy Technology Data Exchange (ETDEWEB)

    Hoff, James R.; Mekkaoui, Abderrazek; Yarema, Ray; /Fermilab; Drake, Gary; Repond, Jose; /Argonne

    2005-10-01

    A research and development collaboration has been started with the goal of producing a prototype hadron calorimeter section for the purpose of proving the Particle Flow Algorithm concept for the International Linear Collider. Given the unique requirements of a Particle Flow Algorithm calorimeter, custom readout electronics must be developed to service these detectors. This paper introduces the DCal or Digital Calorimetry Chip, a custom integrated circuit developed in a 0.25um CMOS process specifically for this International Linear Collider project. The DCal is capable of handling 64 channels, producing a 1-bit Digital-to-Analog conversion of the input (i.e. hit/no hit). It maintains a 24-bit timestamp and is capable of operating either in an externally triggered mode or in a self-triggered mode. Moreover, it is capable of operating either with or without a pipeline delay. Finally, in order to permit the testing of different calorimeter technologies, its analog front end is capable of servicing Particle Flow Algorithm calorimeters made from either Resistive Plate Chambers or Gaseous Electron Multipliers.

  19. Prolonged silicon carbide integrated circuit operation in Venus surface atmospheric conditions

    Directory of Open Access Journals (Sweden)

    Philip G. Neudeck

    2016-12-01

    Full Text Available The prolonged operation of semiconductor integrated circuits (ICs needed for long-duration exploration of the surface of Venus has proven insurmountably challenging to date due to the ∼ 460 °C, ∼ 9.4 MPa caustic environment. Past and planned Venus landers have been limited to a few hours of surface operation, even when IC electronics needed for basic lander operation are protected with heavily cumbersome pressure vessels and cooling measures. Here we demonstrate vastly longer (weeks electrical operation of two silicon carbide (4H-SiC junction field effect transistor (JFET ring oscillator ICs tested with chips directly exposed (no cooling and no protective chip packaging to a high-fidelity physical and chemical reproduction of Venus’ surface atmosphere. This represents more than 100-fold extension of demonstrated Venus environment electronics durability. With further technology maturation, such SiC IC electronics could drastically improve Venus lander designs and mission concepts, fundamentally enabling long-duration enhanced missions to the surface of Venus.

  20. Integrated digital printing of flexible circuits for wireless sensing (Conference Presentation)

    Science.gov (United States)

    Mei, Ping; Whiting, Gregory L.; Schwartz, David E.; Ng, Tse Nga; Krusor, Brent S.; Ready, Steve E.; Daniel, George; Veres, Janos; Street, Bob

    2016-09-01

    Wireless sensing has broad applications in a wide variety of fields such as infrastructure monitoring, chemistry, environmental engineering and cold supply chain management. Further development of sensing systems will focus on achieving light weight, flexibility, low power consumption and low cost. Fully printed electronics provide excellent flexibility and customizability, as well as the potential for low cost and large area applications, but lack solutions for high-density, high-performance circuitry. Conventional electronics mounted on flexible printed circuit boards provide high performance but are not digitally fabricated or readily customizable. Incorporation of small silicon dies or packaged chips into a printed platform enables high performance without compromising flexibility or cost. At PARC, we combine high functionality c-Si CMOS and digitally printed components and interconnects to create an integrated platform that can read and process multiple discrete sensors. Our approach facilitates customization to a wide variety of sensors and user interfaces suitable for a broad range of applications including remote monitoring of health, structures and environment. This talk will describe several examples of printed wireless sensing systems. The technologies required for these sensor systems are a mix of novel sensors, printing processes, conventional microchips, flexible substrates and energy harvesting power solutions.

  1. Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

    Directory of Open Access Journals (Sweden)

    Mohammed Darmi

    2017-10-01

    Full Text Available As we increasingly use advanced technology nodes to design integrated circuits (ICs, physical designers and electronic design automation (EDA providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR. An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics’ physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS and total negative slack (TNS improved up to 13% and 56%, respectively, compared to the baseline flow.

  2. A 64-channel integrated circuit for signal readout from coordinate detectors

    International Nuclear Information System (INIS)

    Aulchenko, V.; Shekhtman, L.; Zhulanov, V.

    2017-01-01

    A specialized integrated circuit was developed for the readout of signal from coordinate detectors of different types, including gas micro-pattern detectors and silicon microstrip detectors. The ASIC includes 64 channels, each containing a low-noise charge-sensitive amplifier with a connectable feedback capacitor and resistor, and fast reset of the feedback capacitor. Each channel of the ASIC also contains 100 cells of analogue memory where the signal can be stored at a rate of 10 MHz. The pitch of input pads is 50 μm and the chip size is 5× 5 mm 2 . The equivalent noise charge of the ASIC channel is about 2000 electrons with 10 pF capacitance at the input and maximal signal before saturation corresponds to 2× 10 6 electrons. The first application for this ASIC is the detector for imaging of explosions at a synchrotron radiation beam (DIMEX), where it has to substitute the old and slower APC128 ASIC. The full-size electronics including 8 ASICs for 512 channels was assembled and tested.

  3. A monolithic lead sulfide-silicon MOS integrated-circuit structure

    Science.gov (United States)

    Jhabvala, M. D.; Barrett, J. R.

    1982-01-01

    A technique is developed for directly integrating infrared photoconductive PbS detector material with MOS transistors. A layer of chromium, instead of aluminum, is deposited followed by a gold deposition in order to ensure device survival during the chemical deposition of the PbS. Among other devices, a structure was fabricated and evaluated in which the PbS was directly coupled to the gate of a PMOS. The external bias, load, and source resistors were connected and the circuit was operated as a source-follower amplifier. Radiometric evaluations were performed on a variety of different MOSFETs of different geometry. In addition, various detector elements were simultaneously fabricated to demonstrate small element capability, and it was shown that elements of 25 x 25 microns could easily be fabricated. Results of room temperature evaluations using a filtered 700 K black body source yielded a detectivity at peak wavelength of 10 to the 11th cm (root Hz)/W at 100 Hz chopping frequency.

  4. Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-Il Dan; Ko, Hyoungho

    2015-10-14

    Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

  5. Micromachined piezoresistive inclinometer with oscillator-based integrated interface circuit and temperature readout

    Science.gov (United States)

    Dalola, Simone; Ferrari, Vittorio; Marioli, Daniele

    2012-03-01

    In this paper a dual-chip system for inclination measurement is presented. It consists of a MEMS (microelectromechanical system) piezoresistive accelerometer manufactured in silicon bulk micromachining and a CMOS (complementary metal oxide semiconductor) ASIC (application specific integrated circuit) interface designed for resistive-bridge sensors. The sensor is composed of a seismic mass symmetrically suspended by means of four flexure beams that integrate two piezoresistors each to detect the applied static acceleration, which is related to inclination with respect to the gravity vector. The ASIC interface is based on a relaxation oscillator where the frequency and the duty cycle of a rectangular-wave output signal are related to the fractional bridge imbalance and the overall bridge resistance of the sensor, respectively. The latter is a function of temperature; therefore the sensing element itself can be advantageously used to derive information for its own thermal compensation. DC current excitation of the sensor makes the configuration unaffected by wire resistances and parasitic capacitances. Therefore, a modular system results where the sensor can be placed remotely from the electronics without suffering accuracy degradation. The inclination measurement system has been characterized as a function of the applied inclination angle at different temperatures. At room temperature, the experimental sensitivity of the system results in about 148 Hz/g, which corresponds to an angular sensitivity around zero inclination angle of about 2.58 Hz deg-1. This is in agreement with finite element method simulations. The measured output fluctuations at constant temperature determine an equivalent resolution of about 0.1° at midrange. In the temperature range of 25-65 °C the system sensitivity decreases by about 10%, which is less than the variation due to the microsensor alone thanks to thermal compensation provided by the current excitation of the bridge and the positive

  6. Integrated circuits for volumetric ultrasound imaging with 2-D CMUT arrays.

    Science.gov (United States)

    Bhuyan, Anshuman; Choe, Jung Woo; Lee, Byung Chul; Wygant, Ira O; Nikoozadeh, Amin; Oralkan, Ömer; Khuri-Yakub, Butrus T

    2013-12-01

    Real-time volumetric ultrasound imaging systems require transmit and receive circuitry to generate ultrasound beams and process received echo signals. The complexity of building such a system is high due to requirement of the front-end electronics needing to be very close to the transducer. A large number of elements also need to be interfaced to the back-end system and image processing of a large dataset could affect the imaging volume rate. In this work, we present a 3-D imaging system using capacitive micromachined ultrasonic transducer (CMUT) technology that addresses many of the challenges in building such a system. We demonstrate two approaches in integrating the transducer and the front-end electronics. The transducer is a 5-MHz CMUT array with an 8 mm × 8 mm aperture size. The aperture consists of 1024 elements (32 × 32) with an element pitch of 250 μm. An integrated circuit (IC) consists of a transmit beamformer and receive circuitry to improve the noise performance of the overall system. The assembly was interfaced with an FPGA and a back-end system (comprising of a data acquisition system and PC). The FPGA provided the digital I/O signals for the IC and the back-end system was used to process the received RF echo data (from the IC) and reconstruct the volume image using a phased array imaging approach. Imaging experiments were performed using wire and spring targets, a ventricle model and a human prostrate. Real-time volumetric images were captured at 5 volumes per second and are presented in this paper.

  7. Diketopiperazines produced by the halophilic archaeon, Haloterrigena hispanica, activate AHL bioreporters.

    Science.gov (United States)

    Tommonaro, Giuseppina; Abbamondi, Gennaro Roberto; Iodice, Carmine; Tait, Karen; De Rosa, Salvatore

    2012-04-01

    The generic term "quorum sensing" has been adopted to describe the bacterial cell-to-cell communication mechanism which coordinates gene expression when the population has reached a high cell density. Quorum sensing depends on the synthesis of small molecules that diffuse in and out of bacterial cells. There are few reports about this mechanism in Archaea. We report the isolation and chemical characterization of small molecules belonging to class of diketopiperazines (DKPs) in Haloterrigena hispanica, an extremely halophilic archaeon. One of the DKPs isolated, the compound cyclo-(L-prolyl-L-valine) activated N-acyl homoserine lactone (AHL) bioreporters, indicating that Archaea may have the ability to interact with AHL-producing bacteria within mixed communities.

  8. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    Science.gov (United States)

    2016-01-20

    Digital CMOS Circuits* *This work was sponsored by the Assistant Secretary of Defense...control. The ultimate sensitivity limitation of a CCD is set by the readout noise of the output amplifier that senses the charge packets and...all‐ digital CMOS readout circuits. The term "photon counting" is used broadly here to mean digital recording of a photon arrival within the

  9. Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

    International Nuclear Information System (INIS)

    Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

    2015-01-01

    Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

  10. Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

    Energy Technology Data Exchange (ETDEWEB)

    Yamada, Takahiro, E-mail: yamada-takahiro@aist.go.jp [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Maezawa, Masaaki [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Urano, Chiharu [National Metrology Institute of Japan, National Institute of Advanced Industrial Science and Technology, Central 3, Umezono 1-1-1, Tsukuba, Ibaraki 305-8563 (Japan)

    2015-11-15

    Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

  11. Pyrolysis characteristics of integrated circuit boards at various particle sizes and temperatures

    International Nuclear Information System (INIS)

    Chiang, H.-L.; Lin, K.-H.; Lai, M.-H.; Chen, T.-C.; Ma, S.-Y.

    2007-01-01

    A pyrolysis method was employed to recycle the metals and brominated compounds blended into printed circuit boards. This research investigated the effect of particle size and process temperature on the element composition of IC boards and pyrolytic residues, liquid products, and water-soluble ionic species in the exhaust, with the overall goal being to identify the pyrolysis conditions that will have the least impact on the environment. Integrated circuit (IC) boards were crushed into 5-40 mesh (0.71-4.4 mm), and the crushed particles were pyrolyzed at temperatures ranging from 200 to 500 deg. C. The thermal decomposition kinetics were measured by a thermogravimetric (TG) analyzer. The composition of pyrolytic residues was analyzed by Energy Dispersive X-ray Spectrometer (EDS), Inductively Coupled Plasma Atomic Emission Spectrometer (ICP-AES) and Inductively Coupled Plasma-Mass Spectrometry (ICP-MS). In addition, the element compositions of liquid products were analyzed by ICP-AES and ICP-MS. Pyrolytic exhaust was collected by a water-absorption system in an ice-bath cooler, and IC analysis showed that the absorbed solution comprised 11 ionic species. Based on the pyrolytic kinetic parameters of TG analysis and pyrolytic residues at various temperatures for 30 min, the effect of particle size was insignificant in this study, and temperature was the key factor for the IC board pyrolysis. Two stages of decomposition were found for IC board pyrolysis under nitrogen atmosphere. The activation energy was 38-47 kcal/mol for the first-stage reaction and 5.2-9.4 kcal/mol for the second-stage reaction. Metal content was low in the liquid by-product of the IC board pyrolysis process, which is an advantage in that the liquid product could be used as a fuel. Brominate and ammonium were the main water-soluble ionic species of the pyrolytic exhaust. A plan for their safe and effective disposal must be developed if the pyrolytic recycling process is to be applied to IC boards

  12. Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

    2014-10-28

    The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

  13. Study and characterization of an integrated circuit-deposited hydrogenated amorphous silicon sensor for the detection of particles and radiations

    International Nuclear Information System (INIS)

    Despeisse, M.

    2006-03-01

    Next generation experiments at the European laboratory of particle physics (CERN) require particle detector alternatives to actual silicon detectors. This thesis presents a novel detector technology, which is based on the deposition of a hydrogenated amorphous silicon sensor on top of an integrated circuit. Performance and limitations of this technology have been assessed for the first time in this thesis in the context of particle detectors. Specific integrated circuits have been designed and the detector segmentation, the interface sensor-chip and the sensor leakage current have been studied in details. The signal induced by the track of an ionizing particle in the sensor has been characterized and results on the signal speed, amplitude and on the sensor resistance to radiation are presented. The results are promising regarding the use of this novel technology for radiation detection, though limitations have been shown for particle physics application. (author)

  14. Sol-Gel Zinc Oxide Humidity Sensors Integrated with a Ring Oscillator Circuit On-a-Chip

    Directory of Open Access Journals (Sweden)

    Ming-Zhi Yang

    2014-10-01

    Full Text Available The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

  15. Pseudomonas fluorescens HK44: Lessons Lerned from a Model Whole-Cell Bioreporter with a Broad Application History

    Czech Academy of Sciences Publication Activity Database

    Trögl, J.; Chauhan, A.; Ripp, S.; Layton, A.C.; Kuncová, Gabriela; Sayler, G.S.

    2012-01-01

    Roč. 12, č. 2 (2012), s. 1544-1571 ISSN 1424-8220 R&D Projects: GA MŠk ME 892; GA MŠk ME 893 Grant - others:USDA(US) 2009-39210-20230 Institutional research plan: CEZ:AV0Z40720504 Keywords : bioluminiscence * bioreporter * biosensors Subject RIV: EI - Biotechnology ; Bionics Impact factor: 1.953, year: 2012

  16. How thin barrier metal can be used to prevent Co diffusion in the modern integrated circuits?

    International Nuclear Information System (INIS)

    Dixit, Hemant; Konar, Aniruddha; Pandey, Rajan; Ethirajan, Tamilmani

    2017-01-01

    In modern integrated circuits (ICs), billions of transistors are connected to each other via thin metal layers (e.g. copper, cobalt, etc) known as interconnects. At elevated process temperatures, inter-diffusion of atomic species can occur among these metal layers, causing sub-optimal performance of interconnects, which may lead to the failure of an IC. Thus, typically a thin barrier metal layer is used to prevent the inter-diffusion of atomic species within interconnects. For ICs with sub-10 nm transistors (10 nm technology node), the design rule (thickness scaling) demands the thinnest possible barrier layer. Therefore, here we investigate the critical thickness of a titanium–nitride (TiN) barrier that can prevent the cobalt diffusion using multi-scale modeling and simulations. First, we compute the Co diffusion barrier in crystalline and amorphous TiN with the nudged elastic band method within first-principles density functional theory simulations. Later, using the calculated activation energy barriers, we quantify the Co diffusion length in the TiN metal layer with the help of kinetic Monte Carlo simulations. Such a multi-scale modelling approach yields an exact critical thickness of the metal layer sufficient to prevent the Co diffusion in IC interconnects. We obtain a diffusion length of a maximum of 2 nm for a typical process of thermal annealing at 400 °C for 30 min. Our study thus provides useful physical insights for the Co diffusion in the TiN layer and further quantifies the critical thickness (∼2 nm) to which the metal barrier layer can be thinned down for sub-10 nm ICs. (paper)

  17. Direct intertectal inputs are an integral component of the bilateral sensorimotor circuit for behavior in Xenopus tadpoles.

    Science.gov (United States)

    Gambrill, Abigail C; Faulkner, Regina L; Cline, Hollis T

    2018-02-14

    The circuit controlling visually-guided behavior in non-mammalian vertebrates, like Xenopus tadpoles, includes retinal projections to the contralateral optic tectum, where visual information is processed, and tectal motor outputs projecting ipsilaterally to hindbrain and spinal cord. Tadpoles have an intertectal commissure whose function is unknown, but it might transfer information between the tectal lobes. Differences in visual experience between the two eyes have profound effects on the development and function of visual circuits in animals with binocular vision, but the effects on animals with fully-crossed retinal projections are not clear. We tested the effect of monocular visual experience on the visuomotor circuit in Xenopus tadpoles. We show that cutting the intertectal commissure or providing visual experience to one eye (monocular visual experience) are both sufficient to disrupt tectally-mediated visual avoidance behavior. Monocular visual experience induces asymmetry in tectal circuit activity across the midline. Repeated exposure to monocular visual experience drives maturation of the stimulated retinotectal synapses, seen as increased AMPA/NMDA ratios, induces synaptic plasticity in intertectal synaptic connections and induces bilaterally asymmetric changes in the tectal excitation/inhibition ratio (E/I). We show that unilateral expression of peptides that interfere with AMPA or GABAA receptor trafficking alters E/I in the transfected tectum and is sufficient to degrade visuomotor behavior. Our study demonstrates that monocular visual experience in animals with fully-crossed visual systems produces asymmetric circuit function across the midline and degrades visuomotor behavior. The data further suggest that intertectal inputs are an integral component of a bilateral visuomotor circuit critical for behavior.

  18. Temperature control system for the study of single event effects in integrated circuits using a cyclotron accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Bakerenkov, A.S., E-mail: as_bakerenkov@list.ru [National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Moscow (Russian Federation); Belyakov, V.V. [National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Moscow (Russian Federation); Kozyukov, A.E. [Joint-Stock Company Institute of Space Device Engineering (JSC ISDE), Moscow (Russian Federation); Pershenkov, V.S.; Solomatin, A.V.; Shurenkov, V.V. [National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Moscow (Russian Federation)

    2015-02-11

    The temperature control system for the study of single event disruptions produced by hard ion impacts in integrated circuits is described. Heating and cooling of the irradiated device are achieved using thermoelectric modules (Peltier modules). The thermodynamic performance of the system is estimated. The technique for the numerical estimation of the main parameters of the temperature control system for cooling and heating is considered. The results of a test of the system in a vacuum cell of an accelerator are presented.

  19. Integrated circuits of silicon on insulator S.O.I. technologies: State of the art and perspectives

    International Nuclear Information System (INIS)

    Leray, J.L.; Dupont-Nivet, E.; Raffaelli, M.; Coic, Y.M.; Musseau, O.; Pere, J.F.; Lalande, P.; Bredy, J.; Auberton-Herve, A.J.; Bruel, M.; Giffard, B.

    1989-01-01

    Silicon On Insulator technologies have been proposed to increase the integrated circuits performances in radiation operation. Active researches are conducted, in France and abroad. This paper reviews briefly radiation effects phenomenology in that particular type of structure S.O.I. New results are presented that show very good radiation behaviour in term of speed, dose (10 to 100 megarad (Si)), dose rate and S.E.U. performances [fr

  20. Improved methods of forming monolithic integrated circuits having complementary bipolar transistors

    Science.gov (United States)

    Bohannon, R. O., Jr.; Cashion, W. F.; Stehlin, R. A.

    1971-01-01

    Two new processes form complementary transistors in monolithic semiconductor circuits, require fewer steps /infusions/ than previous methods, and eliminate such problems as nonuniform h sub FE distribution, low yield, and large device formation.

  1. Integrated Planar Lightwave Circuits for UV Generation and Phase Modulation, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — This SBIR Phase I effort proposes to establish the feasibility of developing a UV Planar Lightwave Circuit (PLC); a compact, highly efficient, waveguide-based...

  2. Inkjet-printed conductive features for rapid integration of electronic circuits in centrifugal microfluidics

    CSIR Research Space (South Africa)

    Kruger, J

    2015-05-01

    Full Text Available This work investigates the properties of conductive circuits inkjet-printed onto the polycarbonate discs used in CD-based centrifugal microfluidics, contributing towards rapidly prototyped electronic systems in smart ubiquitous biosensors, which...

  3. Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

    Science.gov (United States)

    Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

    2016-04-01

    The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

  4. A Alternative Analog Circuit Design Methodology Employing Integrated Artificial Intelligence Techniques

    Science.gov (United States)

    Tuttle, Jeffery L.

    In consideration of the computer processing power now available to the designer, an alternative analog circuit design methodology is proposed. Computer memory capacities no longer require the reduction of the transistor operational characteristics to an imprecise formulation. Therefore, it is proposed that transistor modelling be abandoned in favor of fully characterized transistor data libraries. Secondly, availability of the transistor libraries would facilitate an automated selection of the most appropriate device(s) for the circuit being designed. More specifically, a preprocessor computer program to a more sophisticated circuit simulator (e.g. SPICE) is developed to assist the designer in developing the basic circuit topology and the selection of the most appropriate transistor. Once this is achieved, the circuit topology and selected transistor data library would be downloaded to the simulator for full circuit operational characterization and subsequent design modifications. It is recognized that the design process is enhanced by the use of heuristics as applied to iterative design results. Accordingly, an artificial intelligence (AI) interface is developed to assist the designer in applying the preprocessor results. To demonstrate the retrofitability of the AI interface to established programs, the interface is specifically designed to be as non-intrusive to the host code as possible. Implementation of the proposed methodology offers the potential to speed the design process, since the preprocessor both minimizes the required number of simulator runs and provides a higher acceptance potential of the initial and subsequent simulator runs. Secondly, part count reductions may be realizable since the circuit topologies are not as strongly driven by transistor limitations. Thirdly, the predicted results should more closely match actual circuit operations since the inadequacies of the transistor models have been virtually eliminated. Finally, the AI interface

  5. A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits

    OpenAIRE

    Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio

    2010-01-01

    Abstract—Process variability and environmental fluctuations deeply affect the digital circuits performance in many different ways, one of them, the data processing time which may cause error on synchronous digital circuits due to underestimated time violations. This situation is commonly avoided adding time margins to the clock signal making it larger than nominal worstcase data process time, penalizing the global performance. In this paper a new mechanism for compensating both environm...

  6. Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

    Science.gov (United States)

    Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

    2017-05-01

    A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

  7. Analytical and experimental investigation of thermal transport in three-dimensional integrated circuits (3D ICs)

    Science.gov (United States)

    Choobineh, Leila

    Thermal management of three-dimensional integrated circuits (3D ICs) is recognized to be one of the foremost technological and research challenges currently blocking the widespread adoption of this promising technology. The computation of steady-state temperature fields in a 3D IC is critical for determining the thermal characteristics of a 3D IC and for evaluating any candidate thermal management technology. An analytical solution for the three-dimensional temperature field in a 3D IC based on solution of the governing energy equations using Fourier series expansion for steady-state temperature fields is studied. Comparison of the predicted temperature fields with finite-element simulation shows excellent agreement. The model is used to compute the temperature field in a 3D IC, and it is shown that by utilizing a thermal-friendly floorplanning approach, the maximum temperature of the 3D IC is reduced significantly. Several 3D IC manufacturing and packaging approaches require adjacent die sizes to be different from one another since this enables differentiated manufacturing and design. However, it is expected that unequally-sized die may cause deteriorated thermal performance due to heat spreading and constriction. Heat transfer model for predicting the three-dimensional temperature field in a multi-die 3D IC with unequally-sized die is studied. The model is used to compare the thermal performance of unequally-sized die stacks with a uniformly-sized die stack. Results indicate that the greater the degree of non-uniformity in the die stack, the greater in the peak temperature rise. An analytical modeling of heat transfer in interposer-based microelectronic systems is described. The analytical model is developed to study the effect of various parameters on the temperature field in an interposer system. A non-iterative, analytical heat transfer model for computing three-dimensional temperature fields in a 3D IC has been proposed. The governing energy equations with

  8. Quantum circuit dynamics via path integrals: Is there a classical action for discrete-time paths?

    Science.gov (United States)

    Penney, Mark D.; Enshan Koh, Dax; Spekkens, Robert W.

    2017-07-01

    It is straightforward to compute the transition amplitudes of a quantum circuit using the sum-over-paths methodology when the gates in the circuit are balanced, where a balanced gate is one for which all non-zero transition amplitudes are of equal magnitude. Here we consider the question of whether, for such circuits, the relative phases of different discrete-time paths through the configuration space can be defined in terms of a classical action, as they are for continuous-time paths. We show how to do so for certain kinds of quantum circuits, namely, Clifford circuits where the elementary systems are continuous-variable systems or discrete systems of odd-prime dimension. These types of circuit are distinguished by having phase-space representations that serve to define their classical counterparts. For discrete systems, the phase-space coordinates are also discrete variables. We show that for each gate in the generating set, one can associate a symplectomorphism on the phase-space and to each of these one can associate a generating function, defined on two copies of the configuration space. For discrete systems, the latter association is achieved using tools from algebraic geometry. Finally, we show that if the action functional for a discrete-time path through a sequence of gates is defined using the sum of the corresponding generating functions, then it yields the correct relative phases for the path-sum expression. These results are likely to be relevant for quantizing physical theories where time is fundamentally discrete, characterizing the classical limit of discrete-time quantum dynamics, and proving complexity results for quantum circuits.

  9. Electronic meter with custom integrated circuit for electric energy measurement; Medidor eletronico de energia eletrica com circuito integrado dedicado

    Energy Technology Data Exchange (ETDEWEB)

    Caldas, Roberto Pereira

    1990-04-01

    The design and implementation of an electrical energy electronic meter for operation at low voltages, according to two steps of development carried out in Centro de Pesquisas de Energia Eletrica - CEPEL is described. In the first step, an electronic meter with discrete commercial components has been developed, in order to demonstrate to the Brazilian power suppliers the feasibility of such a device for electrical energy metering and charging. The second step was constituted by the design of an integrated circuit, aiming the reduction of the cost of the meter as well as the enhancement of its reliability. Several techniques of electrical energy measurement are presented. The meter with discrete components makes use of a time division multiplier (TDM), in order to determine the active power in the load. Voltage and current levels have been reduced through the use of voltage and current sensors compatible with the TDM's inputs. A V-F converter employing continuos integration, has been used for the determination of the energy consumed by the load through the integration of the TDM's output signal. Most of the discrete components of the meter have been replaced by the dedicated integrated circuit. The TDM has remained essentially the same, but the V-F converter has been changed into a dual-slope one, which is more adequate for implementation in a single chip. The tests performed with the prototypes of the meter including both the meter with discrete components and the meter with the custom-made integrated circuit have presented measurement errors of less the 0,2 %. The initial goal, according to Brazilian specifications of electromechanical meters and international specifications for electronic meters, was 1 %. (author)

  10. Solid-state circuits

    CERN Document Server

    Pridham, G J

    2013-01-01

    Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

  11. An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

    Science.gov (United States)

    Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

    2017-07-01

    This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

  12. An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

    Science.gov (United States)

    D'Addario, Larry R.; Wang, Douglas

    2016-01-01

    Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlationare proportional to N2 and dominate at sufficiently large N. Here we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope's bandwidth (the so-called "FX" structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with 2 opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chipmemory and the CMACs are re-used as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the IC's size and power consumption. It isintended for fabrication in a 32 nm silicon-on-insulator process, where it will require less than 12mm2 of silicon area and achieve an energy efficiency of 1.76 to 3.3 pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to N = 4096. The system-level energy efficiency, including board-levelI/O, power supplies, and controls, is expected to be 5 to 7 pJ per CMAC operation. Existing correlators for the JVLA (N = 32) and ALMA (N = 64) telescopes achieve about 5000 pJ and 1000 pJ respectively usingapplication-specific ICs in older technologies. To our knowledge, the largest-N existing correlator is LEDA atN = 256; it

  13. Thermoacoustic and thermoreflectance imaging of biased integrated circuits: Voltage and temperature maps

    Energy Technology Data Exchange (ETDEWEB)

    Hernández-Rosales, E.; Cedeño, E. [Gleb Wataghin Physics Institute, University of Campinas - Unicamp, 13083-859 Campinas, SP (Brazil); Instituto Politécnico Nacional, Centro de Investigación en Ciencia Aplicada y Tecnología Avanzada, Legaria 694, Colonia Irrigación, CP 11500, México, DF (Mexico); Hernandez-Wong, J. [Instituto Politécnico Nacional, Centro de Investigación en Ciencia Aplicada y Tecnología Avanzada, Legaria 694, Colonia Irrigación, CP 11500, México, DF (Mexico); CONACYT, México, DF, México (Mexico); Rojas-Trigos, J. B.; Marin, E. [Instituto Politécnico Nacional, Centro de Investigación en Ciencia Aplicada y Tecnología Avanzada, Legaria 694, Colonia Irrigación, CP 11500, México, DF (Mexico); Gandra, F. C. G.; Mansanares, A. M., E-mail: manoel@ifi.unicamp.br [Gleb Wataghin Physics Institute, University of Campinas - Unicamp, 13083-859 Campinas, SP (Brazil)

    2016-07-25

    In this work a combined thermoacoustic and thermoreflectance set-up was designed for imaging biased microelectronic circuits. In particular, it was used with polycrystalline silicon resistive tracks grown on a monocrystalline Si substrate mounted on a test chip. Thermoreflectance images, obtained by scanning a probe laser beam on the sample surface, clearly show the regions periodically heated by Joule effect, which are associated to the electric current distribution in the circuit. The thermoacoustic signal, detected by a pyroelectric/piezoelectric sensor beneath the chip, also discloses the Joule contribution of the whole sample. However, additional information emerges when a non-modulated laser beam is focused on the sample surface in a raster scan mode allowing imaging of the sample. The distribution of this supplementary signal is related to the voltage distribution along the circuit.

  14. The Systematic Integration of Very Large Scale Integrated Circuit Computer-Aided Design Tools into a Toolkit Optimized for Academic Applications.

    Science.gov (United States)

    1984-12-01

    line (DIP) IC package. 1965: Robert Widlar, a designer with Fairchild, develops the first practical integrated circuit operational amplifier ( opamp ...the uA709. Widlar also designed the uA702, uA710, and the uA741 11-2 .*~~~~ .* . . . . . . . .. .* . . . ... . . . . - opamps . 1966: Autonetics...There was resistance to the implementa- tion of automated design aids [17,40]. The reluctance to use CAD programs was partly due to numerous software fail

  15. In vitro evaluation of gaseous microemboli handling of cardiopulmonary bypass circuits with and without integrated arterial line filters.

    Science.gov (United States)

    Liu, Saifei; Newland, Richard F; Tully, Phillip J; Tuble, Sigrid C; Baker, Robert A

    2011-09-01

    The delivery of gaseous microemboli (GME) by the cardiopulmonary bypass circuit should be minimized whenever possible. Innovations in components, such as the integration of arterial line filter (ALF) and ALFs with reduced priming volumes, have provided clinicians with circuit design options. However, before adopting these components clinically, their GME handling ability should be assessed. This study aims to compare the GME handling ability of different oxygenator/ALF combinations with our currently utilized combination. Five commercially available oxygenator/ALF combinations were evaluated in vitro: Terumo Capiox SX25RX and Dideco D734 (SX/D734),Terumo Capiox RX25R and AF125 (RX/AF125), Terumo FX25R (FX), Sorin Synthesis with 102 microm reservoir filter (SYN102), and Sorin Synthesis with 40 microm reservoir filter (SYN40). GME handling was studied by introducing air into the venous return at 100 mL/min for 60 seconds under two flow/ pressure combinations: 3.5 L/min, 150 mmHg and 5 L/min, 200 mmHg. Emboli were measured at three positions in the circuit using the Emboli Detection and Classification (EDAC) Quantifier and analyzed with the General Linear Model. All circuits significantly reduced GME. The SX/D734 and SYN40 circuits were most efficient in GME removal whilst the SYN102 handled embolic load (count and volume) least efficiently (p handle GME. Venous reservoir design influenced the overall GME handling ability. GME removal was less efficient at higher flow and pressure, and for smaller sized emboli. The clinical significance of reducing GME requires further investigation.

  16. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    Energy Technology Data Exchange (ETDEWEB)

    Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu [Department of Materials Science and Engineering, Beckman Institute for Advanced Science and Technology, and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 S Goodwin Ave., Urbana, Illinois 61801 (United States); Bozler, Carl [Lincoln Laboratory, Massachusetts Institute of Technology, 244 Wood Street, Lexington, Massachusetts 02420 (United States); Omenetto, Fiorenzo [Department of Biomedical Engineering, Department of Physics, Tufts University, 4 Colby St., Medford, Massachusetts 02155 (United States)

    2015-01-05

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  17. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    International Nuclear Information System (INIS)

    Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

    2015-01-01

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems

  18. The Piezojunction Effect in Silicon. Consequences and Applications for Integrated Circuits and Sensors

    NARCIS (Netherlands)

    Fruett, F.

    2001-01-01

    This thesis describes an investigation of the piezojunction effect in silicon. The aim of this investigation is twofold. First, to propose some techniques to reduce the mechanical-stress-induced inaccuracy and long-term instability of many analogue circuits such as bandgap references and monolithic

  19. Development of integrated photoplethysmographic recording circuit for trans-nail pulse-wave monitoring system

    Science.gov (United States)

    Qian, Zhengyang; Takezawa, Yoshiki; Shimokawa, Kenji; Kino, Hisashi; Fukushima, Takafumi; Kiyoyama, Koji; Tanaka, Tetsu

    2018-04-01

    Health monitoring and self-management have become increasingly more important because of health awareness improvement, the aging of population, and other reasons. In general, pulse waves are among the most useful physiological signals that can be used to calculate several parameters such as heart rate and blood pressure for health monitoring and self-management. To realize an automatic and real-time pulse-wave monitoring system that can be used in daily life, we have proposed a trans-nail pulse-wave monitoring system that was placed on the fingernail to detect photoplethysmographic (PPG) signals as pulse waves. In this study, we designed a PPG recording circuit that was composed of a 600 × 600 µm2 photodiode (PD), an LED driver with pulse wave modulation (PWM) and a low-frequency ring oscillator (RING), and a PPG signal readout circuit. The proposed circuit had a very small area of 2.2 × 1.1 mm2 designed with 0.18 µm CMOS technology. The proposed circuit was used to detect pulse waves on the human fingernail in both the reflection and transmission modes. Electrical characteristics of the prototype system were evaluated precisely and PPG waveforms were obtained successfully.

  20. Analog Integrated Circuit and System Design for a Compact, Low-Power Cochlear Implant

    NARCIS (Netherlands)

    Ngamkham, W.

    2015-01-01

    Cochlear Implants (CIs) are prosthetic devices that restore hearing in profoundly deaf patients by bypassing the damaged parts of the inner ear and directly stimulating the remaining auditory nerve fibers in the cochlea with electrical pulses. This thesis describs the electronic circuit design of

  1. Monolithically Integrated Light Feedback Control Circuit for Blue/UV LED Smart Package

    NARCIS (Netherlands)

    Koladouz Esfahani, Z.; Tohidian, M.; van Zeijl, H.W.; Kolahdouz, Mohammadreza; Zhang, G.Q.

    2017-01-01

    Given the performance decay of high-power light-emitting diode (LED) chips over time and package condition changes, having a reliable output light for sensitive applications is a point of concern. In this study, a light feedback control circuit, including blue-selective photodiodes, for

  2. Characterization of a fabrication process for the integration of superconducting qubits and rapid-single-flux-quantum circuits

    International Nuclear Information System (INIS)

    Castellano, Maria Gabriella; Groenberg, Leif; Carelli, Pasquale; Chiarello, Fabio; Cosmelli, Carlo; Leoni, Roberto; Poletto, Stefano; Torrioli, Guido; Hassel, Juha; Helistoe, Panu

    2006-01-01

    In order to integrate superconducting qubits with rapid-single-flux-quantum (RSFQ) control circuitry, it is necessary to develop a fabrication process that simultaneously fulfils the requirements of both elements: low critical current density, very low operating temperature (tens of millikelvin) and reduced dissipation on the qubit side; high operation frequency, large stability margins, low dissipated power on the RSFQ side. For this purpose, VTT has developed a fabrication process based on Nb trilayer technology, which allows the on-chip integration of superconducting qubits and RSFQ circuits even at very low temperature. Here we present the characterization (at 4.2 K) of the process from the point of view of the Josephson devices and show that they are suitable to build integrated superconducting qubits

  3. Use of Tunable Whole-Cell Bioreporters to Assess Bioavailable Cadmium and Remediation Performance in Soils.

    Directory of Open Access Journals (Sweden)

    Youngdae Yoon

    Full Text Available It is important to have tools to measure the bioavailability to assess the risks of pollutants because the bioavailability is defined as the portions of pollutants showing the biological effects on living organisms. This study described the construction of tunable Escherichia coli whole-cell bioreporter (WCB using the promoter region of zinc-inducible operon and its application on contaminated soils. It was verified that this WCB system showed specific and sensitive responses to cadmium rather than zinc in the experimental conditions. It was inferred that Cd(II associates stronger with ZntR, a regulatory protein of zinc-inducible operon, than other metal ions. Moreover, the expression of reporter genes, egfp and mcherry, were proportional to the concentration of cadmium, thereby being a quantitative sensor to monitor bioavailable cadmium. The capability to determine bioavailable cadmium was verified with Cd(II amended LUFA soils, and then the applicability on environmental systems was investigated with field soils collected from smelter area in Korea before and after soil-washing. The total amount of cadmium was decreased after soil washing, while the bioavailability was increased. Consequently, it would be valuable to have tools to assess bioavailability and the effectiveness of soil remediation should be evaluated in the aspect of bioavailability as well as removal efficiency.

  4. Use of Tunable Whole-Cell Bioreporters to Assess Bioavailable Cadmium and Remediation Performance in Soils

    Science.gov (United States)

    Yoon, Youngdae; Kim, Sunghoon; Chae, Yooeun; Kang, Yerin; Lee, Youngshim; Jeong, Seung-Woo; An, Youn-Joo

    2016-01-01

    It is important to have tools to measure the bioavailability to assess the risks of pollutants because the bioavailability is defined as the portions of pollutants showing the biological effects on living organisms. This study described the construction of tunable Escherichia coli whole-cell bioreporter (WCB) using the promoter region of zinc-inducible operon and its application on contaminated soils. It was verified that this WCB system showed specific and sensitive responses to cadmium rather than zinc in the experimental conditions. It was inferred that Cd(II) associates stronger with ZntR, a regulatory protein of zinc-inducible operon, than other metal ions. Moreover, the expression of reporter genes, egfp and mcherry, were proportional to the concentration of cadmium, thereby being a quantitative sensor to monitor bioavailable cadmium. The capability to determine bioavailable cadmium was verified with Cd(II) amended LUFA soils, and then the applicability on environmental systems was investigated with field soils collected from smelter area in Korea before and after soil-washing. The total amount of cadmium was decreased after soil washing, while the bioavailability was increased. Consequently, it would be valuable to have tools to assess bioavailability and the effectiveness of soil remediation should be evaluated in the aspect of bioavailability as well as removal efficiency. PMID:27171374

  5. High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

    Science.gov (United States)

    Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

    2017-04-25

    Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

  6. Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom

    Directory of Open Access Journals (Sweden)

    Hang Song

    2017-01-01

    Full Text Available A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

  7. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    Science.gov (United States)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  8. High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes

    Science.gov (United States)

    Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

    2017-09-01

    As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

  9. Report on application specific integrated circuits for relativistic heavy ion detectors

    International Nuclear Information System (INIS)

    Platner, E.D.

    1988-01-01

    Detector systems for RHIC experiments are invariably going to be large and complex. Thus it behooves the planners to incorporate elements that have little need for adjustment, calibration and correction to the produced data. For example, if power, size and cost considerations permit, time can be digitized directly (i.e. with counters, shift registers, etc.) where no adjustments, calibrations or corrections are required. The circuit either works correctly or not at all. This kind of circuit behavior is extremely valuable in detectors with 10 5 or more channel elements. In analog to digital conversion applications, direct conversion (i.e. flash ADC) may be prohibitive in cost, size and power. Here major effort must be given to minimize the magnitude of offset and conversion gain variance. Where possible self correction and adjustment should be applied at the subsystem level

  10. Integrated circuits and molecular components for stress and feeding: implications for eating disorders.

    Science.gov (United States)

    Hardaway, J A; Crowley, N A; Bulik, C M; Kash, T L

    2015-01-01

    Eating disorders are complex brain disorders that afflict millions of individuals worldwide. The etiology of these diseases is not fully understood, but a growing body of literature suggests that stress and anxiety may play a critical role in their development. As our understanding of the genetic and environmental factors that contribute to disease in clinical populations like anorexia nervosa, bulimia nervosa and binge eating disorder continue to grow, neuroscientists are using animal models to understand the neurobiology of stress and feeding. We hypothesize that eating disorder clinical phenotypes may result from stress-induced maladaptive alterations in neural circuits that regulate feeding, and that these circuits can be neurochemically isolated using animal model of eating disorders. © 2014 John Wiley & Sons Ltd and International Behavioural and Neural Genetics Society.

  11. Design of CMOS analog integrated fractional-order circuits applications in medicine and biology

    CERN Document Server

    Tsirimokou, Georgia; Elwakil, Ahmed

    2017-01-01

    This book describes the design and realization of analog fractional-order circuits, which are suitable for on-chip implementation, capable of low-voltage operation and electronic adjustment of their characteristics. The authors provide a brief introduction to fractional-order calculus, followed by design issues for fractional-order circuits of various orders and types. The benefits of this approach are demonstrated with current-mode and voltage-mode filter designs. Electronically tunable emulators of fractional-order capacitors and inductors are presented, where the behavior of the corresponding chips fabricated using the AMS 0.35um CMOS process has been experimentally verified. Applications of fractional-order circuits are demonstrated, including a pre-processing stage suitable for the implementation of the Pan-Tompkins algorithm for detecting the QRS complexes of an electrocardiogram (ECG), a fully tunable implementation of the Cole-Cole model used for the modeling of biological tissues, and a simple, non-i...

  12. External circuit integration with electromagnetic particle in cell modeling of plasma focus devices

    International Nuclear Information System (INIS)

    Seng, Y. S.; Lee, P.; Rawat, R. S.

    2015-01-01

    The pinch performance of a plasma focus (PF) device is sensitive to the physical conditions of the breakdown phase. It is therefore essential to model and study the initial phase in order to optimize device performance. An external circuit is self consistently coupled to the electromagnetic particle in cell code to model the breakdown and initial lift phase of the United Nations University/International Centre for Theoretical Physics (UNU-ICTP) plasma focus device. Gas breakdown during the breakdown phase is simulated successfully, following a drop in the applied voltage across the device and a concurrent substantial rise in the circuit current. As a result, the plasma becomes magnetized, with the growing value of the magnetic field over time leading to the gradual lift off of the well formed current sheath into the axial acceleration phase. This lifting off, with simultaneous outward sheath motion along the anode and vertical cathode, and the strong magnetic fields in the current sheath region, was demonstrated in this work, and hence validates our method of coupling the external circuit to PF devices. Our method produces voltage waveforms that are qualitatively similar to the observed experimental voltage profiles of the UNU-ICTP device. Values of the mean electron energy before and after voltage breakdown turned out to be different, with the values after breakdown being much lower. In both cases, the electron energy density function turned out to be non-Maxwellian

  13. Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

    Science.gov (United States)

    Dell'Erba, Giorgio; Luzio, Alessandro; Natali, Dario; Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu; Noh, Yong-Young; Caironi, Mario

    2014-04-01

    Ambipolar semiconducting polymers, characterized by both high electron (μe) and hole (μh) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μh = 0.29 cm2/V s and μe = 0.001 cm2/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μe = 0.12 cm2/V s and μh = 8 × 10-4 cm2/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

  14. White matter tract integrity of frontostriatal circuit in attention deficit hyperactivity disorder: association with attention performance and symptoms.

    Science.gov (United States)

    Wu, Yi-Huan; Gau, Susan Shur-Fen; Lo, Yu-Chun; Tseng, Wen-Yih Isaac

    2014-01-01

    The frontostriatal circuit has been postulated to account for the core symptoms such as inattention in attention deficit/hyperactivity disorder (ADHD). This study investigated the white matter integrity of frontostriatal fiber tracts using diffusion spectrum imaging (DSI) tractography and its correlations with measures of multi-dimensional aspects of inattention based on psychiatric interview and attention tasks in 25 children with ADHD and 25 matched typically developing (TD) children. All the subjects were assessed with comprehensive psychiatric interviews and the Conner's Continuous Performance Test (CCPT). DSI data were acquired on a 3-Tesla MRI system. The frontostriatal fiber pathways were reconstructed by deterministic tractography, and generalized fractional anisotropy values were measured along individual targeted tracts to investigate alterations in microstructure integrity. Children with ADHD performed worse than TD children in the dimensions of focused attention, sustained attention, impulsivity, and vigilance of the CCPT, and showed impaired integrity in four bilateral frontostriatal tracts, namely the dorsolateral-caudate, medial prefrontal-caudate, orbitofrontal-caudate, and ventrolateral-caudate tracts, and in global white matter as well. The integrity of the left orbitofronto-caudate tract was associated with the symptom of inattention in children with ADHD, compatible with the attention deficit and motivational dysfunction theories in ADHD. The integrity of the frontostriatal tracts was associated with the attention performance only in TD children, suggestive of possible recruitment of tracts other than the frontostriatal tracts implicated in attention deficits in children with ADHD. In conclusion, our results demonstrate the functional involvement of the frontostriatal circuit with respect to clinical symptoms and attention performance. Copyright © 2012 Wiley Periodicals, Inc.

  15. Electronic devices and circuits

    CERN Document Server

    Pridham, Gordon John

    1972-01-01

    Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of

  16. Photonic integrated circuit implementation of a sub-GHz-selectivity frequency comb filter for optical clock multiplication.

    Science.gov (United States)

    Geng, Zihan; Xie, Yiwei; Zhuang, Leimeng; Burla, Maurizio; Hoekman, Marcel; Roeloffzen, Chris G H; Lowery, Arthur J

    2017-10-30

    We report a photonic integrated circuit implementation of an optical clock multiplier, or equivalently an optical frequency comb filter. The circuit comprises a novel topology of a ring-resonator-assisted asymmetrical Mach-Zehnder interferometer in a Sagnac loop, providing a reconfigurable comb filter with sub-GHz selectivity and low complexity. A proof-of-concept device is fabricated in a high-index-contrast stoichiometric silicon nitride (Si 3 N 4 /SiO 2 ) waveguide, featuring low loss, small size, and large bandwidth. In the experiment, we show a very narrow passband for filters of this kind, i.e. a -3-dB bandwidth of 0.6 GHz and a -20-dB passband of 1.2 GHz at a frequency interval of 12.5 GHz. As an application example, this particular filter shape enables successful demonstrations of five-fold repetition rate multiplication of optical clock signals, i.e. from 2.5 Gpulses/s to 12.5 Gpulses/s and from 10 Gpulses/s to 50 Gpulses/s. This work addresses comb spectrum processing on an integrated platform, pointing towards a device-compact solution for optical clock multipliers (frequency comb filters) which have diverse applications ranging from photonic-based RF spectrum scanners and photonic radars to GHz-granularity WDM switches and LIDARs.

  17. Writing of 3D optical integrated circuits with ultrashort laser pulses in the presence of strong spherical aberration

    Science.gov (United States)

    Bukharin, M. A.; Skryabin, N. N.; Khudyakov, D. V.; Vartapetov, S. K.

    2016-09-01

    A novel technique was proposed for 3D femtosecond writing of waveguides and optical integrated circuits in the presence of strong spherical aberration, caused by inscription at significantly different depth under the surface of optical glasses and crystals. Strong negative effect of spherical aberration and related asymmetry of created structures was reduced due to transition to the cumulative thermal regime of femtosecond interaction with the material. The differences in the influence of spherical aberration effect in a broad depth range (larger than 200 µm) was compensated by dynamic adjustment of laser pulse energy during the process of waveguides recording. The presented approach has been experimentally implemented in fused silica. Obtained results can be used in production of a broad class of femtosecond written three-dimensional integrated optical systems, inscripted at non-optimal (for focusing lens) optical depth or in significantly extended range of depths.

  18. Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

    Energy Technology Data Exchange (ETDEWEB)

    Dell' Erba, Giorgio; Natali, Dario [Center for Nano Science and Technology PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano (Italy); Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza L. da Vinci 32, 20133 Milano (Italy); Luzio, Alessandro; Caironi, Mario, E-mail: mario.caironi@iit.it, E-mail: yynoh@dongguk.edu [Center for Nano Science and Technology PoliMi, Istituto Italiano di Tecnologia, Via Pascoli 70/3, 20133 Milano (Italy); Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu [Heeger Center for Advanced Materials, School of Materials Science and Engineering, Gwangju Institute of Science and Technology (GIST), 261 Cheomdan-gwagiro, Buk-gu, Gwangju 500-712 (Korea, Republic of); Noh, Yong-Young, E-mail: mario.caironi@iit.it, E-mail: yynoh@dongguk.edu [Department of Energy and Materials Engineering, Dongguk University, 26 Pil-dong, 3-ga, Jung-gu, Seoul 100-715 (Korea, Republic of)

    2014-04-14

    Ambipolar semiconducting polymers, characterized by both high electron (μ{sub e}) and hole (μ{sub h}) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μ{sub h} = 0.29 cm{sup 2}/V s and μ{sub e} = 0.001 cm{sup 2}/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μ{sub e} = 0.12 cm{sup 2}/V s and μ{sub h} = 8 × 10{sup −4} cm{sup 2}/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

  19. Radiation effects and soft errors in integrated circuits and electronic devices

    CERN Document Server

    Fleetwood, D M

    2004-01-01

    This book provides a detailed treatment of radiation effects in electronic devices, including effects at the material, device, and circuit levels. The emphasis is on transient effects caused by single ionizing particles (single-event effects and soft errors) and effects produced by the cumulative energy deposited by the radiation (total ionizing dose effects). Bipolar (Si and SiGe), metal-oxide-semiconductor (MOS), and compound semiconductor technologies are discussed. In addition to considering the specific issues associated with high-performance devices and technologies, the book includes th

  20. WOCSDICE 94 - European Workshop on Compound Semiconductor Devices and Integrated Circuits (18th) Held in Kinsale, Ireland on 29 May-1 June 1994

    Science.gov (United States)

    1994-06-01

    Taskert, M. Demmiler, J. Braunsteint, B. Hughes* and E. SAnchez Dpto. Tecnologfas de las Comunicaciones , Universidad de Vigo, E-36200 Vigo, Spain. Phone...by large scale integration for digital applications. About one million _MESFETs are now interazed on the most complex Ga•A-s digtal circuits. Even...single chip receivers in the millimtree wave fr-equency range. The pseudomorphic iE-M1vfT devices are also investigated for digital circuits with gate

  1. Implementation of integrated circuit and design of SAR ADC for fully implantable hearing aids.

    Science.gov (United States)

    Kim, Jong Hoon; Lee, Jyung Hyun; Cho, Jin-Ho

    2017-07-20

    The hearing impaired population has been increasing; many people suffer from hearing problems. To deal with this difficulty, various types of hearing aids are being rapidly developed. In particular, fully implantable hearing aids are being actively studied to improve the performance of existing hearing aids and to reduce the stigma of hearing loss patients. It has to be of small size and low-power consumption for easy implantation and long-term use. The objective of the study was to implement a small size and low-power consumption successive approximation register analog-to-digital converter (SAR ADC) for fully implantable hearing aids. The ADC was selected as the SAR ADC because its analog circuit components are less required by the feedback circuit of the SAR ADC than the sigma-delta ADC which is conventionally used in hearing aids, and it has advantages in the area and power consumption. So, the circuit of SAR ADC is designed considering the speech region of humans because the objective is to deliver the speech signals of humans to hearing loss patients. If the switch of sample and hold works in the on/off positions, the charge injection and clock feedthrough are produced by a parasitic capacitor. These problems affect the linearity of the hold voltage, and as a result, an error of the bit conversion is generated. In order to solve the problem, a CMOS switch that consists of NMOS and PMOS was used, and it reduces the charge injection because the charge carriers in the NMOS and PMOS have inversed polarity. So, 16 bit conversion is performed before the occurrence of the Least Significant Bit (LSB) error. In order to minimize the offset voltage and power consumption of the designed comparator, we designed a preamplifier with current mirror. Therefore, the power consumption was reduced by the power control switch used in the comparator. The layout of the designed SAR ADC was performed by Virtuoso Layout Editor (Cadence, USA). In the layout result, the size of the

  2. Hardware security and trust design and deployment of integrated circuits in a threatened environment

    CERN Document Server

    Chaves, Ricardo; Natale, Giorgio; Regazzoni, Francesco

    2017-01-01

    This book provides a comprehensive introduction to hardware security, from specification to implementation. Applications discussed include embedded systems ranging from small RFID tags to satellites orbiting the earth. The authors describe a design and synthesis flow, which will transform a given circuit into a secure design incorporating counter-measures against fault attacks. In order to address the conflict between testability and security, the authors describe innovative design-for-testability (DFT) computer-aided design (CAD) tools that support security challenges, engineered for compliance with existing, commercial tools. Secure protocols are discussed, which protect access to necessary test infrastructures and enable the design of secure access controllers. Covers all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization; Describes new methods and algorithms for the identification/detection of hardware trojans; Defines new architectures capable o...

  3. Analog integrated circuit design automation placement, routing and parasitic extraction techniques

    CERN Document Server

    Martins, Ricardo; Horta, Nuno

    2017-01-01

    This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures...

  4. Design and Test of Application-Specific Integrated Circuits by use of Mobile Clients

    Directory of Open Access Journals (Sweden)

    Michael Auer

    2009-02-01

    Full Text Available The aim of this work is to develop a simultaneous multi user access system – READ (Remote ASIC Design and Test that allows users to perform test and measurements remotely via clients running on mobile devices as well as on standard PCs. The system also facilitates the remote design of circuits with the PAC-Designer The system is controlled by LabVIEW and was implemented using a Data Acquisition Card from National instruments. Such systems are specially suited for manufacturing process monitoring and control. The performance of the simultaneous access was tested under load with a variable number of users. The server implements a queue that processes user’s commands upon request.

  5. Integration of MHD load models with circuit representations the Z generator.

    Energy Technology Data Exchange (ETDEWEB)

    Jennings, Christopher A.; Ampleford, David J.; Jones, Brent Manley; McBride, Ryan D.; Bailey, James E.; Jones, Michael C.; Gomez, Matthew Robert.; Cuneo, Michael Edward; Nakhleh, Charles; Stygar, William A.; Savage, Mark Edward; Wagoner, Timothy C.; Moore, James K.

    2013-03-01

    MHD models of imploding loads fielded on the Z accelerator are typically driven by reduced or simplified circuit representations of the generator. The performance of many of the imploding loads is critically dependent on the current and power delivered to them, so may be strongly influenced by the generators response to their implosion. Current losses diagnosed in the transmission lines approaching the load are further known to limit the energy delivery, while exhibiting some load dependence. Through comparing the convolute performance of a wide variety of short pulse Z loads we parameterize a convolute loss resistance applicable between different experiments. We incorporate this, and other current loss terms into a transmission line representation of the Z vacuum section. We then apply this model to study the current delivery to a wide variety of wire array and MagLif style liner loads.

  6. Use of bioreporters and deletion mutants reveals ionic silver and ROS to be equally important in silver nanotoxicity.

    Science.gov (United States)

    Joshi, Nimisha; Ngwenya, Bryne T; Butler, Ian B; French, Chris E

    2015-04-28

    The mechanism of antibacterial action of silver nanoparticles (AgNp) was investigated by employing a combination of microbiology and geochemical approaches to contribute to the realistic assessment of nanotoxicity. Our studies showed that suspending AgNp in media with different levels of chloride relevant to environmental conditions produced low levels of ionic silver thereby suggesting that dissolution of silver ions from nanoparticulate surface could not be the sole mechanism of toxicity. An Escherichia coli based bioreporter strain responsive to silver ions together with mutant strains of E. coli lacking specific protective systems were tested against AgNp. Deletion mutants lacking silver ion efflux systems and resistance mechanisms against oxidative stress showed an increased sensitivity to AgNp. However, the bioreporter did not respond to silver nanoparticles. Our results suggest that oxidative stress is a major toxicity mechanism and that this is at least partially associated with ionic silver, but that bulk dissolution of silver into the medium is not sufficient to account for the observed effects. Chloride ions do not appear to offer significant protection, indicating that chloride in receiving waters will not necessarily protect environmental bacteria from the toxic effects of nanoparticles in effluents. Copyright © 2015 Elsevier B.V. All rights reserved.

  7. Electro pneumatic trainer embedded with programmable integrated circuit (PIC) microcontroller and graphical user interface platform for aviation industries training purposes

    Science.gov (United States)

    Burhan, I.; Azman, A. A.; Othman, R.

    2016-10-01

    An electro pneumatic trainer embedded with programmable integrated circuit (PIC) microcontroller and Visual Basic (VB) platform is fabricated as a supporting tool to existing teaching and learning process, and to achieve the objectives and learning outcomes towards enhancing the student's knowledge and hands-on skill, especially in electro pneumatic devices. The existing learning process for electro pneumatic courses conducted in the classroom does not emphasize on simulation and complex practical aspects. VB is used as the platform for graphical user interface (GUI) while PIC as the interface circuit between the GUI and hardware of electro pneumatic apparatus. Fabrication of electro pneumatic trainer interfacing between PIC and VB has been designed and improved by involving multiple types of electro pneumatic apparatus such as linear drive, air motor, semi rotary motor, double acting cylinder and single acting cylinder. Newly fabricated electro pneumatic trainer microcontroller interface can be programmed and re-programmed for numerous combination of tasks. Based on the survey to 175 student participants, 97% of the respondents agreed that the newly fabricated trainer is user friendly, safe and attractive, and 96.8% of the respondents strongly agreed that there is improvement in knowledge development and also hands-on skill in their learning process. Furthermore, the Lab Practical Evaluation record has indicated that the respondents have improved their academic performance (hands-on skills) by an average of 23.5%.

  8. Integrated Planar Lightwave Circuits for UV Generation and Phase Modulation Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The primary goal of this SBIR effort is delivery of a compact, robust, highly efficient, fiber-coupled UV module to provide the required 355nm light for integration...

  9. Object Oriented Programmable Integrated Circuit (OOPic) Upgrade and Evaluation for Autonomous Ground Vehicle (AGV)

    National Research Council Canada - National Science Library

    Hoffman, Andrew J

    2006-01-01

    ...). Sensors with the OOPic, and the XBee Wireless Suite were included in the integration. Tests were conducted, including range and time operation analysis for wireless communications for comparison with the legacy BL2000 microcontroller...

  10. Waveguide Phase Modulator for Integrated Planar Lightwave Circuits in KTP Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This SBIR Phase I effort proposes the development of a potassium titanyl phosphate (KTP) waveguide phase modulator for future integration into a Planar Lightwave...

  11. Terahertz imaging technique and application in large scale integrated circuit failure inspection

    Science.gov (United States)

    Di, Zhi-gang; Yao, Jian-quan; Jia, Chun-rong; Xu, De-gang; Bing, Pi-bin; Yang, Peng-fei; Zheng, Yi-bo

    2010-11-01

    Terahertz ray, as a new style optic source, usually means the electromagnetic whose frequencies lies in between 0.1THz~10THz, the waveband region of the electromagnetic spectrum lies in the gap between microwaves and infrared ray. With the development of laser techniques, quantum trap techniques and compound semiconductor techniques, many new terahertz techniques have been pioneered, motivated in part by the vast range of possible applications for terahertz imaging, sensing, and spectroscopy. THz imaging technique was introduced, and THz imaging can give us not only the density picture but also the phase information within frequency domain. Consequently, images of suspicious objects such as concealed metallic or metal weapons are much sharper and more readily identified when imaged with THz imaging scanners. On the base of these, the application of THz imaging in nondestructive examination, more concretely in large scale circuit failure inspection was illuminated, and the important techniques of this application were introduced, also future prospects were discussed. With the development of correlative technology of THz, we can draw a conclusion that THz imaging technology will have nice application foreground.

  12. Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.

    Science.gov (United States)

    Jeong, Gyu-Seob; Bae, Woorham; Jeong, Deog-Kyoon

    2017-08-25

    The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

  13. The Unification of Space Qualified Integrated Circuits by Example of International Space Project GAMMA-400

    Science.gov (United States)

    Bobkov, S. G.; Serdin, O. V.; Arkhangelskiy, A. I.; Arkhangelskaja, I. V.; Suchkov, S. I.; Topchiev, N. P.

    The problem of electronic component unification at the different levels (circuits, interfaces, hardware and software) used in space industry is considered. The task of computer systems for space purposes developing is discussed by example of scientific data acquisition system for space project GAMMA-400. The basic characteristics of high reliable and fault tolerant chips developed by SRISA RAS for space applicable computational systems are given. To reduce power consumption and enhance data reliability, embedded system interconnect made hierarchical: upper level is Serial RapidIO 1x or 4x with rate transfer 1.25 Gbaud; next level - SpaceWire with rate transfer up to 400 Mbaud and lower level - MIL-STD-1553B and RS232/RS485. The Ethernet 10/100 is technology interface and provided connection with the previously released modules too. Systems interconnection allows creating different redundancy systems. Designers can develop heterogeneous systems that employ the peer-to-peer networking performance of Serial RapidIO using multiprocessor clusters interconnected by SpaceWire.

  14. Ultra-broadband Nonlinear Microwave Monolithic Integrated Circuits in SiGe, GaAs and InP

    DEFF Research Database (Denmark)

    Krozer, Viktor; Johansen, Tom Keinicke; Djurhuus, Torsten

    2006-01-01

    Analog MMIC circuits with ultra-wideband operation are discussed in view of their frequency limitation and different circuit topologies. Results for designed and fabricated frequency converters in SiGe, GaAs, and InP technologies are presented in the paper. RF type circuit topologies exhibit a flat...

  15. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience; Conception et test d`un circuit integre (ASIC): application aux chambres multifils et aux photomultiplicateurs de l`experience GRAAL

    Energy Technology Data Exchange (ETDEWEB)

    Bugnet, H.

    1995-11-21

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs.

  16. 75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2010-05-05

    ... Semiconductor, Xiqing Integrated Semiconductor, Manufacturing Site, No. 15 Xinghua Road, Xiqing Economic... Malaysia Sdn. Bhd., NO. 2 Jalan SS 8/2, Free Industrial Zone, Sungai Way, 47300 Petaling Jaya, Selengor, Malaysia. Freescale Semiconductor Pte. Ltd., 7 Changi South Street 2, 03-00, Singapore 486415. Freescale...

  17. mm-Wave Wireless Communications based on Silicon Photonics Integrated Circuits

    DEFF Research Database (Denmark)

    Rommel, Simon; Heck, Martijn; Vegas Olmos, Juan José

    Hybrid photonic-wireless transmission schemes in the mm-wave frequency range are promising candidates to enable the multi-gigabit per second data communications required from wireless and mobile networks of the 5th and future generations. Photonic integration may pave the way to practical...

  18. Silicon Photonics Integrated Circuits for 5th Generation mm-Wave Wireless Communications

    DEFF Research Database (Denmark)

    Rommel, Simon; Vegas Olmos, Juan José; Tafur Monroy, Idelfonso

    Hybrid photonic-wireless transmission schemes in the mm-wave frequency are promising candidates to enable the multi-gigabit per second data communications required from wireless and mobile networks of the 5th and future generations. Photonic integration may pave the way to practical applicability...

  19. Synchronic, optical transmission data link integrated with FPGA circuits (for TESLA LLRF control system)

    Energy Technology Data Exchange (ETDEWEB)

    Zielinski, J.S.

    2006-07-15

    The X-ray free-electron laser X-FEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short X-ray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new possibilities for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated to the LLRF1 system in VUV FEL experiment It is being developed by the ELHEP2 group in the Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller to stabilize the vector sum of fields in cavities of one cryo-module in the experiment. The device can be also used as the simulator of the cavity and test bench for other devices. The synchronic, optical link project was made for the accelerator X-FEL laser TESLA, the LLRF control system experiment at DESY, Hamburg. The control and diagnostic data is transmitted up to 2.5Gbit/s through a plastic fiber in a distance up to a few hundred meters. The link is synchronized once after power up, and never resynchronized when data is transmitted with maximum speed. The one way link bit error rate is less then 10{sup -15}. The transceiver component written in VHDL that works in the dedicated Altera registered Stratix registered GX FPGA circuit. During the work in the PERG laboratory a 2,5Gbit/s serial link with the long vector parallel interface transceiver was created. Long-Data-Vector transceiver transmits 16bit vector each 8ns with 120ns latency. (orig.)

  20. Synchronic, optical transmission data link integrated with FPGA circuits (for TESLA LLRF control system)

    International Nuclear Information System (INIS)

    Zielinski, J.S.

    2006-05-01

    The X-ray free-electron laser X-FEL that is being planned at the DESY research center in cooperation with European partners will produce high-intensity ultra-short X-ray flashes with the properties of laser light. This new light source, which can only be described in terms of superlatives, will open up a whole range of new possibilities for the natural sciences. It could also offer very promising opportunities for industrial users. SIMCON (SIMulator and CONtroller) is the project of the fast, low latency digital controller dedicated to the LLRF1 system in VUV FEL experiment It is being developed by the ELHEP2 group in the Institute of Electronic Systems at Warsaw University of Technology. The main purpose of the project is to create a controller to stabilize the vector sum of fields in cavities of one cryo-module in the experiment. The device can be also used as the simulator of the cavity and test bench for other devices. The synchronic, optical link project was made for the accelerator X-FEL laser TESLA, the LLRF control system experiment at DESY, Hamburg. The control and diagnostic data is transmitted up to 2.5Gbit/s through a plastic fiber in a distance up to a few hundred meters. The link is synchronized once after power up, and never resynchronized when data is transmitted with maximum speed. The one way link bit error rate is less then 10 -15 . The transceiver component written in VHDL that works in the dedicated Altera registered Stratix registered GX FPGA circuit. During the work in the PERG laboratory a 2,5Gbit/s serial link with the long vector parallel interface transceiver was created. Long-Data-Vector transceiver transmits 16bit vector each 8ns with 120ns latency. (orig.)

  1. Integrated GaN photonic circuits on silicon (100) for second harmonic generation

    OpenAIRE

    Xiong, Chi; Pernice, Wolfram; Ryu, Kevin K.; Schuck, Carsten; Fong, King Y.; Palacios, Tomas; Tang, Hong X.

    2014-01-01

    We demonstrate second order optical nonlinearity in a silicon architecture through heterogeneous integration of single-crystalline gallium nitride (GaN) on silicon (100) substrates. By engineering GaN microrings for dual resonance around 1560 nm and 780 nm, we achieve efficient, tunable second harmonic generation at 780 nm. The \\{chi}(2) nonlinear susceptibility is measured to be as high as 16 plus minus 7 pm/V. Because GaN has a wideband transparency window covering ultraviolet, visible and ...

  2. Multisensory integration for odor tracking by flying Drosophila: Behavior, circuits and speculation

    OpenAIRE

    Duistermars, Brian J; Frye, Mark A

    2010-01-01

    Many see fruit flies as an annoyance, invading our homes with a nagging persistence and efficiency. Yet from a scientific perspective, these tiny animals are a wonder of multisensory integration, capable of tracking fragmented odor plumes amidst turbulent winds and constantly varying visual conditions. The peripheral olfactory, mechanosensory, and visual systems of the fruit fly, Drosophila melanogaster, have been studied in great detail;1–4 however, the mechanisms by which fly brains integra...

  3. Low-loss, silicon integrated, aluminum nitride photonic circuits and their use for electro-optic signal processing.

    Science.gov (United States)

    Xiong, Chi; Pernice, Wolfram H P; Tang, Hong X

    2012-07-11

    Photonic miniaturization requires seamless integration of linear and nonlinear optical components to achieve passive and active functions simultaneously. Among the available material systems, silicon photonics holds immense promise for optical signal processing and on-chip optical networks. However, silicon is limited to wavelengths above 1.1 μm and does not provide the desired lowest order optical nonlinearity for active signal processing. Here we report the integration of aluminum nitride (AlN) films on silicon substrates to bring active functionalities to chip-scale photonics. Using CMOS-compatible sputtered thin films we fabricate AlN-on-insulator waveguides that exhibit low propagation loss (0.6 dB/cm). Exploiting AlN's inherent Pockels effect we demonstrate electro-optic modulation up to 4.5 Gb/s with very low energy consumption (down to 10 fJ/bit). The ultrawide transparency window of AlN devices also enables high speed modulation at visible wavelengths. Our low cost, wideband, carrier-free photonic circuits hold promise for ultralow power and high-speed signal processing at the microprocessor chip level.

  4. Design of a high-speed vertical transition in LTCC for interposers suitable for packaging photonic integrated circuits

    Science.gov (United States)

    Jezzini, M. A.; Marraccini, P. J.; Peters, F. H.

    2016-05-01

    The packaging of high speed Photonic Integrated Circuits (PICs) should maintain the electrical signal integrity. The standard packaging of high speed PICs relies on wire bonds. This is not desirable because wire bonds degrade the quality of the electrical signal. The research presented in this paper proposes to replace wire bonds with an interposer with multilevel transmission lines. By attaching the PIC by flip chip onto the interposer, the use of wire bonds is avoided. The main concern for designing an interposer with multilevel transmission lines is the vertical transition, which must be designed to avoid return and radiation losses. In this paper, a novel design of a high speed vertical transition for Low Temperature Co-fired Ceramic (LTCC) is presented. The proposed vertical transition is simpler than others recently published in the literature, due to eliminating the need for additional ceramic layers or air cavities. A LTCC board was fabricated with several variations of the presented transition to find the optimal dimensions of the structure. The structures were fabricated then characterized and have a 3 dB bandwidth of 37 GHz and an open eye diagram at 44 Gbps. A full wave electromagnetic simulation is described and compared with good agreement to the measurements. The results suggest that an LTCC board with this design can be used for 40 Gbps per channel applications. Keywords: Photonics packaging, Low Temperature Co-Fired Ceramics.

  5. Feeding state, insulin and NPR-1 modulate chemoreceptor gene expression via integration of sensory and circuit inputs.

    Science.gov (United States)

    Gruner, Matthew; Nelson, Dru; Winbush, Ari; Hintz, Rebecca; Ryu, Leesun; Chung, Samuel H; Kim, Kyuhyung; Gabel, Chrisopher V; van der Linden, Alexander M

    2014-10-01

    Feeding state and food availability can dramatically alter an animals' sensory response to chemicals in its environment. Dynamic changes in the expression of chemoreceptor genes may underlie some of these food and state-dependent changes in chemosensory behavior, but the mechanisms underlying these expression changes are unknown. Here, we identified a KIN-29 (SIK)-dependent chemoreceptor, srh-234, in C. elegans whose expression in the ADL sensory neuron type is regulated by integration of sensory and internal feeding state signals. We show that in addition to KIN-29, signaling is mediated by the DAF-2 insulin-like receptor, OCR-2 TRPV channel, and NPR-1 neuropeptide receptor. Cell-specific rescue experiments suggest that DAF-2 and OCR-2 act in ADL, while NPR-1 acts in the RMG interneurons. NPR-1-mediated regulation of srh-234 is dependent on gap-junctions, implying that circuit inputs regulate the expression of chemoreceptor genes in sensory neurons. Using physical and genetic manipulation of ADL neurons, we show that sensory inputs from food presence and ADL neural output regulate srh-234 expression. While KIN-29 and DAF-2 act primarily via the MEF-2 (MEF2) and DAF-16 (FOXO) transcription factors to regulate srh-234 expression in ADL neurons, OCR-2 and NPR-1 likely act via a calcium-dependent but MEF-2- and DAF-16-independent pathway. Together, our results suggest that sensory- and circuit-mediated regulation of chemoreceptor genes via multiple pathways may allow animals to precisely regulate and fine-tune their chemosensory responses as a function of internal and external conditions.

  6. A statistical-based material and process guidelines for design of carbon nanotube field-effect transistors in gigascale integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Ghavami, Behnam; Raji, Mohsen; Pedram, Hossein, E-mail: ghavamib@aut.ac.ir [Computer Engendering and Information Technology Department, Amirkabir University of Technology, Tehran (Iran, Islamic Republic of)

    2011-08-26

    Carbon nanotube field-effect transistors (CNFETs) show great promise as building blocks of future integrated circuits. However, synthesizing single-walled carbon nanotubes (CNTs) with accurate chirality and exact positioning control has been widely acknowledged as an exceedingly complex task. Indeed, density and chirality variations in CNT growth can compromise the reliability of CNFET-based circuits. In this paper, we present a novel statistical compact model to estimate the failure probability of CNFETs to provide some material and process guidelines for the design of CNFETs in gigascale integrated circuits. We use measured CNT spacing distributions within the framework of detailed failure analysis to demonstrate that both the CNT density and the ratio of metallic to semiconducting CNTs play dominant roles in defining the failure probability of CNFETs. Besides, it is argued that the large-scale integration of these devices within an integrated circuit will be feasible only if a specific range of CNT density with an acceptable ratio of semiconducting to metallic CNTs can be adjusted in a typical synthesis process.

  7. A high precision peak sensing circuit for measuring the integral linearity of nuclear pulse amplifiers

    International Nuclear Information System (INIS)

    Rogers, L.C.

    1989-01-01

    This paper describes a new instrument that very accurately transforms the peak height of repetitive waveforms into a dc voltage. Used in conjunction with a precision pulse generator, this instrument provides an improved method for establishing the integral linearity of pulse amplifiers. A measured overall accuracy of 0.005% for pulses with a nominal 1.0 μs peaking time has been achieved. This method is particularly useful with very fast amplifiers in the 5-100 ns range. The results of linearity measurements on several typical amplifiers are presented. (orig.)

  8. Cutoff-mesa isolated rib optical waveguide for III-V heterostructure photonic integrated circuits

    Science.gov (United States)

    Vawter, G.A.; Smith, R.E.

    1998-04-28

    A cutoff mesa rib waveguide provides single-mode performance regardless of any deep etches that might be used for electrical isolation between integrated electrooptic devices. Utilizing a principle of a cutoff slab waveguide with an asymmetrical refractive index profile, single mode operation is achievable with a wide range of rib widths and does not require demanding etch depth tolerances. This new waveguide design eliminates reflection effects, or self-interference, commonly seen when conventional rib waveguides are combined with deep isolation etches and thereby reduces high order mode propagation and crosstalk compared to the conventional rib waveguides. 7 figs.

  9. Monolithic microwave integrated circuits for sensors, radar, and communications systems; Proceedings of the Meeting, Orlando, FL, Apr. 2-4, 1991

    Science.gov (United States)

    Leonard, Regis F.; Bhasin, Kul B.

    Consideration is given to MMICs for airborne phased arrays, monolithic GaAs integrated circuit millimeter wave imaging sensors, accurate design of multiport low-noise MMICs up to 20 GHz, an ultralinear low-noise amplifier technology for space communications, variable-gain MMIC module for space applications, a high-efficiency dual-band power amplifier for radar applications, a high-density circuit approach for low-cost MMIC circuits, coplanar SIMMWIC circuits, recent advances in monolithic phased arrays, and system-level integrated circuit development for phased-array antenna applications. Consideration is also given to performance enhancement in future communications satellites with MMIC technology insertion, application of Ka-band MMIC technology for an Orbiter/ACTS communications experiment, a space-based millimeter wave debris tracking radar, low-noise high-yield octave-band feedback amplifiers to 20 GHz, quasi-optical MESFET VCOs, and a high-dynamic-range mixer using novel balun structure. (For individual items see A93-25777 to A93-25814)

  10. Increasing the density of passive photonic-integrated circuits via nanophotonic cloaking

    Science.gov (United States)

    Shen, Bing; Polson, Randy; Menon, Rajesh

    2016-11-01

    Photonic-integrated devices need to be adequately spaced apart to prevent signal cross-talk. This fundamentally limits their packing density. Here we report the use of nanophotonic cloaking to render neighbouring devices invisible to one another, which allows them to be placed closer together than is otherwise feasible. Specifically, we experimentally demonstrated waveguides that are spaced by a distance of ~λ0/2 and designed waveguides with centre-to-centre spacing as small as 600 nm (-2 dB and an extinction ratio >15 dB over a bandwidth larger than 60 nm. This performance can be improved with better design algorithms and industry-standard lithography. The nanophotonic cloak relies on multiple guided-mode resonances, which render such devices very robust to fabrication errors. Our devices are broadly complimentary-metal-oxide-semiconductor compatible, have a minimum pitch of 200 nm and can be fabricated with a single lithography step. The nanophotonic cloaks can be generally applied to all passive integrated photonics.

  11. Transient Thermal Analysis of 3-D Integrated Circuits Packages by the DGTD Method

    KAUST Repository

    Li, Ping

    2017-03-11

    Since accurate thermal analysis plays a critical role in the thermal design and management of the 3-D system-level integration, in this paper, a discontinuous Galerkin time-domain (DGTD) algorithm is proposed to achieve this purpose. Such as the parabolic partial differential equation (PDE), the transient thermal equation cannot be directly solved by the DGTD method. To address this issue, the heat flux, as an auxiliary variable, is introduced to reduce the Laplace operator to a divergence operator. The resulting PDE is hyperbolic, which can be further written into a conservative form. By properly choosing the definition of the numerical flux used for the information exchange between neighboring elements, the hyperbolic thermal PDE can be solved by the DGTD together with the auxiliary differential equation. The proposed algorithm is a kind of element-level domain decomposition method, which is suitable to deal with multiscale geometries in 3-D integrated systems. To verify the accuracy and robustness of the developed DGTD algorithm, several representative examples are benchmarked.

  12. A multichannel integrated circuit for electrical recording of neural activity, with independent channel programmability.

    Science.gov (United States)

    Mora Lopez, Carolina; Prodanov, Dimiter; Braeken, Dries; Gligorijevic, Ivan; Eberle, Wolfgang; Bartic, Carmen; Puers, Robert; Gielen, Georges

    2012-04-01

    Since a few decades, micro-fabricated neural probes are being used, together with microelectronic interfaces, to get more insight in the activity of neuronal networks. The need for higher temporal and spatial recording resolutions imposes new challenges on the design of integrated neural interfaces with respect to power consumption, data handling and versatility. In this paper, we present an integrated acquisition system for in vitro and in vivo recording of neural activity. The ASIC consists of 16 low-noise, fully-differential input channels with independent programmability of its amplification (from 100 to 6000 V/V) and filtering (1-6000 Hz range) capabilities. Each channel is AC-coupled and implements a fourth-order band-pass filter in order to steeply attenuate out-of-band noise and DC input offsets. The system achieves an input-referred noise density of 37 nV/√Hz, a NEF of 5.1, a CMRR > 60 dB, a THD noise ratios.

  13. Surface plasmon polariton band gap structures: implications to integrated plasmonic circuits

    DEFF Research Database (Denmark)

    Bozhevolnyi, S. I.; Volkov, V. S.; Østergaard, John Erland

    2001-01-01

    Conventional photonic band gap (PBG) structures are composed of regions with periodic modulation of refractive index that do not allow the propagation of electromagnetic waves in a certain interval of wavelengths, i.e., that exhibit the PBG effect. The PBG effect is essentially an interference...... phenomenon related to strong multiple scattering of light in periodic media. The interest to the PBG structures has dramatically risen since the possibility of efficient waveguiding around a sharp corner of a line defect in the PBG structure has been pointed out. Given the perspective of integrating various...... PBG-based components within a few hundred micrometers, we realized that other two-dimensional waves, e.g., surface plasmon polaritons (SPPs), might be employed for the same purpose. The SPP band gap (SPPBG) has been observed for the textured silver surfaces by performing angular measurements...

  14. Artificial brains. A million spiking-neuron integrated circuit with a scalable communication network and interface.

    Science.gov (United States)

    Merolla, Paul A; Arthur, John V; Alvarez-Icaza, Rodrigo; Cassidy, Andrew S; Sawada, Jun; Akopyan, Filipp; Jackson, Bryan L; Imam, Nabil; Guo, Chen; Nakamura, Yutaka; Brezzo, Bernard; Vo, Ivan; Esser, Steven K; Appuswamy, Rathinakumar; Taba, Brian; Amir, Arnon; Flickner, Myron D; Risk, William P; Manohar, Rajit; Modha, Dharmendra S

    2014-08-08

    Inspired by the brain's structure, we have developed an efficient, scalable, and flexible non-von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts. Copyright © 2014, American Association for the Advancement of Science.

  15. Integrated Circuits for Rapid Sample Processing and Electrochemical Detection of Biomarkers

    Science.gov (United States)

    Besant, Justin

    The trade-off between speed and sensitivity of detection is a fundamental challenge in the design of point-of-care diagnostics. As the relevant molecules in many diseases exist natively at extremely low levels, many gold-standard diagnostic tests are designed with high sensitivity at the expense of long incubations needed to amplify the target analytes. The central aim of this thesis is to design new strategies to detect biologically relevant analytes with both high speed and sensitivity. The response time of a biosensor is limited by the ability of the target analyte to accumulate to detectable levels at the sensor surface. We overcome this limitation by designing a range of integrated devices to optimize the flux of the analyte to the sensor by increasing the effective analyte concentration, shortening the required diffusion distance, and confining the analyte in close proximity to the sensor. We couple these devices with novel ultrasensitive electrochemical transduction strategies to convert rare analytes into a detectable signal. We showcase the clinical utility of these approaches with several applications including cancer diagnosis, bacterial identification, and antibiotic susceptibility profiling. We design and optimize a device to isolate rare cancer cells from the bloodstream with near 100% efficiency and 10 000-fold specificity. We analyse pathogen specific nucleic acids by lysing bacteria in close proximity to an electrochemical sensor and find that this approach has 10-fold higher sensitivity than standard lysis in bulk solution. We design an electronic chip to readout the antibiotic susceptibility profile with an hour-long incubation by concentrating bacteria into nanoliter chambers with integrated electrodes. Finally, we report a strategy for ultrasensitive visual readout of nucleic acids as low as 100 fM within 10 minutes using an amplification cascade. The strategies presented could guide the development of fast, sensitive and low-cost diagnostics

  16. Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for Fabrication with 0.09-micron High Electron Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide (SiC)

    Science.gov (United States)

    2016-03-01

    monolithic microwave integrated circuits (MMICs) are essential for compact hand-held satellite communications systems that provide instant, secure data...of approximately 30 to 45 GHz, monolithic microwave integrated circuits (MMICs) are essential for compact hand- held satellite communications (SATCOM...efforts focused on developing efficient high-power amplifiers for SATCOM applications , while current efforts are focused on modeling efforts

  17. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    Science.gov (United States)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

  18. Integration of Nanobots Into Neural Circuits As a Future Therapy for Treating Neurodegenerative Disorders

    Directory of Open Access Journals (Sweden)

    Arthur Saniotis

    2018-03-01

    Full Text Available Recent neuroscientific research demonstrates that the human brain is becoming altered by technological devices. Improvements in biotechnologies and computer based technologies are now increasing the likelihood for the development of brain augmentation devices in the next 20 years. We have developed the idea of an “Endomyccorhizae like interface” (ELI nanocognitive device as a new kind of future neuroprosthetic which aims to facilitate neuronal network properties in individuals with neurodegenerative disorders. The design of our ELI may overcome the problems of invasive neuroprosthetics, post-operative inflammation, and infection and neuroprosthetic degradation. The method in which our ELI is connected and integrated to neuronal networks is based on a mechanism similar to endomyccorhizae which is the oldest and most widespread form of plant symbiosis. We propose that the principle of Endomyccorhizae could be relevant for developing a crossing point between the ELI and neuronal networks. Similar to endomyccorhizae the ELI will be designed to form webs, each of which connects multiple neurons together. The ELI will function to sense action potentials and deliver it to the neurons it connects to. This is expected to compensate for neuronal loss in some neurodegenerative disorders, such as Alzheimer's disease and Parkinson's disease.

  19. Novel High Temperature Capacitive Pressure Sensor Utilizing SiC Integrated Circuit Twin Ring Oscillators

    Science.gov (United States)

    Scardelletti, M.; Neudeck, P.; Spry, D.; Meredith, R.; Jordan, J.; Prokop, N.; Krasowski, M.; Beheim, G.; Hunter, G.

    2017-01-01

    This paper describes initial development and testing of a novel high temperature capacitive pressure sensor system. The pressure sensor system consists of two 4H-SiC 11-stage ring oscillators and a SiCN capacitive pressure sensor. One oscillator has the capacitive pressure sensor fixed at one node in its feedback loop and varies as a function of pressure and temperature while the other provides a pressure-independent reference frequency which can be used to temperature compensate the output of the first oscillator. A two-day repeatability test was performed up to 500C on the oscillators and the oscillator fundamental frequency changed by only 1. The SiCN capacitive pressure sensor was characterized at room temperature from 0 to 300 psi. The sensor had an initial capacitance of 3.76 pF at 0 psi and 1.75 pF at 300 psi corresponding to a 54 change in capacitance. The integrated pressure sensor system was characterized from 0 to 300 psi in steps of 50 psi over a temperature range of 25 to 500C. The pressure sensor system sensitivity was 0.113 kHzpsi at 25C and 0.026 kHzpsi at 500C.

  20. Offset cancelling circuit

    NARCIS (Netherlands)

    Wiegerink, Remco J.; Seevinck, Evert; de Jager, Wim

    1989-01-01

    A monolithic offset cancelling circuit to reduce the offset voltage at an integrated audio-amplifier output is described. This offset voltage is detected using a low-pass filter with a very large time constant for which only one small on-chip capacitor is needed. The circuit was realized with a

  1. Study of sensitivity and noise in the piezoelectric self-sensing and self-actuating cantilever with an integrated Wheatstone bridge circuit.

    Science.gov (United States)

    Shin, ChaeHo; Jeon, InSu; Khim, Zheong G; Hong, J W; Nam, HyoJin

    2010-03-01

    A detection method using a self-sensing cantilever is more desirable than other detection methods (optical fiber and laser beam bounce detection) that are bulky and require alignment. The advantage of the self-sensing cantilever is its simplicity, particularly its simple structure. It can be used for the construction of an atomic force microscopy system with a vacuum, fluids, and a low temperature chamber. Additionally, the self-actuating cantilever can be used for a high speed scanning system because the bandwidth is larger than the bulk scanner. Frequently, ZnO film has been used as an actuator in a self-actuating cantilever. In this paper, we studied the characteristics of the self-sensing and self-actuating cantilever with an integrated Wheatstone bridge circuit substituting the ZnO film with a lead zirconate titanate (PZT) film as the actuator. We can reduce the leakage current (to less than 10(-4) A/cm(2)) in the PZT cantilever and improve sensor sensitivity through a reduction of noise level from the external sensor circuit using the Wheatstone bridge circuit embedded into the cantilever. The self-sensing and actuating cantilever with an integrated Wheatstone bridge circuit was compared with a commercial self-sensing cantilever or self-sensing and actuating cantilever without an integrated Wheatstone bridge circuit. The measurement results have shown that sensing the signal to noise level and the minimum detectable deflection improved to 4.78 mV and 1.18 nm, respectively. We believe that this cantilever allows for easier system integration and miniaturization, provides better controllability and higher scan speeds, and offers the potential for full automation.

  2. III-V-on-Silicon Photonic Integrated Circuits for Spectroscopic Sensing in the 2-4 μm Wavelength Range.

    Science.gov (United States)

    Wang, Ruijun; Vasiliev, Anton; Muneeb, Muhammad; Malik, Aditya; Sprengel, Stephan; Boehm, Gerhard; Amann, Markus-Christian; Šimonytė, Ieva; Vizbaras, Augustinas; Vizbaras, Kristijonas; Baets, Roel; Roelkens, Gunther

    2017-08-04

    The availability of silicon photonic integrated circuits (ICs) in the 2-4 μm wavelength range enables miniature optical sensors for trace gas and bio-molecule detection. In this paper, we review our recent work on III-V-on-silicon waveguide circuits for spectroscopic sensing in this wavelength range. We first present results on the heterogeneous integration of 2.3 μm wavelength III-V laser sources and photodetectors on silicon photonic ICs for fully integrated optical sensors. Then a compact 2 μm wavelength widely tunable external cavity laser using a silicon photonic IC for the wavelength selective feedback is shown. High-performance silicon arrayed waveguide grating spectrometers are also presented. Further we show an on-chip photothermal transducer using a suspended silicon-on-insulator microring resonator used for mid-infrared photothermal spectroscopy.

  3. A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

    Science.gov (United States)

    De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

    2017-02-01

    This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

  4. Predictive Direct Torque Control Application-Specific Integrated Circuit of an Induction Motor Drive with a Fuzzy Controller

    Directory of Open Access Journals (Sweden)

    Guo-Ming Sung

    2017-06-01

    Full Text Available This paper proposes a modified predictive direct torque control (PDTC application-specific integrated circuit (ASIC of a motor drive with a fuzzy controller for eliminating sampling and calculating delay times in hysteresis controllers. These delay times degrade the control quality and increase both torque and flux ripples in a motor drive. The proposed fuzzy PDTC ASIC calculates the stator’s magnetic flux and torque by detecting the three-phase current, three-phase voltage, and rotor speed, and eliminates the ripples in the torque and flux by using a fuzzy controller and predictive scheme. The Verilog hardware description language was used to implement the hardware architecture, and the ASIC was fabricated by the Taiwan Semiconductor Manufacturing Company through a 0.18-μm 1P6M CMOS process that involved a cell-based design method. The measurements revealed that the proposed fuzzy PDTC ASIC of the three-phase induction motor yielded a test coverage of 96.03%, fault coverage of 95.06%, chip area of 1.81 × 1.81 mm2, and power consumption of 296 mW, at an operating frequency of 50 MHz and a supply voltage of 1.8 V.

  5. Quality control and authentication of packaged integrated circuits using enhanced-spatial-resolution terahertz time-domain spectroscopy and imaging

    Science.gov (United States)

    Ahi, Kiarash; Shahbazmohamadi, Sina; Asadizanjani, Navid

    2018-05-01

    In this paper, a comprehensive set of techniques for quality control and authentication of packaged integrated circuits (IC) using terahertz (THz) time-domain spectroscopy (TDS) is developed. By material characterization, the presence of unexpected materials in counterfeit components is revealed. Blacktopping layers are detected using THz time-of-flight tomography, and thickness of hidden layers is measured. Sanded and contaminated components are detected by THz reflection-mode imaging. Differences between inside structures of counterfeit and authentic components are revealed through developing THz transmission imaging. For enabling accurate measurement of features by THz transmission imaging, a novel resolution enhancement technique (RET) has been developed. This RET is based on deconvolution of the THz image and the THz point spread function (PSF). The THz PSF is mathematically modeled through incorporating the spectrum of the THz imaging system, the axis of propagation of the beam, and the intensity extinction coefficient of the object into a Gaussian beam distribution. As a result of implementing this RET, the accuracy of the measurements on THz images has been improved from 2.4 mm to 0.1 mm and bond wires as small as 550 μm inside the packaging of the ICs are imaged.

  6. A state-of-the-art review of continuous monitoring and surveillance techniques in relation to reactor pressure circuit integrity

    International Nuclear Information System (INIS)

    Nichols, R.W.

    1991-01-01

    This report reviews the present state of the art in the application to LWR primary circuit components of techniques for continuous monitoring and surveillance as an aid to structural integrity engineering assessments and to plant-life management. After discussing aspects related to the monitoring of plant operating conditions, particularly with respect to transient recording, the paper discusses neutron noise and vibration/noise measurements. The aspects of stress, temperature and chemical environment monitoring are discussed. Turning to measuring changes in mechanical properties of the structural materials the review first covers surveillance programmes for assessing irradiation embrittlement and then indicates a number of possibilities for the non-destructive monitoring of such changes although it is emphasized that none of these is ready for application without further development, calibration and plant trials. Moving on to the subject of monitoring structural damage the role of in-service inspection (ISI) using non-destructive testing methods is mentioned and the way that other methods, especially acoustic emission measurements, could supplement or in part replace such ISI is discussed. Other subjects covered include loose parts detection and leak detection which again often involve the use of acoustic emission. The paper ends with a short discussion and recommendations on future work and future possibilities

  7. An Energy efficient application specific integrated circuit for electrocardiogram feature detection and its potential for ambulatory cardiovascular disease detection.

    Science.gov (United States)

    Jain, Sanjeev Kumar; Bhaumik, Basabi

    2016-03-01

    A novel algorithm based on forward search is developed for real-time electrocardiogram (ECG) signal processing and implemented in application specific integrated circuit (ASIC) for QRS complex related cardiovascular disease diagnosis. The authors have evaluated their algorithm using MIT-BIH database and achieve sensitivity of 99.86% and specificity of 99.93% for QRS complex peak detection. In this Letter, Physionet PTB diagnostic ECG database is used for QRS complex related disease detection. An ASIC for cardiovascular disease detection is fabricated using 130-nm CMOS high-speed process technology. The area of the ASIC is 0.5 mm(2). The power dissipation is 1.73 μW at the operating frequency of 1 kHz with a supply voltage of 0.6 V. The output from the ASIC is fed to their Android application that generates diagnostic report and can be sent to a cardiologist through email. Their ASIC result shows average failed detection rate of 0.16% for six leads data of 290 patients in PTB diagnostic ECG database. They also have implemented a low-leakage version of their ASIC. The ASIC dissipates only 45 pJ with a supply voltage of 0.9 V. Their proposed ASIC is most suitable for energy efficient telemetry cardiovascular disease detection system.

  8. Control strategy and hardware implementation for DC–DC boost power circuit based on proportional–integral compensator for high voltage application

    Directory of Open Access Journals (Sweden)

    Sanjeevikumar Padmanaban

    2015-06-01

    Full Text Available For high-voltage (HV applications, the designers mostly prefer the classical DC–DC boost converter. However, it lacks due to the limitation of the output voltage by the gain transfer ratio, decreased efficiency and its requirement of two sensors for feedback signals, which creates complex control scheme with increased overall cost. Furthermore, the output voltage and efficiency are reduced due to the self-parasitic behavior of power circuit components. To overcome these drawbacks, this manuscript provides, the theoretical development and hardware implementation of DC–DC step-up (boost power converter circuit for obtaining extra output-voltage high-performance. The proposed circuit substantially improves the high output-voltage by voltage-lift technology with a closed loop proportional–integral controller. This complete numerical model of the converter circuit including closed loop P-I controller is developed in simulation (Matlab/Simulink software and the hardware prototype model is implemented with digital signal processor (DSP TMS320F2812. A detailed performance analysis was carried out under both line and load regulation conditions. Numerical simulation and its verification results provided in this paper, prove the good agreement of the circuit with theoretical background.

  9. Properties and application of a multichannel integrated circuit for low-artifact, patterned electrical stimulation of neural tissue

    Science.gov (United States)

    Hottowy, Paweł; Skoczeń, Andrzej; Gunning, Deborah E.; Kachiguine, Sergei; Mathieson, Keith; Sher, Alexander; Wiącek, Piotr; Litke, Alan M.; Dąbrowski, Władysław

    2012-12-01

    Objective. Modern multielectrode array (MEA) systems can record the neuronal activity from thousands of electrodes, but their ability to provide spatio-temporal patterns of electrical stimulation is very limited. Furthermore, the stimulus-related artifacts significantly limit the ability to record the neuronal responses to the stimulation. To address these issues, we designed a multichannel integrated circuit for a patterned MEA-based electrical stimulation and evaluated its performance in experiments with isolated mouse and rat retina. Approach. The Stimchip includes 64 independent stimulation channels. Each channel comprises an internal digital-to-analogue converter that can be configured as a current or voltage source. The shape of the stimulation waveform is defined independently for each channel by the real-time data stream. In addition, each channel is equipped with circuitry for reduction of the stimulus artifact. Main results. Using a high-density MEA stimulation/recording system, we effectively stimulated individual retinal ganglion cells (RGCs) and recorded the neuronal responses with minimal distortion, even on the stimulating electrodes. We independently stimulated a population of RGCs in rat retina, and using a complex spatio-temporal pattern of electrical stimulation pulses, we replicated visually evoked spiking activity of a subset of these cells with high fidelity. Significance. Compared with current state-of-the-art MEA systems, the Stimchip is able to stimulate neuronal cells with much more complex sequences of electrical pulses and with significantly reduced artifacts. This opens up new possibilities for studies of neuronal responses to electrical stimulation, both in the context of neuroscience research and in the development of neuroprosthetic devices.

  10. ESD analog circuits and design

    CERN Document Server

    Voldman, Steven H

    2014-01-01

    A comprehensive and in-depth review of analog circuit layout, schematic architecture, device, power network and ESD design This book will provide a balanced overview of analog circuit design layout, analog circuit schematic development, architecture of chips, and ESD design.  It will start at an introductory level and will bring the reader right up to the state-of-the-art. Two critical design aspects for analog and power integrated circuits are combined. The first design aspect covers analog circuit design techniques to achieve the desired circuit performance. The second and main aspect pres

  11. Gallium Nitride (GaN) Monolithic Microwave Integrated Circuit (MMIC) Designs Submitted to Air Force Research Laboratory (AFRL) Sponsored Qorvo Fabrication

    Science.gov (United States)

    2017-07-01

    ARL-TN-0835● July 2017 US Army Research Laboratory Gallium Nitride (GaN) Monolithic Microwave Integrated Circuit (MMIC) Designs...distribution is unlimited. NOTICES Disclaimers The findings in this report are not to be construed as an official Department of the Army...approval of the use thereof. Destroy this report when it is no longer needed. Do not return it to the originator. ARL-TN-0835 ● JULY

  12. MOS voltage automatic tuning circuit

    OpenAIRE

    李, 田茂; 中田, 辰則; 松本, 寛樹

    2004-01-01

    Abstract ###Automatic tuning circuit adjusts frequency performance to compensate for the process variation. Phase locked ###loop (PLL) is a suitable oscillator for the integrated circuit. It is a feedback system that compares the input ###phase with the output phase. It can make the output frequency equal to the input frequency. In this paper, PLL ###fomed of MOSFET's is presented.The presented circuit consists of XOR circuit, Low-pass filter and Relaxation ###Oscillator. On PSPICE simulation...

  13. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  14. Modern TTL circuits manual

    CERN Document Server

    Marston, R M

    2013-01-01

    Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com

  15. Noise-Reduction Circuit For Imaging Photodetectors

    Science.gov (United States)

    Ramirez, Luis J.; Pain, Bedabrata; Staller, Craig; Hickok, Roger W.

    1995-01-01

    Developmental correlated-triple-sampling circuit suppresses capacitor reset noise and attenuates low frequency noise in integrated-and-sampled circuits of multiplexed photodiode arrays. Noise reduction circuit part of Visible and Infrared Mapping Spectrometer (VIMS) instrument to fly aboard Cassini spacecraft to explore Saturn and its moons. Modified versions of circuit also useful for reducing noise in terrestrial photosensor instruments.

  16. Note: A 102 dB dynamic-range charge-sampling readout for ionizing particle/radiation detectors based on an application-specific integrated circuit (ASIC)

    Science.gov (United States)

    Pullia, A.; Zocca, F.; Capra, S.

    2018-02-01

    An original technique for the measurement of charge signals from ionizing particle/radiation detectors has been implemented in an application-specific integrated circuit form. The device performs linear measurements of the charge both within and beyond its output voltage swing. The device features an unprecedented spectroscopic dynamic range of 102 dB and is suitable for high-resolution ion and X-γ ray spectroscopy. We believe that this approach may change a widespread paradigm according to which no high-resolution spectroscopy is possible when working close to or beyond the limit of the preamplifier's output voltage swing.

  17. Optoelectronic cross-injection locking of a dual-wavelength photonic integrated circuit for low-phase-noise millimeter-wave generation.

    Science.gov (United States)

    Kervella, Gaël; Van Dijk, Frederic; Pillet, Grégoire; Lamponi, Marco; Chtioui, Mourad; Morvan, Loïc; Alouini, Mehdi

    2015-08-01

    We report on the stabilization of a 90-GHz millimeter-wave signal generated from a fully integrated photonic circuit. The chip consists of two DFB single-mode lasers whose optical signals are combined on a fast photodiode to generate a largely tunable heterodyne beat note. We generate an optical comb from each laser with a microwave synthesizer, and by self-injecting the resulting signal, we mutually correlate the phase noise of each DFB and stabilize the beatnote on a multiple of the frequency delivered by the synthesizer. The performances achieved beat note linewidth below 30 Hz.

  18. SEMICONDUCTOR INTEGRATED CIRCUITS: A high-performance, low-power σ Δ ADC for digital audio applications

    Science.gov (United States)

    Hao, Luo; Yan, Han; Cheung, Ray C. C.; Xiaoxia, Han; Shaoyu, Ma; Peng, Ying; Dazhong, Zhu

    2010-05-01

    A high-performance low-power σ Δ analog-to-digital converter (ADC) for digital audio applications is described. It consists of a 2-1 cascaded σ Δ modulator and a decimation filter. Various design optimizations are implemented in the system design, circuit implementation and layout design, including a high-overload-level coefficient-optimized modulator architecture, a power-efficient class A/AB operational transconductance amplifier, as well as a multi-stage decimation filter conserving area and power consumption. The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process. The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm2, which dissipates only 2.1 mA quiescent current in the analog circuits.

  19. Studies on Design Automation and Arithmetic Circuit Design for Single-Flux-Quantum Digital Circuits

    OpenAIRE

    小畑, 幸嗣; Obata, Koji

    2008-01-01

    Superconductive single-flux-quantum (SFQ) circuit technology attracts attention as a nextgeneration technology of integrated circuits because of its ultra-fast computation speedand low power consumption. In SFQ digital circuits, unlike CMOS digital circuits, apulse is used as a carrier of information and the representation of the logic values isdifferent from that in CMOS digital circuits. Therefore, design automation algorithms andstructure of arithmetic circuits suitable for SFQ digital cir...

  20. Resonance circuits for adiabatic circuits

    Directory of Open Access Journals (Sweden)

    C. Schlachta

    2003-01-01

    Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.

  1. Carbon Dioxide Flush of an Integrated Minimized Perfusion Circuit Prior to Priming Prevents Spontaneous Air Release Into the Arterial Line During Clinical Use.

    Science.gov (United States)

    Stehouwer, Marco C; de Vroege, Roel; Hoohenkerk, Gerard J F; Hofman, Frederik N; Kelder, Johannes C; Buchner, Bas; de Mol, Bastian A; Bruins, Peter

    2017-11-01

    Recently, an oxygenator with an integrated centrifugal blood pump (IP) was designed to minimize priming volume and to reduce blood foreign surface contact even further. The use of this oxygenator with or without integrated arterial filter was compared with a conventional oxygenator and nonintegrated centrifugal pump. To compare the air removal characteristics 60 patients undergoing coronary artery bypass grafting were alternately assigned into one of three groups to be perfused with a minimized extracorporeal circuit either with the conventional oxygenator, the oxygenator with IP, or the oxygenator with IP plus integrated arterial filter (IAF). Air entering and leaving the three devices was measured accurately with a bubble counter during cardiopulmonary bypass. No significant differences between all groups were detected, considering air entering the devices. Our major finding was that in both integrated devices groups incidental spontaneous release of air into the arterial line in approximately 40% of the patients was observed. Here, detectable bolus air (>500 µm) was shown in the arterial line, whereas in the minimal extracorporeal circulation circuit (MECC) group this phenomenon was not present. We decided to conduct an amendment of the initial design with METC-approval. Ten patients were assigned to be perfused with an oxygenator with IP and IAF. Importantly, the integrated perfusion systems used in these patients were flushed with carbon dioxide (CO 2 ) prior to priming of the systems. In the group with CO 2 flush no spontaneous air release was observed in all cases and this was significantly different from the initial study with the group with the integrated device and IAF. This suggests that air spilling may be caused by residual air in the integrated device. In conclusion, integration of a blood pump may cause spontaneous release of large air bubbles (>500 µm) into the arterial line, despite the presence of an integrated arterial filter. CO 2 flushing of

  2. Sensor readout detector circuit

    Science.gov (United States)

    Chu, D.D.; Thelen, D.C. Jr.

    1998-08-11

    A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems. 6 figs.

  3. Image quality and radiation dose of lower extremity CT angiography at 70 kVp on an integrated circuit detector dual-source computed tomography.

    Science.gov (United States)

    Qi, Li; Zhao, Yan'E; Zhou, Chang Sheng; Spearman, James V; Renker, Matthias; Schoepf, U Joseph; Zhang, Long Jiang; Lu, Guang Ming

    2015-06-01

    Despite the well-established requirement for radiation dose reduction there are few studies examining the potential for lower extremity CT angiography (CTA) at 70 kVp. To compare the image quality and radiation dose of lower extremity CTA at 70 kVp using a dual-source CT system with an integrated circuit detector to similar studies at 120 kVp. A total of 62 patients underwent lower extremity CTA. Thirty-one patients were examined at 70 kVp using a second generation dual-source CT with an integrated circuit detector (70 kVp group) and 31 patients were evaluated at 120 kVp using a first generation dual-source CT (120 kVp group). The attenuation and image noise were measured and signal-to-noise ratio (SNR) and contrast-to-noise ratio (CNR) were calculated. Two radiologists assessed image quality. Radiation dose was compared. The mean attenuation of the 70 kVp group was higher than the 120 kVp group (575 ± 149 Hounsfield units [HU] vs. 258 ± 38 HU, respectively, P quality score (3.7 ± 0.1 vs. 3.2 ± 0.3, respectively, P quality when compared with standard 120 kVp. © The Foundation Acta Radiologica 2014 Reprints and permissions: sagepub.co.uk/journalsPermissions.nav.

  4. Het onzichtbare circuit

    NARCIS (Netherlands)

    Nauta, Bram

    2013-01-01

    De chip, of geïntegreerde schakeling, heeft in een razend tempo ons leven ingrijpend veranderd. Het lijkt zo vanzelfsprekend dat er weer een nieuwe generatie smartphones, tablets of computers is. Maar dat is het niet. Prof.dr.ir. Bram Nauta, hoogleraar Integrated Circuit Design, laat in zijn rede

  5. Design and realisation of integrated circuits for the readout of pixel sensors in high-energy physics and biomedical imaging

    International Nuclear Information System (INIS)

    Peric, I.

    2004-08-01

    Radiation tolerant pixel-readout chip for the ATLAS pixel detector has been designed, implemented in a deep-submicron CMOS technology and successfully tested. The chip contains readout-channels with complex analog and digital circuits. Chip for steering of the DEPFET active-pixel matrix has been implemented in a high-voltage CMOS technology. The chip contains channels which generate fast sequences of high-voltage signals. Detector containing this chip has been successfully tested. Pixel-readout test chip for an X-ray imaging pixel sensor has been designed, implemented in a CMOS technology and tested. Pixel-readout channels are able to simultaneously count the signals generated by passage of individual photons and to sum the total charge generated during exposure time. (orig.)

  6. SEMICONDUCTOR INTEGRATED CIRCUITS: An advanced monolithic digitalized random carrier frequency spread-spectrum clock generator for EMI suppression

    Science.gov (United States)

    Haiyan, Guo; Zao, Chen; Bo, Zhang; Zhaoji, Li

    2010-06-01

    A novel monolithic digitalized random carrier frequency modulation spread-spectrum clock generator (RCF-SSCG) is proposed. In this design, the output frequency of the proposed RCF-SSCG changes with the intensity of the capacitive charge and discharge current. Its analytical model is induced and the effect of the modulation parameters on the spread spectrum is numerically simulated and discussed. Compared with other works, this design has the advantages of small size, low power consumption and good robustness. The circuit has been fabricated in a 0.5 μm CMOS process and applied to a class D amplifier in which the proposed RCF-SSCG occupies an area of 0.112 mm2 and consumes 9 mW. The experimental results confirm the theoretical analyses.

  7. Offset cancelling circuit

    OpenAIRE

    Wiegerink, Remco J.; Seevinck, Evert; de Jager, Wim

    1989-01-01

    A monolithic offset cancelling circuit to reduce the offset voltage at an integrated audio-amplifier output is described. This offset voltage is detected using a low-pass filter with a very large time constant for which only one small on-chip capacitor is needed. The circuit was realized with a bipolar cell-based semicustom array. Measurements have shown that a -3-dB bandwidth below 5 Hz can be realized with a capacitor value of 50 pF. The resulting offset voltage at the audio-amplifier outpu...

  8. LASER APPLICATIONS AND OTHER TOPICS IN QUANTUM ELECTRONICS: Laser-induced extreme UV radiation sources for manufacturing next-generation integrated circuits

    Science.gov (United States)

    Borisov, V. M.; Vinokhodov, A. Yu; Ivanov, A. S.; Kiryukhin, Yu B.; Mishchenko, V. A.; Prokof'ev, A. V.; Khristoforov, O. B.

    2009-10-01

    The development of high-power discharge sources emitting in the 13.5±0.135-nm spectral band is of current interest because they are promising for applications in industrial EUV (extreme ultraviolet) lithography for manufacturing integrated circuits according to technological precision standards of 22 nm and smaller. The parameters of EUV sources based on a laser-induced discharge in tin vapours between rotating disc electrodes are investigated. The properties of the discharge initiation by laser radiation at different wavelengths are established and the laser pulse parameters providing the maximum energy characteristics of the EUV source are determined. The EUV source developed in the study emits an average power of 276 W in the 13.5±0.135-nm spectral band on conversion to the solid angle 2π sr in the stationary regime at a pulse repetition rate of 3000 Hz.

  9. The Development of an Online Support Tool for the Teaching and Learning of the IEEE Standard 1500 for Embedded Core-based Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Ian A Grout

    2012-11-01

    Full Text Available In this paper, an online education tool for assisting the teaching and learning of the IEEE 1500 standard testability method, used to support the testing of complex system-on-a-chip (SoC integrated circuits (ICs, is developed and presented. The tool is an Internet browser based tool that supports the ability to investigate key aspects of the standard and its application to embedded core-based IC designs. The tool allows the user to create VHDL descriptions of both the test circuitry and the function circuitry via the Internet browser interface. The key considerations for developing this tool were to provide a computer based learning tool to support the teaching and learning of the standard and its application. This paper is an extended version of a paper presented at the EDUCON 2012 conference in April 2012.

  10. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

    Science.gov (United States)

    Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

    2017-06-24

    With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  11. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

    Directory of Open Access Journals (Sweden)

    Chen Yang

    2017-06-01

    Full Text Available With the development of satellite load technology and very large scale integrated (VLSI circuit technology, onboard real-time synthetic aperture radar (SAR imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT, which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array−application-specific integrated circuit (FPGA-ASIC hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  12. A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

    Science.gov (United States)

    Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

    2017-12-01

    One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

  13. III-nitride Photonic Integrated Circuit: Multi-section GaN Laser Diodes for Smart Lighting and Visible Light Communication

    KAUST Repository

    Shen, Chao

    2017-04-01

    The past decade witnessed the rapid development of III-nitride light-emitting diodes (LEDs) and laser diodes (LDs), for smart lighting, visible-light communication (VLC), optical storage, and internet-of-things. Recent studies suggested that the GaN-based LDs, which is free from efficiency droop, outperform LEDs as a viable high-power light source. Conventionally, the InGaN-based LDs are grown on polar, c-plane GaN substrates. However, a relatively low differential gain limited the device performance due to a significant polarization field in the active region. Therefore, the LDs grown on nonpolar m-plane and semipolar (2021)-plane GaN substrates are posed to deliver high-efficiency owing to the entirely or partially eliminated polarization field. To date, the smart lighting and VLC functionalities have been demonstrated based on discrete devices, such as LDs, transverse-transmission modulators, and waveguide photodetectors. The integration of III-nitride photonic components, including the light emitter, modulator, absorber, amplifier, and photodetector, towards the realization of III-nitride photonic integrated circuit (PIC) offers the advantages of small-footprint, high-speed, and low power consumption, which has yet to be investigated. This dissertation presents the design, fabrication, and characterization of the multi-section InGaN laser diodes with integrated functionalities on semipolar (2021)-plane GaN substrates for enabling such photonic integration. The blue-emitting integrated waveguide modulator-laser diode (IWM-LD) exhibits a high modulation efficiency of 2.68 dB/V. A large extinction ratio of 11.3 dB is measured in the violet-emitting IWM-LD. Utilizing an integrated absorber, a high optical power (250mW), droop-free, speckle-free, and large modulation bandwidth (560MHz) blue-emitting superluminescent diode is reported. An integrated short-wavelength semiconductor optical amplifier with the laser diode at ~404 nm is demonstrated with a large gain of 5

  14. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation hardened CMOS devices and circuits - LDRD Project (FY99)

    International Nuclear Information System (INIS)

    Myers, David R.; Jessing, Jeffrey R.; Spahn, Olga B.; Shaneyfelt, Marty R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds

  15. Fluorine containing C(60) derivatives for high-performance electron transporting field-effect transistors and integrated circuits

    NARCIS (Netherlands)

    Wobkenberg, Paul H.; Ball, James; Bradley, Donal D. C.; Anthopoulos, Thomas D.; Kooistra, Floris; Hummelen, Jan C.; de Leeuw, Dago M.; Wöbkenberg, Paul H.

    2008-01-01

    We report on electron transporting organic transistors and integrated ring oscillators based on four different solution processible fluorine containing C(60) derivatives. Electron mobilities up to 0.15 cm(2)/V s are obtained from as-prepared bottom-gate, bottom-contact transistors utilizing gold

  16. High-Frequency Wireless Communications System: 2.45-GHz Front-End Circuit and System Integration

    Science.gov (United States)

    Chen, M.-H.; Huang, M.-C.; Ting, Y.-C.; Chen, H.-H.; Li, T.-L.

    2010-01-01

    In this article, a course on high-frequency wireless communications systems is presented. With the 145-MHz baseband subsystem available from a prerequisite course, the present course emphasizes the design and implementation of the 2.45-GHz front-end subsystem as well as system integration issues. In this curriculum, the 2.45-GHz front-end…

  17. Assessment of image quality and low-contrast detectability in abdominal CT of obese patients: comparison of a novel integrated circuit with a conventional discrete circuit detector at different tube voltages

    International Nuclear Information System (INIS)

    Euler, A.; Heye, T.; Kekelidze, M.; Bongartz, G.; Schindera, Sebastian T.; Szucs-Farkas, Z.; Sommer, C.; Schmidt, B.

    2015-01-01

    To compare image quality and low-contrast detectability of an integrated circuit (IC) detector in abdominal CT of obese patients with conventional detector technology at low tube voltages. A liver phantom with 45 lesions was placed in a water container to mimic an obese patient and examined on two different CT systems at 80, 100 and 120 kVp. The systems were equipped with either the IC or conventional detector. Image noise was measured, and the contrast-to-noise-ratio (CNR) was calculated. Low-contrast detectability was assessed independently by three radiologists. Radiation dose was estimated by the volume CT dose index (CTDI vol ). The image noise was significantly lower, and the CNR was significantly higher with the IC detector at 80, 100 and 120 kVp, respectively (P = 0.023). The IC detector resulted in an increased lesion detection rate at 80 kVp (38.1 % vs. 17.2 %) and 100 kVp (57.0 % vs. 41.0 %). There was no difference in the detection rate between the IC detector at 100 kVp and the conventional detector at 120 kVp (57.0 % vs. 62.2 %). The CTDI vol at 80, 100 and 120 kVp measured 4.5-5.2, 7.3-7.9 and 9.8-10.2 mGy, respectively. The IC detector at 100 kVp resulted in similar low-contrast detectability compared to the conventional detector with a 120-kVp protocol at a radiation dose reduction of 37 %. (orig.)

  18. Circuit Training.

    Science.gov (United States)

    Nelson, Jane B.

    1998-01-01

    Describes a research-based activity for high school physics students in which they build an LC circuit and find its resonant frequency of oscillation using an oscilloscope. Includes a diagram of the apparatus and an explanation of the procedures. (DDR)

  19. Affective Circuits

    DEFF Research Database (Denmark)

    to the intersecting streams of goods, people, ideas, and money as they circulate between African migrants and their kin who remain back home. They also show the complex ways that emotions become entangled in these exchanges. Examining how these circuits operate in domains of social life ranging from child fosterage...

  20. Implementation of Chua's circuit using simulated inductance

    Science.gov (United States)

    Gopakumar, K.; Premlet, B.; Gopchandran, K. G.

    2011-05-01

    In this study we describe how to build an inductorless version of the classic Chua's circuit. A suitable inductor for Chua's circuit is often hard to procure. The required inductor for the circuit is designed using simple circuit elements such as resistors, capacitors and operational amplifiers. The complete circuit can be implemented by using off-the-shelf components, and it can readily be integrated on a single chip. This design of Chua's circuit allows the original dynamics to be slowed down to just a few hertz, enabling implementation of sophisticated control schemes without severe time restrictions. Another novel feature of the circuit is that losses associated with capacitors due to leakages can easily be compensated by providing negative resistance using the same setup. The chaotic behaviour of the circuit is verified by PSpice and Multisim simulation and also by experimental study on a circuit breadboard. The results give excellent agreement with each other and with the results of previous investigators.

  1. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  2. 1.25  GHz sine wave gating InGaAs/InP single-photon detector with a monolithically integrated readout circuit.

    Science.gov (United States)

    Jiang, Wen-Hao; Liu, Jian-Hong; Liu, Yin; Jin, Ge; Zhang, Jun; Pan, Jian-Wei

    2017-12-15

    InGaAs/InP single-photon detectors (SPDs) are the key devices for applications requiring near-infrared single-photon detection. The gating mode is an effective approach to synchronous single-photon detection. Increasing gating frequency and reducing the module size are important challenges for the design of such a detector system. Here we present for the first time, to the best of our knowledge, an InGaAs/InP SPD with 1.25 GHz sine wave gating (SWG) using a monolithically integrated readout circuit (MIRC). The MIRC has a size of 15  mm×15  mm and implements the miniaturization of avalanche extraction for high-frequency SWG. In the MIRC, low-pass filters and a low-noise radio frequency amplifier are integrated based on the technique of low temperature co-fired ceramic, which can effectively reduce the parasitic capacitance and extract weak avalanche signals. We then characterize the InGaAs/InP SPD to verify the functionality and reliability of the MIRC, and the SPD exhibits excellent performance with 27.5% photon detection efficiency, a 1.2 kcps dark count rate, and 9.1% afterpulse probability at 223 K and 100 ns hold-off time. With this MIRC, one can further design miniaturized high-frequency SPD modules that are highly required for practical applications.

  3. Evidence for a Specific Integrative Mechanism for Episodic Memory Mediated by AMPA/kainate Receptors in a Circuit Involving Medial Prefrontal Cortex and Hippocampal CA3 Region.

    Science.gov (United States)

    de Souza Silva, Maria A; Huston, Joseph P; Wang, An-Li; Petri, David; Chao, Owen Yuan-Hsin

    2016-07-01

    We asked whether episodic-like memory requires neural mechanisms independent of those that mediate its component memories for "what," "when," and "where," and if neuronal connectivity between the medial prefrontal cortex (mPFC) and the hippocampus (HPC) CA3 subregion is essential for episodic-like memory. Unilateral lesion of the mPFC was combined with unilateral lesion of the CA3 in the ipsi- or contralateral hemispheres in rats. Episodic-like memory was tested using a task, which assesses the integration of memories for "what, where, and when" concomitantly. Tests for novel object recognition (what), object place (where), and temporal order memory (when) were also applied. Bilateral disconnection of the mPFC-CA3 circuit by N-methyl-d-aspartate (NMDA) lesions disrupted episodic-like memory, but left the component memories for object, place, and temporal order, per se, intact. Furthermore, unilateral NMDA lesion of the CA3 plus injection of (6-cyano-7-nitroquinoxaline-2,3-dione) (CNQX) (AMPA/kainate receptor antagonist), but not AP-5 (NMDA receptor antagonist), into the contralateral mPFC also disrupted episodic-like memory, indicating the mPFC AMPA/kainate receptors as critical for this circuit. These results argue for a selective neural system that specifically subserves episodic memory, as it is not critically involved in the control of its component memories for object, place, and time. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please e-mail: journals.permissions@oup.com.

  4. Development FD-SOI MOSFET Amplifiers for Integrated Read-Out Circuit of Superconducting-Tunnel-Junction Single-Photon-Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Kiuchi, Kenji; et al.

    2015-07-27

    We proposed a new high-resolution single-photon infrared spectrometer for search for radiative decay of cosmic neutrino background (CνB). The superconducting-tunnel-junctions(STJs) are used as a single-photon counting device. Each STJ consists of Nb/Al/AlxOy/Al/Nb layers, and their thicknesses are optimized for the operation temperature at 370 mK cooled by a 3He sorption refrigerator. Our STJs achieved the leak current 250 pA, and the measured data implies that a smaller area STJ fulfills our requirement. FD-SOI MOSFETs are employed to amplify the STJ signal current in order to increase signal-to-noise ratio (S/N). FD-SOI MOSFETs can be operated at cryogenic temperature of 370 mK, which reduces the noise of the signal amplification system. FD-SOI MOSFET characteristics are measured at cryogenic temperature. The Id-Vgs curve shows a sharper turn on with a higher threshold voltage and the Id-Vds curve shows a nonlinear shape in linear region at cryogenic temperature. Taking into account these effects, FD-SOI MOSFETs are available for read-out circuit of STJ detectors. The bias voltage for STJ detectors is 0.4 mV, and it must be well stabilized to deliver high performance. We proposed an FD-SOI MOSFET-based charge integrated amplifier design as a read-out circuit of STJ detectors. The requirements for an operational amplifier used in the amplifier is estimated using SPICE simulation. The op-amp is required to have a fast response (GBW ≥ 100 MHz), and it must have low power dissipation as compared to the cooling power of refrigerator.

  5. VLSI circuits implementing computational models of neocortical circuits.

    Science.gov (United States)

    Wijekoon, Jayawan H B; Dudek, Piotr

    2012-09-15

    This paper overviews the design and implementation of three neuromorphic integrated circuits developed for the COLAMN ("Novel Computing Architecture for Cognitive Systems based on the Laminar Microcircuitry of the Neocortex") project. The circuits are implemented in a standard 0.35 μm CMOS technology and include spiking and bursting neuron models, and synapses with short-term (facilitating/depressing) and long-term (STDP and dopamine-modulated STDP) dynamics. They enable execution of complex nonlinear models in accelerated-time, as compared with biology, and with low power consumption. The neural dynamics are implemented using analogue circuit techniques, with digital asynchronous event-based input and output. The circuits provide configurable hardware blocks that can be used to simulate a variety of neural networks. The paper presents experimental results obtained from the fabricated devices, and discusses the advantages and disadvantages of the analogue circuit approach to computational neural modelling. Copyright © 2012 Elsevier B.V. All rights reserved.

  6. TIMING CIRCUIT

    Science.gov (United States)

    Heyd, J.W.

    1959-07-14

    An electronic circuit is described for precisely controlling the power delivered to a load from an a-c source, and is particularly useful as a welder timer. The power is delivered in uniform pulses, produced by a thyratron, the number of pulses being controlled by a one-shot multivibrator. The starting pulse is synchronized with the a-c line frequency so that each multivlbrator cycle begins at about the same point in the a-c cycle.

  7. Integrated Heterodyne MOEMS for detection of low intensity signals

    Science.gov (United States)

    Elman, Noel M.; Krylov, Slava; Sternheim, Marek; Shacham-Diamand, Yosi

    2006-01-01

    A novel MEMS-based modulation scheme is presented as a method to enhance the signal-to-noise ratio (SNR) of silicon photodiodes adapted for the detection of light-emitting bio-reporter signals. Photodiodes are an attractive photodetector choice because they are VLSI compatible, easily miniaturized, highly scalable, and inexpensive. Silicon photodiodes exhibit a wide response range extending from the ultraviolet (UV) to the near infrared (IR) part of the spectrum, which in principle is appropriate for sensing low intensity optical signals. Silicon photodiodes, however, exhibit limited sensitivity to optical dc signals, as the magnitude of the low frequency noise is comparable to signal magnitude. Optical modulation prior to photodetection overcomes the inherent low frequency noise of photodetectors and system detection circuits. The enhancement scheme is based on a design of high frequency optical modulators that operate in the 1-2 kHz range in order to overcome the low frequency spectral noise. We have denominated this MEMS-based scheme Integrated Heterodyne Optical System (IHOS). The modulation efficiency of the proposed architecture can reach up to 50 percent. In order to implement the MOEMS optical modulators, a new two-mask fabrication process was developed that combines high-aspect ratio and low aspect ratio structures at the same device layer (aspect ratio is defined as a ratio between the structure height to its width). Long stroke electrostatic combdrive actuators integrated with folded flexures (high aspect-ratio) were fabricated together to drive large aperture shutters (low aspect ratio). We have denominated this process MASIS (Multiple Aspect Ratio Structural Integration). Under resonant excitation at approximately 1 kHz, MOEMS modulators demonstrated maximum displacement of about 40 microns at an actuation voltage of 15 V peak in air, and 3.5 V peak in vacuum (8 mTorr). Results of analytical solutions and finite element analysis (FEA) simulations are

  8. Low-temperature spray-deposited indium oxide for flexible thin-film transistors and integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Petti, Luisa; Faber, Hendrik; Anthopoulos, Thomas D., E-mail: t.anthopoulos@imperial.ac.uk [Blackett Laboratory, Department of Physics and Centre for Plastic Electronics, Imperial College London, London SW7 2BW (United Kingdom); Münzenrieder, Niko; Cantarella, Giuseppe; Tröster, Gerhard [Electronics Laboratory, Swiss Federal Institute of Technology Zurich, Gloriastrasse 35, 8092 Zurich (Switzerland); Patsalas, Panos A. [Department of Physics, Laboratory of Applied Physics, Aristotle University of Thessaloniki, GR-54124 Thessaloniki (Greece)

    2015-03-02

    Indium oxide (In{sub 2}O{sub 3}) films were deposited by ultrasonic spray pyrolysis in ambient air and incorporated into bottom-gate coplanar and staggered thin-film transistors. As-fabricated devices exhibited electron-transporting characteristics with mobility values of 1 cm{sup 2}V{sup −1}s{sup −1} and 16 cm{sup 2}V{sup −1}s{sup −1} for coplanar and staggered architectures, respectively. Integration of In{sub 2}O{sub 3} transistors enabled realization of unipolar inverters with high gain (5.3 V/V) and low-voltage operation. The low temperature deposition (≤250 °C) of In{sub 2}O{sub 3} also allowed transistor fabrication on free-standing 50 μm-thick polyimide foils. The resulting flexible In{sub 2}O{sub 3} transistors exhibit good characteristics and remain fully functional even when bent to tensile radii of 4 mm.

  9. Fault Analysis in a Grid Integrated DFIG Based Wind Energy System with NA CB_P Circuit for Ridethrough Capability and Power Quality Improvement

    Science.gov (United States)

    Swain, Snehaprava; Ray, Pravat Kumar

    2016-12-01

    In this paper a three phase fault analysis is done on a DFIG based grid integrated wind energy system. A Novel Active Crowbar Protection (NACB_P) system is proposed to enhance the Fault-ride through (FRT) capability of DFIG both for symmetrical as well as unsymmetrical grid faults. Hence improves the power quality of the system. The protection scheme proposed here is designed with a capacitor in series with the resistor unlike the conventional Crowbar (CB) having only resistors. The major function of the capacitor in the protection circuit is to eliminate the ripples generated in the rotor current and to protect the converter as well as the DC-link capacitor. It also compensates reactive power required by the DFIG during fault. Due to these advantages the proposed scheme enhances the FRT capability of the DFIG and also improves the power quality of the whole system. Experimentally the fault analysis is done on a 3hp slip ring induction generator and simulation results are carried out on a 1.7 MVA DFIG based WECS under different types of grid faults in MATLAB/Simulation and functionality of the proposed scheme is verified.

  10. Study of Ni Metallization in Macroporous Si Using Wet Chemistry for Radio Frequency Cross-Talk Isolation in Mixed Signal Integrated Circuits

    Directory of Open Access Journals (Sweden)

    King-Ning Tu

    2011-05-01

    Full Text Available A highly conductive moat or Faraday cage of through-the-wafer thickness in Si substrate was proposed to be effective in shielding electromagnetic interference thereby reducing radio frequency (RF cross-talk in high performance mixed signal integrated circuits. Such a structure was realized by metallization of selected ultra-high-aspect-ratio macroporous regions that were electrochemically etched in p− Si substrates. The metallization process was conducted by means of wet chemistry in an alkaline aqueous solution containing Ni2+ without reducing agent. It is found that at elevated temperature during immersion, Ni2+ was rapidly reduced and deposited into macroporous Si and a conformal metallization of the macropore sidewalls was obtained in a way that the entire porous Si framework was converted to Ni. A conductive moat was as a result incorporated into p− Si substrate. The experimentally measured reduction of crosstalk in this structure is 5~18 dB at frequencies up to 35 GHz.

  11. A fully integrated, wide-load-range, high-power-conversion-efficiency switched capacitor DC-DC converter with adaptive bias comparator for ultra-low-power power management integrated circuit

    Science.gov (United States)

    Asano, Hiroki; Hirose, Tetsuya; Kojima, Yuta; Kuroki, Nobutaka; Numa, Masahiro

    2018-04-01

    In this paper, we present a wide-load-range switched-capacitor DC-DC buck converter with an adaptive bias comparator for ultra-low-power power management integrated circuit. The proposed converter is based on a conventional one and modified to operate in a wide load range by developing a load current monitor used in an adaptive bias comparator. Measurement results demonstrated that our proposed converter generates a 1.0 V output voltage from a 3.0 V input voltage at a load of up to 100 µA, which is 20 times higher than that of the conventional one. The power conversion efficiency was higher than 60% in the load range from 0.8 to 100 µA.

  12. Collective of mechatronics circuit

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1987-02-15

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  13. Collective of mechatronics circuit

    International Nuclear Information System (INIS)

    1987-02-01

    This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.

  14. LDRD Final Report - Investigations of the impact of the process integration of deposited magnetic films for magnetic memory technologies on radiation-hardened CMOS devices and circuits - LDRD Project (FY99)

    Energy Technology Data Exchange (ETDEWEB)

    MYERS,DAVID R.; JESSING,JEFFREY R.; SPAHN,OLGA B.; SHANEYFELT,MARTY R.

    2000-01-01

    This project represented a coordinated LLNL-SNL collaboration to investigate the feasibility of developing radiation-hardened magnetic non-volatile memories using giant magnetoresistance (GMR) materials. The intent of this limited-duration study was to investigate whether giant magnetoresistance (GMR) materials similar to those used for magnetic tunnel junctions (MTJs) were process compatible with functioning CMOS circuits. Sandia's work on this project demonstrated that deposition of GMR materials did not affect the operation nor the radiation hardness of Sandia's rad-hard CMOS technology, nor did the integration of GMR materials and exposure to ionizing radiation affect the magnetic properties of the GMR films. Thus, following deposition of GMR films on rad-hard integrated circuits, both the circuits and the films survived ionizing radiation levels consistent with DOE mission requirements. Furthermore, Sandia developed techniques to pattern deposited GMR films without degrading the completed integrated circuits upon which they were deposited. The present feasibility study demonstrated all the necessary processing elements to allow fabrication of the non-volatile memory elements onto an existing CMOS chip, and even allow the use of embedded (on-chip) non-volatile memories for system-on-a-chip applications, even in demanding radiation environments. However, funding agencies DTRA, AIM, and DARPA did not have any funds available to support the required follow-on technology development projects that would have been required to develop functioning prototype circuits, nor were such funds available from LDRD nor from other DOE program funds.

  15. Global optimization of digital circuits

    Science.gov (United States)

    Flandera, Richard

    1991-12-01

    This thesis was divided into two tasks. The first task involved developing a parser which could translate a behavioral specification in Very High-Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) into the format used by an existing digital circuit optimization tool, Boolean Reasoning In Scheme (BORIS). Since this tool is written in Scheme, a dialect of Lisp, the parser was also written in Scheme. The parser was implemented is Artez's modification of Earley's Algorithm. Additionally, a VHDL tokenizer was implemented in Scheme and a portion of the VHDL grammar was converted into the format which the parser uses. The second task was the incorporation of intermediate functions into BORIS. The existing BORIS contains a recursive optimization system that optimizes digital circuits by using circuit outputs as inputs into other circuits. Intermediate functions provide a greater selection of functions to be used as circuits inputs. Using both intermediate functions and output functions, the costs of the circuits in the test set were reduced by 43 percent. This is a 10 percent reduction when compared to the existing recursive optimization system. Incorporating intermediate functions into BORIS required the development of an intermediate-function generator and a set of control methods to keep the computation time from increasing exponentially.

  16. Testing Superconductor Logic Integrated Circuits

    NARCIS (Netherlands)

    Arun, A.J.; Kerkhoff, Hans G.

    2005-01-01

    Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these

  17. An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

    Science.gov (United States)

    Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

    2009-10-01

    State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

  18. Electronic logic circuits

    CERN Document Server

    Gibson, J

    2013-01-01

    Most branches of organizing utilize digital electronic systems. This book introduces the design of such systems using basic logic elements as the components. The material is presented in a straightforward manner suitable for students of electronic engineering and computer science. The book is also of use to engineers in related disciplines who require a clear introduction to logic circuits. This third edition has been revised to encompass the most recent advances in technology as well as the latest trends in components and notation. It includes a wide coverage of application specific integrate

  19. Analog circuit design designing dynamic circuit response

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.

  20. Co-Cultured Continuously Bioluminescent Human Cells as Bioreporters for the Detection of Prodrug Therapeutic Impact Pre- and Post-Metabolism

    Directory of Open Access Journals (Sweden)

    Tingting Xu

    2017-12-01

    Full Text Available Modern drug discovery workflows require assay systems capable of replicating the complex interactions of multiple tissue types, but that can still function under high throughput conditions. In this work, we evaluate the use of substrate-free autobioluminescence in human cell lines to support the performance of these assays with reduced economical and logistical restrictions relative to substrate-requiring bioluminescent reporter systems. The use of autobioluminescence was found to support assay functionality similar to existing luciferase reporter targets. The autobioluminescent assay format was observed to correlate strongly with general metabolic activity markers such as ATP content and the presence of reactive oxygen species, but not with secondary markers such as glutathione depletion. At the transcriptional level, autobioluminescent dynamics were most closely associated with expression of the CYP1A1 phase I detoxification pathway. These results suggest constitutively autobioluminescent cells can function as general metabolic activity bioreporters, while pairing expression of the autobioluminescent phenotype to detoxification pathway specific promoters could create more specific sensor systems.