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Sample records for asynchronous fpga resistant

  1. Burst-Mode Asynchronous Controllers on FPGA

    Directory of Open Access Journals (Sweden)

    Duarte L. Oliveira

    2008-01-01

    Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

  2. FPGA BASED ASYNCHRONOUS PIPELINED MB-OFDM UWB TRANSMITTER BACKEND MODULES

    Directory of Open Access Journals (Sweden)

    M. Santhi

    2010-03-01

    Full Text Available In this paper, a novel scheme is proposed which comprises the advantages of asynchronous pipelining techniques and the advantages of FPGAs for implementing a 200Mbps MB-OFDM UWB transmitter digital backend modules. In asynchronous pipelined system, registers are used as in synchronous system. But they are controlled by handshaking signals. Since FPGAs are rich in registers, design and implementation of asynchronous pipelined MBOFDM UWB transmitter on FPGA using four-phase bundled-data protocol is considered in this paper. Novel ideas have also been proposed for designing asynchronous OFDM using Modified Radix-24 SDF and asynchronous interleaver using two RAM banks. Implementation has been performed on ALTERA STRATIX II EP2S60F1020C4 FPGA and it is operating at a speed of 350MHz. It is assured that the proposed MB-OFDM UWB system can be made to work on STRATIX III device with the operating frequency of 528MHz in compliance to the ECMA-368 standard. The proposed scheme is also applicable for FPGA from other vendors and ASIC.

  3. A high level implementation and performance evaluation of level-I asynchronous cache on FPGA

    Directory of Open Access Journals (Sweden)

    Mansi Jhamb

    2017-07-01

    Full Text Available To bridge the ever-increasing performance gap between the processor and the main memory in a cost-effective manner, novel cache designs and implementations are indispensable. Cache is responsible for a major part of energy consumption (approx. 50% of processors. This paper presents a high level implementation of a micropipelined asynchronous architecture of L1 cache. Due to the fact that each cache memory implementation is time consuming and error-prone process, a synthesizable and a configurable model proves out to be of immense help as it aids in generating a range of caches in a reproducible and quick fashion. The micropipelined cache, implemented using C-Elements acts as a distributed message-passing system. The RTL cache model implemented in this paper, comprising of data and instruction caches has a wide array of configurable parameters. In addition to timing robustness our implementation has high average cache throughput and low latency. The implemented architecture comprises of two direct-mapped, write-through caches for data and instruction. The architecture is implemented in a Field Programmable Gate Array (FPGA chip using Very High Speed Integrated Circuit Hardware Description Language (VHSIC HDL along with advanced synthesis and place-and-route tools.

  4. Ultra - Low - Power Asynchronous Processor and FPGA Design using Straintronics Nanomagnets

    Science.gov (United States)

    2013-05-01

    i‐th filter BW  The  coefficients   are  generated  inside  the  controller.  The  architecture  avoids  multipliers  and  shares  the  coefficients ...illustrated  in  Fig  25  –b.  i)  The  E‐field  causes  a  strain  in  PZT   leading  to a deformation S =  .  ii) Strain gets  transformed  to  free NM.  iii... PZT  is a parallel place capacitance while MTJ  is a variable resistance. This  is shown  in Fig  26. Shape anisotropy and uniaxial crystalline

  5. Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance

    Directory of Open Access Journals (Sweden)

    Siva Kotipalli

    2014-01-01

    (SCA resistance. These designs are based on a delay-insensitive (DI logic paradigm known as null convention logic (NCL, which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches. To quantitatively verify such improvements, functional verification and WASSO (weighted average simultaneous switching output analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools. Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected. Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach.

  6. Efficient and side-channel resistant authenticated encryption of FPGA bitstreams

    DEFF Research Database (Denmark)

    Bogdanov, Andrey; Moradi, Amir; Yalcin, Tolga

    2013-01-01

    AE modes of operation with the same countermeasure. We conclude that the deployment of dedicated AE schemes such as ALE significantly facilitates the real-world efficiency and security of FPGA bitstream protection in practice: Not only our solution enables authenticated encryption for bitstream...... on low-cost FPGAs but it also aims to mitigate physical attacks which have been lately shown to undermine the security of the bitstream protection mechanisms in the field.......State-of-the-art solutions for FPGA bitstream protection rely on encryption and authentication of the bitstream to both ensure its confidentiality, thwarting unauthorized copying and reverse engineering, and prevent its unauthorized modification, maintaining a root of trust in the field. Adequate...

  7. FPGA design

    CERN Document Server

    Simpson, Philip

    2010-01-01

    This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

  8. The FPGA Pixel Array Detector

    International Nuclear Information System (INIS)

    Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

    2013-01-01

    A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

  9. Generalized Asynchronous Systems

    Directory of Open Access Journals (Sweden)

    E. S. Kudryashova

    2012-01-01

    Full Text Available The paper consider a mathematical model of a concurrent system, the special case of which is an asynchronous system. Distributed asynchronous automata are introduced here. It is proved that Petri nets and transition systems with independence can be considered as distributed asynchronous automata. Time distributed asynchronous automata are defined in a standard way by correspondence which relates events with time intervals. It is proved that the time distributed asynchronous automata generalize time Petri nets and asynchronous systems.

  10. High precision simple interpolation asynchronous FIFO based on ACEX1K30 for HIRFL-CSRe

    International Nuclear Information System (INIS)

    Li Guihua; Qiao Weimin; Jing Lan

    2008-01-01

    High precision simple interpolation asynchronous FIFO of HIRFL-CSRe was developed based on the ACEX1K30 FPGA in VHDL Hardware Description language. The FIFO runs in FPGA of DSP module of HIRFL-CSRe. The input data of FIFO is from DSP data bus and the output data is to DAC data bus. It's kernel adopts double buffer ping-pong mode and it can implement simple interpolation inside FPGA. The module can control out- put data time delay in 40 ns. The experimental results indicate that this module is practical and accurate to HIRFL-CSRe. (authors)

  11. Asynchronous LMS adaptive equalization

    NARCIS (Netherlands)

    Bergmans, J.W.M.; Lin, M.Y.; Modrie, D.; Otte, R.

    2005-01-01

    Digital data receivers often operate at a fixed sampling rate 1/Ts that is asynchronous to the baud rate 1/T. A digital equalizer that processes the incoming signal will also operate in the asynchronous clock domain. Existing adaptation techniques for this equalizer involve an error sequence ek that

  12. Synthesis and Investigation of Algorithm for Estimation of Active Stator Resistance of Asynchronous Motor with Fixed Rotor

    Directory of Open Access Journals (Sweden)

    D. S. Odnolko

    2012-01-01

    Full Text Available The paper proposes an algorithm for online identification of active stator resistance. Algorithm synthesis has been developed on the basis of a recursive least squares method. The problem has been solved for induction motor model defined in the stationary stator frame α–β-coordinating system. An analysis of negative factors deteriorating the identifier operation has been made in the paper. The analysis has revealed the following: measured signals are noisy due to quantization and differentiation; dynamic model of an induction motor provides only approximate presentation about actual processes in the electromagnetic system of the machine. The paper presents results of  a system simulation while applying the proposed algorithm that confirm the fact that the estimated value of the active stator resistance tends to a true value with high accuracy. The identification test assumes a fixed rotor and nominal parameters uncertainty, but the flexible structure of the algorithm allows to use it as  for single-phase excitation so for full-phase control of the induction motor with freely rotating motor.

  13. The Aeolian Asynchronous Generator

    Directory of Open Access Journals (Sweden)

    Ionel Dragomirescu

    2008-10-01

    Full Text Available The production of the electric energy with lower costs could be realized with the help of the aeolian electric central. In these centrals we can use the squirrel cage asynchronous generators, because these machines are the most safety in function and easy exploited. This work show the function analyzing of the asynchronous generator having on involving torque depending on the square wind speed, the air-density and on the construction of the wing spiral.

  14. Low latency asynchronous interface circuits

    Science.gov (United States)

    Sadowski, Greg

    2017-06-20

    In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

  15. Asynchronized synchronous machines

    CERN Document Server

    Botvinnik, M M

    1964-01-01

    Asynchronized Synchronous Machines focuses on the theoretical research on asynchronized synchronous (AS) machines, which are "hybrids” of synchronous and induction machines that can operate with slip. Topics covered in this book include the initial equations; vector diagram of an AS machine; regulation in cases of deviation from the law of full compensation; parameters of the excitation system; and schematic diagram of an excitation regulator. The possible applications of AS machines and its calculations in certain cases are also discussed. This publication is beneficial for students and indiv

  16. Asynchronous SAR ADC

    NARCIS (Netherlands)

    2011-01-01

    An asynchronous analog to digital convertor for converting an analog input signal into a digital output is presented. According to an embodiment, the analog to digital convertor comprises a clock input operable to receive an external clock signal having a clock period, a comparator operable to

  17. Data acquisition system for charge-division mechanism based on FPGA

    International Nuclear Information System (INIS)

    Yang Litao; Li Dongcang; Yang Lei; Wu Huaiyi; Qi Zhong

    2010-01-01

    Design a system of Peak value acquisition, data processing and data output for 4 channels nuclear signal at the same time by FPGA that base on the basic principle of position information readout for particle through Charger-division Mechanism. In view of the randomness of nuclear signal, so insert asynchronous FIFO in the system, which greatly improve the sampling rate of system. In the article has produced the conjunctive relation and inner circuit structure and give out simulation. From here, you can see the great power of FPGA which used in nuclear data acquisition and processing system. (authors)

  18. Multiparty Asynchronous Session Types

    DEFF Research Database (Denmark)

    Honda, Kohei; Yoshida, Nobuko; Carbone, Marco

    2016-01-01

    . This work extends the foregoing theories of binary session types to multiparty, asynchronous sessions, which often arise in practical communication-centered applications. Presented as a typed calculus for mobile processes, the theory introduces a new notion of types in which interactions involving multiple......Communication is a central elements in software development. As a potential typed foundation for structured communication-centered programming, session types have been studied over the past decade for a wide range of process calculi and programming languages, focusing on binary (two-party) sessions...... peers are directly abstracted as a global scenario. Global types retain the friendly type syntax of binary session types while specifying dependencies and capturing complex causal chains of multiparty asynchronous interactions. A global type plays the role of a shared agreement among communication peers...

  19. FPGA Vision Data Architecture

    Science.gov (United States)

    Morfopoulos, Arin C.; Pham, Thang D.

    2013-01-01

    JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

  20. From OO to FPGA :

    Energy Technology Data Exchange (ETDEWEB)

    Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

    2012-09-01

    Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

  1. FPGA programming using FX3

    CERN Document Server

    Calleja, Stefano

    2014-01-01

    An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

  2. Behavioral synthesis of asynchronous circuits

    DEFF Research Database (Denmark)

    Nielsen, Sune Fallgaard

    2005-01-01

    This thesis presents a method for behavioral synthesis of asynchronous circuits, which aims at providing a synthesis flow which uses and tranfers methods from synchronous circuits to asynchronous circuits. We move the synchronous behavioral synthesis abstraction into the asynchronous handshake...... is idle. This reduces unnecessary switching activity in the individual functional units and therefore the energy consumption of the entire circuit. A collection of behavioral synthesis algorithms have been developed allowing the designer to perform time and power constrained design space exploration...

  3. A low delay transmission method of multi-channel video based on FPGA

    Science.gov (United States)

    Fu, Weijian; Wei, Baozhi; Li, Xiaobin; Wang, Quan; Hu, Xiaofei

    2018-03-01

    In order to guarantee the fluency of multi-channel video transmission in video monitoring scenarios, we designed a kind of video format conversion method based on FPGA and its DMA scheduling for video data, reduces the overall video transmission delay.In order to sace the time in the conversion process, the parallel ability of FPGA is used to video format conversion. In order to improve the direct memory access (DMA) writing transmission rate of PCIe bus, a DMA scheduling method based on asynchronous command buffer is proposed. The experimental results show that this paper designs a low delay transmission method based on FPGA, which increases the DMA writing transmission rate by 34% compared with the existing method, and then the video overall delay is reduced to 23.6ms.

  4. Asynchronous Multiparty Computation

    DEFF Research Database (Denmark)

    Damgård, Ivan Bjerre; Geisler, Martin; Krøigaard, Mikkel

    2009-01-01

    guarantees termination if the adversary allows a preprocessing phase to terminate, in which no information is released. The communication complexity of this protocol is the same as that of a passively secure solution up to a constant factor. It is secure against an adaptive and active adversary corrupting...... less than n/3 players. We also present a software framework for implementation of asynchronous protocols called VIFF (Virtual Ideal Functionality Framework), which allows automatic parallelization of primitive operations such as secure multiplications, without having to resort to complicated...... multithreading. Benchmarking of a VIFF implementation of our protocol confirms that it is applicable to practical non-trivial secure computations....

  5. ASCERTAINMENT OF THE EQUIVALENT CIRCUIT PARAMETERS OF THE ASYNCHRONOUS MACHINE

    Directory of Open Access Journals (Sweden)

    V. S. Safaryan

    2015-01-01

    Full Text Available The article considers experimental and analytical determination of the asynchronous machine equivalent-circuit parameters with application of the reference data. Transient processes investigation of the asynchronous machines necessitates the equivalent circuit parameters (resistance impedance, inductances and coefficient of the stator-rotor contours mutual inductance that help form the transitory-process mathematical simulation model. The reference books do not provide those parameters; they instead give the rated ones (active power, voltage, slide, coefficient of performance and capacity coefficient as well as the ratio of starting and nominal currents and torques. The noted studies on the asynchronous machine equivalent-circuits parametrization fail to solve the problems ad finem or solve them with admissions. The paper presents experimental and analytical determinations of the asynchronous machine equivalent-circuit parameters: the experimental one based on the results of two measurements and the analytical one where the problem boils down to solving a system of nonlineal algebraic equations. The authors investigate the equivalent asynchronous machine input-resistance properties and adduce the dependence curvatures of the input-resistances on the slide. They present a symbolic model for analytical parameterization of the asynchronous machine equivalent-circuit that represents a system of nonlineal equations and requires one of the rotor-parameters arbitrary assignment. The article demonstrates that for the asynchronous machine equivalent-circuit experimental parameterization the measures are to be conducted of the stator-circuit voltage, current and active power with two different slides and arbitrary assignment of one of the rotor parameters. The paper substantiates the fact that additional measurement does not discard the rotor-parameter choice arbitrariness. The authors establish that in motoring mode there is a critical slide by which the

  6. Flexible experimental FPGA based platform

    DEFF Research Database (Denmark)

    Andersen, Karsten Holm; Nymand, Morten

    2016-01-01

    This paper presents an experimental flexible Field Programmable Gate Array (FPGA) based platform for testing and verifying digital controlled dc-dc converters. The platform supports different types of control strategies, dc-dc converter topologies and switching frequencies. The controller platform...... interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...

  7. Pro asynchronous programming with .NET

    CERN Document Server

    Blewett, Richard; Ltd, Rock Solid Knowledge

    2014-01-01

    Pro Asynchronous Programming with .NET teaches the essential skill of asynchronous programming in .NET. It answers critical questions in .NET application development, such as: how do I keep my program responding at all times to keep my users happy how do I make the most of the available hardware how can I improve performanceIn the modern world, users expect more and more from their applications and devices, and multi-core hardware has the potential to provide it. But it takes carefully crafted code to turn that potential into responsive, scalable applications.With Pro Asynchronous Programming

  8. FPGA-Based Sonar Processing

    National Research Council Canada - National Science Library

    Graham, Paul; Nelson, Brent

    1998-01-01

    This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays...

  9. Exploration of Heterogeneous FPGA Architectures

    Directory of Open Access Journals (Sweden)

    Umer Farooq

    2011-01-01

    mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

  10. Asynchronous design of Networks-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2007-01-01

    -synchronous, mesochronous, globally-asynchronous locally-synchronous and fully asynchronous), discusses the circuitry needed to implement these timing methodologies, and provides some implementation details for a couple of asynchronous NoCs designed at the Technical University of Denmark (DTU). The paper is written...... to support an invited talk at the NORCHIP’2007 conference....

  11. Computational Aspects of Asynchronous CA

    OpenAIRE

    Chandesris, Jérôme; Dennunzio, Alberto; Formenti, Enrico; Manzoni, Luca

    2011-01-01

    This work studies some aspects of the computational power of fully asynchronous cellular automata (ACA). We deal with some notions of simulation between ACA and Turing Machines. In particular, we characterize the updating sequences specifying which are "universal", i.e., allowing a (specific family of) ACA to simulate any TM on any input. We also consider the computational cost of such simulations.

  12. Asynchronous control for networked systems

    CERN Document Server

    Rubio, Francisco; Bencomo, Sebastián

    2015-01-01

    This book sheds light on networked control systems; it describes different techniques for asynchronous control, moving away from the periodic actions of classical control, replacing them with state-based decisions and reducing the frequency with which communication between subsystems is required. The text focuses specially on event-based control. Split into two parts, Asynchronous Control for Networked Systems begins by addressing the problems of single-loop networked control systems, laying out various solutions which include two alternative model-based control schemes (anticipatory and predictive) and the use of H2/H∞ robust control to deal with network delays and packet losses. Results on self-triggering and send-on-delta sampling are presented to reduce the need for feedback in the loop. In Part II, the authors present solutions for distributed estimation and control. They deal first with reliable networks and then extend their results to scenarios in which delays and packet losses may occur. The novel ...

  13. Developing asynchronous online interprofessional education.

    Science.gov (United States)

    Sanborn, Heidi

    2016-09-01

    For many health programmes, developing interprofessional education (IPE) has been a challenge. Evidence on the best method for design and implementation of IPE has been slow to emerge, with little research on how to best incorporate IPE in the asynchronous online learning environment. This leaves online programmes with no clear guidance when embarking upon an initiative to integrate IPE into the curriculum. One tool that can be effective at guiding the incorporation of IPE across all learning platforms is the Interprofessional Education Collaborative (IPEC) competencies. A project was designed to integrate the nationally defined IPEC competencies throughout an asynchronous, online baccalaureate nursing completion programme. A programme-wide review led to targeted revision of course and unit-level objectives, learning experiences, and assessments based on the IPEC framework. As a result of this effort, the programme curriculum now provides interprofessional learning activities across all courses. This report provides a method for using the IPEC competencies to incorporate IPE within various asynchronous learning assessments, assuring students learn about, with, and from other professions.

  14. EPOS for Coordination of Asynchronous Sensor Webs

    Data.gov (United States)

    National Aeronautics and Space Administration — Develop, integrate, and deploy software-based tools to coordinate asynchronous, distributed missions and optimize observation planning spanning simultaneous...

  15. The MCD circuit based on FPGA

    International Nuclear Information System (INIS)

    Vu Quoc Trong

    2003-01-01

    Two MCD circuits based on different FPGA are presented as results of the study of the MAX+PLUS II software and FPGA devices. An external memory like 62256 and programmed EPM7064S will be able to form a MCD with 8 kilo channels. (NHA)

  16. An Asynchronous Multi-Sensor Micro Control Unit for Wireless Body Sensor Networks (WBSNs

    Directory of Open Access Journals (Sweden)

    Ching-Hsing Luo

    2011-07-01

    Full Text Available In this work, an asynchronous multi-sensor micro control unit (MCU core is proposed for wireless body sensor networks (WBSNs. It consists of asynchronous interfaces, a power management unit, a multi-sensor controller, a data encoder (DE, and an error correct coder (ECC. To improve the system performance and expansion abilities, the asynchronous interface is created for handshaking different clock domains between ADC and RF with MCU. To increase the use time of the WBSN system, a power management technique is developed for reducing power consumption. In addition, the multi-sensor controller is designed for detecting various biomedical signals. To prevent loss error from wireless transmission, use of an error correct coding technique is important in biomedical applications. The data encoder is added for lossless compression of various biomedical signals with a compression ratio of almost three. This design is successfully tested on a FPGA board. The VLSI architecture of this work contains 2.68-K gate counts and consumes power 496-μW at 133-MHz processing rate by using TSMC 0.13-μm CMOS process. Compared with the previous techniques, this work offers higher performance, more functions, and lower hardware cost than other micro controller designs.

  17. Asynchronous communication in real space process algebra

    NARCIS (Netherlands)

    Baeten, J.C.M.; Bergstra, J.A.

    1991-01-01

    A version of classical real space process algebra is given in which messages travel with constant speed through a three-dimensional medium. It follows that communication is asynchronous and has a broadcasting character. A state operator is used to describe asynchronous message transfer and a

  18. Asynchronous communication in real space process algebra

    NARCIS (Netherlands)

    Bergstra, J.A.; Baeten, J.C.M.

    1992-01-01

    A version of classical real space process algebra is given in which messages travel with constant speed through a three-dimensional medium. It follows that communication is asynchronous and has a broadcasting character. A state operator is used to describe asynchronous message transfer and a

  19. Asynchronous zero-forcing adaptive equalization

    NARCIS (Netherlands)

    Bergmans, J.W.M.; Pozidis, H.; Lin, M.Y.

    2005-01-01

    Digital data receivers often operate at a fixed sampling rate 1/Ts that is asynchronous to the baud rate 1/T. A digital equalizer that processes the incoming signal will also be asynchronous, and its adaptation is commonly based on extensions of the LMS algorithm. In this paper, we develop and

  20. Dynamic modeling of an asynchronous squirrel-cage machine; Modelisation dynamique d'une machine asynchrone a cage

    Energy Technology Data Exchange (ETDEWEB)

    Guerette, D.

    2009-07-01

    This document presented a detailed mathematical explanation and validation of the steps leading to the development of an asynchronous squirrel-cage machine. The MatLab/Simulink software was used to model a wind turbine at variable high speeds. The asynchronous squirrel-cage machine is an electromechanical system coupled to a magnetic circuit. The resulting electromagnetic circuit can be represented as a set of resistances, leakage inductances and mutual inductances. Different models were used for a comparison study, including the Munteanu, Boldea, Wind Turbine Blockset, and SimPowerSystem. MatLab/Simulink modeling results were in good agreement with the results from other comparable models. Simulation results were in good agreement with analytical calculations. 6 refs, 2 tabs, 9 figs.

  1. Autonomous Lawnmower using FPGA implementation.

    Science.gov (United States)

    Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

    2016-11-01

    Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

  2. Understanding and Optimizing Asynchronous Low-Precision Stochastic Gradient Descent

    Science.gov (United States)

    De Sa, Christopher; Feldman, Matthew; Ré, Christopher; Olukotun, Kunle

    2018-01-01

    Stochastic gradient descent (SGD) is one of the most popular numerical algorithms used in machine learning and other domains. Since this is likely to continue for the foreseeable future, it is important to study techniques that can make it run fast on parallel hardware. In this paper, we provide the first analysis of a technique called Buckwild! that uses both asynchronous execution and low-precision computation. We introduce the DMGC model, the first conceptualization of the parameter space that exists when implementing low-precision SGD, and show that it provides a way to both classify these algorithms and model their performance. We leverage this insight to propose and analyze techniques to improve the speed of low-precision SGD. First, we propose software optimizations that can increase throughput on existing CPUs by up to 11×. Second, we propose architectural changes, including a new cache technique we call an obstinate cache, that increase throughput beyond the limits of current-generation hardware. We also implement and analyze low-precision SGD on the FPGA, which is a promising alternative to the CPU for future SGD systems. PMID:29391770

  3. Multichannel analyzer embedded in FPGA; Analizador multicanal embebido en FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98060 Zacatecas, Zac. (Mexico); Ordaz G, O. O. [Universidad de Cordoba, Departamento de Arquitectura de Computadores, Electronica y Tecnologia Electronica, Campus de Rabanales, Ctra. N-IVa Km 396, 14071 Cordoba (Spain); Bravo M, I., E-mail: angelogarciad@hotmail.com [Universidad de Alcala de Henares, Departamento de Electronica, Campus Universitario, Carretera Madrid-Barcelona Km 33.600, 28801 Alcala de Henares, Madrid (Spain)

    2017-10-15

    Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

  4. Multichannel analyzer embedded in FPGA

    International Nuclear Information System (INIS)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R.; Ordaz G, O. O.; Bravo M, I.

    2017-10-01

    Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

  5. Irradiation test of FPGA for BES III

    International Nuclear Information System (INIS)

    Chen Yixin; Liang Hao; Xue Jundong; Liu Baoying; Liu Qiang; Yu Xiaoqi; Zhou Yongzhao; Hou Long

    2005-01-01

    The irradiation effect of FPGA, applied in Front-end Electronics for experiments of High-Energy Physics, is a serious problem. The performance of FPGA, used in the front-end card of Muon Counters of BES III project, needs to be evaluated under irradiation. SEUs on Altera ACEX 1K FPGA, observed in the experiment under the irradiation of γ ray, 14 and 2.5 MeV neutrons, was investigated. The authors calculated involved cross-section and provided reasonable analysis and evaluation for the result of the experiment. The conclusion about feasibility of applying ACEX 1K FPGA in the front-end card of the readout system of Muon Counters for BES III was given. (authors)

  6. Commande adaptive d'une machine asynchrone

    Science.gov (United States)

    Slama-Belkhodja, I.; de Fornel, B.

    1996-06-01

    The paper deals with an indirect self-tuning speed control for an induction motor supplied by a chopper-filter-inverter system. Input/Output models are identified with the recursive least squares algorithm and the controller adaptation is based on a pole assignement strategy. Emphasis is put on the evaluation of the parameter identification in order to avoid instabilities because of disturbances or insufficient excitations. This is especially of importance when the adaptive control is carried out in closed loop systems and without additional test signals. Simulation results show the improvement of the dynamic responses and the robustness against load variations or parameters variations (rotor resistance, inertia). Cat article décrit une stratégie de commande adaptive indirecte à Placement de Pôles (PP), appliquée à la commande en vitesse d'une machine asynchrone alimentée par un ensemble hacheur-filtre-onduleur de tension. L'algorithme des Moindres Carrés Récursifs (MCR) est utilisé pour l'identification des modèles de comportement type entrées/sorties. Un intérêt particulier est porté à la mise en oeuvre de cet algorithme et à la discussion de ses résultats, tenant compte des erreurs de modélisation et de la nature peu riche en excitations des entrées du processus. Différents régimes transitoires ont été simulés pour apprécier l'apport de cette association (MCR-PP) : démarrages et inversion des sens de rotation, à vide et en charges, applications d'échelons de couple résistant, variations paramétriques. Les résultats permettent d'illustrer, tant au niveau des performances que de la robustesse, l'apport d'une telle commande adaptive pour des entraînements électriques avec une machine asynchrone.

  7. Algorithmic strategies for FPGA-based vision

    OpenAIRE

    Lim, Yoong Kang

    2016-01-01

    As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms...

  8. Protection and Control with FPGA technology

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-03-15

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

  9. Protection and Control with FPGA technology

    International Nuclear Information System (INIS)

    Sohn, K. Y.; Yi, W. J.; Koo, I. S.

    2012-01-01

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper

  10. Tethered Forth system for FPGA applications

    Science.gov (United States)

    Goździkowski, Paweł; Zabołotny, Wojciech M.

    2013-10-01

    This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

  11. Asynchronous Parallelization of a CFD Solver

    OpenAIRE

    Abdi, Daniel S.; Bitsuamlak, Girma T.

    2015-01-01

    The article of record as published may be found at http://dx.doi.org/10.1155/2015/295393 A Navier-Stokes equations solver is parallelized to run on a cluster of computers using the domain decomposition method. Two approaches of communication and computation are investigated, namely, synchronous and asynchronous methods. Asynchronous communication between subdomains is not commonly used inCFDcodes; however, it has a potential to alleviate scaling bottlenecks incurred due to process...

  12. Asynchronous networks: modularization of dynamics theorem

    Science.gov (United States)

    Bick, Christian; Field, Michael

    2017-02-01

    Building on the first part of this paper, we develop the theory of functional asynchronous networks. We show that a large class of functional asynchronous networks can be (uniquely) represented as feedforward networks connecting events or dynamical modules. For these networks we can give a complete description of the network function in terms of the function of the events comprising the network: the modularization of dynamics theorem. We give examples to illustrate the main results.

  13. Asynchronous communication in real space process algebra

    OpenAIRE

    Baeten, JCM Jos; Bergstra, JA Jan

    1990-01-01

    A version of classical real space process algebra is given in which messages travel with constant speed through a three-dimensional medium. It follows that communication is asynchronous and has a broadcasting character. A state operator is used to describe asynchronous message transfer and a priority mechanism allows to express the broadcasting mechanism. As an application, a protocol is specified in which the receiver moves with respect to the sender.

  14. Synchronous and Asynchronous ATM Multiplexor Properties Comparsion

    OpenAIRE

    Jan Zabka

    2006-01-01

    The article is aimed to ATM multiplexor computer model utilisation. Based on simulation runs we try to review aspects of use a synchronous and asynchronous ATM multiplexors. ATM multiplexor is the input queuing model with three inputs. Synchronous multiplexor works without an input priority. Multiplexor inputs are served periodically. Asynchronous multiplexor model supports several queuing and priority mechanisms. CLR and CTD are basic performance parameters. Input cell flows are genera...

  15. Fault tolerance based on serial communication of FPGA

    International Nuclear Information System (INIS)

    Peng Jing; Fang Zongliang; Xu Quanzhou; Hu Jiewei; Ma Guizhen

    2012-01-01

    There maybe appear mistake in serial communication. This paper was described the intellectual detector of γ dose ratemeter communication with FPGA. The software of FPGA designed the code about fault tolerance, prevented mistake effectively. (authors)

  16. Computer vision camera with embedded FPGA processing

    Science.gov (United States)

    Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

    2000-03-01

    Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

  17. FPGA based Smart Wireless MIMO Control System

    International Nuclear Information System (INIS)

    Ali, Syed M Usman; Hussain, Sajid; Siddiqui, Ali Akber; Arshad, Jawad Ali; Darakhshan, Anjum

    2013-01-01

    In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input and Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively

  18. FPGA controlled artificial vascular system

    Directory of Open Access Journals (Sweden)

    Laqua D.

    2015-09-01

    Full Text Available Monitoring the oxygen saturation of an unborn child is an invasive procedure, so far. Transabdominal fetal pulse oximetry is a promising method under research, used to estimate the oxygen saturation of a fetus noninvasively. Due to the nature of the method, the fetal information needs to be extracted from a mixed signal. To properly evaluate signal processing algorithms, a phantom modeling fetal and maternal blood circuits and tissue layers is necessary. This paper presents an improved hardware concept for an artificial vascular system, utilizing an FPGA based CompactRIO System from National Instruments. The experimental model to simulate the maternal and fetal blood pressure curve consists of two identical hydraulic circuits. Each of these circuits consists of a pre-pressure system and an artificial vascular system. Pulse curves are generated by proportional valves, separating these two systems. The dilation of the fetal and maternal artificial vessels in tissue substitutes is measured by transmissive and reflective photoplethysmography. The measurement results from the pressure sensors and the transmissive optical sensors are visualized to show the functionality of the pulse generating systems. The trigger frequency for the maternal valve was set to 1 per second, the fetal valve was actuated at 0.7 per second for validation. The reflective curve, capturing pulsations of the fetal and maternal circuit, was obtained with a high power LED (905 nm as light source. The results show that the system generates pulse curves, similar to its physiological equivalent. Further, the acquired reflective optical signal is modulated by the alternating diameter of the tubes of both circuits, allowing for tests of signal processing algorithms.

  19. FPGA Implementation of the stepwise shutdown system

    Energy Technology Data Exchange (ETDEWEB)

    Lotjonen, L.

    2012-07-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and stanfards can be used to some extent but the hardware aspects bring new challenges that cannot be tacled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation processfrom the reguirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  20. FPGA Implementation of the stepwise shutdown system

    International Nuclear Information System (INIS)

    Lotjonen, L.

    2012-01-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and standards can be used to some extent but the hardware aspects bring new challenges that cannot be tackled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation process from the requirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  1. Multichannel FPGA-Based Data-Acquisition-System for Time-Resolved Synchrotron Radiation Experiments

    Science.gov (United States)

    Choe, Hyeokmin; Gorfman, Semen; Heidbrink, Stefan; Pietsch, Ullrich; Vogt, Marco; Winter, Jens; Ziolkowski, Michael

    2017-06-01

    The aim of this contribution is to describe our recent development of a novel compact field-programmable gatearray (FPGA)-based data acquisition (DAQ) system for use with multichannel X-ray detectors at synchrotron radiation facilities. The system is designed for time resolved counting of single photons arriving from several-currently 12-independent detector channels simultaneously. Detector signals of at least 2.8 ns duration are latched by asynchronous logic and then synchronized with the system clock of 100 MHz. The incoming signals are subsequently sorted out into 10 000 time-bins where they are counted. This occurs according to the arrival time of photons with respect to the trigger signal. Repeatable mode of triggered operation is used to achieve high statistic of accumulated counts. The time-bin width is adjustable from 10 ns to 1 ms. In addition, a special mode of operation with 2 ns time resolution is provided for two detector channels. The system is implemented in a pocketsize FPGA-based hardware of 10 cm × 10 cm × 3 cm and thus can easily be transported between synchrotron radiation facilities. For setup of operation and data read-out, the hardware is connected via USB interface to a portable control computer. DAQ applications are provided in both LabVIEW and MATLAB environments.

  2. Asynchronous decentralized method for interconnected electricity markets

    International Nuclear Information System (INIS)

    Huang, Anni; Joo, Sung-Kwan; Song, Kyung-Bin; Kim, Jin-Ho; Lee, Kisung

    2008-01-01

    This paper presents an asynchronous decentralized method to solve the optimization problem of interconnected electricity markets. The proposed method decomposes the optimization problem of combined electricity markets into individual optimization problems. The impact of neighboring markets' information is included in the objective function of the individual market optimization problem by the standard Lagrangian relaxation method. Most decentralized optimization methods use synchronous models of communication to exchange updated market information among markets during the iterative process. In this paper, however, the solutions of the individual optimization problems are coordinated through an asynchronous communication model until they converge to the global optimal solution of combined markets. Numerical examples are presented to demonstrate the advantages of the proposed asynchronous method over the existing synchronous methods. (author)

  3. CCS, locations and asynchronous transition systems

    DEFF Research Database (Denmark)

    Mukund, Madhavan; Nielsen, Mogens

    1992-01-01

    We provide a simple non-interleaved operational semantics for CCS in terms of asynchronous transition systems. We identify the concurrency present in the system in a natural way, in terms of events occurring at independent locations in the system. We extend the standard interleaving transition...... system for CCS by introducing labels on the transitions with information about the locations of events. We then show that the resulting transition system is an asynchronous transition system which has the additional property of being elementary, which means that it can also be represented by a 1-safe net....... We also introduce a notion of bisimulation on asynchronous transition systems which preserves independence. We conjecture that the induced equivalence on CCS processes coincides with the notion of location equivalence proposed by Boudol et al....

  4. Asynchronous Message Service Reference Implementation

    Science.gov (United States)

    Burleigh, Scott C.

    2011-01-01

    This software provides a library of middleware functions with a simple application programming interface, enabling implementation of distributed applications in conformance with the CCSDS AMS (Consultative Committee for Space Data Systems Asynchronous Message Service) specification. The AMS service, and its protocols, implement an architectural concept under which the modules of mission systems may be designed as if they were to operate in isolation, each one producing and consuming mission information without explicit awareness of which other modules are currently operating. Communication relationships among such modules are self-configuring; this tends to minimize complexity in the development and operations of modular data systems. A system built on this model is a society of generally autonomous, inter-operating modules that may fluctuate freely over time in response to changing mission objectives, modules functional upgrades, and recovery from individual module failure. The purpose of AMS, then, is to reduce mission cost and risk by providing standard, reusable infrastructure for the exchange of information among data system modules in a manner that is simple to use, highly automated, flexible, robust, scalable, and efficient. The implementation is designed to spawn multiple threads of AMS functionality under the control of an AMS application program. These threads enable all members of an AMS-based, distributed application to discover one another in real time, subscribe to messages on specific topics, and to publish messages on specific topics. The query/reply (client/server) communication model is also supported. Message exchange is optionally subject to encryption (to support confidentiality) and authorization. Fault tolerance measures in the discovery protocol minimize the likelihood of overall application failure due to any single operational error anywhere in the system. The multi-threaded design simplifies processing while enabling application nodes to

  5. Central FPGA-based destination and load control in the LHCb MHz event readout

    Science.gov (United States)

    Jacobsson, R.

    2012-10-01

    The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

  6. Central FPGA-based destination and load control in the LHCb MHz event readout

    International Nuclear Information System (INIS)

    Jacobsson, R.

    2012-01-01

    The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

  7. An Overview of the Asynchronous Digital Systems – Part 3

    Directory of Open Access Journals (Sweden)

    Mihai Timis

    2008-01-01

    Full Text Available Implementation methods for the digital asynchronous systems use different predefined models like self timed circuits, speed independent circuits, delay insensitive circuits, handshake protocol implementation in asynchronous systems,C Muller circuits.

  8. An Overview of the Asynchronous Digital Systems – Part 2

    Directory of Open Access Journals (Sweden)

    Mihai Timis

    2008-01-01

    Full Text Available Implementation methods for the digital asynchronous systems use different predefined models like self timed circuits, speed independent circuits, delay insensitive circuits, handshake protocol implementation in asynchronous systems,C Muller circuits.

  9. Interpolation algorithm for asynchronous ADC-data

    Directory of Open Access Journals (Sweden)

    S. Bramburger

    2017-09-01

    Full Text Available This paper presents a modified interpolation algorithm for signals with variable data rate from asynchronous ADCs. The Adaptive weights Conjugate gradient Toeplitz matrix (ACT algorithm is extended to operate with a continuous data stream. An additional preprocessing of data with constant and linear sections and a weighted overlap of step-by-step into spectral domain transformed signals improve the reconstruction of the asycnhronous ADC signal. The interpolation method can be used if asynchronous ADC data is fed into synchronous digital signal processing.

  10. Handbook of asynchronous machines with variable speed

    CERN Document Server

    Razik, Hubert

    2013-01-01

    This handbook deals with the asynchronous machine in its close environment. It was born from a reflection on this electromagnetic converter whose integration in industrial environments takes a wide part. Previously this type of motor operated at fixed speed, from now on it has been integrated more and more in processes at variable speed. For this reason it seemed useful, or necessary, to write a handbook on the various aspects from the motor in itself, via the control and while finishing by the diagnosis aspect. Indeed, an asynchronous motor is used nowadays in industry where variation speed a

  11. Asynchronous Operators of Sequential Logic Venjunction & Sequention

    CERN Document Server

    Vasyukevich, Vadim

    2011-01-01

    This book is dedicated to new mathematical instruments assigned for logical modeling of the memory of digital devices. The case in point is logic-dynamical operation named venjunction and venjunctive function as well as sequention and sequentional function. Venjunction and sequention operate within the framework of sequential logic. In a form of the corresponding equations, they organically fit analytical expressions of Boolean algebra. Thus, a sort of symbiosis is formed using elements of asynchronous sequential logic on the one hand and combinational logic on the other hand. So, asynchronous

  12. FPGA Design and Verification Procedure for Nuclear Power Plant MMIS

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Dongil; Yoo, Kawnwoo; Ryoo, Kwangki [Hanbat National Univ., Daejeon (Korea, Republic of)

    2013-05-15

    In this paper, it is shown that it is possible to ensure reliability by performing the steps of the verification based on the FPGA development methodology, to ensure the safety of application to the NPP MMIS of the FPGA run along the step. Currently, the PLC (Programmable Logic Controller) which is being developed is composed of the FPGA (Field Programmable Gate Array) and CPU (Central Processing Unit). As the importance of the FPGA in the NPP (Nuclear Power Plant) MMIS (Man-Machine Interface System) has been increasing than before, the research on the verification of the FPGA has being more and more concentrated recently.

  13. OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently...

  14. Qualification of FPGA-Based Safety-Related PRM System

    International Nuclear Information System (INIS)

    Miyazaki, Tadashi; Oda, Naotaka; Goto, Yasushi; Hayashi, Toshifumi

    2011-01-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of basic logic circuits, and FPGA performs defined processing which is configured by connecting the basic logic circuit inside the FPGA. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Neutron Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development process to the other safety-related systems such as RPS from now on. Toshiba developed a special design process for NRW-FPGA-based safety-related I and C systems. The design process resolves issues for many years regarding testability of the digital system for nuclear safety application. Thus, Toshiba NRW-FPGA-based safety-related I and C systems has much advantage to be a would standard of the digital systems for nuclear safety application. (author)

  15. FPGA Realization of Memory 10 Viterbi Decoder

    DEFF Research Database (Denmark)

    Paaske, Erik; Bach, Thomas Bo; Andersen, Jakob Dahl

    1997-01-01

    sequence mode when feedback from the Reed-Solomon decoder is available. The Viterbi decoder is realized using two Altera FLEX 10K50 FPGA's. The overall operating speed is 30 kbit/s, and since up to three iterations are performed for each frame and only one decoder is used, the operating speed...

  16. Prototyping Advanced Control Systems on FPGA

    Directory of Open Access Journals (Sweden)

    Simard Stéphane

    2009-01-01

    Full Text Available In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs promise to supplant older technologies, such as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing. The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC's MEMS prototyping platform, now used by several Canadian laboratories.

  17. Increasing Student Engagement Using Asynchronous Learning

    Science.gov (United States)

    Northey, Gavin; Bucic, Tania; Chylinski, Mathew; Govind, Rahul

    2015-01-01

    Student engagement is an ongoing concern for educators because of its positive association with deep learning and educational outcomes. This article tests the use of a social networking site (Facebook) as a tool to facilitate asynchronous learning opportunities that complement face-to-face interactions and thereby enable a stronger learning…

  18. Basic Algorithms for the Asynchronous Reconfigurable Mesh

    Directory of Open Access Journals (Sweden)

    Yosi Ben-Asher

    2002-01-01

    Full Text Available Many constant time algorithms for various problems have been developed for the reconfigurable mesh (RM in the past decade. All these algorithms are designed to work with synchronous execution, with no regard for the fact that large size RMs will probably be asynchronous. A similar observation about the PRAM model motivated many researchers to develop algorithms and complexity measures for the asynchronous PRAM (APRAM. In this work, we show how to define the asynchronous reconfigurable mesh (ARM and how to measure the complexity of asynchronous algorithms executed on it. We show that connecting all processors in a row of an n×n ARM (the analog of barrier synchronization in the APRAM model can be solved with complexity Θ(nlog⁡n. Intuitively, this is average work time for solving such a problem. Next, we describe general a technique for simulating T -step synchronous RM algorithms on the ARM with complexity of Θ(T⋅n2log⁡n. Finally, we consider the simulation of the classical synchronous algorithm for counting the number of non-zero bits in an n bits vector using (k

  19. Emphasis on the Impact of Asynchronous Media

    African Journals Online (AJOL)

    ICTs and their utilization is one of the most pertinent issues in the education industry today. ... The paper pointed out specific impact of asynchronous ICT media in ... The paper finally noted that the struggle to be part of the digital world is ...

  20. Asynchronous versus Synchronous Learning in Pharmacy Education

    Science.gov (United States)

    Motycka, Carol A.; St. Onge, Erin L.; Williams, Jennifer

    2013-01-01

    Objective: To better understand the technology being used today in pharmacy education through a review of the current methodologies being employed at various institutions. Also, to discuss the benefits and difficulties of asynchronous and synchronous methodologies, which are being utilized at both traditional and distance education campuses.…

  1. Adaptive hatching hypotheses do not explain asynchronous ...

    African Journals Online (AJOL)

    At the core of the suite of adaptive hatching hypotheses advanced to explain asynchronous hatching in birds is the assumption that if food is not limited then all the hatchlings will develop normally to adulthood. In this study Brown-headed Parrot Poicephalus cryptoxanthus chicks were hand fed and weighed on a daily basis.

  2. Dynamic Performances of Asynchronous Machines | Ubeku ...

    African Journals Online (AJOL)

    The per-phase parameters of a 1.5 hp, 380 V, 50 Hz, 4 poles, 3 phase asynchronous machine used in the simulation were computed with reading obtained from a dc, no-load and blocked rotor tests carried out on the machine in the laboratory. The results obtained from the computer simulations confirmed the capabilities ...

  3. Asynchronous stream processing with S-Net

    NARCIS (Netherlands)

    Grelck, C.; Scholz, S.-B.; Shafarenko, A.

    2010-01-01

    We present the rationale and design of S-Net, a coordination language for asynchronous stream processing. The language achieves a near-complete separation between the application code, written in any conventional programming language, and the coordination/communication code written in S-Net. Our

  4. Commercial FPGA based multipurpose controller: implementation perspective

    International Nuclear Information System (INIS)

    Arredondo, I.; Campo, M. del; Echevarria, P.; Belver, D.; Muguira, L.; Garmendia, N.; Hassanzadegan, H.; Eguiraun, M.; Jugo, J.; Etxebarria, V.

    2012-01-01

    This work presents a fast acquisition multipurpose controller, focussing on its EPICS integration and on its XML based configuration. This controller is based on a Lyrtech VHS-ADC board which encloses an FPGA, connected to a Host PC. This Host acts as local controller and implements an IOC integrating the device in an EPICS network. These tasks have been performed using Java as the main tool to program the PC to make the device fit the desired application. All the process includes the use of different technologies: JNA to handle C functions i.e. FPGA API, JavaIOC to integrate EPICS and XML w3c DOM classes to easily configure the particular application. In order to manage the functions, Java specific tools have been developed: Methods to manage the FPGA (read/write registers, acquire data,...), methods to create and use the EPICS server (put, get, monitor,...), mathematical methods to process the data (numeric format conversions,...) and methods to create/ initialize the application structure by means of an XML file (parse elements, build the DOM and the specific application structure). This XML file has some common nodes and tags for all the applications: FPGA registers specifications definition and EPICS variables. This means that the user only has to include a node for the specific application and use the mentioned tools. A main class is in charge of managing the FPGA and EPICS server according to this XML file. This multipurpose controller has been successfully used to implement a BPM and an LLRF application for the ESS-Bilbao (European Spallation Source) facility. (authors)

  5. Fast FPGA Implementation of an Original Impedance Analyser

    Directory of Open Access Journals (Sweden)

    Abdulrahman HAMED

    2011-02-01

    Full Text Available This article describes in detail the design and rapid prototyping of an embedded impedance analyzer. The measurement principle is based on the feedback control of the excitation voltage VD during a fast frequency sweeping. This function is carried out by a high precision synthesizer whose output resistance RG is digitally adjustable. Real and imaginary parts of the dipole impedance are determined from RG and the phase of VD. The digital architecture design uses the hardware-in-the-loop simulation in which the dipole is modeled using an RLC parallel circuit and a Butterworth Van Dyke structure. All digital functions are implemented on a Stratix II FPGA board with a 100 MHz frequency clock. The parameters taken into account are the frequency range (0 to 5 MHz, speed and resolution of the analysis and the quality factor of the resonant dipole. To reduce the analysis duration, the frequency sweeping rate is adjusted in real time.

  6. An FPGA-based torus communication network

    Energy Technology Data Exchange (ETDEWEB)

    Pivanti, Marcello; Schifano, Sebastiano Fabio [INFN, Ferrara (Italy); Ferrara Univ. (Italy); Simma, Hubert [DESY, Zeuthen (Germany). John von Neumann-Institut fuer Computing NIC

    2011-02-15

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  7. Moessbauer spectrometric data acquisition based on FPGA

    International Nuclear Information System (INIS)

    Zhang Yuan; Li Shimin; Chen Nan; Zhu Jingbo; Xia Yuanfu

    2008-01-01

    FPGA(Field Programmable Gate Array) is a programmable device with strong logical function and timing control ability. It is extremely potent in acquiring and processing timing signals. By replacing the traditional used SCM (Single-Chip Microcomputer) with FPGA, counting speed of Moessbauer spectrometric data acquisition can be improved markedly with significantly decreased size of the spectrometer. The counter, RAM and RS-232 communication of the module are developed on Altera Cyclone series chip EP1C6T144C8 with Quartus II. EP1C6T144C8 has 5980 logical units accompanied by 92160 bits of memory space. It is so powerful that all needs in data acquisition of the Moessbauer spectrometer can be perfectly satisfied while allowing modifications in functions and parameters. (authors)

  8. An Improved Rotary Interpolation Based on FPGA

    Directory of Open Access Journals (Sweden)

    Mingyu Gao

    2014-08-01

    Full Text Available This paper presents an improved rotary interpolation algorithm, which consists of a standard curve interpolation module and a rotary process module. Compared to the conventional rotary interpolation algorithms, the proposed rotary interpolation algorithm is simpler and more efficient. The proposed algorithm was realized on a FPGA with Verilog HDL language, and simulated by the ModelSim software, and finally verified on a two-axis CNC lathe, which uses rotary ellipse and rotary parabolic as an example. According to the theoretical analysis and practical process validation, the algorithm has the following advantages: firstly, less arithmetic items is conducive for interpolation operation; and secondly the computing time is only two clock cycles of the FPGA. Simulations and actual tests have proved that the high accuracy and efficiency of the algorithm, which shows that it is highly suited for real-time applications.

  9. An FPGA-based torus communication network

    International Nuclear Information System (INIS)

    Pivanti, Marcello; Schifano, Sebastiano Fabio; Simma, Hubert

    2011-02-01

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  10. An FPGA-Based Electronic Cochlea

    Directory of Open Access Journals (Sweden)

    M. P. Leong

    2003-06-01

    Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

  11. Guide to FPGA Implementation of Arithmetic Functions

    CERN Document Server

    Deschamps, Jean-Pierre; Cantó, Enrique

    2012-01-01

    This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components.  The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption.  This is not a book on algorithms.  It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others.  Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

  12. Aspects of computation on asynchronous parallel processors

    International Nuclear Information System (INIS)

    Wright, M.

    1989-01-01

    The increasing availability of asynchronous parallel processors has provided opportunities for original and useful work in scientific computing. However, the field of parallel computing is still in a highly volatile state, and researchers display a wide range of opinion about many fundamental questions such as models of parallelism, approaches for detecting and analyzing parallelism of algorithms, and tools that allow software developers and users to make effective use of diverse forms of complex hardware. This volume collects the work of researchers specializing in different aspects of parallel computing, who met to discuss the framework and the mechanics of numerical computing. The far-reaching impact of high-performance asynchronous systems is reflected in the wide variety of topics, which include scientific applications (e.g. linear algebra, lattice gauge simulation, ordinary and partial differential equations), models of parallelism, parallel language features, task scheduling, automatic parallelization techniques, tools for algorithm development in parallel environments, and system design issues

  13. Asynchronous Gossip for Averaging and Spectral Ranking

    Science.gov (United States)

    Borkar, Vivek S.; Makhijani, Rahul; Sundaresan, Rajesh

    2014-08-01

    We consider two variants of the classical gossip algorithm. The first variant is a version of asynchronous stochastic approximation. We highlight a fundamental difficulty associated with the classical asynchronous gossip scheme, viz., that it may not converge to a desired average, and suggest an alternative scheme based on reinforcement learning that has guaranteed convergence to the desired average. We then discuss a potential application to a wireless network setting with simultaneous link activation constraints. The second variant is a gossip algorithm for distributed computation of the Perron-Frobenius eigenvector of a nonnegative matrix. While the first variant draws upon a reinforcement learning algorithm for an average cost controlled Markov decision problem, the second variant draws upon a reinforcement learning algorithm for risk-sensitive control. We then discuss potential applications of the second variant to ranking schemes, reputation networks, and principal component analysis.

  14. Computing by Temporal Order: Asynchronous Cellular Automata

    Directory of Open Access Journals (Sweden)

    Michael Vielhaber

    2012-08-01

    Full Text Available Our concern is the behaviour of the elementary cellular automata with state set 0,1 over the cell set Z/nZ (one-dimensional finite wrap-around case, under all possible update rules (asynchronicity. Over the torus Z/nZ (n<= 11,we will see that the ECA with Wolfram rule 57 maps any v in F_2^n to any w in F_2^n, varying the update rule. We furthermore show that all even (element of the alternating group bijective functions on the set F_2^n = 0,...,2^n-1, can be computed by ECA57, by iterating it a sufficient number of times with varying update rules, at least for n <= 10. We characterize the non-bijective functions computable by asynchronous rules.

  15. Adaptive Hardware Cryptography Engine Based on FPGA

    International Nuclear Information System (INIS)

    Afify, M.A.A.

    2011-01-01

    In the last two decades, with spread of the real time applications over public networks or communications the need for information security become more important but with very high speed for data processing, to keep up with the real time applications requirements, that is the reason for using FPGA as an implementation platform for the proposed cryptography engine. Hence in this thesis a new S-Box design has been demonstrated and implemented, there is a comparison for the simulation results for proposed S-Box simulation results with respect to different designs for S-Box in DES, Two fish and Rijndael algorithms and another comparison among proposed S-Box with different sizes. The proposed S-Box implemented with 32-bits Input data lines and compared with different designs in the encryption algorithms with the same input lines, the proposed S-Box gives implementation results for the maximum frequency 120 MHz but the DES S-Box gives 34 MHz and Rijndael gives 71 MHz, on the other hand the proposed design gives the best implementation area, hence it gives 50 Configurable logic Block CLB but DES gives 88 CLB. The proposed S-Box implemented in different sizes 64-bits, 128-bits, and 256-bits for input data lines. The implementation carried out by using UniDAq PCI card with FPGA Chip XCV 800, synthesizing carried out for all designs by using Leonardo spectrum and simulation carried out by using model sim simulator program form the FPGA advantage package. Finally the results evaluation and verifications carried out using the UniDAq FPGA PCI card with chip XCV 800. Different cases study have been implemented, data encryption, images encryption, voice encryption, and video encryption. A prototype for Remote Monitoring Control System has been implemented. Finally the proposed design for S-Box has a significant achievement in maximum frequency, implementation area, and encryption strength.

  16. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  17. FPGA Flash Memory High Speed Data Acquisition

    Science.gov (United States)

    Gonzalez, April

    2013-01-01

    The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

  18. Signal compression in radar using FPGA

    OpenAIRE

    Escamilla Hemández, Enrique; Kravchenko, Víctor; Ponomaryov, Volodymyr; Duchen Sánchez, Gonzalo; Hernández Sánchez, David

    2010-01-01

    We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of sidelobes. The proposed architecture expl...

  19. An FPGA-based reconfigurable DDC algorithm

    Science.gov (United States)

    Juszczyk, B.; Kasprowicz, G.

    2016-09-01

    This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

  20. FPGA Implementation of Computer Vision Algorithm

    OpenAIRE

    Zhou, Zhonghua

    2014-01-01

    Computer vision algorithms, which play an significant role in vision processing, is widely applied in many aspects such as geology survey, traffic management and medical care, etc.. Most of the situations require the process to be real-timed, in other words, as fast as possible. Field Programmable Gate Arrays (FPGAs) have a advantage of parallelism fabric in programming, comparing to the serial communications of CPUs, which makes FPGA a perfect platform for implementing vision algorithms. The...

  1. FPGA remote update for nuclear environments

    Energy Technology Data Exchange (ETDEWEB)

    Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno [Instituto de Plasmasbe Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentacao, Dept. de Fisica, Universidade de Coimbra, 3004-516 Coimbra, (Portugal)

    2015-07-01

    The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

  2. FPGA communications based on Gigabit Ethernet

    International Nuclear Information System (INIS)

    Doolittle, L.R.; Serrano, C.

    2012-01-01

    The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and reasonable costs. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip and board-independent FPGA design which implements the Gigabit Ethernet (GbE) standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer. (authors)

  3. FPGA Implementation of Heart Rate Monitoring System.

    Science.gov (United States)

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

  4. Blending Online Asynchronous and Synchronous Learning

    Directory of Open Access Journals (Sweden)

    Lisa C. Yamagata-Lynch

    2014-04-01

    Full Text Available In this article I will share a qualitative self-study about a 15-week blended 100% online graduate level course facilitated through synchronous meetings on Blackboard Collaborate and asynchronous discussions on Blackboard. I taught the course at the University of Tennessee (UT during the spring 2012 semester and the course topic was online learning environments. The primary research question of this study was: How can the designer/instructor optimize learning experiences for students who are studying about online learning environments in a blended online course relying on both synchronous and asynchronous technologies? I relied on student reflections of course activities during the beginning, middle, and the end of the semester as the primary data source to obtain their insights regarding course experiences. Through the experiences involved in designing and teaching the course and engaging in this study I found that there is room in the instructional technology research community to address strategies for facilitating online synchronous learning that complement asynchronous learning. Synchronous online whole class meetings and well-structured small group meetings can help students feel a stronger sense of connection to their peers and instructor and stay engaged with course activities. In order to provide meaningful learning spaces in synchronous learning environments, the instructor/designer needs to balance the tension between embracing the flexibility that the online space affords to users and designing deliberate structures that will help them take advantage of the flexible space.

  5. An FPGA-based bolometer for the MAST-U Super-X divertor

    Energy Technology Data Exchange (ETDEWEB)

    Lovell, Jack, E-mail: jack.lovell@durham.ac.uk [Durham University, South Road, Durham DH1 3LE (United Kingdom); Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Naylor, Graham; Field, Anthony [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Drewelow, Peter [MPI für Plasmaphysik, Greifswald (Germany); Sharples, Ray [Durham University, South Road, Durham DH1 3LE (United Kingdom); Collaboration: EUROfusion Consortium, JET, Culham Science Centre, Abingdon OX14 3DB (United Kingdom)

    2016-11-15

    A new resistive bolometer system has been developed for MAST-Upgrade. It will measure radiated power in the new Super-X divertor, with millisecond time resolution, along 16 vertical and 16 horizontal lines of sight. The system uses a Xilinx Zynq-7000 series Field-Programmable Gate Array (FPGA) in the D-TACQ ACQ2106 carrier to perform real time data acquisition and signal processing. The FPGA enables AC-synchronous detection using high performance digital filtering to achieve a high signal-to-noise ratio and will be able to output processed data in real time with millisecond latency. The system has been installed on 8 previously unused channels of the JET vertical bolometer system. Initial results suggest good agreement with data from existing vertical channels but with higher bandwidth and signal-to-noise ratio.

  6. Comparing the force ripple during asynchronous and conventional stimulation.

    Science.gov (United States)

    Downey, Ryan J; Tate, Mark; Kawai, Hiroyuki; Dixon, Warren E

    2014-10-01

    Asynchronous stimulation has been shown to reduce fatigue during electrical stimulation; however, it may also exhibit a force ripple. We quantified the ripple during asynchronous and conventional single-channel transcutaneous stimulation across a range of stimulation frequencies. The ripple was measured during 5 asynchronous stimulation protocols, 2 conventional stimulation protocols, and 3 volitional contractions in 12 healthy individuals. Conventional 40 Hz and asynchronous 16 Hz stimulation were found to induce contractions that were as smooth as volitional contractions. Asynchronous 8, 10, and 12 Hz stimulation induced contractions with significant ripple. Lower stimulation frequencies can reduce fatigue; however, they may also lead to increased ripple. Future efforts should study the relationship between force ripple and the smoothness of the evoked movements in addition to the relationship between stimulation frequency and NMES-induced fatigue to elucidate an optimal stimulation frequency for asynchronous stimulation. © 2014 Wiley Periodicals, Inc.

  7. Current Trends in High-Level Synthesis of Asynchronous Circuits

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2009-01-01

    This paper is a survey paper presenting what the author sees as two major and promising trends in the current research in CAD-tools and design-methods for asynchronous circuits. One branch of research builds on top of existing asynchronous CAD-tools that perform syntax directed translation, e...... a conventional synchronous circuit as the starting point, and then adds some form of handshake-based flow-control. One approach keeps the global clock and implements discrete-time asynchronous operation. Another approach substitutes the clocked registers by asynchronous handshake-registers, thus creating truly...

  8. FPGA based Control of a Production Cell System

    NARCIS (Netherlands)

    Groothuis, M.A.; van Zuijlen, Jasper J.P.; Broenink, Johannes F.

    Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control

  9. Automatic generation of application specific FPGA multicore accelerators

    DEFF Research Database (Denmark)

    Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

    2014-01-01

    High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

  10. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    -the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs....

  11. Pass-transistor asynchronous sequential circuits

    Science.gov (United States)

    Whitaker, Sterling R.; Maki, Gary K.

    1989-01-01

    Design methods for asynchronous sequential pass-transistor circuits, which result in circuits that are hazard- and critical-race-free and which have added degrees of freedom for the input signals, are discussed. The design procedures are straightforward and easy to implement. Two single-transition-time state assignment methods are presented, and hardware bounds for each are established. A surprising result is that the hardware realizations for each next state variable and output variable is identical for a given flow table. Thus, a state machine with N states and M outputs can be constructed using a single layout replicated N + M times.

  12. Massive Asynchronous Parallelization of Sparse Matrix Factorizations

    Energy Technology Data Exchange (ETDEWEB)

    Chow, Edmond [Georgia Inst. of Technology, Atlanta, GA (United States)

    2018-01-08

    Solving sparse problems is at the core of many DOE computational science applications. We focus on the challenge of developing sparse algorithms that can fully exploit the parallelism in extreme-scale computing systems, in particular systems with massive numbers of cores per node. Our approach is to express a sparse matrix factorization as a large number of bilinear constraint equations, and then solving these equations via an asynchronous iterative method. The unknowns in these equations are the matrix entries of the factorization that is desired.

  13. Hyperchaotic Chameleon: Fractional Order FPGA Implementation

    Directory of Open Access Journals (Sweden)

    Karthikeyan Rajagopal

    2017-01-01

    Full Text Available There are many recent investigations on chaotic hidden attractors although hyperchaotic hidden attractor systems and their relationships have been less investigated. In this paper, we introduce a hyperchaotic system which can change between hidden attractor and self-excited attractor depending on the values of parameters. Dynamic properties of these systems are investigated. Fractional order models of these systems are derived and their bifurcation with fractional orders is discussed. Field programmable gate array (FPGA implementations of the systems with their power and resource utilization are presented.

  14. Superconducting cavity driving with FPGA controller

    International Nuclear Information System (INIS)

    Czarski, Tomasz; Koprek, Waldemar; Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Simrock, Stefan; Brandt, Alexander; Chase, Brian; Carcagno, Ruben; Cancelo, Gustavo; Koeth, Timothy W.

    2006-01-01

    A digital control of superconducting cavities for a linear accelerator is presented. FPGA-based controller, supported by Matlab system, was applied. Electrical model of a resonator was used for design of a control system. Calibration of the signal path is considered. Identification of cavity parameters has been carried out for adaptive control algorithm. Feed-forward and feedback modes were applied in operating the cavities. Required performance has been achieved; i.e. driving on resonance during filling and field stabilization during flattop time, while keeping reasonable level of the power consumption. Representative results of the experiments are presented for different levels of the cavity field gradient

  15. Spacewire Routers Implemented with FPGA Technology

    Science.gov (United States)

    Habinc, Sandi; Isomaki, Marko

    2011-08-01

    Routers are an integral part of SpaceWire networks. Aeroflex Gaisler has developed a highly configurable SpaceWire router VHDL IP core to meet the needs for technology independent router designs. The main design goals have been configurability, technology independence, support of the standard and expandability. The IP core being technologically independent allows it to be used in both ASIC and FPGA technology. The latter is now being used to produce versatile standard products that can reach the market faster than for example an ASIC based product.

  16. Signal compression in radar using FPGA

    OpenAIRE

    Enrique Escamilla Hemández; Víctor Kravchenko; Volodymyr Ponomaryov; Gonzalo Duchen Sánchez; David Hernández Sánchez

    2010-01-01

    El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array). El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR). El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde n...

  17. MODELING AND INVESTIGATION OF ASYNCHRONOUS TWO-MACHINE SYSTEM MODES

    Directory of Open Access Journals (Sweden)

    V. S. Safaryan

    2014-01-01

    Full Text Available The paper considers stationary and transient processes of an asynchronous two-machine system. A mathematical model for investigation of stationary and transient modes, static characteristics and research results of dynamic process pertaining to starting-up the asynchronous two-machine system has been given in paper.

  18. Two Studies Examining Argumentation in Asynchronous Computer Mediated Communication

    Science.gov (United States)

    Joiner, Richard; Jones, Sarah; Doherty, John

    2008-01-01

    Asynchronous computer mediated communication (CMC) would seem to be an ideal medium for supporting development in student argumentation. This paper investigates this assumption through two studies. The first study compared asynchronous CMC with face-to-face discussions. The transactional and strategic level of the argumentation (i.e. measures of…

  19. Designing Asynchronous Circuits for Low Power: An IFIR Filter

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Sparsø, Jens

    1999-01-01

    This paper addresses the design of asynchronous circuits for low power through an example: a filter bank for a digital hearing aid. The asynchronous design re-implements an existing synchronous circuit which is used in a commercial product. For comparison, both designs have been fabricated...

  20. Evaluation of discrete modeling efficiency of asynchronous electric machines

    OpenAIRE

    Byczkowska-Lipińska, Liliana; Stakhiv, Petro; Hoholyuk, Oksana; Vasylchyshyn, Ivanna

    2011-01-01

    In the paper the problem of effective mathematical macromodels in the form of state variables intended for asynchronous motor transient analysis is considered. Their comparing with traditional mathematical models of asynchronous motors including models built into MATLAB/Simulink software was carried out and analysis of their efficiency was conducted.

  1. Asynchronous Learning Sources in a High-Tech Organization

    Science.gov (United States)

    Bouhnik, Dan; Giat, Yahel; Sanderovitch, Yafit

    2009-01-01

    Purpose: The purpose of this study is to characterize learning from asynchronous sources among research and development (R&D) personnel. It aims to examine four aspects of asynchronous source learning: employee preferences regarding self-learning; extent of source usage; employee satisfaction with these sources and the effect of the sources on the…

  2. Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum

    Science.gov (United States)

    Smith, S. C.; Al-Assadi, W. K.; Di, J.

    2010-01-01

    As demand increases for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used in the semiconductor industry, as evidenced by the International Technology Roadmap for Semiconductors' (ITRS) prediction of a likely shift from synchronous to asynchronous design…

  3. Localized radio frequency communication using asynchronous transfer mode protocol

    Science.gov (United States)

    Witzke, Edward L.; Robertson, Perry J.; Pierson, Lyndon G.

    2007-08-14

    A localized wireless communication system for communication between a plurality of circuit boards, and between electronic components on the circuit boards. Transceivers are located on each circuit board and electronic component. The transceivers communicate with one another over spread spectrum radio frequencies. An asynchronous transfer mode protocol controls communication flow with asynchronous transfer mode switches located on the circuit boards.

  4. The Determination of the Asynchronous Traction Motor Characteristics of Locomotive

    Directory of Open Access Journals (Sweden)

    Pavel Grigorievich Kolpakhchyan

    2017-01-01

    Full Text Available The article deals with the problem of the locomotive asynchronous traction motor control with the AC diesel-electric transmission. The limitations of the torque of the traction motor when powered by the inverter are determined. The recommendations to improve the use of asynchronous traction motor of locomotives with the AC diesel-electric transmission are given.

  5. Exploring Asynchronous and Synchronous Tool Use in Online Courses

    Science.gov (United States)

    Oztok, Murat; Zingaro, Daniel; Brett, Clare; Hewitt, Jim

    2013-01-01

    While the independent contributions of synchronous and asynchronous interaction in online learning are clear, comparatively less is known about the pedagogical consequences of using both modes in the same environment. In this study, we examine relationships between students' use of asynchronous discussion forums and synchronous private messages…

  6. Asynchronous and Synchronous Online Discussion: Real and Perceived Achievement Differences

    Science.gov (United States)

    Johnson, Genevieve Marie; Buck, George H.

    2007-01-01

    Students in an introductory educational psychology course used two WebCT communication tools (synchronous chat and asynchronous discussion) to discuss four case studies. In response to the item, "I learned the case studies best when using," 39 students selected synchronous chat and 51 students selected asynchronous discussion. Students who…

  7. Regression analysis of sparse asynchronous longitudinal data.

    Science.gov (United States)

    Cao, Hongyuan; Zeng, Donglin; Fine, Jason P

    2015-09-01

    We consider estimation of regression models for sparse asynchronous longitudinal observations, where time-dependent responses and covariates are observed intermittently within subjects. Unlike with synchronous data, where the response and covariates are observed at the same time point, with asynchronous data, the observation times are mismatched. Simple kernel-weighted estimating equations are proposed for generalized linear models with either time invariant or time-dependent coefficients under smoothness assumptions for the covariate processes which are similar to those for synchronous data. For models with either time invariant or time-dependent coefficients, the estimators are consistent and asymptotically normal but converge at slower rates than those achieved with synchronous data. Simulation studies evidence that the methods perform well with realistic sample sizes and may be superior to a naive application of methods for synchronous data based on an ad hoc last value carried forward approach. The practical utility of the methods is illustrated on data from a study on human immunodeficiency virus.

  8. Asynchronous schemes for CFD at extreme scales

    Science.gov (United States)

    Konduri, Aditya; Donzis, Diego

    2013-11-01

    Recent advances in computing hardware and software have made simulations an indispensable research tool in understanding fluid flow phenomena in complex conditions at great detail. Due to the nonlinear nature of the governing NS equations, simulations of high Re turbulent flows are computationally very expensive and demand for extreme levels of parallelism. Current large simulations are being done on hundreds of thousands of processing elements (PEs). Benchmarks from these simulations show that communication between PEs take a substantial amount of time, overwhelming the compute time, resulting in substantial waste in compute cycles as PEs remain idle. We investigate a novel approach based on widely used finite-difference schemes in which computations are carried out asynchronously, i.e. synchronization of data among PEs is not enforced and computations proceed regardless of the status of messages. This drastically reduces PE idle time and results in much larger computation rates. We show that while these schemes remain stable, their accuracy is significantly affected. We present new schemes that maintain accuracy under asynchronous conditions and provide a viable path towards exascale computing. Performance of these schemes will be shown for simple models like Burgers' equation.

  9. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  10. Superconducting cavity driving with FPGA controller

    Energy Technology Data Exchange (ETDEWEB)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland); Simrock, S.; Brand, A. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany); Chase, B.; Carcagno, R.; Cancelo, G. [Fermi National Accelerator Lab., Batavia, IL (United States); Koeth, T.W. [Rutgers - the State Univ. of New Jersey, NJ (United States)

    2006-07-01

    The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

  11. Control de acceso usando FPGA y RFID

    Directory of Open Access Journals (Sweden)

    Dora Luz Almanza Ojeda

    2012-10-01

    Full Text Available Este trabajo presenta el diseño e implementación de un sistema de control de acceso mediante Identificación por Radiofrecuencia (RFID, Radio Frequency Identification controlado por una Matriz de compuertas programables (FPGA, Field Programmable Gate Array. El sistema está constituido por un par de dispositivos de adquisición de radiofrecuencia, una FPGA, un juego de etiquetas y tarjetas pasivas de identificación. Mediante una interfaz gráfica de usuario es posible controlar todo movimiento dentro de una zona determinada, desde los accesos hasta la disponibilidad de equipo; utilizando los dispositivos de adquisición de radiofrecuencia se puede acceder a la información de los usuarios autorizados, así como al control del equipo. Con este sistema es posible monitorear, administrar y reportar todo acceso de personal, movimiento de equipo o plagio de manera eficiente y evitando un gran número de errores humanos.  

  12. An FPGA-Based People Detection System

    Directory of Open Access Journals (Sweden)

    James J. Clark

    2005-05-01

    Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

  13. High performance parallel backprojection on FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Pfanner, Florian; Knaup, Michael; Kachelriess, Marc [Erlangen-Nuernberg Univ., Erlangen (Germany). Inst. of Medical Physics (IMP)

    2011-07-01

    Reconstruction of tomographic images, i.e., images from a Computed Tomography scanner, is a very time consuming issue. The most calculation power is needed for the backprojection step. A closer inspection shows that the algorithm for backprojection is easy to parallelize. FPGAs are able to execute many operations in the same time, so a highly parallel algorithm is a requirement for a powerful acceleration. For data flow rate maximization, we realized the backprojection in a pipelined structure with data throughput of one clock cycle. Due the hardware limitations of the FPGA, it is not possible to reconstruct the image as a whole. So it is necessary to split up the image and reconstruct these parts separately. Despite that, a reconstruction of 512 projections into a 5122 image is calculated within 13 ms on a Virtex 5 FPGA. To save hardware resources we use fixed point arithmetic with an accuracy of 23 bit for calculation. A comparison of the result image and an image, calculated with floating point arithmetic on CPU, shows that there are no differences between these images. (orig.)

  14. Signal compression in radar using FPGA

    Directory of Open Access Journals (Sweden)

    Enrique Escamilla Hemández

    2010-01-01

    Full Text Available El presente artículo muestra la puesta en práctica de hardware para realizar el procesamiento en tiempo real de la señal de radar usando una técnica simple, rápida basada en arquitectura de FPGA (Field Programmable Gate Array. El proceso incluye diversos procedimientos de enventanado durante la compresión del pulso del radar de apertura sintética (SAR. El proceso de compresión de la señal de radar se hace con un filtro acoplado. que aplica funciones clásicas y nuevas de enventanado, donde nos centramos en obtener una mejor atenuación para los valores de lóbulos laterales. La arquitectura propuesta explota los recursos de computación paralela de los dispositivos FPGA para alcanzar una mejor velocidad de cómputo. Las investigaciones experimentales han demostrado que los mejores resultados para el funcionamiento de la compresión del pulso se han obtenido usando las funciones atómicas, mejorando el funcionamiento del sistema del radar en presencia de ruido, y consiguiendo una pequeña degradación en la resolución de rango. La puesta en práctica del tratamiento de señales en el sistema de radar en tiempo real se discute y se justifica la eficiencia de la arquitectura de hardware propuesta.

  15. Superconducting cavity driving with FPGA controller

    International Nuclear Information System (INIS)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S.; Simrock, S.; Brand, A.; Chase, B.; Carcagno, R.; Cancelo, G.; Koeth, T.W.

    2006-01-01

    The digital control of several superconducting cavities for a linear accelerator is presented. The laboratory setup of the CHECHIA cavity and ACC1 module of the VU-FEL TTF in DESY-Hamburg have both been driven by a Field Programmable Gate Array (FPGA) based system. Additionally, a single 9-cell TESLA Superconducting cavity of the FNPL Photo Injector at FERMILAB has been remotely controlled from WUT-ISE laboratory with the support of the DESY team using the same FPGA control system. These experiments focused attention on the general recognition of the cavity features and projected control methods. An electrical model of the resonator was taken as a starting point. Calibration of the signal path is considered key in preparation for the efficient driving of a cavity. Identification of the resonator parameters has been proven to be a successful approach in achieving required performance; i.e. driving on resonance during filling and field stabilization during flattop time while requiring reasonable levels of power consumption. Feed-forward and feedback modes were successfully applied in operating the cavities. Representative results of the experiments are presented for different levels of the cavity field gradient. (orig.)

  16. Automated Metabolic P System Placement in FPGA

    Directory of Open Access Journals (Sweden)

    Kulakovskis Darius

    2016-07-01

    Full Text Available An original Very High Speed Integrated Circuit Hardware Description Language (VHDL code generation tool that can be used to automate Metabolic P (MP system implementation in hardware such as Field Programmable Gate Arrays (FPGA is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT, and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP, slice, and 4-input LUT usage.

  17. FPGA-Based Embedded Motion Estimation Sensor

    Directory of Open Access Journals (Sweden)

    Zhaoyi Wei

    2008-01-01

    Full Text Available Accurate real-time motion estimation is very critical to many computer vision tasks. However, because of its computational power and processing speed requirements, it is rarely used for real-time applications, especially for micro unmanned vehicles. In our previous work, a FPGA system was built to process optical flow vectors of 64 frames of 640×480 image per second. Compared to software-based algorithms, this system achieved much higher frame rate but marginal accuracy. In this paper, a more accurate optical flow algorithm is proposed. Temporal smoothing is incorporated in the hardware structure which significantly improves the algorithm accuracy. To accommodate temporal smoothing, the hardware structure is composed of two parts: the derivative (DER module produces intermediate results and the optical flow computation (OFC module calculates the final optical flow vectors. Software running on a built-in processor on the FPGA chip is used in the design to direct the data flow and manage hardware components. This new design has been implemented on a compact, low power, high performance hardware platform for micro UV applications. It is able to process 15 frames of 640×480 image per second and with much improved accuracy. Higher frame rate can be achieved with further optimization and additional memory space.

  18. An improved real time superresolution FPGA system

    Science.gov (United States)

    Lakshmi Narasimha, Pramod; Mudigoudar, Basavaraj; Yue, Zhanfeng; Topiwala, Pankaj

    2009-05-01

    In numerous computer vision applications, enhancing the quality and resolution of captured video can be critical. Acquired video is often grainy and low quality due to motion, transmission bottlenecks, etc. Postprocessing can enhance it. Superresolution greatly decreases camera jitter to deliver a smooth, stabilized, high quality video. In this paper, we extend previous work on a real-time superresolution application implemented in ASIC/FPGA hardware. A gradient based technique is used to register the frames at the sub-pixel level. Once we get the high resolution grid, we use an improved regularization technique in which the image is iteratively modified by applying back-projection to get a sharp and undistorted image. The algorithm was first tested in software and migrated to hardware, to achieve 320x240 -> 1280x960, about 30 fps, a stunning superresolution by 16X in total pixels. Various input parameters, such as size of input image, enlarging factor and the number of nearest neighbors, can be tuned conveniently by the user. We use a maximum word size of 32 bits to implement the algorithm in Matlab Simulink as well as in FPGA hardware, which gives us a fine balance between the number of bits and performance. The proposed system is robust and highly efficient. We have shown the performance improvement of the hardware superresolution over the software version (C code).

  19. FPGA Design Methodologies Applicable to Nuclear Power Plants

    International Nuclear Information System (INIS)

    Kwong, Yongil; Jeong, Choongheui

    2013-01-01

    In order to solve the above problem, NPPs in some countries such as the US, Canada and Japan have already applied FPGA-based equipment which has advantages as follows: It is easier to verify the performance because it needs only HDL code to configure logic circuits without other software, compared to microprocessor-based equipment, It is much cheaper than ASIC in a small quantity, Its logic circuits are re configurable, It has enough resources like logic blocks and memory blocks to implement I and C functions, Multiple functions can be implemented in a FPGA chip, It is stronger with respect to carboy security than microprocessor-based equipment because its configuration cannot be changed by external access, It is simple to replace it with new one when it is obsolete, Its power consumption is lower. However, FPGA-based equipment does not have only the merits. There are some issues on its application to NPPs. First of all, the experiences in applying it to NPPs are much less than to other industries, and international standards or guidelines are also very few. And there is the small number of FPGA platforms for I and C systems. Finally, the specific guidelines on FPGA design are required because the design has both hardware and software characteristics. In order to handle the above issues, KINS(Korea Institute of Nuclear Safety) built a test platform last year and have developed regulatory guidelines for FPGA-application in NPPs. I and C systems of NPPs have been increasingly using FPGA-based equipment as an alternative of microprocessor-based equipment which is not simple to be evaluated for safety due to its complexity. This paper explained the FPGA design flow and design guidelines. Those methodologies can be used as the guidelines on FPGA verification for safety of I and C systems

  20. Fpga As A Part Of Ms Windows Control Environment

    Directory of Open Access Journals (Sweden)

    Krzysztof Kołek

    2007-01-01

    Full Text Available The attention is focused on the Windows operating system (OS used as a control and measurementenvironment. Windows OS due to extensions becomes a real-time OS (RTOS.Benefits and drawbacks of typical software extensions are compared. As far as hardwaresolutions are concerned the field programmable gate arrays FPGA technology is proposed toensure fast time-critical operations. FPGA-based parallel execution and hardware implementationof the data processing algorithms significantly outperform the classical microprocessoroperating modes. Suitability of the RTOS for a particular application and FPGA hardwaremaintenance is studied.

  1. Long-distance configuration of FPGA based on serial communication

    International Nuclear Information System (INIS)

    Liu Xiang; Song Kezhu; Zhang Sifeng

    2010-01-01

    To solve FPGA configuration in some nuclear electronics, which works in radioactivity environment, the article introduces a way of long-distance configuration with PC and CPLD, based on serial communication. Taking CYCLONE series FPGA and EPCS configuration chip from ALTERA for example, and using the AS configuration mode, we described our design from the aspects of basic theory, hardware connection, software function and communication protocol. With this design, we could configure several FPGAs in the distance of 100 meters, or we could configure on FPGA in the distance of 150 meters. (authors)

  2. Central FPGA-based Destination and Load Control in the LHCb MHz Event Readout

    CERN Document Server

    Jacobsson, Richard

    2012-01-01

    The readout strategy of the LHCb experiment [1] is based on complete event readout at 1 MHz [2]. Over 300 sub-detector readout boards transmit event fragments at 1 MHz over a commercial 70 Gigabyte/s switching network to a distributed event building and trigger processing farm with 1470 individual multi-core computer nodes [3]. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a powerful non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. A high-speed FPGA-based central master module controls the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load balancing and trigger rate regulation as a function of the global farm load. It also ...

  3. Asynchronous and corrected-asynchronous numerical solutions of parabolic PDES on MIMD multiprocessors

    Science.gov (United States)

    Amitai, Dganit; Averbuch, Amir; Itzikowitz, Samuel; Turkel, Eli

    1991-01-01

    A major problem in achieving significant speed-up on parallel machines is the overhead involved with synchronizing the concurrent process. Removing the synchronization constraint has the potential of speeding up the computation. The authors present asynchronous (AS) and corrected-asynchronous (CA) finite difference schemes for the multi-dimensional heat equation. Although the discussion concentrates on the Euler scheme for the solution of the heat equation, it has the potential for being extended to other schemes and other parabolic partial differential equations (PDEs). These schemes are analyzed and implemented on the shared memory multi-user Sequent Balance machine. Numerical results for one and two dimensional problems are presented. It is shown experimentally that the synchronization penalty can be about 50 percent of run time: in most cases, the asynchronous scheme runs twice as fast as the parallel synchronous scheme. In general, the efficiency of the parallel schemes increases with processor load, with the time level, and with the problem dimension. The efficiency of the AS may reach 90 percent and over, but it provides accurate results only for steady-state values. The CA, on the other hand, is less efficient, but provides more accurate results for intermediate (non steady-state) values.

  4. Asynchronous machines. Direct torque control; Machines asynchrones. Commande par controle direct de couple

    Energy Technology Data Exchange (ETDEWEB)

    Fornel, B. de [Institut National Polytechnique, 31 - Toulouse (France)

    2006-05-15

    The asynchronous machine, with its low cost and robustness, is today the most widely used motor to make speed variators. However, its main drawback is that the same current generates both the magnetic flux and the torque, and thus any torque variation creates a flux variation. Such a coupling gives to the asynchronous machine a nonlinear behaviour which makes its control much more complex. The direct self control (DSC) method has been developed to improve the low efficiency of the scalar control method and for the specific railway drive application. The direct torque control (DTC) method is derived from the DSC method but corresponds to other type of applications. The DSC and DTC algorithms for asynchronous motors are presented in this article: 1 - direct control of the stator flux (DSC): principle, flux control, torque control, switching frequency of the inverter, speed estimation; 2 - direct torque control (DTC): principle, electromagnetic torque derivative, signals shape and switching frequency, some results, DTC speed variator without speed sensor, DTC application to multi-machine multi-converter systems; 3 - conclusion. (J.S.)

  5. Asynchronous discrete event schemes for PDEs

    Science.gov (United States)

    Stone, D.; Geiger, S.; Lord, G. J.

    2017-08-01

    A new class of asynchronous discrete-event simulation schemes for advection-diffusion-reaction equations is introduced, based on the principle of allowing quanta of mass to pass through faces of a (regular, structured) Cartesian finite volume grid. The timescales of these events are linked to the flux on the face. The resulting schemes are self-adaptive, and local in both time and space. Experiments are performed on realistic physical systems related to porous media flow applications, including a large 3D advection diffusion equation and advection diffusion reaction systems. The results are compared to highly accurate reference solutions where the temporal evolution is computed with exponential integrator schemes using the same finite volume discretisation. This allows a reliable estimation of the solution error. Our results indicate a first order convergence of the error as a control parameter is decreased, and we outline a framework for analysis.

  6. Error characterization for asynchronous computations: Proxy equation approach

    Science.gov (United States)

    Sallai, Gabriella; Mittal, Ankita; Girimaji, Sharath

    2017-11-01

    Numerical techniques for asynchronous fluid flow simulations are currently under development to enable efficient utilization of massively parallel computers. These numerical approaches attempt to accurately solve time evolution of transport equations using spatial information at different time levels. The truncation error of asynchronous methods can be divided into two parts: delay dependent (EA) or asynchronous error and delay independent (ES) or synchronous error. The focus of this study is a specific asynchronous error mitigation technique called proxy-equation approach. The aim of this study is to examine these errors as a function of the characteristic wavelength of the solution. Mitigation of asynchronous effects requires that the asynchronous error be smaller than synchronous truncation error. For a simple convection-diffusion equation, proxy-equation error analysis identifies critical initial wave-number, λc. At smaller wave numbers, synchronous error are larger than asynchronous errors. We examine various approaches to increase the value of λc in order to improve the range of applicability of proxy-equation approach.

  7. Wire Position Monitoring with FPGA based Electronics

    International Nuclear Information System (INIS)

    Eddy, N.; Lysenko, O.

    2009-01-01

    This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 (Omega) striplines spaced 90 o apart. An FPGA based digitizer

  8. FPGA fabric specific optimization for RLT design

    International Nuclear Information System (INIS)

    Perwaiz, A.; Khan, S.A.

    2010-01-01

    This paper proposes a technique custom to the optimization requirements suited for a particular family of Field Programmable Gate Arrays (FPGAs). As FPGAs have introduced re configurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the Register Transfer Level (RTL) Hardware Descriptive Language (HDL) code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of the algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned Index Terms: Field Programmable Gate Arrays (FPGA), Compression Tree, Bit Width Reduction, Look Ahead Pipelining. (author)

  9. FPGA Design and Implementation of a Rangefinder

    Directory of Open Access Journals (Sweden)

    ALBU Răzvan-Daniel

    2017-10-01

    Full Text Available In this paper we will present the design and implementation of an ultrasonic non-contact rangefinder with FPGA. This rangefinder can be used in numerous applications, ranging from hardly accessible spaces to electromagnetically polluted environments. The experimental implementations proved to be accurate, portable, and easy to operate. Attributable to their programmable nature, FPGAs are an ideal fit for many dissimilar markets. Even though FPGAs used to be designated for lower speed and complexity designs in the past, today’s FPGAs effortlessly push the 500 MHz performance barricade. Since they bring features, such as embedded processors, DSP blocks, clocking, and high-speed serial at lower prices, FPGAs are a convincing alternative for almost any type of design.

  10. Detection of Failure in Asynchronous Motor Using Soft Computing Method

    Science.gov (United States)

    Vinoth Kumar, K.; Sony, Kevin; Achenkunju John, Alan; Kuriakose, Anto; John, Ano P.

    2018-04-01

    This paper investigates the stator short winding failure of asynchronous motor also their effects on motor current spectrums. A fuzzy logic approach i.e., model based technique possibly will help to detect the asynchronous motor failure. Actually, fuzzy logic similar to humanoid intelligent methods besides expected linguistic empowering inferences through vague statistics. The dynamic model is technologically advanced for asynchronous motor by means of fuzzy logic classifier towards investigate the stator inter turn failure in addition open phase failure. A hardware implementation was carried out with LabVIEW for the online-monitoring of faults.

  11. Realise of PWM-generating based on FPGA

    International Nuclear Information System (INIS)

    Su Rongfeng; Xu Ruinian; Huang Maomao

    2012-01-01

    The power supply digital controllers of Shanghai Synchrotron Radiation Facility(SSRF) make use of the PWM (pulse width modulation) wave as the feedback to the power-electrical devices, so as to obtain constant current of high accuracy and stability. The design of PWM wave generation structure in FPGA is good for a compact controller,and the reduction of the usage of Integrated Circuits (ICs) decreases the interference from the noise among the ICs, hence better performance of the controller. In addition, FPGA can be programmed circularly at any time,so as to optimize the structure design and make a maximum use of the advantage of FPGA. As a part of transplanting the complete function of the DSP (digital signal processor/processing), realizing the generation of PWM wave in FPGA is feasible. In this paper, we report progress in this regard at SSRF. (authors)

  12. Application-specific mesh-based heterogeneous FPGA architectures

    CERN Document Server

    Parvez, Husain

    2011-01-01

    This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

  13. Technologies for faults diagnosis of FPGA logic blocks

    Directory of Open Access Journals (Sweden)

    C. U. Ngene

    2012-08-01

    Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

  14. Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components

    National Research Council Canada - National Science Library

    Bardouleau, Graham; Kulp, James

    2005-01-01

    In recent years the size and capabilities of field-programmable gate array (FPGA) devices have increased to a point where they can be deployed as adjunct processing elements within a multicomputer environment...

  15. High-Performance Linear Algebra Processor using FPGA

    National Research Council Canada - National Science Library

    Johnson, J

    2004-01-01

    With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

  16. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

  17. A software radio platform based on ARM and FPGA

    Directory of Open Access Journals (Sweden)

    Yang Xin.

    2016-01-01

    Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

  18. fpga controller design and simulation of a portable dough mixing

    African Journals Online (AJOL)

    modelled and simulated with Matlab/Simulink. Synthesizable VHDL ... Keywords: FPGA, VHDL, PID controller, Pulse Width Modulation, Full H-Bridge DC motor driver. 1. ... and (b) to simulate the control process in a virtual environment, using.

  19. Real-time FPGA architectures for computer vision

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar

    2000-03-01

    This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low level image processing. The FPGA-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on a dedicated VLSI to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real time performance are discussed. Some results are presented and discussed.

  20. Simultaneous Perturbation Particle Swarm Optimization and Its FPGA Implementation

    OpenAIRE

    Maeda, Yutaka; Matsushita, Naoto

    2009-01-01

    In this paper, we presented hardware implementation of the particle swarm optimization algorithm which is combination of the ordinary particle swarm optimization and the simultaneous perturbation method. FPGA is used to realize the system. This algorithm utilizes local information of objective function effectively without lack of advantage of the original particle swarm optimization. Moreover, the FPGA implementation gives higher operation speed effectively using parallelism of the particle s...

  1. Verification and Planning for Stochastic Processes with Asynchronous Events

    National Research Council Canada - National Science Library

    Younes, Hakan L

    2005-01-01

    .... The most common assumption is that of history-independence: the Markov assumption. In this thesis, the author considers the problems of verification and planning for stochastic processes with asynchronous events, without relying on the Markov assumption...

  2. TCDQ-TCT retraction and losses during asynchronous beam dump

    CERN Document Server

    Bracco, Chiara; Quaranta, Elena; CERN. Geneva. ATS Department

    2016-01-01

    The protection provided by the TCDQs in case of asynchronous beam dump depends strongly on their correct setup. They have to respect the strict hierarchy of the full collimation system and shield the tertiary collimators in the experimental regions. This MD aimed at performing asynchronous beam dump tests with different configurations, in order to assess the minimum allowed retraction between TCTs and TCDQs and, as a consequence, on the The protection provided by the TCDQs in case of asynchronous beam dump depends strongly on their correct setup. They have to respect the strict hierarchy of the full collimation system and shield the tertiary collimators in the experimental regions. This MD aimed at performing asynchronous beam dump tests with different configurations, in order to assess the minimum allowed retraction between TCTs and TCDQs and, as a consequence, on the β* reach.

  3. Supporting collaborative discussions on asynchronous time: a technological perspective

    OpenAIRE

    Caballé, Santi

    2011-01-01

    The aim of this paper is to report on an experience of using an innovative on-line learning tool to support real, collaborative learning through discussion in asynchronous time. While asynchronous interaction gives rise to unique opportunities that support active, collaborative learning, unique problems also arise, such as frustration, caused by waiting for other peoples' reactions and feedback and the consequent loss of motivation, which has a negative impact on learning outcomes. In order t...

  4. A Block-Asynchronous Relaxation Method for Graphics Processing Units

    OpenAIRE

    Anzt, H.; Dongarra, J.; Heuveline, Vincent; Tomov, S.

    2011-01-01

    In this paper, we analyze the potential of asynchronous relaxation methods on Graphics Processing Units (GPUs). For this purpose, we developed a set of asynchronous iteration algorithms in CUDA and compared them with a parallel implementation of synchronous relaxation methods on CPU-based systems. For a set of test matrices taken from the University of Florida Matrix Collection we monitor the convergence behavior, the average iteration time and the total time-to-solution time. Analyzing the r...

  5. Functional asynchronous networks: Factorization of dynamics and function

    Directory of Open Access Journals (Sweden)

    Bick Christian

    2016-01-01

    Full Text Available In this note we describe the theory of functional asynchronous networks and one of the main results, the Modularization of Dynamics Theorem, which for a large class of functional asynchronous networks gives a factorization of dynamics in terms of constituent subnetworks. For these networks we can give a complete description of the network function in terms of the function of the events comprising the network and thereby answer a question originally raised by Alon in the context of biological networks.

  6. Novel Asynchronous Wrapper and Its Application to GALS Systems

    Institute of Scientific and Technical Information of China (English)

    Zhuang Shengxian; Peng Anjin; Lars Wanhammar

    2006-01-01

    An asynchronous wrapper with novel handshake circuits for data communication in globally asynchronous locally synchronous (GALS) systems is proposed. The handshake circuits include two communication ports and a local clock generator. Two approaches for the implementation of communication ports are presented, one with pure standard cells and the others with Müller-C elements. The detailed design methodology for GALS systems is given and the circuits are validated with VHDL and circuits simulation in standard CMOS technology.

  7. Fast semivariogram computation using FPGA architectures

    Science.gov (United States)

    Lagadapati, Yamuna; Shirvaikar, Mukul; Dong, Xuanliang

    2015-02-01

    The semivariogram is a statistical measure of the spatial distribution of data and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. The semivariogram is a plot of semivariances for different lag distances between pixels. A semi-variance, γ(h), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h. Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O(n2). Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz, but they can perform tens of thousands of calculations per clock cycle while operating in the low range of power. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. The design consists of several modules dedicated to the constituent computational tasks. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. Anisotropic semivariogram implementation is anticipated to be an extension of the current architecture, ostensibly based on refinements to the current modules. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from MRI scans are utilized for the experiments

  8. Asynchronous Rate Chaos in Spiking Neuronal Circuits.

    Directory of Open Access Journals (Sweden)

    Omri Harish

    2015-07-01

    Full Text Available The brain exhibits temporally complex patterns of activity with features similar to those of chaotic systems. Theoretical studies over the last twenty years have described various computational advantages for such regimes in neuronal systems. Nevertheless, it still remains unclear whether chaos requires specific cellular properties or network architectures, or whether it is a generic property of neuronal circuits. We investigate the dynamics of networks of excitatory-inhibitory (EI spiking neurons with random sparse connectivity operating in the regime of balance of excitation and inhibition. Combining Dynamical Mean-Field Theory with numerical simulations, we show that chaotic, asynchronous firing rate fluctuations emerge generically for sufficiently strong synapses. Two different mechanisms can lead to these chaotic fluctuations. One mechanism relies on slow I-I inhibition which gives rise to slow subthreshold voltage and rate fluctuations. The decorrelation time of these fluctuations is proportional to the time constant of the inhibition. The second mechanism relies on the recurrent E-I-E feedback loop. It requires slow excitation but the inhibition can be fast. In the corresponding dynamical regime all neurons exhibit rate fluctuations on the time scale of the excitation. Another feature of this regime is that the population-averaged firing rate is substantially smaller in the excitatory population than in the inhibitory population. This is not necessarily the case in the I-I mechanism. Finally, we discuss the neurophysiological and computational significance of our results.

  9. Managing Asynchronous Data in ATLAS's Concurrent Framework

    CERN Document Server

    Baines, John; The ATLAS collaboration

    2016-01-01

    In order to be able to make effective use of emerging hardware, where the amount of memory available to any CPU is rapidly decreasing as the core count continues to rise, ATLAS has begun a migration to a concurrent, multi-threaded software framework, known as AthenaMT. Significant progress has been made in implementing AthenaMT - we can currently run realistic Geant4 simulations on massively concurrent machines. the migration of realistic prototypes of reconstruction workflows is more difficult, given the large amounts of legacy code and the complexity and challenges of reconstruction software. These types of workflows, however, are the types that will most benefit from the memory reduction features of a multi-threaded framework. One of the challenges that we will report on in this paper is the re-design and implementation of several key asynchronous technologies whose behaviour is radically different in a concurrent environment than in a serial one, namely the management of Conditions data and the Detector D...

  10. Rapid, generalized adaptation to asynchronous audiovisual speech.

    Science.gov (United States)

    Van der Burg, Erik; Goodbourn, Patrick T

    2015-04-07

    The brain is adaptive. The speed of propagation through air, and of low-level sensory processing, differs markedly between auditory and visual stimuli; yet the brain can adapt to compensate for the resulting cross-modal delays. Studies investigating temporal recalibration to audiovisual speech have used prolonged adaptation procedures, suggesting that adaptation is sluggish. Here, we show that adaptation to asynchronous audiovisual speech occurs rapidly. Participants viewed a brief clip of an actor pronouncing a single syllable. The voice was either advanced or delayed relative to the corresponding lip movements, and participants were asked to make a synchrony judgement. Although we did not use an explicit adaptation procedure, we demonstrate rapid recalibration based on a single audiovisual event. We find that the point of subjective simultaneity on each trial is highly contingent upon the modality order of the preceding trial. We find compelling evidence that rapid recalibration generalizes across different stimuli, and different actors. Finally, we demonstrate that rapid recalibration occurs even when auditory and visual events clearly belong to different actors. These results suggest that rapid temporal recalibration to audiovisual speech is primarily mediated by basic temporal factors, rather than higher-order factors such as perceived simultaneity and source identity. © 2015 The Author(s) Published by the Royal Society. All rights reserved.

  11. Parallel asynchronous systems and image processing algorithms

    Science.gov (United States)

    Coon, D. D.; Perera, A. G. U.

    1989-01-01

    A new hardware approach to implementation of image processing algorithms is described. The approach is based on silicon devices which would permit an independent analog processing channel to be dedicated to evey pixel. A laminar architecture consisting of a stack of planar arrays of the device would form a two-dimensional array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuronlike asynchronous pulse coded form through the laminar processor. Such systems would integrate image acquisition and image processing. Acquisition and processing would be performed concurrently as in natural vision systems. The research is aimed at implementation of algorithms, such as the intensity dependent summation algorithm and pyramid processing structures, which are motivated by the operation of natural vision systems. Implementation of natural vision algorithms would benefit from the use of neuronlike information coding and the laminar, 2-D parallel, vision system type architecture. Besides providing a neural network framework for implementation of natural vision algorithms, a 2-D parallel approach could eliminate the serial bottleneck of conventional processing systems. Conversion to serial format would occur only after raw intensity data has been substantially processed. An interesting challenge arises from the fact that the mathematical formulation of natural vision algorithms does not specify the means of implementation, so that hardware implementation poses intriguing questions involving vision science.

  12. Asynchronous Rate Chaos in Spiking Neuronal Circuits

    Science.gov (United States)

    Harish, Omri; Hansel, David

    2015-01-01

    The brain exhibits temporally complex patterns of activity with features similar to those of chaotic systems. Theoretical studies over the last twenty years have described various computational advantages for such regimes in neuronal systems. Nevertheless, it still remains unclear whether chaos requires specific cellular properties or network architectures, or whether it is a generic property of neuronal circuits. We investigate the dynamics of networks of excitatory-inhibitory (EI) spiking neurons with random sparse connectivity operating in the regime of balance of excitation and inhibition. Combining Dynamical Mean-Field Theory with numerical simulations, we show that chaotic, asynchronous firing rate fluctuations emerge generically for sufficiently strong synapses. Two different mechanisms can lead to these chaotic fluctuations. One mechanism relies on slow I-I inhibition which gives rise to slow subthreshold voltage and rate fluctuations. The decorrelation time of these fluctuations is proportional to the time constant of the inhibition. The second mechanism relies on the recurrent E-I-E feedback loop. It requires slow excitation but the inhibition can be fast. In the corresponding dynamical regime all neurons exhibit rate fluctuations on the time scale of the excitation. Another feature of this regime is that the population-averaged firing rate is substantially smaller in the excitatory population than in the inhibitory population. This is not necessarily the case in the I-I mechanism. Finally, we discuss the neurophysiological and computational significance of our results. PMID:26230679

  13. Energy efficiency analysis and implementation of AES on an FPGA

    Science.gov (United States)

    Kenney, David

    The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher

  14. Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-05-23

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

  15. FPGA fault tolerance in particle physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Gebelein, Jano; Engel, Heiko; Kebschull, Udo [Kirchhoff-Institute for Physics, Heidelberg University (Germany)

    2010-07-01

    The behavior of matter in physically extreme conditions is in focus of many high-energy-physics experiments. For this purpose, high energy charged particles (ions) are collided with each other and energy- or baryon densities are created similar to those at the beginning of the universe or to those which can be found in the center of neutron stars. In both cases a plasma of quarks and gluons (QGP) is present, which immediately decomposes to hadrons within a short period of time. At this process, particles are formed, which allow statements about the beginning of the universe when captured by large detectors, but which also lead to the massive occurance of hardware failures within the detector's electronic devices. This contribution is about methods to mitigate radiation susceptibility for Field Programmable Gate Arrays (FPGA), enabling them to be used within particle detector systems to directly gain valid data in the readout chain or to be used as detector-control-system.

  16. IMPLEMENTATION OF NEURAL - CRYPTOGRAPHIC SYSTEM USING FPGA

    Directory of Open Access Journals (Sweden)

    KARAM M. Z. OTHMAN

    2011-08-01

    Full Text Available Modern cryptography techniques are virtually unbreakable. As the Internet and other forms of electronic communication become more prevalent, electronic security is becoming increasingly important. Cryptography is used to protect e-mail messages, credit card information, and corporate data. The design of the cryptography system is a conventional cryptography that uses one key for encryption and decryption process. The chosen cryptography algorithm is stream cipher algorithm that encrypt one bit at a time. The central problem in the stream-cipher cryptography is the difficulty of generating a long unpredictable sequence of binary signals from short and random key. Pseudo random number generators (PRNG have been widely used to construct this key sequence. The pseudo random number generator was designed using the Artificial Neural Networks (ANN. The Artificial Neural Networks (ANN providing the required nonlinearity properties that increases the randomness statistical properties of the pseudo random generator. The learning algorithm of this neural network is backpropagation learning algorithm. The learning process was done by software program in Matlab (software implementation to get the efficient weights. Then, the learned neural network was implemented using field programmable gate array (FPGA.

  17. Fpga-based control of piezoelectric actuators

    Directory of Open Access Journals (Sweden)

    Juhász László

    2011-01-01

    Full Text Available In many industrial applications like semiconductor production and optical inspection systems, the availability of positioning systems capable to follow trajectory paths in the range of several centimetres, featuring at the same time a nanometre-range precision, is demanding. Pure piezoelectric stages and standard positioning systems with motor and spindle are not able to meet such requirements, because of the small operation range and inadequacies like backlash and friction. One concept for overcoming these problems consists of a hybrid positioning system built through the integration of a DC-drive in series with a piezoelectric actuator. The wide range of potential applications enables a considerable market potential for such an actuator, but due to the high variety of possible positioned objects and dynamic requirements, the required control complexity may be significant. In this paper, a real-time capable state-space control concept for the piezoelectric actuators, embedded in such a hybrid micropositioning system, is presented. The implementation of the controller together with a real-time capable hysteresis compensation measure is performed using a low-budget FPGA-board, whereas the superimposed integrated controller is realized with a dSPACE RCP-system. The advantages of the designed control over a traditional proportional-integral control structure are proven through experimental results using a commercially available hybrid micropositioning system. Positioning results by different dynamic requirements featuring positioning velocities from 1 μm/s up to 5 cm/s are given.

  18. Video Watermarking Implementation Based on FPGA

    International Nuclear Information System (INIS)

    EL-ARABY, W.S.M.S.

    2012-01-01

    The sudden increase in watermarking interest is most likely due to the increase in concern over copyright protection of content. With the rapid growth of the Internet and the multimedia systems in distributed environments, digital data owners are now easier to transfer multimedia documents across the Internet. However, current technology does not protect their copyrights properly. This leads to wide interest of multimedia security and multimedia copyright protection and it has become a great concern to the public in recent years. In the early days, encryption and control access techniques were used to protect the ownership of media. Recently, the watermarking techniques are utilized to keep safely the copyrights. In this thesis, a fast and secure invisible video watermark technique has been introduced. The technique based mainly on DCT and Low Frequency using pseudo random number (PN) sequence generator for embedding algorithm. The system has been realized using VHDL and the results have been verified using MATLAB. The implementation of the introduced watermark system done using Xilinx chip (XCV800). The implementation results show that the total area of watermark technique is 45% of total FPGA area with maximum delay equals 16.393ns. The experimental results show that the two techniques have mean square error (MSE) equal to 0.0133 and peak signal to noise ratio (PSNR) equal to 66.8984db. The results have been demonstrated and compared with conventional watermark technique using DCT.

  19. FPGA Congestion-Driven Placement Refinement

    Energy Technology Data Exchange (ETDEWEB)

    Vicente de, J.

    2005-07-01

    The routing congestion usually limits the complete proficiency of the FPGA logic resources. A key question can be formulated regarding the benefits of estimating the congestion at placement stage. In the last years, it is gaining acceptance the idea of a detailed placement taking into account congestion. In this paper, we resort to the Thermodynamic Simulated Annealing (TSA) algorithm to perform a congestion-driven placement refinement on the top of the common Bounding-Box pre optimized solution. The adaptive properties of TSA allow the search to preserve the solution quality of the pre optimized solution while improving other fine-grain objectives. Regarding the cost function two approaches have been considered. In the first one Expected Occupation (EO), a detailed probabilistic model to account for channel congestion is evaluated. We show that in spite of the minute detail of EO, the inherent uncertainty of this probabilistic model impedes to relieve congestion beyond the sole application of the Bounding-Box cost function. In the second approach we resort to the fast Rectilinear Steiner Regions algorithm to perform not an estimation but a measurement of the global routing congestion. This second strategy allows us to successfully reduce the requested channel width for a set of benchmark circuits with respect to the widespread Versatile Place and Route (VPR) tool. (Author) 31 refs.

  20. Development of FPGA-Based Control Board

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Yoon Hee; Jeong, See Chae; Choi, Woong Seock; Lee, Chang Jae; Jeong, Jin Kwon; Ha, Jae Hong [Korea Power Engineering Company Inc., Daejeon (Korea, Republic of)

    2009-10-15

    It is well known that existing nuclear power plant (NPP) control systems contain many components which are becoming obsolete at an increasing rate. Various studies have been conducted to address control system hardware obsolescence. Obsolete analog and digital control systems in non-nuclear power plants are commonly replaced with modern digital control systems, programmable logic controllers (PLC) and distributed control systems (DCS). Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative means for obsolete control systems. FPGAs are advanced digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of Programmable Logic Device (PLD). Nowadays they can contain millions of logic gates by nanotechnology and so be used to implement extremely large and complex functions that previously could be realized only using Application-Specific Integrated Circuits (ASICs). This paper is to present the development of a FPGAbased control board performing user-defined control functions. An Actel ProASIC{sup plus} FPGA platform is implemented as the comparator of Plant Protection System (PPS). Functional simulation is implemented for the comparator.

  1. Multi-Softcore Architecture on FPGA

    Directory of Open Access Journals (Sweden)

    Mouna Baklouti

    2014-01-01

    Full Text Available To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication.

  2. Effect of asynchronous updating on the stability of cellular automata

    International Nuclear Information System (INIS)

    Baetens, J.M.; Van der Weeën, P.; De Baets, B.

    2012-01-01

    Highlights: ► An upper bound on the Lyapunov exponent of asynchronously updated CA is established. ► The employed update method has repercussions on the stability of CAs. ► A decision on the employed update method should be taken with care. ► Substantial discrepancies arise between synchronously and asynchronously updated CA. ► Discrepancies between different asynchronous update schemes are less pronounced. - Abstract: Although cellular automata (CAs) were conceptualized as utter discrete mathematical models in which the states of all their spatial entities are updated simultaneously at every consecutive time step, i.e. synchronously, various CA-based models that rely on so-called asynchronous update methods have been constructed in order to overcome the limitations that are tied up with the classical way of evolving CAs. So far, only a few researchers have addressed the consequences of this way of updating on the evolved spatio-temporal patterns, and the reachable stationary states. In this paper, we exploit Lyapunov exponents to determine to what extent the stability of the rules within a family of totalistic CAs is affected by the underlying update method. For that purpose, we derive an upper bound on the maximum Lyapunov exponent of asynchronously iterated CAs, and show its validity, after which we present a comparative study between the Lyapunov exponents obtained for five different update methods, namely one synchronous method and four well-established asynchronous methods. It is found that the stability of CAs is seriously affected if one of the latter methods is employed, whereas the discrepancies arising between the different asynchronous methods are far less pronounced and, finally, we discuss the repercussions of our findings on the development of CA-based models.

  3. Embedded system in FPGA-based LLRF controller for FLASH

    Science.gov (United States)

    Szewinski, Jaroslaw; Pucyk, Piotr; Jalmuzna, Wojciech; Fafara, Przemyslaw; Pieciukiewicz, Marcin; Romaniuk, Ryszard; Pozniak, Krzysztof T.

    2006-10-01

    FPGA devices are often used in High Energy Physics and accelerator technology experiments, where the highest technologies are needed. To make FPGA based systems more flexible, common technique is to provide SoC (System on a Chip) solution in the FPGA, which is in most cases a CPU unit. Such a combination gives possibility to balance between hardware and software implementation of particular task. SoC solution on FPGA can be very flexible, because in simplest cases no additional hardware is needed to run programs on CPU, and when system has such devices like UART, SDRAM memory, mass storage and network interface, it can handle full featured operating system such as Linux or VxWorks. Embedded process can be set up in different configurations, depending on the available resources on board, so every user can adjust system to his own needs. Embedded systems can be also used to perform partial self-reconfiguration of FPGA logic of the chip, on which the system is running. This paper will also present some results on SoC implementations in a Low Level RF system under design for the VUV Free Electron Laser, FLASH, DESY, Hamburg.

  4. FAS: Using FPGA to Accelerate and Secure SDN Software Switches

    Directory of Open Access Journals (Sweden)

    Wenwen Fu

    2018-01-01

    Full Text Available Software-Defined Networking (SDN promises the vision of more flexible and manageable networks but requires certain level of programmability in the data plane to accommodate different forwarding abstractions. SDN software switches running on commodity multicore platforms are programmable and are with low deployment cost. However, the performance of SDN software switches is not satisfactory due to the complex forwarding operations on packets. Moreover, this may hinder the performance of real-time security on software switch. In this paper, we analyze the forwarding procedure and identify the performance bottleneck of SDN software switches. An FPGA-based mechanism for accelerating and securing SDN switches, named FAS (FPGA-Accelerated SDN software switch, is proposed to take advantage of the reconfigurability and high-performance advantages of FPGA. FAS improves the performance as well as the capacity against malicious traffic attacks of SDN software switches by offloading some functional modules. We validate FAS on an FPGA-based network processing platform. Experiment results demonstrate that the forwarding rate of FAS can be 44% higher than the original SDN software switch. In addition, FAS provides new opportunity to enhance the security of SDN software switches by allowing the deployment of bump-in-the-wire security modules (such as packet detectors and filters in FPGA.

  5. IHadoop: Asynchronous iterations for MapReduce

    KAUST Repository

    Elnikety, Eslam Mohamed Ibrahim

    2011-11-01

    MapReduce is a distributed programming frame-work designed to ease the development of scalable data-intensive applications for large clusters of commodity machines. Most machine learning and data mining applications involve iterative computations over large datasets, such as the Web hyperlink structures and social network graphs. Yet, the MapReduce model does not efficiently support this important class of applications. The architecture of MapReduce, most critically its dataflow techniques and task scheduling, is completely unaware of the nature of iterative applications; tasks are scheduled according to a policy that optimizes the execution for a single iteration which wastes bandwidth, I/O, and CPU cycles when compared with an optimal execution for a consecutive set of iterations. This work presents iHadoop, a modified MapReduce model, and an associated implementation, optimized for iterative computations. The iHadoop model schedules iterations asynchronously. It connects the output of one iteration to the next, allowing both to process their data concurrently. iHadoop\\'s task scheduler exploits inter-iteration data locality by scheduling tasks that exhibit a producer/consumer relation on the same physical machine allowing a fast local data transfer. For those iterative applications that require satisfying certain criteria before termination, iHadoop runs the check concurrently during the execution of the subsequent iteration to further reduce the application\\'s latency. This paper also describes our implementation of the iHadoop model, and evaluates its performance against Hadoop, the widely used open source implementation of MapReduce. Experiments using different data analysis applications over real-world and synthetic datasets show that iHadoop performs better than Hadoop for iterative algorithms, reducing execution time of iterative applications by 25% on average. Furthermore, integrating iHadoop with HaLoop, a variant Hadoop implementation that caches

  6. IHadoop: Asynchronous iterations for MapReduce

    KAUST Repository

    Elnikety, Eslam Mohamed Ibrahim; El Sayed, Tamer S.; Ramadan, Hany E.

    2011-01-01

    MapReduce is a distributed programming frame-work designed to ease the development of scalable data-intensive applications for large clusters of commodity machines. Most machine learning and data mining applications involve iterative computations over large datasets, such as the Web hyperlink structures and social network graphs. Yet, the MapReduce model does not efficiently support this important class of applications. The architecture of MapReduce, most critically its dataflow techniques and task scheduling, is completely unaware of the nature of iterative applications; tasks are scheduled according to a policy that optimizes the execution for a single iteration which wastes bandwidth, I/O, and CPU cycles when compared with an optimal execution for a consecutive set of iterations. This work presents iHadoop, a modified MapReduce model, and an associated implementation, optimized for iterative computations. The iHadoop model schedules iterations asynchronously. It connects the output of one iteration to the next, allowing both to process their data concurrently. iHadoop's task scheduler exploits inter-iteration data locality by scheduling tasks that exhibit a producer/consumer relation on the same physical machine allowing a fast local data transfer. For those iterative applications that require satisfying certain criteria before termination, iHadoop runs the check concurrently during the execution of the subsequent iteration to further reduce the application's latency. This paper also describes our implementation of the iHadoop model, and evaluates its performance against Hadoop, the widely used open source implementation of MapReduce. Experiments using different data analysis applications over real-world and synthetic datasets show that iHadoop performs better than Hadoop for iterative algorithms, reducing execution time of iterative applications by 25% on average. Furthermore, integrating iHadoop with HaLoop, a variant Hadoop implementation that caches

  7. The integration of FPGA TDC inside White Rabbit node

    International Nuclear Information System (INIS)

    Li, H.; Xue, T.; Gong, G.; Li, J.

    2017-01-01

    White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

  8. A low-power wave union TDC implemented in FPGA

    International Nuclear Information System (INIS)

    Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

    2011-01-01

    A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

  9. FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

    Directory of Open Access Journals (Sweden)

    Tomyslav Sledevič

    2013-05-01

    Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

  10. The integration of FPGA TDC inside White Rabbit node

    Science.gov (United States)

    Li, H.; Xue, T.; Gong, G.; Li, J.

    2017-04-01

    White Rabbit technology is capable of delivering sub-nanosecond accuracy and picosecond precision of synchronization and normal data packets over the fiber network. Carry chain structure in FPGA is a popular way to build TDC and tens of picosecond RMS resolution has been achieved. The integration of WR technology with FPGA TDC can enhance and simplify the TDC in many aspects that includes providing a low jitter clock for TDC, a synchronized absolute UTC/TAI timestamp for coarse counter, a fancy way to calibrate the carry chain DNL and an easy to use Ethernet link for data and control information transmit. This paper presents a FPGA TDC implemented inside a normal White Rabbit node with sub-nanosecond measurement precision. The measured standard deviation reaches 50ps between two distributed TDCs. Possible applications of this distributed TDC are also discussed.

  11. Flexible, fpga-based electronics for modular robots

    DEFF Research Database (Denmark)

    Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

    2008-01-01

    In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... the FPGA and therefore integrate task-specific electronics without physically changing the electronics or we can reconfigure the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...

  12. An FPGA-based heterogeneous image fusion system design method

    Science.gov (United States)

    Song, Le; Lin, Yu-chi; Chen, Yan-hua; Zhao, Mei-rong

    2011-08-01

    Taking the advantages of FPGA's low cost and compact structure, an FPGA-based heterogeneous image fusion platform is established in this study. Altera's Cyclone IV series FPGA is adopted as the core processor of the platform, and the visible light CCD camera and infrared thermal imager are used as the image-capturing device in order to obtain dualchannel heterogeneous video images. Tailor-made image fusion algorithms such as gray-scale weighted averaging, maximum selection and minimum selection methods are analyzed and compared. VHDL language and the synchronous design method are utilized to perform a reliable RTL-level description. Altera's Quartus II 9.0 software is applied to simulate and implement the algorithm modules. The contrast experiments of various fusion algorithms show that, preferably image quality of the heterogeneous image fusion can be obtained on top of the proposed system. The applied range of the different fusion algorithms is also discussed.

  13. FPGA development board for applications in cosmic rays physics

    International Nuclear Information System (INIS)

    Angelov, Ivo; Damov, Krasimir; Dimitrova, Svetla

    2013-01-01

    The modern experiments in cosmic rays and particle physics are usually performed with large number of detectors and signal processing have to be done by complex electronics. The analog signals from the detectors are converted to digital (by discriminators or fast ADC) and connected to different type of logic implemented in FPGA (Field Programmable Gate Arrays). A FPGA development board based on Xilinx XC3S50AN was designed, assembled and tested. The board will be used for developing a modern registering controller (to replace the existing now) for the muon telescope in the University and can be used for other experiments in cosmic rays physics when fast digital pulses have to be processed. Keywords: FPGA, Spartan3A, muon telescope, cosmic rays variations

  14. Porting VIRTEX4 data acquisition design to SPARTAN6 FPGA

    International Nuclear Information System (INIS)

    Suetoe, J.; Hegyesi, G.

    2012-01-01

    Complete text of publication follows. The Atomki's Virtex 4 based 4 channel data acquisition card (LIR) card was used in many applications (miniPET-II, miniPET-III, data acquisition system for the multichannel plate installed at the ECR lab). The goal of the work was to improve the LIR using a higher performance FPGA (Spartan6 Trenz module). The Trenz module based system also supports ADC channels up to 16 channels. This work also implied the porting of the Virtex4 based VHDL code to Spartan 6. Further advantage of the proposed system, besides the improvement in the number of ADC channels, that the Spartan6 FPGA is able to run more complex digital signal processing algorithms than the Virtex 4 FPGA. Easy access to the control parameters (via serial interface or Ethernet), flexibility and high performance were considered during the development. SPARTAN6 FPGA based data acquisition provides more facilities than the VIRTEX4 based. SPARTAN6 is a newer generation of XILINX’s FPGAs, which excellent into the high-speed data acquisition. We ported the HDL code, which runs on LIR module (VIRTEX4 based), to the Trenz module (SPARTAN6 based). The main parts of the whole program code are the command line interpreter, GMII interface, DHCP process, ARP process and the data read out. Those parts were implemented by picoblaze embedded system. Figure 1 shows the command line interpreter process in the Hyper Terminal. The command line interpreter communicates with the PC via serial port. In addition, the AdamIOSetting software also use the serial communication, which was created to the VIRTEX FPGA based data collector. In the Wireshark network analyzer software we examined the DHCP and ARP process and using the AdamIOSettings software we tested the data read out from the flash memory of FPGA board. Figure 2 shows the AdamIOSettings program. Acknowledgements. This work was supported by the ENIAC CSI Project (No.120209).

  15. Multifunctional data acquisition system based on USB and FPGA

    International Nuclear Information System (INIS)

    Huang Tuchen; Gong Hui; Shao Beibei

    2013-01-01

    A multifunctional data acquisition system based on USB and FPGA was developed. The system has four analog inputs digitalized by fast ADC. Based on flexibility of FPGA, different functions can be implemented such as waveform sampling, pulse counting, multi-channel pulse height analysis, and charge division readout process. The hardware communicates with host PC via USB interface. The Labview based user soft ware initializes the hardware, configures the running parameters, reads and processes the data as well as displays the result online. (authors)

  16. VIRTEX-5 Fpga Implementation of Advanced Encryption Standard Algorithm

    Science.gov (United States)

    Rais, Muhammad H.; Qasim, Syed M.

    2010-06-01

    In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

  17. Design and FPGA Implementation of a new hyperchaotic system

    International Nuclear Information System (INIS)

    Wang Guangyi; Bao Xulei; Wang Zhonglin

    2008-01-01

    In this paper, a new four-dimensional autonomous hyperchaotic system is designed for generating complex chaotic signals. In the design, its parameters are selected according to the requirements for chaos and hyperchaos. The hyperchaotic Nature is verified theoretically by using the bifurcation analysis and demonstrated experimentally by the implementation of an analogue electronic circuit. Moreover, the Field Programmable Gate Array (FPGA) technology is applied to implementing a continuous system in a digital form by using a chip of Altera Cyclone II EP2C35F484C8. The digital sequence generated from the FPGA device is observed in our experimental setup. (general)

  18. B-DCGAN:Evaluation of Binarized DCGAN for FPGA

    OpenAIRE

    Terada, Hideo; Shouno, Hayaru

    2018-01-01

    We are trying to implement deep neural networks in the edge computing environment for real-world applications such as the IoT(Internet of Things), the FinTech etc., for the purpose of utilizing the significant achievement of Deep Learning in recent years. Especially, we now focus algorithm implementation on FPGA, because FPGA is one of the promising devices for low-cost and low-power implementation of the edge computer. In this work, we introduce Binary-DCGAN(B-DCGAN) - Deep Convolutional GAN...

  19. Logic synthesis for FPGA-based finite state machines

    CERN Document Server

    Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

    2016-01-01

    This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

  20. Using FPGA coprocessor for ATLAS level 2 trigger application

    International Nuclear Information System (INIS)

    Khomich, Andrei; Hinkelbein, Christian; Kugel, Andreas; Maenner, Reinhard; Mueller, Matthias

    2006-01-01

    Tracking has a central role in the event selection for the High-Level Triggers of ATLAS. It is particularly important to have fast tracking algorithms in the trigger system. This paper investigates the feasibility of using FPGA coprocessor for speeding up of the TRT LUT algorithm-one of the tracking algorithms for second level trigger for ATLAS experiment (CERN). Two realisations of the same algorithm have been compared: one in C++ and a hybrid C++/VHDL implementation. Using a FPGA coprocessor gives an increase of speed by a factor of two compared to a CPU-only implementation

  1. FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications

    Directory of Open Access Journals (Sweden)

    S. Tsakiris

    2009-09-01

    Full Text Available This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this purpose, an appropriate transmitter circuit, implemented by an FPGA, and suitable coupling circuits are constructed. The system has been developed using VHDL language on Nallatech XtremeDSP development kits. The communication system operates in the baseband up to 30 MHz. Measurements of the algorithm's good performance in terms of the number of detected frames and timing offset error are taken and compared to simulations of existing algorithms.

  2. Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

    Directory of Open Access Journals (Sweden)

    Bhattacharyya Shuvra S

    2003-01-01

    Full Text Available We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

  3. FPGA prototyping by Verilog examples Xilinx Spartan-3 version

    CERN Document Server

    Chu, Pong P

    2008-01-01

    FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a "learn by doing" approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.

  4. Simulating fail-stop in asynchronous distributed systems

    Science.gov (United States)

    Sabel, Laura; Marzullo, Keith

    1994-01-01

    The fail-stop failure model appears frequently in the distributed systems literature. However, in an asynchronous distributed system, the fail-stop model cannot be implemented. In particular, it is impossible to reliably detect crash failures in an asynchronous system. In this paper, we show that it is possible to specify and implement a failure model that is indistinguishable from the fail-stop model from the point of view of any process within an asynchronous system. We give necessary conditions for a failure model to be indistinguishable from the fail-stop model, and derive lower bounds on the amount of process replication needed to implement such a failure model. We present a simple one-round protocol for implementing one such failure model, which we call simulated fail-stop.

  5. The Design of Finite State Machine for Asynchronous Replication Protocol

    Science.gov (United States)

    Wang, Yanlong; Li, Zhanhuai; Lin, Wei; Hei, Minglei; Hao, Jianhua

    Data replication is a key way to design a disaster tolerance system and to achieve reliability and availability. It is difficult for a replication protocol to deal with the diverse and complex environment. This means that data is less well replicated than it ought to be. To reduce data loss and to optimize replication protocols, we (1) present a finite state machine, (2) run it to manage an asynchronous replication protocol and (3) report a simple evaluation of the asynchronous replication protocol based on our state machine. It's proved that our state machine is applicable to guarantee the asynchronous replication protocol running in the proper state to the largest extent in the event of various possible events. It also can helpful to build up replication-based disaster tolerance systems to ensure the business continuity.

  6. PsychVACS: a system for asynchronous telepsychiatry.

    Science.gov (United States)

    Odor, Alberto; Yellowlees, Peter; Hilty, Donald; Parish, Michelle Burke; Nafiz, Najia; Iosif, Ana-Maria

    2011-05-01

    To describe the technical development of an asynchronous telepsychiatry application, the Psychiatric Video Archiving and Communication System. A client-server application was developed in Visual Basic.Net with Microsoft(®) SQL database as the backend. It includes the capability of storing video-recorded psychiatric interviews and manages the workflow of the system with automated messaging. Psychiatric Video Archiving and Communication System has been used to conduct the first ever series of asynchronous telepsychiatry consultations worldwide. A review of the software application and the process as part of this project has led to a number of improvements that are being implemented in the next version, which is being written in Java. This is the first description of the use of video recorded data in an asynchronous telemedicine application. Primary care providers and consulting psychiatrists have found it easy to work with and a valuable resource to increase the availability of psychiatric consultation in remote rural locations.

  7. Asynchronous glaciations in arid continental climate

    Science.gov (United States)

    Batbaatar, Jigjidsurengiin; Gillespie, Alan R.; Fink, David; Matmon, Ari; Fujioka, Toshiyuki

    2018-02-01

    Mountain glaciers at ∼26-19 ka, during the global Last Glacial Maximum near the end of the last 105 yr glacial cycle, are commonly considered on the basis of dating and field mapping in several well-studied areas to have been the largest of the late Quaternary and to have advanced synchronously from region to region. However, a numerical sensitivity model (Rupper and Roe, 2008) predicts that the fraction of ablation due to melting varies across Central Asia in proportion to the annual precipitation. The equilibrium-line altitude of glaciers across this region likely varies accordingly: in high altitude, cold and arid regions sublimation can ablate most of the ice, whereas glaciers fed by high precipitation cannot ablate completely due to sublimation alone, but extend downhill until higher temperatures there cause them to melt. We have conducted field studies and 10Be dating at five glaciated sites along a precipitation gradient in Mongolia to test the Rupper/Roe model. The sites are located in nearby 1.875 × 1.875° cells of the Rupper/Roe model, each with a different melt fraction, in this little-studied region. The modern environment of the sites ranges from dry subhumid in the north (47.7° N) to arid in the south (45° N). Our findings show that the maximum local advances in the dry subhumid conditions predated the global Last Glacial Maximum and were likely from MIS 3. However, we also found that at ∼8-7 ka a cirque glacier in one mountain range of the arid Gobi desert grew to a magnitude comparable to that of the local maximum extent. This Holocene maximum occurred during a regional pluvial period thousands of years after the retreat of the Pleistocene glaciers globally. This asynchronous behavior is not predicted by the prevailing and generally correct presumption that glacier advances are dominantly driven by temperature, although precipitation also plays a role. Our findings are consistent with and support the Rupper/Roe model, which calls for

  8. On the Convergence of Asynchronous Parallel Pattern Search

    International Nuclear Information System (INIS)

    Tamara Gilbson Kolda

    2002-01-01

    In this paper the authors prove global convergence for asynchronous parallel pattern search. In standard pattern search, decisions regarding the update of the iterate and the step-length control parameter are synchronized implicitly across all search directions. They lose this feature in asynchronous parallel pattern search since the search along each direction proceeds semi-autonomously. By bounding the value of the step-length control parameter after any step that produces decrease along a single search direction, they can prove that all the processes share a common accumulation point and that such a point is a stationary point of the standard nonlinear unconstrained optimization problem

  9. Application of intelligent soft start in asynchronous motor

    Science.gov (United States)

    Du, Xue; Ye, Ying; Wang, Yuelong; Peng, Lei; Zhang, Suying

    2018-05-01

    The starting way of three phase asynchronous motor has full voltage start and step-down start. Direct starting brings large current impact, causing excessive local temperature to the power grid and larger starting torque will also impact the motor equipment and affect the service life of the motor. Aim at the problem of large current and torque caused by start-up, an intelligent soft starter is proposed. Through the application of intelligent soft start on asynchronous motor, highlights its application advantage in motor control.

  10. DESIGN METHODOLOGY OF SELF-EXCITED ASYNCHRONOUS GENERATOR

    Directory of Open Access Journals (Sweden)

    Berzan V.

    2012-04-01

    Full Text Available The paper sets out the methodology of designing an asynchronous generator with capacitive self-excitation. It is known that its design is possible on the basis of serial synchronous motor with squirrel cage rotor. With this approach, the design reworked only the stator winding of electrical machines, making it cost-effectively implement the creation of the generator. Therefore, the methodology for the design, optimization calculations, the development scheme and the stator winding excitation system gain, not only of practical interest, and may also be useful for specialists in the field of electrical machines in the design of asynchronous generators.

  11. Reliable self-replicating machines in asynchronous cellular automata.

    Science.gov (United States)

    Lee, Jia; Adachi, Susumu; Peper, Ferdinand

    2007-01-01

    We propose a self-replicating machine that is embedded in a two-dimensional asynchronous cellular automaton with von Neumann neighborhood. The machine dynamically encodes its shape into description signals, and despite the randomness of cell updating, it is able to successfully construct copies of itself according to the description signals. Self-replication on asynchronously updated cellular automata may find application in nanocomputers, where reconfigurability is an essential property, since it allows avoidance of defective parts and simplifies programming of such computers.

  12. On the theoretical gap between synchronous and asynchronous MPC protocols

    DEFF Research Database (Denmark)

    Beerliová-Trubíniová, Zuzana; Hirt, Martin; Nielsen, Jesper Buus

    2010-01-01

    that in the cryptographic setting (with setup), the sole reason for it is the distribution of inputs: given an oracle for input distribution, cryptographically-secure asynchronous MPC is possible with the very same condition as synchronous MPC, namely t ..., we show that such an input-distribution oracle can be reduced to an oracle that allows each party to synchronously broadcast one single message. This means that when one single round of synchronous broadcast is available, then asynchronous MPC is possible at the same condition as synchronous MPC...

  13. Design issues in the semantics and scheduling of asynchronous tasks.

    Energy Technology Data Exchange (ETDEWEB)

    Olivier, Stephen L.

    2013-07-01

    The asynchronous task model serves as a useful vehicle for shared memory parallel programming, particularly on multicore and manycore processors. As adoption of model among programmers has increased, support has emerged for the integration of task parallel language constructs into mainstream programming languages, e.g., C and C++. This paper examines some of the design decisions in Cilk and OpenMP concerning semantics and scheduling of asynchronous tasks with the aim of informing the efforts of committees considering language integration, as well as developers of new task parallel languages and libraries.

  14. CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

    CERN Document Server

    Zhu, Yu

    2010-01-01

    Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

  15. Random number generators for large-scale parallel Monte Carlo simulations on FPGA

    Science.gov (United States)

    Lin, Y.; Wang, F.; Liu, B.

    2018-05-01

    Through parallelization, field programmable gate array (FPGA) can achieve unprecedented speeds in large-scale parallel Monte Carlo (LPMC) simulations. FPGA presents both new constraints and new opportunities for the implementations of random number generators (RNGs), which are key elements of any Monte Carlo (MC) simulation system. Using empirical and application based tests, this study evaluates all of the four RNGs used in previous FPGA based MC studies and newly proposed FPGA implementations for two well-known high-quality RNGs that are suitable for LPMC studies on FPGA. One of the newly proposed FPGA implementations: a parallel version of additive lagged Fibonacci generator (Parallel ALFG) is found to be the best among the evaluated RNGs in fulfilling the needs of LPMC simulations on FPGA.

  16. FPGA design best practices for team-based reuse

    CERN Document Server

    Simpson, Philip Andrew

    2015-01-01

    This book describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book’s content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.  This new edition has been enhanced to include new sections on System modeling, embedded design and high level design. The original sections on Design Environment, RTL design and timing closure have all been expand...

  17. A PMSM current controller system on FPGA platform | Ahmadian ...

    African Journals Online (AJOL)

    Journal of Fundamental and Applied Sciences ... Proposed system architecture and computational blocks are described and system level and RTL simulation results are presented. Simulation results show that the total computation cycle time of implemented system on Altera Cyclone II FPGA is 456ns. Keywords: PMSM ...

  18. VHDL, FPGA and the master trigger controller of BES

    International Nuclear Information System (INIS)

    Guo Yanan; Wang Jufang; Zhao Dixin

    1996-01-01

    A Master Trigger Controller was made using fast FPGA (Field-Programmable Gate Array) instead of ECLIC (Emitter-Coupled Logic Integrated Circuit). VHDL (Verilog Hardware Description Language) was used in its design. The same performance was obtained with increased flexibility

  19. FPGA based VME boards for Indus-2 timing control system

    International Nuclear Information System (INIS)

    Lulani, Nitin; Barpande, K.; Fatnani, P.; Sheth, Y.

    2009-01-01

    FPGA based two VME boards are developed and deployed recently for Indus-2 timing control system at RRCAT Indore. New FPGA based 5-channel programmable (Coarse-Fine) delay generator board has replaced three 2-channel coarse and one 4-channel fine existing delay generator boards. Introduction of this board has improved the fine delay resolution (to 0.5ns) as well as channel to channel jitter (to 0.8ns) of the system. It has also improved the coarse delay resolution from previous 33ns to 8ns with the possibility to work at divided Indus-2 RF clock. These improved parameters have resulted in better injection rate of beam. Old coincidence generator board is also replaced with FPGA based newly developed Coincidence clock generator VME board, which has resulted in successful controlled filling of beam (single, multi and 3-symmetrical bucket filling) in Indus-2. Three more existing boards will be replaced by single FPGA based delay generator card in near future. This paper presents the design, test results and features of new boards. (author)

  20. FPGA based fast synchronous serial multi-wire links synchronization

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2013-10-01

    The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

  1. FPGA Mezzanine Cards for CERN’s Accelerator Control System

    CERN Document Server

    Alvarez, P R; Lewis, J; Serrano, J; Wlostowski, T

    2009-01-01

    Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, PCI and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed...

  2. N queens on an fpga: mathematics,programming, or both?

    NARCIS (Netherlands)

    Kuper, Jan; Wester, Rinse

    2014-01-01

    This paper presents a design methodology for deriving an FPGA implementation directly from a mathematical specification, thus avoiding the switch in semantic perspective as is present in widely applied methods which include an imperative implementation as an intermediate step. The first step in the

  3. Junction Temperature Aware Energy Efficient Router Design on FPGA

    DEFF Research Database (Denmark)

    Thind, Vandana; Sharma, Shivani; Minwer, M H

    2015-01-01

    Energy, Power and efficiency are very much related to each other. To make any system efficient, Power consumed by it must be minimized or we can say that power dissipation should be less. In our research we tried to make a energy efficient router design on FPGA by varying junction temperature...

  4. Effective and efficient FPGA synthesis through general functional decomposition

    NARCIS (Netherlands)

    Jozwiak, L.; Slusarczyk, A.S.; Chojnacki, A.

    2003-01-01

    In this paper, a new information-driven circuit synthesis method is discussed that targets LUT-based FPGAs and FPGA-based reconfigurable system-on-a-chip platforms. The method is based on the bottom–up general functional decomposition and theory of information relationship measures that we

  5. Programovatelná hradlová pole - FPGA

    Czech Academy of Sciences Publication Activity Database

    Daněk, Martin

    2006-01-01

    Roč. 12, č. 2 (2006), s. 9-13 ISSN 1210-9592 R&D Projects: GA ČR GA102/04/2137 Institutional research plan: CEZ:AV0Z10750506 Keywords : FPGA architecture * physical design * design flow Subject RIV: JC - Computer Hardware ; Software

  6. Test of Gb Ethernet with FPGA for HADES upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Gilardi, C. [II. Physikalisches Inst., Giessen Univ. (Germany)

    2007-07-01

    Within the HADES experiment, we are investigating a trigger upgrade in order to run heavier systems (Au + Au). We investigate Gigabit Ethernet transfers with Xilinx Virtex II FPGA on the commercial board Celoxica RC300E. We implement the transfer protocols (UDP, ICMP, ARP) with Handel-C. First results of bandwidth and latency will be presented. (orig.)

  7. FPGA-based implementation of sorting networks in MMC applications

    DEFF Research Database (Denmark)

    Ricco, Mattia; Máthé, Lászlo; Teodorescu, Remus

    2016-01-01

    , and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance...

  8. Uranus: a rapid prototyping tool for FPGA embedded computer vision

    Science.gov (United States)

    Rosales-Hernández, Victor; Castillo-Jimenez, Liz; Viveros-Velez, Gilberto; Zuñiga-Grajeda, Virgilio; Treviño Torres, Abel; Arias-Estrada, M.

    2007-01-01

    The starting point for all successful system development is the simulation. Performing high level simulation of a system can help to identify, insolate and fix design problems. This work presents Uranus, a software tool for simulation and evaluation of image processing algorithms with support to migrate them to an FPGA environment for algorithm acceleration and embedded processes purposes. The tool includes an integrated library of previous coded operators in software and provides the necessary support to read and display image sequences as well as video files. The user can use the previous compiled soft-operators in a high level process chain, and code his own operators. Additional to the prototyping tool, Uranus offers FPGA-based hardware architecture with the same organization as the software prototyping part. The hardware architecture contains a library of FPGA IP cores for image processing that are connected with a PowerPC based system. The Uranus environment is intended for rapid prototyping of machine vision and the migration to FPGA accelerator platform, and it is distributed for academic purposes.

  9. Single Event Effects in FPGA Devices 2015-2016

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  10. SEU mitigation exploratory tests in a ITER related FPGA

    International Nuclear Information System (INIS)

    Batista, Antonio J.N.; Leong, Carlos; Santos, Bruno; Fernandes, Ana; Ramos, Ana Rita; Santos, Joana P.; Marques, José G.; Teixeira, Isabel C.; Teixeira, João P.; Sousa, Jorge; Gonçalves, Bruno

    2017-01-01

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  11. Photoelectric radar servo control system based on ARM+FPGA

    Science.gov (United States)

    Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

    2016-01-01

    In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

  12. SEU mitigation exploratory tests in a ITER related FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Batista, Antonio J.N., E-mail: toquim@ipfn.tecnico.ulisboa.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Leong, Carlos [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Santos, Bruno; Fernandes, Ana [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, José G. [Centro de Ciências e Tecnologias Nucleares (C2TN), Instituto Superior Técnico (IST), Universidade de Lisboa - UL, 2695-066 Bobadela (Portugal); Teixeira, Isabel C.; Teixeira, João P. [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Sousa, Jorge; Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

    2017-05-15

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  13. Adding the Human Touch to Asynchronous Online Learning

    Science.gov (United States)

    Glenn, Cynthia Wheatley

    2018-01-01

    For learners to actively accept responsibility in a virtual classroom platform, it is necessary to provide special motivation extending across the traditional classroom setting into asynchronous online learning. This article explores specific ways to do this that bridge the gap between ground and online students' learning experiences, and how…

  14. Miscellany of Students' Satisfaction in an Asynchronous Learning Environment

    Science.gov (United States)

    Larbi-Siaw, Otu; Owusu-Agyeman, Yaw

    2017-01-01

    This study investigates the determinants of students' satisfaction in an asynchronous learning environment using seven key considerations: the e-learning environment, student-content interaction, student and student interaction, student-teacher interaction, group cohesion and timely participation, knowledge of Internet usage, and satisfaction. The…

  15. An improved modelling of asynchronous machine with skin-effect ...

    African Journals Online (AJOL)

    The conventional method of analysis of Asynchronous machine fails to give accurate results especially when the machine is operated under high rotor frequency. At high rotor frequency, skin-effect dominates causing the rotor impedance to be frequency dependant. This paper therefore presents an improved method of ...

  16. Content Analysis Coding Schemes for Online Asynchronous Discussion

    Science.gov (United States)

    Weltzer-Ward, Lisa

    2011-01-01

    Purpose: Researchers commonly utilize coding-based analysis of classroom asynchronous discussion contributions as part of studies of online learning and instruction. However, this analysis is inconsistent from study to study with over 50 coding schemes and procedures applied in the last eight years. The aim of this article is to provide a basis…

  17. Reconceptualising Moderation in Asynchronous Online Discussions Using Grounded Theory

    Science.gov (United States)

    Vlachopoulos, Panos; Cowan, John

    2010-01-01

    This article reports a grounded theory study of the moderation of asynchronous online discussions, to explore the processes by which tutors in higher education decide when and how to moderate. It aims to construct a theory of e-moderation based on some key factors which appear to influence e-moderation. It discusses previous research on the…

  18. Asynchronous Assessment in a Large Lecture Marketing Course

    Science.gov (United States)

    Downey, W. Scott; Schetzsle, Stacey

    2012-01-01

    Asynchronous assessment, which includes quizzes or exams online or outside class, offers marketing educators an opportunity to make more efficient use of class time and to enhance students' learning experiences by giving them more flexibility and choice in their assessment environment. In this paper, we examine the performance difference between…

  19. Asynchronous Group Review of EFL Writing: Interactions and Text Revisions

    Science.gov (United States)

    Saeed, Murad Abdu; Ghazali, Kamila

    2017-01-01

    The current paper reports an empirical study of asynchronous online group review of argumentative essays among nine English as foreign language (EFL) Arab university learners joining English in their first, second, and third years at the institution. In investigating online interactions, commenting patterns, and how the students facilitate text…

  20. Turing Incompleteness of Asynchronous P Systems with Active Membranes

    OpenAIRE

    Leporati, Alberto; Manzoni, Luca; Porreca, Antonio E.

    2013-01-01

    We prove that asynchronous P systems with active membranes without divi- sion rules can be simulated by place/transition Petri nets, and hence are computationally weaker than Turing machines. This result holds even if the synchronisation mechanisms provided by electrical charges and membrane dissolution are exploited.

  1. Asynchronous online foresight panels: the case of wildfire management

    Science.gov (United States)

    David N. Bengston; Robert L. Olson

    2015-01-01

    Text-based asynchronous online conferencing involves structured online discussion and deliberation among multiple participants from multiple sites in which there is a delay in interaction between contributors. This method has been widely used for a variety of purposes in higher education and other settings, but has not been commonly used in futures research. This paper...

  2. OFDM with Index Modulation for Asynchronous mMTC Networks.

    Science.gov (United States)

    Doğan, Seda; Tusha, Armed; Arslan, Hüseyin

    2018-04-21

    One of the critical missions for next-generation wireless communication systems is to fulfill the high demand for massive Machine-Type Communications (mMTC). In mMTC systems, a sporadic transmission is performed between machine users and base station (BS). Lack of coordination between the users and BS in time destroys orthogonality between the subcarriers, and causes inter-carrier interference (ICI). Therefore, providing services to asynchronous massive machine users is a major challenge for Orthogonal Frequency Division Multiplexing (OFDM). In this study, OFDM with index modulation (OFDM-IM) is proposed as an eligible solution to alleviate ICI caused by asynchronous transmission in uncoordinated mMTC networks. In OFDM-IM, data transmission is performed not only by modulated subcarriers but also by the indices of active subcarriers. Unlike classical OFDM, fractional subcarrier activation leads to less ICI in OFDM-IM technology. A novel subcarrier mapping scheme (SMS) named as Inner Subcarrier Activation is proposed to further alleviate adjacent user interference in asynchronous OFDM-IM-based systems. ISA reduces inter-user interference since it gives more activation priority to inner subcarriers compared with the existing SMS-s. The superiority of the proposed SMS is shown through both theoretical analysis and computer-based simulations in comparison to existing mapping schemes for asynchronous systems.

  3. Designing a Web-Based Asynchronous Innovation/Entrepreneurism Course

    Science.gov (United States)

    Ghandforoush, Parviz

    2017-01-01

    Teaching an online fully asynchronous information technology course that requires students to ideate, build an e-commerce website, and develop an effective business plan involves a well-developed and highly engaging course design. This paper describes the design, development, and implementation of such a course and presents information on…

  4. Study of a centrifugal pump, asynchronous motor and inverter, using ...

    African Journals Online (AJOL)

    The signals generated by the micro controller have been used to program the parallel port of a computer. By reading the recorded bits of the parallel port in LabVIEW software, the signals from the micro controller have been restored and made available to the simulation model of the three-phase inverter, asynchronous ...

  5. Optimization of parameters of special asynchronous electric drives

    Science.gov (United States)

    Karandey, V. Yu; Popov, B. K.; Popova, O. B.; Afanasyev, V. L.

    2018-03-01

    The article considers the solution of the problem of parameters optimization of special asynchronous electric drives. The solution of the problem will allow one to project and create special asynchronous electric drives for various industries. The created types of electric drives will have optimum mass-dimensional and power parameters. It will allow one to realize and fulfill the set characteristics of management of technological processes with optimum level of expenses of electric energy, time of completing the process or other set parameters. The received decision allows one not only to solve a certain optimizing problem, but also to construct dependences between the optimized parameters of special asynchronous electric drives, for example, with the change of power, current in a winding of the stator or rotor, induction in a gap or steel of magnetic conductors and other parameters. On the constructed dependences, it is possible to choose necessary optimum values of parameters of special asynchronous electric drives and their components without carrying out repeated calculations.

  6. Positive semidefinite integrated covariance estimation, factorizations and asynchronicity

    DEFF Research Database (Denmark)

    Boudt, Kris; Laurent, Sébastien; Lunde, Asger

    2017-01-01

    An estimator of the ex-post covariation of log-prices under asynchronicity and microstructure noise is proposed. It uses the Cholesky factorization of the covariance matrix in order to exploit the heterogeneity in trading intensities to estimate the different parameters sequentially with as many...

  7. Positive Semidefinite Integrated Covariance Estimation, Factorizations and Asynchronicity

    DEFF Research Database (Denmark)

    Boudt, Kris; Laurent, Sébastien; Lunde, Asger

    An estimator of the ex-post covariation of log-prices under asynchronicity and microstructure noise is proposed. It uses the Cholesky factorization on the correlation matrix in order to exploit the heterogeneity in trading intensity to estimate the different parameters sequentially with as many...

  8. Developing a Successful Asynchronous Online Extension Program for Forest Landowners

    Science.gov (United States)

    Zobrist, Kevin W.

    2014-01-01

    Asynchronous online Extension classes can reach a wide audience, is convenient for the learner, and minimizes ongoing demands on instructor time. However, producing such classes takes significant effort up front. Advance planning and good communication with contributors are essential to success. Considerations include delivery platforms, content…

  9. INFLUENCE OF THE TIME OF DISINHIBITION TO TRANSIENTS AND WEAR OF THE FRICTION LININGS IN AN ASYNCHRONOUS MOTOR

    Directory of Open Access Journals (Sweden)

    V. V. Solencov

    2016-01-01

    Full Text Available Time and the stopping distance of the electric drive with frequent starting-and-braking modes that contain embedded asynchronous motor with a recessed combined braking device depend on the moment of an electromagnet disinhibition. At the same time other important criteria are taken into the account, i.e. wear resistance of the brake device and the smoothness of the deceleration of the electric drive. In general such an asynchronous motor contains asynchronous engine with squirrel-cage rotor, electromechanical normally-closed brake, electromagnetical slip clutch and control circuit. The mechanical characteristics of the deceleration of asynchronous motor with recessed combined brake device at different moments of an electromagnet disinhibition are presented. The mathematical model is featured and the transients in such a motor are presented. Formation models for computer research were carried out in the Fortran 2008 programming language. Calculation of the system of differential equations was fulfilled by the Runge – Kutta method. The deceleration of the electromechanical brake at various speeds caused different time values and stopping distances. The plots of stopping distance and the braking time at various moments of an electromagnet disinhibition are demonstrated. The optimum moment of switching on an electromechanical brake, providing small stopping distance and the braking time is the time when the speed wвкл = 0,6–0,8 of the nominal. In this case the acceptable number of brake applications for friction linings (compared with mechanical braking will increase by 1.6–2.8 times. The pilot study confirmed the validity of the obtained mathematical models and discovered patterns.

  10. FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

    Science.gov (United States)

    Liang, Yutie; Ye, Hua; Galuska, Martin J.; Gessler, Thomas; Kuhn, Wolfgang; Lange, Jens Soren; Wagner, Milan N.; Liu, Zhen'an; Zhao, Jingzhou

    2017-06-01

    A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

  11. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  12. Intermediate Frequency Digital Receiver Based on Multi-FPGA System

    Directory of Open Access Journals (Sweden)

    Chengchang Zhang

    2016-01-01

    Full Text Available Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC system, we have proposed a new intermediate frequency (IF digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF is realized by coordinated rotation digital computer (CORDIC algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.

  13. Architecture exploration of FPGA based accelerators for bioinformatics applications

    CERN Document Server

    Varma, B Sharat Chandra; Balakrishnan, M

    2016-01-01

    This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.

  14. A new FPGA architecture suitable for DSP applications

    International Nuclear Information System (INIS)

    Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan

    2011-01-01

    A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 x 4.5 mm 2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

  15. FPGA Implementation of a SAR Two-dimensional Autofocus Approach

    Directory of Open Access Journals (Sweden)

    Guo Jiangzhe

    2016-08-01

    Full Text Available For real-time autofocus of defocused images produced by Synthetic Aperture Radar (SAR, the twodimensional autofocus approach proposed in this study is used to correct the residual range cell migration and compensate for the phase error. Next, a block-wise Phase Gradient Autofocus (PGA is used to correct the space-variant phase error. The Field-Programmable Gate Array (FPGA design procedures, resource utilization, processing speed, accuracy, and autofocus are discussed in detail. The system is able to autofocus an 8K × 8K complex image with single precision within 5.7 s when the FPGA works at 200 MHz. The processing of the measured data verifies the effectiveness and real-time capability of the proposed method.

  16. FPGA-based network data transmission scheme for CSNS

    International Nuclear Information System (INIS)

    Wang Xiuku; Zhang Hongyu; Gu Minhao; Xiao Liang

    2012-01-01

    This paper presents the FPGA-based network data transmission solutions for the Data Acquisition System of China Spallation Neutron Source (CSNS). The board with FPGA as the core is used as the hardware platform to realize the transmission of network data. A SOPC system is built and an embedded Linux is transplanted on PowerPC Core. An application program based on Linux has been finished to realize the data transmission via embedded Gigabit Ethernet. The relationship between network transfer performance and packet size was obtained by a test program. In addition, the paper also tried to realize some other ways to transfer data: transplanting PetaLinux on Microblaze, transplanting Lwip protocol stack on PowerPC Core and Microblaze. Their advantages and disadvantages are analyzed and compared in this paper, so that different options and recommendations can be given to meet the actual needs of different projects in the future. (authors)

  17. FPGA-based digital convolution for wireless applications

    CERN Document Server

    Guan, Lei

    2017-01-01

    This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. Covering these digital convolutions from basic concept to vivid simulation/illustration, the book is also supplemented with MS PowerPoint presentations to aid in comprehension. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear...

  18. Embedded Active Vision System Based on an FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Chalimbaud Pierre

    2007-01-01

    Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

  19. Embedded Active Vision System Based on an FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Pierre Chalimbaud

    2006-12-01

    Full Text Available In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks, inspired by biological vision systems. For this reason, we propose an original approach based on a system on programmable chip implemented in an FPGA connected to a CMOS imager and an inertial set. With such a structure based on reprogrammable devices, this system admits a high degree of versatility and allows the implementation of parallel image processing algorithms.

  20. HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

    DEFF Research Database (Denmark)

    Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

    2015-01-01

    standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

  1. Teaching Computer Organization and Architecture Using Simulation and FPGA Applications

    OpenAIRE

    D. K.M. Al-Aubidy

    2007-01-01

    This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemente...

  2. FPGA based, modular, configurable controller with fast synchronous optical network

    Energy Technology Data Exchange (ETDEWEB)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems

    2006-07-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  3. FPGA based, modular, configurable controller with fast synchronous optical network

    International Nuclear Information System (INIS)

    Graczyk, R.; Pozniak, K.T.; Romaniuk, R.S.

    2006-01-01

    The paper describes a configurable controller equipped with programmable VLSI FPGA circuit, universal expansion modules PMC, synchronous, optical, multi-gigabit links, commonly used industrial and computer communication interfaces, Ethernet 100TB, system of automatic initialization ACE etc. There are characterized the basic functional characteristics of the device. The possibilities of its usage in various work modes were presented. Realization of particular blocks of the device were discussed. Resulting, during the realization of this project, new hardware layer solutions were also characterized. (orig.)

  4. FPGA applications for single dish activity at Medicina radio telescopes

    Science.gov (United States)

    Bartolini, M.; Naldi, G.; Mattana, A.; Maccaferri, A.; De Biaggi, M.

    FPGA technologies are gaining major attention in the recent years in the field of radio astronomy. At Medicina radio telescopes, FPGAs have been used in the last ten years for a number of purposes and in this article we will take into exam the applications developed and installed for the Medicina Single Dish 32m Antenna: these range from high performance digital signal processing to instrument control developed on top of smaller FPGAs.

  5. Design of a synthesizer for magnetic resonance equipment using FPGA

    International Nuclear Information System (INIS)

    Sonora A

    2006-01-01

    This paper exposes the design of a direct digital synthesizer in FPGA. This desing can generate a sine wave output up to 4MHZ with 3,33 mHz of precision. The frequency is set by 32bit word of phase increment in 350ns. The desing was made for Magnetic Resonance scanners and uses a 97% of logic resources of device. Functions for the synthesizer control are implemented in the same chip

  6. FPGA based mixed-signal circuit novel testing techniques

    International Nuclear Information System (INIS)

    Pouros, Sotirios; Vassios, Vassilios; Papakostas, Dimitrios; Hristov, Valentin

    2013-01-01

    Electronic circuits fault detection techniques, especially on modern mixed-signal circuits, are evolved and customized around the world to meet the industry needs. The paper presents techniques used on fault detection in mixed signal circuits. Moreover, the paper involves standardized methods, along with current innovations for external testing like Design for Testability (DfT) and Built In Self Test (BIST) systems. Finally, the research team introduces a circuit implementation scheme using FPGA

  7. Implementation of Serial and Parallel Bubble Sort on Fpga

    OpenAIRE

    Purnomo, Dwi Marhaendro Jati; Arinaldi, Ahmad; Priyantini, Dwi Teguh; Wibisono, Ari; Febrian, Andreas

    2016-01-01

    Sorting is common process in computational world. Its utilization are on many fields from research to industry. There are many sorting algorithm in nowadays. One of the simplest yet powerful is bubble sort. In this study, bubble sort is implemented on FPGA. The implementation was taken on serial and parallel approach. Serial and parallel bubble sort then compared by means of its memory, execution time, and utility which comprises slices and LUTs. The experiments show that serial bubble sort r...

  8. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    OpenAIRE

    Zulfikar, Z

    2012-01-01

    A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared....

  9. VHDL resolved function based inner communication bus for FPGA

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2017-08-01

    This article discusses a method of building an internal, universal and parametric bus. The solution was designed for a variety of FPGA families and popular VHDL compilers. The algorithm of automatic configuration of address space and methods of receiving and sending addressed data are discussed. The basic solution realized in VHDL language in a behavioral form and chosen examples of practical use of the internal bus are presented in detail.

  10. Accelerating String Set Matching in FPGA Hardware for Bioinformatics Research

    Directory of Open Access Journals (Sweden)

    Burgess Shane C

    2008-04-01

    Full Text Available Abstract Background This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomics. The process of matching peptide sequences against a genome translated in six reading frames is part of a proteogenomic mapping pipeline that is used as a case-study. The Aho-Corasick algorithm is adapted for execution in field programmable gate array (FPGA devices in a manner that optimizes space and performance. In this approach, the traditional Aho-Corasick finite state machine (FSM is split into smaller FSMs, operating in parallel, each of which matches up to 20 peptides in the input translated genome. Each of the smaller FSMs is further divided into five simpler FSMs such that each simple FSM operates on a single bit position in the input (five bits are sufficient for representing all amino acids and special symbols in protein sequences. Results This bit-split organization of the Aho-Corasick implementation enables efficient utilization of the limited random access memory (RAM resources available in typical FPGAs. The use of on-chip RAM as opposed to FPGA logic resources for FSM implementation also enables rapid reconfiguration of the FPGA without the place and routing delays associated with complex digital designs. Conclusion Experimental results show storage efficiencies of over 80% for several data sets. Furthermore, the FPGA implementation executing at 100 MHz is nearly 20 times faster than an implementation of the traditional Aho-Corasick algorithm executing on a 2.67 GHz workstation.

  11. DNA Assembly with De Bruijn Graphs Using an FPGA Platform.

    Science.gov (United States)

    Poirier, Carl; Gosselin, Benoit; Fortier, Paul

    2018-01-01

    This paper presents an FPGA implementation of a DNA assembly algorithm, called Ray, initially developed to run on parallel CPUs. The OpenCL language is used and the focus is placed on modifying and optimizing the original algorithm to better suit the new parallelization tool and the radically different hardware architecture. The results show that the execution time is roughly one fourth that of the CPU and factoring energy consumption yields a tenfold savings.

  12. Embedded active vision system based on an FPGA architecture

    OpenAIRE

    Chalimbaud , Pierre; Berry , François

    2006-01-01

    International audience; In computer vision and more particularly in vision processing, the impressive evolution of algorithms and the emergence of new techniques dramatically increase algorithm complexity. In this paper, a novel FPGA-based architecture dedicated to active vision (and more precisely early vision) is proposed. Active vision appears as an alternative approach to deal with artificial vision problems. The central idea is to take into account the perceptual aspects of visual tasks,...

  13. Asynchronous decision making in a memorized paddle pressing task.

    Science.gov (United States)

    Dankert, James R; Olson, Byron; Si, Jennie

    2008-12-01

    This paper presents a method for asynchronous decision making using recorded neural data in a binary decision task. This is a demonstration of a technique for developing motor cortical neural prosthetics that do not rely on external cued timing information. The system presented in this paper uses support vector machines and leaky integrate-and-fire elements to predict directional paddle presses. In addition to the traditional metrics of accuracy, asynchronous systems must also optimize the time needed to make a decision. The system presented is able to predict paddle presses with a median accuracy of 88% and all decisions are made before the time of the actual paddle press. An alternative bit rate measure of performance is defined to show that the system proposed here is able to perform the task with the same efficiency as the rats.

  14. Parallel, Asynchronous Executive (PAX): System concepts, facilities, and architecture

    Science.gov (United States)

    Jones, W. H.

    1983-01-01

    The Parallel, Asynchronous Executive (PAX) is a software operating system simulation that allows many computers to work on a single problem at the same time. PAX is currently implemented on a UNIVAC 1100/42 computer system. Independent UNIVAC runstreams are used to simulate independent computers. Data are shared among independent UNIVAC runstreams through shared mass-storage files. PAX has achieved the following: (1) applied several computing processes simultaneously to a single, logically unified problem; (2) resolved most parallel processor conflicts by careful work assignment; (3) resolved by means of worker requests to PAX all conflicts not resolved by work assignment; (4) provided fault isolation and recovery mechanisms to meet the problems of an actual parallel, asynchronous processing machine. Additionally, one real-life problem has been constructed for the PAX environment. This is CASPER, a collection of aerodynamic and structural dynamic problem simulation routines. CASPER is not discussed in this report except to provide examples of parallel-processing techniques.

  15. Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits

    Directory of Open Access Journals (Sweden)

    Soundous Chairat

    2017-05-01

    Full Text Available This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT system. By using a separate communication network, we can address both digital and analog blocks at a lower configuration cost, increasing the overall system power efficiency. As reconfiguration only occurs according to specific events and has to be automatically in stand-by most of the time, our design is fully asynchronous using handshake protocols. The paper presents the circuit’s architecture, performance results, and an example of the reconfiguration of frequency locked loops (FLL to validate our work. We obtain an overall energy per bit of 0.07 pJ/bit for one stage, in a 28 nm Fully Depleted Silicon On Insulator (FDSOI technology at 0.6 V and a 1.1 ns/bit latency per stage.

  16. The current state of FPGA technology in the nuclear domain

    Energy Technology Data Exchange (ETDEWEB)

    Ranta, J.

    2012-07-01

    Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

  17. The current state of FPGA technology in the nuclear domain

    International Nuclear Information System (INIS)

    Ranta, J.

    2012-01-01

    Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

  18. Desain Protokol Suara Sebagai Pengendali Dalam Smart Home Menggunakan FPGA

    Directory of Open Access Journals (Sweden)

    Barlian Henryranu Prasetio

    2017-05-01

    Smart home is a system that uses computers and information technology to control home-like equipment such as windows and lights. The system can be a simple control system to a complex system. Computer / microcontroller based on internet/ethernet network equipped with intelligent system and automation system so as to make home to work automatically. Many computer devices / microcontrollers that can be implemented as a controller in the smart home. Smart home control system in this study using Xilinx xpartan-3e that controls the equipment in the house through LAN (Local Area Networking. This control system communicates using broadcast voice on the local network. The Controller System is designed to be able to transmit a voice signal packet from the microphone input and then send it using the ethernet protocol in the home local network using the FPGA. The FPGA is programmed to transmit and encode data packets, converting digital data into analog data to be able to control the equipment in the home. From the simulation test results using ISIM, it is seen that the system works in realtime. Keywords: smart home, voice, fpga, control

  19. Estimation of channel impulse response and FPGA simulation

    Directory of Open Access Journals (Sweden)

    YU Longjie

    2015-02-01

    Full Text Available Wideband code division multiple access (WCDMA is a 3G wireless communication network.The common pilot channel in downlink of WCDMA provides an effective method to estimate the channel impulse response.In this paper,universal software radio peripheral (USRP is utilized to sample and process WCDMA signal which is emitted by China Unicom base station.Firstly,the received signal is pre-processed with filtering and down-sampling.Secondly,fast algorithm of WCDMA cell search is fulfilled.Thirdly,frequency shift caused by USRP′s crystal oscillator is checked and compensated.Eventually,channel impulse response is estimated.In this paper,MATLAB is used to describe the above algorithm and field programmable gate array (FPGA is used to simulate algorithm.In the process of simulation,pipeline and IP core multiplexing are introduced.In the case of 32 MHz clock frequency,FPGA simulation time is 80.861 ms.Simulation results show that FPGA is able to estimate the channel impulse response quickly and accurately with less hardware resources.

  20. Hardware and Software Integration in Project Development of Automated Controller System Using LABVIEW FPGA

    International Nuclear Information System (INIS)

    Mohd Khairulezwan Abd Manan; Mohd Sabri Minhat; Izhar Abu Hussin

    2014-01-01

    The Field-Programmable Gate Array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows user to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field, hence the name field-programmable. This project developed a control system using LabVIEW FPGA. LabVIEW FPGA is easier where it is programmed by using drag and drop icon. Then it will be integrated with the hardware input and output. (author)

  1. New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie D.; Label, Kenneth A.; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  2. New Developments in FPGA Devices: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  3. Teleoperation system using Asynchronous transfer mode, ATM network

    International Nuclear Information System (INIS)

    Mohd Dani Baba; A Nasoruddin Mohamad

    1999-01-01

    This paper examines the application of Asynchronous Transfer Mode (ATM) in a distributed industrial environment such as in teleoperation, which performs real time control manipulation from a remote location. In our study, two models of teleoperation are proposed; the first model is a point to point connection and the second model is through an ATM network. The performance results are analysed as to determine whether the two models can support the teleoperation traffics via simulation using commercial software design tool. (Author)

  4. Asynchronous Multi-Party Computation with Quadratic Communication

    DEFF Research Database (Denmark)

    Hirt, Martin; Nielsen, Jesper Buus; Przydatek, Bartosz

    2008-01-01

    We present an efficient protocol for secure multi-party computation in the asynchronous model with optimal resilience. For n parties, up to t < n/3 of them being corrupted, and security parameter κ, a circuit with c gates can be securely computed with communication complexity O(cn^2k) bits, which...... circuit randomization due to Beaver (Crypto’91), and an abstraction of certificates, which can be of independent interest....

  5. Psychophysiological effects of synchronous versus asynchronous music during cycling.

    Science.gov (United States)

    Lim, Harry B T; Karageorghis, Costas I; Romer, Lee M; Bishop, Daniel T

    2014-02-01

    Synchronizing movement to a musical beat may reduce the metabolic cost of exercise, but findings to date have been equivocal. Our aim was to examine the degree to which the synchronous application of music moderates the metabolic demands of a cycle ergometer task. Twenty-three recreationally active men made two laboratory visits. During the first visit, participants completed a maximal incremental ramp test on a cycle ergometer. At the second visit, they completed four randomized 6-min cycling bouts at 90% of ventilatory threshold (control, metronome, synchronous music, and asynchronous music). Main outcome variables were oxygen uptake, HR, ratings of dyspnea and limb discomfort, affective valence, and arousal. No significant differences were evident for oxygen uptake. HR was lower under the metronome condition (122 ± 15 bpm) compared to asynchronous music (124 ± 17 bpm) and control (125 ± 16 bpm). Limb discomfort was lower while listening to the metronome (2.5 ± 1.2) and synchronous music (2.3 ± 1.1) compared to control (3.0 ± 1.5). Both music conditions, synchronous (1.9 ± 1.2) and asynchronous (2.1 ± 1.3), elicited more positive affective valence compared to metronome (1.2 ± 1.4) and control (1.2 ± 1.2), while arousal was higher with synchronous music (3.4 ± 0.9) compared to metronome (2.8 ± 1.0) and control (2.8 ± 0.9). Synchronizing movement to a rhythmic stimulus does not reduce metabolic cost but may lower limb discomfort. Moreover, synchronous music has a stronger effect on limb discomfort and arousal when compared to asynchronous music.

  6. Asynchronous monitoring of the quality of multilevel optical PAM signals

    Science.gov (United States)

    Siuzdak, J.

    2017-08-01

    In the paper, there is analyzed the signal quality assessment method based on delay tap asynchronous sampling, both for binary and multilevel PAM signals. The obtained multilevel phase diagrams are far more complicated than binary ones. The phase diagrams are affected by the signal distortions but it is difficult to relate reliably the phase diagram form to the distortion type and its influence on the signal quality.

  7. Asynchronous Execution of the Fast Multipole Method Using Charm++

    OpenAIRE

    AbdulJabbar, Mustafa; Yokota, Rio; Keyes, David

    2014-01-01

    Fast multipole methods (FMM) on distributed mem- ory have traditionally used a bulk-synchronous model of com- municating the local essential tree (LET) and overlapping it with computation of the local data. This could be perceived as an extreme case of data aggregation, where the whole LET is communicated at once. Charm++ allows a much finer control over the granularity of communication, and has a asynchronous execution model that fits well with the structure of our FMM code. Unlike previous ...

  8. New slow-control FPGA IP for GBT based system and status update of the GBT-FPGA project

    CERN Document Server

    Mendez, Julian Maxime; Caratelli, Alessandro; Leitao, Pedro Vicente

    2018-01-01

    The GBT-FPGA, part of the GBT (GigaBit Transceiver) project framework, is a VHDL-based core designed to offer a back-end counterpart to the GBTx ASIC, a radiation tolerant 4.8 Gb/s optical transceiver. The GBT-SCA (Slow Control Adapter) radiation tolerant ASIC is also part of the GBT chipset and is used for the slow control in the High Energy Physics experiments. In this context, a new VHDL core named GBT-SC has been designed and released to handle the slow control fields hosted in the serial GBT frame for the GBTx and GBT-SCA. This paper presents the architecture and performance of this new GBT-SC module as well as an outline of recent GBT-FPGA core releases and future plans.

  9. A novel asynchronous access method with binary interfaces

    Directory of Open Access Journals (Sweden)

    Torres-Solis Jorge

    2008-10-01

    Full Text Available Abstract Background Traditionally synchronous access strategies require users to comply with one or more time constraints in order to communicate intent with a binary human-machine interface (e.g., mechanical, gestural or neural switches. Asynchronous access methods are preferable, but have not been used with binary interfaces in the control of devices that require more than two commands to be successfully operated. Methods We present the mathematical development and evaluation of a novel asynchronous access method that may be used to translate sporadic activations of binary interfaces into distinct outcomes for the control of devices requiring an arbitrary number of commands to be controlled. With this method, users are required to activate their interfaces only when the device under control behaves erroneously. Then, a recursive algorithm, incorporating contextual assumptions relevant to all possible outcomes, is used to obtain an informed estimate of user intention. We evaluate this method by simulating a control task requiring a series of target commands to be tracked by a model user. Results When compared to a random selection, the proposed asynchronous access method offers a significant reduction in the number of interface activations required from the user. Conclusion This novel access method offers a variety of advantages over traditionally synchronous access strategies and may be adapted to a wide variety of contexts, with primary relevance to applications involving direct object manipulation.

  10. Pseudo Asynchronous Level Crossing adc for ecg Signal Acquisition.

    Science.gov (United States)

    Marisa, T; Niederhauser, T; Haeberlin, A; Wildhaber, R A; Vogel, R; Goette, J; Jacomet, M

    2017-02-07

    A new pseudo asynchronous level crossing analogue-to-digital converter (adc) architecture targeted for low-power, implantable, long-term biomedical sensing applications is presented. In contrast to most of the existing asynchronous level crossing adc designs, the proposed design has no digital-to-analogue converter (dac) and no continuous time comparators. Instead, the proposed architecture uses an analogue memory cell and dynamic comparators. The architecture retains the signal activity dependent sampling operation by generating events only when the input signal is changing. The architecture offers the advantages of smaller chip area, energy saving and fewer analogue system components. Beside lower energy consumption the use of dynamic comparators results in a more robust performance in noise conditions. Moreover, dynamic comparators make interfacing the asynchronous level crossing system to synchronous processing blocks simpler. The proposed adc was implemented in [Formula: see text] complementary metal-oxide-semiconductor (cmos) technology, the hardware occupies a chip area of 0.0372 mm 2 and operates from a supply voltage of [Formula: see text] to [Formula: see text]. The adc's power consumption is as low as 0.6 μW with signal bandwidth from [Formula: see text] to [Formula: see text] and achieves an equivalent number of bits (enob) of up to 8 bits.

  11. A Synchronous-Asynchronous Particle Swarm Optimisation Algorithm

    Science.gov (United States)

    Ab Aziz, Nor Azlina; Mubin, Marizan; Mohamad, Mohd Saberi; Ab Aziz, Kamarulzaman

    2014-01-01

    In the original particle swarm optimisation (PSO) algorithm, the particles' velocities and positions are updated after the whole swarm performance is evaluated. This algorithm is also known as synchronous PSO (S-PSO). The strength of this update method is in the exploitation of the information. Asynchronous update PSO (A-PSO) has been proposed as an alternative to S-PSO. A particle in A-PSO updates its velocity and position as soon as its own performance has been evaluated. Hence, particles are updated using partial information, leading to stronger exploration. In this paper, we attempt to improve PSO by merging both update methods to utilise the strengths of both methods. The proposed synchronous-asynchronous PSO (SA-PSO) algorithm divides the particles into smaller groups. The best member of a group and the swarm's best are chosen to lead the search. Members within a group are updated synchronously, while the groups themselves are asynchronously updated. Five well-known unimodal functions, four multimodal functions, and a real world optimisation problem are used to study the performance of SA-PSO, which is compared with the performances of S-PSO and A-PSO. The results are statistically analysed and show that the proposed SA-PSO has performed consistently well. PMID:25121109

  12. Data Collection for Mobile Group Consumption: An Asynchronous Distributed Approach

    Directory of Open Access Journals (Sweden)

    Weiping Zhu

    2016-04-01

    Full Text Available Mobile group consumption refers to consumption by a group of people, such as a couple, a family, colleagues and friends, based on mobile communications. It differs from consumption only involving individuals, because of the complex relations among group members. Existing data collection systems for mobile group consumption are centralized, which has the disadvantages of being a performance bottleneck, having single-point failure and increasing business and security risks. Moreover, these data collection systems are based on a synchronized clock, which is often unrealistic because of hardware constraints, privacy concerns or synchronization cost. In this paper, we propose the first asynchronous distributed approach to collecting data generated by mobile group consumption. We formally built a system model thereof based on asynchronous distributed communication. We then designed a simulation system for the model for which we propose a three-layer solution framework. After that, we describe how to detect the causality relation of two/three gathering events that happened in the system based on the collected data. Various definitions of causality relations based on asynchronous distributed communication are supported. Extensive simulation results show that the proposed approach is effective for data collection relating to mobile group consumption.

  13. Data Collection for Mobile Group Consumption: An Asynchronous Distributed Approach.

    Science.gov (United States)

    Zhu, Weiping; Chen, Weiran; Hu, Zhejie; Li, Zuoyou; Liang, Yue; Chen, Jiaojiao

    2016-04-06

    Mobile group consumption refers to consumption by a group of people, such as a couple, a family, colleagues and friends, based on mobile communications. It differs from consumption only involving individuals, because of the complex relations among group members. Existing data collection systems for mobile group consumption are centralized, which has the disadvantages of being a performance bottleneck, having single-point failure and increasing business and security risks. Moreover, these data collection systems are based on a synchronized clock, which is often unrealistic because of hardware constraints, privacy concerns or synchronization cost. In this paper, we propose the first asynchronous distributed approach to collecting data generated by mobile group consumption. We formally built a system model thereof based on asynchronous distributed communication. We then designed a simulation system for the model for which we propose a three-layer solution framework. After that, we describe how to detect the causality relation of two/three gathering events that happened in the system based on the collected data. Various definitions of causality relations based on asynchronous distributed communication are supported. Extensive simulation results show that the proposed approach is effective for data collection relating to mobile group consumption.

  14. Economical Implementation of a Filter Engine in an FPGA

    Science.gov (United States)

    Kowalski, James E.

    2009-01-01

    A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be

  15. Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

    Science.gov (United States)

    Du, Hongtao; Qi, Hairong; Szu, Harold H.

    2005-03-01

    Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles (UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications. These affordable and reusable devices have to fit a series of size, weight, and power constraints. Cameras used on such micro-UAVs are therefore mounted directly at a fixed angle without any motion-compensated gimbals. This mounting scheme has resulted in the so-called jitter effect in which jitter is defined as sub-pixel or small amplitude vibrations. The jitter blur caused by the jitter effect needs to be corrected before any other processing algorithms can be practically applied. Jitter restoration has been solved by various optimization techniques, including Wiener approximation, maximum a-posteriori probability (MAP), etc. However, these algorithms normally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed a smart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised artificial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithm resembles the capability of the human visual system, in which an agreement between the pair of eyes indicates "signal", otherwise, the jitter noise. Using this non-statistical method, for each single pixel, a deterministic blind sources separation (BSS) process can then be carried out independently based on a deterministic minimum of the Helmholtz free energy with a generalization of Shannon's information theory applied to open dynamic systems. From a hardware implementation point of view, the process of jitter restoration of an image using Szu's algorithm can be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent component analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) and Application

  16. ON THE ISSUE OF VECTOR CONTROL OF THE ASYNCHRONOUS MOTORS

    Directory of Open Access Journals (Sweden)

    B. I. Firago

    2015-01-01

    Full Text Available The paper considers the issue of one of the widespread types of vector control realization for the asynchronous motors with a short-circuited rotor. Of all more than 20 vector control types known presently, the following are applied most frequently: direct vector control with velocity pickup (VP, direct vector control without VP, indirect vector control with VP and indirect vector control without VP. Despite the fact that the asynchronous-motor indirect vector control without VP is the easiest and most spread, the absence of VP does not allow controlling the motor electromagnetic torque at zero velocity. This is the reason why for electric motor drives of such requirements they utilize the vector control with a velocity transducer. The systems of widest dissemination became the direct and indirect vector control systems with X-axis alignment of the synchronously rotating x–y-coordinate frame along the rotor flux-linkage vector inasmuch as this provides the simplest correlations for controlling variables. Although these two types of vector control are well presented in literature, a number of issues concerning their realization and practical application require further elaboration. These include: the block schemes adequate representation as consisted with the modern realization of vector control and clarification of the analytical expressions for evaluating the regulator parameters.The authors present a technique for evaluating the dynamics of an asynchronous electric motor drive with direct vector control and x-axis alignment along the vector of rotor flux linkage. The article offers a generalized structure of this vector control type with detailed description of its principal blocks: controlling system, frequency converter, and the asynchronous motor.The paper presents a direct vector control simulating model developed in the MatLab environment on the grounds of this structure. The authors illustrate the described technique with the results

  17. Pharmacists' perception of synchronous versus asynchronous distance learning for continuing education programs.

    Science.gov (United States)

    Buxton, Eric C

    2014-02-12

    To evaluate and compare pharmacists' satisfaction with the content and learning environment of a continuing education program series offered as either synchronous or asynchronous webinars. An 8-lecture series of online presentations on the topic of new drug therapies was offered to pharmacists in synchronous and asynchronous webinar formats. Participants completed a 50-question online survey at the end of the program series to evaluate their perceptions of the distance learning experience. Eighty-two participants completed the survey instrument (41 participants from the live webinar series and 41 participants from the asynchronous webinar series.) Responses indicated that while both groups were satisfied with the program content, the asynchronous group showed greater satisfaction with many aspects of the learning environment. The synchronous and asynchronous webinar participants responded positively regarding the quality of the programming and the method of delivery, but asynchronous participants rated their experience more positively overall.

  18. Design and demonstration of a multitechnology FPGA for photonic information processing

    Science.gov (United States)

    Mal, Prosenjit; Hawk, Chris; Toshniwal, Kavita; Beyette, Fred R., Jr.

    2003-11-01

    We present here a novel architecture for a multi-technology field programmabler gate array (MT-FPGA). Implemented with a conventional CMOS VLSI technology the architecture is suitable for prototyping photonic information processing systems. We report here that this new FPGA architecture will enable the design of reconfigurable systems that incorporate technologies outside the traditional electronic domain.

  19. Implementation of a feed-forward artificial neural network in VHDL on FPGA

    NARCIS (Netherlands)

    Dondon, P.; Carvalho, J.; Gardere, R.; Lahalle, P.; Tsenov, G.; Mladenov, V.M.; Reljin, B.; Stankovic, S.

    2014-01-01

    Describing an Artificial Neural Network (ANN) using VHDL allows a further implementation of such a system on FPGA. Indeed, the principal point of using FPGA for ANNs is flexibility that gives it an advantage toward other systems like ASICS which are entirely dedicated to one unique architecture and

  20. Development of a multi-purpose logic module with the FPGA

    International Nuclear Information System (INIS)

    Nanbu, K.; Ishikawa, T.; Shimizu, H.

    2008-01-01

    We have developed a multi-purpose logic module (MPLM) with an FPGA. The internal circuit of this module can be modified easily with the FPGA. This kind of module enables trigger pulse processing for nuclear science. As a first step, the MPLM is used as an event tag generator in experiments with the FOREST detector system. (author)

  1. An FPGA bridge preserving traffing quality of service for on-chip network-based systems

    NARCIS (Netherlands)

    Nejad, A.B.; Escudero Martinez, M.; Goossens, K.G.W.

    2011-01-01

    FPGA prototyping of recent large Systems on Chip (SoCs) is very challenging due to the resource limitation of a single FPGA. Moreover, having external access to SoCs for verification and debug purposes is essential. In this paper, we suggest to partition a network-on-chip (NoC) based system into

  2. Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration

    NARCIS (Netherlands)

    Becher, Andreas; Bauer, Florian; Ziener, Daniel; Teich, Jürgen

    2014-01-01

    In this paper, we propose an approach for energy-aware FPGA-based query acceleration for databases on embedded devices. After the analysis of an incoming query, a query-specific hardware accelerator is generated on-the-fly and loaded on the FPGA for subsequent query execution using partial dynamic

  3. Multirate Digital Filters Based on FPGA and Its Applications

    International Nuclear Information System (INIS)

    Sharaf El-Din, R.M.A.

    2013-01-01

    Digital Signal Processing (DSP) is one of the fastest growing techniques in the electronics industry. It is used in a wide range of application fields such as, telecommunications, data communications, image enhancement and processing, video signals, digital TV broadcasting, and voice synthesis and recognition. Field Programmable Gate Array (FPGA) offers good solution for addressing the needs of high performance DSP systems. The focus of this thesis is on one of the basic DSP functions, namely filtering signals to remove unwanted frequency bands. Multi rate Digital Filters (MDFs) are the main theme here. Theory and implementation of MDF, as a special class of digital filters, will be discussed. Multi rate digital filters represent a class of digital filters having a number of attractive features like, low requirements for the coefficient word lengths, significant saving in computation and storage requirements results in a significant reduction in its dynamic power consumption. This thesis introduces an efficient FPGA realization of a multi rate decimation filter with narrow pass-band and narrow transition band to reduce the frequency sample rate by factor of 64 for noise thermometer applications. The proposed multi rate decimation filter is composed of three stages; the first stage is a Cascaded Integrator Comb (CIC) decimation filter, the second stage is a two-coefficient Half-Band (HB) filter and the last stage is a sharper transition HB filter. The frequency responses of individual stages as well as the overall filter response have been demonstrated with full simulation using MATLAB. The design and implementation of the proposed MDF on FPGA (XILINX Virtex XCV800 BG432-4), using VHSIC Hardware Description Language (VHDL), has been introduced. The implementation areas of the proposed filter stages are compared. Using CIC-HB technique saves 18% of the design area, compared to using six stages HB decimation filters.

  4. Delay model and performance testing for FPGA carry chain TDC

    International Nuclear Information System (INIS)

    Kang Xiaowen; Liu Yaqiang; Cui Junjian Yang Zhangcan; Jin Yongjie

    2011-01-01

    Time-of-flight (TOF) information would improve the performance of PET (position emission tomography). TDC design is a key technique. It proposed Carry Chain TDC Delay model. Through changing the significant delay parameter of model, paper compared the difference of TDC performance, and finally realized Time-to-Digital Convertor (TDC) based on Carry Chain Method using FPGA EP2C20Q240C8N with 69 ps LSB, max error below 2 LSB. Such result could meet the TOF demand. It also proposed a Coaxial Cable Measuring method for TDC testing, without High-precision test equipment. (authors)

  5. IMPLEMENTATION OF SERIAL AND PARALLEL BUBBLE SORT ON FPGA

    Directory of Open Access Journals (Sweden)

    Dwi Marhaendro Jati Purnomo

    2016-06-01

    Full Text Available Sorting is common process in computational world. Its utilization are on many fields from research to industry. There are many sorting algorithm in nowadays. One of the simplest yet powerful is bubble sort. In this study, bubble sort is implemented on FPGA. The implementation was taken on serial and parallel approach. Serial and parallel bubble sort then compared by means of its memory, execution time, and utility which comprises slices and LUTs. The experiments show that serial bubble sort required smaller memory as well as utility compared to parallel bubble sort. Meanwhile, parallel bubble sort performed faster than serial bubble sort

  6. Enhanced Temperature Control Method Using ANFIS with FPGA

    Directory of Open Access Journals (Sweden)

    Chiung-Wei Huang

    2014-01-01

    Full Text Available Temperature control in etching process is important for semiconductor manufacturing technology. However, pressure variations in vacuum chamber results in a change in temperature, worsening the accuracy of the temperature of the wafer and the speed and quality of the etching process. This work develops an adaptive network-based fuzzy inference system (ANFIS using a field-programmable gate array (FPGA to improve the effectiveness. The proposed method adjusts every membership function to keep the temperature in the chamber stable. The improvement of the proposed algorithm is confirmed using a medium vacuum (MV inductively-coupled plasma- (ICP- type etcher.

  7. Development of Integral Environment in Matlab/Simulink for FPGA

    Directory of Open Access Journals (Sweden)

    Dejan Jokic

    2014-01-01

    Full Text Available In this paper is presented realization of integral environment which consists of software and hardware components for the purpose of programming Altera DE boards. Software component is Toolbox FPGA Real Time which enables simple use of Matlab/Simulink with DSP Builder for the purpose of realization of control structures. Hardware component are Interface cards that make connection of DE board with object of control possible. Simulation and experimental results of DC motor control indicate the usefulness of the proposed concept.

  8. Energy Efficient FPGA based Hardware Accelerators for Financial Applications

    DEFF Research Database (Denmark)

    Kenn Toft, Jakob; Nannarelli, Alberto

    2014-01-01

    Field Programmable Gate Arrays (FPGAs) based accelerators are very suitable to implement application-specific processors using uncommon operations or number systems. In this work, we design FPGA-based accelerators for two financial computations with different characteristics and we compare...... the accelerator performance and energy consumption to a software execution of the application. The experimental results show that significant speed-up and energy savings, can be obtained for large data sets by using the accelerator at expenses of a longer development time....

  9. FPGA curved track fitter with very low resource usage

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jin-Yuan; Wang, M.; Gottschalk, E.; Shi, Z.; /Fermilab

    2006-11-01

    Standard least-squares curved track fitting process is tailored for FPGA implementation. The coefficients in the fitting matrices are carefully chosen so that only shift and accumulation operations are used in the process. The divisions and full multiplications are eliminated. Comparison in an application example shows that the fitting errors of the low resource usage implementation are less than 4% bigger than the fitting errors of the exact least-squares algorithm. The implementation is suitable for low-cost, low-power applications such as high energy physics detector trigger systems.

  10. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    . Zulfikar

    2012-10-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  11. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    Zulfikar .

    2015-05-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  12. FPGA implementation of adaptive beamforming in hearing aids.

    Science.gov (United States)

    Samtani, Kartik; Thomas, Jobin; Varma, G Abhinav; Sumam, David S; Deepu, S P

    2017-07-01

    Beamforming is a spatial filtering technique used in hearing aids to improve target sound reception by reducing interference from other directions. In this paper we propose improvements in an existing architecture present for two omnidirectional microphone array based adaptive beamforming for hearing aid applications and implement the same on Xilinx Artix 7 FPGA using VHDL coding and Xilinx Vivado ® 2015.2. The nulls are introduced in particular directions by combination of two fixed polar patterns. This combination can be adaptively controlled to steer the null in the direction of noise. The beamform patterns and improvements in SNR values obtained from experiments in a conference room environment are analyzed.

  13. FPGA Based Low Power ROM Design Using Capacitance Scaling

    DEFF Research Database (Denmark)

    Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

    2015-01-01

    An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

  14. FPGA Implementation of Video Transmission System Based on LTE

    Directory of Open Access Journals (Sweden)

    Lu Yan

    2015-01-01

    Full Text Available In order to support high-definition video transmission, an implementation of video transmission system based on Long Term Evolution is designed. This system is developed on Xilinx Virtex-6 FPGA ML605 Evaluation Board. The paper elaborates the features of baseband link designed in Xilinx ISE and protocol stack designed in Xilinx SDK, and introduces the process of setting up hardware and software platform in Xilinx XPS. According to test, this system consumes less hardware resource and is able to transmit bidirectional video clearly and stably.

  15. LAPACKrc: Fast linear algebra kernels/solvers for FPGA accelerators

    International Nuclear Information System (INIS)

    Gonzalez, Juan; Nunez, Rafael C

    2009-01-01

    We present LAPACKrc, a family of FPGA-based linear algebra solvers able to achieve more than 100x speedup per commodity processor on certain problems. LAPACKrc subsumes some of the LAPACK and ScaLAPACK functionalities, and it also incorporates sparse direct and iterative matrix solvers. Current LAPACKrc prototypes demonstrate between 40x-150x speedup compared against top-of-the-line hardware/software systems. A technology roadmap is in place to validate current performance of LAPACKrc in HPC applications, and to increase the computational throughput by factors of hundreds within the next few years.

  16. SRF cavity testing using a FPGA Self Excited Loop

    Energy Technology Data Exchange (ETDEWEB)

    Ben-Zvi, I. [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2017-08-30

    Various authors have previously studied the theory and practice of cavity testing, notably an extensive treatment by Powers [1] and Padamsee [2]. The advent of the digital Low Level RF (LLRF) electronics based on Field Programmable Logic Arrays (FPGA) provides various improvements over the rather complex systems used in the past as well as enabling new measurement techniques.In this document we reintroduce a technique that seems to have fallen out of practice in recent times, that is obtaining the coupling constant β through measurements from just one port, the reflected power port, of the directional coupler placed in front of the cavity.

  17. SRF cavity testing using a FPGA Self Excited Loop

    CERN Document Server

    Ben-Zvi, Ilan

    2018-01-01

    This document provides a detailed description of procedures for very-high precision calibration and testing of superconducting RF cavities using digital Low-Level RF (LLRF) electronics based on Field Programmable Gate Arrays (FPGA). The use of a Self-Excited Loop with an innovative procedure for fast turn-on allows the measurement of the forward, reflected and transmitted power from a single port of the directional coupler in front of the cavity, thus eliminating certain measurement errors. Various procedures for measuring the quality factor as a function of cavity fields are described, including a single RF pulse technique. Errors are estimated for the measurements.

  18. The Mechanical Transient Process at Asynchronous Motor Oscillating Mode

    Science.gov (United States)

    Antonovičs, Uldis; Bražis, Viesturs; Greivulis, Jānis

    2009-01-01

    The research object is squirrel-cage asynchronous motor connected to single-phase sinusoidal. There are shown, that by connecting to the stator windings a certain sequence of half-period positive and negative voltage, a motor rotor is rotated, but three times slower than in the three-phase mode. Changing the connecting sequence of positive and negative half-period voltage to stator windings, motor can work in various oscillating modes. It is tested experimentally. The mechanical transient processes had been researched in rotation and oscillating modes.

  19. Asynchronous variational integration using continuous assumed gradient elements.

    Science.gov (United States)

    Wolff, Sebastian; Bucher, Christian

    2013-03-01

    Asynchronous variational integration (AVI) is a tool which improves the numerical efficiency of explicit time stepping schemes when applied to finite element meshes with local spatial refinement. This is achieved by associating an individual time step length to each spatial domain. Furthermore, long-term stability is ensured by its variational structure. This article presents AVI in the context of finite elements based on a weakened weak form (W2) Liu (2009) [1], exemplified by continuous assumed gradient elements Wolff and Bucher (2011) [2]. The article presents the main ideas of the modified AVI, gives implementation notes and a recipe for estimating the critical time step.

  20. Electrotechnics - AC motors. Asynchronous and brush-less motors - Lecture and exercises with solutions; Electrotechnique - Moteurs a courant alternatif. Moteurs asynchrones et brushless - Cours et problemes resolus

    Energy Technology Data Exchange (ETDEWEB)

    Jacob, D.

    2005-07-01

    This book proposes a presentation of AC electric motors essentially based on physics and technology. Its originality consists in avoiding to use mathematical formulations (like Park's transformation). The modeling retained, which only uses magnetic momentum, magnetic fields and reluctance concepts, leads simply and naturally to the vectorial control principle. The book develops some lecture elements which includes some topics rarely considered like the dimensioning of an asynchronous motor or of a single-phase brush-less motor. Experimental results illustrate the physical phenomena described and many original problems are resolved and commented at the end of each chapter. Content: signals and systems in electrotechnics, torque and rotating magnetic fields generation, asynchronous machine in permanent regime, speed variation of the asynchronous motor, special asynchronous motors, synchronous machine in permanent regime, brush-less motor, note about step motors, note about inverters, index. (J.S.)

  1. Towards behavioral synthesis of asynchronous circuits - an implementation template targeting syntax directed compilation

    DEFF Research Database (Denmark)

    Nielsen, Sune Fallgaard; Sparsø, Jens; Madsen, Jan

    2004-01-01

    This paper presents a method for behavioral synthesis of asynchronous circuits. Our approach aims at providing a synthesis flow which is very similar to what is found in existing synchronous design tools. We adapt the synchronous behavioral synthesis abstraction into the asynchronous handshake...

  2. Using Television Sitcoms to Facilitate Asynchronous Discussions in the Online Communication Course

    Science.gov (United States)

    Tolman, Elizabeth; Asbury, Bryan

    2012-01-01

    Asynchronous discussions are a useful instructional resource in the online communication course. In discussion groups students have the opportunity to actively participate and interact with students and the instructor. Asynchronous communication allows for flexibility because "participants can interact with significant amounts of time between…

  3. The design of an asynchronous Tiny RISC TM/TR4101 microprocessor core

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Jensen, P.; Korger, P.

    1998-01-01

    This paper presents the design of an asynchronous version of the TR4101 embedded microprocessor core developed by LSI Logic Inc. The asynchronous processor, called ARISC, was designed using the same CAD tools and the same standard cell library that was used to implement the TR4101. The paper repo...

  4. A new FPGA architecture suitable for DSP applications

    Energy Technology Data Exchange (ETDEWEB)

    Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan, E-mail: 071021037@fudan.edu.cn [ASIC and System State Key Laboratory, Fudan University, Shanghai 201203 (China)

    2011-05-15

    A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 {mu}m CMOS technology successfully. The die size is 6.3 x 4.5 mm{sup 2} with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

  5. Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform

    Directory of Open Access Journals (Sweden)

    Vishwa Seneviratne

    2017-07-01

    Full Text Available Antenna array-based multi-dimensional infinite-impulse response (IIR digital beamformers are employed in a multitude of radio frequency (RF applications ranging from electronically-scanned radar, radio telescopes, long-range detection and target tracking. A method to design 3D IIR beam filters using 2D IIR beam filters is described. A cascaded 2D IIR beam filter architecture is proposed based on systolic array architecture as an alternative for an existing radar application. Differential-form transfer function and polyphase structures are employed in the design to gain an increase in the speed of operation to gigahertz range. The feasibility of practical implementation of a 4-phase polyphase 2D IIR beam filter is explored. A digital hardware prototype is designed, implemented and tested using a ROACH-2 Field Programmable Gate Array (FPGA platform fitted with a Xilinx Virtex-6 SX475T FPGA chip and multi-input analog-to-digital converters (ADC boards set to a maximum sampling rate of 960 MHz. The article describes a method to build a 3D IIR beamformer using polyphase structures. A comparison of technical specifications of an existing radar application based on phased-array and the proposed 3D IIR beamformer is also explained to illustrate the proposed method to be a better alternative for such applications.

  6. An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator.

    Science.gov (United States)

    Wang, Runchun M; Thakur, Chetan S; van Schaik, André

    2018-01-01

    This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF) neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons). This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

  7. An FPGA Implementation of Secured Steganography Communication System

    Directory of Open Access Journals (Sweden)

    Ahlam Fadhil Mahmood

    2013-04-01

    Full Text Available     Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.        In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.      This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secures data transmission applications

  8. An FPGA Implementation of Secured Steganography Communication System

    Directory of Open Access Journals (Sweden)

    Ahlam Mahmood

    2014-04-01

    Full Text Available Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.  In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.  This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secure data transmission applications

  9. FPGA platform for MEMS Disc Resonance Gyroscope (DRG) control

    Science.gov (United States)

    Keymeulen, Didier; Peay, Chris; Foor, David; Trung, Tran; Bakhshi, Alireza; Withington, Phil; Yee, Karl; Terrile, Rich

    2008-04-01

    Inertial navigation systems based upon optical gyroscopes tend to be expensive, large, power consumptive, and are not long lived. Micro-Electromechanical Systems (MEMS) based gyros do not have these shortcomings; however, until recently, the performance of MEMS based gyros had been below navigation grade. Boeing and JPL have been cooperating since 1997 to develop high performance MEMS gyroscopes for miniature, low power space Inertial Reference Unit applications. The efforts resulted in demonstration of a Post Resonator Gyroscope (PRG). This experience led to the more compact Disc Resonator Gyroscope (DRG) for further reduced size and power with potentially increased performance. Currently, the mass, volume and power of the DRG are dominated by the size of the electronics. This paper will detail the FPGA based digital electronics architecture and its implementation for the DRG which will allow reduction of size and power and will increase performance through a reduction in electronics noise. Using the digital control based on FPGA, we can program and modify in real-time the control loop to adapt to the specificity of each particular gyro and the change of the mechanical characteristic of the gyro during its life time.

  10. Optimizing latency in Xilinx FPGA implementations of the GBT

    International Nuclear Information System (INIS)

    Muschter, S; Bohm, C; Baron, S; Soos, C; Cachemiche, J-P

    2010-01-01

    The GigaBit Transceiver (GBT) system has been developed to replace the Timing, Trigger and Control (TTC) system, currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation. This code was optimized for resource utilization, as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

  11. FPGA based algorithms for data reduction at Belle II

    Energy Technology Data Exchange (ETDEWEB)

    Muenchow, David; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liu, Ming; Spruck, Bjoern [II. Physikalisches Institut, Universitaet Giessen (Germany)

    2011-07-01

    Belle II, the upgrade of the existing Belle experiment at Super-KEKB in Tsukuba, Japan, is an asymmetric e{sup +}e{sup -} collider with a design luminosity of 8.10{sup 35}cm{sup -2}s{sup -1}. At Belle II the estimated event rate is {<=}30 kHz. The resulting data rate at the Pixel Detector (PXD) will be {<=}7.2 GB/s. This data rate needs to be reduced to be able to process and store the data. A region of interest (ROI) selection is based upon two mechanisms. a.) a tracklet finder using the silicon strip detector and b.) the HLT using all other Belle II subdetectors. These ROIs and the pixel data are forwarded to an FPGA based Compute Node for processing. Here a VHDL based algorithm on FPGA with the benefit of pipelining and parallelisation will be implemented. For a fast data handling we developed a dedicated memory management system for buffering and storing the data. The status of the implementation and performance tests of the memory manager and data reduction algorithm is presented.

  12. FPGA Implementation of a Simple 3D Graphics Pipeline

    Directory of Open Access Journals (Sweden)

    Vladimir Kasik

    2015-01-01

    Full Text Available Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGA-based implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance Computing.

  13. Optimizing latency in Xilinx FPGA implementations of the GBT

    CERN Document Server

    Muschter, S; Bohm, C; Cachemiche, J-P; Baron, S

    2010-01-01

    The GigaBit Transceiver (GBT) {[}1] system has been developed to replace the Timing, Trigger and Control (TTC) system {[}2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation {[}3]. This code was optimized for resource utilization {[}4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The la...

  14. Optimizing latency in Xilinx FPGA implementations of the GBT

    Science.gov (United States)

    Muschter, S.; Baron, S.; Bohm, C.; Cachemiche, J.-P.; Soos, C.

    2010-12-01

    The GigaBit Transceiver (GBT) [1] system has been developed to replace the Timing, Trigger and Control (TTC) system [2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation [3]. This code was optimized for resource utilization [4], as the GBT protocol is very demanding. It was not, however, optimized for latency — which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The latency optimization results were compared with measurement results from a Virtex 6 ML605 development board [5] equipped with a XC6VLX240T with speedgrade-1 and the package FF1156. Bit error rate tests were also performed to ensure an error free operation. The two final optimizations were analyzed for utilization and compared with the original code, distributed in the Starter Kit.

  15. A Sea-of-Gates Style FPGA Placement Algorithm

    Directory of Open Access Journals (Sweden)

    Kalapi Roy

    1996-01-01

    Full Text Available Field Programmable Gate Arrays (FPGAs have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool developed specifically for this architecture.

  16. FPGA Dynamic Power Minimization through Placement and Routing Constraints

    Directory of Open Access Journals (Sweden)

    Deepak Agarwal

    2006-08-01

    Full Text Available Field-programmable gate arrays (FPGAs are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuits mapped into 0.12 μm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.

  17. Anti Theft Mechanism Through Face recognition Using FPGA

    Science.gov (United States)

    Sundari, Y. B. T.; Laxminarayana, G.; Laxmi, G. Vijaya

    2012-11-01

    The use of vehicle is must for everyone. At the same time, protection from theft is also very important. Prevention of vehicle theft can be done remotely by an authorized person. The location of the car can be found by using GPS and GSM controlled by FPGA. In this paper, face recognition is used to identify the persons and comparison is done with the preloaded faces for authorization. The vehicle will start only when the authorized personís face is identified. In the event of theft attempt or unauthorized personís trial to drive the vehicle, an MMS/SMS will be sent to the owner along with the location. Then the authorized person can alert the security personnel for tracking and catching the vehicle. For face recognition, a Principal Component Analysis (PCA) algorithm is developed using MATLAB. The control technique for GPS and GSM is developed using VHDL over SPTRAN 3E FPGA. The MMS sending method is written in VB6.0. The proposed application can be implemented with some modifications in the systems wherever the face recognition or detection is needed like, airports, international borders, banking applications etc.

  18. A shared synapse architecture for efficient FPGA implementation of autoencoders.

    Science.gov (United States)

    Suzuki, Akihiro; Morie, Takashi; Tamukoh, Hakaru

    2018-01-01

    This paper proposes a shared synapse architecture for autoencoders (AEs), and implements an AE with the proposed architecture as a digital circuit on a field-programmable gate array (FPGA). In the proposed architecture, the values of the synapse weights are shared between the synapses of an input and a hidden layer, and between the synapses of a hidden and an output layer. This architecture utilizes less of the limited resources of an FPGA than an architecture which does not share the synapse weights, and reduces the amount of synapse modules used by half. For the proposed circuit to be implemented into various types of AEs, it utilizes three kinds of parameters; one to change the number of layers' units, one to change the bit width of an internal value, and a learning rate. By altering a network configuration using these parameters, the proposed architecture can be used to construct a stacked AE. The proposed circuits are logically synthesized, and the number of their resources is determined. Our experimental results show that single and stacked AE circuits utilizing the proposed shared synapse architecture operate as regular AEs and as regular stacked AEs. The scalability of the proposed circuit and the relationship between the bit widths and the learning results are also determined. The clock cycles of the proposed circuits are formulated, and this formula is used to estimate the theoretical performance of the circuit when the circuit is used to construct arbitrary networks.

  19. Algebraic Number Precoded OFDM Transmission for Asynchronous Cooperative Multirelay Networks

    Directory of Open Access Journals (Sweden)

    Hua Jiang

    2014-01-01

    Full Text Available This paper proposes a space-time block coding (STBC transmission scheme for asynchronous cooperative systems. By combination of rotated complex constellations and Hadamard transform, these constructed codes are capable of achieving full cooperative diversity with the analysis of the pairwise error probability (PEP. Due to the asynchronous characteristic of cooperative systems, orthogonal frequency division multiplexing (OFDM technique with cyclic prefix (CP is adopted for combating timing delays from relay nodes. The total transmit power across the entire network is fixed and appropriate power allocation can be implemented to optimize the network performance. The relay nodes do not require decoding and demodulation operation, resulting in a low complexity. Besides, there is no delay for forwarding the OFDM symbols to the destination node. At the destination node the received signals have the corresponding STBC structure on each subcarrier. In order to reduce the decoding complexity, the sphere decoder is implemented for fast data decoding. Bit error rate (BER performance demonstrates the effectiveness of the proposed scheme.

  20. Asynchronous Channel-Hopping Scheme under Jamming Attacks

    Directory of Open Access Journals (Sweden)

    Yongchul Kim

    2018-01-01

    Full Text Available Cognitive radio networks (CRNs are considered an attractive technology to mitigate inefficiency in the usage of licensed spectrum. CRNs allow the secondary users (SUs to access the unused licensed spectrum and use a blind rendezvous process to establish communication links between SUs. In particular, quorum-based channel-hopping (CH schemes have been studied recently to provide guaranteed blind rendezvous in decentralized CRNs without using global time synchronization. However, these schemes remain vulnerable to jamming attacks. In this paper, we first analyze the limitations of quorum-based rendezvous schemes called asynchronous channel hopping (ACH. Then, we introduce a novel sequence sensing jamming attack (SSJA model in which a sophisticated jammer can dramatically reduce the rendezvous success rates of ACH schemes. In addition, we propose a fast and robust asynchronous rendezvous scheme (FRARS that can significantly enhance robustness under jamming attacks. Our numerical results demonstrate that the performance of the proposed scheme vastly outperforms the ACH scheme when there are security concerns about a sequence sensing jammer.

  1. Formation of the wide asynchronous binary asteroid population

    International Nuclear Information System (INIS)

    Jacobson, Seth A.; Scheeres, Daniel J.; McMahon, Jay

    2014-01-01

    We propose and analyze a new mechanism for the formation of the wide asynchronous binary population. These binary asteroids have wide semimajor axes relative to most near-Earth and main belt asteroid systems. Confirmed members have rapidly rotating primaries and satellites that are not tidally locked. Previously suggested formation mechanisms from impact ejecta, from planetary flybys, and directly from rotational fission events cannot satisfy all of the observations. The newly hypothesized mechanism works as follows: (1) these systems are formed from rotational fission, (2) their satellites are tidally locked, (3) their orbits are expanded by the binary Yarkovsky-O'Keefe-Radzievskii-Paddack (BYORP) effect, (4) their satellites desynchronize as a result of the adiabatic invariance between the libration of the secondary and the mutual orbit, and (5) the secondary avoids resynchronization because of the YORP effect. This seemingly complex chain of events is a natural pathway for binaries with satellites that have particular shapes, which define the BYORP effect torque that acts on the system. After detailing the theory, we analyze each of the wide asynchronous binary members and candidates to assess their most likely formation mechanism. Finally, we suggest possible future observations to check and constrain our hypothesis.

  2. An Asynchronous IEEE Floating-Point Arithmetic Unit

    Directory of Open Access Journals (Sweden)

    Joel R. Noche

    2007-12-01

    Full Text Available An asynchronous floating-point arithmetic unit is designed and tested at the transistor level usingCadence software. It uses CMOS (complementary metal oxide semiconductor and DCVS (differentialcascode voltage switch logic in a 0.35 µm process using a 3.3 V supply voltage, with dual-rail data andsingle-rail control signals using four-phase handshaking.Using 17,085 transistors, the unit handles single-precision (32-bit addition/subtraction, multiplication,division, and remainder using the IEEE 754-1985 Standard for Binary Floating-Point Arithmetic, withrounding and other operations to be handled by separate hardware or software. Division and remainderare done using a restoring subtractive algorithm; multiplication uses an additive algorithm. Exceptionsare noted by flags (and not trap handlers and the output is in single-precision.Previous work on asynchronous floating-point arithmetic units have mostly focused on single operationssuch as division. This is the first work to the authors' knowledge that can perform floating-point addition,multiplication, division, and remainder using a common datapath.

  3. Asynchronous Task-Based Polar Decomposition on Manycore Architectures

    KAUST Repository

    Sukkari, Dalal

    2016-10-25

    This paper introduces the first asynchronous, task-based implementation of the polar decomposition on manycore architectures. Based on a new formulation of the iterative QR dynamically-weighted Halley algorithm (QDWH) for the calculation of the polar decomposition, the proposed implementation replaces the original and hostile LU factorization for the condition number estimator by the more adequate QR factorization to enable software portability across various architectures. Relying on fine-grained computations, the novel task-based implementation is also capable of taking advantage of the identity structure of the matrix involved during the QDWH iterations, which decreases the overall algorithmic complexity. Furthermore, the artifactual synchronization points have been severely weakened compared to previous implementations, unveiling look-ahead opportunities for better hardware occupancy. The overall QDWH-based polar decomposition can then be represented as a directed acyclic graph (DAG), where nodes represent computational tasks and edges define the inter-task data dependencies. The StarPU dynamic runtime system is employed to traverse the DAG, to track the various data dependencies and to asynchronously schedule the computational tasks on the underlying hardware resources, resulting in an out-of-order task scheduling. Benchmarking experiments show significant improvements against existing state-of-the-art high performance implementations (i.e., Intel MKL and Elemental) for the polar decomposition on latest shared-memory vendors\\' systems (i.e., Intel Haswell/Broadwell/Knights Landing, NVIDIA K80/P100 GPUs and IBM Power8), while maintaining high numerical accuracy.

  4. Continuous EEG signal analysis for asynchronous BCI application.

    Science.gov (United States)

    Hsu, Wei-Yen

    2011-08-01

    In this study, we propose a two-stage recognition system for continuous analysis of electroencephalogram (EEG) signals. An independent component analysis (ICA) and correlation coefficient are used to automatically eliminate the electrooculography (EOG) artifacts. Based on the continuous wavelet transform (CWT) and Student's two-sample t-statistics, active segment selection then detects the location of active segment in the time-frequency domain. Next, multiresolution fractal feature vectors (MFFVs) are extracted with the proposed modified fractal dimension from wavelet data. Finally, the support vector machine (SVM) is adopted for the robust classification of MFFVs. The EEG signals are continuously analyzed in 1-s segments, and every 0.5 second moves forward to simulate asynchronous BCI works in the two-stage recognition architecture. The segment is first recognized as lifted or not in the first stage, and then is classified as left or right finger lifting at stage two if the segment is recognized as lifting in the first stage. Several statistical analyses are used to evaluate the performance of the proposed system. The results indicate that it is a promising system in the applications of asynchronous BCI work.

  5. Spatiotemporal Features for Asynchronous Event-based Data

    Directory of Open Access Journals (Sweden)

    Xavier eLagorce

    2015-02-01

    Full Text Available Bio-inspired asynchronous event-based vision sensors are currently introducing a paradigm shift in visual information processing. These new sensors rely on a stimulus-driven principle of light acquisition similar to biological retinas. They are event-driven and fully asynchronous, thereby reducing redundancy and encoding exact times of input signal changes, leading to a very precise temporal resolution. Approaches for higher-level computer vision often rely on the realiable detection of features in visual frames, but similar definitions of features for the novel dynamic and event-based visual input representation of silicon retinas have so far been lacking. This article addresses the problem of learning and recognizing features for event-based vision sensors, which capture properties of truly spatiotemporal volumes of sparse visual event information. A novel computational architecture for learning and encoding spatiotemporal features is introduced based on a set of predictive recurrent reservoir networks, competing via winner-take-all selection. Features are learned in an unsupervised manner from real-world input recorded with event-based vision sensors. It is shown that the networks in the architecture learn distinct and task-specific dynamic visual features, and can predict their trajectories over time.

  6. A Parallel Particle Swarm Optimization Algorithm Accelerated by Asynchronous Evaluations

    Science.gov (United States)

    Venter, Gerhard; Sobieszczanski-Sobieski, Jaroslaw

    2005-01-01

    A parallel Particle Swarm Optimization (PSO) algorithm is presented. Particle swarm optimization is a fairly recent addition to the family of non-gradient based, probabilistic search algorithms that is based on a simplified social model and is closely tied to swarming theory. Although PSO algorithms present several attractive properties to the designer, they are plagued by high computational cost as measured by elapsed time. One approach to reduce the elapsed time is to make use of coarse-grained parallelization to evaluate the design points. Previous parallel PSO algorithms were mostly implemented in a synchronous manner, where all design points within a design iteration are evaluated before the next iteration is started. This approach leads to poor parallel speedup in cases where a heterogeneous parallel environment is used and/or where the analysis time depends on the design point being analyzed. This paper introduces an asynchronous parallel PSO algorithm that greatly improves the parallel e ciency. The asynchronous algorithm is benchmarked on a cluster assembled of Apple Macintosh G5 desktop computers, using the multi-disciplinary optimization of a typical transport aircraft wing as an example.

  7. Asynchronous cracking with dissimilar paths in multilayer graphene.

    Science.gov (United States)

    Jang, Bongkyun; Kim, Byungwoon; Kim, Jae-Hyun; Lee, Hak-Joo; Sumigawa, Takashi; Kitamura, Takayuki

    2017-11-16

    Multilayer graphene consists of a stack of single-atomic-thick monolayer graphene sheets bound with π-π interactions and is a fascinating model material opening up a new field of fracture mechanics. In this study, fracture behavior of single-crystalline multilayer graphene was investigated using an in situ mode I fracture test under a scanning electron microscope, and abnormal crack propagation in multilayer graphene was identified for the first time. The fracture toughness of graphene was determined from the measured load-displacement curves and the realistic finite element modelling of specimen geometries. Nonlinear fracture behavior of the multilayer graphene is discussed based on nonlinear elastic fracture mechanics. In situ scanning electron microscope images obtained during the fracture test showed asynchronous crack propagation along independent paths, causing interlayer shear stress and slippages. We also found that energy dissipation by interlayer slippages between the graphene layers is the reason for the enhanced fracture toughness of multilayer graphene. The asynchronous cracking with independent paths is a unique cracking and toughening mechanism for single-crystalline multilayer graphene, which is not observed for the monolayer graphene. This could provide a useful insight for the design and development of graphene-based composite materials for structural applications.

  8. Parallel asynchronous hardware implementation of image processing algorithms

    Science.gov (United States)

    Coon, Darryl D.; Perera, A. G. U.

    1990-01-01

    Research is being carried out on hardware for a new approach to focal plane processing. The hardware involves silicon injection mode devices. These devices provide a natural basis for parallel asynchronous focal plane image preprocessing. The simplicity and novel properties of the devices would permit an independent analog processing channel to be dedicated to every pixel. A laminar architecture built from arrays of the devices would form a two-dimensional (2-D) array processor with a 2-D array of inputs located directly behind a focal plane detector array. A 2-D image data stream would propagate in neuron-like asynchronous pulse-coded form through the laminar processor. No multiplexing, digitization, or serial processing would occur in the preprocessing state. High performance is expected, based on pulse coding of input currents down to one picoampere with noise referred to input of about 10 femtoamperes. Linear pulse coding has been observed for input currents ranging up to seven orders of magnitude. Low power requirements suggest utility in space and in conjunction with very large arrays. Very low dark current and multispectral capability are possible because of hardware compatibility with the cryogenic environment of high performance detector arrays. The aforementioned hardware development effort is aimed at systems which would integrate image acquisition and image processing.

  9. A Correctness Verification Technique for Commercial FPGA Synthesis Tools

    International Nuclear Information System (INIS)

    Kim, Eui Sub; Yoo, Jun Beom; Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo

    2014-01-01

    Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

  10. A Correctness Verification Technique for Commercial FPGA Synthesis Tools

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2014-10-15

    Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

  11. Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia; Sparsø, Jens; Sørensen, Rasmus Bo

    2013-01-01

    In this paper we explore the design of an asynchronous router for a time-division-multiplexed (TDM) network-on-chip (NOC) that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either....... This adds hardware complexity and increases area and power consumption. We propose to use asynchronous routers in order to achieve a simpler, more robust and globally-asynchronous NOC, and this represents an unexplored point in the design space. The paper presents a range of alternative router designs. All...... routers have been synthesized for a 65nm CMOS technology, and the paper reports post-layout figures for area, speed and energy and compares the asynchronous designs with an existing mesochronous clocked router. The results show that an asynchronous router is 2 times smaller, marginally slower...

  12. Development of FPGA-based safety-related I and C systems

    Energy Technology Data Exchange (ETDEWEB)

    Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S. [08, Shinsugita-cho, Isogo-ku, Yokohama 235-8523 (Japan); 1, Toshiba-cho, Fuchu, Tokyo 183-8511 (Japan)

    2006-07-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  13. Development of FPGA-based safety-related instrumentation and control systems

    Energy Technology Data Exchange (ETDEWEB)

    Oda, N.; Tanaka, A.; Izumi, M.; Tarumi, T.; Sato, T. [Toshiba Corporation, Isogo Nuclear Engineering Center, Yokohama (Japan)

    2004-07-01

    Toshiba has developed systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related instrumentation and control systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  14. Verification of FPGA-based NPP I and C systems. General approach and techniques

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Reva, Lubov; Siora, Alexander

    2011-01-01

    This paper presents a general approach and techniques for design and verification of Field Programmable Gates Arrays (FPGA)-based Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP). Appropriate regulatory documents used for I and C systems design, development, verification and validation (V and V) are discussed considering the latest international standards and guidelines. Typical development and V and V processes of FPGA electronic design for FPGA-based NPP I and C systems are presented. Some safety-related features of implementation process are discussed. Corresponding development artifacts, related to design and implementation activities are outlined. An approach to test-based verification of FPGA electronic design algorithms, used in FPGA-based reactor trip systems is proposed. The results of application of test-based techniques for assessment of FPGA electronic design algorithms for reactor trip system (RTS) produced by Research and Production Corporation (RPC) 'Radiy' are presented. Some principles of invariant-oriented verification for FPGA-based safety-critical systems are outlined. (author)

  15. An evaluation and acceptance of COTS software for FPGA-based controllers in NPPS

    International Nuclear Information System (INIS)

    Jung, Sejin; Kim, Eui-Sub; Yoo, Junbeom; Kim, Jang-Yeol; Choi, Jong Gyun

    2016-01-01

    Highlights: • All direct/indirect COTS SW should be dedicated. • FPGA synthesis tools are important for the safety of new digital I&Cs. • No standards/reports are yet available to deal with the indirect SW – FPGA synthesis tools. • This paper proposes a new evaluation/acceptance process and criteria for indirect SW. - Abstract: FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of PLC (Programmable Logic Controller)-based digital I&C (Instrumentation & Control). Software aspect of FPGA development encompasses several commercial tools such as logic synthesis and P&R (Place & Route), which should be first dedicated in accordance with domestic standards based on EPRI NP-5652. Even if a state-of-the-art supplementary EPRI TR-1025243 makes an effort, the dedication of indirect COTS (Commercial Off-The-Shelf) SW such as FPGA logic synthesis tools has still caused a dispute. This paper proposes an acceptance process and evaluation criteria, specific to COTS SW, not commercial-grade direct items. It specifically incorporates indirect COTS SW and also provides categorized evaluation criteria for acceptance. It provides an explicit linkage between acceptance methods (Verification and Validation techniques) and evaluation criteria, too. We tried to perform the evaluation and acceptance process upon a commercial FPGA logic synthesis tool being used to develop a new FPGA-based digital I&C in Korea, and could confirm its applicability.

  16. Logic qualification of FPGA-based safety-related I and C systems

    International Nuclear Information System (INIS)

    Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

    2009-01-01

    We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

  17. Desgin of On-line Monitoring Device for MOA (Metal Oxide Arrestor Based on FPGA and C8051F

    Directory of Open Access Journals (Sweden)

    Xiaotong YAO

    2014-10-01

    Full Text Available Monitoring of metal oxide surge arresters (MOA due to aging, moisture and other components cause increased resistive current. Through a lot of practices, it has been proved that in the early days, MOA insulation damage and current increase is not obvious. The accurate working conditions of the MOA are also not obvious but it can reflect the aging or moisture of MOA. When the resistive current of the fundamental component increases, there is no increment in the harmonic components that is the general performance of a serious or moisture contamination. In the same way when the resistive current of harmonic components increases, the fundamental component is not increased and it is the general performance of aging. Therefore, this paper designed an experiment-based FPGA and C8051F-line monitoring device. This device uses resistive current as a detection target. The main monitoring parameters are the fundamental and peak value of resistive current, third harmonic content of the leakage current, phase angle difference and power consumption. Through laboratory tests, the device can be used with a network arrester line monitoring, maintenance, reduce the economic losses caused by power outages and improve the distribution network reliability.

  18. Carry-chain propagation delay impacts on resolution of FPGA-based TDC

    International Nuclear Information System (INIS)

    Dong Lei; Yang Junfeng; Song Kezhu

    2014-01-01

    The architecture of carry chains in Field-Programmable Gate Array (FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter (TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy. (authors)

  19. Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

    International Nuclear Information System (INIS)

    Pappas, I; Kalenteridis, V; Vassiliadis, N; Pournara, H; Siozios, K; Koutroumpezis, G; Tatas, K; Nikolaidis, S; Siskos, S; Soudris, D J; Thanailakis, A

    2005-01-01

    A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 μm CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools

  20. Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

    Energy Technology Data Exchange (ETDEWEB)

    Pappas, I [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Kalenteridis, V [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Vassiliadis, N [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Pournara, H [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siozios, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Koutroumpezis, G [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Tatas, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Nikolaidis, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siskos, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Soudris, D J [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Thanailakis, A [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece)

    2005-01-01

    A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 {mu}m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

  1. Development of γ dose rate monitor based on FPGA and single-chip microcomputer

    International Nuclear Information System (INIS)

    He Zhiguo; Ling Qiu; Guo Lanying; Yang Binhua

    2009-01-01

    A novelγdose rate monitor with multiple channels signal collection in which takes the FPGA as the core process chip and single-chip microcomputer as the data processor had been developed. This paper introduced the communication interface design between FPGA and MCU, and gave the data acquisition module and the function simulation chart designed by FPGA. In addition, the software and hardware design diagrams of MCU had been given in this paper. The maximum digitallization was carried on in the designing process. The experiments showed that the scheme for the system matched to the requests completely. (authors)

  2. High Performance and Energy Efficient Traffic Light Controller Design Using FPGA

    DEFF Research Database (Denmark)

    Pandey, Sujeet; Shrivastav, Vivek Kumar; Sharma, Rashmi

    2017-01-01

    and then we have analyzed power consumption for traffic light controller on different FPGA. Leakage power is in range of 97.5-99% of total power consumption by traffic light controller on Virtex-7 FPGA. Signal power, clock power and IOs power are almost negligible. Power dissipation is measured on XPOWER......In this work, Verilog is used as hardware description language for implementation of traffic light controller. It shows Red, Green and Yellow color at a predefined interval. Technology scaling is used as energy efficient technique. We have used 90nm, 65nm, 40nm and 28nm technology based FPGA...

  3. Note: Design of FPGA based system identification module with application to atomic force microscopy

    Science.gov (United States)

    Ghosal, Sayan; Pradhan, Sourav; Salapaka, Murti

    2018-05-01

    The science of system identification is widely utilized in modeling input-output relationships of diverse systems. In this article, we report field programmable gate array (FPGA) based implementation of a real-time system identification algorithm which employs forgetting factors and bias compensation techniques. The FPGA module is employed to estimate the mechanical properties of surfaces of materials at the nano-scale with an atomic force microscope (AFM). The FPGA module is user friendly which can be interfaced with commercially available AFMs. Extensive simulation and experimental results validate the design.

  4. Development of an FPGA-Based Motion Control IC for Caving Machine

    Directory of Open Access Journals (Sweden)

    Chiu-Keng Lai

    2014-03-01

    Full Text Available Since the Field Programmable Gate Arrays (FPGAs with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

  5. Frog: Asynchronous Graph Processing on GPU with Hybrid Coloring Model

    Energy Technology Data Exchange (ETDEWEB)

    Shi, Xuanhua; Luo, Xuan; Liang, Junling; Zhao, Peng; Di, Sheng; He, Bingsheng; Jin, Hai

    2018-01-01

    GPUs have been increasingly used to accelerate graph processing for complicated computational problems regarding graph theory. Many parallel graph algorithms adopt the asynchronous computing model to accelerate the iterative convergence. Unfortunately, the consistent asynchronous computing requires locking or atomic operations, leading to significant penalties/overheads when implemented on GPUs. As such, coloring algorithm is adopted to separate the vertices with potential updating conflicts, guaranteeing the consistency/correctness of the parallel processing. Common coloring algorithms, however, may suffer from low parallelism because of a large number of colors generally required for processing a large-scale graph with billions of vertices. We propose a light-weight asynchronous processing framework called Frog with a preprocessing/hybrid coloring model. The fundamental idea is based on Pareto principle (or 80-20 rule) about coloring algorithms as we observed through masses of realworld graph coloring cases. We find that a majority of vertices (about 80%) are colored with only a few colors, such that they can be read and updated in a very high degree of parallelism without violating the sequential consistency. Accordingly, our solution separates the processing of the vertices based on the distribution of colors. In this work, we mainly answer three questions: (1) how to partition the vertices in a sparse graph with maximized parallelism, (2) how to process large-scale graphs that cannot fit into GPU memory, and (3) how to reduce the overhead of data transfers on PCIe while processing each partition. We conduct experiments on real-world data (Amazon, DBLP, YouTube, RoadNet-CA, WikiTalk and Twitter) to evaluate our approach and make comparisons with well-known non-preprocessed (such as Totem, Medusa, MapGraph and Gunrock) and preprocessed (Cusha) approaches, by testing four classical algorithms (BFS, PageRank, SSSP and CC). On all the tested applications and

  6. Controlador empotrado en FPGA para Sistema Inteligente de Transporte

    Directory of Open Access Journals (Sweden)

    Alejandro José Cabrera Sarmiento

    2011-11-01

    Full Text Available 1024x768 Normal 0 21 false false false ES X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;} En el presente trabajo se expone la concepción, desarrollo e implementación de un controlador empotrado en un FPGA de Xilinx para ser utilizado en un Sistema Inteligente de Transporte (SIT. La estructura hardware del controlador está basada en la utilización de diversos módulos de propiedad intelectual del sistema de procesamiento MicroBlaze y el soporte de software está basado en la utilización del sistema operativo Petalinux. El controlador empotrado dispone de interfaces Ethernet, USB, UART, SPI e I2C para la comunicación con los diferentes niveles jerárquicos del SIT. Ha sido implementado sobre una placa de desarrollo basada en un FPGA Spartan3E de 1.200 k compuertas, ocupando un 59% de sus recursos configurables. El resto de los recursos disponibles en el FPGA permite, además de la posible actualización del controlador, la implementación hardware de algoritmos que requieren una alta velocidad de procesamiento.

  7. Extending the BEAGLE library to a multi-FPGA platform.

    Science.gov (United States)

    Jin, Zheming; Bakos, Jason D

    2013-01-19

    Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein's pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein's pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple Field Programmable Gate Array (FPGA)-based platform called the Convey HC-1. The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform's peak memory bandwidth and the implementation's memory efficiency, as 2.03 × peak bandwidth × memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a ~40X speedup when compared with BEAGLE's CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE's GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design methodology that emphasizes high memory

  8. A prototype pixel readout chip for asynchronous detection applications

    International Nuclear Information System (INIS)

    Raymond, D.M.; Hall, G.; Lewis, A.J.; Sharp, P.H.

    1991-01-01

    A two-dimensional array of amplifier cells has been fabricated as a prototype readout system for a matching array of silicon diode detectors. Each cell contains a preamplifier, shaping amplifier, comparator and analogue signal storage in an area of 300 μmx320 μm using 3 μm CMOS technology. Full size chips will be bump bonded to pixel detector arrays. Low noise and asynchronous operation are novel design features. With noise levels of less than 250 rms electrons for input capacitances up to 600 fF, pixel detectors will be suitable for autoradiography, synchrotron X-ray and high energy particle detection applications. The design of the prototype chip is presented and future developments and prospects for applications are discussed. (orig.)

  9. Asynchronous sampled-data approach for event-triggered systems

    Science.gov (United States)

    Mahmoud, Magdi S.; Memon, Azhar M.

    2017-11-01

    While aperiodically triggered network control systems save a considerable amount of communication bandwidth, they also pose challenges such as coupling between control and event-condition design, optimisation of the available resources such as control, communication and computation power, and time-delays due to computation and communication network. With this motivation, the paper presents separate designs of control and event-triggering mechanism, thus simplifying the overall analysis, asynchronous linear quadratic Gaussian controller which tackles delays and aperiodic nature of transmissions, and a novel event mechanism which compares the cost of the aperiodic system against a reference periodic implementation. The proposed scheme is simulated on a linearised wind turbine model for pitch angle control and the results show significant improvement against the periodic counterpart.

  10. Asynchronous emergence by loggerhead turtle (Caretta caretta) hatchlings.

    Science.gov (United States)

    Houghton, J D; Hays, G C

    2001-03-01

    For many decades it has been accepted that marine turtle hatchlings from the same nest generally emerge from the sand together. However, for loggerhead turtles (Caretta caretta) nesting on the Greek Island of Kefalonia, a more asynchronous pattern of emergence has been documented. By placing temperature loggers at the top and bottom of nests laid on Kefalonia during 1998, we examined whether this asynchronous emergence was related to the thermal conditions within nests. Pronounced thermal variation existed not only between, but also within, individual nests. These within-nest temperature differences were related to the patterns of hatchling emergence, with hatchlings from nests displaying large thermal ranges emerging over a longer time-scale than those characterised by more uniform temperatures. In many egg-laying animals, parental care of the offspring may continue while the eggs are incubating and also after they have hatched. Consequently, the importance of the nest site for determining incubation conditions may be reduced since the parents themselves may alter the local environment. By contrast, in marine turtles, parental care ceases once the eggs have been laid and the nest site covered. The positioning of the nest site, in both space and time, may therefore have profound effects for marine turtles by affecting, for example, the survival of the eggs and hatchlings as well as their sex (Janzen and Paukstis 1991). During incubation, sea turtle embryos grow from a few cells at oviposition to a self-sufficient organism at hatching some 50-80 days later (Ackerman 1997). After hatching, the young turtles dig up through the sand and emerge typically en masse at the surface 1-7 nights later, with a number of stragglers following over the next few nights (Christens 1990). This contrasts with the frequently observed pattern of hatching asynchrony in birds. It has been suggested that the cause of mass emergence in turtles is that eggs within a clutch are fertilised

  11. Blow Flies Visiting Decaying Alligators: Is Succession Synchronous or Asynchronous?

    Directory of Open Access Journals (Sweden)

    Mark P. Nelder

    2009-01-01

    Full Text Available Succession patterns of adult blow flies (Diptera: Calliphoridae on decaying alligators were investigated in Mobile (Ala, USA during August 2002. The most abundant blow fly species visiting the carcasses were Chrysomya rufifacies (Macquart, Cochliomyia macellaria (Fabricus, Chrysomya megacephala (Fabricus, Phormia regina (Meigen, and Lucilia coeruleiviridis (Macquart. Lucilia coeruleiviridis was collected more often during the early stages of decomposition, followed by Chrysomya spp., Cochliomyia macellaria, and Phormia regina in the later stages. Lucilia coeruleiviridis was the only synchronous blow fly on the three carcasses; other blow fly species exhibited only site-specific synchrony. Using dichotomous correlations and analyses of variance, we demonstrated that blow fly-community succession was asynchronous among three alligators; however, Monte Carlo simulations indicate that there was some degree of synchrony between the carcasses.

  12. Asynchronous data-driven classification of weapon systems

    International Nuclear Information System (INIS)

    Jin, Xin; Mukherjee, Kushal; Gupta, Shalabh; Ray, Asok; Phoha, Shashi; Damarla, Thyagaraju

    2009-01-01

    This communication addresses real-time weapon classification by analysis of asynchronous acoustic data, collected from microphones on a sensor network. The weapon classification algorithm consists of two parts: (i) feature extraction from time-series data using symbolic dynamic filtering (SDF), and (ii) pattern classification based on the extracted features using the language measure (LM) and support vector machine (SVM). The proposed algorithm has been tested on field data, generated by firing of two types of rifles. The results of analysis demonstrate high accuracy and fast execution of the pattern classification algorithm with low memory requirements. Potential applications include simultaneous shooter localization and weapon classification with soldier-wearable networked sensors. (rapid communication)

  13. Asynchronous machine rotor speed estimation using a tabulated numerical approach

    Science.gov (United States)

    Nguyen, Huu Phuc; De Miras, Jérôme; Charara, Ali; Eltabach, Mario; Bonnet, Stéphane

    2017-12-01

    This paper proposes a new method to estimate the rotor speed of the asynchronous machine by looking at the estimation problem as a nonlinear optimal control problem. The behavior of the nonlinear plant model is approximated off-line as a prediction map using a numerical one-step time discretization obtained from simulations. At each time-step, the speed of the induction machine is selected satisfying the dynamic fitting problem between the plant output and the predicted output, leading the system to adopt its dynamical behavior. Thanks to the limitation of the prediction horizon to a single time-step, the execution time of the algorithm can be completely bounded. It can thus easily be implemented and embedded into a real-time system to observe the speed of the real induction motor. Simulation results show the performance and robustness of the proposed estimator.

  14. Induction motor for superconducting synchronous/asynchronous motor

    International Nuclear Information System (INIS)

    Litz, D.C.; Haller, H.E. III.

    1975-01-01

    An induction motor structure for use on the outside of a superconducting rotor comprising a cylindrical shell of solid and laminated, magnetic iron with squirrel cage windings embedded in the outer circumference of said shell is described. The sections of the shell between the superconducting windings of the rotor are solid magnetic iron. The sections of the shell over the superconducting windings are made of laminations of magnetic iron. These laminations are parallel to the axis of the machine and are divided in halves with the laminations in each half oriented in diagonal opposition so that the intersection of the laminations forms a V. This structure presents a relatively high reluctance to leakage flux from the superconducting windings in the synchronous operating mode, while presenting a low reluctance path to the stator flux during asynchronous operation

  15. Exploring Asynchronous Many-Task Runtime Systems toward Extreme Scales

    Energy Technology Data Exchange (ETDEWEB)

    Knight, Samuel [O8953; Baker, Gavin Matthew; Gamell, Marc [Rutgers U; Hollman, David [08953; Sjaardema, Gregor [SNL; Kolla, Hemanth [SNL; Teranishi, Keita; Wilke, Jeremiah J; Slattengren, Nicole [SNL; Bennett, Janine Camille

    2015-10-01

    Major exascale computing reports indicate a number of software challenges to meet the dramatic change of system architectures in near future. While several-orders-of-magnitude increase in parallelism is the most commonly cited of those, hurdles also include performance heterogeneity of compute nodes across the system, increased imbalance between computational capacity and I/O capabilities, frequent system interrupts, and complex hardware architectures. Asynchronous task-parallel programming models show a great promise in addressing these issues, but are not yet fully understood nor developed su ciently for computational science and engineering application codes. We address these knowledge gaps through quantitative and qualitative exploration of leading candidate solutions in the context of engineering applications at Sandia. In this poster, we evaluate MiniAero code ported to three leading candidate programming models (Charm++, Legion and UINTAH) to examine the feasibility of these models that permits insertion of new programming model elements into an existing code base.

  16. Indoor Positioning for Smartphones Using Asynchronous Ultrasound Trilateration

    Directory of Open Access Journals (Sweden)

    James D. Carswell

    2013-06-01

    Full Text Available Modern smartphones are a great platform for Location Based Services (LBS. While outdoor LBS for smartphones has proven to be very successful, indoor LBS for smartphones has not yet fully developed due to the lack of an accurate positioning technology. In this paper we present an accurate indoor positioning approach for commercial off-the-shelf (COTS smartphones that uses the innate ability of mobile phones to produce ultrasound, combined with Time-Difference-of-Arrival (TDOA asynchronous trilateration. We evaluate our indoor positioning approach by describing its strengths and weaknesses, and determine its absolute accuracy. This is accomplished through a range of experiments that involve variables such as position of control point microphones, position of phone within the room, direction speaker is facing and presence of user in the signal path. Test results show that our Lok8 (locate mobile positioning system can achieve accuracies better than 10 cm in a real-world environment.

  17. Bio-Inspired Asynchronous Pixel Event Tricolor Vision Sensor.

    Science.gov (United States)

    Lenero-Bardallo, Juan Antonio; Bryn, D H; Hafliger, Philipp

    2014-06-01

    This article investigates the potential of the first ever prototype of a vision sensor that combines tricolor stacked photo diodes with the bio-inspired asynchronous pixel event communication protocol known as Address Event Representation (AER). The stacked photo diodes are implemented in a 22 × 22 pixel array in a standard STM 90 nm CMOS process. Dynamic range is larger than 60 dB and pixels fill factor is 28%. The pixels employ either simple pulse frequency modulation (PFM) or a Time-to-First-Spike (TFS) mode. A heuristic linear combination of the chip's inherent pseudo colors serves to approximate RGB color representation. Furthermore, the sensor outputs can be processed to represent the radiation in the near infrared (NIR) band without employing external filters, and to color-encode direction of motion due to an asymmetry in the update rates of the different diode layers.

  18. Operational aspects of asynchronous filtering for flood forecasting

    Science.gov (United States)

    Rakovec, O.; Weerts, A. H.; Sumihar, J.; Uijlenhoet, R.

    2015-06-01

    This study investigates the suitability of the asynchronous ensemble Kalman filter (AEnKF) and a partitioned updating scheme for hydrological forecasting. The AEnKF requires forward integration of the model for the analysis and enables assimilation of current and past observations simultaneously at a single analysis step. The results of discharge assimilation into a grid-based hydrological model (using a soil moisture error model) for the Upper Ourthe catchment in the Belgian Ardennes show that including past predictions and observations in the data assimilation method improves the model forecasts. Additionally, we show that elimination of the strongly non-linear relation between the soil moisture storage and assimilated discharge observations from the model update becomes beneficial for improved operational forecasting, which is evaluated using several validation measures.

  19. Operational aspects of asynchronous filtering for hydrological forecasting

    Science.gov (United States)

    Rakovec, O.; Weerts, A. H.; Sumihar, J.; Uijlenhoet, R.

    2015-03-01

    This study investigates the suitability of the Asynchronous Ensemble Kalman Filter (AEnKF) and a partitioned updating scheme for hydrological forecasting. The AEnKF requires forward integration of the model for the analysis and enables assimilation of current and past observations simultaneously at a single analysis step. The results of discharge assimilation into a grid-based hydrological model for the Upper Ourthe catchment in the Belgian Ardennes show that including past predictions and observations in the data assimilation method improves the model forecasts. Additionally, we show that elimination of the strongly non-linear relation between the soil moisture storage and assimilated discharge observations from the model update becomes beneficial for improved operational forecasting, which is evaluated using several validation measures.

  20. Label-acquired magnetorotation for biosensing: An asynchronous rotation assay

    International Nuclear Information System (INIS)

    Hecht, Ariel; Kinnunen, Paivo; McNaughton, Brandon; Kopelman, Raoul

    2011-01-01

    This paper presents a novel application of magnetic particles for biosensing, called label-acquired magnetorotation (LAM). This method is based on a combination of the traditional sandwich assay format with the asynchronous magnetic bead rotation (AMBR) method. In label-acquired magnetorotation, an analyte facilitates the binding of a magnetic label bead to a nonmagnetic solid phase sphere, forming a sandwich complex. The sandwich complex is then placed in a rotating magnetic field, where the rotational frequency of the sandwich complex is a function of the amount of analyte attached to the surface of the sphere. Here, we use streptavidin-coated beads and biotin-coated particles as analyte mimics, to be replaced by proteins and other biological targets in future work. We show this sensing method to have a dynamic range of two orders of magnitude.

  1. An Asynchronous Cellular Automata-Based Adaptive Illumination Facility

    Science.gov (United States)

    Bandini, Stefania; Bonomi, Andrea; Vizzari, Giuseppe; Acconci, Vito

    The term Ambient Intelligence refers to electronic environments that are sensitive and responsive to the presence of people; in the described scenario the environment itself is endowed with a set of sensors (to perceive humans or other physical entities such as dogs, bicycles, etc.), interacting with a set of actuators (lights) that choose their actions (i.e. state of illumination) in an attempt improve the overall experience of these users. The model for the interaction and action of sensors and actuators is an asynchronous Cellular Automata (CA) with memory, supporting a self-organization of the system as a response to the presence and movements of people inside it. The paper will introduce the model, as well as an ad hoc user interface for the specification of the relevant parameters of the CA transition rule that determines the overall system behaviour.

  2. Realization of station for testing asynchronous three-phase motors

    Science.gov (United States)

    Wróbel, A.; Surma, W.

    2016-08-01

    Nowadays, you cannot imagine the construction and operation of machines without the use of electric motors [13-15]. The proposed position is designed to allow testing of asynchronous three-phase motors. The position consists of a tested engine and the engine running as a load, both engines combined with a mechanical clutch [2]. The value of the load is recorded by measuring shaft created with Strain Gauge Bridge. This concept will allow to study the basic parameters of the engines, visualization motor parameters both vector and scalar controlled, during varying load drive system. In addition, registration during the variable physical parameters of the working electric motor, controlled by a frequency converter or controlled by a contactor will be possible. Position is designed as a teaching and research position to characterize the engines. It will be also possible selection of inverter parameters.

  3. Time-delayed chameleon: Analysis, synchronization and FPGA implementation

    Science.gov (United States)

    Rajagopal, Karthikeyan; Jafari, Sajad; Laarem, Guessas

    2017-12-01

    In this paper we report a time-delayed chameleon-like chaotic system which can belong to different families of chaotic attractors depending on the choices of parameters. Such a characteristic of self-excited and hidden chaotic flows in a simple 3D system with time delay has not been reported earlier. Dynamic analysis of the proposed time-delayed systems are analysed in time-delay space and parameter space. A novel adaptive modified functional projective lag synchronization algorithm is derived for synchronizing identical time-delayed chameleon systems with uncertain parameters. The proposed time-delayed systems and the synchronization algorithm with controllers and parameter estimates are then implemented in FPGA using hardware-software co-simulation and the results are presented.

  4. improvement of digital image watermarking techniques based on FPGA implementation

    International Nuclear Information System (INIS)

    EL-Hadedy, M.E

    2006-01-01

    digital watermarking provides the ownership of a piece of digital data by marking the considered data invisibly or visibly. this can be used to protect several types of multimedia objects such as audio, text, image and video. this thesis demonstrates the different types of watermarking techniques such as (discrete cosine transform (DCT) and discrete wavelet transform (DWT) and their characteristics. then, it classifies these techniques declaring their advantages and disadvantages. an improved technique with distinguished features, such as peak signal to noise ratio ( PSNR) and similarity ratio (SR) has been introduced. the modified technique has been compared with the other techniques by measuring heir robustness against differ attacks. finally, field programmable gate arrays (FPGA) based implementation and comparison, for the proposed watermarking technique have been presented and discussed

  5. Real-time particle image velocimetry based on FPGA technology

    International Nuclear Information System (INIS)

    Iriarte Munoz, Jose Miguel

    2008-01-01

    Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach. [es

  6. An FPGA-based rapid prototyping platform for wavelet coprocessors

    Science.gov (United States)

    Vera, Alonzo; Meyer-Baese, Uwe; Pattichis, Marios

    2007-04-01

    MatLab/Simulink-based design flows are being used by DSP designers to improve time-to-market of FPGA implementations. 1 Commonly, digital signal processing cores are integrated in an embedded system as coprocessors. Existing CAD tools do not fully address the integration of a DSP coprocessor into an embedded system design. This integration might prove to be time consuming and error prone. It also requires that the DSP designer has an excellent knowledge of embedded systems and computer architecture details. We present a prototyping platform and design flow that allows rapid integration of embedded systems with a wavelet coprocessor. The platform comprises of software and hardware modules that allow a DSP designer a painless integration of a coprocessor with a PowerPC-based embedded system. The platform has a wide range of applications, from industrial to educational environments.

  7. FPGA implementation of predictive degradation model for engine oil lifetime

    Science.gov (United States)

    Idros, M. F. M.; Razak, A. H. A.; Junid, S. A. M. Al; Suliman, S. I.; Halim, A. K.

    2018-03-01

    This paper presents the implementation of linear regression model for degradation prediction on Register Transfer Logic (RTL) using QuartusII. A stationary model had been identified in the degradation trend for the engine oil in a vehicle in time series method. As for RTL implementation, the degradation model is written in Verilog HDL and the data input are taken at a certain time. Clock divider had been designed to support the timing sequence of input data. At every five data, a regression analysis is adapted for slope variation determination and prediction calculation. Here, only the negative value are taken as the consideration for the prediction purposes for less number of logic gate. Least Square Method is adapted to get the best linear model based on the mean values of time series data. The coded algorithm has been implemented on FPGA for validation purposes. The result shows the prediction time to change the engine oil.

  8. FPGA implementation of advanced FEC schemes for intelligent aggregation networks

    Science.gov (United States)

    Zou, Ding; Djordjevic, Ivan B.

    2016-02-01

    In state-of-the-art fiber-optics communication systems the fixed forward error correction (FEC) and constellation size are employed. While it is important to closely approach the Shannon limit by using turbo product codes (TPC) and low-density parity-check (LDPC) codes with soft-decision decoding (SDD) algorithm; rate-adaptive techniques, which enable increased information rates over short links and reliable transmission over long links, are likely to become more important with ever-increasing network traffic demands. In this invited paper, we describe a rate adaptive non-binary LDPC coding technique, and demonstrate its flexibility and good performance exhibiting no error floor at BER down to 10-15 in entire code rate range, by FPGA-based emulation, making it a viable solution in the next-generation high-speed intelligent aggregation networks.

  9. A minimal SATA III Host Controller based on FPGA

    Science.gov (United States)

    Liu, Hailiang

    2018-03-01

    SATA (Serial Advanced Technology Attachment) is an advanced serial bus which has a outstanding performance in transmitting high speed real-time data applied in Personal Computers, Financial Industry, astronautics and aeronautics, etc. In this express, a minimal SATA III Host Controller based on Xilinx Kintex 7 serial FPGA is designed and implemented. Compared to the state-of-art, registers utilization are reduced 25.3% and LUTs utilization are reduced 65.9%. According to the experimental results, the controller works precisely and steady with the reading bandwidth of up to 536 MB per second and the writing bandwidth of up to 512 MB per second, both of which are close to the maximum bandwidth of the SSD(Solid State Disk) device. The host controller is very suitable for high speed data transmission and mass data storage.

  10. Implementace OFDM demodulátoru v obvodu FPGA

    OpenAIRE

    Solar, Pavel

    2010-01-01

    Diplomová práce stručně rozebírá princip OFDM modulace, možnosti synchronizace a odhadu frekvenční charakteristiky kanálu v OFDM. Je vytvořen jednoduchý model OFDM systému v programu MATLAB. Kombinací schématického popisu a popisu v jazyce VHDL je vytvořen ve vývojovém prostředí ISE behaviorální popis OFDM demodulátoru pro implementaci do FPGA. The master's thesis briefly analyses the principle of OFDM modulation, possibilities of the synchronization and channel estimation in OFDM. The sim...

  11. A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

    Directory of Open Access Journals (Sweden)

    Kevin R. Townsend

    2015-01-01

    Full Text Available On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.

  12. Validation of a Real-time AVS Encoder on FPGA

    Directory of Open Access Journals (Sweden)

    Qun Fang Yuan

    2014-01-01

    Full Text Available A whole I frame AVS real-time video encoder is designed and implemented on FPGA platform in this paper. The system uses the structure of the flow calculation, coupled with a dual-port RAM memory between/among the various functional modules. Reusable design and pipeline design are used to optimize various encoding module and to ensure the efficient operation of the pipeline. Through the simulation of ISE software and the verification of Xilinx Vritex-4 pro platform, it can be seen that the highest working frequency can be up to 110 MHz, meeting the requirements of the whole I frame real- time encoding of AVS in CIF resolution.

  13. FPGA Implementation of Real-Time Ethernet for Motion Control

    Directory of Open Access Journals (Sweden)

    Chen Youdong

    2013-01-01

    Full Text Available This paper provides an applicable implementation of real-time Ethernet named CASNET, which modifies the Ethernet medium access control (MAC to achieve the real-time requirement for motion control. CASNET is the communication protocol used for motion control system. Verilog hardware description language (VHDL has been used in the MAC logic design. The designed MAC serves as one of the intellectual properties (IPs and is applicable to various industrial controllers. The interface of the physical layer is RJ45. The other layers have been implemented by using C programs. The real-time Ethernet has been implemented by using field programmable gate array (FPGA technology and the proposed solution has been tested through the cycle time, synchronization accuracy, and Wireshark testing.

  14. FPGA based compute nodes for high level triggering in PANDA

    International Nuclear Information System (INIS)

    Kuehn, W; Gilardi, C; Kirschner, D; Lang, J; Lange, S; Liu, M; Perez, T; Yang, S; Schmitt, L; Jin, D; Li, L; Liu, Z; Lu, Y; Wang, Q; Wei, S; Xu, H; Zhao, D; Korcyl, K; Otwinowski, J T; Salabura, P

    2008-01-01

    PANDA is a new universal detector for antiproton physics at the HESR facility at FAIR/GSI. The PANDA data acquisition system has to handle interaction rates of the order of 10 7 /s and data rates of several 100 Gb/s. FPGA based compute nodes with multi-Gb/s bandwidth capability using the ATCA architecture are designed to handle tasks such as event building, feature extraction and high level trigger processing. Data connectivity is provided via optical links as well as multiple Gb Ethernet ports. The boards will support trigger algorithms such us pattern recognition for RICH detectors, EM shower analysis, fast tracking algorithms and global event characterization. Besides VHDL, high level C-like hardware description languages will be considered to implement the firmware

  15. Implementation of a pulse coupled neural network in FPGA.

    Science.gov (United States)

    Waldemark, J; Millberg, M; Lindblad, T; Waldemark, K; Becanovic, V

    2000-06-01

    The Pulse Coupled neural network, PCNN, is a biologically inspired neural net and it can be used in various image analysis applications, e.g. time-critical applications in the field of image pre-processing like segmentation, filtering, etc. a VHDL implementation of the PCNN targeting FPGA was undertaken and the results presented here. The implementation contains many interesting features. By pipelining the PCNN structure a very high throughput of 55 million neuron iterations per second could be achieved. By making the coefficients re-configurable during operation, a complete recognition system could be implemented on one, or maybe two, chip(s). Reconsidering the ranges and resolutions of the constants may save a lot of hardware, since the higher resolution requires larger multipliers, adders, memories etc.

  16. Method to implement the CCD timing generator based on FPGA

    Science.gov (United States)

    Li, Binhua; Song, Qian; He, Chun; Jin, Jianhui; He, Lin

    2010-07-01

    With the advance of the PFPA technology, the design methodology of digital systems is changing. In recent years we develop a method to implement the CCD timing generator based on FPGA and VHDL. This paper presents the principles and implementation skills of the method. Taking a developed camera as an example, we introduce the structure, input and output clocks/signals of a timing generator implemented in the camera. The generator is composed of a top module and a bottom module. The bottom one is made up of 4 sub-modules which correspond to 4 different operation modes. The modules are implemented by 5 VHDL programs. Frame charts of the architecture of these programs are shown in the paper. We also describe implementation steps of the timing generator in Quartus II, and the interconnections between the generator and a Nios soft core processor which is the controller of this generator. Some test results are presented in the end.

  17. A FPGA Implementation of the CAR-FAC Cochlear Model

    Directory of Open Access Journals (Sweden)

    Ying Xu

    2018-04-01

    Full Text Available This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC cochlear model. The CAR part simulates the basilar membrane's (BM response to sound. The FAC part models the outer hair cell (OHC, the inner hair cell (IHC, and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

  18. A FPGA Implementation of the CAR-FAC Cochlear Model.

    Science.gov (United States)

    Xu, Ying; Thakur, Chetan S; Singh, Ram K; Hamilton, Tara Julia; Wang, Runchun M; van Schaik, André

    2018-01-01

    This paper presents a digital implementation of the Cascade of Asymmetric Resonators with Fast-Acting Compression (CAR-FAC) cochlear model. The CAR part simulates the basilar membrane's (BM) response to sound. The FAC part models the outer hair cell (OHC), the inner hair cell (IHC), and the medial olivocochlear efferent system functions. The FAC feeds back to the CAR by moving the poles and zeros of the CAR resonators automatically. We have implemented a 70-section, 44.1 kHz sampling rate CAR-FAC system on an Altera Cyclone V Field Programmable Gate Array (FPGA) with 18% ALM utilization by using time-multiplexing and pipeline parallelizing techniques and present measurement results here. The fully digital reconfigurable CAR-FAC system is stable, scalable, easy to use, and provides an excellent input stage to more complex machine hearing tasks such as sound localization, sound segregation, speech recognition, and so on.

  19. Hardware Implementation Of Line Clipping A lgorithm By Using FPGA

    Directory of Open Access Journals (Sweden)

    Amar Dawod

    2013-04-01

    Full Text Available The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance the clipping is still a bottleneck of any graphical system. So its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA. The designed hardware unit consists of two parts : the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the  designed unit is capable of clipping (232524 line segments per second.       

  20. Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping

    Energy Technology Data Exchange (ETDEWEB)

    Ceriani, Marco; Palermo, Gianluca; Secchi, Simone; Tumeo, Antonino; Villa, Oreste

    2013-04-29

    We present a prototype of a multi-core architecture implemented on FPGA, designed to enable efficient execution of irregular applications on distributed shared memory machines, while maintaining high performance on regular workloads. The architecture is composed of off-the-shelf soft-core cores, local interconnection and memory interface, integrated with custom components that optimize it for irregular applications. It relies on three key elements: a global address space, multithreading, and fine-grained synchronization. Global addresses are scrambled to reduce the formation of network hot-spots, while the latency of the transactions is covered by integrating an hardware scheduler within the custom load/store buffers to take advantage from the availability of multiple executions threads, increasing the efficiency in a transparent way to the application. We evaluated a dual node system irregular kernels showing scalability in the number of cores and threads.

  1. Implementation of FPGA-Based Diverse Protection System

    International Nuclear Information System (INIS)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min

    2015-01-01

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails

  2. Implementation of FPGA-Based Diverse Protection System

    Energy Technology Data Exchange (ETDEWEB)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

    2015-10-15

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

  3. Asynchronous learning: student utilization out of sync with their preference

    Directory of Open Access Journals (Sweden)

    Edward K. Lew

    2016-06-01

    Full Text Available Background: Asynchronous learning is gaining popularity. Data are limited regarding this learning method in medical students rotating in emergency medicine (EM. In EM, faculty time is limited to give in-person lectures. The authors sought to create an online curriculum that students could utilize as an additional learning modality. Objective: The goal was to evaluate effectiveness, participation, and preference for this mode of learning. Methods: We developed five online, narrated PowerPoint presentations. After orientation, access to the online curriculum was provided to the students, which they could review at their leisure. Results: One hundred and seven fourth-year medical students participated. They reported the curriculum to be of high quality. Pretest scores were similar for those that viewed all lectures – compliant group (CG (9.5 [CI 4.8–14.1] and those that did not view any – non-compliant group (NCG (9.6 [CI 5.9–13.4]. There was no statistical significant difference in posttest scores between the groups although there was improvement overall: CG 14.6 (CI 6.9–22.1; NCG 11.4 (CI 5.7–17.1. A majority (69.2% favored inclusion of asynchronous learning, but less than a quarter (22.4% reported viewing all five modules and more than a third (36.4% viewed none. Conclusion: Despite student-expressed preference for an online curriculum, they used the online resource less than expected. This should give pause to educators looking to convert core EM topics to an online format. However, when high-quality online lectures are utilized as a learning tool, this study demonstrates that they had neither a positive nor a negative impact on test scores.

  4. An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator

    Directory of Open Access Journals (Sweden)

    Runchun M. Wang

    2018-04-01

    Full Text Available This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons. This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

  5. FPGA-based prototype of portable environmental radiation monitor

    Energy Technology Data Exchange (ETDEWEB)

    Benahmed, A.; Elkarch, H. [CNESTEN -Centre National de l' Energie des Sciences et Techniques Nucleaires (Morocco)

    2015-07-01

    This new portable radiological environmental monitor consists of 2 main components, Gamma ionization chamber and a FPGA-based electronic enclosure linked to convivial software for treatment and analyzing. The HPIC ion chamber is the heart of this radiation measurement system and is running in range from 0 to 100 mR/h, so that the sensitivity at the output is 20 mV/μR/h, with a nearly flat energy response from 0,07 to 10 MEV. This paper presents a contribution for developing a new nuclear measurement data acquisition system based on Cyclone III FPGA Starter Kit ALTERA, and a user-friendly software to run real-time control and data processing. It was developed to substitute the older radiation monitor RSS-112 PIC installed in CNESTEN's Laboratory in order to improve some of its functionalities related to acquisition time and data memory capacity. As for the associated acquisition software, it was conceived under the virtual LabView platform from National Instrument, and offers a variety of system setup for radiation environmental monitoring. It gives choice to display both the statistical data and the dose rate. Statistical data shows a summary of current data, current time/date and dose integrator values, and the dose rate displays the current dose rate in large numbers for viewing from a distance as well as the date and time. The prototype version of this new instrument and its data processing software has been successfully tested and validated for viewing and monitoring the environmental radiation of Moroccan nuclear center. (authors)

  6. FPGA-based RF spectrum merging and adaptive hopset selection

    Science.gov (United States)

    McLean, R. K.; Flatley, B. N.; Silvius, M. D.; Hopkinson, K. M.

    The radio frequency (RF) spectrum is a limited resource. Spectrum allotment disputes stem from this scarcity as many radio devices are confined to a fixed frequency or frequency sequence. One alternative is to incorporate cognition within a reconfigurable radio platform, therefore enabling the radio to adapt to dynamic RF spectrum environments. In this way, the radio is able to actively sense the RF spectrum, decide, and act accordingly, thereby sharing the spectrum and operating in more flexible manner. In this paper, we present a novel solution for merging many distributed RF spectrum maps into one map and for subsequently creating an adaptive hopset. We also provide an example of our system in operation, the result of which is a pseudorandom adaptive hopset. The paper then presents a novel hardware design for the frequency merger and adaptive hopset selector, both of which are written in VHDL and implemented as a custom IP core on an FPGA-based embedded system using the Xilinx Embedded Development Kit (EDK) software tool. The design of the custom IP core is optimized for area, and it can process a high-volume digital input via a low-latency circuit architecture. The complete embedded system includes the Xilinx PowerPC microprocessor, UART serial connection, and compact flash memory card IP cores, and our custom map merging/hopset selection IP core, all of which are targeted to the Virtex IV FPGA. This system is then incorporated into a cognitive radio prototype on a Rice University Wireless Open Access Research Platform (WARP) reconfigurable radio.

  7. Innovative approach to implementation of FPGA-based NPP instrumentation and control systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; Siora, Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper. (author)

  8. Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

    International Nuclear Information System (INIS)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir; SIORA Alexander

    2011-01-01

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper

  9. Innovative Approach to Implementation of FPGA-based NPP Instrumentation and Control Systems

    Energy Technology Data Exchange (ETDEWEB)

    Andrashov, Anton; Kharchenko, Vyacheslav; Sklyar, Volodymir [Centre for Safety Infrastructure-Oriented Research and Analysis, Kharkov (Ukraine); SIORA Alexander [Research and Production Corporation Radiy, Kirovograd (Ukraine)

    2011-08-15

    Advantages of application of Field Programmable Gates Arrays (FPGA) technology for implementation of Instrumentation and Control (I and C) systems for Nuclear Power Plants (NPP) are outlined. Specific features of FPGA technology in the context of cyber security threats for NPPs I and C systems are analyzed. Description of FPGA-based platform used for implementation of different safety I and C systems for NPPs is presented. Typical architecture of NPPs safety I and C system based on the platform, as well as approach to implementation of I and C systems using FPGA-based platform are discussed. Data on implementation experience of application of the platform for NPP safety I and C systems modernization projects are finalizing the paper.

  10. A natural-color mapping for single-band night-time image based on FPGA

    Science.gov (United States)

    Wang, Yilun; Qian, Yunsheng

    2018-01-01

    A natural-color mapping for single-band night-time image method based on FPGA can transmit the color of the reference image to single-band night-time image, which is consistent with human visual habits and can help observers identify the target. This paper introduces the processing of the natural-color mapping algorithm based on FPGA. Firstly, the image can be transformed based on histogram equalization, and the intensity features and standard deviation features of reference image are stored in SRAM. Then, the real-time digital images' intensity features and standard deviation features are calculated by FPGA. At last, FPGA completes the color mapping through matching pixels between images using the features in luminance channel.

  11. Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

    Directory of Open Access Journals (Sweden)

    He Chen

    2011-12-01

    Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

  12. Development of an FPGA-based controller for safety critical application

    International Nuclear Information System (INIS)

    Xing, A.; De Grosbois, J.; Sklyar, V.; Archer, P.; Awwal, A.

    2011-01-01

    In implementing safety functions, Field Programmable Gate Arrays (FPGA) technology offers a distinct combination of benefits and advantages over microprocessor-based systems. FPGAs can be designed such that the final product is purely hardware, without any overhead runtime software, bringing the design closer to a conventional hardware-based solution. On the other hand, FPGAs can implement more complex safety logic that would generally require microprocessor-based safety systems. There are now qualified FPGA-based platforms available on the market with a credible use history in safety applications in nuclear power plants. Atomic Energy of Canada (AECL), in collaboration with RPC Radiy, has initiated a development program to define a vigorous FPGA engineering process suitable for implementing safety critical functions at the application development level. This paper provides an update on the FPGA development program along with the proposed design model using function block diagrams for the development of safety controllers in CANDU applications. (author)

  13. A FPGA Approach in a Motorised Linear Stage Remote Controlled Experiment

    Directory of Open Access Journals (Sweden)

    Stamen Gadzhanov

    2013-04-01

    Full Text Available In recent years, an advanced motion control software for rapid development has been introduced by National Instruments, accompanied by innovative and improved FPGA-based hardware platforms. Compared to the well-known standard NI DAQ PCI/USB board solutions, this new approach offers robust stability in a deterministic real-time environment combined with the highest possible performance and re-configurability of the FPGA core. The NI Compact RIO (cRIO Real Time Controller utilises two distinctive interface modes of functionality: Scan and FPGA modes. This paper presents an application of a motion control flexible workbench based on the FPGA module, and analyses the advantages and disadvantages in comparison to another approach - the LabVIEW NI SoftMotion module run in scan interface mode. The workbench replicates real industrial applications and is very useful for experimentation with Brushless DC/ Permanent Magnet Synchronous motors and drives, and feedback devices.

  14. Timing measurements of some tracking algorithms and suitability of FPGA's to improve the execution speed

    CERN Document Server

    Khomich, A; Kugel, A; Männer, R; Müller, M; Baines, J T M

    2003-01-01

    Some of track reconstruction algorithms which are common to all B-physics channels and standard RoI processing have been tested for execution time and assessed for suitability for speed-up by using FPGA coprocessor. The studies presented in this note were performed in the C/C++ framework, CTrig, which was the fullest set of algorithms available at the time of study For investigation of possible speed-up of algorithms most time consuming parts of TRT-LUT was implemented in VHDL for running in FPGA coprocessor board MPRACE. MPRACE (Reconfigurable Accelerator / Computing Engine) is an FPGA-Coprocessor based on Xilinx Virtex-2 FPGA and made as 64Bit/66MHz PCI card developed at the University of Mannheim. Timing measurements results for a TRT Full Scan algorithm executed on the MPRACE are presented here as well. The measurement results show a speed-up factor of ~2 for this algorithm.

  15. Dynamic Reconfiguration Of FPGA Nodes In A Distributed Computing System: A Preliminary Investigation

    National Research Council Canada - National Science Library

    Nixon, Patrick

    2002-01-01

    This report results from a contract tasking Trinity College, Dublin to investigate a specialized portion of a heterogeneous information system, specifically, Field Programmable Gate Array (FPGA)-based nodes...

  16. Advanced Image Processing Package for FPGA-Based Re-Programmable Miniature Electronics

    National Research Council Canada - National Science Library

    Ovod, Vladimir I; Baxter, Christopher R; Massie, Mark A; McCarley, Paul L

    2005-01-01

    .... An advanced image-processing package has been designed at Nova Sensors to re-configure the FPGA-based co-processor board for numerous applications including motion detection, optical background...

  17. Rad-Hard and ULP FPGA with "Full" Functionality, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the...

  18. A FPGA-based architecture for real-time image matching

    Science.gov (United States)

    Wang, Jianhui; Zhong, Sheng; Xu, Wenhui; Zhang, Weijun; Cao, Zhiguo

    2013-10-01

    Image matching is a fundamental task in computer vision. It is used to establish correspondence between two images taken at different viewpoint or different time from the same scene. However, its large computational complexity has been a challenge to most embedded systems. This paper proposes a single FPGA-based image matching system, which consists of SIFT feature detection, BRIEF descriptor extraction and BRIEF matching. It optimizes the FPGA architecture for the SIFT feature detection to reduce the FPGA resources utilization. Moreover, we implement BRIEF description and matching on FPGA also. The proposed system can implement image matching at 30fps (frame per second) for 1280x720 images. Its processing speed can meet the demand of most real-life computer vision applications.

  19. Modeling and Analysis of Asynchronous Systems Using SAL and Hybrid SAL

    Science.gov (United States)

    Tiwari, Ashish; Dutertre, Bruno

    2013-01-01

    We present formal models and results of formal analysis of two different asynchronous systems. We first examine a mid-value select module that merges the signals coming from three different sensors that are each asynchronously sampling the same input signal. We then consider the phase locking protocol proposed by Daly, Hopkins, and McKenna. This protocol is designed to keep a set of non-faulty (asynchronous) clocks phase locked even in the presence of Byzantine-faulty clocks on the network. All models and verifications have been developed using the SAL model checking tools and the Hybrid SAL abstractor.

  20. UNIVERSAL REGULAR AUTONOMOUS ASYNCHRONOUS SYSTEMS: ω-LIMIT SETS, INVARIANCE AND BASINS OF ATTRACTION

    Directory of Open Access Journals (Sweden)

    Serban Vlad

    2011-07-01

    Full Text Available The asynchronous systems are the non-deterministic real timebinarymodels of the asynchronous circuits from electrical engineering.Autonomy means that the circuits and their models have no input.Regularity means analogies with the dynamical systems, thus such systems may be considered to be real time dynamical systems with a’vector field’, Universality refers to the case when the state space of the system is the greatest possible in the sense of theinclusion. The purpose of this paper is that of defining, by analogy with the dynamical systems theory, the omega-limit sets, the invariance and the basins of attraction of the universal regular autonomous asynchronous systems.

  1. Fuzzy Controller Design Using FPGA for Photovoltaic Maximum Power Point Tracking

    OpenAIRE

    Basil M Hamed; Mohammed S. El-Moghany

    2012-01-01

    The cell has optimum operating point to be able to get maximum power. To obtain Maximum Power from photovoltaic array, photovoltaic power system usually requires Maximum Power Point Tracking (MPPT) controller. This paper provides a small power photovoltaic control system based on fuzzy control with FPGA technology design and implementation for MPPT. The system composed of photovoltaic module, buck converter and the fuzzy logic controller implemented on FPGA for controlling on/off time of MOSF...

  2. Direct Measurement of Power Dissipated by Monte Carlo Simulations on CPU and FPGA Platforms

    OpenAIRE

    Albicocco, Pietro; Papini, Davide; Nannarelli, Alberto

    2012-01-01

    In this technical report, we describe how power dissipation measurements on different computing platforms (a desktop computer and an FPGA board) are performed by using a Hall effectbased current sensor. The chosen application is a Monte Carlo simulation for European option pricing which is a popular algorithm used in financial computations. The Hall effect probe measurements complement the measurements performed on the core of the FPGA by a built-in Xilinxpower monitoring system.

  3. Scaling of Supply Voltage in Design of Energy Saver FIR Filter on 28nm FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Jain, Vishal; Sharma, Rashmi

    2017-01-01

    In this work, we are going to analyze the effect of main supply voltage, auxiliary supply voltage, local voltage of different power bank, and supply voltage in GTX transceiver and BRAM on power dissipation of our FIR design using Verilog during implementation on 28nm FPGA. We have also taken three.......33%, 86%, 90.67%, 65.33%, 52%, and 48.67% reduction in IO power dissipation of FIR Filter design on CSG324 package of Artix-7 FPGA family....

  4. Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Harris, Fred; Koch, Peter

    2012-01-01

    This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks......% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively....

  5. Investigation of Electromagnetic Signatures of a FPGA Using an APREL EM-ISIGHT System

    Science.gov (United States)

    2015-12-01

    shelf (COTS) field- programmable gate array (FPGA) at the optimized factor levels established from the DOE and varying the programmed signal. This...signature using APREL’s EM-ISight automated system is hypothesized to be a novel way to accomplish this task. Research Questions The research...a field programmable gate array (FPGA) is the circuit board utilized for testing the inherent electromagnetic signature. Every device produces an

  6. A Design Methodology for Efficient Implementation of Deconvolutional Neural Networks on an FPGA

    OpenAIRE

    Zhang, Xinyu; Das, Srinjoy; Neopane, Ojash; Kreutz-Delgado, Ken

    2017-01-01

    In recent years deep learning algorithms have shown extremely high performance on machine learning tasks such as image classification and speech recognition. In support of such applications, various FPGA accelerator architectures have been proposed for convolutional neural networks (CNNs) that enable high performance for classification tasks at lower power than CPU and GPU processors. However, to date, there has been little research on the use of FPGA implementations of deconvolutional neural...

  7. FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

    Directory of Open Access Journals (Sweden)

    Swapnil Mhaske

    2017-01-01

    Full Text Available We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

  8. FPGA hardware acceleration for high performance neutron transport computation based on agent methodology - 318

    International Nuclear Information System (INIS)

    Shanjie, Xiao; Tatjana, Jevremovic

    2010-01-01

    The accurate, detailed and 3D neutron transport analysis for Gen-IV reactors is still time-consuming regardless of advanced computational hardware available in developed countries. This paper introduces a new concept in addressing the computational time while persevering the detailed and accurate modeling; a specifically designed FPGA co-processor accelerates robust AGENT methodology for complex reactor geometries. For the first time this approach is applied to accelerate the neutronics analysis. The AGENT methodology solves neutron transport equation using the method of characteristics. The AGENT methodology performance was carefully analyzed before the hardware design based on the FPGA co-processor was adopted. The most time-consuming kernel part is then transplanted into the FPGA co-processor. The FPGA co-processor is designed with data flow-driven non von-Neumann architecture and has much higher efficiency than the conventional computer architecture. Details of the FPGA co-processor design are introduced and the design is benchmarked using two different examples. The advanced chip architecture helps the FPGA co-processor obtaining more than 20 times speed up with its working frequency much lower than the CPU frequency. (authors)

  9. Design Verification Enhancement of FPGA-based Plant Protection System Trip Logics for Nuclear Power Plant

    International Nuclear Information System (INIS)

    Ahmed, Ibrahim; Jung, Jae Cheon; Heo, Gyun Young

    2016-01-01

    As part of strengthening the application of FPGA technology and find solution to its challenges in NPPs, international atomic energy agency (IAEA) has indicated interest by joining sponsorship of Topical Group on FPGA Applications in NPPs (TG-FAN) that hold meetings up to 7th times until now, in form of workshop (International workshop on the application of FPGAs in NPPs) annually since 2008. The workshops attracted a significant interest and had a broad representation of stakeholders such as regulators, utilities, research organizations, system designers, and vendors, from various countries that converge to discuss the current issues regarding instrumentation and control (I and C) systems as well as FPGA applications. Two out of many technical issues identified by the group are lifecycle of FPGA-based platforms, systems, and applications; and methods and tools for V and V. Therefore, in this work, several design steps that involved the use of model-based systems engineering process as well as MATLAB/SIMULINK model which lead to the enhancement of design verification are employed. The verified and validated design output works correctly and effectively. Conclusively, the model-based systems engineering approach and the structural step-by-step design modeling techniques including SIMULINK model utilized in this work have shown how FPGA PPS trip logics design verification can be enhanced. If these design approaches are employ in the design of FPGA-based I and C systems, the design can be easily verified and validated

  10. A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

    Science.gov (United States)

    Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

    2015-10-01

    Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

  11. Transition to Asynchronous Transfer Mode (ATM) an Implementation Model for NPS Software Metrics Lab

    National Research Council Canada - National Science Library

    Carney, Cameron

    1999-01-01

    With Asynchronous Transfer Mode (ATM), we are experiencing the emergence of a network technology that has the potential of satisfying the requirement for a worldwide standard to allow interoperability of information, regardless...

  12. Integration of asynchronous knowledge sources in a novel speech recognition framework

    OpenAIRE

    Van hamme, Hugo

    2008-01-01

    Van hamme H., ''Integration of asynchronous knowledge sources in a novel speech recognition framework'', Proceedings ITRW on speech analysis and processing for knowledge discovery, 4 pp., June 2008, Aalborg, Denmark.

  13. Determining sociability, social space, and social presence in (A)synchronous collaborative groups

    NARCIS (Netherlands)

    Kreijns, K.; Kirschner, P.A.; Jochems, W.; Buuren, H. van

    2004-01-01

    The effectiveness of group learning in asynchronous distributed learning groups depends on the social interaction that takes place. This social interaction affects both cognitive and socioemotional processes that take place during learning, group forming, establishment of group structures, and group

  14. Students experiences with collaborative learning in asynchronous computer-supported collaborative learning environments.

    NARCIS (Netherlands)

    Dewiyanti, Silvia; Brand-Gruwel, Saskia; Jochems, Wim; Broers, Nick

    2008-01-01

    Dewiyanti, S., Brand-Gruwel, S., Jochems, W., & Broers, N. (2007). Students experiences with collaborative learning in asynchronous computer-supported collaborative learning environments. Computers in Human Behavior, 23, 496-514.

  15. ZONES OF STEADY CAPACITOR EXCITATION IN A MODE OF GENERATION OF TYPICAL ASYNCHRONOUS MACHINES

    Directory of Open Access Journals (Sweden)

    Postoronca Sv.

    2009-12-01

    Full Text Available In work some features of a mode of capacitor excitation of industrial asynchronous electric motors, and also generators made on their base which can be used in wind installations of low power are considered. Borders of zones of steady capacitor excitation of asynchronous electric motors in rated power of 0,25-22,0 kW and generators made on their base, and also character of influence of own losses and active capacity of loading of the equivalent circuit of the asynchronous machine resulted in parameters have been determined. Some recommendations after maintenance of stability of capacitor excitation of asynchronous machines for work in a mode of generation of electric energy are given.

  16. Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend

    DEFF Research Database (Denmark)

    Nielsen, Sune Fallgaard; Sparsø, Jens; Madsen, Jan

    2009-01-01

    The current state-of-the art in high-level synthesis of asynchronous circuits is syntax directed translation, which performs a one-to-one mapping of a HDL-description into a corresponding circuit. This paper presents a method for behavioral synthesis of asynchronous circuits which builds on top...... description language Balsa [1]. This ”conventional” template architecture allows us to adapt traditional synchronous synthesis techniques for resource sharing, scheduling, binding etc, to the domain of asynchronous circuits. A prototype tool has been implemented on top of the Balsa framework, and the method...... is illustrated through the implementation of a set of example circuits. The main contributions of the paper are: the fundamental idea, the template architecture and its implementation using asynchronous handshake components, and the implementation of a prototype tool....

  17. Distributed Consensus of Stochastic Delayed Multi-agent Systems Under Asynchronous Switching.

    Science.gov (United States)

    Wu, Xiaotai; Tang, Yang; Cao, Jinde; Zhang, Wenbing

    2016-08-01

    In this paper, the distributed exponential consensus of stochastic delayed multi-agent systems with nonlinear dynamics is investigated under asynchronous switching. The asynchronous switching considered here is to account for the time of identifying the active modes of multi-agent systems. After receipt of confirmation of mode's switching, the matched controller can be applied, which means that the switching time of the matched controller in each node usually lags behind that of system switching. In order to handle the coexistence of switched signals and stochastic disturbances, a comparison principle of stochastic switched delayed systems is first proved. By means of this extended comparison principle, several easy to verified conditions for the existence of an asynchronously switched distributed controller are derived such that stochastic delayed multi-agent systems with asynchronous switching and nonlinear dynamics can achieve global exponential consensus. Two examples are given to illustrate the effectiveness of the proposed method.

  18. Determining sociability, social space, and social presence in (a)synchronous collaborating groups

    NARCIS (Netherlands)

    Kreijns, C.J.; Kirschner, P.A.; Jochems, W.M.G.; Buuren, van H.

    2004-01-01

    The effectiveness of group learning in asynchronous distributed learning groups depends on the social interaction that takes place. This social interaction affects both cognitive and socioemotional processes that take place during learning, group forming, establishment of group structures, and group

  19. Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques

    Directory of Open Access Journals (Sweden)

    Nikos Sklavos

    2002-01-01

    Full Text Available An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA is presented in this paper. In order to evaluate the asynchronous design a synchronous version of the algorithm was also designed. VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercial available tools the VHDL code was synthesized. After placing and routing both designs were fabricated with 0.6 μm CMOS technology. With a system clock of up to 8 MHz and a power supply of 5 V the two chips were tested and evaluated comparing with the software implementation of the IDEA algorithm. This new approach proves efficiently the lowest power consumption of the asynchronous implementation compared to the existing synchronous. Therefore, the asynchronous chip performs efficiently in Wireless Encryption Protocols and high speed networks.

  20. Asynchronous Sensor fuSion for Improved Safety of air Traffic (ASSIST), Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — SSCI proposes to develop, implement and test a collision detection system for unmanned aerial vehicles (UAV), referred to as the Asynchronous Sensor fuSion for...

  1. Operational aspects of asynchronous filtering for improved flood forecasting

    Science.gov (United States)

    Rakovec, Oldrich; Weerts, Albrecht; Sumihar, Julius; Uijlenhoet, Remko

    2014-05-01

    Hydrological forecasts can be made more reliable and less uncertain by recursively improving initial conditions. A common way of improving the initial conditions is to make use of data assimilation (DA), a feedback mechanism or update methodology which merges model estimates with available real world observations. The traditional implementation of the Ensemble Kalman Filter (EnKF; e.g. Evensen, 2009) is synchronous, commonly named a three dimensional (3-D) assimilation, which means that all assimilated observations correspond to the time of update. Asynchronous DA, also called four dimensional (4-D) assimilation, refers to an updating methodology, in which observations being assimilated into the model originate from times different to the time of update (Evensen, 2009; Sakov 2010). This study investigates how the capabilities of the DA procedure can be improved by applying alternative Kalman-type methods, e.g., the Asynchronous Ensemble Kalman Filter (AEnKF). The AEnKF assimilates observations with smaller computational costs than the original EnKF, which is beneficial for operational purposes. The results of discharge assimilation into a grid-based hydrological model for the Upper Ourthe catchment in Belgian Ardennes show that including past predictions and observations in the AEnKF improves the model forecasts as compared to the traditional EnKF. Additionally we show that elimination of the strongly non-linear relation between the soil moisture storage and assimilated discharge observations from the model update becomes beneficial for an improved operational forecasting, which is evaluated using several validation measures. In the current study we employed the HBV-96 model built within a recently developed open source modelling environment OpenStreams (2013). The advantage of using OpenStreams (2013) is that it enables direct communication with OpenDA (2013), an open source data assimilation toolbox. OpenDA provides a number of algorithms for model calibration

  2. Violation of the equivalence principle for stressed bodies in asynchronous relativity

    Energy Technology Data Exchange (ETDEWEB)

    Andrade Martins, R. de (Centro de Logica, Epistemologia e Historia da Ciencia, Campinas (Brazil))

    1983-12-11

    In the recently developed asynchronous formulation of the relativistic theory of extended bodies, the inertial mass of a body does not explicitly depend on its pressure or stress. The detailed analysis of the weight of a box filled with a gas and placed in a weak gravitational field shows that this feature of asynchronous relativity implies a breakdown of the equivalence between inertial and passive gravitational mass for stressed systems.

  3. An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations

    Directory of Open Access Journals (Sweden)

    Ausif Mahmood

    1996-01-01

    a circuit remain fixed during the entire simulation. We remove this limitation and, by extending the analyses to multi-input, multi-output circuits with an arbitrary number of input events, show that the conservative asynchronous simulation extracts more parallelism and executes faster than synchronous simulation in general. Our conclusions are supported by a comparison of the idealized execution times of synchronous and conservative asynchronous algorithms on ISCAS combinational and sequential benchmark circuits.

  4. Asynchronous Free-Space Optical CDMA Communications System for Last-mile Access Network

    DEFF Research Database (Denmark)

    Jurado-Navas, Antonio; Raddo, Thiago R.; Sanches, Anderson L.

    2016-01-01

    We propose a new hybrid asynchronous OCDMA-FSO communications system for access network solutions. New ABER expressions are derived under gamma-gamma scintillation channels, where all users can surprisingly achieve error-free transmissions when FEC is employed.......We propose a new hybrid asynchronous OCDMA-FSO communications system for access network solutions. New ABER expressions are derived under gamma-gamma scintillation channels, where all users can surprisingly achieve error-free transmissions when FEC is employed....

  5. Strict optical orthogonal codes for purely asynchronous code-division multiple-access applications

    Science.gov (United States)

    Zhang, Jian-Guo

    1996-12-01

    Strict optical orthogonal codes are presented for purely asynchronous optical code-division multiple-access (CDMA) applications. The proposed code can strictly guarantee the peaks of its cross-correlation functions and the sidelobes of any of its autocorrelation functions to have a value of 1 in purely asynchronous data communications. The basic theory of the proposed codes is given. An experiment on optical CDMA systems is also demonstrated to verify the characteristics of the proposed code.

  6. The study of transient processes in the asynchronous starting of the synchronous motor

    OpenAIRE

    Alexandru Bârlea; Olivian Chiver

    2012-01-01

    Starting synchronous motors can be achieved by several ethods: starting with an auxiliary motor launch, starting in asynchronous regim, by feeding from a variable frequency source, auto-synchronization with the network.. In our case we study the transient processes in a asynchronous regim . In this case the synchronous motor is started like a squirrel cage induction motor . To start, the synchronous motor is equipped with a starting winding cage placed in the pole pieces of polar inducers; la...

  7. MED5/355: Using Web-technology for Asynchronous Telemedicine Consulting

    OpenAIRE

    Reviakin, Y; Sukhanov, A

    1999-01-01

    Introduction Common telemedicine consultations can be divided in two classes: real-time telemedicine consultations and asynchronous telemedicine consultations. The advantage of real-time consultations is obvious - this is a natural discussion between physicians, which may be realised on the basis of desktop videoconferences. But the problems are also obvious: the necessity of additional hardware and the elevated demands for channel bandwidth. Because of the latter, the use of asynchronous tel...

  8. Simulating Quantitative Cellular Responses Using Asynchronous Threshold Boolean Network Ensembles

    Directory of Open Access Journals (Sweden)

    Shah Imran

    2011-07-01

    Full Text Available Abstract Background With increasing knowledge about the potential mechanisms underlying cellular functions, it is becoming feasible to predict the response of biological systems to genetic and environmental perturbations. Due to the lack of homogeneity in living tissues it is difficult to estimate the physiological effect of chemicals, including potential toxicity. Here we investigate a biologically motivated model for estimating tissue level responses by aggregating the behavior of a cell population. We assume that the molecular state of individual cells is independently governed by discrete non-deterministic signaling mechanisms. This results in noisy but highly reproducible aggregate level responses that are consistent with experimental data. Results We developed an asynchronous threshold Boolean network simulation algorithm to model signal transduction in a single cell, and then used an ensemble of these models to estimate the aggregate response across a cell population. Using published data, we derived a putative crosstalk network involving growth factors and cytokines - i.e., Epidermal Growth Factor, Insulin, Insulin like Growth Factor Type 1, and Tumor Necrosis Factor α - to describe early signaling events in cell proliferation signal transduction. Reproducibility of the modeling technique across ensembles of Boolean networks representing cell populations is investigated. Furthermore, we compare our simulation results to experimental observations of hepatocytes reported in the literature. Conclusion A systematic analysis of the results following differential stimulation of this model by growth factors and cytokines suggests that: (a using Boolean network ensembles with asynchronous updating provides biologically plausible noisy individual cellular responses with reproducible mean behavior for large cell populations, and (b with sufficient data our model can estimate the response to different concentrations of extracellular ligands. Our

  9. Comparing face-to-face, synchronous, and asynchronous learning: postgraduate dental resident preferences.

    Science.gov (United States)

    Kunin, Marc; Julliard, Kell N; Rodriguez, Tobias E

    2014-06-01

    The Department of Dental Medicine of Lutheran Medical Center has developed an asynchronous online curriculum consisting of prerecorded PowerPoint presentations with audio explanations. The focus of this study was to evaluate if the new asynchronous format satisfied the educational needs of the residents compared to traditional lecture (face-to-face) and synchronous (distance learning) formats. Lectures were delivered to 219 dental residents employing face-to-face and synchronous formats, as well as the new asynchronous format; 169 (77 percent) participated in the study. Outcomes were assessed with pretests, posttests, and individual lecture surveys. Results found the residents preferred face-to-face and asynchronous formats to the synchronous format in terms of effectiveness and clarity of presentations. This preference was directly related to the residents' perception of how well the technology worked in each format. The residents also rated the quality of student-instructor and student-student interactions in the synchronous and asynchronous formats significantly higher after taking the lecture series than they did before taking it. However, they rated the face-to-face format as significantly more conducive to student-instructor and student-student interaction. While the study found technology had a major impact on the efficacy of this curricular model, the results suggest that the asynchronous format can be an effective way to teach a postgraduate course.

  10. Semivariogram Analysis of Bone Images Implemented on FPGA Architectures.

    Science.gov (United States)

    Shirvaikar, Mukul; Lagadapati, Yamuna; Dong, Xuanliang

    2017-03-01

    Osteoporotic fractures are a major concern for the healthcare of elderly and female populations. Early diagnosis of patients with a high risk of osteoporotic fractures can be enhanced by introducing second-order statistical analysis of bone image data using techniques such as variogram analysis. Such analysis is computationally intensive thereby creating an impediment for introduction into imaging machines found in common clinical settings. This paper investigates the fast implementation of the semivariogram algorithm, which has been proven to be effective in modeling bone strength, and should be of interest to readers in the areas of computer-aided diagnosis and quantitative image analysis. The semivariogram is a statistical measure of the spatial distribution of data, and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. A semi-variance, γ ( h ), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h . Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O ( n 2 ) Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current

  11. Spatial and color clustering on an FPGA-based computer system

    Science.gov (United States)

    Leeser, Miriam E.; Kitaryeva, Natalya V.; Crisman, Jill D.

    1998-10-01

    We are mapping an image clustering algorithm onto an FPGA- based computer system. Our approach processes raw pixel data in the red, green, blue color space and generates an output image where all pixels are assigned to classes. A class is a group of pixels with similar color and location. These classes are then used as the basis of further processing to generate tags. The tags, in turn, are used to generate queries for searching libraries of digital images. We run our image tagging approach on an FPGA-based computing machine. The image clustering algorithm is run on an FPGA board, and only the classified image is communicated to the host PC. Further processing is run on the host. Our experimental system consists of an Annapolis Wildforce board with four Xilinx XC4000 chips and a PCI connection to a host PC. Our implementation allows the raw image data to stay local to the FPGAs, and only the class image is communicated to the host PC. The classified pixels are then used to generate tags which can be used for searching a digital library. This approach allows us to parallelize the image processing on the FPGA board, and to minimize the data handled by the PC. FPGA platforms are ideally suited for this sort of initial processing of images. The large amount of image data can be preprocessed by exploiting the inherent parallelism available in FPGA architectures, keeping unnecessary data off the host processor. The result of our algorithm is a reduction by up to a factor of six in the number of bits required to represent each pixel. The output data is passed to the host PC, thus reducing the processing and memory resources needed compared to handling the raw data on the PC. The process of generating tags of images is simplified by first classifying pixels on an FPGA-based system, and digital library search is accelerated.

  12. Identity Presentation: The Construction of Identity in Asynchronous Discussion

    Directory of Open Access Journals (Sweden)

    Brian Morgan

    2008-08-01

    Full Text Available This study examines the use of e-mail as a tool for long term discussion between teachers and grade six students. E-mail messages between grade six students and teachers were collected over the course of one academic year. Methods of conversation analysis within a framework of social practice are used to examine the data. While identity is more readily constructed and more fully developed in contexts which allow for physical embodiment such as face-to-face discussion, this analysis found that identity can be constructed in a context that does not provide for the physical embodiment of identity: Identity was constructed using the social, cultural, and technological tools provided and supported by e-mail to develop social practices germane to the e-mail discussion. This study has implications for further understanding the relation between identity, goals, constraints and affordances, and the collaborative creation of social practices in asynchronous computer mediated communication. URN: urn:nbn:de:0114-fqs0803185

  13. FACT. Normalized and asynchronous mirror alignment for Cherenkov telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Mueller, Sebastian Achim [ETH Zurich (Switzerland); Buss, Jens [TU Dortmund (Germany)

    2016-07-01

    Imaging Atmospheric Cherenkov Telescopes (IACTs) need fast and large imaging optics to map the faint Cherenkov light emitted in cosmic ray air showers onto their image sensors. Segmented reflectors are inexpensive, lightweight and offer good image quality. However, alignment of the mirror facets remains a challenge. A good alignment is crucial in IACT observations to separate gamma rays from hadronic cosmic rays. We present a star tracking alignment method which is not restricted to clear nights. It normalizes the mirror facet reflections to be independent of the reference star or the cloud coverage. It records asynchronously of the telescope drive which makes the method easy to integrate in existing telescopes. It can be combined with remote facet actuation, but it does not need one to work. Furthermore, it can reconstruct all individual mirror facet point spread functions. We present the method and alignment results on the First Geiger-mode Photo Diode Avalanche Cherenkov Telescope (FACT) on the Canary Island of La Palma, Spain.

  14. Preparation for an online asynchronous university doctoral course. Lessons learned.

    Science.gov (United States)

    Milstead, J A; Nelson, R

    1998-01-01

    This article addresses the development of the initial course in the first completely online doctoral program in nursing. Synchronous and asynchronous methods of distance education were assessed. Planning focused at the university, school, and course levels. University planning involved the technical infrastructure, registration, student services, and library services. School planning examined administrative commitment and faculty commitment and willingness. Course planning focused on marketing, precourse information, time frame, modular design, planned interaction, and professor availability and support. Implementation issues centered on getting students connected, learning the software, changing instructional methods, and managing chats. Traditional methods of evaluating student learning and course evaluation were supplemented with the development of qualitative and quantitative tools to gather data for making administrative decisions. The Dean and faculty agreed that the internet was an effective method of delivering content in the initial Health Policy course. The Dean and faculty agreed to continue the PhD program online for one cohort and continue to evaluate student progress and faculty and student satisfaction.

  15. Performance Studies for Protection Against Asynchronous Dumps in the LHC

    CERN Document Server

    Kramer, T; Bracco, C; Goddard, B; Meddahi, M

    2010-01-01

    The LHC beam dump system has to safely dispose all beams in a wide energy range of 450 GeV to 7 TeV. A 3 ms abort gap in the beam structure for the switch-on of the extraction kicker field ideally allows a loss-free extraction under normal operating conditions. However, a low number of asynchronous beam aborts is to be expected from reliability calculations and from the first year's operational experience with the beam dump kickers. For such cases, MAD-X simulations including all optics and alignment errors have been performed to determine loss patterns around the LHC as a function of the position of the main protection elements in interaction region six. Special attention was paid to the beam load on the tungsten collimators which protect the triplets in the LHC experimental insertions, and the tracking results compared with semi-analytical numerical estimates. The simulations are also compared to the results of beam commissioning of these protection devices.

  16. Asynchronous vehicle pose correction using visual detection of ground features

    International Nuclear Information System (INIS)

    Harnarinesingh, Randy E S; Syan, Chanan S

    2014-01-01

    The inherent noise associated with odometry manifests itself as errors in localization for autonomous vehicles. Visual odometry has been previously used in order to supplement classical vehicle odometry. However, visual odometry is limited in its ability to reduce errors in localization for large travel distances that entail the cumulative summing of individual frame-to-frame image errors. In this paper, a novel machine vision approach for tiled surfaces is proposed to address this problem. Tile edges in a laboratory environment are used to define a travel trajectory for the Quansar Qbot (autonomous vehicle) built on the iRobot iRoomba platform with a forward facing camera. Tile intersections are used to enable asynchronous error recovery for vehicle position and orientation. The proposed approach employs real-time image classification and is feasible for error mitigation for large travel distances. The average position error for an 8m travel distance using classical odometry was measured to be 0.28m. However, implementation of the proposed approach resulted in an error of 0.028m. The proposed approach therefore significantly reduces pose estimation error and could be used to supplement existing modalities such as GPS and Laser-based range sensors

  17. Combining Synchronous and Asynchronous Collaboration within 3D City Models

    Science.gov (United States)

    Klimke, Jan; Döllner, Jürgen

    This paper presents an approach for combining spatially distributed synchronous and asynchronous collaboration within 3D city models. Software applications use these models as additional communication medium to facilitate communication of georeferenced and geospatial information. Collaboration tools should support both the communication with other collaborators and their awareness of the current collaboration context. To support collaborative knowledge construction and gathering, we have designed a collaboration system to facilitate (a) creation of annotations that have 3D references to the virtual 3D city model and (b) collection information about the context in which these annotations are created. Our approach supports synchronous collaboration in connection with the creation of non volatile, precisely georeferenced units of information allow for a comprehensible form of cooperation in spatially distributed settings. Storage and retrieval of this information is provided through a Web Feature Service, which eases integration of collaboration data into existing applications. We further introduce a visualization technique that integrates annotations as complex structured data into the 3D visualization. This avoids media breaks and disruptions in working processes and creates a spatial coherence between annotation and annotated feature or geometry.

  18. Synchronous versus asynchronous modeling of gene regulatory networks.

    Science.gov (United States)

    Garg, Abhishek; Di Cara, Alessandro; Xenarios, Ioannis; Mendoza, Luis; De Micheli, Giovanni

    2008-09-01

    In silico modeling of gene regulatory networks has gained some momentum recently due to increased interest in analyzing the dynamics of biological systems. This has been further facilitated by the increasing availability of experimental data on gene-gene, protein-protein and gene-protein interactions. The two dynamical properties that are often experimentally testable are perturbations and stable steady states. Although a lot of work has been done on the identification of steady states, not much work has been reported on in silico modeling of cellular differentiation processes. In this manuscript, we provide algorithms based on reduced ordered binary decision diagrams (ROBDDs) for Boolean modeling of gene regulatory networks. Algorithms for synchronous and asynchronous transition models have been proposed and their corresponding computational properties have been analyzed. These algorithms allow users to compute cyclic attractors of large networks that are currently not feasible using existing software. Hereby we provide a framework to analyze the effect of multiple gene perturbation protocols, and their effect on cell differentiation processes. These algorithms were validated on the T-helper model showing the correct steady state identification and Th1-Th2 cellular differentiation process. The software binaries for Windows and Linux platforms can be downloaded from http://si2.epfl.ch/~garg/genysis.html.

  19. [System of telesonography with synchronous teleconsultations and asynchronous telediagnoses (Togo)].

    Science.gov (United States)

    Adambounou, K; Farin, F; Boucher, A; Adjenou, K V; Gbeassor, M; N'dakena, K; Vincent, N; Arbeille, P

    2012-01-01

    Ultrasonography is an important nonirradiating diagnostic medical imaging procedure, frequently used, especially in urgent circumstances. This relatively inexpensive noninvasive examination makes it possible to diagnose disorders in various parts of the human body, by examining, for example, the abdomen and pelvis, the cardiovascular system, and the muscles and joints. Ultrasound is also an operator-dependent examination, in that the quality of the result depends on precision in the manipulation of the probe. Unfortunately, many small medical centers and isolated sites do not have an appropriate well-trained sonographer to perform initial evaluations, and an untrained operator cannot capture the appropriate echographic views required for a safe diagnosis of current patients, even with realtime vocal guidance (personal data). The lack of experienced physicians or qualified technicians means that diagnostic ultrasound is not always accessible to patients for rapid examination worldwide, especially in Africa, Amazonia or near the North or South Poles. This situation has led to the development of a new concept of telemedicine: telesonography, with a remote ultrasound diagnosis either in real time (synchronous) or delayed (asynchronous; store-and-forward). These systems of real-time telesonography and data transmission require expensive and complex technology with sophisticated equipment not available in many developing countries. The purpose of this study is to design a low-cost real-time system of telesonography for teleconsultations with experts and a delayed telediagnostic mode between isolated peripheral hospitals and a University Hospital center (UHC). An IP camera and an internet video server were installed in a geographically isolated site equipped with an ultrasound machine and an operator with basic training in its use. Synchronous teleconsultation (second-opinion diagnosis) is possible via internet with a UHC expert. If no ultrasound operator is available at

  20. An FPGA- Based General-Purpose Data Acquisition Controller

    Science.gov (United States)

    Robson, C. C. W.; Bousselham, A.; Bohm

    2006-08-01

    System development in advanced FPGAs allows considerable flexibility, both during development and in production use. A mixed firmware/software solution allows the developer to choose what shall be done in firmware or software, and to make that decision late in the process. However, this flexibility comes at the cost of increased complexity. We have designed a modular development framework to help to overcome these issues of increased complexity. This framework comprises a generic controller that can be adapted for different systems by simply changing the software or firmware parts. The controller can use both soft and hard processors, with or without an RTOS, based on the demands of the system to be developed. The resulting system uses the Internet for both control and data acquisition. In our studies we developed the embedded system in a Xilinx Virtex-II Pro FPGA, where we used both PowerPC and MicroBlaze cores, http, Java, and LabView for control and communication, together with the MicroC/OS-II and OSE operating systems

  1. Design and FPGA implementation for MAC layer of Ethernet PON

    Science.gov (United States)

    Zhu, Zengxi; Lin, Rujian; Chen, Jian; Ye, Jiajun; Chen, Xinqiao

    2004-04-01

    Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.

  2. Electronic readout for THGEM detectors based on FPGA TDCs

    Energy Technology Data Exchange (ETDEWEB)

    Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Koenigsmann, Kay; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut, Freiburg Univ. (Germany); Collaboration: COMPASS-II RICH upgrade Group

    2013-07-01

    In the framework of the RD51 programme the characteristics of a new detector design, called THGEM, which is based on multi-layer arrangements of printed circuit board material, is investigated. The THGEMs combine the advantages for covering gains up to 10{sup 6} in electron multiplication at large detector areas and low material budget. Studies are performed by extending the design to a hybrid gas detector by adding a Micromega layer, which significantly improves the ion back flow ratio of the chamber. With the upgrade of the COMPASS experiment at CERN a MWPC plane of the RICH-1 detector will be replaced by installing THGEM chambers. This summarizes to 40k channels of electronic readout, including amplification, discrimination and time-to-digital conversion of the anode signals. Due to the expected hit rate of the detector we design a cost-efficient TDC, based on Artix7 FPGA technology, with time resolution below 100 ps and sufficient hit buffer depth. To cover the large readout area the data is transferred via optical fibres to a central readout system which is part of the GANDALF framework.

  3. Cryogenic loss monitors with FPGA TDC signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Warner, A.; Wu, J.; /Fermilab

    2011-09-01

    Radiation hard helium gas ionization chambers capable of operating in vacuum at temperatures ranging from 5K to 350K have been designed, fabricated and tested and will be used inside the cryostats at Fermilab's Superconducting Radiofrequency beam test facility. The chamber vessels are made of stainless steel and all materials used including seals are known to be radiation hard and suitable for operation at 5K. The chambers are designed to measure radiation up to 30 kRad/hr with sensitivity of approximately 1.9 pA/(Rad/hr). The signal current is measured with a recycling integrator current-to-frequency converter to achieve a required measurement capability for low current and a wide dynamic range. A novel scheme of using an FPGA-based time-to-digital converter (TDC) to measure time intervals between pulses output from the recycling integrator is employed to ensure a fast beam loss response along with a current measurement resolution better than 10-bit. This paper will describe the results obtained and highlight the processing techniques used.

  4. Automation of FBTR fuel pin inspection using FPGA

    International Nuclear Information System (INIS)

    Khare, K.M.; Pai, Siddhesh; Pant, Brijesh; Sendhil Raja, S.; Gupta, P.K.

    2011-01-01

    A non-contact metrology system for inspection of FBTR fuel pins has been developed. The system consists of a stepper motors driven mechanism for orientation and positioning of FBTR fuel pin, a telecentric imaging system, absolute linear encoder with 0.1 μm resolution and a Field Programmable Gate Array (FPCA) based controller. The FBTR pin assembly is telecentrically illuminated from bottom by a red LED and its shadow graph is imaged using a CCD camera through telecentric imaging lens system. For system control and automation we have used a FPGA that has integrated soft picoblaze processor, X-θ axis motion controller, custom IPs for encoder data acquisition, synchronization circuit, RS485 interface along with other l/Os. Using the Graphical User Interface (GUI) on a PC the system is initialized at home position and the controller provides the trigger signal for start of data acquisition of CCD camera. CCD image of pin and the corresponding X-θ information is captured. After the acquisition of one set of images, the imaging module is moved with a step size pre-programmed to ensure proper stitching of acquired images. The GUI is programmed to analyze these X-θ Images to calculate the required parameters of the fuel pin like the diameter variation, pitch and bow. The details of the instrument and measurements made with it will be presented. (author)

  5. FPGA implementation of image dehazing algorithm for real time applications

    Science.gov (United States)

    Kumar, Rahul; Kaushik, Brajesh Kumar; Balasubramanian, R.

    2017-09-01

    Weather degradation such as haze, fog, mist, etc. severely reduces the effective range of visual surveillance. This degradation is a spatially varying phenomena, which makes this problem non trivial. Dehazing is an essential preprocessing stage in applications such as long range imaging, border security, intelligent transportation system, etc. However, these applications require low latency of the preprocessing block. In this work, single image dark channel prior algorithm is modified and implemented for fast processing with comparable visual quality of the restored image/video. Although conventional single image dark channel prior algorithm is computationally expensive, it yields impressive results. Moreover, a two stage image dehazing architecture is introduced, wherein, dark channel and airlight are estimated in the first stage. Whereas, transmission map and intensity restoration are computed in the next stages. The algorithm is implemented using Xilinx Vivado software and validated by using Xilinx zc702 development board, which contains an Artix7 equivalent Field Programmable Gate Array (FPGA) and ARM Cortex A9 dual core processor. Additionally, high definition multimedia interface (HDMI) has been incorporated for video feed and display purposes. The results show that the dehazing algorithm attains 29 frames per second for the image resolution of 1920x1080 which is suitable of real time applications. The design utilizes 9 18K_BRAM, 97 DSP_48, 6508 FFs and 8159 LUTs.

  6. FPGA-accelerated algorithm for the regular expression matching system

    Science.gov (United States)

    Russek, P.; Wiatr, K.

    2015-01-01

    This article describes an algorithm to support a regular expressions matching system. The goal was to achieve an attractive performance system with low energy consumption. The basic idea of the algorithm comes from a concept of the Bloom filter. It starts from the extraction of static sub-strings for strings of regular expressions. The algorithm is devised to gain from its decomposition into parts which are intended to be executed by custom hardware and the central processing unit (CPU). The pipelined custom processor architecture is proposed and a software algorithm explained accordingly. The software part of the algorithm was coded in C and runs on a processor from the ARM family. The hardware architecture was described in VHDL and implemented in field programmable gate array (FPGA). The performance results and required resources of the above experiments are given. An example of target application for the presented solution is computer and network security systems. The idea was tested on nearly 100,000 body-based viruses from the ClamAV virus database. The solution is intended for the emerging technology of clusters of low-energy computing nodes.

  7. An FPGA computing demo core for space charge simulation

    International Nuclear Information System (INIS)

    Wu, Jinyuan; Huang, Yifei

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computed using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.

  8. Functional verification of dynamically reconfigurable FPGA-based systems

    CERN Document Server

    Gong, Lingkan

    2015-01-01

    This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric.  Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an i...

  9. Implementation of Wireless Communications Systems on FPGA-Based Platforms

    Directory of Open Access Journals (Sweden)

    Voros NS

    2007-01-01

    Full Text Available Wireless communications are a very popular application domain. The efficient implementation of their components (access points and mobile terminals/network interface cards in terms of hardware cost and design time is of great importance. This paper describes the design and implementation of the HIPERLAN/2 WLAN system on a platform including general purpose microprocessors and FPGAs. Detailed implementation results (performance, code size, and FPGA resources utilization are presented. The main goal of the design case presented is to provide insight into the design aspects of a complex system based on FPGAs. The results prove that an implementation based on microprocessors and FPGAs is adequate for the access point part of the system where the expected volumes are rather small. At the same time, such an implementation serves as a prototyping of an integrated implementation (System-on-Chip, which is necessary for the mobile terminals of a HIPERLAN/2 system. Finally, firmware upgrades were developed allowing the implementation of an outdoor wireless communication system on the same platform.

  10. An FPGA computing demo core for space charge simulation

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jinyuan; Huang, Yifei; /Fermilab

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computed using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.

  11. Fast neuromimetic object recognition using FPGA outperforms GPU implementations.

    Science.gov (United States)

    Orchard, Garrick; Martin, Jacob G; Vogelstein, R Jacob; Etienne-Cummings, Ralph

    2013-08-01

    Recognition of objects in still images has traditionally been regarded as a difficult computational problem. Although modern automated methods for visual object recognition have achieved steadily increasing recognition accuracy, even the most advanced computational vision approaches are unable to obtain performance equal to that of humans. This has led to the creation of many biologically inspired models of visual object recognition, among them the hierarchical model and X (HMAX) model. HMAX is traditionally known to achieve high accuracy in visual object recognition tasks at the expense of significant computational complexity. Increasing complexity, in turn, increases computation time, reducing the number of images that can be processed per unit time. In this paper we describe how the computationally intensive and biologically inspired HMAX model for visual object recognition can be modified for implementation on a commercial field-programmable aate Array, specifically the Xilinx Virtex 6 ML605 evaluation board with XC6VLX240T FPGA. We show that with minor modifications to the traditional HMAX model we can perform recognition on images of size 128 × 128 pixels at a rate of 190 images per second with a less than 1% loss in recognition accuracy in both binary and multiclass visual object recognition tasks.

  12. FPGA-based prototype storage system with phase change memory

    Science.gov (United States)

    Li, Gezi; Chen, Xiaogang; Chen, Bomy; Li, Shunfen; Zhou, Mi; Han, Wenbing; Song, Zhitang

    2016-10-01

    With the ever-increasing amount of data being stored via social media, mobile telephony base stations, and network devices etc. the database systems face severe bandwidth bottlenecks when moving vast amounts of data from storage to the processing nodes. At the same time, Storage Class Memory (SCM) technologies such as Phase Change Memory (PCM) with unique features like fast read access, high density, non-volatility, byte-addressability, positive response to increasing temperature, superior scalability, and zero standby leakage have changed the landscape of modern computing and storage systems. In such a scenario, we present a storage system called FLEET which can off-load partial or whole SQL queries to the storage engine from CPU. FLEET uses an FPGA rather than conventional CPUs to implement the off-load engine due to its highly parallel nature. We have implemented an initial prototype of FLEET with PCM-based storage. The results demonstrate that significant performance and CPU utilization gains can be achieved by pushing selected query processing components inside in PCM-based storage.

  13. Asynchronous vs didactic education: it’s too early to throw in the towel on tradition

    Science.gov (United States)

    2013-01-01

    Background Asynchronous, computer based instruction is cost effective, allows self-directed pacing and review, and addresses preferences of millennial learners. Current research suggests there is no significant difference in learning compared to traditional classroom instruction. Data are limited for novice learners in emergency medicine. The objective of this study was to compare asynchronous, computer-based instruction with traditional didactics for senior medical students during a week-long intensive course in acute care. We hypothesized both modalities would be equivalent. Methods This was a prospective observational quasi-experimental study of 4th year medical students who were novice learners with minimal prior exposure to curricular elements. We assessed baseline knowledge with an objective pre-test. The curriculum was delivered in either traditional lecture format (shock, acute abdomen, dyspnea, field trauma) or via asynchronous, computer-based modules (chest pain, EKG interpretation, pain management, trauma). An interactive review covering all topics was followed by a post-test. Knowledge retention was measured after 10 weeks. Pre and post-test items were written by a panel of medical educators and validated with a reference group of learners. Mean scores were analyzed using dependent t-test and attitudes were assessed by a 5-point Likert scale. Results 44 of 48 students completed the protocol. Students initially acquired more knowledge from didactic education as demonstrated by mean gain scores (didactic: 28.39% ± 18.06; asynchronous 9.93% ± 23.22). Mean difference between didactic and asynchronous = 18.45% with 95% CI [10.40 to 26.50]; p = 0.0001. Retention testing demonstrated similar knowledge attrition: mean gain scores −14.94% (didactic); -17.61% (asynchronous), which was not significantly different: 2.68% ± 20.85, 95% CI [−3.66 to 9.02], p = 0.399. The attitudinal survey revealed that 60.4% of students believed the asynchronous

  14. Asynchronous vs didactic education: it's too early to throw in the towel on tradition.

    Science.gov (United States)

    Jordan, Jaime; Jalali, Azadeh; Clarke, Samuel; Dyne, Pamela; Spector, Tahlia; Coates, Wendy

    2013-08-08

    Asynchronous, computer based instruction is cost effective, allows self-directed pacing and review, and addresses preferences of millennial learners. Current research suggests there is no significant difference in learning compared to traditional classroom instruction. Data are limited for novice learners in emergency medicine. The objective of this study was to compare asynchronous, computer-based instruction with traditional didactics for senior medical students during a week-long intensive course in acute care. We hypothesized both modalities would be equivalent. This was a prospective observational quasi-experimental study of 4th year medical students who were novice learners with minimal prior exposure to curricular elements. We assessed baseline knowledge with an objective pre-test. The curriculum was delivered in either traditional lecture format (shock, acute abdomen, dyspnea, field trauma) or via asynchronous, computer-based modules (chest pain, EKG interpretation, pain management, trauma). An interactive review covering all topics was followed by a post-test. Knowledge retention was measured after 10 weeks. Pre and post-test items were written by a panel of medical educators and validated with a reference group of learners. Mean scores were analyzed using dependent t-test and attitudes were assessed by a 5-point Likert scale. 44 of 48 students completed the protocol. Students initially acquired more knowledge from didactic education as demonstrated by mean gain scores (didactic: 28.39% ± 18.06; asynchronous 9.93% ± 23.22). Mean difference between didactic and asynchronous = 18.45% with 95% CI [10.40 to 26.50]; p = 0.0001. Retention testing demonstrated similar knowledge attrition: mean gain scores -14.94% (didactic); -17.61% (asynchronous), which was not significantly different: 2.68% ± 20.85, 95% CI [-3.66 to 9.02], p = 0.399. The attitudinal survey revealed that 60.4% of students believed the asynchronous modules were educational and 95

  15. Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

    Energy Technology Data Exchange (ETDEWEB)

    Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I. [Research and Production Corporation Radiy, 29 Geroev Stalingrada Str., Kirovograd 25006 (Ukraine); Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A., E-mail: marketing@radiy.co [Center for Safety Infrastructure-Oriented Research and Analysis, 37 Astronomicheskaya Str., Kharkiv 61085 (Ukraine)

    2010-10-15

    The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY{sup TM} platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY{sup TM} platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY{sup TM} platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

  16. Design for an IO block array in a tile-based FPGA

    International Nuclear Information System (INIS)

    Ding Guangxin; Chen Lingdou; Liu Zhongli

    2009-01-01

    A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 μm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process. (semiconductor integrated circuits)

  17. Safety critical FPGA-based NPP instrumentation and control systems: assessment, development and implementation

    International Nuclear Information System (INIS)

    Bakhmach, E. S.; Siora, A. A.; Tokarev, V. I.; Kharchenko, V. S.; Sklyar, V. V.; Andrashov, A. A.

    2010-10-01

    The stages of development, production, verification, licensing and implementation methods and technologies of safety critical instrumentation and control systems for nuclear power plants (NPP) based on FPGA (Field Programmable Gates Arrays) technologies are described. A life cycle model and multi-version technologies of dependability and safety assurance of FPGA-based instrumentation and control systems are discussed. An analysis of NPP instrumentation and control systems construction principles developed by Research and Production Corporation Radiy using FPGA-technologies and results of these systems implementation and operation at Ukrainian and Bulgarian NPP are presented. The RADIY TM platform has been designed and developed by Research and Production Corporation Radiy, Ukraine. The main peculiarity of the RADIY TM platform is the use of FPGA as programmable components for logic control operation. The FPGA-based RADIY TM platform used for NPP instrumentation and control systems development ensures sca lability of system functions types, volume and peculiarities (by changing quantity and quality of sensors, actuators, input/output signals and control algorithms); sca lability of dependability (safety integrity) (by changing a number of redundant channel, tiers, diagnostic and reconfiguration procedures); sca lability of diversity (by changing types, depth and method of diversity selection). (Author)

  18. Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

    International Nuclear Information System (INIS)

    Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

    2016-01-01

    The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

  19. Motion camera based on a custom vision sensor and an FPGA architecture

    Science.gov (United States)

    Arias-Estrada, Miguel

    1998-09-01

    A digital camera for custom focal plane arrays was developed. The camera allows the test and development of analog or mixed-mode arrays for focal plane processing. The camera is used with a custom sensor for motion detection to implement a motion computation system. The custom focal plane sensor detects moving edges at the pixel level using analog VLSI techniques. The sensor communicates motion events using the event-address protocol associated to a temporal reference. In a second stage, a coprocessing architecture based on a field programmable gate array (FPGA) computes the time-of-travel between adjacent pixels. The FPGA allows rapid prototyping and flexible architecture development. Furthermore, the FPGA interfaces the sensor to a compact PC computer which is used for high level control and data communication to the local network. The camera could be used in applications such as self-guided vehicles, mobile robotics and smart surveillance systems. The programmability of the FPGA allows the exploration of further signal processing like spatial edge detection or image segmentation tasks. The article details the motion algorithm, the sensor architecture, the use of the event- address protocol for velocity vector computation and the FPGA architecture used in the motion camera system.

  20. Pediatric emergency medicine asynchronous e-learning: a multicenter randomized controlled Solomon four-group study.

    Science.gov (United States)

    Chang, Todd P; Pham, Phung K; Sobolewski, Brad; Doughty, Cara B; Jamal, Nazreen; Kwan, Karen Y; Little, Kim; Brenkert, Timothy E; Mathison, David J

    2014-08-01

    Asynchronous e-learning allows for targeted teaching, particularly advantageous when bedside and didactic education is insufficient. An asynchronous e-learning curriculum has not been studied across multiple centers in the context of a clinical rotation. We hypothesize that an asynchronous e-learning curriculum during the pediatric emergency medicine (EM) rotation improves medical knowledge among residents and students across multiple participating centers. Trainees on pediatric EM rotations at four large pediatric centers from 2012 to 2013 were randomized in a Solomon four-group design. The experimental arms received an asynchronous e-learning curriculum consisting of nine Web-based, interactive, peer-reviewed Flash/HTML5 modules. Postrotation testing and in-training examination (ITE) scores quantified improvements in knowledge. A 2 × 2 analysis of covariance (ANCOVA) tested interaction and main effects, and Pearson's correlation tested associations between module usage, scores, and ITE scores. A total of 256 of 458 participants completed all study elements; 104 had access to asynchronous e-learning modules, and 152 were controls who used the current education standards. No pretest sensitization was found (p = 0.75). Use of asynchronous e-learning modules was associated with an improvement in posttest scores (p effect (partial η(2) = 0.19). Posttest scores correlated with ITE scores (r(2) = 0.14, p e-learning is an effective educational tool to improve knowledge in a clinical rotation. Web-based asynchronous e-learning is a promising modality to standardize education among multiple institutions with common curricula, particularly in clinical rotations where scheduling difficulties, seasonality, and variable experiences limit in-hospital learning. © 2014 by the Society for Academic Emergency Medicine.

  1. [A novel proposal explaining sleep disturbance of children in Japan--asynchronization].

    Science.gov (United States)

    Kohyama, Jun

    2008-07-01

    It has been reported that more than half of the children in Japan suffer from daytime sleepiness. In contrast, about one quarter of junior high-school students in Japan complain of insomnia. According to the International Classification of Sleep Disorders (Second edition), these children could be diagnosed as having behaviorally-induced insufficient sleep syndrome due to inadequate sleeping habits. Getting on adequate amount of sleep should solve such problems;however, such a therapeutic approach often fails. Although social factors are involved in these sleep disturbances, I feel that a novel notion - asynchronization - leads to an understanding of the pathophysiology of disturbances in these children. Further, it could contribute to resolve their problems. The essence of asynchronization is a disturbance of various aspects (e.g., cycle, amplitude, phase, and interrelationship) of the biological rhythms that normally exhibits circadian oscillation. The main cause of asynchronization is hypothesized to be the combination of light exposure during night and the lack of light exposure in the morning. Asynchronization results in the disturbance of variable systems. Thus, symptoms of asynchronization include disturbances of the autonomic nervous system (sleepiness, insomnia, disturbance of hormonal excretion, gastrointestinal problems, etc.) and higher brain function (disorientation, loss of sociality, loss of will or motivation, impaired alertness and performance, etc.). Neurological (attention deficit, aggression, impulsiveness, hyperactivity, etc.), psychiatric (depressive disorders, personality disorders, anxiety disorders, etc.) and somatic (tiredness, fatigue, etc.) disturbances could also be symptoms of asynchronization. At the initial phase of asynchronization, disturbances are functional and can be resolved relatively easily, such as by the establishment of a regular sleep-wakefulness cycle;however, without adequate intervention the disturbances could gradually

  2. Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The report presents the experimental results in details. The Appendix lists the kernel source code.

  3. Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

  4. Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA

    DEFF Research Database (Denmark)

    Singh, Ritu; Kalia, Kartik; Minver, M. H.

    2016-01-01

    Abstract-In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective frequency of different mobile...

  5. Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Rehman, M. Atiqur; Hussain, Dil muhammed Akbar

    2016-01-01

    , SSTL and LVCMOS family respectively. Device static power and design static power are two types of static power dissipation. Device static power is also known as Leakage power when the device is on but not configured. Design static power is power dissipation when bit file of design is downloaded on FPGA......nm FPGA....

  6. Realization of manchester encoding and decoding and fast-speed communication for digital power supply based on FPGA

    International Nuclear Information System (INIS)

    Chen Huanguang; Xu Ruinian; Shen Tianjian; Li Deming

    2008-01-01

    A design and simulation to realize the process of Manchester encoding and decoding, to realize the process of SPI communication between FPGA and DSP, using Altera company's Quartus II IDE on FPGA is presented in this paper. And the application on the digital power supply controller with Manchester communication by optical fiber is introduced. (authors)

  7. Contributions a l'etude et a l'application industrielle de la machine asynchrone

    Science.gov (United States)

    Ouhrouche, Mohand-Ameziane

    The work presented in this thesis, done in the Electrical Drives Laboratory of Electrical and Computer Engineering Department, deals with the industrial applications of a three-phase induction machine (electrical drives and electricity generation). This thesis, characterized by its multidisciplinary content, has two major parts. The first one deals with the on-line and off-line parametric identification of the induction machine model necessary to achieve accurate vector control strategy. The second part, which is a resume of a research work sponsored by Hydro-Quebec, deals with the application of an induction machine in Asynchronous Non Utility Generators units (ANUG). As it is shown in the following, major scientific contributions are made in both two parts. In the first part of our research work, we propose a new speed sensorless vector control strategy for an induction machine, which is adaptive to the rotor resistance variations. The proposed control strategy is based on the Extended Kalman Filter approach and a decoupling controller which takes into account the rotor resistance variations. The consideration of coupled electrical and mechanical modes leads to a fifth order nonlinear model of the induction machine. The load torque is taken as a function of the rotor angular speed. The Extended Kalman Filter, based on the process's nonlinear (bilinear) model, estimate simultaneously the rotor resistance, angular speed and the flux vector from the startup to the steady state equilibrium point. The machine-converter-control system is implemented in MATLAB/SIMULINK environment and the obtained results confirm the robustness of the proposed scheme. As in the electrical drives erea, the induction machine is now widely used by small to medium power Non Utility Generator units (NUG) to produce electricity. In Quebec, these NUGs units are integrated into the Hydro-Quebec 25 kV distribution system via transformer which exhibit nonlinear characteristics. We have shown by

  8. Asynchronous Task-Based Parallelization of Algebraic Multigrid

    KAUST Repository

    AlOnazi, Amani A.

    2017-06-23

    As processor clock rates become more dynamic and workloads become more adaptive, the vulnerability to global synchronization that already complicates programming for performance in today\\'s petascale environment will be exacerbated. Algebraic multigrid (AMG), the solver of choice in many large-scale PDE-based simulations, scales well in the weak sense, with fixed problem size per node, on tightly coupled systems when loads are well balanced and core performance is reliable. However, its strong scaling to many cores within a node is challenging. Reducing synchronization and increasing concurrency are vital adaptations of AMG to hybrid architectures. Recent communication-reducing improvements to classical additive AMG by Vassilevski and Yang improve concurrency and increase communication-computation overlap, while retaining convergence properties close to those of standard multiplicative AMG, but remain bulk synchronous.We extend the Vassilevski and Yang additive AMG to asynchronous task-based parallelism using a hybrid MPI+OmpSs (from the Barcelona Supercomputer Center) within a node, along with MPI for internode communications. We implement a tiling approach to decompose the grid hierarchy into parallel units within task containers. We compare against the MPI-only BoomerAMG and the Auxiliary-space Maxwell Solver (AMS) in the hypre library for the 3D Laplacian operator and the electromagnetic diffusion, respectively. In time to solution for a full solve an MPI-OmpSs hybrid improves over an all-MPI approach in strong scaling at full core count (32 threads per single Haswell node of the Cray XC40) and maintains this per node advantage as both weak scale to thousands of cores, with MPI between nodes.

  9. iHadoop: Asynchronous Iterations Support for MapReduce

    KAUST Repository

    Elnikety, Eslam

    2011-08-01

    MapReduce is a distributed programming framework designed to ease the development of scalable data-intensive applications for large clusters of commodity machines. Most machine learning and data mining applications involve iterative computations over large datasets, such as the Web hyperlink structures and social network graphs. Yet, the MapReduce model does not efficiently support this important class of applications. The architecture of MapReduce, most critically its dataflow techniques and task scheduling, is completely unaware of the nature of iterative applications; tasks are scheduled according to a policy that optimizes the execution for a single iteration which wastes bandwidth, I/O, and CPU cycles when compared with an optimal execution for a consecutive set of iterations. This work presents iHadoop, a modified MapReduce model, and an associated implementation, optimized for iterative computations. The iHadoop model schedules iterations asynchronously. It connects the output of one iteration to the next, allowing both to process their data concurrently. iHadoop\\'s task scheduler exploits inter- iteration data locality by scheduling tasks that exhibit a producer/consumer relation on the same physical machine allowing a fast local data transfer. For those iterative applications that require satisfying certain criteria before termination, iHadoop runs the check concurrently during the execution of the subsequent iteration to further reduce the application\\'s latency. This thesis also describes our implementation of the iHadoop model, and evaluates its performance against Hadoop, the widely used open source implementation of MapReduce. Experiments using different data analysis applications over real-world and synthetic datasets show that iHadoop performs better than Hadoop for iterative algorithms, reducing execution time of iterative applications by 25% on average. Furthermore, integrating iHadoop with HaLoop, a variant Hadoop implementation that caches

  10. Design of optical axis jitter control system for multi beam lasers based on FPGA

    Science.gov (United States)

    Ou, Long; Li, Guohui; Xie, Chuanlin; Zhou, Zhiqiang

    2018-02-01

    A design of optical axis closed-loop control system for multi beam lasers coherent combining based on FPGA was introduced. The system uses piezoelectric ceramics Fast Steering Mirrors (FSM) as actuator, the Fairfield spot detection of multi beam lasers by the high speed CMOS camera for optical detecting, a control system based on FPGA for real-time optical axis jitter suppression. The algorithm for optical axis centroid detecting and PID of anti-Integral saturation were realized by FPGA. Optimize the structure of logic circuit by reuse resource and pipeline, as a result of reducing logic resource but reduced the delay time, and the closed-loop bandwidth increases to 100Hz. The jitter of laser less than 40Hz was reduced 40dB. The cost of the system is low but it works stably.

  11. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    Millar James

    2006-01-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  12. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    James Millar

    2006-10-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  13. FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool

    Directory of Open Access Journals (Sweden)

    Mohammed Bahoura

    2016-02-01

    Full Text Available In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA using Xilinx System Generator (XSG and the Nexys-4 Artix-7 FPGA board. This high-level programming tool allows us to design, simulate and execute the compiled design in Matlab/Simulink environment quickly and easily. Intermediate signals obtained at various steps of the proposed system are presented for typical blue whale calls. Classification performances based on the fixed-point XSG/FPGA implementation are compared to those obtained by the floating-point Matlab simulation, using a representative database of the blue whale calls.

  14. RADIOMETRIC CALIBRATION OF MARS HiRISE HIGH RESOLUTION IMAGERY BASED ON FPGA

    Directory of Open Access Journals (Sweden)

    Y. Hou

    2016-06-01

    Full Text Available Due to the large data amount of HiRISE imagery, traditional radiometric calibration method is not able to meet the fast processing requirements. To solve this problem, a radiometric calibration system of HiRISE imagery based on field program gate array (FPGA is designed. The montage gap between two channels caused by gray inconsistency is removed through histogram matching. The calibration system is composed of FPGA and DSP, which makes full use of the parallel processing ability of FPGA and fast computation as well as flexible control characteristic of DSP. Experimental results show that the designed system consumes less hardware resources and the real-time processing ability of radiometric calibration of HiRISE imagery is improved.

  15. Diversity for security: case assessment for FPGA-based safety-critical systems

    Directory of Open Access Journals (Sweden)

    Kharchenko Vyacheslav

    2016-01-01

    Full Text Available Industrial safety critical instrumentation and control systems (I&Cs are facing more with information (in general and cyber, in particular security threats and attacks. The application of programmable logic, first of all, field programmable gate arrays (FPGA in critical systems causes specific safety deficits. Security assessment techniques for such systems are based on heuristic knowledges and the expert judgment. Main challenge is how to take into account features of FPGA technology for safety critical I&Cs including systems in which are applied diversity approach to minimize risks of common cause failure. Such systems are called multi-version (MV systems. The goal of the paper is in description of the technique and tool for case-based security assessment of MV FPGA-based I&Cs.

  16. An efficient and cost effective FPGA based implementation of the Viola-Jones face detection algorithm

    Directory of Open Access Journals (Sweden)

    Peter Irgens

    2017-04-01

    Full Text Available We present an field programmable gate arrays (FPGA based implementation of the popular Viola-Jones face detection algorithm, which is an essential building block in many applications such as video surveillance and tracking. Our implementation is a complete system level hardware design described in a hardware description language and validated on the affordable DE2-115 evaluation board. Our primary objective is to study the achievable performance with a low-end FPGA chip based implementation. In addition, we release to the public domain the entire project. We hope that this will enable other researchers to easily replicate and compare their results to ours and that it will encourage and facilitate further research and educational ideas in the areas of image processing, computer vision, and advanced digital design and FPGA prototyping.

  17. Implementation of 4-way Superscalar Hash MIPS Processor Using FPGA

    Science.gov (United States)

    Sahib Omran, Safaa; Fouad Jumma, Laith

    2018-05-01

    Due to the quick advancements in the personal communications systems and wireless communications, giving data security has turned into a more essential subject. This security idea turns into a more confounded subject when next-generation system requirements and constant calculation speed are considered in real-time. Hash functions are among the most essential cryptographic primitives and utilized as a part of the many fields of signature authentication and communication integrity. These functions are utilized to acquire a settled size unique fingerprint or hash value of an arbitrary length of message. In this paper, Secure Hash Algorithms (SHA) of types SHA-1, SHA-2 (SHA-224, SHA-256) and SHA-3 (BLAKE) are implemented on Field-Programmable Gate Array (FPGA) in a processor structure. The design is described and implemented using a hardware description language, namely VHSIC “Very High Speed Integrated Circuit” Hardware Description Language (VHDL). Since the logical operation of the hash types of (SHA-1, SHA-224, SHA-256 and SHA-3) are 32-bits, so a Superscalar Hash Microprocessor without Interlocked Pipelines (MIPS) processor are designed with only few instructions that were required in invoking the desired Hash algorithms, when the four types of hash algorithms executed sequentially using the designed processor, the total time required equal to approximately 342 us, with a throughput of 4.8 Mbps while the required to execute the same four hash algorithms using the designed four-way superscalar is reduced to 237 us with improved the throughput to 5.1 Mbps.

  18. STAR: FPGA-based software defined satellite transponder

    Science.gov (United States)

    Davalle, Daniele; Cassettari, Riccardo; Saponara, Sergio; Fanucci, Luca; Cucchi, Luca; Bigongiari, Franco; Errico, Walter

    2013-05-01

    This paper presents STAR, a flexible Telemetry, Tracking & Command (TT&C) transponder for Earth Observation (EO) small satellites, developed in collaboration with INTECS and SITAEL companies. With respect to state-of-the-art EO transponders, STAR includes the possibility of scientific data transfer thanks to the 40 Mbps downlink data-rate. This feature represents an important optimization in terms of hardware mass, which is important for EO small satellites. Furthermore, in-flight re-configurability of communication parameters via telecommand is important for in-orbit link optimization, which is especially useful for low orbit satellites where visibility can be as short as few hundreds of seconds. STAR exploits the principles of digital radio to minimize the analog section of the transceiver. 70MHz intermediate frequency (IF) is the interface with an external S/X band radio-frequency front-end. The system is composed of a dedicated configurable high-speed digital signal processing part, the Signal Processor (SP), described in technology-independent VHDL working with a clock frequency of 184.32MHz and a low speed control part, the Control Processor (CP), based on the 32-bit Gaisler LEON3 processor clocked at 32 MHz, with SpaceWire and CAN interfaces. The quantization parameters were fine-tailored to reach a trade-off between hardware complexity and implementation loss which is less than 0.5 dB at BER = 10-5 for the RX chain. The IF ports require 8-bit precision. The system prototype is fitted on the Xilinx Virtex 6 VLX75T-FF484 FPGA of which a space-qualified version has been announced. The total device occupation is 82 %.

  19. Multichannel analyzer for nuclear spectrometry with FPGA using Vivado

    International Nuclear Information System (INIS)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R.; Ordaz G, O. O.; Ibarra D, S.; Bravo M, I.

    2017-09-01

    The different applications of ionizing radiation have made this a very significant and useful tool, in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, cannot be perceived by the five senses, in such a way that in order to know the presence of it, radiation detectors and additional devices are required that allow to quantify and classify it. This is the case of the multichannel analyzer that is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The development or conditioning of nuclear technology has increased considerably due to the demand of the applications; therefore this allows developing systems that cover some commercial requirements, cost and volume in relation to the user needs. The objective of the work was to design and implement an intellectual property core (IP Core) which functions as a multichannel analyzer for nuclear spectrometry. For the IP Core design methodology, its components were created in VHDL hardware description language and packaged in the Vivado design suite, making use of resources such as the ARM processor cores that the Zynq chip contains. Likewise, for the first phase of the implementation, the hardware architecture was embedded in the FPGA and the application for the ARM processor was programmed in C language. For the second phase, the management, control and visualization of the results, a virtual instrument was developed in the LabView programming platform. The data obtained as a result of the development and implementation of the IP Core was observed graphically in a histogram that is part of the aforementioned virtual instrument. (Author)

  20. [Cost-effectiveness of Synchronous vs. Asynchronous Telepsychiatry in Prison Inmates With Depression].

    Science.gov (United States)

    Barrera-Valencia, Camilo; Benito-Devia, Alexis Vladimir; Vélez-Álvarez, Consuelo; Figueroa-Barrera, Mario; Franco-Idárraga, Sandra Milena

    Telepsychiatry is defined as the use of information and communication technology (ICT) in providing remote psychiatric services. Telepsychiatry is applied using two types of communication: synchronous (real time) and asynchronous (store and forward). To determine the cost-effectiveness of a synchronous and an asynchronous telepsychiatric model in prison inmate patients with symptoms of depression. A cost-effectiveness study was performed on a population consisting of 157 patients from the Establecimiento Penitenciario y Carcelario de Mediana Seguridad de Manizales, Colombia. The sample was determined by applying Zung self-administered surveys for depression (1965) and the Hamilton Depression Rating Scale (HDRS), the latter being the tool used for the comparison. Initial Hamilton score, arrival time, duration of system downtime, and clinical effectiveness variables had normal distributions (P>.05). There were significant differences (P<.001) between care costs for the different models, showing that the mean cost of the asynchronous model is less than synchronous model, and making the asynchronous model more cost-effective. The asynchronous model is the most cost-effective model of telepsychiatry care for patients with depression admitted to a detention centre, according to the results of clinical effectiveness, cost measurement, and patient satisfaction. Copyright © 2016 Asociación Colombiana de Psiquiatría. Publicado por Elsevier España. All rights reserved.