Design and Verification of Application Specific Integrated Circuits in a Network of Online Labs

Directory of Open Access Journals (Sweden)

A.Y. Al-Zoubi

2009-08-01

Full Text Available A solution to implement a remote laboratory for testing and designing analog Application-Specific Integrated Circuits of the type (ispPAC10 is presented. The application allows electrical engineering students to access and perform measurements and conduct analog electronics experiments over the internet. PAC-Designer software, running on a Citrix server, is used in the circuit design in which the signals are generated and the responses are acquired by a data acquisition board controlled by LabVIEW. Three interconnected remote labs located in three different continents will be implementing the proposed system.

Source-circuit design overview

Science.gov (United States)

Ross, R. G., Jr.

1983-01-01

The source circuit is the fundamental electrical building block of a large central-station array; it consists of a series-parallel network of solar cells that develops full system voltage. The array field is generally made up of a large number of parallel source circuits. Source-circuit electrical configuration is driven by a number of design considerations, which must be considered simultaneously. Array fault tolerance and hot spot heating endurance are examined in detail.

Multiuser remote access to distributed heterogeneous system of programmable logic based laboratory equipment for remote digital circuits design labs

Directory of Open Access Journals (Sweden)

Mikhail N. Yokhin

2017-12-01

Full Text Available The paper contains an analysis of perspective structures of software and hardware equipment of universal digital design laboratories with the purpose of enabling laboratory classes of digital circuit design to be taken remotely. Implementation characteristics and usage experience of some of those structures applied to labs on several hardware related courses of « Computer science and computer engineering» program in NRNU MEPhI are presented. The paper also considers different aspects of usage of remote access enabled laboratory which should be taken into account to substantiate laboratory configuration from technical and economical standpoints. To increase equipment usage efficiency an approach to group several distinct projects to place them on a single FPGA chip is proposed. The paper shows advisability and gives an example of parametrizable virtual stand for remote debugging of FPGA projects.

Simplified design of filter circuits

CERN Document Server

Lenk, John

1999-01-01

Simplified Design of Filter Circuits, the eighth book in this popular series, is a step-by-step guide to designing filters using off-the-shelf ICs. The book starts with the basic operating principles of filters and common applications, then moves on to describe how to design circuits by using and modifying chips available on the market today. Lenk's emphasis is on practical, simplified approaches to solving design problems.Contains practical designs using off-the-shelf ICsStraightforward, no-nonsense approachHighly illustrated with manufacturer's data sheets

Automatic design of digital synthetic gene circuits.

Directory of Open Access Journals (Sweden)

Mario A Marchisio

2011-02-01

Full Text Available De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.

Semiconductors integrated circuit design for manufacturability

CERN Document Server

Balasinki, Artur

2011-01-01

Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

Digital logic circuit design with ALTERA MAX+PLUS II

International Nuclear Information System (INIS)

Lee, Seung Ho; Park, Yong Su; Lee, Ju Heon

2006-03-01

Contents of this book are the kinds of integrated circuit, design process of integrated circuit, introduction of ALTERA MAX+PLUS II, designing logic circuit with VHDL of ALTERA MAX+PLUS II, grammar and practice of VHDL of ALTERA MAX+PLUS II, design for adder, subtractor, parallel binary subtractor, BCD design, CLA design, code converter design, ALU design, register design, counter design, accumulator design, state machine design, frequency divider design, circuit design with TENMILLION counter, LCD module, circuit design for control the outside RAM in training kit and introduction for HEB-DTK-20K-240/HBE-DTK-IOK.

Design of analog integrated circuits and systems

CERN Document Server

Laker, Kenneth R

1994-01-01

This text is designed for senior or graduate level courses in analog integrated circuits or design of analog integrated circuits. This book combines consideration of CMOS and bipolar circuits into a unified treatment. Also included are CMOS-bipolar circuits made possible by BiCMOS technology. The text progresses from MOS and bipolar device modelling to simple one and two transistor building block circuits. The final two chapters present a unified coverage of sample-data and continuous-time signal processing systems.

Sequential circuit design for radiation hardened multiple voltage integrated circuits

Science.gov (United States)

Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

2009-11-24

The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

Designing Novel Quaternary Quantum Reversible Subtractor Circuits

Science.gov (United States)

Haghparast, Majid; Monfared, Asma Taheri

2018-01-01

Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Science.gov (United States)

Lohn, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris; Norvig, Peter (Technical Monitor)

2000-01-01

We describe a parallel genetic algorithm (GA) that automatically generates circuit designs using evolutionary search. A circuit-construction programming language is introduced and we show how evolution can generate practical analog circuit designs. Our system allows circuit size (number of devices), circuit topology, and device values to be evolved. We present experimental results as applied to analog filter and amplifier design tasks.

A guide to printed circuit board design

CERN Document Server

Hamilton, Charles

1984-01-01

A Guide to Printed Circuit Board Design discusses the basic design principles of printed circuit board (PCB). The book consists of nine chapters; each chapter provides both text discussion and illustration relevant to the topic being discussed. Chapter 1 talks about understanding the circuit diagram, and Chapter 2 covers how to compile component information file. Chapter 3 deals with the design layout, while Chapter 4 talks about preparing the master artworks. The book also covers generating computer aided design (CAD) master patterns, and then discusses how to prepare the production drawing a

Energy efficient circuit design using nanoelectromechanical relays

Science.gov (United States)

Venkatasubramanian, Ramakrishnan

Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS

Circuit design techniques for non-crystalline semiconductors

CERN Document Server

Sambandan, Sanjiv

2012-01-01

Despite significant progress in materials and fabrication technologies related to non-crystalline semiconductors, fundamental drawbacks continue to limit real-world application of these devices in electronic circuits. To help readers deal with problems such as low mobility and intrinsic time variant behavior, Circuit Design Techniques for Non-Crystalline Semiconductors outlines a systematic design approach, including circuit theory, enabling users to synthesize circuits without worrying about the details of device physics. This book: Offers examples of how self-assembly can be used as a powerf

Reverse Engineering Camouflaged Sequential Integrated Circuits Without Scan Access

OpenAIRE

Massad, Mohamed El; Garg, Siddharth; Tripunitara, Mahesh

2017-01-01

Integrated circuit (IC) camouflaging is a promising technique to protect the design of a chip from reverse engineering. However, recent work has shown that even camouflaged ICs can be reverse engineered from the observed input/output behaviour of a chip using SAT solvers. However, these so-called SAT attacks have so far targeted only camouflaged combinational circuits. For camouflaged sequential circuits, the SAT attack requires that the internal state of the circuit is controllable and obser...

Microelectronic circuit design for energy harvesting systems

CERN Document Server

Di Paolo Emilio, Maurizio

2017-01-01

This book describes the design of microelectronic circuits for energy harvesting, broadband energy conversion, new methods and technologies for energy conversion. The author also discusses the design of power management circuits and the implementation of voltage regulators. Coverage includes advanced methods in low and high power electronics, as well as principles of micro-scale design based on piezoelectric, electromagnetic and thermoelectric technologies with control and conditioning circuit design. Provides a single-source reference to energy harvesting and its applications; Serves as a practical guide to microelectronics design for energy harvesting, with application to mobile power supplies; Enables readers to develop energy harvesting systems for wearable/mobile electronics.

Macromodels of digital integrated circuits for program packages of circuit engineering design

Science.gov (United States)

Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

1984-04-01

Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

Foundations for microstrip circuit design

CERN Document Server

Edwards, Terry

2016-01-01

Building on the success of the previous three editions, Foundations for Microstrip Circuit Design offers extensive new, updated and revised material based upon the latest research. Strongly design-oriented, this fourth edition provides the reader with a fundamental understanding of this fast expanding field making it a definitive source for professional engineers and researchers and an indispensable reference for senior students in electronic engineering. Topics new to this edition: microwave substrates, multilayer transmission line structures, modern EM tools and techniques, microstrip and planar transmision line design, transmission line theory, substrates for planar transmission lines, Vias, wirebonds, 3D integrated interposer structures, computer-aided design, microstrip and power-dependent effects, circuit models, microwave network analysis, microstrip passive elements, and slotline design fundamentals.

Design and Test of Application-Specific Integrated Circuits by use of Mobile Clients

Directory of Open Access Journals (Sweden)

Michael Auer

2009-02-01

Full Text Available The aim of this work is to develop a simultaneous multi user access system – READ (Remote ASIC Design and Test that allows users to perform test and measurements remotely via clients running on mobile devices as well as on standard PCs. The system also facilitates the remote design of circuits with the PAC-Designer The system is controlled by LabVIEW and was implemented using a Data Acquisition Card from National instruments. Such systems are specially suited for manufacturing process monitoring and control. The performance of the simultaneous access was tested under load with a variable number of users. The server implements a queue that processes user’s commands upon request.

Analog integrated circuits design for processing physiological signals.

Science.gov (United States)

Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

2010-01-01

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

Wireless transceiver circuits system perspectives and design aspects

CERN Document Server

Rhee, Woogeun

2015-01-01

This cutting-edge work contains comprehensive coverage of integrated circuit (IC) design for modern transceiver circuits and wireless systems. Ranging in scope from system perspectives to practical circuit design for emerging wireless applications, the book includes detailed discussions of transceiver architectures and system parameters, mm-wave circuits, ultra-low-power radios for biomedical and sensor applications, and the latest circuit techniques. Written by renowned international experts in IC industry and academia, the text is an ideal reference for engineers and researchers in the area

Circuit arrangement of an electronic component for the design of fail-safe protective circuits

International Nuclear Information System (INIS)

Centmaier, W.; Bernhard, U.; Friederich, B.; Heisecke, I.

1974-01-01

The critical parameters of reactors are controlled by safety circuits. These circuits are controlled designed as logic modules operating by the 'n-out-of-m' selection principle. In most cases, a combination of a '1-out-of-3' circuit with a '2-out-of-3' circuit and separate indication is sufficient for a dynamic fail-safe circuit. The basic logic elements are AND and OR gate circuits, respectively, which are triggered by pulse trains and in which the failure of a pulse train is indicated as an error at the output. The module allows the design of safety circuits offering various degrees of safety. If the indication of an error is made on the modules, faulty components can be exchanged by the maintenance crew right away. (DG) [de

23rd workshop on Advances in Analog Circuit Design

CERN Document Server

Baschirotto, Andrea; Makinwa, Kofi

2015-01-01

This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design.  Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.    • Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing; • Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; • Presents material in a tutorial-based format.

Oscillator circuits frontiers in design, analysis and applications

CERN Document Server

2016-01-01

This book surveys recent developments in the design, analysis and applications of oscillator circuit design. It highlights developments in the analysis of synchronization and wave phenomena, new analytical and design methods and their application, and novel engineering applications of oscillator circuits.

The design of charge measurement circuit of MWPC

International Nuclear Information System (INIS)

Guan Xiaolei; Xiang Haisheng; Sheng Huayi; Zhao Yubin; Zhao Pingping; Zhang Hongyu; Jiang Xiaoshan; Zhao Jingwei; Zhao Dongxu

2010-01-01

It introduces the design of charge measurement (MQ) circuit of MWPC, including how MQ works in the whole MWPC readout electronic system, the architecture of MQ circuit, and the logic and algorithm design of FPGA. MQ circuit can also be applied to readout systems for other detectors. The test results in different working modes are provided. (authors)

CAD-CAM printed circuit board design

Science.gov (United States)

Agy, W. E.

A step-by-step procedure for a printed circuit design achieved by CAD is presented. The operator at the interactive CRT station moves a stylus across a graphics tablet and intersperses commands which result in computer-generated pictorial forms on the screen that were drawn on the pad. Standard symbols are used for commands allowing, for instance, connections to be made of specific types in certain locations, which can be automatically edited from a materials list. An entire network of drawn lines can be referenced by a signal name for recall, and a finished circuit schematic can be checked for designs rules compliance, including fault reporting in terms of designator/pin number. A map may be present delineating the boundaries of the circuitry area, and previously completed circuitry segments can be recalled for piece-by-piece assembly of the circuit board.

RF microwave circuit design for wireless applications

CERN Document Server

Rohde, Ulrich L

2012-01-01

Provides researchers and engineers with a complete set of modeling, design, and implementation tools for tackling the newest IC technologies Revised and completely updated, RF/Microwave Circuit Design for Wireless Applications, Second Edition is a unique, state-of-the-art guide to wireless integrated circuit design that provides researchers and engineers with a complete set of modeling, design, and implementation tools for tackling even the newest IC technologies. It emphasizes practical design solutions for high-performance devices and circuitry, incorporating ample exa

Design optimization of radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

1975-01-01

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

Design, Analysis and Test of Logic Circuits Under Uncertainty

CERN Document Server

Krishnaswamy, Smita; Hayes, John P

2013-01-01

Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:   • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;   • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-l...

Essential knowledge for transistor-level LSI circuit design

CERN Document Server

Nakura, Toru

2016-01-01

This book is a collection of the miscellaneous knowledge essential for transistor-level LSI circuit design, summarized as the issues that need to be considered in each design step. To design an LSI that actually functions and to be able to properly measure it, an extremely large amount of diverse, detailed knowledge is necessary. Even though one may read a textbook about an op-amp, for example, the op-amp circuit design may not actually be possible to complete in one’s CAD tools. The first half of this text explains important design issues such as the operating principles of CAD tools, including schematic entry, SPICE simulation, layout and verification, and RC extraction. Then, mistake-prone topics for many circuit design beginners, resulting from their lack of consideration of these subjects, are explained including IO buffers, noise, and problems due to the progress of miniaturization. Following these topics, basic but very specialized issues for LSI circuit measurement are explained including measuremen...

RF Circuit Design in Nanometer CMOS

NARCIS (Netherlands)

Nauta, Bram

2007-01-01

With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

Controllable clock circuit design in PEM system

International Nuclear Information System (INIS)

Sun Yunhua; Wang Peihua; Hu Tingting; Feng Baotong; Shuai Lei; Huang Huan; Wei Shujun; Li Ke; Zhao Jingwei; Wei Long

2011-01-01

A high-precision synchronized clock circuit design will be presented, which can supply steady, reliable and anti-jamming clock signal for the data acquirement (DAQ) system of Positron Emission Mammography (PEM). This circuit design is based on the Single-Chip Microcomputer and high-precision clock chip, and can achieve multiple controllable clock signals. The jamming between the clock signals can be reduced greatly with the differential transmission. Meanwhile, the adoption of CAN bus control in the clock circuit can prompt the clock signals to be transmitted or masked simultaneously when needed. (authors)

Controllable clock circuit design in PEM system

International Nuclear Information System (INIS)

Sun Yunhua; Wang Peilin; Hu Tingting; Feng Baotong; Shuai Lei; Huang Huan; Wei Shujun; Li Ke; Zhao Jingwei; Wei Long

2010-01-01

A high-precision synchronized clock circuit design will be presented, which can supply steady, reliable and anti-jamming clock signal for the data acquirement (DAQ) system of Positron Emission Mammography (PEM). This circuit design is based on the Single-Chip Microcomputer and high-precision clock chip, and can achieve multiple controllable clock signals. The jamming between the clock signals can be reduced greatly with the differential transmission. Meanwhile, the adoption of CAN bus control in the clock circuit can prompt the clock signals to be transmitted or masked simultaneously when needed. (authors)

Practical design of digital circuits basic logic to microprocessors

CERN Document Server

Kampel, Ian

1983-01-01

Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible. The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his """"tools"""" - or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptio

Design of 3D integrated circuits and systems

CERN Document Server

Sharma, Rohit

2014-01-01

Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

Low cost design of microprocessor EDAC circuit

International Nuclear Information System (INIS)

Hao Li; Yu Lixin; Peng Heping; Zhuang Wei

2015-01-01

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)

Introduction of circuit design on RFID system

International Nuclear Information System (INIS)

Pak, Sunho

2007-06-01

This is a case of research of Fujitsu company and design of basic circuit of electronic technique. It is composed of two parts. The first part deals with introduction of RFID system design, which lists basic knowledge of ubiquitous, glossary of high frequency, design of impedance matching circuit, RFID system, sorts and design of filter, modulator and a transmission and RFID system design. The second part deals with research and development of Fujitsu company, including RFID middle ware RFID CONNECT of Fujitsu, sensor network of Fujitsu and high handing technique of RFID system.

Introduction of circuit design on RFID system

Energy Technology Data Exchange (ETDEWEB)

Pak, Sunho

2007-06-15

This is a case of research of Fujitsu company and design of basic circuit of electronic technique. It is composed of two parts. The first part deals with introduction of RFID system design, which lists basic knowledge of ubiquitous, glossary of high frequency, design of impedance matching circuit, RFID system, sorts and design of filter, modulator and a transmission and RFID system design. The second part deals with research and development of Fujitsu company, including RFID middle ware RFID CONNECT of Fujitsu, sensor network of Fujitsu and high handing technique of RFID system.

Circuit and interconnect design for high bit-rate applications

NARCIS (Netherlands)

Veenstra, H.

2006-01-01

This thesis presents circuit and interconnect design techniques and design flows that address the most difficult and ill-defined aspects of the design of ICs for high bit-rate applications. Bottlenecks in interconnect design, circuit design and on-chip signal distribution for high bit-rate

Hardware security and trust design and deployment of integrated circuits in a threatened environment

CERN Document Server

Chaves, Ricardo; Natale, Giorgio; Regazzoni, Francesco

2017-01-01

This book provides a comprehensive introduction to hardware security, from specification to implementation. Applications discussed include embedded systems ranging from small RFID tags to satellites orbiting the earth. The authors describe a design and synthesis flow, which will transform a given circuit into a secure design incorporating counter-measures against fault attacks. In order to address the conflict between testability and security, the authors describe innovative design-for-testability (DFT) computer-aided design (CAD) tools that support security challenges, engineered for compliance with existing, commercial tools. Secure protocols are discussed, which protect access to necessary test infrastructures and enable the design of secure access controllers. Covers all aspects of hardware security including design, manufacturing, testing, reliability, validation and utilization; Describes new methods and algorithms for the identification/detection of hardware trojans; Defines new architectures capable o...

On stethoscope design: a challenge for biomedical circuit designers.

Science.gov (United States)

Hahn, A W

2001-01-01

Most clinicians learned the art and science of auscultation using an acoustic stethoscope. While many models of electronic stethoscopes have been marketed over the years, none of them seem to do a very good job of emulating the most common forms of acoustic stethoscopes available. This paper is an appeal to biomedical circuit designers to learn more about the acoustics of commonly used stethoscopes and to develop an appropriate group of circuits which would emulate them much like music synthesizers can emulate almost any musical instrument. The implications are for creative designers to move toward a rational and acceptable design for both personal physician use and for telemedicine.

Analog circuit design art, science and personalities

CERN Document Server

Williams, Jim

1991-01-01

This book is far more than just another tutorial or reference guide - it's a tour through the world of analog design, combining theory and applications with the philosophies behind the design process. Readers will learn how leading analog circuit designers approach problems and how they think about solutions to those problems. They'll also learn about the `analog way' - a broad, flexible method of thinking about analog design tasks.A comprehensive and useful guide to analog theory and applications. Covers visualizing the operation of analog circuits. Looks at how to rap

25th workshop on Advances in Analog Circuit Design

CERN Document Server

Harpe, Pieter; Makinwa, Kofi

2017-01-01

This book is based on the 18 tutorials presented during the 25th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of continuous-time sigma-delta modulators, automotive electronics, and power management. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

Applications of modularized circuit designs in a new hyper-chaotic system circuit implementation

International Nuclear Information System (INIS)

Wang Rui; Sun Hui; Wang Jie-Zhi; Wang Lu; Wang Yan-Chao

2015-01-01

Modularized circuit designs for chaotic systems are introduced in this paper. Especially, a typical improved modularized design strategy is proposed and applied to a new hyper-chaotic system circuit implementation. In this paper, the detailed design procedures are described. Multisim simulations and physical experiments are conducted, and the simulation results are compared with Matlab simulation results for different system parameter pairs. These results are consistent with each other and they verify the existence of the hyper-chaotic attractor for this new hyper-chaotic system. (paper)

New way on designing majorant coincidence circuits

International Nuclear Information System (INIS)

Gajdamaka, R.I.; Kalinnikov, V.A.; Nikityuk, N.M.; Shirikov, V.P.

1982-01-01

A new way of designing fast devices of combinatorial selection by the number of particles passing through a multichannel charged particle detector is decribed. The algorithm of their operation is based on modern algebraic coding theory. By application of analytical computational methods Boolean expressions can be obtianed for designing basic circuits for a large number of inputs. An example of computation of 15 inputs majorant coincidence circuit is considered

Designing Asynchronous Circuits for Low Power: An IFIR Filter

DEFF Research Database (Denmark)

Nielsen, Lars Skovby; Sparsø, Jens

1999-01-01

This paper addresses the design of asynchronous circuits for low power through an example: a filter bank for a digital hearing aid. The asynchronous design re-implements an existing synchronous circuit which is used in a commercial product. For comparison, both designs have been fabricated...

Insulated transcriptional elements enable precise design of genetic circuits.

Science.gov (United States)

Zong, Yeqing; Zhang, Haoqian M; Lyu, Cheng; Ji, Xiangyu; Hou, Junran; Guo, Xian; Ouyang, Qi; Lou, Chunbo

2017-07-03

Rational engineering of biological systems is often complicated by the complex but unwanted interactions between cellular components at multiple levels. Here we address this issue at the level of prokaryotic transcription by insulating minimal promoters and operators to prevent their interaction and enable the biophysical modeling of synthetic transcription without free parameters. This approach allows genetic circuit design with extraordinary precision and diversity, and consequently simplifies the design-build-test-learn cycle of circuit engineering to a mix-and-match workflow. As a demonstration, combinatorial promoters encoding NOT-gate functions were designed from scratch with mean errors of 96% using our insulated transcription elements. Furthermore, four-node transcriptional networks with incoherent feed-forward loops that execute stripe-forming functions were obtained without any trial-and-error work. This insulation-based engineering strategy improves the resolution of genetic circuit technology and provides a simple approach for designing genetic circuits for systems and synthetic biology.Unwanted interactions between cellular components can complicate rational engineering of biological systems. Here the authors design insulated minimal promoters and operators that enable biophysical modeling of bacterial transcription without free parameters for precise circuit design.

Programming languages for circuit design.

Science.gov (United States)

Pedersen, Michael; Yordanov, Boyan

2015-01-01

This chapter provides an overview of a programming language for Genetic Engineering of Cells (GEC). A GEC program specifies a genetic circuit at a high level of abstraction through constraints on otherwise unspecified DNA parts. The GEC compiler then selects parts which satisfy the constraints from a given parts database. GEC further provides more conventional programming language constructs for abstraction, e.g., through modularity. The GEC language and compiler is available through a Web tool which also provides functionality, e.g., for simulation of designed circuits.

Circuit design for RF transceivers

CERN Document Server

Leenaerts, Domine; Vaucher, Cicero S

2007-01-01

Second edition of this successful 2001 RF Circuit Design book, has been updated, latest technology reviews have been added as well as several actual case studies. Due to the authors being active in industry as well as academia, this should prove to be an essential guide on RF Transceiver Design for students and engineers.

A new integrated microwave SQUID circuit design

International Nuclear Information System (INIS)

Erne, S.N.; Finnegan, T.F.

1980-01-01

In this paper we consider the design and operation of a planar thin-film rf-SQUID circuit which can be realized via microwave-integrated-circuit (MIC) techniques and which differs substantially from pervious microwave SQUID configurations involving either mechanical point-contact or cylindrical thin-film micro-bridge geometries. (orig.)

Design of ternary clocked adiabatic static random access memory

International Nuclear Information System (INIS)

Wang Pengjun; Mei Fengna

2011-01-01

Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions. (semiconductor integrated circuits)

Design for Accessibility

DEFF Research Database (Denmark)

Herriott, Richard

2012-01-01

A report on how nine rail builder, operators and transport designers deal with design for accessibility......A report on how nine rail builder, operators and transport designers deal with design for accessibility...

22nd Workshop on Advances in Analog Circuit Design

CERN Document Server

Makinwa, Kofi; Harpe, Pieter

2014-01-01

This book is based on the 18 tutorials presented during the 22nd workshop on Advances in Analog Circuit Design.  Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including frequency reference, power management for systems-on-chip, and smart wireless interfaces.  This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.    ·         Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; ·         Presents material in a tutorial-based format; ·         Includes coverage of frequency reference, power management for systems-on-chip, and smart wireless interfaces.

PUZZLE - A program for computer-aided design of printed circuit artwork

Science.gov (United States)

Harrell, D. A. W.; Zane, R.

1971-01-01

Program assists in solving spacing problems encountered in printed circuit /PC/ design. It is intended to have maximum use for two-sided PC boards carrying integrated circuits, and also aids design of discrete component circuits.

Digital logic circuit design with ALTERA MAX+PLUS II

International Nuclear Information System (INIS)

Lee, Seung Ho; Park, Yong Su; Park, Gun Jong; Lee, Ju Heon

2006-09-01

This book is composed of five parts. The first part has introduction of ALTERA MAX+PLUS II and graphic editor, text editor, compiler, waveform editor simulator and timing analyzer of it. The second part is about direction of digital logic circuit design with training kit. The third part has grammar and practice of VHDL in ALTERA MAX+PLUS II including example and history of VHDL. The fourth part shows the design example of digital logic circuit by VHDL of ALTERA MAX+PLUS II which lists designs of adder and subtractor, code converter, counter, state machine and LCD module. The last part explains design example of digital logic circuit by graphic editor in ALTERA MAX+PLUS II.

Designing an Electro-Hydraulic Control Module for an Open-Circuit Variable Displacement Pump

DEFF Research Database (Denmark)

Pedersen, Henrik Clemmensen; Andersen, Torben Ole; Hansen, Michael Rygaard

2005-01-01

, in the form of an electric control signal, under varying working conditions, when having access to engine speed and actual pump pressure. The paper presents a model of both the pump and the control module, along with design considerations on which linear controllers are developed for a worst point......This paper deals with the problem of designing an electric control module for a Sauer-Danfoss Series 45 H-frame open circuit axial piston pump. The purpose of the electric control module is to replace the existing hydro-mechanical (LS) regulator, and enable the pump to follow a reference pressure...

Design of delay insensitive circuits using multi-ring structures

DEFF Research Database (Denmark)

Sparsø, Jens; Staunstrup, Jørgen; Dantzer-Sørensen, Michael

1992-01-01

The design and VLSI implementation of a delay insensitive circuit that computes the inner product of two vec·tors is described. The circuit is based on an iterative serial-parallel multiplication algorithm. The design is based on a data flow approach using pipelines and rings that are combined...

A Alternative Analog Circuit Design Methodology Employing Integrated Artificial Intelligence Techniques

Science.gov (United States)

Tuttle, Jeffery L.

In consideration of the computer processing power now available to the designer, an alternative analog circuit design methodology is proposed. Computer memory capacities no longer require the reduction of the transistor operational characteristics to an imprecise formulation. Therefore, it is proposed that transistor modelling be abandoned in favor of fully characterized transistor data libraries. Secondly, availability of the transistor libraries would facilitate an automated selection of the most appropriate device(s) for the circuit being designed. More specifically, a preprocessor computer program to a more sophisticated circuit simulator (e.g. SPICE) is developed to assist the designer in developing the basic circuit topology and the selection of the most appropriate transistor. Once this is achieved, the circuit topology and selected transistor data library would be downloaded to the simulator for full circuit operational characterization and subsequent design modifications. It is recognized that the design process is enhanced by the use of heuristics as applied to iterative design results. Accordingly, an artificial intelligence (AI) interface is developed to assist the designer in applying the preprocessor results. To demonstrate the retrofitability of the AI interface to established programs, the interface is specifically designed to be as non-intrusive to the host code as possible. Implementation of the proposed methodology offers the potential to speed the design process, since the preprocessor both minimizes the required number of simulator runs and provides a higher acceptance potential of the initial and subsequent simulator runs. Secondly, part count reductions may be realizable since the circuit topologies are not as strongly driven by transistor limitations. Thirdly, the predicted results should more closely match actual circuit operations since the inadequacies of the transistor models have been virtually eliminated. Finally, the AI interface

A design method of oscillatory De-Qing circuit

International Nuclear Information System (INIS)

Feng Wenquan

1988-01-01

With some particular advantages the oscillatory De-Qing circuit now is widely used. However its design is very complex. By means of a quantitative analysis for this circuit a group of design formulas is obtained. According to these design formulas the maximum allowable charging inductance L c , the De-Qing network resistance R and capacitance C can easily be determined, if the PFN capacitance C N , the maximum pulse frequency F max , and percentage regulation η are given. Simple and direct formulas for specific situation are listed. Finally, a design example is given and a comparison with experimental result is made, which shows that the design method is feasible and reliable

A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

Science.gov (United States)

Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

2010-01-01

This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

Power management techniques for integrated circuit design

CERN Document Server

Chen, Ke-Horng

2016-01-01

This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

Design automation for integrated nonlinear logic circuits (Conference Presentation)

Science.gov (United States)

Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

2016-05-01

A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

Digital integrated circuit design using Verilog and SystemVerilog

CERN Document Server

Mehler, Ronald W

2014-01-01

For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

Nucleic acids for the rational design of reaction circuits.

Science.gov (United States)

Padirac, Adrien; Fujii, Teruo; Rondelez, Yannick

2013-08-01

Nucleic acid-based circuits are rationally designed in vitro assemblies that can perform complex preencoded programs. They can be used to mimic in silico computations. Recent works emphasized the modularity and robustness of these circuits, which allow their scaling-up. Another new development has led to dynamic, time-responsive systems that can display emergent behaviors like oscillations. These are closely related to biological architectures and provide an in vitro model of in vivo information processing. Nucleic acid circuits have already been used to handle various processes for technological or biotechnological purposes. Future applications of these chemical smart systems will benefit from the rapidly growing ability to design, construct, and model nucleic acid circuits of increasing size. Copyright © 2012 Elsevier Ltd. All rights reserved.

Custom high-reliability radiation-hard CMOS-LSI circuit design

International Nuclear Information System (INIS)

Barnard, W.J.

1981-01-01

Sandia has developed a custom CMOS-LSI design capability to provide high reliability radiation-hardened circuits. This capability relies on (1) proven design practices to enhance reliability, (2) use of well characterized cells and logic modules, (3) computer-aided design tools to reduce design time and errors and to standardize design definition, and (4) close working relationships with the system designer and technology fabrication personnel. Trade-offs are made during the design between circuit complexity/performance and technology/producibility for high reliability and radiation-hardened designs to result. Sandia has developed and is maintaining a radiation-hardened bulk CMOS technology fabrication line for production of prototype and small production volume parts

An optimum design of R-C oscillatory De-Qing circuit

International Nuclear Information System (INIS)

Cao Dezhang; Pan Linghe; Yang Tianlu

1990-01-01

An optimum design of R-C oscillatory De-Qing circuit has been developed for voltage regulation of the pulse modulator. When a new coefficient T 3 /T is introduced, the selection of De-Qing circuit parameters will become quite simple and the optimum parameters can be calculated directly. The De-Qing circuit parameters calculated will be effective in the whole range of the percentage regulation η from zero to maximum design value. The limit value of η is 0.36 or 0.29, theoretically, when the time constant of the De-Qing circuit is 3RC or 5RC respectively

Design structure for in-system redundant array repair in integrated circuits

Science.gov (United States)

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Control circuits in power electronics practical issues in design and implementation

CERN Document Server

Castilla, Miguel

2016-01-01

Control circuits are a key element in the operation and performance of power electronics converters. This book describes practical issues related to the design and implementation of these control circuits, and is divided into three parts - analogue control circuits, digital control circuits, and new trends in control circuits.

Pulse Detecting Genetic Circuit – A New Design Approach

Science.gov (United States)

Inniss, Mara; Iba, Hitoshi; Way, Jeffrey C.

2016-01-01

A robust cellular counter could enable synthetic biologists to design complex circuits with diverse behaviors. The existing synthetic-biological counters, responsive to the beginning of the pulse, are sensitive to the pulse duration. Here we present a pulse detecting circuit that responds only at the falling edge of a pulse–analogous to negative edge triggered electric circuits. As biological events do not follow precise timing, use of such a pulse detector would enable the design of robust asynchronous counters which can count the completion of events. This transcription-based pulse detecting circuit depends on the interaction of two co-expressed lambdoid phage-derived proteins: the first is unstable and inhibits the regulatory activity of the second, stable protein. At the end of the pulse the unstable inhibitor protein disappears from the cell and the second protein triggers the recording of the event completion. Using stochastic simulation we showed that the proposed design can detect the completion of the pulse irrespective to the pulse duration. In our simulation we also showed that fusing the pulse detector with a phage lambda memory element we can construct a counter which can be extended to count larger numbers. The proposed design principle is a new control mechanism for synthetic biology which can be integrated in different circuits for identifying the completion of an event. PMID:27907045

Radio frequency integrated circuit design for cognitive radio systems

CERN Document Server

Fahim, Amr

2015-01-01

This book fills a disconnect in the literature between Cognitive Radio systems and a detailed account of the circuit implementation and architectures required to implement such systems.  Throughout the book, requirements and constraints imposed by cognitive radio systems are emphasized when discussing the circuit implementation details.  In addition, this book details several novel concepts that advance state-of-the-art cognitive radio systems.  This is a valuable reference for anybody with background in analog and radio frequency (RF) integrated circuit design, needing to learn more about integrated circuits requirements and implementation for cognitive radio systems. ·         Describes in detail cognitive radio systems, as well as the circuit implementation and architectures required to implement them; ·         Serves as an excellent reference to state-of-the-art wideband transceiver design; ·         Emphasizes practical requirements and constraints imposed by cognitive radi...

Parts & Pools: A Framework for Modular Design of Synthetic Gene Circuits

Energy Technology Data Exchange (ETDEWEB)

Marchisio, Mario Andrea, E-mail: marchisio@hit.edu.cn [School of Life Science and Technology, Harbin Institute of Technology, Harbin (China)

2014-10-06

Published in 2008, Parts & Pools represents one of the first attempts to conceptualize the modular design of bacterial synthetic gene circuits with Standard Biological Parts (DNA segments) and Pools of molecules referred to as common signal carriers (e.g., RNA polymerases and ribosomes). The original framework for modeling bacterial components and designing prokaryotic circuits evolved over the last years and brought, first, to the development of an algorithm for the automatic design of Boolean gene circuits. This is a remarkable achievement since gene digital circuits have a broad range of applications that goes from biosensors for health and environment care to computational devices. More recently, Parts & Pools was enabled to give a proper formal description of eukaryotic biological circuit components. This was possible by employing a rule-based modeling approach, a technique that permits a faithful calculation of all the species and reactions involved in complex systems such as eukaryotic cells and compartments. In this way, Parts & Pools is currently suitable for the visual and modular design of synthetic gene circuits in yeast and mammalian cells too.

Parts & Pools: A Framework for Modular Design of Synthetic Gene Circuits

International Nuclear Information System (INIS)

Marchisio, Mario Andrea

2014-01-01

Published in 2008, Parts & Pools represents one of the first attempts to conceptualize the modular design of bacterial synthetic gene circuits with Standard Biological Parts (DNA segments) and Pools of molecules referred to as common signal carriers (e.g., RNA polymerases and ribosomes). The original framework for modeling bacterial components and designing prokaryotic circuits evolved over the last years and brought, first, to the development of an algorithm for the automatic design of Boolean gene circuits. This is a remarkable achievement since gene digital circuits have a broad range of applications that goes from biosensors for health and environment care to computational devices. More recently, Parts & Pools was enabled to give a proper formal description of eukaryotic biological circuit components. This was possible by employing a rule-based modeling approach, a technique that permits a faithful calculation of all the species and reactions involved in complex systems such as eukaryotic cells and compartments. In this way, Parts & Pools is currently suitable for the visual and modular design of synthetic gene circuits in yeast and mammalian cells too.

CMOS analog integrated circuits high-speed and power-efficient design

CERN Document Server

Ndjountche, Tertulien

2011-01-01

High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

A Parallel Genetic Algorithm for Automated Electronic Circuit Design

Science.gov (United States)

Long, Jason D.; Colombano, Silvano P.; Haith, Gary L.; Stassinopoulos, Dimitris

2000-01-01

Parallelized versions of genetic algorithms (GAs) are popular primarily for three reasons: the GA is an inherently parallel algorithm, typical GA applications are very compute intensive, and powerful computing platforms, especially Beowulf-style computing clusters, are becoming more affordable and easier to implement. In addition, the low communication bandwidth required allows the use of inexpensive networking hardware such as standard office ethernet. In this paper we describe a parallel GA and its use in automated high-level circuit design. Genetic algorithms are a type of trial-and-error search technique that are guided by principles of Darwinian evolution. Just as the genetic material of two living organisms can intermix to produce offspring that are better adapted to their environment, GAs expose genetic material, frequently strings of 1s and Os, to the forces of artificial evolution: selection, mutation, recombination, etc. GAs start with a pool of randomly-generated candidate solutions which are then tested and scored with respect to their utility. Solutions are then bred by probabilistically selecting high quality parents and recombining their genetic representations to produce offspring solutions. Offspring are typically subjected to a small amount of random mutation. After a pool of offspring is produced, this process iterates until a satisfactory solution is found or an iteration limit is reached. Genetic algorithms have been applied to a wide variety of problems in many fields, including chemistry, biology, and many engineering disciplines. There are many styles of parallelism used in implementing parallel GAs. One such method is called the master-slave or processor farm approach. In this technique, slave nodes are used solely to compute fitness evaluations (the most time consuming part). The master processor collects fitness scores from the nodes and performs the genetic operators (selection, reproduction, variation, etc.). Because of dependency

Electrical impedance tomography system: an open access circuit design

Directory of Open Access Journals (Sweden)

Soleimani Manuchehr

2006-05-01

Full Text Available Abstract Background This paper reports a simple 2-D system for electrical impedance tomography EIT, which works efficiently and is low cost. The system has been developed in the Sharif University of Technology Tehran-Iran (for the author's MSc Project. Methods The EIT system consists of a PC in which an I/O card is installed with an external current generator, a multiplexer, a power supply and a phantom with an array of electrodes. The measurement system provides 12-bit accuracy and hence, suitable data acquisition software has been prepared accordingly. The synchronous phase detection method has been implemented for voltage measurement. Different methods of image reconstruction have been used with this instrument to generate electrical conductivity images. Results The results of simulation and real measurement of the system are presented. The reconstruction programs were written in MATLAB and the data acquisition software in C++. The system has been tested with both static and dynamic mode in a 2-D domain. Better results have been produced in the dynamic mode of operation, due to the cancellation of errors. Conclusion In the spirit of open access publication the design details of this simple EIT system are made available here.

CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

Energy Technology Data Exchange (ETDEWEB)

Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

2000-08-10

In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

Science.gov (United States)

Reagor, James A; Holt, David W

2016-03-01

Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

Analog Circuit Design Optimization Based on Evolutionary Algorithms

Directory of Open Access Journals (Sweden)

Mansour Barari

2014-01-01

Full Text Available This paper investigates an evolutionary-based designing system for automated sizing of analog integrated circuits (ICs. Two evolutionary algorithms, genetic algorithm and PSO (Parswal particle swarm optimization algorithm, are proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through specific electrical simulation, to the optimization system in the MATLAB environment, for the selected topology. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met. Comparisons with available methods like genetic algorithms show that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.

30 CFR 75.907 - Design of trailing cables for medium-voltage circuits.

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Design of trailing cables for medium-voltage... Medium-Voltage Alternating Current Circuits § 75.907 Design of trailing cables for medium-voltage circuits. [Statutory Provisions] Trailing cables for medium-voltage circuits shall include grounding...

Circuit Design of Surface Acoustic Wave Based Micro Force Sensor

Directory of Open Access Journals (Sweden)

Yuanyuan Li

2014-01-01

Full Text Available Pressure sensors are commonly used in industrial production and mechanical system. However, resistance strain, piezoresistive sensor, and ceramic capacitive pressure sensors possess limitations, especially in micro force measurement. A surface acoustic wave (SAW based micro force sensor is designed in this paper, which is based on the theories of wavelet transform, SAW detection, and pierce oscillator circuits. Using lithium niobate as the basal material, a mathematical model is established to analyze the frequency, and a peripheral circuit is designed to measure the micro force. The SAW based micro force sensor is tested to show the reasonable design of detection circuit and the stability of frequency and amplitude.

Electronic circuit design with HEP computational tools

International Nuclear Information System (INIS)

Vaz, Mario

1996-01-01

CPSPICE is an electronic circuit statistical simulation program developed to run in a parallel environment under UNIX operating system and TCP/IP communications protocol, using CPS - Cooperative Processes Software , SPICE program and CERNLIB software package. It is part of a set of tools being develop, intended to help electronic engineers to design, model and simulate complex systems and circuits for High Energy Physics detectors, based on statistical methods, using the same software and methodology used by HEP physicists for data analysis. CPSPICE simulates electronic circuits by Monte Carlo method, through several different processes running simultaneously SPICE in UNIX parallel computers or workstation farms. Data transfer between CPS processes for a modified version of SPICE2G6 is done by RAM memory, but can also be done through hard disk files if no source files are available for the simulator, and for bigger simulation outputs files. Simulation results are written in a HBOOK file as a NTUPLE, to be examined by HBOOK in batch model or graphics, and analyzed by statistical procedures available. The HBOOK file be stored on hard disk for small amount of data, or into Exabyte tape file for large amount of data. HEP tools also helps circuit or component modeling, like MINUT program from CERNLIB, that implements Nelder and Mead Simplex and Gradient with or without derivatives algorithms, and can be used for design optimization.This paper presents CPSPICE program implementation. The scheme adopted is suitable to make parallel other electronic circuit simulators. (author)

Evolvable designs of experiments applications for circuits

CERN Document Server

Iordache, Octavian

2009-01-01

Adopting a groundbreaking approach, the highly regarded author shows how to design methods for planning increasingly complex experiments. He begins with a brief introduction to standard quality methods and the technology in standard electric circuits. The book then gives numerous examples of how to apply the proposed methodology in a series of real-life case studies. Although these case studies are taken from the printed circuit board industry, the methods are equally applicable to other fields of engineering.

High-frequency analog integrated circuit design

CERN Document Server

1995-01-01

To learn more about designing analog integrated circuits (ICs) at microwave frequencies using GaAs materials, turn to this text and reference. It addresses GaAs MESFET-based IC processing. Describes the newfound ability to apply silicon analog design techniques to reliable GaAs materials and devices which, until now, was only available through technical papers scattered throughout hundred of articles in dozens of professional journals.

Practical guide to organic field effect transistor circuit design

CERN Document Server

Sou, Antony

2016-01-01

The field of organic electronics spans a very wide range of disciplines from physics and chemistry to hardware and software engineering. This makes the field of organic circuit design a daunting prospect full of intimidating complexities, yet to be exploited to its true potential. Small focussed research groups also find it difficult to move beyond their usual boundaries and create systems-on-foil that are comparable with the established silicon world.This book has been written to address these issues, intended for two main audiences; firstly, physics or materials researchers who have thus far designed circuits using only basic drawing software; and secondly, experienced silicon CMOS VLSI design engineers who are already knowledgeable in the design of full custom transistor level circuits but are not familiar with organic devices or thin film transistor (TFT) devices.In guiding the reader through the disparate and broad subject matters, a concise text has been written covering the physics and chemistry of the...

Servo Platform Circuit Design of Pendulous Gyroscope Based on DSP

Science.gov (United States)

Tan, Lilong; Wang, Pengcheng; Zhong, Qiyuan; Zhang, Cui; Liu, Yunfei

2018-03-01

In order to solve the problem when a certain type of pendulous gyroscope in the initial installation deviation more than 40 degrees, that the servo platform can not be up to the speed of the gyroscope in the rough north seeking phase. This paper takes the digital signal processor TMS320F28027 as the core, uses incremental digital PID algorithm, carries out the circuit design of the servo platform. Firstly, the hardware circuit is divided into three parts: DSP minimum system, motor driving circuit and signal processing circuit, then the mathematical model of incremental digital PID algorithm is established, based on the model, writes the PID control program in CCS3.3, finally, the servo motor tracking control experiment is carried out, it shows that the design can significantly improve the tracking ability of the servo platform, and the design has good engineering practice.

[Design of blood-pressure parameter auto-acquisition circuit].

Science.gov (United States)

Chen, Y P; Zhang, D L; Bai, H W; Zhang, D A

2000-02-01

This paper presents the realization and design of a kind of blood-pressure parameter auto-acquisition circuit. The auto-acquisition of blood-pressure parameter controlled by 89C2051 single chip microcomputer is accomplished by collecting and processing the driving signal of LCD. The circuit that is successfully applied in the home unit of telemedicine system has the simple and reliable properties.

Design of An Energy Efficient Hydraulic Regenerative circuit

Science.gov (United States)

Ramesh, S.; Ashok, S. Denis; Nagaraj, Shanmukha; Adithyakumar, C. R.; Reddy, M. Lohith Kumar; Naulakha, Niranjan Kumar

2018-02-01

Increasing cost and power demand, leads to evaluation of new method to increase through productivity and help to solve the power demands. Many researchers have break through to increase the efficiency of a hydraulic power pack, one of the promising methods is the concept of regenerative. The objective of this research work is to increase the efficiency of a hydraulic circuit by introducing a concept of regenerative circuit. A Regenerative circuit is a system that is used to speed up the extension stroke of the double acting single rod hydraulic cylinder. The output is connected to the input in the directional control value. By this concept, increase in velocity of the piston and decrease the cycle time. For the research, a basic hydraulic circuit and a regenerative circuit are designated and compared both with their results. The analysis was based on their time taken for extension and retraction of the piston. From the detailed analysis of both the hydraulic circuits, it is found that the efficiency by introducing hydraulic regenerative circuit increased by is 5.3%. The obtained results conclude that, implementing hydraulic regenerative circuit in a hydraulic power pack decreases power consumption, reduces cycle time and increases productivity in a longer run.

Analog circuit design automation for performance

NARCIS (Netherlands)

Ning, Zhen-Qiu; Ning, Zhen-Qiu; Kole, Marq; Kole, M.E.; Mouthaan, A.J.; Wallinga, Hans

1992-01-01

This paper describes an improved version of the program SEAS (a Simulated Evolution approach for Analog circuit Synthesis), in which an approach for selection of alternatives based on the evaluation of mutation values is developed, and design automafion for high performance comparators is covered.

Electromagnetic Compatibility Design of the Computer Circuits

Science.gov (United States)

Zitai, Hong

2018-02-01

Computers and the Internet have gradually penetrated into every aspect of people’s daily work. But with the improvement of electronic equipment as well as electrical system, the electromagnetic environment becomes much more complex. Electromagnetic interference has become an important factor to hinder the normal operation of electronic equipment. In order to analyse the computer circuit compatible with the electromagnetic compatibility, this paper starts from the computer electromagnetic and the conception of electromagnetic compatibility. And then, through the analysis of the main circuit and system of computer electromagnetic compatibility problems, we can design the computer circuits in term of electromagnetic compatibility. Finally, the basic contents and methods of EMC test are expounded in order to ensure the electromagnetic compatibility of equipment.

Design of pressure-driven microfluidic networks using electric circuit analogy.

Science.gov (United States)

Oh, Kwang W; Lee, Kangsun; Ahn, Byungwook; Furlani, Edward P

2012-02-07

This article reviews the application of electric circuit methods for the analysis of pressure-driven microfluidic networks with an emphasis on concentration- and flow-dependent systems. The application of circuit methods to microfluidics is based on the analogous behaviour of hydraulic and electric circuits with correlations of pressure to voltage, volumetric flow rate to current, and hydraulic to electric resistance. Circuit analysis enables rapid predictions of pressure-driven laminar flow in microchannels and is very useful for designing complex microfluidic networks in advance of fabrication. This article provides a comprehensive overview of the physics of pressure-driven laminar flow, the formal analogy between electric and hydraulic circuits, applications of circuit theory to microfluidic network-based devices, recent development and applications of concentration- and flow-dependent microfluidic networks, and promising future applications. The lab-on-a-chip (LOC) and microfluidics community will gain insightful ideas and practical design strategies for developing unique microfluidic network-based devices to address a broad range of biological, chemical, pharmaceutical, and other scientific and technical challenges.

Design of organic complementary circuits and systems on foil

CERN Document Server

Abdinia, Sahel; Cantatore, Eugenio

2015-01-01

This book describes new approaches to fabricate complementary organic electronics, and focuses on the design of circuits and practical systems created using these manufacturing approaches. The authors describe two state-of-the-art, complementary organic technologies, characteristics and modeling of their transistors and their capability to implement circuits and systems on foil. Readers will benefit from the valuable overview of the challenges and opportunities that these extremely innovative technologies provide. ·         Demonstrates first circuits implemented using specific complementary organic technologies, including first printed analog to digital converter, first dynamic logic on foil and largest complementary organic circuit ·         Includes step-by-step design from single transistor level to complete systems on foil ·         Provides a platform for comparing state-of-the-art complementary organic technologies and for comparing these with other similar technologies, spec...

Electrostatic Discharge Current Linear Approach and Circuit Design Method

Directory of Open Access Journals (Sweden)

Pavlos K. Katsivelis

2010-11-01

Full Text Available The Electrostatic Discharge phenomenon is a great threat to all electronic devices and ICs. An electric charge passing rapidly from a charged body to another can seriously harm the last one. However, there is a lack in a linear mathematical approach which will make it possible to design a circuit capable of producing such a sophisticated current waveform. The commonly accepted Electrostatic Discharge current waveform is the one set by the IEC 61000-4-2. However, the over-simplified circuit included in the same standard is incapable of producing such a waveform. Treating the Electrostatic Discharge current waveform of the IEC 61000-4-2 as reference, an approximation method, based on Prony’s method, is developed and applied in order to obtain a linear system’s response. Considering a known input, a method to design a circuit, able to generate this ESD current waveform in presented. The circuit synthesis assumes ideal active elements. A simulation is carried out using the PSpice software.

Design of remote laser-induced fluorescence system's acquisition circuit

Science.gov (United States)

Wang, Guoqing; Lou, Yue; Wang, Ran; Yan, Debao; Li, Xin; Zhao, Xin; Chen, Dong; Zhao, Qi

2017-10-01

Laser-induced fluorescence system(LIfS) has been found its significant application in identifying one kind of substance from another by its properties even it's thimbleful, and becomes useful in plenty of fields. Many superior works have reported LIfS' theoretical analysis , designs and uses. However, the usual LIPS is always constructed in labs to detect matter quite closely, for the system using low-power laser as excitation source and charge coupled device (CCD) as detector. Promoting the detectivity of LIfS is of much concern to spread its application. Here, we take a high-energy narrow-pulse laser instead of commonly used continuous wave laser to operate sample, thus we can get strong fluorescent. Besides, photomultiplier (PMT) with high sensitivity is adopted in our system to detect extremely weak fluorescence after a long flight time from the sample to the detector. Another advantage in our system, as the fluorescence collected into spectroscopy, multiple wavelengths of light can be converted to the corresponding electrical signals with the linear array multichannel PMT. Therefore, at the cost of high-powered incentive and high-sensitive detector, a remote LIFS is get. In order to run this system, it is of importance to turn light signal to digital signal which can be processed by computer. The pulse width of fluorescence is deeply associated with excitation laser, at the nanosecond(ns) level, which has a high demand for acquisition circuit. We design an acquisition circuit including, I/V conversion circuit, amplifying circuit and peak-holding circuit. The simulation of circuit shows that peak-holding circuit can be one effective approach to reducing difficulty of acquisition circuit.

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Directory of Open Access Journals (Sweden)

Ramesh Vaddi

2009-01-01

Full Text Available In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

Reactivating Neural Circuits with Clinically Accessible Stimulation to Restore Hand Function in Persons with Tetraplegia

Science.gov (United States)

2017-09-01

AWARD NUMBER: W81XWH-16-1-0395 TITLE: Reactivating Neural Circuits with Clinically Accessible Stimulation to Restore Hand Function in...estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data...Clinically Accessible Stimulation to Restore Hand Function in Persons with Tetraplegia 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S

Device reliability challenges for modern semiconductor circuit design – a review

Directory of Open Access Journals (Sweden)

C. Schlünder

2009-05-01

Full Text Available Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1. Degradation mechanisms like Negative Bias Temperature Instability (NBTI or Hot Carrier Injection (HCI lead to parameter drifts during operation adding on top of the process variations.

The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs.

An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.

Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations

Directory of Open Access Journals (Sweden)

Marco Lanuzza

2011-04-01

Full Text Available Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits. Five well known adder circuits were designed exploiting an industrial 45 nm static complementary metal-oxide semiconductor (CMOS standard cell library. The designed adders were comparatively evaluated under different energy constraints. As a main result, the performed analysis demonstrates that, for a given energy budget, simpler circuits (which are conventionally identified as low-energy slow architectures operating at higher power supply voltages can achieve a timing yield significantly better than more complex faster adders when used in low-power design with supply voltages lower than nominal.

Design, Fabrication and Integration of a NaK-Cooled Circuit

International Nuclear Information System (INIS)

Garber, Anne; Godfroy, Thomas

2006-01-01

The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed for use with a eutectic mixture of sodium potassium (NaK), was redesigned for use with lithium. Due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature circuit include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This paper summarizes the integration and preparations for the fill of the pumped NaK circuit. (authors)

High performance integer arithmetic circuit design on FPGA architecture, implementation and design automation

CERN Document Server

Palchaudhuri, Ayan

2016-01-01

This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from us...

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

Science.gov (United States)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Ultra low-power integrated circuit design for wireless neural interfaces

CERN Document Server

Holleman, Jeremy; Otis, Brian

2014-01-01

Presenting results from real prototype systems, this volume provides an overview of ultra low-power integrated circuits and systems for neural signal processing and wireless communication. Topics include analog, radio, and signal processing theory and design for ultra low-power circuits.

Optimal Design of Rectification Circuit in Electronic Circuit Fault Self-repair Based on EHW and RBT

Institute of Scientific and Technical Information of China (English)

ZHANG Junbin; CAI Jinyan; MENG Yafeng

2018-01-01

Reliability of traditional electronic circuit is improved mainly by redundant fault-tolerant technol-ogy with large hardware resource consumption and limited fault self-repair capability. In complicated environment, electronic circuit faults appear easily. If on-site immedi-ate repair is not implemented, normal running of elec-tronic system will be directly affected. In order to solve these problems, Evolvable hardware (EHW) technology is widely used. The conventional EHW has some bottlenecks. The optimal design of Rectification circuit (RTC) is fur-ther researched on the basis of the previously proposed fault self-repair based on EHW and Reparation balance technology (RBT). Fault sets are selected by fault danger degree and fault coverage rate. The optimal designed RTC can completely repair faults in the fault set. Simulation re-sults prove that it has higher self-repair capability and less hardware resource.

Designable DNA-binding domains enable construction of logic circuits in mammalian cells.

Science.gov (United States)

Gaber, Rok; Lebar, Tina; Majerle, Andreja; Šter, Branko; Dobnikar, Andrej; Benčina, Mojca; Jerala, Roman

2014-03-01

Electronic computer circuits consisting of a large number of connected logic gates of the same type, such as NOR, can be easily fabricated and can implement any logic function. In contrast, designed genetic circuits must employ orthogonal information mediators owing to free diffusion within the cell. Combinatorial diversity and orthogonality can be provided by designable DNA- binding domains. Here, we employed the transcription activator-like repressors to optimize the construction of orthogonal functionally complete NOR gates to construct logic circuits. We used transient transfection to implement all 16 two-input logic functions from combinations of the same type of NOR gates within mammalian cells. Additionally, we present a genetic logic circuit where one input is used to select between an AND and OR function to process the data input using the same circuit. This demonstrates the potential of designable modular transcription factors for the construction of complex biological information-processing devices.

Nyquist AD Converters, Sensor Interfaces, and Robustness Advances in Analog Circuit Design, 2012

CERN Document Server

Baschirotto, Andrea; Steyaert, Michiel

2013-01-01

This book is based on the presentations during the 21st workshop on Advances in Analog Circuit Design.  Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity.  This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.  Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; Presents material in a tutorial-based format; Includes coverage of Nyquist A/D converters, capacitive sensor interfaces, reliability, variability, and connectivity.

Design of synthetic biological logic circuits based on evolutionary algorithm.

Science.gov (United States)

Chuang, Chia-Hua; Lin, Chun-Liang; Chang, Yen-Chang; Jennawasin, Tanagorn; Chen, Po-Kuei

2013-08-01

The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real-structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis-regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer-based modelling technology has been verified showing its great advantages in the purpose.

Design of Microcantilever-Based Biosensor with Digital Feedback Control Circuit

Directory of Open Access Journals (Sweden)

Jayu P. Kalambe

2012-01-01

Full Text Available This paper present the design of cantilever-based biosensors with new readout, which hold promises as fast and cheap “point of care” device as well as interesting research tools. The fabrication process and related issues of the cantilever based bio-sensor are discussed. Coventorware simulation is carried out to analyze the device behavior. A fully integrated control circuit has been designed to solve manufacturing challenge which will take care of positioning of the cantilever instead of creating nanometer gap between the electrodes. The control circuit will solve the manufacturing challenge faced by the readout methods where it is essential to maintain precise gap between the electrodes. The circuit can take care of variation obtained due to fabrication process and maintain the precise gap between the electrodes by electrostatic actuation. The control circuit consist of analog and digital modules. The reliability issues of the sensor are also discussed.

Wireless and photonic high-speed communication technologies, circuits and design tools

DEFF Research Database (Denmark)

Krozer, Viktor; Johansen, Tom Keinicke; Jiang, Chenhui

2009-01-01

were reported. These communication systems present new challenges for circuit designers. The presentation will be devoted to technologies and various aspects of circuit design for 100 G applications. We will present overview on wired and wireless systems demonstrating the challenges of this research...... including design challenges, relevant trade-offs and the present bottlenecks. Different system architectures will be presented with their impact on component requirements. Similarities and differences of wired and wireless applications will be pointed out. Design methodologies, necessary tools and circuit...... are fundamental to emerging consumer and professional applications. These systems start to emerge as near future applications and are subject of ongoing research activities in Europe, for example within the EU FP6 GIBON project. Wireless systems with over 100 GHz carriers as well as first over 100-G fibre systems...

Design and implementation of JOM-3 Overhauser magnetometer analog circuit

Science.gov (United States)

Zhang, Xiao; Jiang, Xue; Zhao, Jianchang; Zhang, Shuang; Guo, Xin; Zhou, Tingting

2017-09-01

Overhauser magnetometer, a kind of static-magnetic measurement system based on the Overhauser effect, has been widely used in archaeological exploration, mineral resources exploration, oil and gas basin structure detection, prediction of engineering exploration environment, earthquakes and volcanic eruotions, object magnetic measurement and underground buried booty exploration. Overhauser magnetometer plays an important role in the application of magnetic field measurement for its characteristics of small size, low power consumption and high sensitivity. This paper researches the design and the application of the analog circuit of JOM-3 Overhauser magnetometer. First, the Larmor signal output by the probe is very weak. In order to obtain the signal with high signal to noise rstio(SNR), the design of pre-amplifier circuit is the key to improve the quality of the system signal. Second, in this paper, the effectual step which could improve the frequency characters of bandpass filter amplifier circuit were put forward, and theoretical analysis was made for it. Third, the shaping circuit shapes the amplified sine signal into a square wave signal which is suitable for detecting the rising edge. Fourth, this design elaborated the optimized choice of tuning circuit, so the measurement range of the magnetic field can be covered. Last, integrated analog circuit testing system was formed to detect waveform of each module. By calculating the standard deviation, the sensitivity of the improved Overhauser magnetometer is 0.047nT for Earth's magnetic field observation. Experimental results show that the new magnetometer is sensitive to earth field measurement.

Applications of modularized circuit designs in a new hyper-chaotic system circuit implementation

Science.gov (United States)

Wang, Rui; Sun, Hui; Wang, Jie-Zhi; Wang, Lu; Wang, Yan-Chao

2015-02-01

Modularized circuit designs for chaotic systems are introduced in this paper. Especially, a typical improved modularized design strategy is proposed and applied to a new hyper-chaotic system circuit implementation. In this paper, the detailed design procedures are described. Multisim simulations and physical experiments are conducted, and the simulation results are compared with Matlab simulation results for different system parameter pairs. These results are consistent with each other and they verify the existence of the hyper-chaotic attractor for this new hyper-chaotic system. Project supported by the Young Scientists Fund of the National Natural Science Foundation of China (Grant No. 61403395), the Natural Science Foundation of Tianjin, China (Grant No. 13JCYBJC39000), the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry of China, the Fund from the Tianjin Key Laboratory of Civil Aircraft Airworthiness and Maintenance in Civil Aviation of China (Grant No. 104003020106), the National Basic Research Program of China (Grant No. 2014CB744904), and the Fund for the Scholars of Civil Aviation University of China (Grant No. 2012QD21x).

Principles of transistor circuits introduction to the design of amplifiers, receivers and digital circuits

CERN Document Server

Amos, S W

2013-01-01

For over thirty years, Stan Amos has provided students and practitioners with a text they could rely on to keep them at the forefront of transistor circuit design. This seminal work has now been presented in a clear new format and completely updated to include the latest equipment such as laser diodes, Trapatt diodes, optocouplers and GaAs transistors, and the most recent line output stages and switch-mode power supplies.Although integrated circuits have widespread application, the role of discrete transistors is undiminished, both as important building blocks which students must understand an

Design of The High Efficiency Power Factor Correction Circuit for Power Supply

Directory of Open Access Journals (Sweden)

Atiye Hülya OBDAN

2017-12-01

Full Text Available Designing power factor correction circuits for switched power supplies has become important in recent years in terms of efficient use of energy. Power factor correction techniques play a significant role in high power density and energy efficiency. For these purposes, bridgeless PFC topologies and control strategies have been developed alongside basic boost PFC circuits. The power density can be increased using bridgeless structures by means of reducing losses in the circuit. This article examines bridgeless PFC structures and compares their performances in terms of losses and power factor. A semi-bridgeless PFC, which is widely used at high power levels, was analyzed and simulated. The designed circuit simulation using the current mode control method was performed in the PSIM program. A prototype of a 900 W semi-bridgeless PFC circuit was implemented and the results obtained from the circuit are presented

Digitally-assisted analog and RF CMOS circuit design for software-defined radio

CERN Document Server

Okada, Kenichi

2011-01-01

This book describes the state-of-the-art in RF, analog, and mixed-signal circuit design for Software Defined Radio (SDR). It synthesizes for analog/RF circuit designers the most important general design approaches to take advantage of the most recent CMOS technology, which can integrate millions of transistors, as well as several real examples from the most recent research results.

High-frequency and microwave circuit design

CERN Document Server

Nelson, Charles

2007-01-01

An integral part of any communications system, high-frequency and microwave design stimulates major progress in the wireless world and continues to serve as a foundation for the commercial wireless products we use every day. The exceptional pace of advancement in developing these systems stipulates that engineers be well versed in multiple areas of electronics engineering. With more illustrations, examples, and worked problems, High-Frequency and Microwave Circuit Design, Second Edition provides engineers with a diverse body of knowledge they can use to meet the needs of this rapidly progressi

Design of an improved RCD buffer circuit for full bridge circuit

Science.gov (United States)

Yang, Wenyan; Wei, Xueye; Du, Yongbo; Hu, Liang; Zhang, Liwei; Zhang, Ou

2017-05-01

In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubber circuit with the improved RCD snubber circuit. By comparing and analyzing, it is proved that the improved buffer circuit can absorb surge voltage. Finally, experiments are demonstrated to validate that the correctness of the RC formula and the improved RCD snubber circuit.

Exploration and design of smart home circuit based on ZigBee

Science.gov (United States)

Luo, Huirong

2018-05-01

To apply ZigBee technique in smart home circuit design, in the hardware design link of ZigBee node, TI Company's ZigBee wireless communication chip CC2530 was used to complete the design of ZigBee RF module circuit and peripheral circuit. In addition, the function demand and the overall scheme of the intelligent system based on smart home furnishing were proposed. Finally, the smart home system was built by combining ZigBee network and intelligent gateway. The function realization, reliability and power consumption of ZigBee network were tested. The results showed that ZigBee technology was applied to smart home system, making it have some advantages in terms of flexibility, scalability, power consumption and indoor aesthetics. To sum up, the system has high application value.

Designing charge-sensitive preamplifiers based on low-noise analog integrated circuits

International Nuclear Information System (INIS)

Agakhanyan, T.M.

1998-01-01

The methodology for designing charge-sensitive preamplifiers on the low-noise analog integral circuits, including all the stages: the mathematical synthesis with optimization of the intermediate function; the scheme-technical synthesis with parametric optimization of the scheme and analysis of draft projects with the parameter verification is presented. The designing is conducted on the basis of requirements for signal parameters and noise indices of the preamplifier. The system of automated designing of the charge-sensitive preamplifiers on the low-noise analog integral circuits is developed [ru

Design and experimental results of coaxial circuits for gyroklystron amplifiers

International Nuclear Information System (INIS)

Flaherty, M.K.E.; Lawson, W.; Cheng, J.; Calame, J.P.; Hogan, B.; Latham, P.E.; Granatstein, V.L.

1994-01-01

At the University of Maryland high power microwave source development for use in linear accelerator applications continues with the design and testing of coaxial circuits for gyroklystron amplifiers. This presentation will include experimental results from a coaxial gyroklystron that was tested on the current microwave test bed, and designs for second harmonic coaxial circuits for use in the next generation of the gyroklystron program. The authors present test results for a second harmonic coaxial circuit. Similar to previous second harmonic experiments the input cavity resonated at 9.886 GHz and the output frequency was 19.772 GHz. The coaxial insert was positioned in the input cavity and drift region. The inner conductor consisted of a tungsten rod with copper and ceramic cylinders covering its length. Two tungsten rods that bridged the space between the inner and outer conductors supported the whole assembly. The tube produced over 20 MW of output power with 17% efficiency. Beam interception by the tungsten rods resulted in minor damage. Comparisons with previous non-coaxial circuits showed that the coaxial configuration increased the parameter space over which stable operation was possible. Future experiments will feature an upgraded modulator and beam formation system capable of producing 300 MW of beam power. The fundamental frequency of operation is 8.568 GHz. A second harmonic coaxial gyroklystron circuit was designed for use in the new system. A scattering matrix code predicts a resonant frequency of 17.136 GHz and Q of 260 for the cavity with 95% of the outgoing microwaves in the desired TE032 mode. Efficiency studies of this second harmonic output cavity show 20% expected efficiency. Shorter second harmonic output cavity designs are also being investigated with expected efficiencies near 34%

Designing reversible arithmetic, logic circuit to implement micro-operation in quantum computation

International Nuclear Information System (INIS)

Kalita, Gunajit; Saikia, Navajit

2016-01-01

The futuristic computing is desired to be more power full with low-power consumption. That is why quantum computing has been a key area of research for quite some time and is getting more and more attention. Quantum logic being reversible, a significant amount of contributions has been reported on reversible logic in recent times. Reversible circuits are essential parts of quantum computers, and hence their designs are of great importance. In this paper, designs of reversible circuits are proposed using a recently proposed reversible gate for arithmetic and logic operations to implement various micro-operations (simple add and subtract, add with carry, subtract with borrow, transfer, incrementing, decrementing etc., and logic operations like XOR, XNOR, complementing etc.) in a reversible computer like quantum computer. The two new reversible designs proposed here for half adder and full adders are also used in the presented reversible circuits to implement various microoperations. The quantum costs of these designs are comparable. Many of the implemented micro-operations are not seen in previous literatures. The performances of the proposed circuits are compared with existing designs wherever available. (paper)

Integrated Circuit Design of 3 Electrode Sensing System Using Two-Stage Operational Amplifier

Science.gov (United States)

Rani, S.; Abdullah, W. F. H.; Zain, Z. M.; N, Aqmar N. Z.

2018-03-01

This paper presents the design of a two-stage operational amplifier(op amp) for 3-electrode sensing system readout circuits. The designs have been simulated using 0.13μm CMOS technology from Silterra (Malaysia) with Mentor graphics tools. The purpose of this projects is mainly to design a miniature interfacing circuit to detect the redox reaction in the form of current using standard analog modules. The potentiostat consists of several op amps combined together in order to analyse the signal coming from the 3-electrode sensing system. This op amp design will be used in potentiostat circuit device and to analyse the functionality for each module of the system.

Designing Robustness to Temperature in a Feedforward Loop Circuit

OpenAIRE

Sen, Shaunak; Kim, Jongmin; Murray, Richard M.

2013-01-01

Incoherent feedforward loops represent important biomolecular circuit elements capable of a rich set of dynamic behavior including adaptation and pulsed responses. Temperature can modulate some of these properties through its effect on the underlying reaction rate parameters. It is generally unclear how to design such a circuit where the properties are robust to variations in temperature. Here, we address this issue using a combination of tools from control and dynamical systems theory as wel...

Design and Radiation Assessment of Optoelectronic Transceiver Circuits for ITER

CERN Document Server

Leroux, P; Van Uffelen, M; Steyaert, M

2008-01-01

The presented work describes the design and characterization results of different electronic building blocks for a MGy gamma radiation tolerant optoelectronic transceiver aiming at ITER applications. The circuits are implemented using the 70GHz fT SiGe HBT in a 0.35μm BiCMOS technology. A VCSEL driver circuit has been designed and measured up to a TID of 1.6 MGy and up to a bit rate of 622Mbps. No significant degradation is seen in the eye opening of the output signal. On the receiver side, both a 1GHz, 3kΩ transimpedance and a 5GHz Cherry-Hooper amplifier with over 20dB voltage gain have been designed.

Design and implementation of a hybrid circuit system for micro sensor signal processing

International Nuclear Information System (INIS)

Wang Zhuping; Chen Jing; Liu Ruqing

2011-01-01

This paper covers a micro sensor analog signal processing circuit system (MASPS) chip with low power and a digital signal processing circuit board implementation including hardware connection and software design. Attention has been paid to incorporate the MASPS chip into the digital circuit board. The ultimate aim is to form a hybrid circuit used for mixed-signal processing, which can be applied to a micro sensor flow monitoring system. (semiconductor integrated circuits)

Automatic Design of Synthetic Gene Circuits through Mixed Integer Non-linear Programming

Science.gov (United States)

Huynh, Linh; Kececioglu, John; Köppe, Matthias; Tagkopoulos, Ilias

2012-01-01

Automatic design of synthetic gene circuits poses a significant challenge to synthetic biology, primarily due to the complexity of biological systems, and the lack of rigorous optimization methods that can cope with the combinatorial explosion as the number of biological parts increases. Current optimization methods for synthetic gene design rely on heuristic algorithms that are usually not deterministic, deliver sub-optimal solutions, and provide no guaranties on convergence or error bounds. Here, we introduce an optimization framework for the problem of part selection in synthetic gene circuits that is based on mixed integer non-linear programming (MINLP), which is a deterministic method that finds the globally optimal solution and guarantees convergence in finite time. Given a synthetic gene circuit, a library of characterized parts, and user-defined constraints, our method can find the optimal selection of parts that satisfy the constraints and best approximates the objective function given by the user. We evaluated the proposed method in the design of three synthetic circuits (a toggle switch, a transcriptional cascade, and a band detector), with both experimentally constructed and synthetic promoter libraries. Scalability and robustness analysis shows that the proposed framework scales well with the library size and the solution space. The work described here is a step towards a unifying, realistic framework for the automated design of biological circuits. PMID:22536398

Trends in integrated circuit design for particle physics experiments

International Nuclear Information System (INIS)

Atkin, E V

2017-01-01

Integrated circuits are one of the key complex units available to designers of multichannel detector setups. A whole number of factors makes Application Specific Integrated Circuits (ASICs) valuable for Particle Physics and Astrophysics experiments. Among them the most important ones are: integration scale, low power dissipation, radiation tolerance. In order to make possible future experiments in the intensity, cosmic, and energy frontiers today ASICs should provide new level of functionality at a new set of constraints and trade-offs, like low-noise high-dynamic range amplification and pulse shaping, high-speed waveform sampling, low power digitization, fast digital data processing, serialization and data transmission. All integrated circuits, necessary for physical instrumentation, should be radiation tolerant at an earlier not reached level (hundreds of Mrad) of total ionizing dose and allow minute almost 3D assemblies. The paper is based on literary source analysis and presents an overview of the state of the art and trends in nowadays chip design, using partially own ASIC lab experience. That shows a next stage of ising micro- and nanoelectronics in physical instrumentation. (paper)

Integrated Circuit Design in US High-Energy Physics

Energy Technology Data Exchange (ETDEWEB)

Geronimo, G. D. [Brookhaven National Lab. (BNL), Upton, NY (United States); Christian, D. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Bebek, C. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Garcia-Sciveres, M. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Lippe, H. V. D. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Haller, G. [SLAC National Accelerator Lab., Menlo Park, CA (United States); Grillo, AA [Univ. of California, Santa Cruz, CA (United States); Newcomer, M [Univ. of Pennsylvania, Philadelphia, PA (United States)

2013-07-10

This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies; Outlook of future technologies including 2.5D and 3D; Survey of ICs used in current experiments and ICs targeted for approved or proposed experiments; IC design at US institutes and recommendations for collaboration in the future.

Oscillator circuits

CERN Document Server

Graf, Rudolf F

1996-01-01

This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing

Measuring circuits

CERN Document Server

Graf, Rudolf F

1996-01-01

This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings

Visual accessibility in graphic design: A client–designer communication failure

OpenAIRE

Cornish, Katie; Goodman-Deane, Joy; Ruggeri, Kai; Clarkson, P. John

2015-01-01

It is essential that graphic design is visually clear and accessible. However, evidence suggests that a lack of consideration is given to visual accessibility in print-based graphic design. Furthermore, effective client-designer communication is a vital component in this. This paper investigates current graphic design practice, with regard to visual accessibility, specifically focussing on client-designer communication. A survey of 122 graphic designers and clients identified that these two g...

The Signal Detection and Control Circuit Design for Confocal Auto-Focus System

OpenAIRE

Yin Liu; Jin Yu; Zeqiang Mo

2016-01-01

Based on the demands of Confocal Auto-Focus system, the implementation method of signal measurement circuit and control circuit is given. Using the high performance instrumental amplifier AD620BN, low noise precision FET Op amplifier AD795JRZ and ultralow offset voltage Op amplifier OP07EP, a signal measurement circuit used to converse the two differential light intensity signal to electric signal is designed. And a control circuit which takes MCU MSP430F149 as core processes the former signa...

Advanced Breakdown Modeling for Solid-State Circuit Design

NARCIS (Netherlands)

Milovanovi?, V.

2010-01-01

Modeling of the effects occurring outside the usual region of application of semiconductor devices is becoming more important with increasing demands set upon electronic systems for simultaneous speed and output power. Analog integrated circuit designers are forced to enter regimes of transistor

Design of ternary clocked adiabatic static random access memory

Science.gov (United States)

Pengjun, Wang; Fengna, Mei

2011-10-01

Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions.

Adder design using a 5-input majority gate in a novel “multilayer gate design paradigm” for quantum dot cellular automata circuits

International Nuclear Information System (INIS)

Kumar, Rohit; Ghosh, Bahniman; Gupta, Shoubhik

2015-01-01

This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input–output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact. (paper)

Optimal design of RTCs in digital circuit fault self-repair based on global signal optimization

Institute of Scientific and Technical Information of China (English)

Zhang Junbin; Cai Jinyan; Meng Yafeng

2016-01-01

Since digital circuits have been widely and thoroughly applied in various fields, electronic systems are increasingly more complicated and require greater reliability. Faults may occur in elec-tronic systems in complicated environments. If immediate field repairs are not made on the faults, elec-tronic systems will not run normally, and this will lead to serious losses. The traditional method for improving system reliability based on redundant fault-tolerant technique has been unable to meet the requirements. Therefore, on the basis of (evolvable hardware)-based and (reparation balance technology)-based electronic circuit fault self-repair strategy proposed in our preliminary work, the optimal design of rectification circuits (RTCs) in electronic circuit fault self-repair based on global sig-nal optimization is deeply researched in this paper. First of all, the basic theory of RTC optimal design based on global signal optimization is proposed. Secondly, relevant considerations and suitable ranges are analyzed. Then, the basic flow of RTC optimal design is researched. Eventually, a typical circuit is selected for simulation verification, and detailed simulated analysis is made on five circumstances that occur during RTC evolution. The simulation results prove that compared with the conventional design method based RTC, the global signal optimization design method based RTC is lower in hardware cost, faster in circuit evolution, higher in convergent precision, and higher in circuit evolution success rate. Therefore, the global signal optimization based RTC optimal design method applied in the elec-tronic circuit fault self-repair technology is proven to be feasible, effective, and advantageous.

Multi-Layer E-Textile Circuits

Science.gov (United States)

Dunne, Lucy E.; Bibeau, Kaila; Mulligan, Lucie; Frith, Ashton; Simon, Cory

2012-01-01

Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

Science.gov (United States)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

Process Variations and Probabilistic Integrated Circuit Design

CERN Document Server

Haase, Joachim

2012-01-01

Uncertainty in key parameters within a chip and between different chips in the deep sub micron era plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process.  Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development.   This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits.  Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.  Trains IC designers to recognize problems caused by parameter variations during manufacturing and to choose the best methods available to mitigate these issues during the design process; Offers both qual...

Mechanically and electrically robust metal-mask design for organic CMOS circuits

Science.gov (United States)

Shintani, Michihiro; Qin, Zhaoxing; Kuribara, Kazunori; Ogasahara, Yasuhiro; Hiromoto, Masayuki; Sato, Takashi

2018-04-01

The design of metal masks for fabricating organic CMOS circuits requires the consideration of not only the electrical property of the circuits, but also the mechanical strength of the masks. In this paper, we propose a new design flow for metal masks that realizes coanalysis of the mechanical and electrical properties and enables design exploration considering the trade-off between the two properties. As a case study, we apply a “stitching technique” to the mask design of a ring oscillator and explore the best design. With this technique, mask patterns are divided into separate parts using multiple mask layers to improve the mechanical strength at the cost of high resistance of the vias. By a numerical experiment, the design trade-off of the stitching technique is quantitatively analyzed, and it is demonstrated that the proposed flow is useful for the exploration of the designs of metal masks.

Superior model for fault tolerance computation in designing nano-sized circuit systems

Energy Technology Data Exchange (ETDEWEB)

Singh, N. S. S., E-mail: narinderjit@petronas.com.my; Muthuvalu, M. S., E-mail: msmuthuvalu@gmail.com [Fundamental and Applied Sciences Department, Universiti Teknologi PETRONAS, Bandar Seri Iskandar, Perak (Malaysia); Asirvadam, V. S., E-mail: vijanth-sagayan@petronas.com.my [Electrical and Electronics Engineering Department, Universiti Teknologi PETRONAS, Bandar Seri Iskandar, Perak (Malaysia)

2014-10-24

As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalization of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines.

Superior model for fault tolerance computation in designing nano-sized circuit systems

International Nuclear Information System (INIS)

Singh, N. S. S.; Muthuvalu, M. S.; Asirvadam, V. S.

2014-01-01

As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalization of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines

Design of Threshold Controller Based Chaotic Circuits

DEFF Research Database (Denmark)

Mohamed, I. Raja; Murali, K.; Sinha, Sudeshna

2010-01-01

We propose a very simple implementation of a second-order nonautonomous chaotic oscillator, using a threshold controller as the only source of nonlinearity. We demonstrate the efficacy and simplicity of our design through numerical and experimental results. Further, we show that this approach...... of using a threshold controller as a nonlinear element, can be extended to obtain autonomous and multiscroll chaotic attractor circuits as well....

Design of a semi-custom integrated circuit for the SLAC SLC timing control system

International Nuclear Information System (INIS)

Linstadt, E.

1984-10-01

A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given

Analog circuit design a tutorial guide to applications and solutions

CERN Document Server

Williams, Jim

2011-01-01

* Covers the fundamentals of linear/analog circuit and system design to guide engineers with their design challenges. * Based on the Application Notes of Linear Technology, the foremost designer of high performance analog products, readers will gain practical insights into design techniques and practice. * Broad range of topics, including power management tutorials, switching regulator design, linear regulator design, data conversion, signal conditioning, and high frequency/RF design. * Contributors include the leading lights in analog design, Robert Dobkin, Jim Willia

Electric circuits essentials

CERN Document Server

REA, Editors of

2012-01-01

REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph

Integrated circuits, and design and manufacture thereof

Science.gov (United States)

Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

2006-04-18

A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

Directory of Open Access Journals (Sweden)

Kwang-Jow Gan

2016-06-01

Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

AnalogRF and mixed-signal circuit systematic design

CERN Document Server

Tlelo-Cuautle, Esteban; Castro-Lopez, Rafael

2013-01-01

Despite the fact that in the digital domain, designers can take full benefits of IPs and design automation tools to synthesize and design very complex systems, the analog designers’ task is still considered as a ‘handcraft’, cumbersome and very time consuming process. Thus, tremendous efforts are being deployed  to develop new design methodologies in the analog/RF and mixed-signal domains. This book collects 16 state-of-the-art contributions devoted to the topic of systematic design of analog, RF and mixed signal circuits. Divided in the two parts Methodologies and Techniques recent theories, synthesis techniques and design methodologies, as well as new sizing approaches in the field of robust analog and mixed signal design automation are presented for researchers and R/D engineers.  

Atomic memory access hardware implementations

Science.gov (United States)

Ahn, Jung Ho; Erez, Mattan; Dally, William J

2015-02-17

Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.

Circuit Design and Implementation of Micro-Displacement Measurement System of Laser Self-Mixing Interference

Directory of Open Access Journals (Sweden)

Guang Ya LIU

2014-02-01

Full Text Available In this paper we put forward the basic structure of a micro-displacement measuring system based on the basic theory of laser feedback, and designed a hardware circuit of the system, including the LD driver and modulation circuit, photoelectric signal amplifier and filter circuit, which meet the requirements of the follow-up experimental study by theoretical analysis and Multisim simulation to the circuit.

Analog Circuit Design Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC

CERN Document Server

Roermund, Arthur; Baschirotto, Andrea

2012-01-01

The book contains the contribution of 18 tutorials of the 20th workshop on Advances in Analog Circuit Design.  Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 20 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of Low-Voltage Low-Power Data Converters - Chaired by Prof. Anderea Baschirotto, University of Milan-Bicocca Short Range Wireless Front-Ends - Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology Power management and DC-DC - Chaired by Prof. M. Steyaert, Katholieke University Leuven Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design.

Modular design of synthetic gene circuits with biological parts and pools.

Science.gov (United States)

Marchisio, Mario Andrea

2015-01-01

Synthetic gene circuits can be designed in an electronic fashion by displaying their basic components-Standard Biological Parts and Pools of molecules-on the computer screen and connecting them with hypothetical wires. This procedure, achieved by our add-on for the software ProMoT, was successfully applied to bacterial circuits. Recently, we have extended this design-methodology to eukaryotic cells. Here, highly complex components such as promoters and Pools of mRNA contain hundreds of species and reactions whose calculation demands a rule-based modeling approach. We showed how to build such complex modules via the joint employment of the software BioNetGen (rule-based modeling) and ProMoT (modularization). In this chapter, we illustrate how to utilize our computational tool for synthetic biology with the in silico implementation of a simple eukaryotic gene circuit that performs the logic AND operation.

Innovative design with learning reflexiveness for developing the Hamiltonian circuit learning games

Directory of Open Access Journals (Sweden)

Meng-Chien Yang

2018-02-01

Full Text Available In this study, we use a new proposed framework to develop the Hamiltonian circuit learning games for college students. The framework is for enhancing learners’ activities with learning reflexiveness. The design of these games is based on this framework to achieve the targeted learning outcomes. In recent years, the game-based learning is a very popular research topic. The Hamiltonian circuit is an important concepts for learning many computer science and electric engineering topics, such as IC design routing algorithm. The developed games use guiding rules to enable students to learn the Hamiltonian circuit in complicate graph problem. After the game, the learners are given a reviewing test which using the animation film for explaining the knowledge. This design concept is different from the previous studies. Through this new design, the outcome gets the better learning results under the effect of reflection. The students will have a deeper impression on the subject, and through self-learning and active thinking, in the game will have a deeper experience.

Analytical Study on Thermal and Mechanical Design of Printed Circuit Heat Exchanger

Energy Technology Data Exchange (ETDEWEB)

Yoon, Su-Jong [Idaho National Lab. (INL), Idaho Falls, ID (United States); Sabharwall, Piyush [Idaho National Lab. (INL), Idaho Falls, ID (United States); Kim, Eung-Soo [Idaho National Lab. (INL), Idaho Falls, ID (United States)

2013-09-01

The analytical methodologies for the thermal design, mechanical design and cost estimation of printed circuit heat exchanger are presented in this study. In this study, three flow arrangements of parallel flow, countercurrent flow and crossflow are taken into account. For each flow arrangement, the analytical solution of temperature profile of heat exchanger is introduced. The size and cost of printed circuit heat exchangers for advanced small modular reactors, which employ various coolants such as sodium, molten salts, helium, and water, are also presented.

The design and development of a multilayer RF circuit card

OpenAIRE

Ferro, John Francis

1991-01-01

The goal of this project was to design an airborne radio frequency circuit card that was very light weight, occupied a small volume, and operated from 20 Mhz to 1500 Mhz. The circuit card being reported on is called an RF multicoupler, and is one of two cards used in a radio frequency distribution unit (RFD). This unit interfaces a large number of receivers to various antennas. In the past this type of circuitry was done by cascading discrete connectorized RF compo...

Design and Characterization of DNA Strand-Displacement Circuits in Serum-Supplemented Cell Medium.

Science.gov (United States)

Fern, Joshua; Schulman, Rebecca

2017-09-15

The functional stability and lifetimes of synthetic molecular circuits in biological environments are important for long-term, stable sensors or controllers of cell or tissue behavior. DNA-based molecular circuits, in particular DNA strand-displacement circuits, provide simple and effective biocompatible control mechanisms and sensors, but are vulnerable to digestion by nucleases present in living tissues and serum-supplemented cell culture. The stability of double-stranded and single-stranded DNA circuit components in serum-supplemented cell medium and the corresponding effect of nuclease-mediated degradation on circuit performance were characterized to determine the major routes of degradation and DNA strand-displacement circuit failure. Simple circuit design choices, such as the use of 5' toeholds within the DNA complexes used as reactants in the strand-displacement reactions and the termination of single-stranded components with DNA hairpin domains at the 3' termini, significantly increase the functional lifetime of the circuit components in the presence of nucleases. Simulations of multireaction circuits, guided by the experimentally measured operation of single-reaction circuits, enable predictive realization of multilayer and competitive-reaction circuit behavior. Together, these results provide a basic route to increased DNA circuit stability in cell culture environments.

PathwayAccess: CellDesigner plugins for pathway databases.

Science.gov (United States)

Van Hemert, John L; Dickerson, Julie A

2010-09-15

CellDesigner provides a user-friendly interface for graphical biochemical pathway description. Many pathway databases are not directly exportable to CellDesigner models. PathwayAccess is an extensible suite of CellDesigner plugins, which connect CellDesigner directly to pathway databases using respective Java application programming interfaces. The process is streamlined for creating new PathwayAccess plugins for specific pathway databases. Three PathwayAccess plugins, MetNetAccess, BioCycAccess and ReactomeAccess, directly connect CellDesigner to the pathway databases MetNetDB, BioCyc and Reactome. PathwayAccess plugins enable CellDesigner users to expose pathway data to analytical CellDesigner functions, curate their pathway databases and visually integrate pathway data from different databases using standard Systems Biology Markup Language and Systems Biology Graphical Notation. Implemented in Java, PathwayAccess plugins run with CellDesigner version 4.0.1 and were tested on Ubuntu Linux, Windows XP and 7, and MacOSX. Source code, binaries, documentation and video walkthroughs are freely available at http://vrac.iastate.edu/~jlv.

Importance of Practical Relevance and Design Modules in Electrical Circuits Education

Directory of Open Access Journals (Sweden)

Kalpathy Sundaram

2011-05-01

Full Text Available The interactive technical electronic book, TechEBook, currently under development at the University of Central Florida (UCF, provides a useful tool for engineers and scientists through unique features compared to the most used traditional electrical circuit textbooks available in the market. TechEBook has comprised the two worlds of classical circuit books and an interactive operating platform such as iPads, laptops and desktops utilizing Java Virtual Machine operator. The TechEBook provides an interactive applets screen that holds many modules, in which each had a specific application in the self learning process. This paper describes two of the interactive techniques in the TechEBook known as, Practical Relevance Modules (PRM and Design Modules (DM. The Practical Relevance Module will assist the readers to learn electrical circuit analysis and to understand the practical application of the electrical network theory through solving real world examples and problems. The Design Module will help students design real-life problems. These modules will be displayed after each section in the TechEBook for the user to relate his/her understanding with the outside world, which introduces the term me-applying and me-designing, as a comprehensive full experience for self or individualized education. The main emphasis of this paper is the PRM while the DM will be discussed in brief. A practical example of applying the PRM and DM features is discussed as part of a basic electrical engineering course currently given at UCF and results show improved student performances in learning materials in Electrical Circuits. In the future, such modules can be redesigned to become highly interactive with illustrated animations.

Integrated electric circuit engineering system in LSI design center, Konami Kogyo Co. Ltd

Energy Technology Data Exchange (ETDEWEB)

Kamitsuki, Kagehiko; Tanaka, Tomiaki

1988-08-26

Development of the integrated engineering system is presented which designs and manufactures the hardwares, softwares and cases of electronic game products with LSI integratedly as an experiment. The system is intended to reduce the number of each development of the parts, to verify each other by comparing each parts with the product concept during the development, to reduce modifications, and to shorten development periods. The main subsystems are an electric circuit CAD for LSI designs and a mechanical CAD for case or printed circuit board designs. The LSI development period has been shortened up to one month by a larger capacity computer and higher speed simulator, and the electric circuit engineering system capable of keeping step with the software development has been approximately completed. In the future, the system will be intended to introduce an expert system or a visual system capable of predicting the final product during a logical design period. (10 figs, 1 photo)

The Design of Phase-Locked-Loop Circuit for Precision Capacitance Micrometer

Directory of Open Access Journals (Sweden)

Li Shujie

2016-01-01

Full Text Available High precision non-contact micrometer is normally divided into three categories: inductance micrometer, capacitance micrometer and optical interferometer micrometer. The capacitance micrometer is widely used because it has high performance to price ratio. With the improvement of automation level, precision of capacitance micrometer is required higher and higher. Generally, capacitance micrometer consists of the capacitance sensor, capacitance/voltage conversion circuit, and modulation and demodulation circuits. However, due to the existing of resistors, capacitors and other components in the circuit, the phase shift of the carrier signal and the modulated signal might occur. In this case, the specific value of phase shift cannot be determined. Therefore, error caused by the phase shift cannot be eliminated. This will reduce the accuracy of micrometer. In this design, in order to eliminate the impact of the phase shift, the phase-locked-loop (PLL circuit is employed. Through the experiment, the function of tracking the input signal phase and frequency is achieved by the phase-locked-loop circuit. This signal processing method can also be applied to tuber electrical resistance tomography system and other precision measurement circuit.

The design of a semi-custom intergrated circuit for the SLAC SLC timing control system

International Nuclear Information System (INIS)

Linstadt, E.

1985-01-01

A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given

Design of arithmetic circuits in quantum dot cellular automata nanotechnology

CERN Document Server

Sridharan, K

2015-01-01

This research monograph focuses on the design of arithmetic circuits in Quantum Dot Cellular Automata (QCA). Using the fact that the 3-input majority gate is a primitive in QCA, the book sets out to discover hitherto unknown properties of majority logic in the context of arithmetic circuit designs. The pursuit for efficient adders in QCA takes two forms. One involves application of the new results in majority logic to existing adders. The second involves development of a custom adder for QCA technology. A QCA adder named as hybrid adder is proposed and it is shown that it outperforms existing multi-bit adders with respect to area and delay. The work is extended to the design of a low-complexity multiplier for signed numbers in QCA. Furthermore the book explores two aspects unique to QCA technology, namely thermal robustness and the role of interconnects. In addition, the book introduces the reader to QCA layout design and simulation using QCADesigner. Features & Benefits: This research-based book: ·  �...

Signal detection circuit design of HCN measurement system based on TDLAS

Science.gov (United States)

He, Chungui; Zhang, Yujun; Chen, Chen; Lu, Yibing; Liu, Guohua; Gao, Yanwei; You, Kun; He, Ying; Zhang, Kai; Liu, Wenqing

2016-10-01

Hydrogen cyanide gas leakage may exist in the petrochemical industry, smelting plant, and other industrial processes, causing serious harm to the environment, and even threatening the safety of personnel. So the continuous detection of HCN gas plays an important role in the prevention of risk in production process and storage environment that existing hydrogen cyanide gas. The Tunable Diode Laser Technology (TDLAS) has advantages of non-contact, high sensitivity, high selectivity, and fast response time, etc., which is one of the ideal method of gas detection technologies and can be used to measure the hydrogen cyanide concentration. This paper studies the HCN detection system based on TDLAS technology, selects the absorption lines of hydrogen cyanide in 6539.12cm-1, and utilizes the center wavelength of 1.529μm distributed feedback (DFB) laser as a light source. It is discussed in detail on technical requirements of a high frequency modulated laser signal detection circuit, including noise level, gain, and bandwidth. Based on the above theory, the high frequency modulation preamplifier circuit and main amplifier circuit are designed for InGaAs photoelectric detector. The designed circuits are calculation analyzed with corresponding formula and simulation analyzed based on the Multisim software.

Toward scalable parts families for predictable design of biological circuits.

Science.gov (United States)

Lucks, Julius B; Qi, Lei; Whitaker, Weston R; Arkin, Adam P

2008-12-01

Our current ability to engineer biological circuits is hindered by design cycles that are costly in terms of time and money, with constructs failing to operate as desired, or evolving away from the desired function once deployed. Synthetic biologists seek to understand biological design principles and use them to create technologies that increase the efficiency of the genetic engineering design cycle. Central to the approach is the creation of biological parts--encapsulated functions that can be composited together to create new pathways with predictable behaviors. We define five desirable characteristics of biological parts--independence, reliability, tunability, orthogonality and composability, and review studies of small natural and synthetic biological circuits that provide insights into each of these characteristics. We propose that the creation of appropriate sets of families of parts with these properties is a prerequisite for efficient, predictable engineering of new function in cells and will enable a large increase in the sophistication of genetic engineering applications.

Critical Gates Identification for Fault-Tolerant Design in Math Circuits

Directory of Open Access Journals (Sweden)

Tian Ban

2017-01-01

Full Text Available Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to the detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature to find a good trade-off. In this paper, critical constituent gates in math circuits are detected and graded based on the impact of an error in the output of a circuit. These critical gates should be hardened first under the area constraint of design criteria. Indeed, output bits considered crucial to a system receive higher priorities to be protected, reducing the occurrence of critical errors. The 74283 fast adder is used as an example to illustrate the feasibility and efficiency of the proposed approach.

[Design of High Frequency Signal Detecting Circuit of Human Body Impedance Used for Ultrashort Wave Diathermy Apparatus].

Science.gov (United States)

Fan, Xu; Wang, Yunguang; Cheng, Haiping; Chong, Xiaochen

2016-02-01

The present circuit was designed to apply to human tissue impedance tuning and matching device in ultra-short wave treatment equipment. In order to judge if the optimum status of circuit parameter between energy emitter circuit and accepter circuit is in well syntony, we designed a high frequency envelope detect circuit to coordinate with automatic adjust device of accepter circuit, which would achieve the function of human tissue impedance matching and tuning. Using the sampling coil to receive the signal of amplitude-modulated wave, we compared the voltage signal of envelope detect circuit with electric current of energy emitter circuit. The result of experimental study was that the signal, which was transformed by the envelope detect circuit, was stable and could be recognized by low speed Analog to Digital Converter (ADC) and was proportional to the electric current signal of energy emitter circuit. It could be concluded that the voltage, transformed by envelope detect circuit can mirror the real circuit state of syntony and realize the function of human tissue impedance collecting.

EPICS: Channel Access security design

International Nuclear Information System (INIS)

Kraimer, M.; Hill, J.

1994-05-01

This document presents the design for implementing the requirements specified in: EPICS -- Channel Access Security -- functional requirements, Ned. D. Arnold, 03/09/92. Use of the access security system is described along with a summary of the functional requirements. The programmer's interface is given. Security protocol is described and finally aids for reading the access security code are provided

Design of switched-capacitor filter circuits using low gain amplifiers

CERN Document Server

Serra, Hugo Alexandre de Andrade

2015-01-01

This book describes the design of switched-capacitor filter circuits using low gain amplifiers and demonstrates some techniques that can minimize the effects of parasitic capacitances during the design phase. Focus is given in the design of low-pass and band-pass SC filters, and how higher order filters can be achieved using cascaded biquadratic filter sections. The authors also describe a low voltage implementation of a low-pass SC filter.

Reported Design Processes for Accessibility in Rail Transport

DEFF Research Database (Denmark)

Herriott, Richard; Cook, Sharon

2014-01-01

requirements with the aim of maximising accessibility in products and services. A review of ID literature has mainly developed in the arena of product design and design for assistive technology. Accessibility is a fundamental requirement in public transport (PT) yet there exists little research on design...... for accessibility or ID in this area. How is accessibility and the needs of users accounted for in rail transport design? This paper analyses interviews with rolling stock producers, operators and design consultancies. These conducted to determine if ID design methods are used explicitly and the extent to which...

Design of CMOS analog integrated fractional-order circuits applications in medicine and biology

CERN Document Server

Tsirimokou, Georgia; Elwakil, Ahmed

2017-01-01

This book describes the design and realization of analog fractional-order circuits, which are suitable for on-chip implementation, capable of low-voltage operation and electronic adjustment of their characteristics. The authors provide a brief introduction to fractional-order calculus, followed by design issues for fractional-order circuits of various orders and types. The benefits of this approach are demonstrated with current-mode and voltage-mode filter designs. Electronically tunable emulators of fractional-order capacitors and inductors are presented, where the behavior of the corresponding chips fabricated using the AMS 0.35um CMOS process has been experimentally verified. Applications of fractional-order circuits are demonstrated, including a pre-processing stage suitable for the implementation of the Pan-Tompkins algorithm for detecting the QRS complexes of an electrocardiogram (ECG), a fully tunable implementation of the Cole-Cole model used for the modeling of biological tissues, and a simple, non-i...

Superconducting high current magnetic Circuit: Design and Parameter Estimation of a Simulation Model

CERN Document Server

Kiefer, Alexander; Reich, Werner Dr

The Large Hadron Collider (LHC) utilizes superconducting main dipole magnets that bend the trajectory of the particle beams. In order to adjust the not completely homogeneous magnetic feld of the main dipole magnets, amongst others, sextupole correctcorrector magnets are used. In one of the 16 corrector magnet circuits placed in the LHC, 154 of these sextupole corrector magnets (MCS) are connected in series. This circuit extends on a 3.35 km tunnel section of the LHC. In 2015, at one of the 16 circuits a fault was detected. The simulation of this circuit is helpful for fnding the fault by applying alternating current at different frequencies. Within this Thesis a PSpice model for the simulation of the superconducting corrector magnet circuit was designed. The physical properties of the circuit and its elements were analyzed and implemented. For the magnets and bus-bars, sub-circuits were created which reflect the parasitic effects of electrodynamics and electrostats. The inductance values and capacitance valu...

Analog front end circuit design of CSNS beam loss monitor system

International Nuclear Information System (INIS)

Xiao Shuai; Guo Xian; Tian Jianmin; Zeng Lei; Xu Taoguang; Fu Shinian

2013-01-01

The China Spallation Neutron Source (CSNS) beam loss monitor system uses gas ionization chamber to detect beam losses. The output signals from ionization chamber need to be processed in the analog front end circuit, which has been designed and developed independently. The way of transimpedance amplifier was used to achieve current-voltage (I-V) conversion measurement of signal with low repetition rate, low duty cycle and low amplitude. The analog front end circuit also realized rapid response to the larger beam loss in order to protect the safe operation of the accelerator equipment. The testing results show that the analog front end circuit meets the requirements of beam loss monitor system. (authors)

Compact self-powered synchronous energy extraction circuit design with enhanced performance

Science.gov (United States)

Liu, Weiqun; Zhao, Caiyou; Badel, Adrien; Formosa, Fabien; Zhu, Qiao; Hu, Guangdi

2018-04-01

Synchronous switching circuit is viewed as an effective solution of enhancing the generator’s performance and providing better adaptability for load variations. A critical issue for these synchronous switching circuits is the self-powered realization. In contrast with other methods, the electronic breaker possesses the advantage of simplicity and reliability. However, beside the energy consumption of the electronic breakers, the parasitic capacitance decreases the available piezoelectric voltage. In this technical note, a new compact design of the self-powered switching circuit using electronic breaker is proposed. The envelope diodes are excluded and only a single envelope capacitor is used. The parasitic capacitance is reduced to half with boosted performance while the components are reduced with cost saved.

Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

International Nuclear Information System (INIS)

Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun

2016-01-01

The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD

Design improvement of FPGA and CPU based digital circuit cards to solve timing issues

Energy Technology Data Exchange (ETDEWEB)

Lee, Dongil; Lee, Jaeki; Lee, Kwang-Hyun [KHNP CRI, Daejeon (Korea, Republic of)

2016-10-15

The digital circuit cards installed at NPPs (Nuclear Power Plant) are mostly composed of a CPU (Central Processing Unit) and a PLD (Programmable Logic Device; these include a FPGA (Field Programmable Gate Array) and a CPLD (Complex Programmable Logic Device)). This type of structure is typical and is maintained using digital circuit cards. There are no big problems with this device as a structure. In particular, signal delay causes a lot of problems when various IC (Integrated Circuit) and several circuit cards are connected to the BUS of the backplane in the BUS design. This paper suggests a structure to improve the BUS signal timing problems in a circuit card consisting of CPU and FPGA. Nowadays, as the structure of circuit cards has become complex and mass data at high speed is communicated through the BUS, data integrity is the most important issue. The conventional design does not consider delay and the synchronicity of signal and this causes many problems in data processing. In order to solve these problems, it is important to isolate the BUS controller from the CPU and maintain constancy of the signal delay by using a PLD.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

Science.gov (United States)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor

Science.gov (United States)

Karaki, Nobuo; Nanmoto, Takashi; Inoue, Satoshi

This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500kHz, drawing 180μA from a 5V power source. The microprocessor's electromagnetic emissions are 21dB less than those of the synchronous counterpart.

Lecture note on digital circuit design for high energy physics experiment

International Nuclear Information System (INIS)

Ikeda, Hirokazu.

1993-08-01

This lecture gives basic ideas and practice of the digital circuit design for high energy physics experiment. The lecture has a special emphasis on a simulation study with a hardware description language. The student could complete a design of a simple RISC based computer after finishing this course. (author)

A cell-based design approach for RSFQ circuits using a binary decision diagram

International Nuclear Information System (INIS)

Yoshikawa, N.; Koshiyama, J.

1999-01-01

We propose a cell-based design approach for rapid single flux quantum (RSFQ) circuits based on a binary decision diagram (BDD). The BDD is a way to represent a logical function using a directed graph which consists of binary switches having one input and two outputs. Since complex logic circuits can be implemented in the form of regular arrays of the BDD binary switches, we can use a cell-based layout methodology for the design of the RSFQ circuits. In this study, we implemented the BDD binary switches by a D 2 flip-flop. In the BDD design approach we made a cell library which contains a binary switch, pulse splitters, confluence buffers and Josephson transmission lines. All cell layouts in the library have identical widths and heights, so that any logic function can be laid out by simple connection of the library cells. As a case study, we implemented a 1-bit RSFQ half-adder and a 3-bit encoder for a flash AD converter. (author)

Error correcting circuit design with carbon nanotube field effect transistors

Science.gov (United States)

Liu, Xiaoqiang; Cai, Li; Yang, Xiaokuo; Liu, Baojun; Liu, Zhongyong

2018-03-01

In this work, a parallel error correcting circuit based on (7, 4) Hamming code is designed and implemented with carbon nanotube field effect transistors, and its function is validated by simulation in HSpice with the Stanford model. A grouping method which is able to correct multiple bit errors in 16-bit and 32-bit application is proposed, and its error correction capability is analyzed. Performance of circuits implemented with CNTFETs and traditional MOSFETs respectively is also compared, and the former shows a 34.4% decrement of layout area and a 56.9% decrement of power consumption.

Designing TSVs for 3D Integrated Circuits

CERN Document Server

Khan, Nauman

2013-01-01

This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits.  It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks.  Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available....

Design method of general-purpose driving circuit for CCD based on CPLD

International Nuclear Information System (INIS)

Zhang Yong; Tang Benqi; Xiao Zhigang; Wang Zujun; Huang Shaoyan

2005-01-01

It is very important for studying the radiation damage effects and mechanism systematically about CCD to develop a general-purpose test platform. The paper discusses the design method of general-purpose driving circuit for CCD based on CPLD and the realization approach. A main controller has being designed to read the data file from the outer memory, setup the correlative parameter registers and produce the driving pulses according with parameter request strictly, which is based on MAX7000S by using MAX-PLUS II software. The basic driving circuit module has being finished based on this method. The output waveform of the module is the same figure as the simulation waveform. The result indicates that the design method is feasible. (authors)

Feedback in analog circuits

CERN Document Server

Ochoa, Agustin

2016-01-01

This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...

Designer's handbook of instrumentation and control circuits

CERN Document Server

Carr, Joseph J

1991-01-01

Here is a comprehensive, practical guide to the entire process of analog instrumentation and control, from sensor input to data conversion circuitry and final output. This readable handbook avoids complex mathematical treatments, instead taking an applications-oriented approach and presenting many sample circuits and concrete examples. It is an essential reference for engineers and high-level technicians in a variety of scientific and engineering fields--anywhere data is collected electronically and where such data is used to control physical processes.Key Features* Covers design o

Wideband continuous-time ΣΔ ADCs, automotive electronics, and power management : advances in analog circuit design 2016

NARCIS (Netherlands)

Baschirotto, A.; Harpe, P.J.A.; Makinwa, K.A.A.

2017-01-01

This book is based on the 18 tutorials presented during the 25th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with

Design principles and realization of electro-optical circuit boards

Science.gov (United States)

Betschon, Felix; Lamprecht, Tobias; Halter, Markus; Beyer, Stefan; Peterson, Harry

2013-02-01

The manufacturing of electro-optical circuit boards (EOCB) is based to a large extent on established technologies. First products with embedded polymer waveguides are currently produced in series. The range of applications within the sensor and data communication markets is growing with the increasing maturity level. EOCBs require design flows, processes and techniques similar to existing printed circuit board (PCB) manufacturing and appropriate for optical signal transmission. A key aspect is the precise and automated assembly of active and passive optical components to the optical waveguides which has to be supported by the technology. The design flow is described after a short introduction into the build-up of EOCBs and the motivation for the usage of this technology within the different application fields. Basis for the design of EOCBs are the required optical signal transmission properties. Thereafter, the devices for the electro-optical conversion are chosen and the optical coupling approach is defined. Then, the planar optical elements (waveguides, splitters, couplers) are designed and simulated. This phase already requires co-design of the optical and electrical domain using novel design flows. The actual integration of an optical system into a PCB is shown in the last part. The optical layer is thereby laminated to the purely electrical PCB using a conventional PCB-lamination process to form the EOCB. The precise alignment of the various electrical and optical layers is thereby essential. Electrical vias are then generated, penetrating also the optical layer, to connect the individual electrical layers. Finally, the board has to be tested electrically and optically.

Frontiers in Planar Lightwave Circuit Technology Design, Simulation, and Fabrication

CERN Document Server

Janz, Siegfried; Tanev, Stoyan

2005-01-01

This book is the result of the NATO Advanced Research Workshop on Frontiers in Planar Lightwave Circuit Technology, which took place in Ottawa, Canada from September 21-25, 2004. Many of the world’s leading experts in integrated photonic design, theory and experiment were invited to give lectures in their fields of expertise, and participate in discussions on current research and applications, as well as the new directions planar lightwave circuit technology is evolving towards. The sum of their contributions to this book constitutes an excellent record of many key issues and scientific problems in planar lightwave circuit research at the time of writing. In this volume the reader will find detailed overviews of experimental and theoretical work in high index contrast waveguide systems, micro-optical resonators, nonlinear optics, and advanced optical simulation methods, as well as articles describing emerging applications of integrated optics for medical and biological applications.

Operational amplifier circuits analysis and design

CERN Document Server

Nelson, J C C

1995-01-01

This book, a revised and updated version of the author's Basic Operational Amplifiers (Butterworths 1986), enables the non-specialist to make effective use of readily available integrated circuit operational amplifiers for a range of applications, including instrumentation, signal generation and processing.It is assumed the reader has a background in the basic techniques of circuit analysis, particularly the use of j notation for reactive circuits, with a corresponding level of mathematical ability. The underlying theory is explained with sufficient but not excessive, detail. A range of compu

Dynamic Analysis and Circuit Design of a Novel Hyperchaotic System with Fractional-Order Terms

Directory of Open Access Journals (Sweden)

Abir Lassoued

2017-01-01

Full Text Available A novel hyperchaotic system with fractional-order (FO terms is designed. Its highly complex dynamics are investigated in terms of equilibrium points, Lyapunov spectrum, and attractor forms. It will be shown that the proposed system exhibits larger Lyapunov exponents than related hyperchaotic systems. Finally, to enhance its potential application, a related circuit is designed by using the MultiSIM Software. Simulation results verify the effectiveness of the suggested circuit.

LANSCE personnel access control system (PACS)

International Nuclear Information System (INIS)

Sturrock, J.C.; Gallegos, F.R.; Hall, M.J.

1997-01-01

The Radiation Security System (RSS) at the Los Alamos Neutron Science Center (LANSCE) provides personnel protection from prompt radiation due to accelerated beam. The Personnel Access Control System (PACS) is a component of the RSS that is designed to prevent personnel access to areas where prompt radiation is a hazard. PACS was designed to replace several older personnel safety systems (PSS) with a single modem unified design. Lessons learned from the operation over the last 20 years were incorporated into a redundant sensor, single-point failure safe, fault tolerant, and tamper-resistant system that prevents access to the beam areas by controlling the access keys and beam stoppers. PACS uses a layered philosophy to the physical and electronic design. The most critical assemblies are battery backed up, relay logic circuits; less critical devices use Programmable Logic Controllers (PLCs) for timing functions and communications. Outside reviewers have reviewed the operational safety of the design. The design philosophy, lessons learned, hardware design, software design, operation, and limitations of the device are described

Design and characterization of integrated components for SiN photonic quantum circuits.

Science.gov (United States)

Poot, Menno; Schuck, Carsten; Ma, Xiao-Song; Guo, Xiang; Tang, Hong X

2016-04-04

The design, fabrication, and detailed calibration of essential building blocks towards fully integrated linear-optics quantum computation are discussed. Photonic devices are made from silicon nitride rib waveguides, where measurements on ring resonators show small propagation losses. Directional couplers are designed to be insensitive to fabrication variations. Their offset and coupling lengths are measured, as well as the phase difference between the transmitted and reflected light. With careful calibrations, the insertion loss of the directional couplers is found to be small. Finally, an integrated controlled-NOT circuit is characterized by measuring the transmission through different combinations of inputs and outputs. The gate fidelity for the CNOT operation with this circuit is estimated to be 99.81% after post selection. This high fidelity is due to our robust design, good fabrication reproducibility, and extensive characterizations.

MEMS 3-DoF gyroscope design, modeling and simulation through equivalent circuit lumped parameter model

International Nuclear Information System (INIS)

Mian, Muhammad Umer; Khir, M. H. Md.; Tang, T. B.; Dennis, John Ojur; Riaz, Kashif; Iqbal, Abid; Bazaz, Shafaat A.

2015-01-01

Pre-fabrication, behavioural and performance analysis with computer aided design (CAD) tools is a common and fabrication cost effective practice. In light of this we present a simulation methodology for a dual-mass oscillator based 3 Degree of Freedom (3-DoF) MEMS gyroscope. 3-DoF Gyroscope is modeled through lumped parameter models using equivalent circuit elements. These equivalent circuits consist of elementary components which are counterpart of their respective mechanical components, used to design and fabricate 3-DoF MEMS gyroscope. Complete designing of equivalent circuit model, mathematical modeling and simulation are being presented in this paper. Behaviors of the equivalent lumped models derived for the proposed device design are simulated in MEMSPRO T-SPICE software. Simulations are carried out with the design specifications following design rules of the MetalMUMPS fabrication process. Drive mass resonant frequencies simulated by this technique are 1.59 kHz and 2.05 kHz respectively, which are close to the resonant frequencies found by the analytical formulation of the gyroscope. The lumped equivalent circuit modeling technique proved to be a time efficient modeling technique for the analysis of complex MEMS devices like 3-DoF gyroscopes. The technique proves to be an alternative approach to the complex and time consuming couple field analysis Finite Element Analysis (FEA) previously used

MEMS 3-DoF gyroscope design, modeling and simulation through equivalent circuit lumped parameter model

Energy Technology Data Exchange (ETDEWEB)

Mian, Muhammad Umer, E-mail: umermian@gmail.com; Khir, M. H. Md.; Tang, T. B. [Department of Electrical and Electronic Engineering, Universiti Teknologi PETRONAS, Tronoh, Perak (Malaysia); Dennis, John Ojur [Department of Fundamental & Applied Sciences, Universiti Teknologi PETRONAS, Tronoh, Perak (Malaysia); Riaz, Kashif; Iqbal, Abid [Faculty of Electronics Engineering, GIK Institute of Engineering Sciences and Technology, Topi, Khyber Pakhtunkhaw (Pakistan); Bazaz, Shafaat A. [Department of Computer Science, Center for Advance Studies in Engineering, Islamabad (Pakistan)

2015-07-22

Pre-fabrication, behavioural and performance analysis with computer aided design (CAD) tools is a common and fabrication cost effective practice. In light of this we present a simulation methodology for a dual-mass oscillator based 3 Degree of Freedom (3-DoF) MEMS gyroscope. 3-DoF Gyroscope is modeled through lumped parameter models using equivalent circuit elements. These equivalent circuits consist of elementary components which are counterpart of their respective mechanical components, used to design and fabricate 3-DoF MEMS gyroscope. Complete designing of equivalent circuit model, mathematical modeling and simulation are being presented in this paper. Behaviors of the equivalent lumped models derived for the proposed device design are simulated in MEMSPRO T-SPICE software. Simulations are carried out with the design specifications following design rules of the MetalMUMPS fabrication process. Drive mass resonant frequencies simulated by this technique are 1.59 kHz and 2.05 kHz respectively, which are close to the resonant frequencies found by the analytical formulation of the gyroscope. The lumped equivalent circuit modeling technique proved to be a time efficient modeling technique for the analysis of complex MEMS devices like 3-DoF gyroscopes. The technique proves to be an alternative approach to the complex and time consuming couple field analysis Finite Element Analysis (FEA) previously used.

Minimum-Energy Sub-Threshold Self-Timed Circuits: Design Methodology and a Case Study

DEFF Research Database (Denmark)

Akgun, Omer Can; Rodrigues, Joachim; Sparsø, Jens

2010-01-01

, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which is based on contemporary synchronous EDA tools, and which transforms a synchronous design, into a corresponding self-timed circuit. The design flow and the current-sensing technique is validated...

The design of infrared information collection circuit based on embedded technology

Science.gov (United States)

Liu, Haoting; Zhang, Yicong

2013-07-01

S3C2410 processor is a 16/32 bit RISC embedded processor which based on ARM920T core and AMNA bus, and mainly for handheld devices, and high cost, low-power applications. This design introduces a design plan of the PIR sensor system, circuit and its assembling, debugging. The Application Circuit of the passive PIR alarm uses the invisibility of the infrared radiation well into the alarm system, and in order to achieve the anti-theft alarm and security purposes. When the body goes into the range of PIR sensor detection, sensors will detect heat sources and then the sensor will output a weak signal. The Signal should be amplified, compared and delayed; finally light emitting diodes emit light, playing the role of a police alarm.

Multi parametric card to personal computers interface based in ispLSI1016 circuits

International Nuclear Information System (INIS)

Osorio Deliz, J.F.; Toledo Acosta, R.B.; Arista Romeu, E.

1997-01-01

It is described the design and principal characteristic of the interface circuit for a 16 bit multi parametric add on card for IBM or compatible microcomputer which content two communication channels of direct memory access and bidirectional between the card and the computer, an interrupt controller, a programmable address register, a default add res register of the card, a four channels multiplexer, as well as the decoder logic of the 80C186 and computer. The circuit was designed with two programmable logic devices ispL1016, which allowed drastically to diminish the quantity of utilized components and get a more flexible design in less time better characteristics

Top-down design and verification methodology for analog mixed-signal integrated circuits

NARCIS (Netherlands)

Beviz, P.

2016-01-01

The current report contains the introduction of a novel Top-Down Design and Verification methodology for AMS integrated circuits. With the introduction of new design and verification flow, more reliable and efficient development of AMS ICs is possible. The assignment incorporated the research on the

Analog circuit design : low voltage low power; short range wireless front-ends; power management and DC-DC

NARCIS (Netherlands)

Steyaert, M.; Roermund, van A.H.M.; Baschirotto, A.

2012-01-01

The book contains the contribution of 18 tutorials of the 20th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art

Thermal hydraulic tradeoffs in the design of IRIS primary circuit

International Nuclear Information System (INIS)

Oriani, L.; Lombardi, C.; Ricotti, M.E.; Paramonov, D.; Carelli, M.; Conway, L.

2001-01-01

IRIS (International Reactor Innovative and Secure) is currently being developed by an international consortium, led by Westinghouse and including universities. In order to achieve high level of safety, reduce complexity and capital cost, and enhance proliferation resistance, an integral primary circuit configuration has been selected. The integral configuration (the core, steam generators, coolant pumps, pressurizer and control rods are all contained within the reactor vessel) has no loop piping and thereby eliminates the possibility of large loss of coolant accidents. If the reactor vessel and components are designed for a very high level of natural circulation, which is promoted by an integral design, the consequence of loss of flow accidents can be significantly reduced or even completely eliminated. Core and integral primary circuit design optimization has been performed using the OSCAR computer code, a specialized tool for the analyses of the IRIS primary system developed at POLIMI. Results of trade-off studies of various in-vessel configurations explored to achieve tight packaging and high serviceability and/or replacement of components such as steam generators and pumps are reported. Effects of changes in secondary side parameters and steam generator design on system efficiency were explored together with the optimization of the vessel and steam generator dimensions and costs. The aim of the trade-off analyses was to limit the design space, and select a reference configuration for the IRIS reactor. (author)

Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits

Directory of Open Access Journals (Sweden)

Lun Li

2006-04-01

Full Text Available The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stages can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses upon a technique that integrates the best characteristics of both simulation and formal verification methods to provide an effective design validation tool, referred as Integrated Design Validation (IDV. The novelty in this approach consists of three components, circuit complexity analysis, partitioning based on design hierarchy, and coverage analysis. The circuit complexity analyzer and partitioning decompose a large design into sub-components and feed sub-components to different verification and/or simulation tools based upon known existing strengths of modern verification and simulation tools. The coverage analysis unit computes the coverage of design validation and improves the coverage by further partitioning. Various simulation and verification tools comprising IDV are evaluated and an example is used to illustrate the overall validation process. The overall process successfully validates the example to a high coverage rate within a short time. The experimental result shows that our approach is a very promising design validation method.

FLANDES, Flange Design for He Circuits by Taylor-Forge Method

International Nuclear Information System (INIS)

Pitchford, B.E.

1977-01-01

1 - Nature of the physical problem solved: Flange design for helium circuits. 2 - Method of solution: This is a flange design programme based on the Taylor forge method with an additional calculation of flange rotation and bolt load change during the application of internal pressure. The method relates only to the integral hub type of flange, with or without a secondary O-ring seal but will deal also with the flange and cover plate case

Reported Design Processes for Accessibility in Rail Transport

DEFF Research Database (Denmark)

Herriott, Richard; Cook, Sharon

2014-01-01

Accessibility is a fundamental requirement in public transport (PT) yet there exists little research on design for accessibility or inclusive design (ID) in this area. This paper sets out to discover what methods are used in the rail sector to achieve accessibility goals and to examine how far...... these methods deviate from user-centred and ID norms. Semi-structured interviews were conducted with nine rolling stock producers, operators and design consultancies. The purpose was to determine if ID design methods are used explicitly and the extent to which the processes used conformed to ID (if at all......). The research found that the role of users in the design process of manufacturers was limited and that compliance with industry standards was the dominant means to achieving accessibility goals. Design consultancies were willing to apply more user-centred design if the client requested it. Where operators were...

Rapid Co-optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

OpenAIRE

Hills, Gage; Zhang, Jie; Shulaker, Max Marcel; Wei, Hai; Lee, Chi-Shuen; Balasingam, Arjun; Wong, H. -S. Philip; Mitra, Subhasish

2015-01-01

Carbon nanotube field-effect transistors (CNFETs) are promising candidates for building energy-efficient digital systems at highly-scaled technology nodes. However, carbon nanotubes (CNTs) are inherently subject to variations that reduce circuit yield, increase susceptibility to noise, and severely degrade their anticipated energy and speed benefits. Joint exploration and optimization of CNT processing options and CNFET circuit design are required to overcome this outstanding challenge. Unfor...

Self-clocked sequential circuits: - a design example | Aghdasi ...

African Journals Online (AJOL)

This paper uses a design methodology for the State variable toggling through data driven clocks to implement a Direct Memory Access Controller (DMAC) as a design example. The design is simulated on software and also implemented using discrete hardware components. The methodology can be extended to parallel ...

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

Science.gov (United States)

Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

2015-11-01

We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80-120%, with respect to the designed bias currents.

Automatic Circuit Design and Optimization Using Modified PSO Algorithm

Directory of Open Access Journals (Sweden)

Subhash Patel

2016-04-01

Full Text Available In this work, we have proposed modified PSO algorithm based optimizer for automatic circuit design. The performance of the modified PSO algorithm is compared with two other evolutionary algorithms namely ABC algorithm and standard PSO algorithm by designing two stage CMOS operational amplifier and bulk driven OTA in 130nm technology. The results show the robustness of the proposed algorithm. With modified PSO algorithm, the average design error for two stage op-amp is only 0.054% in contrast to 3.04% for standard PSO algorithm and 5.45% for ABC algorithm. For bulk driven OTA, average design error is 1.32% with MPSO compared to 4.70% with ABC algorithm and 5.63% with standard PSO algorithm.

A circuit design for front-end read-out electronics of beam homogeneity measurement

International Nuclear Information System (INIS)

She Qianshun; Su Hong; Xu Zhiguo; Ma Xiaoli; Hu Zhengguo; Mao Ruishi; Xu Hushan

2011-01-01

It introduces a circuit design of beam homogeneity measurement for heavy ion beam in the monitoring needs, which convert multichannel weak current from 10 pA to 100 nA of the output of parallel plate avalanche counter (PPAC) for large area with sensitive two-dimensional position to voltage signal from -2 V to -20 mV by current-voltage-converter (IVC) circuit which composed of T-feedback resistor networks, combined with data acquisition and processing system realized the beam homogeneity measurement in heavy ion tumor therapy of the Institute of Modern Physics. Experiments have shown that the circuit with speed and high precision. This circuit can be used for read-out of the beam for the Multiwire Proportional Chamber, Faraday Cup and other weak current sources. (authors)

Conceptual design of a versatile radiation tolerant integrated signal conditioning circuit for resistive sensors

Energy Technology Data Exchange (ETDEWEB)

Leroux, P. [Katholieke Hogeschool Kempen, Kleinhoefstraat 4, B-2440 Geel (Belgium); Katholieke Universiteit Leuven, Dept. ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee (Belgium); SCK-CEN, Belgian Nuclear Research Centre, Boeretang 200, B-2400 Mol (Belgium); Sterckx, J. [Katholieke Hogeschool Kempen, Kleinhoefstraat 4, B-2440 Geel (Belgium); Van Uffelen, M.; Damiani, C. [Fusion 4 Energy, Ed. B3, c/Josep, no 2, Torres Diagonal Litoral, 08019 Barcelona (Spain)

2011-07-01

This paper presents the design of a radiation tolerant configurable discrete time CMOS signal conditioning circuit for use with resistive sensors like strain gauge pressure sensors. The circuit is intended to be used for remote handling in harsh environments in the International Thermonuclear Experimental fusion Reactor (ITER). The design features a 5 V differential preamplifier using a Correlated Double Sampling (CDS) architecture at a sample rate of 20 kHz and a 24 V discrete time post amplifier. The gain is digitally controllable between 27 and 400 in the preamplifier and between 1 and 8 in the post amplifier. The nominal input referred noise voltage is only 8.5 {mu}V while consuming only 1 mW. The circuit has a simulated radiation tolerance of more than 1 MGy. (authors)

Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

Science.gov (United States)

Aziz, Syed Mahfuzul; Sicard, Etienne; Ben Dhia, Sonia

2010-01-01

This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied…

Circuits and filters handbook

CERN Document Server

Chen, Wai-Kai

2003-01-01

A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi

An Improved Zero Potential Circuit for Readout of a Two-Dimensional Resistive Sensor Array.

Science.gov (United States)

Wu, Jian-Feng; Wang, Feng; Wang, Qi; Li, Jian-Qing; Song, Ai-Guo

2016-12-06

With one operational amplifier (op-amp) in negative feedback, the traditional zero potential circuit could access one element in the two-dimensional (2-D) resistive sensor array with the shared row-column fashion but it suffered from the crosstalk problem for the non-scanned elements' bypass currents, which were injected into array's non-scanned electrodes from zero potential. Firstly, for suppressing the crosstalk problem, we designed a novel improved zero potential circuit with one more op-amp in negative feedback to sample the total bypass current and calculate the precision resistance of the element being tested (EBT) with it. The improved setting non-scanned-electrode zero potential circuit (S-NSE-ZPC) was given as an example for analyzing and verifying the performance of the improved zero potential circuit. Secondly, in the S-NSE-ZPC and the improved S-NSE-ZPC, the effects of different parameters of the resistive sensor arrays and their readout circuits on the EBT's measurement accuracy were simulated with the NI Multisim 12. Thirdly, part features of the improved circuit were verified with the experiments of a prototype circuit. Followed, the results were discussed and the conclusions were given. The experiment results show that the improved circuit, though it requires one more op-amp, one more resistor and one more sampling channel, can access the EBT in the 2-D resistive sensor array more accurately.

Design and engineering of intracellular-metabolite-sensing/regulation gene circuits in Saccharomyces cerevisiae.

Science.gov (United States)

Wang, Meng; Li, Sijin; Zhao, Huimin

2016-01-01

The development of high-throughput phenotyping tools is lagging far behind the rapid advances of genotype generation methods. To bridge this gap, we report a new strategy for design, construction, and fine-tuning of intracellular-metabolite-sensing/regulation gene circuits by repurposing bacterial transcription factors and eukaryotic promoters. As proof of concept, we systematically investigated the design and engineering of bacterial repressor-based xylose-sensing/regulation gene circuits in Saccharomyces cerevisiae. We demonstrated that numerous properties, such as induction ratio and dose-response curve, can be fine-tuned at three different nodes, including repressor expression level, operator position, and operator sequence. By applying these gene circuits, we developed a cell sorting based, rapid and robust high-throughput screening method for xylose transporter engineering and obtained a sugar transporter HXT14 mutant with 6.5-fold improvement in xylose transportation capacity. This strategy should be generally applicable and highly useful for evolutionary engineering of proteins, pathways, and genomes in S. cerevisiae. © 2015 Wiley Periodicals, Inc.

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

International Nuclear Information System (INIS)

Yamada, Takahiro; Maezawa, Masaaki; Urano, Chiharu

2015-01-01

Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

Energy Technology Data Exchange (ETDEWEB)

Yamada, Takahiro, E-mail: yamada-takahiro@aist.go.jp [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Maezawa, Masaaki [Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology, Central 2, Umezono 1-1-1, Tsukuba, Ibaraki 305-8568 (Japan); Urano, Chiharu [National Metrology Institute of Japan, National Institute of Advanced Industrial Science and Technology, Central 3, Umezono 1-1-1, Tsukuba, Ibaraki 305-8563 (Japan)

2015-11-15

Highlights: • We demonstrated RSFQ digital components of a new quantum voltage noise source. • A pseudo-random number generator and variable pulse number multiplier are designed. • Fabrication process is based on four Nb wiring layers and Nb/AlOx/Nb junctions. • The circuits successfully operated with wide dc bias current margins, 80–120%. - Abstract: We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33 mA for the PRNG, and 1677 junctions and 218 mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

Design of chaotic analog noise generators with logistic map and MOS QT circuits

International Nuclear Information System (INIS)

Vazquez-Medina, R.; Diaz-Mendez, A.; Rio-Correa, J.L. del; Lopez-Hernandez, J.

2009-01-01

In this paper a method to design chaotic analog noise generators using MOS transistors is presented. Two aspects are considered, the determination of operation regime of the MOS circuit and the statistical distribution of its output signal. The operation regime is related with the transconductance linear (TL: translinear) principle. For MOS transistors this principle was originally formulated in weak inversion regime; but, strong inversion regimen is used because in 1991, Seevinck and Wiegerink made the generalization for this principle. The statistical distribution of the output signal on the circuit, which should be a uniform distribution, is related with the parameter value that rules the transfer function of the circuit, the initial condition (seed) in the circuit and its operation as chaotic generator. To show these concepts, the MOS Quadratic Translinear circuit proposed by Wiegerink in 1993 was selected and it is related with the logistic map and its properties. This circuit will operate as noise generator if it works in strong inversion regime using current-mode approach when the parameter that rules the transfer function is higher than the onset chaos value (3.5699456...) for the logistic map.

Bridging ultrahigh-Q devices and photonic circuits

Science.gov (United States)

Yang, Ki Youl; Oh, Dong Yoon; Lee, Seung Hoon; Yang, Qi-Fan; Yi, Xu; Shen, Boqiang; Wang, Heming; Vahala, Kerry

2018-05-01

Optical microresonators are essential to a broad range of technologies and scientific disciplines. However, many of their applications rely on discrete devices to attain challenging combinations of ultra-low-loss performance (ultrahigh Q) and resonator design requirements. This prevents access to scalable fabrication methods for photonic integration and lithographic feature control. Indeed, finding a microfabrication bridge that connects ultrahigh-Q device functions with photonic circuits is a priority of the microcavity field. Here, an integrated resonator having a record Q factor over 200 million is presented. Its ultra-low-loss and flexible cavity design brings performance to integrated systems that has been the exclusive domain of discrete silica and crystalline microcavity devices. Two distinctly different devices are demonstrated: soliton sources with electronic repetition rates and high-coherence/low-threshold Brillouin lasers. This multi-device capability and performance from a single integrated cavity platform represents a critical advance for future photonic circuits and systems.

Analysis and design of elementary MOS amplifier stages

CERN Document Server

Murmann, Boris

2013-01-01

Analog integrated circuit (IC) design is often viewed as a “black art,” accessible only to those with special talent or years of experience. As an attempt to disprove this stereotype, this book was written to provide a customized introduction for the beginner with a minimum amount of prerequisite knowledge. Specifically, the material is positioned to fill the gap between general introductions on analog circuits, which are usually centered on discrete (printed circuit board) components, and advanced graduate books on integrated circuits. The need for filling the gap between these two types of texts has become stronger over the past decade for several reasons. The first is that advanced material has become less accessible for the inexperienced learner due to the growing complexity associated with the state-of-the-art. A second reason is that today’s typical intro course sequence has been expanded to include embedded system design; this leaves very little time to cover analog circuit principles at a level...

Robust parameter design for integrated circuit fabrication procedure with respect to categorical characteristic

International Nuclear Information System (INIS)

Sohn, S.Y.

1999-01-01

We consider a robust parameter design of the process for forming contact windows in complementary metal-oxide semiconductor circuits. Robust design is often used to find the optimal levels of process conditions which would provide the output of consistent quality as close to a target value. In this paper, we analyze the results of the fractional factorial design of nine factors: mask dimension, viscosity, bake temperature, spin speed, bake time, aperture, exposure time, developing time, etch time, where the outcome of the experiment is measured in terms of a categorized window size with five categories. Random effect analysis is employed to model both the mean and variance of categorized window size as functions of some controllable factors as well as random errors. Empirical Bayes' procedures are then utilized to fit both the models, and to eventually find the robust design of CMOS circuit process by means of a Bootstrap resampling approach

Design of Strain-Compensated Epitaxial Layers Using an Electrical Circuit Model

Science.gov (United States)

Kujofsa, Tedi; Ayers, John E.

2017-12-01

The design of heterostructures that exhibit desired strain characteristics is critical for the realization of semiconductor devices with improved performance and reliability. The control of strain and dislocation dynamics requires an understanding of the relaxation processes associated with mismatched epitaxy, and the starting point for this analysis is the equilibrium strain profile, because the difference between the actual strain and the equilibrium value determines the driving force for dislocation glide and relaxation. Previously, we developed an electrical circuit model approach for the equilibrium analysis of semiconductor heterostructures, in which an epitaxial layer may be represented by a stack of subcircuits, each of which involves an independent current source, a resistor, an independent voltage source, and an ideal diode. In this work, we have applied the electrical circuit model to study the strain compensation mechanism and show that, for a given compositionally uniform device layer with fixed mismatch and layer thickness, a buffer layer may be designed (in terms of thickness and mismatch) to tailor the strain in the device layer. A special case is that in which the device layer will exhibit zero residual strain in equilibrium (complete strain compensation). In addition, the application of the electrical circuit analogy enables the determination of exact expressions for the residual strain characteristics of both the buffer and device layers in the general case where the device layer may exhibit partial strain compensation. On the basis of this framework, it is possible to develop design equations for the tailoring of the strain in a device layer grown on a uniform composition buffer.

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

Science.gov (United States)

Gupta, Neha; Parihar, Priyanka; Neema, Vaibhav

2018-04-01

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DECODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.

Design and characterization of radiation resistant integrated circuits for the LHC particle detectors using deep sub-micron CMOS technologies

International Nuclear Information System (INIS)

Anelli, Giovanni Maria

2000-01-01

The electronic circuits associated with the particle detectors of the CERN Large Hadron Collider (LHC) have to work in a highly radioactive environment. This work proposes a methodology allowing the design of radiation resistant integrated circuits using the commercial sub-micron CMOS technology. This method uses the intrinsic radiation resistance of ultra-thin grid oxides, the technology of enclosed layout transistors (ELT), and the protection rings to avoid the radio-induced creation of leakage currents. In order to check the radiation tolerance level, several test structures have been designed and tested with different radiation sources. These tests have permitted to study the physical phenomena responsible for the damages induced by the radiations and the possible remedies. Then, the particular characteristics of ELT transistors and their influence on the design of complex integrated circuits has been explored. The modeling of the W/L ratio, the asymmetries (for instance in the output conductance) and the performance of ELT couplings have never been studied yet. The noise performance of the 0.25 μ CMOS technology, used in the design of several integrated circuits of the LHC detectors, has been characterized before and after irradiation. Finally, two integrated circuits designed using the proposed method are presented. The first one is an analogic memory and the other is a circuit used for the reading of the signals of one of the LHC detectors. Both circuits were irradiated and have endured very high doses practically without any sign of performance degradation. (J.S.)

A new design approach for control circuits of pipelined single-flux-quantum microprocessors

International Nuclear Information System (INIS)

Yamanashi, Y; Akimoto, A; Yoshikawa, N; Tanaka, M; Kawamoto, T; Kamiya, Y; Fujimaki, A; Terai, H; Yorozu, S

2006-01-01

A novel method of design for controllers of pipelined microprocessors using single-flux-quantum (SFQ) logic has been proposed. The proposed design approach is based on one hot encoding and is very suitable for designing a finite state machine using SFQ logic circuits, where each internal state of the microprocessor is represented by a flip-flop. In this approach, decoding of the internal state can be performed instantaneously, in contrast to the case in the conventional method using a binary state register. Moreover, pipelining is effectively implemented without increasing the circuit size because no pipeline registers are required in the one hot encoding. By using this method, we have designed a controller for our new SFQ microprocessors, which employs pipelining. The number of Josephson junctions of the newly designed controller is 1067, while the previous version without pipelining contains 1721 Josephson junctions. These results indicate that the proposed design approach is very effective for pipelined SFQ microprocessors. We have implemented a new controller using the NEC 2.5 kA cm -2 Nb standard process and confirmed its correct operation experimentally

Digital circuit boards mach 1 GHz

CERN Document Server

Morrison, Ralph

2012-01-01

A unique, practical approach to the design of high-speed digital circuit boards The demand for ever-faster digital circuit designs is beginning to render the circuit theory used by engineers ineffective. Digital Circuit Boards presents an alternative to the circuit theory approach, emphasizing energy flow rather than just signal interconnection to explain logic circuit behavior. The book shows how treating design in terms of transmission lines will ensure that the logic will function, addressing both storage and movement of electrical energy on these lines. It cove

A Sequential Circuit-Based IP Watermarking Algorithm for Multiple Scan Chains in Design-for-Test

Directory of Open Access Journals (Sweden)

C. Wu

2011-06-01

Full Text Available In Very Large Scale Integrated Circuits (VLSI design, the existing Design-for-Test(DFT based watermarking techniques usually insert watermark through reordering scan cells, which causes large resource overhead, low security and coverage rate of watermark detection. A novel scheme was proposed to watermark multiple scan chains in DFT for solving the problems. The proposed scheme adopts DFT scan test model of VLSI design, and uses a Linear Feedback Shift Register (LFSR for pseudo random test vector generation. All of the test vectors are shifted in scan input for the construction of multiple scan chains with minimum correlation. Specific registers in multiple scan chains will be changed by the watermark circuit for watermarking the design. The watermark can be effectively detected without interference with normal function of the circuit, even after the chip is packaged. The experimental results on several ISCAS benchmarks show that the proposed scheme has lower resource overhead, probability of coincidence and higher coverage rate of watermark detection by comparing with the existing methods.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

Science.gov (United States)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

Chemical sensors fabricated by a photonic integrated circuit foundry

Science.gov (United States)

Stievater, Todd H.; Koo, Kee; Tyndall, Nathan F.; Holmstrom, Scott A.; Kozak, Dmitry A.; Goetz, Peter G.; McGill, R. Andrew; Pruessner, Marcel W.

2018-02-01

We describe the detection of trace concentrations of chemical agents using waveguide-enhanced Raman spectroscopy in a photonic integrated circuit fabricated by AIM Photonics. The photonic integrated circuit is based on a five-centimeter long silicon nitride waveguide with a trench etched in the top cladding to allow access to the evanescent field of the propagating mode by analyte molecules. This waveguide transducer is coated with a sorbent polymer to enhance detection sensitivity and placed between low-loss edge couplers. The photonic integrated circuit is laid-out using the AIM Photonics Process Design Kit and fabricated on a Multi-Project Wafer. We detect chemical warfare agent simulants at sub parts-per-million levels in times of less than a minute. We also discuss anticipated improvements in the level of integration for photonic chemical sensors, as well as existing challenges.

Learning Abstract Physical Concepts from Experience: Design and Use of an RC Circuit

Science.gov (United States)

Parra, Alfredo; Ordenes, Jorge; de la Fuente, Milton

2018-05-01

Science learning for undergraduate students requires grasping a great number of theoretical concepts in a rather short time. In our experience, this is especially difficult when students are required to simultaneously use abstract concepts, mathematical reasoning, and graphical analysis, such as occurs when learning about RC circuits. We present a simple experimental model in this work that allows students to easily design, build, and analyze RC circuits, thus providing an opportunity to test personal ideas, build graphical descriptions, and explore the meaning of the respective mathematical models, ultimately gaining a better grasp of the concepts involved. The result suggests that the simple setup indeed helps untrained students to visualize the essential points of this kind of circuit.

Robust parameter design for integrated circuit fabrication procedure with respect to categorical characteristic

Energy Technology Data Exchange (ETDEWEB)

Sohn, S.Y

1999-12-01

We consider a robust parameter design of the process for forming contact windows in complementary metal-oxide semiconductor circuits. Robust design is often used to find the optimal levels of process conditions which would provide the output of consistent quality as close to a target value. In this paper, we analyze the results of the fractional factorial design of nine factors: mask dimension, viscosity, bake temperature, spin speed, bake time, aperture, exposure time, developing time, etch time, where the outcome of the experiment is measured in terms of a categorized window size with five categories. Random effect analysis is employed to model both the mean and variance of categorized window size as functions of some controllable factors as well as random errors. Empirical Bayes' procedures are then utilized to fit both the models, and to eventually find the robust design of CMOS circuit process by means of a Bootstrap resampling approach.

Beyond access: a case study on the intersection between accessibility, sustainability, and universal design.

Science.gov (United States)

Gossett, Andrea; Mirza, Mansha; Barnds, Ann Kathleen; Feidt, Daisy

2009-11-01

A growing emphasis has been placed on providing equal opportunities for all people, particularly people with disabilities, to support participation. Barriers to participation are represented in part by physical space restrictions. This article explores the decision-making process during the construction of a new office building housing a disability-rights organization. The building project featured in this study was developed on the principles of universal design, maximal accessibility, and sustainability to support access and participation. A qualitative case study approach was used involving collection of data through in-depth interviews with key decision-makers; non-participant observations at design meetings; and on-site tours. Qualitative thematic analysis along with the development of a classification system was used to understand specific building elements and the relevant decision processes from which they resulted. Recording and analyzing the design process revealed several key issues including grassroots involvement of stakeholders; interaction between universal design and sustainable design; addressing diversity through flexibility and universality; and segregationist accessibility versus universal design. This case study revealed complex interactions between accessibility, universal design, and sustainability. Two visual models were proposed to understand and analyze these complexities.

Design on Hygrometry System of Primary Coolant Circuit of HTR-PM

International Nuclear Information System (INIS)

Sun Yanfei; Zhong Shuoping; Huang Xiaojin

2014-01-01

Helium is the primary coolant in HTR-PM. If vapor get into the helium in primary coolant circuit because of some special reasons, such as the broken of steam-generator tube, chemical reaction will take effect between the graphite in reactor core and vapor in primary coolant circuit, and the safety of the reactor operation will be influenced. So the humidity of the helium in primary coolant circuit is one key parameter of HTR-PM to be monitored in-line. Once the humidity is too high, trigger signal of turning off the reactor must be issued. The hygrometry system of HTR-PM is consisting of filter, cooler, hygrometry sensor, flow meter, and some valves and tube. Helium with temperature of 250℃ is lead into the hygrometry system from the outlet of the main helium blower. After measuring, the helium is re-injected back to the primary circuit. No helium loses in this processing, and no other pump is needed. Key factors and calculations in design on hygrometry system of HTR-PM are described. A sample instrument has been made. Results of experiments proves that this hygrometry system is suitable for monitoring the humidity of the primary coolant of HTR-PM. (author)

An Improved Zero Potential Circuit for Readout of a Two-Dimensional Resistive Sensor Array

Directory of Open Access Journals (Sweden)

Jian-Feng Wu

2016-12-01

Full Text Available With one operational amplifier (op-amp in negative feedback, the traditional zero potential circuit could access one element in the two-dimensional (2-D resistive sensor array with the shared row-column fashion but it suffered from the crosstalk problem for the non-scanned elements’ bypass currents, which were injected into array’s non-scanned electrodes from zero potential. Firstly, for suppressing the crosstalk problem, we designed a novel improved zero potential circuit with one more op-amp in negative feedback to sample the total bypass current and calculate the precision resistance of the element being tested (EBT with it. The improved setting non-scanned-electrode zero potential circuit (S-NSE-ZPC was given as an example for analyzing and verifying the performance of the improved zero potential circuit. Secondly, in the S-NSE-ZPC and the improved S-NSE-ZPC, the effects of different parameters of the resistive sensor arrays and their readout circuits on the EBT’s measurement accuracy were simulated with the NI Multisim 12. Thirdly, part features of the improved circuit were verified with the experiments of a prototype circuit. Followed, the results were discussed and the conclusions were given. The experiment results show that the improved circuit, though it requires one more op-amp, one more resistor and one more sampling channel, can access the EBT in the 2-D resistive sensor array more accurately.

Analysis and Evaluation of Statistical Models for Integrated Circuits Design

Directory of Open Access Journals (Sweden)

Sáenz-Noval J.J.

2011-10-01

Full Text Available Statistical models for integrated circuits (IC allow us to estimate the percentage of acceptable devices in the batch before fabrication. Actually, Pelgrom is the statistical model most accepted in the industry; however it was derived from a micrometer technology, which does not guarantee reliability in nanometric manufacturing processes. This work considers three of the most relevant statistical models in the industry and evaluates their limitations and advantages in analog design, so that the designer has a better criterion to make a choice. Moreover, it shows how several statistical models can be used for each one of the stages and design purposes.

Analysis and design of a genetic circuit for dynamic metabolic engineering.

Science.gov (United States)

Anesiadis, Nikolaos; Kobayashi, Hideki; Cluett, William R; Mahadevan, Radhakrishnan

2013-08-16

Recent advances in synthetic biology have equipped us with new tools for bioprocess optimization at the genetic level. Previously, we have presented an integrated in silico design for the dynamic control of gene expression based on a density-sensing unit and a genetic toggle switch. In the present paper, analysis of a serine-producing Escherichia coli mutant shows that an instantaneous ON-OFF switch leads to a maximum theoretical productivity improvement of 29.6% compared to the mutant. To further the design, global sensitivity analysis is applied here to a mathematical model of serine production in E. coli coupled with a genetic circuit. The model of the quorum sensing and the toggle switch involves 13 parameters of which 3 are identified as having a significant effect on serine concentration. Simulations conducted in this reduced parameter space further identified the optimal ranges for these 3 key parameters to achieve productivity values close to the maximum theoretical values. This analysis can now be used to guide the experimental implementation of a dynamic metabolic engineering strategy and reduce the time required to design the genetic circuit components.

Analog Integrated Circuit Design for Spike Time Dependent Encoder and Reservoir in Reservoir Computing Processors

Science.gov (United States)

2018-01-01

HAS BEEN REVIEWED AND IS APPROVED FOR PUBLICATION IN ACCORDANCE WITH ASSIGNED DISTRIBUTION STATEMENT. FOR THE CHIEF ENGINEER : / S / / S...bridged high-performance computing, nanotechnology , and integrated circuits & systems. 15. SUBJECT TERMS neuromorphic computing, neuron design, spike...multidisciplinary effort encompassed high-performance computing, nanotechnology , integrated circuits, and integrated systems. The project’s architecture was

Comparative study of electromagnetic compatibility methods in printed circuit board design tools

International Nuclear Information System (INIS)

Marinova, Galia

2002-01-01

The paper considers the state-of-the art in electromagnetic compatibility (EMC) oriented printed circuit board (PCB) design. A general methodology of EMC oriented PCB design is synthesized. The main CAD tools available today are estimated and compared for their abilities to treat EMC oriented design. To help non experts a knowledge-base containing more than 50 basic rules for EMC-oriented PCB design is proposed. It can be applied in the PCB design CAD tools that possess rule-builders or it can help interactive design. Trends in this area of EMC-oriented PCB design are deduced. (Author)

Memristor Circuits and Systems

KAUST Repository

Zidan, Mohammed A.

2015-05-01

Current CMOS-based technologies are facing design challenges related to the continuous scaling down of the minimum feature size, according to Moore’s law. Moreover, conventional computing architecture is no longer an effective way of fulfilling modern applications demands, such as big data analysis, pattern recognition, and vector processing. Therefore, there is an exigent need to shift to new technologies, at both the architecture and the device levels. Recently, memristor devices and structures attracted attention for being promising candidates for this job. Memristor device adds a new dimension for designing novel circuits and systems. In addition, high-density memristor-based crossbar is widely considered to be the essential element for future memory and bio-inspired computing systems. However, numerous challenges need to be addressed before the memristor genuinely replaces current memory and computing technologies, which is the motivation behind this research effort. In order to address the technology challenges, we begin by fabricating and modeling the memristor device. The devices fabricated at our local clean room enriched our understanding of the memristive phenomenon and enabled the experimental testing for our memristor-based circuits. Moreover, our proposed mathematical modeling for memristor behavior is an essential element for the theoretical circuit design stage. Designing and addressing the challenges of memristor systems with practical complexity, however, requires an extra step, which takes the form of a reliable and modular simulation platform. We, therefore, built a new simulation platform for the resistive crossbar, which can simulate realistic size arrays filled with real memory data. In addition, this simulation platform includes various crossbar nonidealities in order to obtain accurate simulation results. Consequently, we were able to address the significant challenges facing the high density memristor crossbar, as the building block for

High School Student Information Access and Engineering Design Performance

Science.gov (United States)

Mentzer, Nathan

2014-01-01

Developing solutions to engineering design problems requires access to information. Research has shown that appropriately accessing and using information in the design process improves solution quality. This quasi-experimental study provides two groups of high school students with a design problem in a three hour design experience. One group has…

Design of a 300-Watt Isolated Power Supply with Minimized Circuit Input-to-Output Parasitic Capacitance

DEFF Research Database (Denmark)

Nguyen-Duy, Khiem; Petersen, Lars Press; Knott, Arnold

2014-01-01

This paper presents the design of a 300-Watt isolated power supply for MOS gate driver circuit in medium and high voltage applications. The key feature of the developed power supply is having a very low circuit input-to-output parasitic capacitance, thus maximizing its noise immunity. This makes...

Design and application of multilayer monolithic microwave integrated circuit transformers

Energy Technology Data Exchange (ETDEWEB)

Economides, S.B

1999-07-01

The design and performance of planar spiral transformers, using multilayer GaAs and silicon MMIC technology, are presented. This multilayer technology gives new opportunities for improving the performance of planar transformers, couplers and baluns. Planar transformers have high parasitic resistance and capacitance and low levels of coupling. Using multilayer technology these problems are overcome by applying a multilayer structure of three metal layers separated by two polyimide dielectric layers. The improvements gained by placing the conductors on different metal layers, and using conductors raised on polyimide layers for low capacitance, have been investigated. The circuits were fabricated using a novel experimental fabrication process, which uses entirely standard materials and techniques and is compatible with BJT's and silicon-germanium HBT's. The transformers were all characterised up to 20 GHz using RF-on-wafer measurements. They demonstrated good performance, considering the experimental nature of in-house multilayer technology and the difficulties in simulating these three-dimensional new geometries. With high resistivity substrates, the silicon components achieved virtually the same performance as their gallium arsenide counterparts. The transformers were then used in simulations of transformer-coupled HBT amplifier circuits, to demonstrate their capabilities. It was shown that these circuits present good performance compared to standard off-the shelf component circuits and are very promising for use in most multilayer MMIC applications. The structures were further used in coupling configurations, and applied in balun circuits and pushpull amplifiers. The spiral transformer coupler can operate at low frequencies without using up much chip area. In a balun configuration, the balun can compensate for coupling and phase imbalance and operates over 5 to 15 GHz. The spiral coupler does not always need multilayer processing, so the balun may be

Principles of transistor circuits introduction to the design of amplifiers, receivers and digital circuits

CERN Document Server

Amos, S W

2013-01-01

Principles of Transistor Circuits: Sixth Edition discusses the principles, concepts, and practices involved integrated circuits. The current edition includes up-to-date circuits, the section on thyristors has been revised to give more information on modern types, and dated information has been eliminated. The book covers related topics such as semiconductors and junction diodes; the principles behind transistors; and common amplifiers. The book also covers bias and DC stabilization; large-signal and small-signal AF amplifiers; DC and pulse amplifiers; sinusoidal oscillators; pulse and sawtooth

A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

International Nuclear Information System (INIS)

Quinn, Heather M.; Graham, Paul S.; Morgan, Keith S.; Caffrey, Michael P.

2008-01-01

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID: Device and Circuit Co-Design

Directory of Open Access Journals (Sweden)

Tony T. Kim

2011-07-01

Full Text Available Recently, double-gate MOSFETs (DGMOSFETs have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.

Mechanical Designs for Inorganic Stretchable Circuits in Soft Electronics.

Science.gov (United States)

Wang, Shuodao; Huang, Yonggang; Rogers, John A

2015-09-01

Mechanical concepts and designs in inorganic circuits for different levels of stretchability are reviewed in this paper, through discussions of the underlying mechanics and material theories, fabrication procedures for the constituent microscale/nanoscale devices, and experimental characterization. All of the designs reported here adopt heterogeneous structures of rigid and brittle inorganic materials on soft and elastic elastomeric substrates, with mechanical design layouts that isolate large deformations to the elastomer, thereby avoiding potentially destructive plastic strains in the brittle materials. The overall stiffnesses of the electronics, their stretchability, and curvilinear shapes can be designed to match the mechanical properties of biological tissues. The result is a class of soft stretchable electronic systems that are compatible with traditional high-performance inorganic semiconductor technologies. These systems afford promising options for applications in portable biomedical and health-monitoring devices. Mechanics theories and modeling play a key role in understanding the underlining physics and optimization of these systems.

Generating and checking control logic in the HDL-based design of reversible circuits

DEFF Research Database (Denmark)

Wille, Robert; Keszocze, Oliver; Othmer, Lars

2017-01-01

Although different from the conventional computing paradigm, reversible computation received significant interest due to its applications in various (emerging) technologies. Here, computations can be executed not only from the inputs to the outputs, but also in the reverse direction. This leads...... solution constitutes the first automatic method for these important designs steps in the domain of reversible circuit design....

A radiation-hardened 1K-bit dielectrically isolated random access memory

International Nuclear Information System (INIS)

Sandors, T.J.; Boarman, J.W.; Kasten, A.J.; Wood, G.M.

1982-01-01

Dielectric Isolation has been used for many years as the bipolar technology for latch-up free, radiation hardened integrated circuits in strategic systems. The state-of-the-art up to this point has been the manufacture of MSI functions containing a maximum of several hundred isolated components. This paper discusses a 1024 Bit Random Access Memory chip containing over 4000 dielectrically isolated components which has been designed for strategic radiation environments. The process utilized and the circuit design of the 1024 Bit RAM have been previously discussed. The techniques used are similar to those employed for the MX digital integrated circuits except for specific items required to make this a true LSI technology. These techniques, along with electrical and radiation data for the RAM, are presented

Dynamical Analysis, Synchronization, Circuit Design, and Secure Communication of a Novel Hyperchaotic System

Directory of Open Access Journals (Sweden)

Li Xiong

2017-01-01

Full Text Available This paper is devoted to introduce a novel fourth-order hyperchaotic system. The hyperchaotic system is constructed by adding a linear feedback control level based on a modified Lorenz-like chaotic circuit with reduced number of amplifiers. The local dynamical entities, such as the basic dynamical behavior, the divergence, the eigenvalue, and the Lyapunov exponents of the new hyperchaotic system, are all investigated analytically and numerically. Then, an active control method is derived to achieve global chaotic synchronization of the novel hyperchaotic system through making the synchronization error system asymptotically stable at the origin based on Lyapunov stability theory. Next, the proposed novel hyperchaotic system is applied to construct another new hyperchaotic system with circuit deformation and design a new hyperchaotic secure communication circuit. Furthermore, the implementation of two novel electronic circuits of the proposed hyperchaotic systems is presented, examined, and realized using physical components. A good qualitative agreement is shown between the simulations and the experimental results around 500 kHz and below 1 MHz.

VHDL-AMS Simulation Framework for Molecular-FET Device-to-Circuit Modeling and Design

Directory of Open Access Journals (Sweden)

Mariagrazia Graziano

2018-01-01

Full Text Available We concentrate on Molecular-FET as a device and present a new modular framework based on VHDL-AMS. We have implemented different Molecular-FET models within the framework. The framework allows comparison between the models in terms of the capability to calculate accurate I-V characteristics. It also provides the option to analyze the impact of Molecular-FET and its implementation in the circuit with the extension of its use in an architecture based on the crossbar configuration. This analysis evidences the effect of choices of technological parameters, the ability of models to capture the impact of physical quantities, and the importance of considering defects at circuit fabrication level. The comparison tackles the computational efforts of different models and techniques and discusses the trade-off between accuracy and performance as a function of the circuit analysis final requirements. We prove this methodology using three different models and test them on a 16-bit tree adder included in Pentium 4 that, to the best of our knowledge, is the biggest circuits based on molecular device ever designed and analyzed.

Channel Access Algorithm Design for Automatic Identification System

Institute of Scientific and Technical Information of China (English)

Oh Sang-heon; Kim Seung-pum; Hwang Dong-hwan; Park Chan-sik; Lee Sang-jeong

2003-01-01

The Automatic Identification System (AIS) is a maritime equipment to allow an efficient exchange of the navigational data between ships and between ships and shore stations. It utilizes a channel access algorithm which can quickly resolve conflicts without any intervention from control stations. In this paper, a design of channel access algorithm for the AIS is presented. The input/output relationship of each access algorithm module is defined by drawing the state transition diagram, dataflow diagram and flowchart based on the technical standard, ITU-R M.1371. In order to verify the designed channel access algorithm, the simulator was developed using the C/C++ programming language. The results show that the proposed channel access algorithm can properly allocate transmission slots and meet the operational performance requirements specified by the technical standard.

Electronic Circuit Analysis Language (ECAL)

Science.gov (United States)

Chenghang, C.

1983-03-01

The computer aided design technique is an important development in computer applications and it is an important component of computer science. The special language for electronic circuit analysis is the foundation of computer aided design or computer aided circuit analysis (abbreviated as CACD and CACA) of simulated circuits. Electronic circuit analysis language (ECAL) is a comparatively simple and easy to use circuit analysis special language which uses the FORTRAN language to carry out the explanatory executions. It is capable of conducting dc analysis, ac analysis, and transient analysis of a circuit. Futhermore, the results of the dc analysis can be used directly as the initial conditions for the ac and transient analyses.

Micro-relay technology for energy-efficient integrated circuits

CERN Document Server

Kam, Hei

2015-01-01

This book describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers and highlights the importance of co-design across design hierarchies when optimizing system performance (in this case, energy-efficiency). This book is ideal for researchers and engineers focused on semiconductors, integrated circuits, and energy efficient electronics. This book also: ·         Covers microsystem fabrication, MEMS device design, circuit design, circuit micro-architecture, and CAD ·         Describes work previously done in the field and also lays the groundwork and criteria for future energy-efficient device and system design ·         Maximizes reader insights into the design and modeling of micro-relay, micro-relay reliability, integrated circuit design with micro-relays, and more

Dynamic theory for the mesoscopic electric circuit

International Nuclear Information System (INIS)

Chen Bin; Shen Xiaojuan; Li Youquan; Sun LiLy; Yin Zhujian

2005-01-01

The quantum theory for mesoscopic electric circuit with charge discreteness is briefly described. The minibands of quasienergy in LC design mesoscopic electric circuit have been found. In the mesoscopic 'pure' inductance design circuit, just like in the mesoscopic metallic rings, the quantum dynamic characteristics have been obtained explicitly. In the 'pure' capacity design circuit, the Coulomb blockade had also been addressed

Design of a CMOS readout circuit on ultra-thin flexible silicon chip for printed strain gauges

Directory of Open Access Journals (Sweden)

M. Elsobky

2017-09-01

Full Text Available Flexible electronics represents an emerging technology with features enabling several new applications such as wearable electronics and bendable displays. Precise and high-performance sensors readout chips are crucial for high quality flexible electronic products. In this work, the design of a CMOS readout circuit for an array of printed strain gauges is presented. The ultra-thin readout chip and the printed sensors are combined on a thin Benzocyclobutene/Polyimide (BCB/PI substrate to form a Hybrid System-in-Foil (HySiF, which is used as an electronic skin for robotic applications. Each strain gauge utilizes a Wheatstone bridge circuit, where four Aerosol Jet® printed meander-shaped resistors form a full-bridge topology. The readout chip amplifies the output voltage difference (about 5 mV full-scale swing of the strain gauge. One challenge during the sensor interface circuit design is to compensate for the relatively large dc offset (about 30 mV at 1 mA in the bridge output voltage so that the amplified signal span matches the input range of an analog-to-digital converter (ADC. The circuit design uses the 0. 5 µm mixed-signal GATEFORESTTM technology. In order to achieve the mechanical flexibility, the chip fabrication is based on either back thinned wafers or the ChipFilmTM technology, which enables the manufacturing of silicon chips with a thickness of about 20 µm. The implemented readout chip uses a supply of 5 V and includes a 5-bit digital-to-analog converter (DAC, a differential difference amplifier (DDA, and a 10-bit successive approximation register (SAR ADC. The circuit is simulated across process, supply and temperature corners and the simulation results indicate excellent performance in terms of circuit stability and linearity.

Grounding and shielding circuits and interference

CERN Document Server

Morrison, Ralph

2016-01-01

Applies basic field behavior in circuit design and demonstrates how it relates to grounding and shielding requirements and techniques in circuit design This book connects the fundamentals of electromagnetic theory to the problems of interference in all types of electronic design. The text covers power distribution in facilities, mixing of analog and digital circuitry, circuit board layout at high clock rates, and meeting radiation and susceptibility standards. The author examines the grounding and shielding requirements and techniques in circuit design and applies basic physics to circuit behavior. The sixth edition of this book has been updated with new material added throughout the chapters where appropriate. The presentation of the book has also been rearranged in order to reflect the current trends in the field.

VLSI design

CERN Document Server

Chandrasetty, Vikram Arkalgud

2011-01-01

This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

Behavioral synthesis of asynchronous circuits

DEFF Research Database (Denmark)

Nielsen, Sune Fallgaard

2005-01-01

This thesis presents a method for behavioral synthesis of asynchronous circuits, which aims at providing a synthesis flow which uses and tranfers methods from synchronous circuits to asynchronous circuits. We move the synchronous behavioral synthesis abstraction into the asynchronous handshake...... is idle. This reduces unnecessary switching activity in the individual functional units and therefore the energy consumption of the entire circuit. A collection of behavioral synthesis algorithms have been developed allowing the designer to perform time and power constrained design space exploration...

Design and implementation of therapeutic ultrasound generating circuit for dental tissue formation and tooth-root healing.

Science.gov (United States)

Woon Tiong Ang; Scurtescu, C; Wing Hoy; El-Bialy, T; Ying Yin Tsui; Jie Chen

2010-02-01

Biological tissue healing has recently attracted a great deal of research interest in various medical fields. Trauma to teeth, deep and root caries, and orthodontic treatment can all lead to various degrees of root resorption. In our previous study, we showed that low-intensity pulsed ultrasound (LIPUS) enhances the growth of lower incisor apices and accelerates their rate of eruption in rabbits by inducing dental tissue growth. We also performed clinical studies and demonstrated that LIPUS facilitates the healing of orthodontically induced teeth-root resorption in humans. However, the available LIPUS devices are too large to be used comfortably inside the mouth. In this paper, the design and implementation of a low-power LIPUS generator is presented. The generator is the core of the final intraoral device for preventing tooth root loss and enhancing tooth root tissue healing. The generator consists of a power-supply subsystem, an ultrasonic transducer, an impedance-matching circuit, and an integrated circuit composed of a digital controller circuitry and the associated driver circuit. Most of our efforts focus on the design of the impedance-matching circuit and the integrated system-on-chip circuit. The chip was designed and fabricated using 0.8- ¿m high-voltage technology from Dalsa Semiconductor, Inc. The power supply subsystem and its impedance-matching network are implemented using discrete components. The LIPUS generator was tested and verified to function as designed and is capable of producing ultrasound power up to 100 mW in the vicinity of the transducer's resonance frequency at 1.5 MHz. The power efficiency of the circuitry, excluding the power supply subsystem, is estimated at 70%. The final products will be tailored to the exact size of teeth or biological tissue, which is needed to be used for stimulating dental tissue (dentine and cementum) healing.

Design and development of improved ballscrew and control circuit for reactivity mechanisms of 220 MWe PHWR operating stations

International Nuclear Information System (INIS)

Jain, A.K.; Rama Mohan, N.; Mathew, Jimmy; Mathur, M.K.; Roy, S.; Ingle, V.J.; Ghoshal, B.; Ashok Kumar, B.; Patil, D.C.; Dwivedi, K.P.; Bhambra, H.S.

2006-01-01

There has been persistent failure of Ballscrews used for Reactivity Mechanism in standardised 220 MWe PHWR units. The detailed review of failures indicated that on one hand the number of demands for operation of Absorber Rod and Regulating Rod had increased due to use of digital circuit in the drive control system as compared analog circuits used earlier. On the other hand, the existing design of ballscrew had some inherent weaknesses to withstand the loads generated during starting and stopping of the regulating rods. To solve these problems two-pronged approach was adopted. The control problem was traced to overshooting of the servomotor of Absorber Rod and Regulating Rod to the full speed at the time of starting and thereafter, settling to the required speed. This sudden overshooting produces a jerk in the drive mechanism. A modified circuit has been evolved to solve this problem. Also, Changing the dead band and gain of control circuits have reduced the number of rod movements. A 'new design' of Ballscrew assembly was finalised by NPCIL with a view to withstand the severe loads generated during starting and stopping of the regulating rods and to achieve enhanced service life under water-lubrication condition. Based on this design, prototype assemblies were successfully manufactured by two Indian manufacturers. The design was cleared for manufacturing of the bulk production of Ballscrew assemblies after evaluation of its performance during rigorous 'Acceptance Testing'. Two ballscrews of new design were installed in the KGS-1 reactor and are operating since July 2005. This paper covers operational feedback including ballscrew failures in various units, Design/Development of Modified Reactivity Mechanism Ballscrews and Control Circuit based on analysis of underlying causes of failures and feedback on performance of new design. (author)

Database design for Physical Access Control System for nuclear facilities

Energy Technology Data Exchange (ETDEWEB)

Sathishkumar, T., E-mail: satishkumart@igcar.gov.in; Rao, G. Prabhakara, E-mail: prg@igcar.gov.in; Arumugam, P., E-mail: aarmu@igcar.gov.in

2016-08-15

Highlights: • Database design needs to be optimized and highly efficient for real time operation. • It requires a many-to-many mapping between Employee table and Doors table. • This mapping typically contain thousands of records and redundant data. • Proposed novel database design reduces the redundancy and provides abstraction. • This design is incorporated with the access control system developed in-house. - Abstract: A (Radio Frequency IDentification) RFID cum Biometric based two level Access Control System (ACS) was designed and developed for providing access to vital areas of nuclear facilities. The system has got both hardware [Access controller] and software components [server application, the database and the web client software]. The database design proposed, enables grouping of the employees based on the hierarchy of the organization and the grouping of the doors based on Access Zones (AZ). This design also illustrates the mapping between the Employee Groups (EG) and AZ. By following this approach in database design, a higher level view can be presented to the system administrator abstracting the inner details of the individual entities and doors. This paper describes the novel approach carried out in designing the database of the ACS.

Database design for Physical Access Control System for nuclear facilities

International Nuclear Information System (INIS)

Sathishkumar, T.; Rao, G. Prabhakara; Arumugam, P.

2016-01-01

Highlights: • Database design needs to be optimized and highly efficient for real time operation. • It requires a many-to-many mapping between Employee table and Doors table. • This mapping typically contain thousands of records and redundant data. • Proposed novel database design reduces the redundancy and provides abstraction. • This design is incorporated with the access control system developed in-house. - Abstract: A (Radio Frequency IDentification) RFID cum Biometric based two level Access Control System (ACS) was designed and developed for providing access to vital areas of nuclear facilities. The system has got both hardware [Access controller] and software components [server application, the database and the web client software]. The database design proposed, enables grouping of the employees based on the hierarchy of the organization and the grouping of the doors based on Access Zones (AZ). This design also illustrates the mapping between the Employee Groups (EG) and AZ. By following this approach in database design, a higher level view can be presented to the system administrator abstracting the inner details of the individual entities and doors. This paper describes the novel approach carried out in designing the database of the ACS.

A design comparison of two kinds power circuit for personal dosimeter

International Nuclear Information System (INIS)

Deng Changming; Liu Zhengshan; Guo Zhanjie

2001-01-01

Personal dosimeter is commonly requested using battery for its power supply, and hope the battery life is long. Also with the fall of battery voltage, some performance of instrument as well as drop. Reasonable supply design can protract the battery life. The paper introduces two method: power supply with battery directly and supply used power chip conversion. Combine personal dosimeter, authors carried through the design comparison for battery life, power consumption, cost and volume. Based on the comparison result and instrument fact request, you can choose method of power circuit

Memristor-based nanoelectronic computing circuits and architectures

CERN Document Server

Vourkas, Ioannis

2016-01-01

This book considers the design and development of nanoelectronic computing circuits, systems and architectures focusing particularly on memristors, which represent one of today’s latest technology breakthroughs in nanoelectronics. The book studies, explores, and addresses the related challenges and proposes solutions for the smooth transition from conventional circuit technologies to emerging computing memristive nanotechnologies. Its content spans from fundamental device modeling to emerging storage system architectures and novel circuit design methodologies, targeting advanced non-conventional analog/digital massively parallel computational structures. Several new results on memristor modeling, memristive interconnections, logic circuit design, memory circuit architectures, computer arithmetic systems, simulation software tools, and applications of memristors in computing are presented. High-density memristive data storage combined with memristive circuit-design paradigms and computational tools applied t...

A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMS

KAUST Repository

Dadgour, Hamed F.

2010-01-01

Nano-Electro-Mechanical Switches (NEMS) offer the prospect of improved energy-efficiency in digital circuits due to their near-zero subthreshold leakage and extremely low subthreshold swing values. Among the different approaches of implementing NEMS, laterallyactuated double-gate NEMS devices have attracted much attention as they provide unique and exciting circuit design opportunities. For instance, this paper demonstrates that compact XOR/XNOR gates can be implemented using only two such NEMS transistors. While this in itself is a major improvement, its implications for minimizing Boolean functions using Karnaugh maps (K-maps) are even more significant. In the standard K-map technique, which is used in digital circuit design, adjacent "1s" (minterms) are grouped only in horizontal and/or vertical directions; the diagonal (or zig-zag) grouping of adjacent "1s" is not an option due to the absence of compact XOR/XNOR gates. However, this work demonstrates, for the first time ever, that in lateral double-gate NEMS-based circuits, grouping of minterms is possible in horizontal and vertical as well as diagonal fashions. This is because the diagonal groupings of minterms require XOR/XNOR operations, which are available in such NEMS-based circuits at minimal costs. This novel design paradigm facilitates more compact implementations of Boolean functions and thus, considerably improves their energy-efficiency. For example, a lateral NEMS-based full-adder is implemented using less than half the number of transistors, which is required by a CMOS-based full-adder. Furthermore, circuit simulations are performed to evaluate the energy-efficiencies of the NEMS-based 32-bit carry-save adders compared to their standard CMOS-based counterparts. Copyright 2010 ACM.

Timergenerator circuits manual

CERN Document Server

Marston, R M

2013-01-01

Timer/Generator Circuits Manual is an 11-chapter text that deals mainly with waveform generator techniques and circuits. Each chapter starts with an explanation of the basic principles of its subject followed by a wide range of practical circuit designs. This work presents a total of over 300 practical circuits, diagrams, and tables.Chapter 1 outlines the basic principles and the different types of generator. Chapters 2 to 9 deal with a specific type of waveform generator, including sine, square, triangular, sawtooth, and special waveform generators pulse. These chapters also include pulse gen

Design and demonstration of adiabatic quantum-flux-parametron logic circuits with superconductor magnetic shields

International Nuclear Information System (INIS)

Inoue, Kenta; Narama, Tatsuya; Yamanashi, Yuki; Yoshikawa, Nobuyuki; Takeuchi, Naoki

2015-01-01

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic with zero static power and very small dynamic power due to adiabatic switching operations. In order to build large-scale digital circuits, we built AQFP logic cells using superconductor magnetic shields, which are necessary in order to avoid unwanted magnetic couplings between the cells and excitation currents. In preliminary experimental tests, we confirmed that the unwanted coupling became negligibly small thanks to the superconductor shields. As a demonstration, we designed a four-to-one multiplexor and a 16-junction full adder using the shielded logic cells. In both circuits, we confirmed correct logic operations with wide operation margins of excitation currents. These results indicate that large-scale AQFP digital circuits can be realized using the shielded logic cells. (paper)

Design of a High Performance Green-Mode PWM Controller IC with Smart Sensing Protection Circuits

Directory of Open Access Journals (Sweden)

Shen-Li Chen

2014-08-01

Full Text Available A design of high performance green-mode pulse-width-modulation (PWM controller IC with smart sensing protection circuits for the application of lithium-ion battery charger (1.52 V ~ 7.5 V is investigated in this paper. The protection circuits architecture of this system mainly bases on the lithium battery function and does for the system design standard of control circuit. In this work, the PWM controller will be with an automatic load sensing and judges the system operated in the operating mode or in the standby mode. Therefore, it reduces system’s power dissipation effectively and achieves the saving power target. In the same time, many protection sensing circuits such as: (1 over current protection (OCP and under current protection (UCP, (2 over voltage protection (OVP and under voltage protection (UVP, (3 loading determintion and short circuit protection (SCP, (4 over temperature protection (OTP, (5 VDD surge-spiking protection are included. Then, it has the characteristics of an effective monitoring the output loading and the harm prevention as a battery charging. Eventually, this green-mode pulse-width-modulation (PWM controller IC will be that the operation voltage is 3.3 V, the operation frequency is 0.98 MHz, and the output current range is from 454 mA to 500 mA. Meanwhile, the output convert efficiency is range from 74.8 % to 91 %, the power dissipation efficiency in green-mode is 25 %, and the operation temperature range is between -20 0C ~ 114 0C.

Synthesis of logic circuits with evolutionary algorithms

Energy Technology Data Exchange (ETDEWEB)

JONES,JAKE S.; DAVIDSON,GEORGE S.

2000-01-26

In the last decade there has been interest and research in the area of designing circuits with genetic algorithms, evolutionary algorithms, and genetic programming. However, the ability to design circuits of the size and complexity required by modern engineering design problems, simply by specifying required outputs for given inputs has as yet eluded researchers. This paper describes current research in the area of designing logic circuits using an evolutionary algorithm. The goal of the research is to improve the effectiveness of this method and make it a practical aid for design engineers. A novel method of implementing the algorithm is introduced, and results are presented for various multiprocessing systems. In addition to evolving standard arithmetic circuits, work in the area of evolving circuits that perform digital signal processing tasks is described.

Analog Integrated Circuit and System Design for a Compact, Low-Power Cochlear Implant

NARCIS (Netherlands)

Ngamkham, W.

2015-01-01

Cochlear Implants (CIs) are prosthetic devices that restore hearing in profoundly deaf patients by bypassing the damaged parts of the inner ear and directly stimulating the remaining auditory nerve fibers in the cochlea with electrical pulses. This thesis describs the electronic circuit design of

Toolbox for the design of LiNbO3-based passive and active integrated quantum circuits

Science.gov (United States)

Sharapova, P. R.; Luo, K. H.; Herrmann, H.; Reichelt, M.; Meier, T.; Silberhorn, C.

2017-12-01

We present and discuss perspectives of current developments on advanced quantum optical circuits monolithically integrated in the lithium niobate platform. A set of basic components comprising photon pair sources based on parametric down conversion (PDC), passive routing elements and active electro-optically controllable switches and polarisation converters are building blocks of a toolbox which is the basis for a broad range of diverse quantum circuits. We review the state-of-the-art of these components and provide models that properly describe their performance in quantum circuits. As an example for applications of these models we discuss design issues for a circuit providing on-chip two-photon interference. The circuit comprises a PDC section for photon pair generation followed by an actively controllable modified mach-Zehnder structure for observing Hong-Ou-Mandel interference. The performance of such a chip is simulated theoretically by taking even imperfections of the properties of the individual components into account.

Statistical delay estimation in digital circuits using VHDL

Directory of Open Access Journals (Sweden)

Milić Miljana Lj.

2014-01-01

Full Text Available The most important feature of modern integrated circuit is the speed. It depends on circuit's delay. For the design of high-speed digital circuits, it is necessary to evaluate delays in the earliest stages of design, thus making it easy to modify and redesign a circuit if it's too slow. This paper gives an approach for efficient delay estimation in the describing phase of the circuit design. The method can statistically estimate the minimum and maximum delay of all possible paths and signal transitions in the circuit, considering the practical implementation of circuits, and information about the parameters' tolerances. The method uses a VHDL description and is verified on ISCAS85 benchmark circuits. Matlab was used for data processing.

A design concept for an MMIC (Monolithic Microwave Integrated Circuit) microstrip phased array

Science.gov (United States)

Lee, Richard Q.; Smetana, Jerry; Acosta, Roberto

1987-01-01

A conceptual design for a microstrip phased array with monolithic microwave integrated circuit (MMIC) amplitude and phase controls is described. The MMIC devices used are 20 GHz variable power amplifiers and variable phase shifters recently developed by NASA contractors for applications in future Ka proposed design, which concept is for a general NxN element array of rectangular lattice geometry. Subarray excitation is incorporated in the MMIC phased array design to reduce the complexity of the beam forming network and the number of MMIC components required.

Pulsewidth modulated DC-to-DC power conversion circuits, dynamics, and control designs

CERN Document Server

Choi, Byungcho

2013-01-01

This is the definitive reference for anyone involved in pulsewidth modulated DC-to-DC power conversion Pulsewidth Modulated DC-to-DC Power Conversion: Circuits, Dynamics, and Control Designs provides engineers, researchers, and students in the power electronics field with comprehensive and complete guidance to understanding pulsewidth modulated (PWM) DC-to-DC power converters. Presented in three parts, the book addresses the circuitry and operation of PWM DC-to-DC converters and their dynamic characteristics, along with in-depth discussions of control design of PWM DC-to

Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits

International Nuclear Information System (INIS)

Nishigai, T.; Ito, M.; Yoshikawa, N.; Fujimaki, A.; Terai, H.; Yorozu, S.

2005-01-01

We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10 ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10 ps

Equivalent circuit and optimum design of a multilayer laminated piezoelectric transformer.

Science.gov (United States)

Dong, Shuxiang; Carazo, Alfredo Vazquez; Park, Seung Ho

2011-12-01

A multilayer laminated piezoelectric Pb(Zr(1-x)Ti(x))O(3) (PZT) ceramic transformer, operating in a half- wavelength longitudinal resonant mode (λ/2 mode), has been analyzed. This piezoelectric transformer is composed of one thickness-polarized section (T-section) for exciting the longitudinal mechanical vibrations, two longitudinally polarized sections (L-section) for generating high-voltage output, and two insulating layers laminated between the T-section and L-section layers to provide insulation between the input and output sections. Based on the piezoelectric constitutive and motion equations, an electro-elasto-electric (EEE) equivalent circuit has been developed, and correspondingly, an effective EEE coupling coefficient was proposed for optimum design of this multilayer transformer. Commercial finite element analysis software is used to determine the validity of the developed equivalent circuit. Finally, a prototype sample was manufactured and experimental data was collected to verify the model's validity.

Design and implementation of improved LsCpLp resonant circuit for power supply for high-power electromagnetic acoustic transducer excitation

Science.gov (United States)

Zao, Yongming; Ouyang, Qi; Chen, Jiawei; Zhang, Xinglan; Hou, Shuaicheng

2017-08-01

This paper investigates the design and implementation of an improved series-parallel inductor-capacitor-inductor (LsCpLp) resonant circuit power supply for excitation of electromagnetic acoustic transducers (EMATs). The main advantage of the proposed resonant circuit is the absence of a high-permeability dynamic transformer. A high-frequency pulsating voltage gain can be achieved through a double resonance phenomenon. Both resonant tailing behavior and higher harmonics are suppressed by the improved resonant circuit, which also contributes to the generation of ultrasonic waves. Additionally, the proposed circuit can realize impedance matching and can also optimize the transduction efficiency. The complete design and implementation procedure for the power supply is described and has been validated by implementation of the proposed power supply to drive a portable EMAT. The circuit simulation results show close agreement with the experimental results and thus confirm the validity of the proposed topology. The proposed circuit is suitable for use as a portable EMAT excitation power supply that is fed by a low-voltage source.

Design and implementation of improved LsCpLp resonant circuit for power supply for high-power electromagnetic acoustic transducer excitation.

Science.gov (United States)

Zao, Yongming; Ouyang, Qi; Chen, Jiawei; Zhang, Xinglan; Hou, Shuaicheng

2017-08-01

This paper investigates the design and implementation of an improved series-parallel inductor-capacitor-inductor (L s C p L p ) resonant circuit power supply for excitation of electromagnetic acoustic transducers (EMATs). The main advantage of the proposed resonant circuit is the absence of a high-permeability dynamic transformer. A high-frequency pulsating voltage gain can be achieved through a double resonance phenomenon. Both resonant tailing behavior and higher harmonics are suppressed by the improved resonant circuit, which also contributes to the generation of ultrasonic waves. Additionally, the proposed circuit can realize impedance matching and can also optimize the transduction efficiency. The complete design and implementation procedure for the power supply is described and has been validated by implementation of the proposed power supply to drive a portable EMAT. The circuit simulation results show close agreement with the experimental results and thus confirm the validity of the proposed topology. The proposed circuit is suitable for use as a portable EMAT excitation power supply that is fed by a low-voltage source.

On equivalent resistance of electrical circuits

Science.gov (United States)

Kagan, Mikhail

2015-01-01

While the standard (introductory physics) way of computing the equivalent resistance of nontrivial electrical circuits is based on Kirchhoff's rules, there is a mathematically and conceptually simpler approach, called the method of nodal potentials, whose basic variables are the values of the electric potential at the circuit's nodes. In this paper, we review the method of nodal potentials and illustrate it using the Wheatstone bridge as an example. We then derive a closed-form expression for the equivalent resistance of a generic circuit, which we apply to a few sample circuits. The result unveils a curious interplay between electrical circuits, matrix algebra, and graph theory and its applications to computer science. The paper is written at a level accessible by undergraduate students who are familiar with matrix arithmetic. Additional proofs and technical details are provided in appendices.

Co-design of on-chip antennas and circuits for a UNII band monolithic transceiver

KAUST Repository

Shamim, Atif; Arsalan, Muhammad; Roy, L; Salama, Khaled N.

2012-01-01

with two on-chip antennas. Both antennas are characterized for their radiation properties through an on-wafer custom measurement setup. The strategy to co-design on-chip antennas with circuits, resultant trade-offs and measurement challenges have also been

Microwave amplifier and active circuit design using the real frequency technique

CERN Document Server

Jarry, Pierre

2016-01-01

This book focuses on the authors' Real Frequency Technique (RFT) and its application to a wide variety of multi-stage microwave amplifiers and active filters, and passive equalizers for radar pulse shaping and antenna return loss applications. The first two chapters review the fundamentals of microwave amplifier design and provide a description of the RFT. Each subsequent chapter introduces a new type of amplifier or circuit design, reviews its design problems, and explains how the RFT can be adapted to solve these problems. The authors take a practical approach by summarizing the design steps and giving numerous examples of amplifier realizations and measured responses. Provides a complete description of the RFT as it is first used to design multistage lumped amplifiers using a progressive optimization of the equalizers, leading to a small umber of parameters to optimize simultaneously Presents modifications to the RFT to design trans-impedance microwave amplifiers that are used for photodiodes acti...

The point of practical use for the transistor circuit

International Nuclear Information System (INIS)

1996-01-01

This is comprised of eight chapters and goes as follows; what is transistor? the first step for use of transistor such as connection between power and signal source, static characteristic of transistor and equivalent circuit of transistor, design of easy small-signal amplifier circuit, design for amplification of electric power and countermeasure for prevention of trouble, transistor concerned interface, transistor circuit around micro computer, transistor in active use of FET and power circuit and transistor. It has an appendix on transistor and design of bias of FET circuits like small signal transistor circuit and FET circuit.

Radio-frequency integrated-circuit engineering

CERN Document Server

Nguyen, Cam

2015-01-01

Radio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC's using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. Provide

Circuit Design for Sensor Detection Signal Conditioner Nitrate Content

Directory of Open Access Journals (Sweden)

Robeth Manurung

2011-09-01

Full Text Available Nitrate is one of macro nutrients very important for agriculture. The availability of nitrate in soil is limited because it is very easy to leaching by rain, therefore nitrate could be contaminated ground water by  over-process of fertilizer. This process could also produce inefficiency in agriculture if it happened continuesly without pre-analysis of farm field. The answer those problems, it is need to develop the ion sensor system to measure concentrations of nitrat in soil. The system is consist of nitrate ion sensor device, signal conditioning and data acquisition circuit. The design and fabrications of signal conditioning circuit which integrated into ion nitrate sensor system and will apply for agriculture. This sensor has been used amperometric with three electrodes configuration: working, reference  and auxiliarry; the ion senstive membrane has use conductive polymer. The screen printing technique has been choosen to fabricate electrodes and deposition technique for ion sensitive membrane is electropolymerization. The characterization of sensor has been conducted using nitrate standard solution with range of concentration between 1 µM–1 mM. The characterization has shown that sensor has a good response with cureent output between 2.8–4.71 µA, liniearity factor is 99.65% and time response 250 second.

Small circuits for cryptography.

Energy Technology Data Exchange (ETDEWEB)

Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik

2005-10-01

This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.

The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits

CERN Document Server

Arora, Mohit

2012-01-01

This book highlights the complex issues, tasks and skills that must be mastered by an IP designer, in order to design an optimized and robust digital circuit to solve a problem. The techniques and methodologies described can serve as a bridge between specifications that are known to the designer and RTL code that is final outcome, reducing significantly the time it takes to convert initial ideas and concepts into right-first-time silicon.� Coverage focuses on real problems rather than theoretical concepts, with an emphasis on design techniques across various aspects of chip-design.�� Describes techniques to help IP designers get it right the first time, creating designs optimized in terms of power, area and performance; Focuses on practical aspects of chip design and minimizes theory; Covers chip design in a consistent way, starting with basics and gradually developing advanced concepts, such as electromagnetic compatibility (EMC) design techniques and low-power design techniques such as dynamic voltage...

Electronic devices and circuits

CERN Document Server

Pridham, Gordon John

1968-01-01

Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th

Universal programmable quantum circuit schemes to emulate an operator

Energy Technology Data Exchange (ETDEWEB)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos [Department of Computer Science, Purdue University, West Lafayette, Indiana 47907 (United States); Kais, Sabre [Department of Chemistry, Department of Physics and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907 (United States); Qatar Environment and Energy Research Institute, Doha (Qatar)

2012-12-21

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

Universal programmable quantum circuit schemes to emulate an operator

International Nuclear Information System (INIS)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos; Kais, Sabre

2012-01-01

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix–which can be non-unitary–in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e −iHt for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

Study of the computer aided design of combinatory logical circuits

International Nuclear Information System (INIS)

Sisso, Robert

1969-01-01

This survey aims at obtaining, automatically, low costs circuits in NOR and NAND technology for completely and incompletely specified functions. Two methods are proposed; the first one (chain fusion and element combination method) aims at obtaining directly the circuits by applying synthesis algorithms, the automation of which is provided by a new notation which binds bi-univocally circuit and function. The second one (decomposition method) uses the principle of the simple disjoined decomposition and enables to determine within this scope the upper boundary evolution of the circuit minimum cost. (author) [fr

CHEETAH: circuit-switched high-speed end-to-end transport architecture

Science.gov (United States)

Veeraraghavan, Malathi; Zheng, Xuan; Lee, Hyuk; Gardner, M.; Feng, Wuchun

2003-10-01

Leveraging the dominance of Ethernet in LANs and SONET/SDH in MANs and WANs, we propose a service called CHEETAH (Circuit-switched High-speed End-to-End Transport ArcHitecture). The service concept is to provide end hosts with high-speed, end-to-end circuit connectivity on a call-by-call shared basis, where a "circuit" consists of Ethernet segments at the ends that are mapped into Ethernet-over-SONET long-distance circuits. This paper focuses on the file-transfer application for such circuits. For this application, the CHEETAH service is proposed as an add-on to the primary Internet access service already in place for enterprise hosts. This allows an end host that is sending a file to first attempt setting up an end-to-end Ethernet/EoS circuit, and if rejected, fall back to the TCP/IP path. If the circuit setup is successful, the end host will enjoy a much shorter file-transfer delay than on the TCP/IP path. To determine the conditions under which an end host with access to the CHEETAH service should attempt circuit setup, we analyze mean file-transfer delays as a function of call blocking probability in the circuit-switched network, probability of packet loss in the IP network, round-trip times, link rates, and so on.

Standardization of Schwarz-Christoffel transformation for engineering design of semiconductor and hybrid integrated-circuit elements

Science.gov (United States)

Yashin, A. A.

1985-04-01

A semiconductor or hybrid structure into a calculable two-dimensional region mapped by the Schwarz-Christoffel transformation and a universal algorithm can be constructed on the basis of Maxwell's electro-magnetic-thermal similarity principle for engineering design of integrated-circuit elements. The design procedure involves conformal mapping of the original region into a polygon and then the latter into a rectangle with uniform field distribution, where conductances and capacitances are calculated, using tabulated standard mapping functions. Subsequent synthesis of a device requires inverse conformal mapping. Devices adaptable as integrated-circuit elements are high-resistance film resistors with periodic serration, distributed-resistance film attenuators with high transformation ratio, coplanar microstrip lines, bipolar transistors, directional couplers with distributed coupling to microstrip lines for microwave bulk devices, and quasirregular smooth matching transitions from asymmetric to coplanar microstrip lines.

Security electronics circuits manual

CERN Document Server

MARSTON, R M

1998-01-01

Security Electronics Circuits Manual is an invaluable guide for engineers and technicians in the security industry. It will also prove to be a useful guide for students and experimenters, as well as providing experienced amateurs and DIY enthusiasts with numerous ideas to protect their homes, businesses and properties.As with all Ray Marston's Circuits Manuals, the style is easy-to-read and non-mathematical, with the emphasis firmly on practical applications, circuits and design ideas. The ICs and other devices used in the practical circuits are modestly priced and readily available ty

Principles of transistor circuits introduction to the design of amplifiers, receivers and digital circuits

CERN Document Server

Amos, S W

1990-01-01

Principles of Transistor Circuits, Seventh Edition discusses the fundamental concepts of transistor circuits. The book is comprised of 16 chapters that cover amplifiers, oscillators, and generators. Chapter 1 discusses semiconductors and junction nodes, while Chapter 2 covers the basic principles of transistors. The subsequent chapters focus on amplifiers, where one of the chapters discusses bias and D.C. The book also talks about sinusoidal oscillators and covers modulators, demodulators, mixers, and receivers. Chapters 13 and 14 discuss pulse generators and sawtooth generators, respectively.

Design and testing of integrated circuits for reactor protection channels

International Nuclear Information System (INIS)

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.

1995-01-01

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built

Analog integrated circuit design automation placement, routing and parasitic extraction techniques

CERN Document Server

Martins, Ricardo; Horta, Nuno

2017-01-01

This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets. Introduces readers to hierarchical combination of Pareto fronts of placements; Presents electromigration-aware routing with multilayer multiport terminal structures...

Parallel LC circuit model for multi-band absorption and preliminary design of radiative cooling.

Science.gov (United States)

Feng, Rui; Qiu, Jun; Liu, Linhua; Ding, Weiqiang; Chen, Lixue

2014-12-15

We perform a comprehensive analysis of multi-band absorption by exciting magnetic polaritons in the infrared region. According to the independent properties of the magnetic polaritons, we propose a parallel inductance and capacitance(PLC) circuit model to explain and predict the multi-band resonant absorption peaks, which is fully validated by using the multi-sized structure with identical dielectric spacing layer and the multilayer structure with the same strip width. More importantly, we present the application of the PLC circuit model to preliminarily design a radiative cooling structure realized by merging several close peaks together. This omnidirectional and polarization insensitive structure is a good candidate for radiative cooling application.

Four-terminal circuit element with photonic core

Science.gov (United States)

Sampayan, Stephen

2017-08-29

A four-terminal circuit element is described that includes a photonic core inside of the circuit element that uses a wide bandgap semiconductor material that exhibits photoconductivity and allows current flow through the material in response to the light that is incident on the wide bandgap material. The four-terminal circuit element can be configured based on various hardware structures using a single piece or multiple pieces or layers of a wide bandgap semiconductor material to achieve various designed electrical properties such as high switching voltages by using the photoconductive feature beyond the breakdown voltages of semiconductor devices or circuits operated based on electrical bias or control designs. The photonic core aspect of the four-terminal circuit element provides unique features that enable versatile circuit applications to either replace the semiconductor transistor-based circuit elements or semiconductor diode-based circuit elements.

Lecture note on circuit technology for high energy physics experiment

International Nuclear Information System (INIS)

Ikeda, Hirokazu.

1992-07-01

This lecture gives basic ideas and practice of the circuit technology for high energy physics experiment. The program of this lecture gives access to the integrated circuit technology to be applied for a high luminosity hadron collider experiment. (author)

A current-mode multi-valued adder circuit for multi-operand addition

Science.gov (United States)

Cini, Ugur; Morgül, Avni

2011-06-01

Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.

Design analysis of a lead–lithium/supercritical CO2 Printed Circuit Heat Exchanger for primary power recovery

International Nuclear Information System (INIS)

Fernández, Iván; Sedano, Luis

2013-01-01

Highlights: • A design for a PbLi/CO 2 (SC) Printed Circuit Heat Exchanger which optimizes the pressure drop performance is proposed. • Numerical analyses have been performed to optimize the airfoil fins shape and arrangement. • SiC is proposed as structural material and tritium permeation barrier for the PCHE. • The integrated flux is larger than expected and allows reducing the CO 2 mass flow in this sector of the power cycle. • A transport model has been developed to evaluate the permeation of tritium from the liquid metal to the secondary CO 2 . -- Abstract: One of the key issues for fusion power plant technology is the efficient, reliable and safe recovery of the power extracted by the primary coolants. An interesting design option for power conversion cycles based on Dual Coolant Breeding Blankets (DCBB) is a Printed Circuit Heat Exchanger, which is supported by the advantages of its compactness, thermal effectiveness, high temperature and pressure capability and corrosion resistance. This work presents a design analysis of a silicon carbide Printed Circuit Heat Exchanger for lead–lithium/supercritical CO 2 at DEMO ranges (4× segmentation)

Implementation of Chua's circuit using simulated inductance

Science.gov (United States)

Gopakumar, K.; Premlet, B.; Gopchandran, K. G.

2011-05-01

In this study we describe how to build an inductorless version of the classic Chua's circuit. A suitable inductor for Chua's circuit is often hard to procure. The required inductor for the circuit is designed using simple circuit elements such as resistors, capacitors and operational amplifiers. The complete circuit can be implemented by using off-the-shelf components, and it can readily be integrated on a single chip. This design of Chua's circuit allows the original dynamics to be slowed down to just a few hertz, enabling implementation of sophisticated control schemes without severe time restrictions. Another novel feature of the circuit is that losses associated with capacitors due to leakages can easily be compensated by providing negative resistance using the same setup. The chaotic behaviour of the circuit is verified by PSpice and Multisim simulation and also by experimental study on a circuit breadboard. The results give excellent agreement with each other and with the results of previous investigators.

A programming language for composable DNA circuits.

Science.gov (United States)

Phillips, Andrew; Cardelli, Luca

2009-08-06

Recently, a range of information-processing circuits have been implemented in DNA by using strand displacement as their main computational mechanism. Examples include digital logic circuits and catalytic signal amplification circuits that function as efficient molecular detectors. As new paradigms for DNA computation emerge, the development of corresponding languages and tools for these paradigms will help to facilitate the design of DNA circuits and their automatic compilation to nucleotide sequences. We present a programming language for designing and simulating DNA circuits in which strand displacement is the main computational mechanism. The language includes basic elements of sequence domains, toeholds and branch migration, and assumes that strands do not possess any secondary structure. The language is used to model and simulate a variety of circuits, including an entropy-driven catalytic gate, a simple gate motif for synthesizing large-scale circuits and a scheme for implementing an arbitrary system of chemical reactions. The language is a first step towards the design of modelling and simulation tools for DNA strand displacement, which complements the emergence of novel implementation strategies for DNA computing.

Model Comparison Exercise Circuit Training Game and Circuit Ladder Drills to Improve Agility and Speed

Directory of Open Access Journals (Sweden)

Susilaturochman Hendrawan Koestanto

2017-11-01

Full Text Available The purpose of this study was to compare: (1 the effect of circuit training game and circuit ladder drill for the agility; (2 the effect of circuit training game and circuit ladder drill on speed; (3 the difference effect of circuit training game and circuit ladder drill for the speed (4 the difference effect of circuit training game and circuit ladder drill on agility. The type of this research was quantitative with quasi-experimental methods. The design of this research was Factorial Design, with analysing data using ANOVA. The process of data collection was done by using 30 meters sprint speed test and shuttle run test during the pretest and posttest. Furthermore, the data was analyzed by using SPSS 22.0 series. Result: The circuit training game exercise program and circuit ladder drill were significant to increase agility and speed (sig 0.000 < α = 0.005 Group I, II, III had significant differences (sig 0.000 < α = 0.005. The mean of increase in speed of group I = 0.20 seconds, group II = 0.31 seconds, and group III = 0.11 seconds. The average increase agility to group I = 0.34 seconds group II = 0.60 seconds, group III = 0.13 seconds. Based on the analysis above, it could be concluded that there was an increase in the speed and agility of each group after being given a training.

Remote tuning of NMR probe circuits.

Science.gov (United States)

Kodibagkar, V D; Conradi, M S

2000-05-01

There are many circumstances in which the probe tuning adjustments cannot be located near the rf NMR coil. These may occur in high-temperature NMR, low-temperature NMR, and in the use of magnets with small diameter access bores. We address here circuitry for connecting a fixed-tuned probe circuit by a transmission line to a remotely located tuning network. In particular, the bandwidth over which the probe may be remotely tuned while keeping the losses in the transmission line acceptably low is considered. The results show that for all resonant circuit geometries (series, parallel, series-parallel), overcoupling of the line to the tuned circuit is key to obtaining a large tuning bandwidth. At equivalent extents of overcoupling, all resonant circuit geometries have nearly equal remote tuning bandwidths. Particularly for the case of low-loss transmission line, the tuning bandwidth can be many times the tuned circuit's bandwidth, f(o)/Q. Copyright 2000 Academic Press.

49 CFR 236.786 - Principle, closed circuit.

Science.gov (United States)

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Principle, closed circuit. 236.786 Section 236.786 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL RAILROAD ADMINISTRATION... Principle, closed circuit. The principle of circuit design where a normally energized electric circuit which...

The test of VLSI circuits

Science.gov (United States)

Baviere, Ph.

Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

Design and Implementation of Linux Access Control Model

Institute of Scientific and Technical Information of China (English)

Wei Xiaomeng; Wu Yongbin; Zhuo Jingchuan; Wang Jianyun; Haliqian Mayibula

2017-01-01

In this paper,the design and implementation of an access control model for Linux system are discussed in detail. The design is based on the RBAC model and combines with the inherent characteristics of the Linux system,and the support for the process and role transition is added.The core idea of the model is that the file is divided into different categories,and access authority of every category is distributed to several roles.Then,roles are assigned to users of the system,and the role of the user can be transited from one to another by running the executable file.

Multiobjective Optimization for Electronic Circuit Design in Time and Frequency Domains

Directory of Open Access Journals (Sweden)

J. Dobes

2013-04-01

Full Text Available The multiobjective optimization provides an extraordinary opportunity for the finest design of electronic circuits because it allows to mathematically balance contradictory requirements together with possible constraints. In this paper, an original and substantial improvement of an existing method for the multiobjective optimization known as GAM (Goal Attainment Method is suggested. In our proposal, the GAM algorithm itself is combined with a procedure that automatically provides a set of parameters -- weights, coordinates of the reference point -- for which the method generates noninferior solutions uniformly spread over an appropriately selected part of the Pareto front. Moreover, the resulting set of obtained solutions is then presented in a suitable graphic form so that the solution representing the most satisfactory tradeoff can be easily chosen by the designer. Our system generates various types of plots that conveniently characterize results of up to four-dimensional problems. Technically, the procedures of the multiobjective optimization were created as a software add-on to the CIA (Circuit Interactive Analyzer program. This way enabled us to utilize many powerful features of this program, including the sensitivity analyses in time and frequency domains. As a result, the system is also able to perform the multiobjective optimization in the time domain and even highly nonlinear circuits can be significantly improved by our program. As a demonstration of this feature, a multiobjective optimization of a C-class power amplifier in the time domain is thoroughly described in the paper. Further, a four-dimensional optimization of a video amplifier is demonstrated with an original graphic representation of the Pareto front, and also some comparison with the weighting method is done. As an example of improving noise properties, a multiobjective optimization of a low-noise amplifier is performed, and the results in the frequency domain are shown

Maximum Acceleration Recording Circuit

Science.gov (United States)

Bozeman, Richard J., Jr.

1995-01-01

Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.

Radiation-sensitive switching circuits

Energy Technology Data Exchange (ETDEWEB)

Moore, J.H.; Cockshott, C.P.

1976-03-16

A radiation-sensitive switching circuit has a light emitting diode which supplies light to a photo-transistor, the light being interrupted from time to time. When the photo-transistor is illuminated, current builds up and when this current reaches a predetermined value, a trigger circuit changes state. The peak output of the photo-transistor is measured and the trigger circuit is arranged to change state when the output of the device is a set proportion of the peak output, so as to allow for aging of the components. The circuit is designed to control the ignition system in an automobile engine.

Joint Hybrid Backhaul and Access Links Design in Cloud-Radio Access Networks

KAUST Repository

Dhifallah, Oussama Najeeb

2015-09-06

The cloud-radio access network (CRAN) is expected to be the core network architecture for next generation mobile radio systems. In this paper, we consider the downlink of a CRAN formed of one central processor (the cloud) and several base station (BS), where each BS is connected to the cloud via either a wireless or capacity-limited wireline backhaul link. The paper addresses the joint design of the hybrid backhaul links (i.e., designing the wireline and wireless backhaul connections from the cloud to the BSs) and the access links (i.e., determining the sparse beamforming solution from the BSs to the users). The paper formulates the hybrid backhaul and access link design problem by minimizing the total network power consumption. The paper solves the problem using a two-stage heuristic algorithm. At one stage, the sparse beamforming solution is found using a weighted mixed 11/12 norm minimization approach; the correlation matrix of the quantization noise of the wireline backhaul links is computed using the classical rate-distortion theory. At the second stage, the transmit powers of the wireless backhaul links are found by solving a power minimization problem subject to quality-of-service constraints, based on the principle of conservation of rate by utilizing the rates found in the first stage. Simulation results suggest that the performance of the proposed algorithm approaches the global optimum solution, especially at high signal-to-interference-plus-noise ratio (SINR).

Design of nuclear pulse shaped circuit based on proportional counter

International Nuclear Information System (INIS)

Song Qianqian; Cheng Yi; Tuo Xianguo

2011-01-01

Use the self-developed proportional to sample gas tritium in environment and make the measurement. For this detector, a kind of pulse shape circuit based on second order active low pass filtering circuit realized filtering and shaping nuclear pulse by high-speed operational amplifier, with less stages that has been approved for filter Gaussian wave. Use Multisim 10.0 to simulate the different parameters of the filter circuit. The simulation result was consistent with the theoretical results. The experiments proved the feasibility of this circuit, and at the same time provided a convenient and reliable method for analysis and optimization of the nuclear pulse waveform in order for discriminating by MCA. (authors)

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

CERN Document Server

Lim, Sung Kyu

2013-01-01

This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits.  It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs.  Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process. Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability. Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the e...

Secure integrated circuits and systems

CERN Document Server

Verbauwhede, Ingrid MR

2010-01-01

On any advanced integrated circuit or 'system-on-chip' there is a need for security. In many applications the actual implementation has become the weakest link in security rather than the algorithms or protocols. The purpose of the book is to give the integrated circuits and systems designer an insight into the basics of security and cryptography from the implementation point of view. As a designer of integrated circuits and systems it is important to know both the state-of-the-art attacks as well as the countermeasures. Optimizing for security is different from optimizations for speed, area,

A new modeling procedure for circuit design and performance prediction of evaporator coils using CO2 as refrigerant

International Nuclear Information System (INIS)

Larbi Bendaoud, Adlane; Ouzzane, Mohamed; Aidoun, Zine; Galanis, Nicolas

2010-01-01

The replacement of environmentally damaging synthetic refrigerants due to their ODP or GWI potential by natural refrigerants such as CO 2 is now up in the research agenda. Moreover, current energy supply concerns make of efficiency another first priority issue to dictate new stringent design criteria for industrial and commercial equipment. Heat exchangers are the most important components in refrigeration systems where they are used as evaporators or condensers and their design and operation have a considerable impact on overall system performance. Hence, it is important to better understand their thermal and hydrodynamic behaviour in order to improve their design and operation. Numerical simulation represents a very efficient tool for achieving this objective. In this paper, a new modeling approach, accounting for the heat transfer the hydrodynamics of the problem and intended to predict the dynamic behaviour of a refrigeration coil under dry conditions is proposed. A related FORTRAN program was developed, allowing the study of a large range of complex refrigerant circuit configurations. The equations describing these aspects are strongly coupled, and their decoupling is reached by using an original method of resolution. Circuits may have several inlets, outlets, bifurcations and feed one or several other tubes inlets. The coil was subdivided into several elementary control volumes and its analysis provided detailed information in X, Y and Z directions. Validation was performed with data from a CO 2 secondary refrigeration loop test bench built in CanmetENERGY Laboratories. These data were predicted satisfactorily over the operating range corresponding to refrigeration applications. Exemplary simulations were then performed on an evaporator typically employed in supermarkets, showing the effect of circuiting on operation and performance. Even though circuiting is common practice in refrigeration this simulation shows that care must be exercised in making the

Advanced circuit simulation using Multisim workbench

CERN Document Server

Báez-López, David; Cervantes-Villagómez, Ofelia Delfina

2012-01-01

Multisim is now the de facto standard for circuit simulation. It is a SPICE-based circuit simulator which combines analog, discrete-time, and mixed-mode circuits. In addition, it is the only simulator which incorporates microcontroller simulation in the same environment. It also includes a tool for printed circuit board design.Advanced Circuit Simulation Using Multisim Workbench is a companion book to Circuit Analysis Using Multisim, published by Morgan & Claypool in 2011. This new book covers advanced analyses and the creation of models and subcircuits. It also includes coverage of transmissi

READ - Remote Analog ASIC Design System

Directory of Open Access Journals (Sweden)

Michael E. Auer

2006-11-01

Full Text Available The scope of this work is to present a solution to implement a remote electronic laboratory for testing and designing analog ASICs (ispPAC10. The application allows users to create circuit schematics, upload the design to the device and perform measurements. The software used for designing circuits is the PAC-Designer and it runs on a Citrix server. The signals are generated and the responses are acquired by a data acquisition board controlled by LabView. The virtual instruments interact with some ActiveX controls specially designed to look like real oscilloscope and function generator devices and represent the user interface of the lab. These ActiveX give users the control over the LabView VIs and the access to its facilities in order to perform electronic exercises.

Design of two digital radiation tolerant integrated circuits for high energy physics experiments data readout

CERN Document Server

Bonacini, Sandro

2003-01-01

High Energy Physics research (HEP) involves the design of readout electron- ics for its experiments, which generate a high radiation ¯eld in the detectors. The several integrated circuits placed in the future Large Hadron Collider (LHC) experiments' environment have to resist the radiation and carry out their normal operation. In this thesis I will describe in detail what, during my 10-months partic- ipation in the digital section of the Microelectronics group at CERN, I had the possibility to work on: - The design of a radiation-tolerant data readout digital integrated cir- cuit in a 0.25 ¹m CMOS technology, called \\the Kchip", for the CMS preshower front-end system. This will be described in Chapter 3. - The design of a radiation-tolerant SRAM integrated circuit in a 0.13 ¹m CMOS technology, for technology radiation testing purposes and fu- ture applications in the HEP ¯eld. The SRAM will be described in Chapter 4. All the work has carried out under the supervision and with the help of Dr. Kostas Klouki...

Electronic circuits for communications systems: A compilation

Science.gov (United States)

1972-01-01

The compilation of electronic circuits for communications systems is divided into thirteen basic categories, each representing an area of circuit design and application. The compilation items are moderately complex and, as such, would appeal to the applications engineer. However, the rationale for the selection criteria was tailored so that the circuits would reflect fundamental design principles and applications, with an additional requirement for simplicity whenever possible.

Design and Analysis of Compact DNA Strand Displacement Circuits for Analog Computation Using Autocatalytic Amplifiers.

Science.gov (United States)

Song, Tianqi; Garg, Sudhanshu; Mokhtar, Reem; Bui, Hieu; Reif, John

2018-01-19

A main goal in DNA computing is to build DNA circuits to compute designated functions using a minimal number of DNA strands. Here, we propose a novel architecture to build compact DNA strand displacement circuits to compute a broad scope of functions in an analog fashion. A circuit by this architecture is composed of three autocatalytic amplifiers, and the amplifiers interact to perform computation. We show DNA circuits to compute functions sqrt(x), ln(x) and exp(x) for x in tunable ranges with simulation results. A key innovation in our architecture, inspired by Napier's use of logarithm transforms to compute square roots on a slide rule, is to make use of autocatalytic amplifiers to do logarithmic and exponential transforms in concentration and time. In particular, we convert from the input that is encoded by the initial concentration of the input DNA strand, to time, and then back again to the output encoded by the concentration of the output DNA strand at equilibrium. This combined use of strand-concentration and time encoding of computational values may have impact on other forms of molecular computation.

Microwave Photonic Architecture for Direction Finding of LPI Emitters: Front End Analog Circuit Design and Component Characterization

Science.gov (United States)

2016-09-01

into two parts. The design, development, and testing efforts of the front-end microwave photonics circuit design and the system integration with the...miniature microwave - photonic phase-sampling DF technique is investigated in this thesis. This front-end design uses a combination of integrated optical...NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIFORNIA THESIS Approved for public release. Distribution is unlimited. MICROWAVE

Design issues of a low cost lock-in amplifier readout circuit for an infrared detector

Science.gov (United States)

Scheepers, L.; Schoeman, J.

2014-06-01

In the past, high resolution thermal sensors required expensive cooling techniques making the early thermal imagers expensive to operate and cumbersome to transport, limiting them mainly to military applications. However, the introduction of uncooled microbolometers has overcome many of earlier problems and now shows great potential for commercial optoelectric applications. The structure of uncooled microbolometer sensors, especially their smaller size, makes them attractive in low cost commercial applications requiring high production numbers with relatively low performance requirements. However, the biasing requirements of these microbolometers cause these sensors to generate a substantial amount of noise on the output measurements due to self-heating. Different techniques to reduce this noise component have been attempted, such as pulsed biasing currents and the use of blind bolometers as common mode reference. These techniques proved to either limit the performance of the microbolometer or increase the cost of their implementation. The development of a low cost lock-in amplifier provides a readout technique to potentially overcome these challenges. High performance commercial lock-in amplifiers are very expensive. Using this as a readout circuit for a microbolometer will take away from the low manufacturing cost of the detector array. Thus, the purpose of this work was to develop a low cost readout circuit using the technique of phase sensitive detection and customizing this as a readout circuit for microbolometers. The hardware and software of the readout circuit was designed and tested for improvement of the signal-to-noise ratio (SNR) of the microbolometer signal. An optical modulation system was also developed in order to effectively identify the desired signal from the noise with the use of the readout circuit. A data acquisition and graphical user interface sub system was added in order to display the signal recovered by the readout circuit. The readout

Laser system for testing radiation imaging detector circuits

Science.gov (United States)

Zubrzycka, Weronika; Kasinski, Krzysztof

2015-09-01

Performance and functionality of radiation imaging detector circuits in charge and position measurement systems need to meet tight requirements. It is therefore necessary to thoroughly test sensors as well as read-out electronics. The major disadvantages of using radioactive sources or particle beams for testing are high financial expenses and limited accessibility. As an alternative short pulses of well-focused laser beam are often used for preliminary tests. There are number of laser-based devices available on the market, but very often their applicability in this field is limited. This paper describes concept, design and validation of laser system for testing silicon sensor based radiation imaging detector circuits. The emphasis is put on keeping overall costs low while achieving all required goals: mobility, flexible parameters, remote control and possibility of carrying out automated tests. The main part of the developed device is an optical pick-up unit (OPU) used in optical disc drives. The hardware includes FPGA-controlled circuits for laser positioning in 2 dimensions (horizontal and vertical), precision timing (frequency and number) and amplitude (diode current) of short ns-scale (3.2 ns) light pulses. The system is controlled via USB interface by a dedicated LabVIEW-based application enabling full manual or semi-automated test procedures.

Instrumentation and test gear circuits manual

CERN Document Server

Marston, R M

2013-01-01

Instrumentation and Test Gear Circuits Manual provides diagrams, graphs, tables, and discussions of several types of practical circuits. The practical circuits covered in this book include attenuators, bridges, scope trace doublers, timebases, and digital frequency meters. Chapter 1 discusses the basic instrumentation and test gear principles. Chapter 2 deals with the design of passive attenuators, and Chapter 3 with passive and active filter circuits. The subsequent chapters tackle 'bridge' circuits, analogue and digital metering techniques and circuitry, signal and waveform generation, and p

Digital circuit testing a guide to DFT and other techniques

CERN Document Server

Wong, Francis C

1991-01-01

Recent technological advances have created a testing crisis in the electronics industry--smaller, more highly integrated electronic circuits and new packaging techniques make it increasingly difficult to physically access test nodes. New testing methods are needed for the next generation of electronic equipment and a great deal of emphasis is being placed on the development of these methods. Some of the techniques now becoming popular include design for testability (DFT), built-in self-test (BIST), and automatic test vector generation (ATVG). This book will provide a practical introduction to

Radiation-hardened CMOS integrated circuits

International Nuclear Information System (INIS)

Derbenwick, G.F.; Hughes, R.C.

1977-01-01

Electronic circuits that operate properly after exposure to ionizing radiation are necessary for nuclear weapon systems, satellites, and apparatus designed for use in radiation environments. The program to develop and theoretically model radiation-tolerant integrated circuit components has resulted in devices that show an improvement in hardness up to a factor of ten thousand over earlier devices. An inverter circuit produced functions properly after an exposure of 10 6 Gy (Si) which, as far as is known, is the record for an integrated circuit

Magnetic circuit design of magnetically driving gliding arc discharge device

International Nuclear Information System (INIS)

Jiang Zhonghe; Liu Minghai; Gu Chenglin; Pan Yuan

2002-01-01

A gliding arc discharge driven by magnetic field at atmospheric pressure can generate non-equilibrium plasma with good confinement property, and has extensive application in the areas of microelectronic fabrication, environmental engineering, etc. The magnetic circuit of the generator is designed with the permeance method, and analytic expression is obtained on the magnetic induction, the permeant magnetic material thickness and length of air gap. The results have been compared with those of the finite element method, the difference is 3.1%. But the permeance method is more concise and convenient and more universal and economical. So the permeance method is a more credible and useful engineering arithmetic

Universal Design for Learning: Guidelines for Accessible Online Instruction

Science.gov (United States)

Rogers-Shaw, Carol; Carr-Chellman, Davin J.; Choi, Jinhee

2018-01-01

Universal Design for Learning (UDL) is a framework for the teaching-learning transaction that conceptualizes knowledge through learner-centered foci emphasizing accessibility, collaboration, and community. Given the importance of access to achieving social justice, UDL is a promising approach to meeting all learners' needs more effectively. In…

Compact beam splitters with deep gratings for miniature photonic integrated circuits: design and implementation aspects.

Science.gov (United States)

Chen, Chin-Hui; Klamkin, Jonathan; Nicholes, Steven C; Johansson, Leif A; Bowers, John E; Coldren, Larry A

2009-09-01

We present an extensive study of an ultracompact grating-based beam splitter suitable for photonic integrated circuits (PICs) that have stringent density requirements. The 10 microm long beam splitter exhibits equal splitting, low insertion loss, and also provides a high extinction ratio in an integrated coherent balanced receiver. We further present the design strategies for avoiding mode distortion in the beam splitter and discuss optimization of the widths of the detectors to improve insertion loss and extinction ratio of the coherent receiver circuit. In our study, we show that the grating-based beam splitter is a competitive technology having low fabrication complexity for ultracompact PICs.

Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

Science.gov (United States)

Stinner, F. Scott

As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

Computer-aided engineering of semiconductor integrated circuits

Science.gov (United States)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

Implementation of integrated circuit and design of SAR ADC for fully implantable hearing aids.

Science.gov (United States)

Kim, Jong Hoon; Lee, Jyung Hyun; Cho, Jin-Ho

2017-07-20

The hearing impaired population has been increasing; many people suffer from hearing problems. To deal with this difficulty, various types of hearing aids are being rapidly developed. In particular, fully implantable hearing aids are being actively studied to improve the performance of existing hearing aids and to reduce the stigma of hearing loss patients. It has to be of small size and low-power consumption for easy implantation and long-term use. The objective of the study was to implement a small size and low-power consumption successive approximation register analog-to-digital converter (SAR ADC) for fully implantable hearing aids. The ADC was selected as the SAR ADC because its analog circuit components are less required by the feedback circuit of the SAR ADC than the sigma-delta ADC which is conventionally used in hearing aids, and it has advantages in the area and power consumption. So, the circuit of SAR ADC is designed considering the speech region of humans because the objective is to deliver the speech signals of humans to hearing loss patients. If the switch of sample and hold works in the on/off positions, the charge injection and clock feedthrough are produced by a parasitic capacitor. These problems affect the linearity of the hold voltage, and as a result, an error of the bit conversion is generated. In order to solve the problem, a CMOS switch that consists of NMOS and PMOS was used, and it reduces the charge injection because the charge carriers in the NMOS and PMOS have inversed polarity. So, 16 bit conversion is performed before the occurrence of the Least Significant Bit (LSB) error. In order to minimize the offset voltage and power consumption of the designed comparator, we designed a preamplifier with current mirror. Therefore, the power consumption was reduced by the power control switch used in the comparator. The layout of the designed SAR ADC was performed by Virtuoso Layout Editor (Cadence, USA). In the layout result, the size of the

A NEW CONTROL CIRCUIT AND COMPUTER SOFTWARE FOR CONTROLING PHOTOVOLTAIC SYSTEMS

Directory of Open Access Journals (Sweden)

Mustafa Berkant SELEK

2008-02-01

Full Text Available In this study, a new microcontroller circuit was designed and new computer software was implemented to control power flow currents of renewable energy system, which is established in Solar Energy Institute, Ege University, Bornova, Izmir, Turkey. PIC18F452 microcontroller based electronic circuit was designed to control another electronic circuit that includes power electronic switching components. Readily available standard control circuits are designed for switching single level inverters. In contrary, implemented circuit allows to switch multilevel inverters. In addition, because the efficiency of solar energy panels is considerably low, solar panels should be operated under the maximum power point (MPP. Therefore, MPP algorithm is included in the designed control circuit. Next, the control circuit also includes a serial communication interface based on RS232 standard. Using this interface enables the user to choose all functions available in the control circuit and take status report via computer software. Last, a general purpose command set was designed to establish communication between the computer software and the microcontroller-based control circuit. As a result, it is aimed that this study supply a basis for the researchers who want to develop own control circuits or more visual software.

Accessible Earth: Enhancing diversity in the Geosciences through accessible course design

Science.gov (United States)

Bennett, R. A.; Lamb, D. A.

2017-12-01

The tradition of field-based instruction in the geoscience curriculum, which culminates in a capstone geological field camp, presents an insurmountable barrier to many disabled students who might otherwise choose to pursue geoscience careers. There is a widespread perception that success as a practicing geoscientist requires direct access to outcrops and vantage points available only to those able to traverse inaccessible terrain. Yet many modern geoscience activities are based on remotely sensed geophysical data, data analysis, and computation that take place entirely from within the laboratory. To challenge the perception of geoscience as a career option only for the non-disabled, we have created the capstone Accessible Earth Study Abroad Program, an alternative to geologic field camp for all students, with a focus on modern geophysical observation systems, computational thinking, data science, and professional development.In this presentation, we will review common pedagogical approaches in geosciences and current efforts to make the field more inclusive. We will review curricular access and inclusivity relative to a wide range of learners and provide examples of accessible course design based on our experiences in teaching a study abroad course in central Italy, and our plans for ongoing assessment, refinement, and dissemination of the effectiveness of our efforts.

Design, development and evaluation of a resistor-based multiplexing circuit for a 20×20 SiPM array

International Nuclear Information System (INIS)

Wang, Zhonghai; Sun, Xishan; Lou, Kai; Meier, Joseph; Zhou, Rong; Yang, Chaowen; Zhu, Xiaorong; Shao, Yiping

2016-01-01

One technical challenge in developing a large-size scintillator detector with multiple Silicon Photomultiplier (SiPM) arrays is to read out a large number of detector output channels. To achieve this, different signal multiplexing circuits have been studied and applied with different performances and cost-effective tradeoffs. Resistor-based multiplexing circuits exhibit simplicity and signal integrity, but also present the disadvantage of timing shift among different channels. In this study, a resistor-based multiplexing circuit for a large-sized SiPM array readout was developed and evaluated by simulation and experimental studies. Similarly to a multiplexing circuit used for multi-anode PMT, grounding and branching resistors were connected to each SiPM output channel. The grounding resistor was used to simultaneously reduce the signal crosstalk among different channels and to improve timing performance. Both grounding and branching resistor values were optimized to maintain a balanced performance of the event energy, timing, and positioning. A multiplexing circuit was implemented on a compact PCB and applied for a flat-panel detector which consisted of a 32×32 LYSO scintillator crystals optically coupled to 5×5 SiPM arrays for a total 20×20 output channels. Test results showed excellent crystal identification for all 1024 LYSO crystals (each with 2×2×30 mm"3 size) with "2"2Na flood-source irradiation. The measured peak-to-valley ratio from typical crystal map profile is around 3:1 to 6.6:1, an average single crystal energy resolution of about 17.3%, and an average single crystal timing resolution of about 2 ns. Timing shift among different crystals, as reported in some other resistor-based multiplexing circuit designs, was not observed. In summary, we have designed and implemented a practical resistor-based multiplexing circuit that can be readily applied for reading out a large SiPM array with good detector performance.

Design, development and evaluation of a resistor-based multiplexing circuit for a 20×20 SiPM array

Energy Technology Data Exchange (ETDEWEB)

Wang, Zhonghai [College of Physical Science and Technology, Key Laboratory of Radiation Physics and Technology, Ministry of Education, Sichuan University, Chengdu (China); Department of Radiation Oncology, University of Texas Southwestern Medical Center, Dallas, Tx (United States); Sun, Xishan [Department of Radiation Oncology, University of Texas Southwestern Medical Center, Dallas, Tx (United States); Lou, Kai [Department of Electrical and Computer Engineering, Rice University, Houston, Tx (United States); Meier, Joseph [Department of Imaging Physics, The University of Texas MD Anderson Cancer Center, Houston, Tx (United States); Zhou, Rong; Yang, Chaowen [College of Physical Science and Technology, Key Laboratory of Radiation Physics and Technology, Ministry of Education, Sichuan University, Chengdu (China); Zhu, Xiaorong [Department of Radiation Physics, The University of Texas MD Anderson Cancer Center, Houston, Tx (United States); Shao, Yiping [Department of Radiation Oncology, University of Texas Southwestern Medical Center, Dallas, Tx (United States)

2016-04-21

One technical challenge in developing a large-size scintillator detector with multiple Silicon Photomultiplier (SiPM) arrays is to read out a large number of detector output channels. To achieve this, different signal multiplexing circuits have been studied and applied with different performances and cost-effective tradeoffs. Resistor-based multiplexing circuits exhibit simplicity and signal integrity, but also present the disadvantage of timing shift among different channels. In this study, a resistor-based multiplexing circuit for a large-sized SiPM array readout was developed and evaluated by simulation and experimental studies. Similarly to a multiplexing circuit used for multi-anode PMT, grounding and branching resistors were connected to each SiPM output channel. The grounding resistor was used to simultaneously reduce the signal crosstalk among different channels and to improve timing performance. Both grounding and branching resistor values were optimized to maintain a balanced performance of the event energy, timing, and positioning. A multiplexing circuit was implemented on a compact PCB and applied for a flat-panel detector which consisted of a 32×32 LYSO scintillator crystals optically coupled to 5×5 SiPM arrays for a total 20×20 output channels. Test results showed excellent crystal identification for all 1024 LYSO crystals (each with 2×2×30 mm{sup 3} size) with {sup 22}Na flood-source irradiation. The measured peak-to-valley ratio from typical crystal map profile is around 3:1 to 6.6:1, an average single crystal energy resolution of about 17.3%, and an average single crystal timing resolution of about 2 ns. Timing shift among different crystals, as reported in some other resistor-based multiplexing circuit designs, was not observed. In summary, we have designed and implemented a practical resistor-based multiplexing circuit that can be readily applied for reading out a large SiPM array with good detector performance.

Vertically Integrated Circuits at Fermilab

International Nuclear Information System (INIS)

Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

2009-01-01

The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

Local and Remote Laboratory User Experimentation Access using Digital Programmable Logic

Directory of Open Access Journals (Sweden)

Ian A Grout

2005-06-01

Full Text Available This paper will discuss the structure and operation of a programmable logic based experimentation arrangement that is suitable for both local and remote teaching and learning scenarios targeting electronic and microelectronic circuit design and test principles. With this experimentation arrangement, the ability to provide both local and Internet based “remote” access for the student and the teacher can provide a number of advantages where physical laboratory accessibility is limited and/or the learning experience must be undertaken with one or more of the parties remotely based. The paper concentrates on the design and example use of a system developed within the University of Limerick.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

Energy Technology Data Exchange (ETDEWEB)

Li Shu; Zhang Tong [Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 (United States)], E-mail: lis4@rpi.edu, E-mail: tzhang@ecse.rpi.edu

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

Science.gov (United States)

Li, Shu; Zhang, Tong

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect

International Nuclear Information System (INIS)

Li Shu; Zhang Tong

2008-01-01

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance

Design of quaternary logic circuit using quantum dot gate-quantum dot channel FET (QDG-QDCFET)

Science.gov (United States)

Karmakar, Supriya

2014-10-01

This paper presents the implementation of quaternary logic circuits based on quantum dot gate-quantum dot channel field effect transistor (QDG-QDCFET). The super lattice structure in the quantum dot channel region of QDG-QDCFET and the electron tunnelling from inversion channel to the quantum dot layer in the gate region of a QDG-QDCFET change the threshold voltage of this device which produces two intermediate states between its ON and OFF states. This property of QDG-QDCFET is used to implement multi-valued logic for future multi-valued logic circuit. This paper presents the design of basic quaternary logic operation such as inverter, AND and OR operation based on QDG-QDCFET.

Design and testing of integrated circuits for reactor protection channels

International Nuclear Information System (INIS)

Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.; Rana, I.

1995-01-01

Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing

Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

International Nuclear Information System (INIS)

Zhang Mingming; Chen Zhongjian; Zhang Yacong; Lu Wengao; Ji Lijiu

2010-01-01

A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration. Continuous-time semi-Gaussian filter is chosen to avoid switch noise. The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application. The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology. Test results show the functions of the readout integrated circuit are correct. The equivalent noise charge with no detector connected is 500-700 e in the typical mode, the gain is tunable within 13-130 mV/fC and the peaking time varies from 0.7 to 1.6 μs, in which the average gain is about 20.5 mV/fC, and the linearity reaches 99.2%. (authors)

Accessible Web Design - The Power of the Personal Message.

Science.gov (United States)

Whitney, Gill

2015-01-01

The aim of this paper is to describe ongoing research being carried out to enable people with visual impairments to communicate directly with designers and specifiers of hobby and community web sites to maximise the accessibility of their sites. The research started with an investigation of the accessibility of community and hobby web sites as perceived by a group of visually impaired end users. It is continuing with an investigation into how to best to communicate with web designers who are not experts in web accessibility. The research is making use of communication theory to investigate how terminology describing personal experience can be used in the most effective and powerful way. By working with the users using a Delphi study the research has ensured that the views of the visually impaired end users is successfully transmitted.

Research on and design of key circuits in RFID tag chip for container management

Directory of Open Access Journals (Sweden)

Wang Wenjie

2016-01-01

Full Text Available This paper introduces the design of semi-passive RFID tag chip capable of monitoring container safety. A system framework complying with requirements by ISO/IEC 18000-6C is firstly presented, and then differences from the key units of common passive chip, such as switch-state monitoring circuit, power management unit and anti-shake design in baseband processor, are elaborated. The main function of such a chip is to record the container opening frequency during transportation. Finally, the realizations of each unit’s function are simulated.

Robert Lacoste's the darker side practical applications for electronic design concepts from circuit cellar

CERN Document Server

Lacoste, Robert

2009-01-01

Robert Lacoste's The Darker Side column has quickly become a must read among Circuit Cellar devotees. His column provides readers with succinct theoretical concepts and practical applications on topics as far reaching as digital modulation to antenna basics. Difficult concepts are demystified as Robert shines a light on complex topics within electronic design.This book collects sixteen Darker Side articles that have been enriched with new, exclusive content from the author. An intro into The Darker Side will give examples of material that can enhance and optimize the way you design. A

Voltage linear transformation circuit design

Science.gov (United States)

Sanchez, Lucas R. W.; Jin, Moon-Seob; Scott, R. Phillip; Luder, Ryan J.; Hart, Michael

2017-09-01

Many engineering projects require automated control of analog voltages over a specified range. We have developed a computer interface comprising custom hardware and MATLAB code to provide real-time control of a Thorlabs adaptive optics (AO) kit. The hardware interface includes an op amp cascade to linearly shift and scale a voltage range. With easy modifications, any linear transformation can be accommodated. In AO applications, the design is suitable to drive a range of different types of deformable and fast steering mirrors (FSM's). Our original motivation and application was to control an Optics in Motion (OIM) FSM which requires the customer to devise a unique interface to supply voltages to the mirror controller to set the mirror's angular deflection. The FSM is in an optical servo loop with a wave front sensor (WFS), which controls the dynamic behavior of the mirror's deflection. The code acquires wavefront data from the WFS and fits a plane, which is subsequently converted into its corresponding angular deflection. The FSM provides +/-3° optical angular deflection for a +/-10 V voltage swing. Voltages are applied to the mirror via a National Instruments digital-to-analog converter (DAC) followed by an op amp cascade circuit. This system has been integrated into our Thorlabs AO testbed which currently runs at 11 Hz, but with planned software upgrades, the system update rate is expected to improve to 500 Hz. To show that the FSM subsystem is ready for this speed, we conducted two different PID tuning runs at different step commands. Once 500 Hz is achieved, we plan to make the code and method for our interface solution freely available to the community.

The role of simulation in designing for universal access

DEFF Research Database (Denmark)

Keates, Simeon; Looms, Peter

2014-01-01

the difficulty of finding and recruiting suitable participants. Simulation aids offer a potentially cost-effective replacement or complement to participatory design. This paper examines a number of the issues associated with the use of simulation aids when designing for Universal Access. It concludes...

Ramp generator circuit for probe diagnostics using microcontroller for LHCD system

International Nuclear Information System (INIS)

Virani, C G; Sharma, P K

2010-01-01

It is well known that in LHCD system, the rf power coupling between antenna and plasma strongly depends on the edge plasma parameter. Thus it is mandatory to monitor edge plasma parameter to establish proper impedance matching condition when LHCD power is launched into the plasma. For SST1 LHCD system, we intend to monitor the edge plasma parameter employing electric probes, connected to the grill antenna sides for the said purpose. In SST1, initially LHCD system would couple rf power to plasmas lasting for small durations. Gradually the power and pulse length would be increased to eventually get 1000 seconds plasma. To monitor the edge plasma parameter, over such a wide spectrum (say few millisecond to seconds) during the above campaign, a flexible measurement scheme is desired which would cater to entire spectrum of operation. Normally a ramp is utilized to bias the electric probe, which yields various plasma parameters. To cater our requirement, the ramp generator must have facility to change ramp-up rate to meet our pulse length requirement. Further during SST operation, the human access near the machine would not be permitted and ramp circuit might not be accessible for manual settings. Thus remote setting facility to change ramp-up rate is also desired. Keeping these constraints in mind, a ramp circuit has been designed using Analog Device micro-controller ADuC842. The circuit has both manual and remote setting facility. Ramp generator parameters like Ramp-up rate, Trigger mode, number of cycles, etc. can be set from PC through RS-485 serial link. Initially low voltage (0-5V) ramp signal is generated using micro-controller and inbuilt DAC. This low voltage ramp is then amplified with PA-85 op-amp to get desired probe biasing voltage (-110V to +110V). The ramp period can be change form (1ms to 1000 ms) to cater to different plasma pulse length. Programming for micro-controller is done in structured language-C with the help of ''Keil'' IDE. In this paper, a

Ramp generator circuit for probe diagnostics using microcontroller for LHCD system

Energy Technology Data Exchange (ETDEWEB)

Virani, C G; Sharma, P K, E-mail: cgvirani@ipr.res.i [Institute for Plasma Research, Bhat, Gandhinagar 382428 (India)

2010-02-01

It is well known that in LHCD system, the rf power coupling between antenna and plasma strongly depends on the edge plasma parameter. Thus it is mandatory to monitor edge plasma parameter to establish proper impedance matching condition when LHCD power is launched into the plasma. For SST1 LHCD system, we intend to monitor the edge plasma parameter employing electric probes, connected to the grill antenna sides for the said purpose. In SST1, initially LHCD system would couple rf power to plasmas lasting for small durations. Gradually the power and pulse length would be increased to eventually get 1000 seconds plasma. To monitor the edge plasma parameter, over such a wide spectrum (say few millisecond to seconds) during the above campaign, a flexible measurement scheme is desired which would cater to entire spectrum of operation. Normally a ramp is utilized to bias the electric probe, which yields various plasma parameters. To cater our requirement, the ramp generator must have facility to change ramp-up rate to meet our pulse length requirement. Further during SST operation, the human access near the machine would not be permitted and ramp circuit might not be accessible for manual settings. Thus remote setting facility to change ramp-up rate is also desired. Keeping these constraints in mind, a ramp circuit has been designed using Analog Device micro-controller ADuC842. The circuit has both manual and remote setting facility. Ramp generator parameters like Ramp-up rate, Trigger mode, number of cycles, etc. can be set from PC through RS-485 serial link. Initially low voltage (0-5V) ramp signal is generated using micro-controller and inbuilt DAC. This low voltage ramp is then amplified with PA-85 op-amp to get desired probe biasing voltage (-110V to +110V). The ramp period can be change form (1ms to 1000 ms) to cater to different plasma pulse length. Programming for micro-controller is done in structured language-C with the help of ''Keil'' IDE

Development of large-scale thyristor dc circuit breaker

International Nuclear Information System (INIS)

Kobayashi, S.; Tanoue, Y.; Ikegame, H.; Matushita, T.; Sato, Y.

1981-01-01

A study for developing a thyristor dc circuit breaker that is applicable to the Tokamak device for engineering feasibility is presented. The design and test of a unit circuit breaker consisting of 4kV-3kA thyristors connected 2 in series and 12 in parallel are described. And based on the results a 50kV-24kA thyristor dc circuit breaker is conceptually designed

Development of a pulse shape discrimination circuit

International Nuclear Information System (INIS)

Ye Bangjiao; Fan Wei; Fan Yangmei; Yu Xiaoqi; Mei Wen; Wang Zhongmin; Han Rongdian; Xiao Zhenxi

1994-01-01

A pulse shape discrimination circuit was designed and used in an experiment measuring double-differential cross sections of (n, charged particle) reaction; to identify p, α and γ. The performance of the circuit was tested. With this circuit, excellent identification of p, α and γ was obtained. ((orig.))

Clock generators for SOC processors circuits and architectures

CERN Document Server

Fahim, Amr

2004-01-01

This book explores the design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. The text takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The comprehensive coverage includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discrete-time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The book provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, as well as the circuit level.

Radiation-sensitive switching circuits

Energy Technology Data Exchange (ETDEWEB)

Moore, J.H.; Cockshott, C.P.

1976-03-16

A radiation-sensitive switching circuit includes a light emitting diode which from time to time illuminates a photo-transistor, the photo-transistor serving when its output reaches a predetermined value to operate a trigger circuit. In order to allow for aging of the components, the current flow through the diode is increased when the output from the transistor falls below a known level. Conveniently, this is achieved by having a transistor in parallel with the diode, and turning the transistor off when the output from the phototransistor becomes too low. The circuit is designed to control the ignition system in an automobile engine.

Accessibility through user-centred and Inclusive Design processes

DEFF Research Database (Denmark)

Herriott, Richard

2014-01-01

This PhD dissertation addresses the subject of accessibility through user-centred and Inclusive Design processes (ID). The project takes as its starting point the observation that the concept of Inclusive Design is not adequately delimited. The supporting literature in the field of ID is structured...... around the fact that the needs of individuals with reduced capabilities compared to the norm (referred to for convenience as "the elderly and disabled") have not been properly addressed by standard design processes. In response to this fact, ID is a proposed design method to find more effective means...

Process design kit and circuits at a 2 µm technology node for flexible wearable electronics applications (Conference Presentation)

Science.gov (United States)

Torres-Miranda, Miguel; Petritz, Andreas; Gold, Herbert; Stadlober, Barbara

2016-09-01

In this work we present our most advanced technology node of organic thin film transistors (OTFTs) manufactured with a channel length as short as 2 μm by contact photolithography and a self-alignment process directly on a plastic substrate. Our process design kit (PDK) is described with P-type transistors, capacitors and 3 metal layers for connections of complex circuits. The OTFTs are composed of a double dielectric layer with a photopatternable ultra thin polymer (PNDPE) and alumina, with a thickness on the order of 100 nm. The organic semiconductor is either Pentacene or DNTT, which have a stable average mobility up to 0.1 cm2/Vs. Finally, a polymer (e.g.: Parylene-C) is used as a passivation layer. We describe also our design rules for the placement of standard circuit cells. A "plastic wafer" is fabricated containing 49 dies. Each die of 1 cm2 has between 25 to 50 devices, proving larger scale integration in such a small space, unique in organic technologies. Finally, we present the design (by simulations using a Spice model for OTFTs) and the test of analog and digital basic circuits: amplifiers with DC gains of about 20 dB, comparators, inverters and logic gates working in the frequency range of 1-10 kHz. These standard circuit cells could be used for signal conditioning and integrated as active matrices for flexible sensors from 3rd party institutions, thus opening our fab to new ideas and sophisticated pre-industrial low cost applications for the emerging fields of biomedical devices and wearable electronics for virtual/augmented reality.

A Novel Approach to Power Circuit Breaker Design for Replacement of SF6

Directory of Open Access Journals (Sweden)

D. J. Telfer

2004-01-01

Full Text Available This contribution explores the role of PTFE ablation in enhancing current interruption for various background gases in high voltage circuit breakers. An assessment of the current interruption capability has been made in terms of the arcing duration and the contact gap length at which critical arc extinction is achieved. These observations are supported by measurements of the magnitude of extinction and re-ignition voltage peaks. Most previous and other current experimental work on gas filled circuit breaker design follows conventional wisdom in investigating arcing behaviours at elevated gas pressures (usually up to 6 bar. But in this work we concentrate on the effects of using low gas pressures (less than 1 bar in the presence of a close-fitting shield of ablatant polymer material (PTFE that surrounds the electrode assembly of an experimental high power circuit breaker. We demonstrate that for several different gases, arc extinction capability compares well under these conditions with SF6, suggesting that SF6 could be replaced entirely in this novel system by more environmentally friendly gases. Moreover, the critical contact gap lengths at extinction are only slightly greater than when using SF6 at 6 bar. Weight loss measurements from the ablatant shield suggest that a chemical puffer action is the most likely mechanism for achieving the observed arc extinctions in this system.

Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS

Directory of Open Access Journals (Sweden)

David Bol

2011-01-01

Full Text Available Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust and energy-efficient ultra-low-voltage circuits in 65/45 nm CMOS under relaxed yet strict timing constraints.

Arithmetic circuits for DSP applications

CERN Document Server

Stouraitis, Thanos

2017-01-01

Arithmetic Circuits for DSP Applications is a complete resource on arithmetic circuits for digital signal processing (DSP). It covers the key concepts, designs and developments of different types of arithmetic circuits, which can be used for improving the efficiency of implementation of a multitude of DSP applications. Each chapter includes various applications of the respective class of arithmetic circuits along with information on the future scope of research. Written for students, engineers, and researchers in electrical and computer engineering, this comprehensive text offers a clear understanding of different types of arithmetic circuits used for digital signal processing applications. The text includes contributions from noted researchers on a wide range of topics, including a review o circuits used in implementing basic operations like additions and multiplications; distributed arithmetic as a technique for the multiplier-less implementation of inner products for DSP applications; discussions on look ...

Switchless charge-discharge circuit for electrical capacitance tomography

International Nuclear Information System (INIS)

Kryszyn, J; Smolik, W T; Radzik, B; Olszewski, T; Szabatin, R

2014-01-01

The main factor limiting the performance of electrical capacitance tomography (ECT) is an extremely low value of inter-electrode capacitances. The charge-discharge circuit is a well suited circuit for a small capacitance measurement due to its immunity to noise and stray capacitance, although it has a problem associated with a charge injected by the analogue switches, which results in a dc offset. This paper presents a new diode-based circuit for capacitance measurement in which a charge transfer method is realized without switches. The circuit was built and tested in one channel configuration with 16 multiplexed electrodes. The performance of the elaborated circuit and a comparison with a classic charge-discharge circuit are presented. The elaborated circuit can be used for sensors with inter-electrode capacitances not lower than 10 fF. The presented approach allows us to obtain a similar performance to the classic charge-discharge circuit, but has a simplified design. A lack of the need to synchronize the analogue switches in the transmitter and the receiver part of this circuit could be a desirable feature in the design of measurement systems integrated with electrodes. (paper)

Medical Equipment Tele- and Condition-Based Maintenance with Enhanced Remote Diagnostic Access (RDA) and Computer Vision

Science.gov (United States)

2010-04-01

failing to comply with a collection of information if it does not display a currently valid OMB control number. 1. REPORT DATE APR 2010 2. REPORT...The second is a ‘mechanical’ part that is controlled by circuit boards and is accessible by the technician via the serial console and running...was the use of conventional remote access solution designed for telecommuters or teleworkers in the Information Technology (IT) world, such as a

Development of 3D integrated circuits for HEP

International Nuclear Information System (INIS)

Yarema, R.; Fermilab

2006-01-01

Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented

Differential transimpedance amplifier circuit for correlated differential amplification

Science.gov (United States)

Gresham, Christopher A [Albuquerque, NM; Denton, M Bonner [Tucson, AZ; Sperline, Roger P [Tucson, AZ

2008-07-22

A differential transimpedance amplifier circuit for correlated differential amplification. The amplifier circuit increase electronic signal-to-noise ratios in charge detection circuits designed for the detection of very small quantities of electrical charge and/or very weak electromagnetic waves. A differential, integrating capacitive transimpedance amplifier integrated circuit comprising capacitor feedback loops performs time-correlated subtraction of noise.

Considerations on Circuit Design and Data Acquisition of a Portable Surface Plasmon Resonance Biosensing System

Directory of Open Access Journals (Sweden)

Keke Chang

2015-08-01

Full Text Available The aim of this study was to develop a circuit for an inexpensive portable biosensing system based on surface plasmon resonance spectroscopy. This portable biosensing system designed for field use is characterized by a special structure which consists of a microfluidic cell incorporating a right angle prism functionalized with a biomolecular identification membrane, a laser line generator and a data acquisition circuit board. The data structure, data memory capacity and a line charge-coupled device (CCD array with a driving circuit for collecting the photoelectric signals are intensively focused on and the high performance analog-to-digital (A/D converter is comprehensively evaluated. The interface circuit and the photoelectric signal amplifier circuit are first studied to obtain the weak signals from the line CCD array in this experiment. Quantitative measurements for validating the sensitivity of the biosensing system were implemented using ethanol solutions of various concentrations indicated by volume fractions of 5%, 8%, 15%, 20%, 25%, and 30%, respectively, without a biomembrane immobilized on the surface of the SPR sensor. The experiments demonstrated that it is possible to detect a change in the refractive index of an ethanol solution with a sensitivity of 4.99838 × 105 ΔRU/RI in terms of the changes in delta response unit with refractive index using this SPR biosensing system, whereby the theoretical limit of detection of 3.3537 × 10−5 refractive index unit (RIU and a high linearity at the correlation coefficient of 0.98065. The results obtained from a series of tests confirmed the practicality of this cost-effective portable SPR biosensing system.

Microphotonic devices for compact planar lightwave circuits and sensor systems

Science.gov (United States)

Cardenas Gonzalez, Jaime

2005-07-01

Higher levels of integration in planar lightwave circuits and sensor systems can reduce fabrication costs and broaden viable applications for optical network and sensor systems. For example, increased integration and functionality can lead to sensor systems that are compact enough for easy transport, rugged enough for field applications, and sensitive enough even for laboratory applications. On the other hand, more functional and compact planar lightwave circuits can make optical networks components less expensive for the metro and access markets in urban areas and allow penetration of fiber to the home. Thus, there is an important area of opportunity for increased integration to provide low cost, compact solutions in both network components and sensor systems. In this dissertation, a novel splitting structure for microcantilever deflection detection is introduced. The splitting structure is designed so that its splitting ratio is dependent on the vertical position of the microcantilever. With this structure, microcantilevers sensitized to detect different analytes or biological agents can be integrated into an array on a single chip. Additionally, the integration of a depolarizer into the optoelectronic integrated circuit in an interferometric fiber optic gyroscope is presented as a means for cost reduction. The savings come in avoiding labor intensive fiber pigtailing steps by permitting batch fabrication of these components. In particular, this dissertation focuses on the design of the waveguides and polarization rotator, and the impact of imperfect components on the performance of the depolarizer. In the area of planar lightwave circuits, this dissertation presents the development of a fabrication process for single air interface bends (SAIBs). SAIBs can increase integration by reducing the area necessary to make a waveguide bend. Fabrication and measurement of a 45° SAIB with a bend efficiency of 93.4% for TM polarization and 92.7% for TE polarization are

Electric Circuit Model Analogy for Equilibrium Lattice Relaxation in Semiconductor Heterostructures

Science.gov (United States)

Kujofsa, Tedi; Ayers, John E.

2018-01-01

The design and analysis of semiconductor strained-layer device structures require an understanding of the equilibrium profiles of strain and dislocations associated with mismatched epitaxy. Although it has been shown that the equilibrium configuration for a general semiconductor strained-layer structure may be found numerically by energy minimization using an appropriate partitioning of the structure into sublayers, such an approach is computationally intense and non-intuitive. We have therefore developed a simple electric circuit model approach for the equilibrium analysis of these structures. In it, each sublayer of an epitaxial stack may be represented by an analogous circuit configuration involving an independent current source, a resistor, an independent voltage source, and an ideal diode. A multilayered structure may be built up by the connection of the appropriate number of these building blocks, and the node voltages in the analogous electric circuit correspond to the equilibrium strains in the original epitaxial structure. This enables analysis using widely accessible circuit simulators, and an intuitive understanding of electric circuits can easily be extended to the relaxation of strained-layer structures. Furthermore, the electrical circuit model may be extended to continuously-graded epitaxial layers by considering the limit as the individual sublayer thicknesses are diminished to zero. In this paper, we describe the mathematical foundation of the electrical circuit model, demonstrate its application to several representative structures involving In x Ga1- x As strained layers on GaAs (001) substrates, and develop its extension to continuously-graded layers. This extension allows the development of analytical expressions for the strain, misfit dislocation density, critical layer thickness and widths of misfit dislocation free zones for a continuously-graded layer having an arbitrary compositional profile. It is similar to the transition from circuit

Quantification, modelling and design for signal history dependent effects in mixed-signal SOI/SOS circuits

International Nuclear Information System (INIS)

Edwards, C.F.; Redman-White, W.; Bracey, M.; Tenbroek, B.M.; Lee, M.S.; Uren, M.J.; Brunson, K.M.

1999-01-01

This paper deals with how the radiation hardness of mixed signal SOI/SOS CMOS circuits is taken into account at both architectural terms as well as the the transistor level cell designs. The primary issue is to deal with divergent transistor threshold shifts, and to understand the effects of large amplitude non stationary signals on analogue cell behaviour. (authors)

The Maplin electronic circuits handbook

CERN Document Server

Tooley, Michael

1990-01-01

The Maplin Electronic Circuits Handbook provides pertinent data, formula, explanation, practical guidance, theory and practical guidance in the design, testing, and construction of electronic circuits. This book discusses the developments in electronics technology techniques.Organized into 11 chapters, this book begins with an overview of the common types of passive component. This text then provides the reader with sufficient information to make a correct selection of passive components for use in the circuits. Other chapters consider the various types of the most commonly used semiconductor

A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMS

KAUST Repository

Dadgour, Hamed F.; Hussain, Muhammad Mustafa; Banerjee, Kaustav

2010-01-01

. While this in itself is a major improvement, its implications for minimizing Boolean functions using Karnaugh maps (K-maps) are even more significant. In the standard K-map technique, which is used in digital circuit design, adjacent "1s" (minterms

A New Simple Chaotic Circuit Based on Memristor

Science.gov (United States)

Wu, Renping; Wang, Chunhua

In this paper, a new memristor is proposed, and then an emulator built from off-the-shelf solid state components imitating the behavior of the proposed memristor is presented. Multisim simulation and breadboard experiment are done on the emulator, exhibiting a pinched hysteresis loop in the voltage-current plane when the emulator is driven by a periodic excitation voltage. In addition, a new simple chaotic circuit is designed by using the proposed memristor and other circuit elements. It is exciting that this circuit with only a linear negative resistor, a capacitor, an inductor and a memristor can generate a chaotic attractor. The dynamical behaviors of the proposed chaotic system are analyzed by Lyapunov exponents, phase portraits and bifurcation diagrams. Finally, an electronic circuit is designed to implement the chaotic system. For the sake of simple circuit topology, the proposed chaotic circuit can be easily manufactured at low cost.

Designing Broadband Access Networks with Triple Redundancy

DEFF Research Database (Denmark)

Pedersen, Jens Myrup; Riaz, Muhammad Tahir; Knudsen, Thomas Phillip

2005-01-01

An architecture is proposed for designing broadband access networks, which offer triple redundancy to the end users, resulting in networks providing connectivity even in case of any two independent node or line failures. Two physically independent connections are offered by fiber, and the last...... provided by some wireless solution. Based on experience with planning Fiber To The Home, the architecture is designed to meet a number of demands, making it practicable and useful in realworld network planning. The proposed wired topology is planar, and suitable for being fitted onto the road network...

A Testable Design Method for Memories by Boundary Scan Technique

Directory of Open Access Journals (Sweden)

Qiao Guo-Hui

2016-01-01

Full Text Available This paper presents a design for test the embedded flash in an object System-on-a-chip (SoC. The feature of the Flash TAP (Test Access Port complies with the IEEE std.1149.1, and it can select different scan chains and other control registers for other test. By the trade-off between the test time and the circuit area, an IST (In System Test circuit is designed in the SoC. Experiment results on the embedded memory have shown that the proposed method costs small testing timing by the use of IST.

Circuit for Communication Over Power Lines

Science.gov (United States)

Krasowski, Michael J.; Prokop, Normal F.; Greer, Lawrence C., III; Nappier, Jennifer

2011-01-01

Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

Circuit modeling for electromagnetic compatibility

CERN Document Server

Darney, Ian B

2013-01-01

Very simply, electromagnetic interference (EMI) costs money, reduces profits, and generally wreaks havoc for circuit designers in all industries. This book shows how the analytic tools of circuit theory can be used to simulate the coupling of interference into, and out of, any signal link in the system being reviewed. The technique is simple, systematic and accurate. It enables the design of any equipment to be tailored to meet EMC requirements. Every electronic system consists of a number of functional modules interconnected by signal links and power supply lines. Electromagnetic interference

Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

Science.gov (United States)

Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

2015-10-14

We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

Alternative Design Concepts for Multi-Circuit HTS Link Systems

CERN Document Server

Ballarino, A

2011-01-01

Superconducting cables for power transmission usually contain two conductors for DC application, or three conductors for AC, with high voltage insulation. In contrast, for some applications related to accelerators it is convenient to transfer high currents via superconducting links feeding a number of circuits at relatively low voltage, of the order of a kilovolt, over distances of up to a few hundred meters. For power transmission applications based on cooling via sub-cooled liquid nitrogen, suitable HTS conductors are only available in the form of tape, and a multi-layer variant can be envisaged for the multi-circuit links. However, where cooling to temperatures of the order of 20 K is feasible, MgB2 conductor, available in the form of both tape and wire, can also be envisaged and in the latter case used to assemble round cables. There are, therefore, two distinct topologies - based on the use of wires or tapes - that can be envisaged for use in applications to multi-circuit link systems. In this paper the ...

Reactor protection system design using application specific integrated circuits

International Nuclear Information System (INIS)

Battle, R.E.; Bryan, W.L.; Kisner, R.A.; Wilson, T.L. Jr.

1992-01-01

Implementing reactor protection systems (RPS) or other engineering safeguard systems with application specific integrated circuits (ASICs) offers significant advantages over conventional analog or software based RPSs. Conventional analog RPSs suffer from setpoints drifts and large numbers of discrete analog electronics, hardware logic, and relays which reduce reliability because of the large number of potential failures of components or interconnections. To resolve problems associated with conventional discrete RPSs and proposed software based RPS systems, a hybrid analog and digital RPS system implemented with custom ASICs is proposed. The actual design of the ASIC RPS resembles a software based RPS but the programmable software portion of each channel is implemented in a fixed digital logic design including any input variable computations. Set point drifts are zero as in proposed software systems, but the verification and validation of the computations is made easier since the computational logic an be exhaustively tested. The functionality is assured fixed because there can be no future changes to the ASIC without redesign and fabrication. Subtle error conditions caused by out of order evaluation or time dependent evaluation of system variables against protection criteria are eliminated by implementing all evaluation computations in parallel for simultaneous results. On- chip redundancy within each RPS channel and continuous self-testing of all channels provided enhanced assurance that a particular channel is available and faults are identified as soon as possible for corrective actions. The use of highly integrated ASICs to implement channel electronics rather than the use of discrete electronics greatly reduces the total number of components and interconnections in the RPS to further increase system reliability. A prototype ASIC RPS channel design and the design environment used for ASIC RPS systems design is discussed

Microelectronics from fundamentals to applied design

CERN Document Server

Di Paolo Emilio, Maurizio

2016-01-01

This book serves as a practical guide for practicing engineers who need to design analog circuits for microelectronics.  Readers will develop a comprehensive understanding of the basic techniques of analog modern electronic circuit design, discrete and integrated, application as sensors and control and data acquisition systems,and techniques of PCB design.  ·         Describes fundamentals of microelectronics design in an accessible manner; ·         Takes a problem-solving approach to the topic, offering a hands-on guide for practicing engineers; ·         Provides realistic examples to inspire a thorough understanding of system-level issues, before going into the detail of components and devices; ·         Uses a new approach and provides several skills that help engineers and designers retain key and advanced concepts.

Integrated electric circuit CAD system in Minolta Camera Co. Ltd

Energy Technology Data Exchange (ETDEWEB)

Nakagami, Tsuyoshi; Hirata, Sumiaki; Matsumura, Fumihiko

1988-08-26

Development background, fundamental concept, details and future plan of the integrated electric circuit CAD system for OA equipment are presented. The central integrated database is basically intended to store experiences or know-hows, to cover the wide range of data required for designs, and to provide a friendly interface. This easy-to-use integrated database covers the drawing data, parts information, design standards, know-hows and system data. The system contains the circuit design function to support drawing circuit diagrams, the wiring design function to support the wiring and arrangement of printed circuit boards and various parts integratedly, and the function to verify designs, to make full use of parts or technical information, to maintain the system security. In the future, as the system will be wholly in operation, the design period reduction, quality improvement and cost saving will be attained by this integrated design system. (19 figs, 2 tabs)

Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for Fabrication with 0.09-micron High Electron Mobility Transistors (HEMTs) using 2-mil Gallium Nitride (GaN) on Silicon Carbide (SiC)

Science.gov (United States)

2016-03-01

ARL-TN-0743 ● MAR 2016 US Army Research Laboratory Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for...originator. ARL-TN-0743 ● MAR 2016 US Army Research Laboratory Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo...To) October 2015–January 2016 4. TITLE AND SUBTITLE Microwave Integrated Circuit Amplifier Designs Submitted to Qorvo for Fabrication with 0.09

Equivalent circuit analysis of terahertz metamaterial filters

KAUST Repository

Zhang, Xueqian

2011-01-01

An equivalent circuit model for the analysis and design of terahertz (THz) metamaterial filters is presented. The proposed model, derived based on LMC equivalent circuits, takes into account the detailed geometrical parameters and the presence of a dielectric substrate with the existing analytic expressions for self-inductance, mutual inductance, and capacitance. The model is in good agreement with the experimental measurements and full-wave simulations. Exploiting the circuit model has made it possible to predict accurately the resonance frequency of the proposed structures and thus, quick and accurate process of designing THz device from artificial metamaterials is offered. ©2011 Chinese Optics Letters.

Maximum Temperature Detection System for Integrated Circuits

Science.gov (United States)

Frankiewicz, Maciej; Kos, Andrzej

2015-03-01

The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

Coplanar strips for Josephson voltage standard circuits

International Nuclear Information System (INIS)

Schubert, M.; May, T.; Wende, G.; Fritzsch, L.; Meyer, H.-G.

2001-01-01

We present a microwave circuit for Josephson voltage standards. Here, the Josephson junctions are integrated in a microwave transmission line designed as coplanar strips (CPS). The new layout offers the possibility of achieving a higher scale of integration and to considerably simplify the fabrication technology. The characteristic impedance of the CPS is about 50 Ω, and this should be of interest for programmable Josephson voltage standard circuits with SNS or SINIS junctions. To demonstrate the function of the microwave circuit design, conventional 10 V Josephson voltage standard circuits with 17000 Nb/AlO x /Nb junctions were prepared and tested. Stable Shapiro steps at the 10 V level were generated. Furthermore, arrays of 1400 SINIS junctions in this microwave layout exhibited first-order Shapiro steps. Copyright 2001 American Institute of Physics

Energy-efficient neuron, synapse and STDP integrated circuits.

Science.gov (United States)

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

Topology Optimization of Building Blocks for Photonic Integrated Circuits

DEFF Research Database (Denmark)

Jensen, Jakob Søndergaard; Sigmund, Ole

2005-01-01

Photonic integrated circuits are likely candidates as high speed replacements for the standard electrical integrated circuits of today. However, in order to obtain a satisfactorily performance many design prob- lems that up until now have resulted in too high losses must be resolved. In this work...... we demonstrate how the method of topology optimization can be used to design a variety of high performance building blocks for the future circuits....

Thermal measurement a requirement for monolithic microwave integrated circuit design

OpenAIRE

Hopper, Richard; Oxley, C. H.

2008-01-01

The thermal management of structures such as Monolithic Microwave Integrated Circuits (MMICs) is important, given increased circuit packing densities and RF output powers. The paper will describe the IR measurement technology necessary to obtain accurate temperature profiles on the surface of semiconductor devices. The measurement procedure will be explained, including the device mounting arrangement and emissivity correction technique. The paper will show how the measurement technique has be...

Human engineering considerations in designing a computerized controlled access security system

International Nuclear Information System (INIS)

Moore, J.W.; Banks, W.W.

1988-01-01

This paper describes a human engineering effort in the design of a major security system upgrade at Lawrence Livermore National Laboratory. This upgrade was to be accomplished by replacing obsolete and difficult-to-man (i.e., multiple operator task actions required) security equipment and systems with a new, automated, computer-based access control system. The initial task was to assist the electronic and mechanical engineering staff in designing a computerized security access system too functionally and ergonomically accommodate 100% of the Laboratory user population. The new computerized access system was intended to control entry into sensitive exclusion areas by requiring personnel to use an entry booth-based system and/or a remote access control panel system. The primary user interface with the system was through a control panel containing a magnetic card reader, function buttons, LCD display, and push-button keypad

Impact of line edge roughness on the performance of 14-nm FinFET: Device-circuit Co-design

Science.gov (United States)

Rathore, Rituraj Singh; Rana, Ashwani K.

2018-01-01

With the evolution of sub-20 nm FinFET technology, line edge roughness (LER) has been identified as a critical problem and may result in critical device parameter variation and performance limitation in the future VLSI circuit application. In the present work, an analytical model of fin-LER has been presented, which shows the impact of correlated and uncorrelated LER on FinFET structure. Further, the influence of correlated and uncorrelated fin- LER on all electrical performance parameters is thoroughly investigated using the three-dimensional (3-D) Technology Computer Aided Design (TCAD) simulations for 14-nm technology node. Moreover, the impact of all possible fin shapes on threshold voltage (VTH), drain induced barrier lowering (DIBL), on-current (ION), and off-current (IOFF) has been compared with the well calibrated rectangular FinFET structure. In addition, the influence of all possible fin geometries on the read stability of six-transistor (6-T) Static-Random-Access-Memory (SRAM) has been investigated. The study reveals that fin-LER plays a vital role as it directly governs the electrostatics of the FinFET structure. This has been found that there is a high degree of fluctuations in all performance parameters for uncorrelated fin-LER type FinFETs as compared to correlated fin-LER with respect to rectangular FinFET structure. This paper gives physical insight of FinFET design, especially in sub-20 nm technology nodes by concluding that the impact of LER on electrical parameters are minimum for correlated LER.

Circuit Implementation of Coronary Artery Chaos Phenomenon and Optimal PID Synchronization Controller Design

Directory of Open Access Journals (Sweden)

Cheng-Yu Yeh

2012-01-01

Full Text Available This study aimed at the implementation and synchronization control of cardiac circuit. First, the MATLAB-Simulink was used to simulate the dynamic behavior of cardiac chaotic circuit, and simple electronic modules were used to implement the cardiac system. Then the Particle Swarm Optimization (PSO was used to seek for the proportional, integral, and derivative gains of optimal PID controller, and the PID controller which could synchronize the slave cardiac circuit and the master cardiac circuit was obtained, in order to synchronize the master/slave chaotic cardiac circuits. This method can be provided for cardiac doctors to diagnose and medicate cardiac abnormality.

High voltage short plus generation based on avalanche circuit

International Nuclear Information System (INIS)

Hu Yuanfeng; Yu Xiaoqi

2006-01-01

Simulate the avalanche circuit in series with PSPICE module, design the high voltage short plus generation circuit by avalanche transistor in series for the sweep deflection circuit of streak camera. The output voltage ranges 1.2 KV into 50 ohm load. The rise time of the circuit is less than 3 ns. (authors)

Low-Noise CMOS Circuits for On-Chip Signal Processing in Focal-Plane Arrays

Science.gov (United States)

Pain, Bedabrata

The performance of focal-plane arrays can be significantly enhanced through the use of on-chip signal processing. Novel, in-pixel, on-focal-plane, analog signal-processing circuits for high-performance imaging are presented in this thesis. The presence of a high background-radiation is a major impediment for infrared focal-plane array design. An in-pixel, background-suppression scheme, using dynamic analog current memory circuit, is described. The scheme also suppresses spatial noise that results from response non-uniformities of photo-detectors, leading to background limited infrared detector readout performance. Two new, low-power, compact, current memory circuits, optimized for operation at ultra-low current levels required in infrared-detection, are presented. The first one is a self-cascading current memory that increases the output impedance, and the second one is a novel, switch feed-through reducing current memory, implemented using error-current feedback. This circuit can operate with a residual absolute -error of less than 0.1%. The storage-time of the memory is long enough to also find applications in neural network circuits. In addition, a voltage-mode, accurate, low-offset, low-power, high-uniformity, random-access sample-and-hold cell, implemented using a CCD with feedback, is also presented for use in background-suppression and neural network applications. A new, low noise, ultra-low level signal readout technique, implemented by individually counting photo-electrons within the detection pixel, is presented. The output of each unit-cell is a digital word corresponding to the intensity of the photon flux, and the readout is noise free. This technique requires the use of unit-cell amplifiers that feature ultra-high-gain, low-power, self-biasing capability and noise in sub-electron levels. Both single-input and differential-input implementations of such amplifiers are investigated. A noise analysis technique is presented for analyzing sampled

Design and Preliminary Results of a Feedback Circuit for Plasma Displacement Control in IR-T1 Tokamak

International Nuclear Information System (INIS)

TalebiTaher, A.; Ghoranneviss, M.; Tarkeshian, R.; Salem, M. K.; Khorshid, P.

2008-01-01

Since displacement is very important for plasma position control, in IR-T1 tokamak a combination of two cosine coils and two saddle sine coils is used for horizontal displacement measurement. According to the multiple moment theory, the output of these coils linearly depends to radial displacement of plasma column. A new circuit for adding these signals to feedback system designed and unwanted effects of other fields in final output compensated. After compensation and calibration of the system, the output of horizontal displacement circuits applied to feedback control system. By considers the required auxiliary vertical field, a proportional amplifier and driver circuit are constructed to drive power transistors these power transistors switch the feedback bank capacitors. In the experiment, a good linear proportionality between displacement and output observed by applying an appropriate feedback field, the linger confinement time in IR-T1 tokamak obtained, applying this system to discharge increased the plasma duration and realizes repetitive discharges

Rational design of modular circuits for gene transcription: A test of the bottom-up approach

Directory of Open Access Journals (Sweden)

Giordano Emanuele

2010-11-01

Full Text Available Abstract Background Most of synthetic circuits developed so far have been designed by an ad hoc approach, using a small number of components (i.e. LacI, TetR and a trial and error strategy. We are at the point where an increasing number of modular, inter-changeable and well-characterized components is needed to expand the construction of synthetic devices and to allow a rational approach to the design. Results We used interchangeable modular biological parts to create a set of novel synthetic devices for controlling gene transcription, and we developed a mathematical model of the modular circuits. Model parameters were identified by experimental measurements from a subset of modular combinations. The model revealed an unexpected feature of the lactose repressor system, i.e. a residual binding affinity for the operator site by induced lactose repressor molecules. Once this residual affinity was taken into account, the model properly reproduced the experimental data from the training set. The parameters identified in the training set allowed the prediction of the behavior of networks not included in the identification procedure. Conclusions This study provides new quantitative evidences that the use of independent and well-characterized biological parts and mathematical modeling, what is called a bottom-up approach to the construction of gene networks, can allow the design of new and different devices re-using the same modular parts.