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Sample records for wave integrated circuit

  1. Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

    Science.gov (United States)

    Pavlidis, Dimitris

    1991-01-01

    The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

  2. InP HEMT Integrated Circuits for Submillimeter Wave Radiometers in Earth Remote Sensing

    Science.gov (United States)

    Deal, William R.; Chattopadhyay, Goutam

    2012-01-01

    The operating frequency of InP integrated circuits has pushed well into the Submillimeter Wave frequency band, with amplification reported as high as 670 GHz. This paper provides an overview of current performance and potential application of InP HEMT to Submillimeter Wave radiometers for earth remote sensing.

  3. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication.

    Science.gov (United States)

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-02-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

  4. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

    Science.gov (United States)

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-02-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

  5. Metamaterial CRLH Antennas on Silicon Substrate for Millimeter-Wave Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Gheorghe Ioan Sajin

    2012-01-01

    Full Text Available The paper presents two composite right/left-handed (CRLH coplanar waveguide (CPW zeroth-order resonant (ZOR antennas which were designed, processed, and electrically characterized for applications in the millimetric wave frequency range. Two CRLH antennas were developed for f=27 GHz and f=38.5, GHz, respectively. The CRLH antenna on f=27 GHz shows a return loss of RL<−18.78 dB at f=26.88 GHz. The −3 dB radiation characteristic beamwidth was approximately 37° and the gain was Gi=2.82 dBi. The CRLH antenna on f=38.5 GHz has a return loss of RL<−38.5 dB at f=38.82 GHz and the −3 dB radiation characteristic beamwidth of approximately 17°. The gains were Gi=1.08 dBi at f=38 GHz and Gi=1.2 dBi at f=38.6 GHz. The maximum measured gain was Gi=1.75 dBi at f=38.2 GHz. It is, upon the authors' knowledge, the first report of millimeter wave CRLH antennas on silicon substrate in CPW technique for use in mm-wave monolithic integrated circuit.

  6. Disposable photonic integrated circuits for evanescent wave sensors by ultra-high volume roll-to-roll method.

    Science.gov (United States)

    Aikio, Sanna; Hiltunen, Jussi; Hiitola-Keinänen, Johanna; Hiltunen, Marianne; Kontturi, Ville; Siitonen, Samuli; Puustinen, Jarkko; Karioja, Pentti

    2016-02-08

    Flexible photonic integrated circuit technology is an emerging field expanding the usage possibilities of photonics, particularly in sensor applications, by enabling the realization of conformable devices and introduction of new alternative production methods. Here, we demonstrate that disposable polymeric photonic integrated circuit devices can be produced in lengths of hundreds of meters by ultra-high volume roll-to-roll methods on a flexible carrier. Attenuation properties of hundreds of individual devices were measured confirming that waveguides with good and repeatable performance were fabricated. We also demonstrate the applicability of the devices for the evanescent wave sensing of ambient refractive index. The production of integrated photonic devices using ultra-high volume fabrication, in a similar manner as paper is produced, may inherently expand methods of manufacturing low-cost disposable photonic integrated circuits for a wide range of sensor applications.

  7. Millimeter-Wave Integrated Circuit Design for Wireless and Radar Applications

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Krozer, Viktor; Vidkjær, Jens

    2006-01-01

    This paper describes a quadrature voltage-controlled oscillator (QVCO), frequency doubler, and sub-harmonic mixer (SHM) for a millimeter-wave (mm-wave) front-end implemented in a high-speed InP DHBT technology. The QVCO exhibits large tuning range from 38 to 47.8 GHz with an output power around -15...... from 40-50 GHz. To the authors knowledge the QVCO, frequency doubler, and SHM presents the first mm-wave implementations of these circuits in InP DHBT technology....

  8. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  9. Silicon Photonics Integrated Circuits for 5th Generation mm-Wave Wireless Communications

    DEFF Research Database (Denmark)

    Rommel, Simon; Vegas Olmos, Juan José; Tafur Monroy, Idelfonso

    Hybrid photonic-wireless transmission schemes in the mm-wave frequency are promising candidates to enable the multi-gigabit per second data communications required from wireless and mobile networks of the 5th and future generations. Photonic integration may pave the way to practical applicability...

  10. mm-Wave Wireless Communications based on Silicon Photonics Integrated Circuits

    DEFF Research Database (Denmark)

    Rommel, Simon; Heck, Martijn; Vegas Olmos, Juan José

    Hybrid photonic-wireless transmission schemes in the mm-wave frequency range are promising candidates to enable the multi-gigabit per second data communications required from wireless and mobile networks of the 5th and future generations. Photonic integration may pave the way to practical...

  11. Silicon Photonics Integrated Circuits for 5th Generation mm-Wave Wireless Communications

    DEFF Research Database (Denmark)

    Rommel, Simon; Vegas Olmos, Juan José; Tafur Monroy, Idelfonso

    Hybrid photonic-wireless transmission schemes in the mm-wave frequency are promising candidates to enable the multi-gigabit per second data communications required from wireless and mobile networks of the 5th and future generations. Photonic integration may pave the way to practical applicability...... of such photonic-wireless hybrid links by reduction in complexity, size and – most importantly – cost....

  12. Photonic Integrated Circuits

    Science.gov (United States)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  13. Integrated Circuit Immunity

    Science.gov (United States)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  14. Integrated circuit cell library

    Science.gov (United States)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  15. Linear integrated circuits

    CERN Document Server

    Carr, Joseph

    1996-01-01

    The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

  16. Synthetic biology: integrated gene circuits.

    Science.gov (United States)

    Nandagopal, Nagarajan; Elowitz, Michael B

    2011-09-02

    A major goal of synthetic biology is to develop a deeper understanding of biological design principles from the bottom up, by building circuits and studying their behavior in cells. Investigators initially sought to design circuits "from scratch" that functioned as independently as possible from the underlying cellular system. More recently, researchers have begun to develop a new generation of synthetic circuits that integrate more closely with endogenous cellular processes. These approaches are providing fundamental insights into the regulatory architecture, dynamics, and evolution of genetic circuits and enabling new levels of control across diverse biological systems.

  17. Integrated circuit cooled turbine blade

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.; Holloman, Harry; Koester, Steven

    2017-08-29

    A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channel connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.

  18. Optoelectronic cross-injection locking of a dual-wavelength photonic integrated circuit for low-phase-noise millimeter-wave generation.

    Science.gov (United States)

    Kervella, Gaël; Van Dijk, Frederic; Pillet, Grégoire; Lamponi, Marco; Chtioui, Mourad; Morvan, Loïc; Alouini, Mehdi

    2015-08-01

    We report on the stabilization of a 90-GHz millimeter-wave signal generated from a fully integrated photonic circuit. The chip consists of two DFB single-mode lasers whose optical signals are combined on a fast photodiode to generate a largely tunable heterodyne beat note. We generate an optical comb from each laser with a microwave synthesizer, and by self-injecting the resulting signal, we mutually correlate the phase noise of each DFB and stabilize the beatnote on a multiple of the frequency delivered by the synthesizer. The performances achieved beat note linewidth below 30 Hz.

  19. Variational integrators for electric circuits

    Energy Technology Data Exchange (ETDEWEB)

    Ober-Blöbaum, Sina, E-mail: sinaob@math.upb.de [Computational Dynamics and Optimal Control, University of Paderborn (Germany); Tao, Molei [Courant Institute of Mathematical Sciences, New York University (United States); Cheng, Mulin [Applied and Computational Mathematics, California Institute of Technology (United States); Owhadi, Houman; Marsden, Jerrold E. [Control and Dynamical Systems, California Institute of Technology (United States); Applied and Computational Mathematics, California Institute of Technology (United States)

    2013-06-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator.

  20. Design of Integrated Circuits Approaching Terahertz Frequencies

    DEFF Research Database (Denmark)

    Yan, Lei

    In this thesis, monolithic microwave integrated circuits(MMICs) are presented for millimeter-wave and submillimeter-wave or terahertz(THz) applications. Millimeter-wave power generation from solid state devices is not only crucial for the emerging high data rate wireless communications but also...... are designed based on the monolithic membrane supported Schottky diodes, which is under development at Chalmers University of Technology, Sweden. To simplify the baseband circuitry, the received IF signal from the subharmonic mixer is further amplified and downconverted to the DC range with a low noise...

  1. Invention of the Integrated Circuit

    Indian Academy of Sciences (India)

    Home; Journals; Resonance – Journal of Science Education; Volume 17; Issue 11. Invention of the Integrated Circuit. Jack S Kilby. Classics Volume 17 Issue 11 November 2012 pp 1100-1115. Fulltext. Click here to view fulltext PDF. Permanent link: http://www.ias.ac.in/article/fulltext/reso/017/11/1100-1115 ...

  2. Development of CMOS integrated circuits

    Science.gov (United States)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  3. Bioluminescent bioreporter integrated circuits (BBICs)

    Science.gov (United States)

    Simpson, Michael L.; Sayler, Gary S.; Nivens, David; Ripp, Steve; Paulus, Michael J.; Jellison, Gerald E.

    1998-07-01

    As the workhorse of the integrated circuit (IC) industry, the capabilities of CMOS have been expanded well beyond the original applications. The full spectrum of analog circuits from switched-capacitor filters to microwave circuit blocks, and from general-purpose operational amplifiers to sub- nanosecond analog timing circuits for nuclear physics experiments have been implemented in CMOS. This technology has also made in-roads into the growing area of monolithic sensors with devices such as active-pixel sensors and other electro-optical detection devices. While many of the processes used for MEMS fabrication are not compatible with the CMOS IC process, depositing a sensor material onto a previously fabricated CMOS circuit can create a very useful category of sensors. In this work we report a chemical sensor composed of bioluminescent bioreporters (genetically engineered bacteria) deposited onto a micro-luminometer fabricated in a standard CMOS IC process. The bioreporter used for this work emitted 490-nm light when exposed to toluene. This luminescence was detected by the micro- luminometer giving an indication of the concentration of toluene. Other bioluminescent bioreporters sensitive to explosives, mercury, and other organic chemicals and heavy metals have been reported. These could be incorporated (individually or in combination) with the micro-luminometer reported here to form a variety of chemical sensors.

  4. Full Wave Analysis of Passive Microwave Monolithic Integrated Circuit Devices Using a Generalized Finite Difference Time Domain (GFDTD) Algorithm

    Science.gov (United States)

    Lansing, Faiza S.; Rascoe, Daniel L.

    1993-01-01

    This paper presents a modified Finite-Difference Time-Domain (FDTD) technique using a generalized conformed orthogonal grid. The use of the Conformed Orthogonal Grid, Finite Difference Time Domain (GFDTD) enables the designer to match all the circuit dimensions, hence eliminating a major source o error in the analysis.

  5. Integrated circuits for multimedia applications

    DEFF Research Database (Denmark)

    Vandi, Luca

    2007-01-01

    , and it is applied to a broad-band dual-loop receiver architecture in order to boost the linearity performances of the stage. A simplified noise- and linearity analysis of the circuit is derived, and a comparison is provided with a more traditional dual-loop topology (a broad-band stage based on shunt......This work presents several key aspects in the design of RF integrated circuits for portable multimedia devices. One chapter is dedicated to the application of negative-feedback topologies to receiver frontends. A novel feedback technique suitable for common multiplier-based mixers is described......-series feedback), showing a difference in compression point in the order of 10dBm for the same power consumption. The same principle is also applied to a more conventional narrow-band stage in which a single loop is employed in order to enhance noise performances. Noise analysis shows sensible improvements...

  6. 1.25  GHz sine wave gating InGaAs/InP single-photon detector with a monolithically integrated readout circuit.

    Science.gov (United States)

    Jiang, Wen-Hao; Liu, Jian-Hong; Liu, Yin; Jin, Ge; Zhang, Jun; Pan, Jian-Wei

    2017-12-15

    InGaAs/InP single-photon detectors (SPDs) are the key devices for applications requiring near-infrared single-photon detection. The gating mode is an effective approach to synchronous single-photon detection. Increasing gating frequency and reducing the module size are important challenges for the design of such a detector system. Here we present for the first time, to the best of our knowledge, an InGaAs/InP SPD with 1.25 GHz sine wave gating (SWG) using a monolithically integrated readout circuit (MIRC). The MIRC has a size of 15  mm×15  mm and implements the miniaturization of avalanche extraction for high-frequency SWG. In the MIRC, low-pass filters and a low-noise radio frequency amplifier are integrated based on the technique of low temperature co-fired ceramic, which can effectively reduce the parasitic capacitance and extract weak avalanche signals. We then characterize the InGaAs/InP SPD to verify the functionality and reliability of the MIRC, and the SPD exhibits excellent performance with 27.5% photon detection efficiency, a 1.2 kcps dark count rate, and 9.1% afterpulse probability at 223 K and 100 ns hold-off time. With this MIRC, one can further design miniaturized high-frequency SPD modules that are highly required for practical applications.

  7. Next Generation Mid-Wave Infrared Cascaded Light Emitting Diodes: Growth of Broadband, Multispectral, and Single Color Devices on Gaas and Integrated Circuits

    Science.gov (United States)

    Provence, Sydney R.

    InAs/GaSb superlattices are an attractive material system for infrared light emitting diodes, due to the ability to tune the band gap throughout most of the infrared regime. A key consideration in the epitaxial growth of these heterostructures is crystalline material quality. In developing thick layers of epitaxially grown material, there are moderate amounts of elastic strain that can be incorporated into a heterostructure, beyond which deformations will form that will alleviate the lattice mismatch. This thesis investigates the optical and electronic properties of lattice-mismatched and strained materials through the study of thick dual-color light emitting diodes, broadband light emitting diodes, and InAs/GaSb superlattice devices developed on GaAs substrates and GaAs integrated circuits. A dual-color infrared light emitting diode is demonstrated emitting in the mid-wave infrared band at 3.81 mum and 4.72 mum. The design of the device stacks two independently operable InAs/GaSb superlattices structures on top of one another, so that 10 mum of material is grown with molecular beam epitaxy. Each layer is lattice-matched to a GaSb substrate. At quasi-continuous operation, radiances of 5.48 W/cm2-sr and 2.67 W/cm 2-sr are obtained. A broadband light emitting diode spanning the mid-wave infrared is demonstrated with eight stages of InAs/GaSb superlattices individually tuned to a different color. The performance of the device is compared with an identical eight stage device emitting in the middle of the mid-wave infrared. The emission of the fabricated broadband device spans from 3.2 ?m to 6 mum with peak radiance of 137.1 mW/cm2-sr. Growth of antimonide-based devices on GaAs is desirable to the relative transparency of semi-insulating substrates throughout the infrared, and as semi-insulating GaSb substrates are not available. The growth of bulk GaSb on GaAs is explored through different techniques in order to confine relaxation due to lattice mismatch strain to the

  8. Characterization of nanostructure ferrite material on gallium nitride on SiC substrate for millimeter wave integrated circuit

    Directory of Open Access Journals (Sweden)

    Brian O’Keefe

    2017-05-01

    Full Text Available In this paper, for the first time, the characterization of spin-casted thick Barium nano-hexaferrite film on GaN-on-SiC substrate over a broad frequency range of 30-110 GHz is presented. Real and imaginary parts of both permittivity and permeability of the ferrite/polymer film are computed from transmittance data obtained by using a free space quasi-optical millimeter wave spectrometer. The spin-casted composite film shows strong resonance in the Q band, and mixing the powder with polymer slightly shifts the resonance frequency lower compared to pure powder. The high temperature compatibility of GaN substrate enables us to run burn-out tests at temperatures up to 900°C. Significant shortening phenomenon of resonance linewidth after heat treatment was found. Linewidth is reduced from 2.8 kOe to 1.7 kOe. Experiment results show that the aforementioned film is a good candidate in applications of non-reciprocal ferrite devices like isolators, phase shifters, and circulators.

  9. Scaling of graphene integrated circuits.

    Science.gov (United States)

    Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

    2015-05-07

    The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

  10. An integrator circuit in cerebellar cortex.

    Science.gov (United States)

    Maex, Reinoud; Steuber, Volker

    2013-09-01

    The brain builds dynamic models of the body and the outside world to predict the consequences of actions and stimuli. A well-known example is the oculomotor integrator, which anticipates the position-dependent elasticity forces acting on the eye ball by mathematically integrating over time oculomotor velocity commands. Many models of neural integration have been proposed, based on feedback excitation, lateral inhibition or intrinsic neuronal nonlinearities. We report here that a computational model of the cerebellar cortex, a structure thought to implement dynamic models, reveals a hitherto unrecognized integrator circuit. In this model, comprising Purkinje cells, molecular layer interneurons and parallel fibres, Purkinje cells were able to generate responses lasting more than 10 s, to which both neuronal and network mechanisms contributed. Activation of the somatic fast sodium current by subthreshold voltage fluctuations was able to maintain pulse-evoked graded persistent activity, whereas lateral inhibition among Purkinje cells via recurrent axon collaterals further prolonged the responses to step and sine wave stimulation. The responses of Purkinje cells decayed with a time-constant whose value depended on their baseline spike rate, with integration vanishing at low ( 30 per s). The model predicts that the apparently fast circuit of the cerebellar cortex may control the timing of slow processes without having to rely on sensory feedback. Thus, the cerebellar cortex may contain an adaptive temporal integrator, with the sensitivity of integration to the baseline spike rate offering a potential mechanism of plasticity of the response time-constant. © 2013 Federation of European Neuroscience Societies and John Wiley & Sons Ltd.

  11. Design of analog integrated circuits and systems

    CERN Document Server

    Laker, Kenneth R

    1994-01-01

    This text is designed for senior or graduate level courses in analog integrated circuits or design of analog integrated circuits. This book combines consideration of CMOS and bipolar circuits into a unified treatment. Also included are CMOS-bipolar circuits made possible by BiCMOS technology. The text progresses from MOS and bipolar device modelling to simple one and two transistor building block circuits. The final two chapters present a unified coverage of sample-data and continuous-time signal processing systems.

  12. Recent advances in silicon photonic integrated circuits

    Science.gov (United States)

    Bowers, John E.; Komljenovic, Tin; Davenport, Michael; Hulme, Jared; Liu, Alan Y.; Santis, Christos T.; Spott, Alexander; Srinivasan, Sudharsanan; Stanton, Eric J.; Zhang, Chong

    2016-02-01

    We review recent breakthroughs in silicon photonics technology and components and describe progress in silicon photonic integrated circuits. Heterogeneous silicon photonics has recently demonstrated performance that significantly outperforms native III-V components. The impact active silicon photonic integrated circuits could have on interconnects, telecommunications, sensors and silicon electronics is reviewed.

  13. Active components for integrated plasmonic circuits

    DEFF Research Database (Denmark)

    Krasavin, A.V.; Bolger, P.M.; Zayats, A.V.

    2009-01-01

    We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides.......We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides....

  14. Analog MOS integrated circuits for signal processing

    Science.gov (United States)

    Gregorian, R.; Temes, G. C.

    Theoretical and practical aspects of analog MOS integrated circuits are discussed. The basic properties of these circuits are described, providing necessary background material in mathematics and semiconductor device physics and technology. The operation and design of such important circuits as switched-capacitor filters, analog-to-digital and digital-to-analog converters, amplifiers, modulators, and oscillators. Practical problems encountered in design are discussed, solutions are provided, and some examples of actual system applications are given.

  15. Circuit quantum acoustodynamics with surface acoustic waves.

    Science.gov (United States)

    Manenti, Riccardo; Kockum, Anton F; Patterson, Andrew; Behrle, Tanja; Rahamim, Joseph; Tancredi, Giovanna; Nori, Franco; Leek, Peter J

    2017-10-17

    The experimental investigation of quantum devices incorporating mechanical resonators has opened up new frontiers in the study of quantum mechanics at a macroscopic level. It has recently been shown that surface acoustic waves (SAWs) can be piezoelectrically coupled to superconducting qubits, and confined in high-quality Fabry-Perot cavities in the quantum regime. Here we present measurements of a device in which a superconducting qubit is coupled to a SAW cavity, realising a surface acoustic version of cavity quantum electrodynamics. We use measurements of the AC Stark shift between the two systems to determine the coupling strength, which is in agreement with a theoretical model. This quantum acoustodynamics architecture may be used to develop new quantum acoustic devices in which quantum information is stored in trapped on-chip acoustic wavepackets, and manipulated in ways that are impossible with purely electromagnetic signals, due to the 10(5) times slower mechanical waves.In this work, Manenti et al. present measurements of a device in which a tuneable transmon qubit is piezoelectrically coupled to a surface acoustic wave cavity, realising circuit quantum acoustodynamic architecture. This may be used to develop new quantum acoustic devices.

  16. Silicon integrated circuits part A : supplement 2

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

  17. Lateral power transistors in integrated circuits

    CERN Document Server

    Erlbacher, Tobias

    2014-01-01

    This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

  18. Integrated Circuit Stellar Magnitude Simulator

    Science.gov (United States)

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  19. Radio-frequency integrated-circuit engineering

    CERN Document Server

    Nguyen, Cam

    2015-01-01

    Radio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC's using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. Provide

  20. Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

    OpenAIRE

    石橋, 孝昭

    2012-01-01

    This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

  1. Progress in organic integrated circuit manufacture

    Science.gov (United States)

    Taylor, D. Martin

    2016-02-01

    This review article focuses on the development of processes for the manufacture of organic electronic circuits. Beginning with the first report of an organic transistor it highlights the key developments leading to the successful manufacture of microprocessors and other complex circuits incorporating organic transistors. Both batch processing (based on silicon integrated circuit technology) as well as mass-printing, roll-to-roll (R2R) approaches are discussed. Currently, the best circuit performances are achieved using batch processing. It is suggested that an emerging, large mass-market for electronic tags may dictate that R2R manufacture will likely be required to meet the high throughput rates needed. However, significant improvements in resolution and registration are necessary to achieve increased circuit operating speeds.

  2. Empty substrate integrated waveguide technology for E plane high-frequency and high-performance circuits

    OpenAIRE

    Belenguer, Angel; Cano, Juan Luis; Esteban, Héctor; Artal, Eduardo; Boria, Vicente E.

    2017-01-01

    Substrate integrated circuits (SIC) have attracted much attention in the last years because of their great potential of low cost, easy manufacturing, integration in a circuit board, and higher-quality factor than planar circuits. A first suite of SIC where the waves propagate through dielectric have been first developed, based on the well-known substrate integrated waveguide (SIW) and related technological implementations. One step further has been made with a new suite of empty substrate int...

  3. Displacement Damage in Bipolar Linear Integrated Circuits

    Science.gov (United States)

    Rax, B. G.; Johnston, A. H.; Miyahira, T.

    2000-01-01

    Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

  4. Pulsed-Power Burnout of Integrated Circuits

    Science.gov (United States)

    Results of pulsed-power burnout testing the Fairchild 9046 quad dual-input nand gate and the Amelco 6041 three-input nand gate showed the circuits to...be vulnerable to junction burnout for pulses of less than 100 V and pulse widths on the order of 100 nsec. Calculations based on Wunsch-Bell junction... burnout theory showed good agreement with the experimental results. Sample calculations applying Wunsch-Bell theory to integrated circuits are given.

  5. Phase-controlled integrated photonic quantum circuits.

    Science.gov (United States)

    Smith, Brian J; Kundys, Dmytro; Thomas-Peter, Nicholas; Smith, P G R; Walmsley, I A

    2009-08-03

    Scalable photonic quantum technologies are based on multiple nested interferometers. To realize this architecture, integrated optical structures are needed to ensure stable, controllable, and repeatable operation. Here we show a key proof-of-principle demonstration of an externallycontrolled photonic quantum circuit based upon UV-written waveguide technology. In particular, we present non-classical interference of photon pairs in a Mach-Zehnder interferometer constructed with X couplers in an integrated optical circuit with a thermo-optic phase shifter in one of the interferometer arms.

  6. Integrated Circuits in the Introductory Electronics Laboratory

    Science.gov (United States)

    English, Thomas C.; Lind, David A.

    1973-01-01

    Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

  7. Silicon Photonic Integrated Circuit Mode Multiplexer

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ou, Haiyan; Xu, Jing

    2013-01-01

    We propose and demonstrate a novel silicon photonic integrated circuit enabling multiplexing of orthogonal modes in a few-mode fiber (FMF). By selectively launching light to four vertical grating couplers, all six orthogonal spatial and polarization modes supported by the FMF are successfully exc...

  8. LC Quadrature Generation in Integrated Circuits

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    Today quadrature signals for IQ demodulation are provided through RC polyphase networks, quadrature oscillators or double frequency VCOs. This paper presents a new method for generating quadrature signals in integrated circuits using only inductors and capacitors. This LC quadrature generation...... method enables significantly reduced noise and power consumption....

  9. Accurate Electromagnetic Modeling Methods for Integrated Circuits

    NARCIS (Netherlands)

    Sheng, Z.

    2010-01-01

    The present development of modern integrated circuits (IC’s) is characterized by a number of critical factors that make their design and verification considerably more difficult than before. This dissertation addresses the important questions of modeling all electromagnetic behavior of features on

  10. Data readout system utilizing photonic integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

    2013-10-11

    We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

  11. Power management techniques for integrated circuit design

    CERN Document Server

    Chen, Ke-Horng

    2016-01-01

    This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

  12. Reverse Engineering Integrated Circuits Using Finite State Machine Analysis

    Energy Technology Data Exchange (ETDEWEB)

    Oler, Kiri J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Miller, Carl H. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2016-04-12

    In this paper, we present a methodology for reverse engineering integrated circuits, including a mathematical verification of a scalable algorithm used to generate minimal finite state machine representations of integrated circuits.

  13. The RD53A Integrated Circuit

    CERN Document Server

    Garcia-Sciveres, Maurice

    2017-01-01

    Implementation details for the RD53A pixel readout integrated circuit designed by the RD53 Collaboration. This is a companion to the specifications document and will eventually become a reference for chip users. RD53A is not intended to be a final production IC for use in an experiment, and contains design variations for testing purposes, making the pixel matrix non-uniform. The chip size is 20.0 mm by 11.8 mm.

  14. Efficient Integrated Circuits for Wideband Wireless Transceivers

    OpenAIRE

    Duong, Quoc-Tai

    2016-01-01

    The proliferation of portable communication devices combined with the relentless demand for higher data rates has spurred the development of wireless communication standards which can support wide signal bandwidths. Benefits of the complementary metal oxide semiconductor (CMOS) process such as high device speeds and low manufacturing cost have rendered it the technology of choice for implementing wideband wireless transceiver integrated circuits (ICs). This dissertation addresses the key chal...

  15. High-frequency analog integrated circuit design

    CERN Document Server

    1995-01-01

    To learn more about designing analog integrated circuits (ICs) at microwave frequencies using GaAs materials, turn to this text and reference. It addresses GaAs MESFET-based IC processing. Describes the newfound ability to apply silicon analog design techniques to reliable GaAs materials and devices which, until now, was only available through technical papers scattered throughout hundred of articles in dozens of professional journals.

  16. Progress in radiation immune thermionic integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Lynn, D.K.; McCormick, J.B. (comps.)

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

  17. Power system with an integrated lubrication circuit

    Science.gov (United States)

    Hoff, Brian D [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL; Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Lane, William H [Chillicothe, IL

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  18. Circuit Design of Surface Acoustic Wave Based Micro Force Sensor

    Directory of Open Access Journals (Sweden)

    Yuanyuan Li

    2014-01-01

    Full Text Available Pressure sensors are commonly used in industrial production and mechanical system. However, resistance strain, piezoresistive sensor, and ceramic capacitive pressure sensors possess limitations, especially in micro force measurement. A surface acoustic wave (SAW based micro force sensor is designed in this paper, which is based on the theories of wavelet transform, SAW detection, and pierce oscillator circuits. Using lithium niobate as the basal material, a mathematical model is established to analyze the frequency, and a peripheral circuit is designed to measure the micro force. The SAW based micro force sensor is tested to show the reasonable design of detection circuit and the stability of frequency and amplitude.

  19. Mouldable all-carbon integrated circuits.

    Science.gov (United States)

    Sun, Dong-Ming; Timmermans, Marina Y; Kaskela, Antti; Nasibulin, Albert G; Kishimoto, Shigeru; Mizutani, Takashi; Kauppinen, Esko I; Ohno, Yutaka

    2013-01-01

    A variety of plastic products, ranging from those for daily necessities to electronics products and medical devices, are produced by moulding techniques. The incorporation of electronic circuits into various plastic products is limited by the brittle nature of silicon wafers. Here we report mouldable integrated circuits for the first time. The devices are composed entirely of carbon-based materials, that is, their active channels and passive elements are all fabricated from stretchable and thermostable assemblies of carbon nanotubes, with plastic polymer dielectric layers and substrates. The all-carbon thin-film transistors exhibit a mobility of 1,027 cm(2) V(-1) s(-1) and an ON/OFF ratio of 10(5). The devices also exhibit extreme biaxial stretchability of up to 18% when subjected to thermopressure forming. We demonstrate functional integrated circuits that can be moulded into a three-dimensional dome. Such mouldable electronics open new possibilities by allowing for the addition of electronic/plastic-like functionalities to plastic/electronic products, improving their designability.

  20. Integrated Circuits for Analog Signal Processing

    CERN Document Server

    2013-01-01

      This book presents theory, design methods and novel applications for integrated circuits for analog signal processing.  The discussion covers a wide variety of active devices, active elements and amplifiers, working in voltage mode, current mode and mixed mode.  This includes voltage operational amplifiers, current operational amplifiers, operational transconductance amplifiers, operational transresistance amplifiers, current conveyors, current differencing transconductance amplifiers, etc.  Design methods and challenges posed by nanometer technology are discussed and applications described, including signal amplification, filtering, data acquisition systems such as neural recording, sensor conditioning such as biomedical implants, actuator conditioning, noise generators, oscillators, mixers, etc.   Presents analysis and synthesis methods to generate all circuit topologies from which the designer can select the best one for the desired application; Includes design guidelines for active devices/elements...

  1. Microtelemetry--the use of integrated circuits in biotelemetry.

    Science.gov (United States)

    Gill, R W

    1976-02-01

    Integrated circuits are now in widespread use in such equipment as computers and consumer electronics, where their low cost, high reliability and small size are their principal advantages. In biotelemetry, small size is of particular importance. Here the use of integrated circuits allows systems of considerable complexity to be produced with high reliability in small packages. Commercial integrated circuits with the low power consumption and low voltage operation needed for biotelemetry are now becoming available; some such applications are briefly reviewed. In addition, examples of the use of custom integrated circuits in biotelemetry, and of the use of integrated circuit technology to build unique transducers and assemblies, are described.

  2. Thermoelectricity from wasted heat of integrated circuits

    KAUST Repository

    Fahad, Hossain M.

    2012-05-22

    We demonstrate that waste heat from integrated circuits especially computer microprocessors can be recycled as valuable electricity to power up a portion of the circuitry or other important accessories such as on-chip cooling modules, etc. This gives a positive spin to a negative effect of ever increasing heat dissipation associated with increased power consumption aligned with shrinking down trend of transistor dimension. This concept can also be used as an important vehicle for self-powered systemson- chip. We provide theoretical analysis supported by simulation data followed by experimental verification of on-chip thermoelectricity generation from dissipated (otherwise wasted) heat of a microprocessor.

  3. 3D packaging for integrated circuit systems

    Energy Technology Data Exchange (ETDEWEB)

    Chu, D.; Palmer, D.W. [eds.

    1996-11-01

    A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

  4. Nanotechnology: high-speed integrated nanowire circuits.

    Science.gov (United States)

    Friedman, Robin S; McAlpine, Michael C; Ricketts, David S; Ham, Donhee; Lieber, Charles M

    2005-04-28

    Macroelectronic circuits made on substrates of glass or plastic could one day make computing devices ubiquitous owing to their light weight, flexibility and low cost. But these substrates deform at high temperatures so, until now, only semiconductors such as organics and amorphous silicon could be used, leading to poor performance. Here we present the use of low-temperature processes to integrate high-performance multi-nanowire transistors into logical inverters and fast ring oscillators on glass substrates. As well as potentially enabling powerful electronics to permeate all aspects of modern life, this advance could find application in devices such as low-cost radio-frequency tags and fully integrated high-refresh-rate displays.

  5. Experimental observation of sub-terahertz backward-wave amplification in a multi-level microfabricated slow-wave circuit

    Energy Technology Data Exchange (ETDEWEB)

    Baik, Chan-Wook, E-mail: cw.baik@samsung.com; Ahn, Ho Young; Kim, Yongsung; Lee, Jooho; Hong, Seogwoo; Lee, Sang Hun; Choi, Jun Hee; Kim, Sunil; Kim, Jong Min; Hwang, Sungwoo [Samsung Advanced Institute of Technology, Suwon 443-803 (Korea, Republic of); Jeon, So-Yeon; Yu, SeGi [Department of Physics, Hankuk University of Foreign Studies, Yongin 449-791 (Korea, Republic of); Collins, George; Read, Michael E.; Lawrence Ives, R. [Calabazas Creek Research, Inc., San Mateo, California 94404-1010 (United States)

    2015-11-09

    In our earlier paper dealing with dispersion retrieval from ultra-deep, reactive-ion-etched, slow-wave circuits on silicon substrates, it was proposed that splitting high-aspect-ratio circuits into multilevels enabled precise characterization in sub-terahertz frequency regime. This achievement prompted us to investigate beam-wave interaction through a vacuum-sealed integration with a 15-kV, 85-mA, thermionic, electron gun. Our experimental study demonstrates sub-terahertz, backward-wave amplification driven by an external oscillator. The measured output shows a frequency downshift, as well as power amplification, from beam loading even with low beam perveance. This offers a promising opportunity for the development of terahertz radiation sources, based on silicon technologies.

  6. Parallel Jacobi EVD Methods on Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Chi-Chia Sun

    2014-01-01

    Full Text Available Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation.

  7. Post irradiation effects (PIE) in integrated circuits

    Science.gov (United States)

    Shaw, D. C.; Lowry, L.; Barnes, C.; Zakharia, M.; Agarwal, S.; Rax, B.

    1991-01-01

    Post-irradiation effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. Data presented show failure due to rebound after a 10 krad(Si) dose. In particular, five device types are investigated with varying PIE response. Special attention has been given to the HI1-507A analog multiplexer because its PIE response is extreme. X-ray diffraction has been uniquely employed to measure physical stress in the HI1-507A metallization. An attempt has been made to show a relationship between stress relaxation and radiation effects. All data presented support the current MIL-STD Method 1019.4 but demonstrate the importance of performing PIE measurements, even when mission doses are as low as 10 krad(Si).

  8. RD53A Integrated Circuit Specifications

    CERN Document Server

    Garcia-Sciveres, Mauricio

    2015-01-01

    Specifications for the RD53 collaboration’s first engineering wafer run of an integrated circuit (IC) for hybrid pixel detector readout, called RD53A. RD53A is intended to demonstrate in a large format IC the suitability of the technology (including radiation tolerance), the stable low threshold operation, and the high hit and trigger rate capabilities, required for HL-LHC upgrades of ATLAS and CMS. The wafer scale production will permit the experiments to prototype bump bonding assembly with realistic sensors in this new technology and to measure the performance of hybrid assemblies. RD53A is not intended to be a final production IC for use in an experiment, and will contain design variations for testing purposes, making the pixel matrix non-uniform.

  9. Integrated Reconfigurable High-Voltage Transmitting Circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2014-01-01

    -out and measurements are performed on the integrated circuit. The transmitting circuit is reconfigurable externally making it able to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes, pulse voltages up to 100 V, maximum pulse range of 50 V and frequencies up to 5 MHz. The area...

  10. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  11. Energy-efficient neuron, synapse and STDP integrated circuits.

    Science.gov (United States)

    Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

    2012-06-01

    Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

  12. Integrated devices in digital circuit design

    Science.gov (United States)

    Hope, G. S.

    Aspects of combinational design are examined, taking into account logical operations, truth tables, Karnaugh maps as input output expressions, minimum forms, maximum forms, minterm forms, symbols, fundamental relationships, Karnaugh maps as design tools, the implementation of logic functions, logic and implementation, logic nor implementation, implementation examples, the exclusive or function, symmetrical forms, reduction, and practical circuits. Multiplexers and demultiplexers in combinational circuits are considered along with fundamental mode circuits, event-driven sequential circuits, event-driven circuit implementation using multiplexers, clock-driven sequential circuits, counters and multiplexers in clock-driven sequential circuits, state diagram construction, registers in logic design, a digital system, programming and programming aids, input and output techniques, operation and configuration of independent systems, and a definition of a Boolean algebra. Attention is also given to Intel's and Motorola's executable instructions.

  13. Aluminum alloy metallization for integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Ghate, P.B.

    1981-09-11

    Aluminum metallization is most widely used for contacts and interconnections in both bipolar and MOS integrated circuits. Aluminum alloy films, such as Al-Si and Al-Cu films, were introduced to minimize the erosion of silicon from contact windows and to improve the electromigration resistance of interconnections. Recently, magnetron sputter-deposited aluminum, Al-2wt.%Cu and Al-2wt.%Cu-1wt.%Si films were employed to study the stability and contact resistance of Si-(Al alloy film) contacts on devices with shallow junction depths of the order of 0.35 ..mu..m. Test structures were used to determine the leakage currents of 100n/sup +//p/sup +/ diodes as a function of the storage time (up to 1000 h) at 150 C, and the physical nature of the Si-(Al alloy) contacts was examined using scanning electron microscopy. The compatibility of the Al-Cu-Si metallization with the very large scale integrated requirements of interconnection and Si-metal contacts for shallow junction devices is discussed.

  14. Wide-band polarization controller for Si photonic integrated circuits.

    Science.gov (United States)

    Velha, P; Sorianello, V; Preite, M V; De Angelis, G; Cassese, T; Bianchi, A; Testa, F; Romagnoli, M

    2016-12-15

    A circuit for the management of any arbitrary polarization state of light is demonstrated on an integrated silicon (Si) photonics platform. This circuit allows us to adapt any polarization into the standard fundamental TE mode of a Si waveguide and, conversely, to control the polarization and set it to any arbitrary polarization state. In addition, the integrated thermal tuning allows kilohertz speed which can be used to perform a polarization scrambler. The circuit was used in a WDM link and successfully used to adapt four channels into a standard Si photonic integrated circuit.

  15. Topology Optimization of Building Blocks for Photonic Integrated Circuits

    DEFF Research Database (Denmark)

    Jensen, Jakob Søndergaard; Sigmund, Ole

    2005-01-01

    Photonic integrated circuits are likely candidates as high speed replacements for the standard electrical integrated circuits of today. However, in order to obtain a satisfactorily performance many design prob- lems that up until now have resulted in too high losses must be resolved. In this work...... we demonstrate how the method of topology optimization can be used to design a variety of high performance building blocks for the future circuits....

  16. Securing Health Sensing Using Integrated Circuit Metric

    Directory of Open Access Journals (Sweden)

    Ruhma Tahir

    2015-10-01

    Full Text Available Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware “fingerprints”. The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner.

  17. Counterfeit integrated circuits detection and avoidance

    CERN Document Server

    Tehranipoor, Mark (Mohammad); Forte, Domenic

    2015-01-01

    This timely and exhaustive study offers a much-needed examination of the scope and consequences of the electronic counterfeit trade.  The authors describe a variety of shortcomings and vulnerabilities in the electronic component supply chain, which can result in counterfeit integrated circuits (ICs).  Not only does this book provide an assessment of the current counterfeiting problems facing both the public and private sectors, it also offers practical, real-world solutions for combatting this substantial threat.   ·      Helps beginners and practitioners in the field by providing a comprehensive background on the counterfeiting problem; ·      Presents innovative taxonomies for counterfeit types, test methods, and counterfeit defects, which allows for a detailed analysis of counterfeiting and its mitigation; ·      Provides step-by-step solutions for detecting different types of counterfeit ICs; ·      Offers pragmatic and practice-oriented, realistic solutions to counterfeit IC d...

  18. Designing TSVs for 3D Integrated Circuits

    CERN Document Server

    Khan, Nauman

    2013-01-01

    This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits.  It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks.  Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available....

  19. CLASSICS Invention of the Integrated Circuit

    Indian Academy of Sciences (India)

    IAS Admin

    electrical functions being connected directly by cutting out areas of the various layers.” This remarkable ... In 1947 I graduated from the University of Illinois with a degree in electrical engineering. I was hired by A. S. .... first circuit attempted was a phase-shift oscillator, a favorite demonstration vehicle for linear circuits at that ...

  20. F-Paris: integrated electronic circuits [Tender

    CERN Multimedia

    2003-01-01

    "Fourniture, montage et tests des circuits imprimes et modules multi composants pour le trajectographe central de CMS. Maximum de 12 000 circuits imprimes et modules multi-composants necessaires au trajectographe central de l'experience CMS aupres du Large Hadron Collider" (1 page).

  1. Integrated differential high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Farch, Kjartan

    2015-01-01

    In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order...... to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption...

  2. Design of 3D integrated circuits and systems

    CERN Document Server

    Sharma, Rohit

    2014-01-01

    Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

  3. Parallel sparse direct solver for integrated circuit simulation

    CERN Document Server

    Chen, Xiaoming; Yang, Huazhong

    2017-01-01

    This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques. · Introduces complicated algorithms of sparse linear solvers, using concise principles and simple examples, without complex theory or lengthy derivations; · Describes a parallel sparse direct solver that can be adopted to accelerate any SPICE-like integrated circuit simulato...

  4. Nanophotonic integrated circuits from nanoresonators grown on silicon.

    Science.gov (United States)

    Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

    2014-07-07

    Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

  5. Present and future trends in integrated analog signal processing circuits

    Science.gov (United States)

    Nakayama, Kenji; Iwata, Atsushi; Yanagisawa, Takeshi

    1988-12-01

    An overview is presented of the recent and future trends in the design and applications of integrated analog signal processing circuits. Design techniques are reviewed for operational amplifiers, monolithic bipolar active RC circuits, switched-capacitor (SC) circuits, continuous-time MOS circuits, and analog-to-digital converters (ADCs). High-frequency filter realization, up to 100 MHz, has been attempted by bipolar active RC circuits and GaAs circuits. Improved design techniques for SC circuits are proposed. A multistage noise shaping ADC is very useful to integrate an accurate ADC. A high SNR (more than 91 dB) is obtained by the three-stage ADC, which can be applied to digital audio systems. An overview is presented of silicon compilers for SC circuits. A mixed analog/digital master slice LSI is proposed to simplify an LSI customizing process. A voice-band modem LSI has been developed, resulting in good filter responses and SNR. Finally, promising applications of integrated analog circuits are briefly reviewed.

  6. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

    DEFF Research Database (Denmark)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

    2016-01-01

    -division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-oninsulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7x7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror......, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained...

  7. 76 FR 76434 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Science.gov (United States)

    2011-12-07

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions, Receipt... Commission has received a complaint entitled In Re Certain Integrated Circuits, Chipsets, And Products... importation of certain integrated circuits, chipsets, and products containing same including televisions. The...

  8. 77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...

    Science.gov (United States)

    2012-06-13

    ... COMMISSION Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of... within the United States after importation of certain radio frequency integrated circuits and devices... after importation of certain radio frequency integrated circuits and devices containing same that...

  9. Radiation-hardened transistor and integrated circuit

    Science.gov (United States)

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  10. Logistic Regression Modeling of Diminishing Manufacturing Sources for Integrated Circuits

    National Research Council Canada - National Science Library

    Gravier, Michael

    1999-01-01

    .... This thesis draws on available data from the electronics integrated circuit industry to attempt to assess whether statistical modeling offers a viable method for predicting the presence of DMSMS...

  11. Analog integrated circuits design for processing physiological signals.

    Science.gov (United States)

    Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

    2010-01-01

    Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

  12. Integrating integrated circuit chips on paper substrates using inkjet printed electronics

    CSIR Research Space (South Africa)

    Bezuidenhout, Petrone H

    2016-11-01

    Full Text Available connect various integrated circuit(IC) chip packages to a paper substrate using a commercially-available conductive silver ink. The verification process included contact resistance compared to line resistance, percentage effective connections, geometry...

  13. Large Scale Integrated Circuits for Military Applications.

    Science.gov (United States)

    1977-05-01

    film formation, etching of numerous openings in the oxide film at locations precisely defined by photolitho - graphy, chemical treatment of the...circuit speed inversely with the linear dimensions. The practical implication is that improvements in photolitho - graphy, or the use of electron beam

  14. Electrothermal simulation of SOI CMOS analog integrated circuits

    Science.gov (United States)

    Yu, Feixia; Cheng, Ming-C.

    2007-05-01

    An analytical approach, combining a heat flow device model for SOI devices and a thermal model for interconnects, is presented for electrothermal simulation of SOI analog integrated circuits. The proposed approach is able to account for large temperature gradients in device, heat exchanges between devices, heat losses from the silicon islands and interconnects to the substrate through oxide, and temperature influences on electronic characteristics. Electrothermal simulations of SOI analog integrated circuits in SPICE coupled with the proposed approach are performed and compared with the isothermal model using the BSIMSOI thermal circuit. Heat flow, thermal coupling and self-heating effects in some SOI analog integrated circuits influenced by non-isothermal effects are examined. Limitations of the BSIMSOI isothermal is discussed.

  15. Integrated Circuit For Simulation Of Neural Network

    Science.gov (United States)

    Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

    1988-01-01

    Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

  16. Integrating Neural Circuits Controlling Female Sexual Behavior

    Directory of Open Access Journals (Sweden)

    Paul E. Micevych

    2017-06-01

    Full Text Available The hypothalamus is most often associated with innate behaviors such as is hunger, thirst and sex. While the expression of these behaviors important for survival of the individual or the species is nested within the hypothalamus, the desire (i.e., motivation for them is centered within the mesolimbic reward circuitry. In this review, we will use female sexual behavior as a model to examine the interaction of these circuits. We will examine the evidence for a hypothalamic circuit that regulates consummatory aspects of reproductive behavior, i.e., lordosis behavior, a measure of sexual receptivity that involves estradiol membrane-initiated signaling in the arcuate nucleus (ARH, activating β-endorphin projections to the medial preoptic nucleus (MPN, which in turn modulate ventromedial hypothalamic nucleus (VMH activity—the common output from the hypothalamus. Estradiol modulates not only a series of neuropeptides, transmitters and receptors but induces dendritic spines that are for estrogenic induction of lordosis behavior. Simultaneously, in the nucleus accumbens of the mesolimbic system, the mating experience produces long term changes in dopamine signaling and structure. Sexual experience sensitizes the response of nucleus accumbens neurons to dopamine signaling through the induction of a long lasting early immediate gene. While estrogen alone increases spines in the ARH, sexual experience increases dendritic spine density in the nucleus accumbens. These two circuits appear to converge onto the medial preoptic area where there is a reciprocal influence of motivational circuits on consummatory behavior and vice versa. While it has not been formally demonstrated in the human, such circuitry is generally highly conserved and thus, understanding the anatomy, neurochemistry and physiology can provide useful insight into the motivation for sexual behavior and other innate behaviors in humans.

  17. Investigation for connecting waveguide in off-planar integrated circuits.

    Science.gov (United States)

    Lin, Jie; Feng, Zhifang

    2017-09-01

    The transmission properties of a vertical waveguide connected by different devices in off-planar integrated circuits are designed, investigated, and analyzed in detail by the finite-difference time-domain method. The results show that both guide bandwidth and transmission efficiency can be adjusted effectively by shifting the vertical waveguide continuously. Surprisingly, the wide guide band (0.385[c/a]∼0.407[c/a]) and well transmission (-6  dB) are observed simultaneously in several directions when the vertical waveguide is located at a specific location. The results are very important for all-optical integrated circuits, especially in compact integration.

  18. Micro-relay technology for energy-efficient integrated circuits

    CERN Document Server

    Kam, Hei

    2015-01-01

    This book describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers and highlights the importance of co-design across design hierarchies when optimizing system performance (in this case, energy-efficiency). This book is ideal for researchers and engineers focused on semiconductors, integrated circuits, and energy efficient electronics. This book also: ·         Covers microsystem fabrication, MEMS device design, circuit design, circuit micro-architecture, and CAD ·         Describes work previously done in the field and also lays the groundwork and criteria for future energy-efficient device and system design ·         Maximizes reader insights into the design and modeling of micro-relay, micro-relay reliability, integrated circuit design with micro-relays, and more

  19. Novel paradigm for integrated photonics circuits: transient interconnection network

    Science.gov (United States)

    Fazio, Eugenio; Belardini, Alessandro; Bastiani, Lorenzo; Alonzo, Massimo; Chauvet, Mathieu; Zheludev, Nikolay I.; Soci, Cesare

    2017-01-01

    Self-confined beams and spatial solitons were always investigated for a purely academic point of view, describing their formation and cross-interaction. We propose a novel paradigm for integrated photonics circuits based on self-confined interconnections. We consider that circuits are not designed since beginning; a network of writing lasers provide the circuit configuration inside which information at a different wavelength travels. we propose new designs for interconnections and both digital and analog switching gates somehow inspired by Nature, following analog decision routes used in biological networks like brain synapsis or animal path finding.

  20. Advances in Thick Film Conductors for Microwave Integrated Circuits

    OpenAIRE

    Wilson, Larry K.; Rich, Debbie D.; Rich, Phil W.; R. Wayne Johnson

    1980-01-01

    New conductor pastes have made possible great improvements in the loss characteristics of thick film microwave integrated circuits. This paper presents data on the microwave characteristics of transmission structures made from newly developed copper, silver and gold conductor pastes on alumina and garnet substrates. The resistivity and microstructure for each conductor material was examined for correlation with microwave properties. These data show that thick film circuits can give excellent ...

  1. Dielectric isolation for power integrated circuits; Isolation dielectrique enterree pour les circuits integres de puissance

    Energy Technology Data Exchange (ETDEWEB)

    Zerrouk, D.

    1997-07-18

    Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called `smart power` devices use either self isolation, junction isolation or Silicon-On-Insulator (SOI) to integrate low voltage elements with vertical power devices. Dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Thesis work consists of the study of the feasibility of a dielectric technology based on the melting and the solidification in a Rapid Thermal Processing furnace (RTP), of thick polysilicon films deposited on oxide. The purpose of this technique is to obtain substrate with localized SOI structures for smart power applications. SOI technology offers significant potential advantages, such as non-occurrence of latch-up in CMOS structures, high packaging density, low parasitic capacitance and the possibility of 3D structures. In addition, SOI technology using thick silicon films (10-100 {mu}m) offers special advantages for high voltage integrated circuits. Several techniques have been developed to form SOI films. Zone melting recrystallization is one of the most promising for localized SOI. The SOI structures have first been analyzed in term of extended defects. N-channel MOSFET`s transistors have also been fabricated in the SOI substrates and electrically characterized (threshold voltages, off-state leakage current, mobilities,...). The SOI transistors exhibit good characteristics, although inferior to witness transistors. The recrystallized silicon films are therefore found to be suitable for the fabrication of SOI devices. (author) 106 refs.

  2. Single Event Transients in Linear Integrated Circuits

    Science.gov (United States)

    Buchner, Stephen; McMorrow, Dale

    2005-01-01

    On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed

  3. Process Variations and Probabilistic Integrated Circuit Design

    CERN Document Server

    Haase, Joachim

    2012-01-01

    Uncertainty in key parameters within a chip and between different chips in the deep sub micron era plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process.  Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development.   This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits.  Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.  Trains IC designers to recognize problems caused by parameter variations during manufacturing and to choose the best methods available to mitigate these issues during the design process; Offers both qual...

  4. Silica Integrated Optical Circuits Based on Glass Photosensitivity

    Science.gov (United States)

    Abushagur, Mustafa A. G.

    1999-01-01

    Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

  5. Silicon integrated circuits advances in materials and device research

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Silicon Integrated Circuits, Part B covers the special considerations needed to achieve high-power Si-integrated circuits. The book presents articles about the most important operations needed for the high-power circuitry, namely impurity diffusion and oxidation; crystal defects under thermal equilibrium in silicon and the development of high-power device physics; and associated technology. The text also describes the ever-evolving processing technology and the most promising approaches, along with the understanding of processing-related areas of physics and chemistry. Physicists, chemists, an

  6. 3D circuit integration for Vertex and other detectors

    Energy Technology Data Exchange (ETDEWEB)

    Yarema, Ray; /Fermilab

    2007-09-01

    High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

  7. Integrated circuits for particle physics experiments

    CERN Document Server

    Snoeys, W; Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Toifl, Thomas H; Wyllie, Ken H

    2000-01-01

    High energy particle physics experiments investigate the nature of matter through the identification of subatomic particles produced in collisions of protons, electrons, or heavy ions which have been accelerated to very high energies. Future experiments will have hundreds of millions of detector channels to observe the interaction region where collisions take place at a 40 MHz rate. This paper gives an overview of the electronics requirements for such experiments and explains how data reduction, timing distribution, and radiation tolerance in commercial CMOS circuits are achieved for these big systems. As a detailed example, the electronics for the innermost layers of the future tracking detector, the pixel vertex detector, is discussed with special attention to system aspects. A small-scale prototype (130 channels) implemented in standard 0.25 mu m CMOS remains fully functional after a 30 Mrad(SiO/sub 2/) irradiation. A full-scale pixel readout chip containing 8000 readout channels in a 14 by 16 mm/sup 2/ ar...

  8. Biochips: The Integrated Circuit of Biology

    DEFF Research Database (Denmark)

    Madsen, Jan

    2012-01-01

    Microfluidic biochips integrate different biochemical analysis functionalities (e.g., dispensers, filters, mixers, separators, detectors) on-chip, miniaturizing the macroscopic chemical and biological processes often processed by lab-robots, to a sub-millimeter scale. These microsystems offer sev...

  9. Photonic integrated circuits for NG-EPON

    Science.gov (United States)

    Rodrigues, Carla; Rodrigues, Francisco; Lima, Mário; Teixeira, António

    2017-08-01

    This paper intends to propose a monolithic photonic integrated InP transceiver for Next Generation of Ethernet Passive Optical Network (NG-EPON). The presented architecture was designed as an Optical Network Unit (ONU). The concept behind the suggested transceiver architecture is here presented together with the steps necessary to deploy the proposed solution.

  10. 75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...

    Science.gov (United States)

    2010-12-06

    ... United States after importation of certain semiconductor integrated circuits using tungsten metallization... COMMISSION Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing... Manufacturing Corporation of China; Integrated Device Technology, Inc. of San Jose, California; and Nanya...

  11. Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia

    Energy Technology Data Exchange (ETDEWEB)

    Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

    2007-04-24

    Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

  12. Classical Conditioning with Pulsed Integrated Neural Networks: Circuits and System

    DEFF Research Database (Denmark)

    Lehmann, Torsten

    1998-01-01

    In this paper we investigate on-chip learning for pulsed, integrated neural networks. We discuss the implementational problems the technology imposes on learning systems and we find that abiologically inspired approach using simple circuit structures is most likely to bring success. We develop a ...... chip to solve simple classical conditioning tasks, thus verifying the design methodologies put forward in the paper....

  13. Reliability of lithium niobate Annealed Proton Exchanged integrated optical circuits

    Science.gov (United States)

    Kissa, Karl M.; Eng, Hogan; Lewis, David K.; Rodino, Vincent D.; Suchoski, Paul G., Jr.; Koziarz, Nancy A.

    1995-06-01

    Several studies have been performed recently that demonstrate the reliability of lithium niobate Annealed Proton Exchanged (APE) Integrated Optical Circuits (IOCs). Studies have been performed on APE IOC die as well as pigtailed and packaged devices. The tests indicate that the reliability of APE IOCs meet or surpass the needs of most military and commercial applications.

  14. Three-dimensional integrated circuit design

    CERN Document Server

    Xie, Yuan; Sapatnekar, Sachin S

    2009-01-01

    This book presents an overview of the field of 3D IC design, with an emphasis on electronic design automation (EDA) tools and algorithms that can enable the adoption of 3D ICs, and the architectural implementation and potential for future 3D system design. The aim of this book is to provide the reader with a complete understanding of: the promise of 3D ICs in building novel systems that enable the chip industry to continue along the path of performance scaling, the state of the art in fabrication technologies for 3D integration, the most prominent 3D-specific EDA challenges, along with solutio

  15. Radio frequency integrated circuit design for cognitive radio systems

    CERN Document Server

    Fahim, Amr

    2015-01-01

    This book fills a disconnect in the literature between Cognitive Radio systems and a detailed account of the circuit implementation and architectures required to implement such systems.  Throughout the book, requirements and constraints imposed by cognitive radio systems are emphasized when discussing the circuit implementation details.  In addition, this book details several novel concepts that advance state-of-the-art cognitive radio systems.  This is a valuable reference for anybody with background in analog and radio frequency (RF) integrated circuit design, needing to learn more about integrated circuits requirements and implementation for cognitive radio systems. ·         Describes in detail cognitive radio systems, as well as the circuit implementation and architectures required to implement them; ·         Serves as an excellent reference to state-of-the-art wideband transceiver design; ·         Emphasizes practical requirements and constraints imposed by cognitive radi...

  16. Automated Cell Synthesis of Analog Integrated Circuit Layout Anasyn.

    Science.gov (United States)

    Stanojevich, Bob Srbislav

    This thesis describes a novel model to automate cell generation for the design of analog integrated circuits and the conclusions about important features that such automation should include. This research represents the first attempt to address this problem by analyzing relevant issues of what constitutes an analog cell and how a technique can be implemented to generate these cells automatically. Our motivation for doing this is the critical limitations to circuit performance which arise from cell design. This thesis defines unique construction properties for the layout of some commonly used analog circuit topologies or cells. This thesis defines the physical layout of analog circuit cells beyond simple geometrical description. Each cell is an independent object that can be interfaced and communicated with. This thesis has extended the concept of an analog cell even further by incorporating synthesis rules into the cell definition. These rules are used to dynamically construct the optimized layout that will satisfy many of the options encountered in actual analog circuit design such as area, matching, tolerance, element rationing and parasitic components. This model can construct complex geometric shapes such as common-centroids, waffles, interdigitated, cascode etc. that are optimized at device level with the precise models for parasitic components. Furthermore, Object-Oriented implementation used in this thesis allow for easy integration of this work into other CAD tools. To demonstrate the feasibility and correctness of the ideas described in this thesis, a CAD tool ANASYN has been written. To test and demonstrate the utility and the performance developed, a variety of test cells have been generated. Data presented clearly demonstrate the uniqueness, flexibility, and precision of the analog circuit layout cells implemented in this research thesis. In addition, one test chip and one design chip have been laid out using cells generated by ANASYN and fabricated at

  17. Flexible circuits with integrated switches for robotic shape sensing

    Science.gov (United States)

    Harnett, C. K.

    2016-05-01

    Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

  18. A Millimeter-Wave Quasi-Optical Circuit for Compact Triple-Band Receiving System

    Science.gov (United States)

    Han, Seog-Tae; Lee, Jung-Won; Lee, Bangwon; Chung, Moon-Hee; Lee, Sung-Mo; Je, Do-Heung; Wi, Seog-Oh; Goldsmith, Paul F.

    2017-12-01

    A novel receiver optical system designed for Korean VLBI Network (KVN) has been used for conducting simultaneous millimeter-wave very long baseline interferometry (VLBI) observations at frequencies of 22, 43, 86, and 129 GHz. This multi-frequency band receiver system has been effective in compensation of atmospheric phase fluctuation by unique phase referencing technique in mm-VLBI observations. However, because the original optics system incorporated individual cryogenic receivers in separate cryostats, a rather bulky optical bench of size about 2600 mm x 2300 mm x 60 mm was required. To circumvent difficulties in installation and beam alignment, an integrated quasi-optical circuit incorporating a more compact triple-band receiver in single cryostat is proposed in this paper. The recommended frequency bands of the improved triple-band receiver are K(18-26 GHz) band, Q(35-50 GHz) band, and W(85-115 GHz) band. A frequency-independent quasi-optical circuit for triple band is adopted to obtain constant aperture efficiency as a function of the observed frequencies. The simulation results show that total aperture efficiency of each recommended frequency band is maintained almost constant within 1%. We present the design details of the compact wideband quasi-optical circuit and the triple-band receiver optimized for simultaneous multi-frequency observations.

  19. Digital integrated circuit design using Verilog and SystemVerilog

    CERN Document Server

    Mehler, Ronald W

    2014-01-01

    For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

  20. Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

    Science.gov (United States)

    Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

    2015-10-14

    We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

  1. Automated tuning, control and stabilization of photonic integrated circuits

    Science.gov (United States)

    O. De Aguiar, Douglas; Annoni, Andrea; Peserico, Nicola; Guglielmi, Emanuele; Carminati, Marco; Ferrari, Giorgio; Morichetti, Francesco

    2017-05-01

    The complexity scaling of silicon photonics circuits is raising novel needs related to control. Reconfigurable architectures need fast, accurate and robust procedures for the tuning and stabilization of their working point, counteracting temperature drifts originated by environmental fluctuations and mutual thermal crosstalk from surrounding integrated devices. In this contribution, we report on our recent achievements on the automated tuning, control and stabilization of silicon photonics architectures. The proposed control strategy exploits transparent integrated detectors to monitor non-invasively the light propagating in the silicon waveguides in key spots of the circuit. Local monitoring enables the partitioning of complex architectures in small photonic cells that can be easily tuned and controlled, with need for neither preliminary circuit calibration nor global optimization algorithms. The ability to monitor the Quality Of of Transmission (QoT) of the optical paths in Photonic Integrated Circuits (PICs) is also demonstrated with the use of channel labelling and non-invasive light monitoring. Several examples of applications are presented that include the automatic reconfiguration and feedback controlled stabilization of an 8×8 switch fabric based on Mach-Zehnder interferometers (MZIs) and the realization of a wavelength locking platform enabling feedback-control of silicon microring resonators (MRRs) for the realization of a 4×10 Gbit/s wavelength-division-multiplexing transmitter. The effectiveness and the robustness of the proposed approach for tuning and stabilization of the presented architectures is demonstrated by showing that no significant performance degradation is observed under uncooled operation for the silicon chip.

  2. Traveling-Wave Tube Cold-Test Circuit Optimization Using CST MICROWAVE STUDIO

    Science.gov (United States)

    Chevalier, Christine T.; Kory, Carol L.; Wilson, Jeffrey D.; Wintucky, Edwin G.; Dayton, James A., Jr.

    2003-01-01

    The internal optimizer of CST MICROWAVE STUDIO (MWS) was used along with an application-specific Visual Basic for Applications (VBA) script to develop a method to optimize traveling-wave tube (TWT) cold-test circuit performance. The optimization procedure allows simultaneous optimization of circuit specifications including on-axis interaction impedance, bandwidth or geometric limitations. The application of Microwave Studio to TWT cold-test circuit optimization is described.

  3. Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

    CERN Document Server

    A Papa, David

    2013-01-01

    This book introduces techniques that advance the capabilities and strength of modern software tools for physical synthesis, with the ultimate goal to improve the quality of leading-edge semiconductor products.  It provides a comprehensive introduction to physical synthesis and takes the reader methodically from first principles through state-of-the-art optimizations used in cutting edge industrial tools. It explains how to integrate chip optimizations in novel ways to create powerful circuit transformations that help satisfy performance requirements. Broadens the scope of physical synthesis optimization to include accurate transformations operating between the global and local scales; Integrates groups of related transformations to break circular dependencies and increase the number of circuit elements that can be jointly optimized to escape local minima;  Derives several multi-objective optimizations from first observations through complete algorithms and experiments; Describes integrated optimization te...

  4. RF and microwave integrated circuit development technology, packaging and testing

    CERN Document Server

    Gamand, Patrice; Kelma, Christophe

    2018-01-01

    RF and Microwave Integrated Circuit Development bridges the gap between existing literature, which focus mainly on the 'front-end' part of a product development (system, architecture, design techniques), by providing the reader with an insight into the 'back-end' part of product development. In addition, the authors provide practical answers and solutions regarding the choice of technology, the packaging solutions and the effects on the performance on the circuit and to the industrial testing strategy. It will also discuss future trends and challenges and includes case studies to illustrate examples. * Offers an overview of the challenges in RF/microwave product design * Provides practical answers to packaging issues and evaluates its effect on the performance of the circuit * Includes industrial testing strategies * Examines relevant RF MIC technologies and the factors which affect the choice of technology for a particular application, e.g. technical performance and cost * Discusses future trends and challen...

  5. Integrated circuit electrometer and sweep circuitry for an atmospheric probe

    Science.gov (United States)

    Zimmerman, L. E.

    1971-01-01

    The design of electrometer circuitry using an integrated circuit operational amplifier with a MOSFET input is described. Input protection against static voltages is provided by a dual ultra low leakage diode or a neon lamp. Factors affecting frequency response leakage resistance, and current stability are discussed, and methods are suggested for increasing response speed and for eliminating leakage resistance and current instabilities. Based on the above, two practical circuits, one having a linear response and the other a logarithmic response, were designed and evaluated experimentally. The design of a sweep circuit to implement mobility measurements using atmospheric probes is presented. A triangular voltage waveform is generated and shaped to contain a step in voltage from zero volts in both positive and negative directions.

  6. Empty substrate integrated waveguide technology for E plane high-frequency and high-performance circuits

    Science.gov (United States)

    Belenguer, Angel; Cano, Juan Luis; Esteban, Héctor; Artal, Eduardo; Boria, Vicente E.

    2017-01-01

    Substrate integrated circuits (SIC) have attracted much attention in the last years because of their great potential of low cost, easy manufacturing, integration in a circuit board, and higher-quality factor than planar circuits. A first suite of SIC where the waves propagate through dielectric have been first developed, based on the well-known substrate integrated waveguide (SIW) and related technological implementations. One step further has been made with a new suite of empty substrate integrated waveguides, where the waves propagate through air, thus reducing the associated losses. This is the case of the empty substrate integrated waveguide (ESIW) or the air-filled substrate integrated waveguide (air-filled SIW). However, all these SIC are H plane structures, so classical H plane solutions in rectangular waveguides have already been mapped to most of these new SIC. In this paper a novel E plane empty substrate integrated waveguide (ESIW-E) is presented. This structure allows to easily map classical E plane solutions in rectangular waveguide to this new substrate integrated solution. It is similar to the ESIW, although more layers are needed to build the structure. A wideband transition (covering the frequency range between 33 GHz and 50 GHz) from microstrip to ESIW-E is designed and manufactured. Measurements are successfully compared with simulation, proving the validity of this new SIC. A broadband high-frequency phase shifter (for operation from 35 GHz to 47 GHz) is successfully implemented in ESIW-E, thus proving the good performance of this new SIC in a practical application.

  7. Power-Integrated Circuit Active Leakage Current Detector

    Directory of Open Access Journals (Sweden)

    M. F. Bulacio

    2012-01-01

    Full Text Available Most of the failures of induction motors become insulation faults, causing a permanent damage. Using differential current transformers, a system capable of insulation fault detection was developed, based on the differential relay protection scheme. Both signal injection and fault detection circuitry were integrated in a single chip. The proposed scheme is faster than other existing protection and not restricted to protect induction motors, but several other devices (such as IGBTs and systems. This paper explains the principle of operation of fault protection scheme and analyzes an integrated implementation through simulations and experimental results. A power-integrated circuit (PIC implementation is presented.

  8. Micromachined Integrated Quantum Circuit Containing a Superconducting Qubit

    Science.gov (United States)

    Brecht, T.; Chu, Y.; Axline, C.; Pfaff, W.; Blumoff, J. Z.; Chou, K.; Krayzman, L.; Frunzio, L.; Schoelkopf, R. J.

    2017-04-01

    We present a device demonstrating a lithographically patterned transmon integrated with a micromachined cavity resonator. Our two-cavity, one-qubit device is a multilayer microwave-integrated quantum circuit (MMIQC), comprising a basic unit capable of performing circuit-QED operations. We describe the qubit-cavity coupling mechanism of a specialized geometry using an electric-field picture and a circuit model, and obtain specific system parameters using simulations. Fabrication of the MMIQC includes lithography, etching, and metallic bonding of silicon wafers. Superconducting wafer bonding is a critical capability that is demonstrated by a micromachined storage-cavity lifetime of 34.3 μ s , corresponding to a quality factor of 2 ×106 at single-photon energies. The transmon coherence times are T1=6.4 μ s , and T2echo=11.7 μ s . We measure qubit-cavity dispersive coupling with a rate χq μ/2 π =-1.17 MHz , constituting a Jaynes-Cummings system with an interaction strength g /2 π =49 MHz . With these parameters we are able to demonstrate circuit-QED operations in the strong dispersive regime with ease. Finally, we highlight several improvements and anticipated extensions of the technology to complex MMIQCs.

  9. Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

    Science.gov (United States)

    Liu, Yuanda; Ang, Kah-Wee

    2017-07-25

    Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10(3). Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

  10. Organic printed photonics: From microring lasers to integrated circuits.

    Science.gov (United States)

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-09-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

  11. 76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...

    Science.gov (United States)

    2011-09-19

    ... COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice... certain digital televisions containing integrated circuit devices and components thereof by reason of... the sale within the United States after importation of certain digital televisions containing...

  12. 77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...

    Science.gov (United States)

    2012-12-12

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products... integrated circuit packages provided with multiple heat-conducting paths and products containing same by...

  13. 76 FR 34101 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Science.gov (United States)

    2011-06-10

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including... integrated circuits, chipsets, and products containing same including televisions, media players, and cameras...

  14. 77 FR 42764 - Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions; Notice...

    Science.gov (United States)

    2012-07-20

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions; Notice of... limited exclusion order against certain integrated circuits, chipsets, and products containing the same...

  15. 77 FR 39510 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not...

    Science.gov (United States)

    2012-07-03

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not... the sale within the United States after importation of certain semiconductor integrated circuit...

  16. Design techniques for low-voltage analog integrated circuits

    Science.gov (United States)

    Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

    2017-08-01

    In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

  17. Broadband opto-mechanical phase shifter for photonic integrated circuits

    Science.gov (United States)

    Guo, Xiang; Zou, Chang-Ling; Ren, Xi-Feng; Sun, Fang-Wen; Guo, Guang-Can

    2012-08-01

    A broadband opto-mechanical phase shifter for photonic integrated circuits is proposed and numerically investigated. The structure consists of a mode-carrying waveguide and a deformable non-mode-carrying nanostring, which are parallel with each other. Since the nanostring can be deflected by the optical gradient force between the waveguide and the nanostring, the effective refractive indices of the waveguide will be changed and a phase shift will be generated. The phase shift under different geometry sizes, launched powers and boundary conditions are calculated and the dynamical properties as well as the thermal noise's effect are also discussed. It is demonstrated that a π phase shift can be realized with only about 0.64 mW launched power and 50 μm long nanostring. The proposed phase shifter may find potential usage in future investigation of photonic integrated circuits.

  18. On-chip enzymatic microbiofuel cell-powered integrated circuits.

    Science.gov (United States)

    Mark, Andrew G; Suraniti, Emmanuel; Roche, Jérôme; Richter, Harald; Kuhn, Alexander; Mano, Nicolas; Fischer, Peer

    2017-05-16

    A variety of diagnostic and therapeutic medical technologies rely on long term implantation of an electronic device to monitor or regulate a patient's condition. One proposed approach to powering these devices is to use a biofuel cell to convert the chemical energy from blood nutrients into electrical current to supply the electronics. We present here an enzymatic microbiofuel cell whose electrodes are directly integrated into a digital electronic circuit. Glucose oxidizing and oxygen reducing enzymes are immobilized on microelectrodes of an application specific integrated circuit (ASIC) using redox hydrogels to produce an enzymatic biofuel cell, capable of harvesting electrical power from just a single droplet of 5 mM glucose solution. Optimisation of the fuel cell voltage and power to match the requirements of the electronics allow self-powered operation of the on-board digital circuitry. This study represents a step towards implantable self-powered electronic devices that gather their energy from physiological fluids.

  19. Gigahertz flexible graphene transistors for microwave integrated circuits.

    Science.gov (United States)

    Yeh, Chao-Hui; Lain, Yi-Wei; Chiu, Yu-Chiao; Liao, Chen-Hung; Moyano, David Ricardo; Hsu, Shawn S H; Chiu, Po-Wen

    2014-08-26

    Flexible integrated circuits with complex functionalities are the missing link for the active development of wearable electronic devices. Here, we report a scalable approach to fabricate self-aligned graphene microwave transistors for the implementation of flexible low-noise amplifiers and frequency mixers, two fundamental building blocks of a wireless communication receiver. A devised AlOx T-gate structure is used to achieve an appreciable increase of device transconductance and a commensurate reduction of the associated parasitic resistance, thus yielding a remarkable extrinsic cutoff frequency of 32 GHz and a maximum oscillation frequency of 20 GHz; in both cases the operation frequency is an order of magnitude higher than previously reported. The two frequencies work at 22 and 13 GHz even when subjected to a strain of 2.5%. The gigahertz microwave integrated circuits demonstrated here pave the way for applications which require high flexibility and radio frequency operations.

  20. Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

    Science.gov (United States)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2012-01-01

    Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

  1. Radiation Testing and Evaluation Issues for Modern Integrated Circuits

    Science.gov (United States)

    LaBel, Kenneth A.; Cohn, Lew M.

    2005-01-01

    Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

  2. Surface wave modes of printed circuits on ferrite substrates

    Science.gov (United States)

    Yang, Hung-Yu; Castaneda, Jesse A.; Alexopoulos, Nicolaos G.

    1992-04-01

    Surface waves due to a current source on a grounded ferrite slab are investigated. Electromagnetic fields of the structure are in terms of a continuous plane wave spectrum. The spectrum of each field component is obtained numerically through the exponential-matrix method. The surface waves of the structure are extracted from the continuous spectrum by using the residue theorem and the method of steepest descent. Two types of surface waves are found and their properties are described. The surface wave modes found include dynamic surface wave modes which are closely related to the surface waves of a grounded dielectric slab, and magneto-static surface wave modes which are related to the solution of Laplace's equation for the magnetic potential.

  3. Optimization of Segmentation Quality of Integrated Circuit Images

    Directory of Open Access Journals (Sweden)

    Gintautas Mušketas

    2012-04-01

    Full Text Available The paper presents investigation into the application of genetic algorithms for the segmentation of the active regions of integrated circuit images. This article is dedicated to a theoretical examination of the applied methods (morphological dilation, erosion, hit-and-miss, threshold and describes genetic algorithms, image segmentation as optimization problem. The genetic optimization of the predefined filter sequence parameters is carried out. Improvement to segmentation accuracy using a non optimized filter sequence makes 6%.Artcile in Lithuanian

  4. ELECTRON AND OPTICAL BEAM TESTING OF INTEGRATED CIRCUITS

    OpenAIRE

    Collin, J.-P.

    1989-01-01

    The evolution of Integrated Circuits technology and architecture is pushing today the associated test and characterization technology to even higher levels. The test must not only present even higher parametric performances like voltage, temporal and spatial resolutions and a good fault coverage but also high level functionalities like a CAD link and automation capabilities. Each and all of these characteristics, when they are identified as measurement and functional performances, need more a...

  5. Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits

    Science.gov (United States)

    2017-03-01

    H- field; Probe Array; Counterfeit Detection; IC Trust . Introduction Counterfeiting is a huge flail that still continues to serve in the...Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits   contains the RF-switch matrix and broad-band (BB) low noise amplifiers (LNAs...fabricated, tested and used for IC’s TRUST . Measurement setup has been proposed for system validation and of IC scanning surface. Validation test of the

  6. Integrated Circuit Readout for the Silicon Sensor Test Station

    OpenAIRE

    Atkin, E; Kluev, A.; Silaev, A.; Fedenko, A.; Karmanov, D.; Merkin, M.(Moscow State University, Moscow, Russia); Voronin, A.

    2009-01-01

    Various chips for the silicon sensors measurements are described. These chips are based on 0.35 um and 0.18um CMOS technology. Several analog chips together with self-trigger /derandomizer one allow to measure silicon sensors designed for different purposes. Tracking systems, calorimeters, particle charge measurement system and other application sensors can be investigated by the integrated circuit readout with laser or radioactive sources. Also electrical parameters of silicon sensors can be...

  7. Mathematical model of an integrated circuit cooling through cylindrical rods

    OpenAIRE

    Beltrán-Prieto, Luis Antonio; Beltrán-Prieto, Juan Carlos; Komínková Oplatková, Zuzana

    2017-01-01

    One of the main challenges in integrated circuits development is to propose alternatives to handle the extreme heat generated by high frequency of electrons moving in a reduced space that cause overheating and reduce the lifespan of the device. The use of cooling fins offers an alternative to enhance the heat transfer using combined a conduction-convection systems. Mathematical model of such process is important for parametric design and also to gain information about temperature distribution...

  8. Short circuit analysis of distribution system with integration of DG

    DEFF Research Database (Denmark)

    Su, Chi; Liu, Zhou; Chen, Zhe

    2014-01-01

    Integration of distributed generation (DG) such as wind turbines into distribution system is increasing all around the world, because of the flexible and environmentally friendly characteristics. However, DG integration may change the pattern of the fault currents in the distribution system...... during both balanced and unbalanced faults. Major factors such as external grid short circuit power capacity, WT integration location, connection type of WT integration transformer are taken into account. In turn, the challenges brought to the protection system in the distribution network are presented...... and as a result bring challenges to the network protection system. This problem has been frequently discussed in the literature, but mostly considering only the balanced fault situation. This paper presents an investigation on the influence of full converter based wind turbine (WT) integration on fault currents...

  9. Solid-state circuits

    CERN Document Server

    Pridham, G J

    2013-01-01

    Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided

  10. 77 FR 39735 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Science.gov (United States)

    2012-07-05

    ... Integrated Circuit Packages Provided With Multiple Heat- Conducting Paths and Products Containing Same... within the United States after importation of certain integrated circuit packages provided with multiple... importation, or the sale within the United States after importation of certain integrated circuit packages...

  11. 75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

    Science.gov (United States)

    2010-02-04

    ... COMMISSION In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice... importation, and sale within the United States after importation of certain semiconductor integrated circuits... infringement certain LSI integrated circuits, as well as certain Seagate hard disk drives that contain the...

  12. 77 FR 64826 - Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation...

    Science.gov (United States)

    2012-10-23

    ... COMMISSION Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation... integrated circuit chips and products containing the same by reason of infringement of certain claims of U.S... importation of certain integrated circuit chips and products containing the same that infringe one or more of...

  13. Arbitrary modeling of TSVs for 3D integrated circuits

    CERN Document Server

    Salah, Khaled; El-Rouby, Alaa

    2014-01-01

    This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor?and inductive-based

  14. Pneumatic oscillator circuits for timing and control of integrated microfluidics

    Science.gov (United States)

    Duncan, Philip N.; Nguyen, Transon V.; Hui, Elliot E.

    2013-01-01

    Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices. PMID:24145429

  15. Pneumatic oscillator circuits for timing and control of integrated microfluidics.

    Science.gov (United States)

    Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

    2013-11-05

    Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

  16. FDTD-SPICE for Characterizing Metamaterials Integrated with Electronic Circuits

    Directory of Open Access Journals (Sweden)

    Zhengwei Hao

    2012-01-01

    Full Text Available A powerful time-domain FDTD-SPICE simulator is implemented and applied to the broadband analysis of metamaterials integrated with active and tunable circuit elements. First, the FDTD-SPICE modeling theory is studied and details of interprocess communication and hybridization of the two techniques are discussed. To verify the model, some simple cases are simulated with results in both time domain and frequency domain. Then, simulation of a metamaterial structure constructed from periodic resonant loops integrated with lumped capacitor elements is studied, which demonstrates tuning resonance frequency of medium by changing the capacitance of the integrated elements. To increase the bandwidth of the metamaterial, non-Foster transistor configurations are integrated with the loops and FDTD-SPICE is applied to successfully bridge the physics of electromagnetic and circuit topologies and to model the whole composite structure. Our model is also applied to the design and simulation of a metasurface integrated with nonlinear varactors featuring tunable reflection phase characteristic.

  17. Generation of optical vortices in an integrated optical circuit

    Science.gov (United States)

    Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

    2017-09-01

    In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = ‑1.

  18. Design automation for integrated nonlinear logic circuits (Conference Presentation)

    Science.gov (United States)

    Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

    2016-05-01

    A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

  19. Integrated diode circuits for greater than 1 THz

    Science.gov (United States)

    Schoenthal, Gerhard Siegbert

    The terahertz frequency band, spanning from roughly 100 GHz to 10 THz, forms the transition from electronics to photonics. This band is often referred to as the "terahertz technology gap" because it lacks typical microwave and optical components. The deficit of terahertz devices makes it difficult to conduct important scientific measurements that are exclusive to this band in fields such as radio astronomy and chemical spectroscopy. In addition, a number of scientific, military and commercial applications will become more practical when a suitable terahertz technology is developed. UVa's Applied Electrophysics Laboratory has extended non-linear microwave diode technology into the terahertz region. Initial success was achieved with whisker-contacted diodes and then discrete planar Schottky diodes soldered onto quartz circuits. Work at UVa and the Jet Propulsion Laboratory succeeded in integrating this diode technology onto low dielectric substrates, thereby producing more practical components with greater yield and improved performance. However, the development of circuit integration technologies for greater than 1 THz and the development of broadly tunable sources of terahertz power remain as major research goals. Meeting these critical needs is the primary motivation for this research. To achieve this goal and demonstrate a useful prototype for one of our sponsors, this research project has focused on the development of a Sideband Generator at 1.6 THz. This component allows use of a fixed narrow band source as a tunable power source for terahertz spectroscopy and compact range radar. To prove the new fabrication and circuit technologies, initial devices were fabricated and tested at 200 and 600 GHz. These circuits included non-ohmic cathodes, air-bridged fingers, oxideless anode formation, and improved quartz integration processes. The excellent performance of these components validated these new concepts. The prototype process was then further optimized to

  20. Development of Integrated Single Flux Quantum - Superconducting Qubit Circuits

    Science.gov (United States)

    Leonard, Edward, Jr.; Thorbeck, Ted; Zhu, Shaojiang; Howington, Caleb; Hutchings, Matthew; Nelson, Jj; Plourde, Britton; McDermott, Robert

    Significant theoretical and experimental progress has been made in recent years towards a scalable superconducting quantum circuit architecture. Here we present a first attempt to integrate classical control elements from the single flux quantum (SFQ) digital logic family with a superconducting transom qubit on a single chip. The SFQ driving circuit is fabricated in a six-layer high-Jc Nb/Al-AlOx/Nb junction process while the transmon qubit is subsequently formed using submicron Al-AlOx-Al junctions grown by double-angle evaporation. We investigate sources of decoherence associated with the more complex fabrication process and describe first attempts to perform coherent qubit manipulations using resonant trains of SFQ pulses.

  1. A novel readout integrated circuit for ferroelectric FPA detector

    Science.gov (United States)

    Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

    2017-11-01

    Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

  2. Multifunctional and multi-output plasmonic meta-elements for integrated optical circuits.

    Science.gov (United States)

    Wang, Jiayuan; Hu, Chuang; Zhang, Jiasen

    2014-09-22

    Based on a novel phase-sieve method by in-plane interference processes, a well-designed nonperiodic nanogroove array on gold surface is proposed as a multifunctional and multi-output plasmonic meta-element (MPM) for surface plasmon polariton waves. An MPM functions as a plasmonic lens (PL) as well as a plasmonic array illuminator (PAI), and another MPM acts as two PLs with an intersection angle of π/4 are fabricated and validated by leakage radiation microscopy measurements. Our proposed scheme with implemented functionalities could promote potential applications in high density integrated optical circuits.

  3. Method of making thermally-isolated silicon-based integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.; Bauer, Todd

    2017-11-21

    Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

  4. Thermally-isolated silicon-based integrated circuits and related methods

    Energy Technology Data Exchange (ETDEWEB)

    Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

    2017-05-09

    Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

  5. Lithography for enabling advances in integrated circuits and devices.

    Science.gov (United States)

    Garner, C Michael

    2012-08-28

    Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

  6. Advances in integrated photonic circuits for packet-switched interconnection

    Science.gov (United States)

    Williams, Kevin A.; Stabile, Ripalta

    2014-03-01

    Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

  7. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  8. Integrated circuits: Resistless processing simplifies production and cuts costs

    Science.gov (United States)

    Weiner, K.

    1993-03-01

    Reducing the complexity and cost of producing deep-submicrometer integrated circuits (IC's) will soon be possible using a revolutionary approach being developed at the Lawrence Livermore National Laboratory (LLNL). Resistless Projection Doping (RPD) will eliminate the need for photoresist processing during the impurity doping step. This single innovation will reduce the doping sequence from 13 steps to 1 and eliminate the need for five pieces of capital equipment costing more than $5 million. The overall cost of high-volume wafer fabrication will be reduced by more than 10 percent. In addition, the LLNL RPD machine is compact and modular, minimizing facilities costs when compared to today's industry-standard doping equipment. These physical characteristics of the machine also allow the RPD process to be easily incorporated into single-wafer, 'cluster' processing tools. When integrated with existing deposition, etching, and annealing steps and developing lithography techniques, the LLNL doping process completes the technology set required to produce a flexible fabrication facility of the future. At one-fifth the cost of current mega-fabrication facilities, the availability of these compact, low-volume, smart factories will give US manufacturers a substantial competitive advantage in the world-wide marketplace for high-value custom and semi-custom integrated circuits.

  9. Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices

    Directory of Open Access Journals (Sweden)

    Lee Carroll

    2016-12-01

    Full Text Available Dedicated multi-project wafer (MPW runs for photonic integrated circuits (PICs from Si foundries mean that researchers and small-to-medium enterprises (SMEs can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

  10. Numerical counting ratemeter with variable time constant and integrated circuits; Ictometre numerique a constante de temps variable a circuits integres

    Energy Technology Data Exchange (ETDEWEB)

    Kaiser, J.; Fuan, J. [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

    1967-07-01

    We present here the prototype of a numerical counting ratemeter which is a special version of variable time-constant frequency meter (1). The originality of this work lies in the fact that the change in the time constant is carried out automatically. Since the criterion for this change is the accuracy in the annunciated result, the integration time is varied as a function of the frequency. For the prototype described in this report, the time constant varies from 1 sec to 1 millisec. for frequencies in the range 10 Hz to 10 MHz. This prototype is built entirely of MECL-type integrated circuits from Motorola and is thus contained in two relatively small boxes. (authors) [French] Nous presentons ici le prototype d'un ictometre numerique, celui-ci etant une version speciale d'un frequencemetre a constante de temps variable (1). Le nouvel interet de cette etude est le fait que le changement de la constante de temps se fait automatiquement. Le critere de ce changement etant la precision du resultat a afficher on change alors le temps d'integration en fonction de la frequence. Pour le prototype decrit dans ce rapport la constante de temps varie entre 1 s et 1 ms pour des frequences allant de 10 Hz a 10 MHz. Ce prototype est entierement realise en circuit integre type MECL de Motorola et se presente en consequence dans deux boitiers d'une taille relativement petite. (auteurs)

  11. Ring-plane traveling-wave tube slow-wave circuit design simulations at V-Band frequencies

    Science.gov (United States)

    Kory, Carol L.; Wilson, Jeffrey D.

    1995-01-01

    The V-Band frequency range of 59-64 GHz is a region of the millimeter-wave spectrum that has been designated for intersatellite communications. As a first effort to develop a high-efficiency V-band TWT, variations on a ring-plane slow-wave circuit were computationally investigated to develop an alternative to the more conventional ferruled coupled-cavity circuit. The ring-plane circuit was chosen because of its high interaction impedance, large beam aperture, and excellent thermal dissipation properties. Despite the high-power capabilities of the ring-plane TWT, disadvantages of low bandwidth and high voltage requirements have until now prevented its acceptance outside the laboratory. In this paper, we use the three-dimensional electromagnetic simulation code MAFIA to investigate methods of increasing the bandwidth and lowering the operating voltage. Dispersion, impedance, and attenuation calculations for various geometric variations and loading distributions were performed. Based on the results of the variations, a circuit termed the finned-ladder TWT slowwave circuit was designed and is compared here to the scaled ring-plane prototype and the conventional ferruled coupled-cavity TWT circuit over the V-band frequency range.

  12. Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

    Science.gov (United States)

    Shahrjerdi, Davood; Bedell, Stephen W

    2013-01-09

    In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

  13. Integrated biocircuits: engineering functional multicellular circuits and devices.

    Science.gov (United States)

    Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

    2018-01-19

    Novel in vitro platforms are currently revolutionizing the study and reconstruction of cellular circuitry to bypass the pertaining obstacles of data retrieval in vivo. While earlier approaches have provided great insights into culturing circuits in planar dissociated cell culture systems, the lack of full control over network activity and formation limits our understanding of their functionality. Thus, integrating various controllable parameters are required in creating a suitable microenvironment including cell patterning, highly-specified electrical and chemical stimuli, and rational circuit formation via logic functions. Recent advancements in organoid and 3D culture systems account for another major microenvironment factor of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain and other neural structures and compare them to disease models to identify the underlying principles of pathology. This perspective focuses on exploring the current state of the art of living multicellular device technologies to provide knowledge of the advancements of the fabrication processes and identify the current biological principles that are applied in designing these devices. It then provides perspectives and proposes new insights into the future of these devices within the scope of living cellular devices that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics. © 2018 IOP Publishing Ltd.

  14. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  15. Custom Integrated Circuit Design for Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere

    ) are contained in the probe. Due to the nature of ultrasonic transducers, the transmitting circuitry needs to generate high-voltage pulses to drive them. Furthermore, the low-voltage receiving circuitry has to provide high enough signal to noise ratio (SNR) in order to generate usable imaging. For the purpose...... of evaluating the feasibility of the transmitting and receiving circuitry of a handheld probe for portable ultrasound scanners, three integrated circuit prototypes have been fabricated. Measurements have been performed on all of them with satisfactory results. The first part of this project is focused...

  16. Inspection of the integrity of surface mounted integrated circuits on a printed circuit board using vision

    OpenAIRE

    Yakoub, Imad

    1991-01-01

    Machine vision technology has permeated many areas of industry, and automated inspection systems are playing increasingly important roles in many production processes. Electronic manufacturing is a good example of the integration of vision based feedback in manufacturing and the assembly of surface mount PCBs is typical of the technology involved. There are opportunities to use machine vision during different stages of the surface mount process. The problem in the inspection of solder joints ...

  17. Integrated circuits based on bilayer MoS₂ transistors.

    Science.gov (United States)

    Wang, Han; Yu, Lili; Lee, Yi-Hsien; Shi, Yumeng; Hsu, Allen; Chin, Matthew L; Li, Lain-Jong; Dubey, Madan; Kong, Jing; Palacios, Tomas

    2012-09-12

    Two-dimensional (2D) materials, such as molybdenum disulfide (MoS(2)), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS(2) allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene's advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors, and photodetectors made from few-layer MoS(2) show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multistage circuits and logic building blocks on MoS(2) to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic technology. The circuits comprise between 2 to 12 transistors seamlessly integrated side-by-side on a single sheet of bilayer MoS(2). Both enhancement-mode and depletion-mode transistors were fabricated thanks to the use of gate metals with different work functions.

  18. Integrated circuit amplifiers for multi-electrode intracortical recording.

    Science.gov (United States)

    Jochum, Thomas; Denison, Timothy; Wolf, Patrick

    2009-02-01

    Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

  19. Mixed signal custom integrated circuit development for physics instrumentation

    Energy Technology Data Exchange (ETDEWEB)

    Britton, C.L. Jr.; Bryan, W.L.; Emery, M.S. [and others

    1998-10-01

    The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented.

  20. High quality silicon-based substrates for microwave and millimeter wave passive circuits

    Science.gov (United States)

    Belaroussi, Y.; Rack, M.; Saadi, A. A.; Scheen, G.; Belaroussi, M. T.; Trabelsi, M.; Raskin, J.-P.

    2017-09-01

    Porous silicon substrate is very promising for next generation wireless communication requiring the avoidance of high-frequency losses originating from the bulk silicon. In this work, new variants of porous silicon (PSi) substrates have been introduced. Through an experimental RF performance, the proposed PSi substrates have been compared with different silicon-based substrates, namely, standard silicon (Std), trap-rich (TR) and high resistivity (HR). All of the mentioned substrates have been fabricated where identical samples of CPW lines have been integrated on. The new PSi substrates have shown successful reduction in the substrate's effective relative permittivity to values as low as 3.7 and great increase in the substrate's effective resistivity to values higher than 7 kΩ cm. As a concept proof, a mm-wave bandpass filter (MBPF) centred at 27 GHz has been integrated on the investigated substrates. Compared with the conventional MBPF implemented on standard silicon-based substrates, the measured S-parameters of the PSi-based MBPF have shown high filtering performance, such as a reduction in insertion loss and an enhancement of the filter selectivity, with the joy of having the same filter performance by varying the temperature. Therefore, the efficiency of the proposed PSi substrates has been well highlighted. From 1994 to 1995, she was assistant of physics at (USTHB), Algiers . From 1998 to 2011, she was a Researcher at characterization laboratory in ionized media and laser division at the Advanced Technologies Development Center. She has integrated the Analog Radio Frequency Integrated Circuits team as Researcher since 2011 until now in Microelectronic and Nanotechnology Division at Advanced Technologies Development Center (CDTA), Algiers. She has been working towards her Ph.D. degree jointly at CDTA and Ecole Nationale Polytechnique, Algiers, since 2012. Her research interest includes fabrication and characterization of microwave passive devices on porous

  1. Analysis of Wave Propagation in Stratified Structures Using Circuit Analogues, with Application to Electromagnetic Absorbers

    Science.gov (United States)

    Sjoberg, Daniel

    2008-01-01

    This paper presents an overview of how circuit models can be used for analysing wave propagation in stratified structures. Relatively complex structures can be analysed using models which are accessible to undergraduate students. Homogeneous slabs are modelled as transmission lines, and thin sheets between the slabs are modelled as lumped…

  2. Modeling of the Voltage Waves in the LHC Main Dipole Circuits

    CERN Document Server

    Ravaioli, E; Formenti, F; Steckert, J; Thiesen, H; Verweij, A

    2012-01-01

    When a fast power abort is triggered in the LHC main dipole chain, voltage transients are generated at the output of the power converter and across the energy-extraction switches. The voltage waves propagate through the chain of 154 superconducting dipoles and can have undesired effects leading to spurious triggering of the quench protection system and firing of the quench heaters. The phase velocity of the waves travelling along the chain changes due to the inhomogeneous AC behavior of the dipoles. Furthermore, complex phenomena of reflection and superposition are present in the circuit. For these reasons analytical calculations are not sufficient for properly analyzing the circuit behavior after a fast power abort. The transients following the switch-off of the power converter and the opening of the switches are analyzed by means of a complete electrical model, developed with the Cadence© suite (PSpice© based). The model comprises all the electrical components of the circuit, additional components simula...

  3. Sub-millimeter-Wave Equivalent Circuit Model for External Parasitics in Double-Finger HEMT Topologies

    Science.gov (United States)

    Karisan, Yasir; Caglayan, Cosan; Sertel, Kubilay

    2018-02-01

    We present a novel distributed equivalent circuit that incorporates a three-way-coupled transmission line to accurately capture the external parasitics of double-finger high electron mobility transistor (HEMT) topologies up to 750 GHz. A six-step systematic parameter extraction procedure is used to determine the equivalent circuit elements for a representative device layout. The accuracy of the proposed approach is validated in the 90-750 GHz band through comparisons between measured data (via non-contact probing) and full-wave simulations, as well as the equivalent circuit response. Subsequently, a semi-distributed active device model is incorporated into the proposed parasitic circuit to demonstrate that the three-way-coupled transmission line model effectively predicts the adverse effect of parasitic components on the sub-mmW performance in an amplifier setting.

  4. Integrated Circuit Design in US High-Energy Physics

    Energy Technology Data Exchange (ETDEWEB)

    Geronimo, G. D. [Brookhaven National Lab. (BNL), Upton, NY (United States); Christian, D. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Bebek, C. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Garcia-Sciveres, M. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Lippe, H. V. D. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Haller, G. [SLAC National Accelerator Lab., Menlo Park, CA (United States); Grillo, AA [Univ. of California, Santa Cruz, CA (United States); Newcomer, M [Univ. of Pennsylvania, Philadelphia, PA (United States)

    2013-07-10

    This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies; Outlook of future technologies including 2.5D and 3D; Survey of ICs used in current experiments and ICs targeted for approved or proposed experiments; IC design at US institutes and recommendations for collaboration in the future.

  5. Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

    Science.gov (United States)

    Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

    2015-04-06

    Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

  6. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Science.gov (United States)

    2012-03-29

    ... Certain Semiconductor Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is... importation of certain semiconductor integrated circuit devices and products containing same. The complaint...] [FR Doc No: 2012-7567] INTERNATIONAL TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated...

  7. Infrared transparent graphene heater for silicon photonic integrated circuits.

    Science.gov (United States)

    Schall, Daniel; Mohsin, Muhammad; Sagade, Abhay A; Otto, Martin; Chmielak, Bartos; Suckow, Stephan; Giesecke, Anna Lena; Neumaier, Daniel; Kurz, Heinrich

    2016-04-18

    Thermo-optical tuning of the refractive index is one of the pivotal operations performed in integrated silicon photonic circuits for thermal stabilization, compensation of fabrication tolerances, and implementation of photonic operations. Currently, heaters based on metal wires provide the temperature control in the silicon waveguide. The strong interaction of metal and light, however, necessitates a certain gap between the heater and the photonic structure to avoid significant transmission loss. Here we present a graphene heater that overcomes this constraint and enables an energy efficient tuning of the refractive index. We achieve a tuning power as low as 22 mW per free spectral range and fast response time of 3 µs, outperforming metal based waveguide heaters. Simulations support the experimental results and suggest that for graphene heaters the spacing to the silicon can be further reduced yielding the best possible energy efficiency and operation speed.

  8. Photonic integrated circuits unveil crisis-induced intermittency.

    Science.gov (United States)

    Karsaklian Dal Bosco, Andreas; Akizawa, Yasuhiro; Kanno, Kazutaka; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki

    2016-09-19

    We experimentally investigate an intermittent route to chaos in a photonic integrated circuit consisting of a semiconductor laser with time-delayed optical feedback from a short external cavity. The transition from a period-doubling dynamics to a fully-developed chaos reveals a stage intermittently exhibiting these two dynamics. We unveil the bifurcation mechanism underlying this route to chaos by using the Lang-Kobayashi model and demonstrate that the process is based on a phenomenon of attractor expansion initiated by a particular distribution of the local Lyapunov exponents. We emphasize on the crucial importance of the distribution of the steady-state solutions introduced by the time-delayed feedback on the existence of this intermittent dynamics.

  9. Uncertain behaviours of integrated circuits improve computational performance.

    Science.gov (United States)

    Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

    2015-11-20

    Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance.

  10. Two multichannel integrated circuits for neural recording and signal processing.

    Science.gov (United States)

    Obeid, Iyad; Morizio, James C; Moxon, Karen A; Nicolelis, Miguel A L; Wolf, Patrick D

    2003-02-01

    We have developed, manufactured, and tested two analog CMOS integrated circuit "neurochips" for recording from arrays of densely packed neural electrodes. Device A is a 16-channel buffer consisting of parallel noninverting amplifiers with a gain of 2 V/V. Device B is a 16-channel two-stage analog signal processor with differential amplification and high-pass filtering. It features selectable gains of 250 and 500 V/V as well as reference channel selection. The resulting amplifiers on Device A had a mean gain of 1.99 V/V with an equivalent input noise of 10 microV(rms). Those on Device B had mean gains of 53.4 and 47.4 dB with a high-pass filter pole at 211 Hz and an equivalent input noise of 4.4 microV(rms). Both devices were tested in vivo with electrode arrays implanted in the somatosensory cortex.

  11. Further on integrator circuit analogy for natural convection

    Energy Technology Data Exchange (ETDEWEB)

    Khane, Vaibhav [Nuclear Engineering, Missouri University of Science and Technology, 225 Fulton Hall, 300W. 13th St., Rolla, MO-65409 (United States); Usman, Shoaib, E-mail: usmans@mst.ed [Nuclear Engineering, Missouri University of Science and Technology, 225 Fulton Hall, 300W. 13th St., Rolla, MO-65409 (United States)

    2010-03-15

    This research is an extension of the previous work on the development of an integrator (RC) circuit analogy for natural convection. This analogy has been proven experimentally as well as by numerical simulations. Additional Rayleigh-Benard convection numerical simulations were performed to investigate DELTAT (temperature difference between source and sink) dependence of the thermal resistance of a natural convection system. Our results suggest that analogous to voltage dependent resistor (VDR) in electrical engineering, DELTAT dependent thermal resistance is observed in natural convection system. This DELTAT dependent thermal resistance leads to a variable time constant. Moreover, this research also suggests that for a natural convection system, in addition to the thermal capacitance a kinetic energy capacitance also exists. The relative contribution of kinetic energy capacitance depends on Rayleigh number. These results provide significant step forward towards development of a new inexpensive modeling and transient analysis tool for a natural convection system.

  12. Enabling the Internet of Things from integrated circuits to integrated systems

    CERN Document Server

    2017-01-01

    This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a fresh perspective on how the IoT will evolve based on recent and foreseeable trends in the semiconductor industry, highlighting the key challenges, as well as the opportunities for circuit and system innovation to address them. This book describes what the IoT really means from the design point of view, and how the constraints imposed by applications translate into integrated circuit requirements and design guidelines. Chapter contributions equally come from industry and academia. After providing a system perspective on IoT nodes, this book focuses on state-of-the-art design techniques for IoT applications, encompassing the fundamental sub-systems encountered in Systems on Chip for IoT: ultra-low power digital architectures and circuits low- and zero-leakage memories (including emerging technologies) circuits for hardwar...

  13. One-chip analog circuits for a new type of plasma wave receiver on board space missions

    Science.gov (United States)

    Zushi, Takahiro; Kojima, Hirotsugu; Yamakawa, Hiroshi

    2017-03-01

    Plasma waves are important observational targets for scientific missions investigating space plasma phenomena. Conventional fast Fourier transform (FFT)-based spectrum plasma wave receivers have the disadvantages of a large size and a narrow dynamic range. This paper proposes a new type of FFT-based spectrum plasma wave receiver that overcomes the disadvantages of conventional receivers. The receiver measures and calculates the whole spectrum by dividing the observation frequency range into three bands: bands 1, 2, and 3, which span 1 Hz to 1 kHz, 1 to 10 kHz, and 10 to 100 kHz, respectively. To reduce the size of the receiver, its analog section was realized using application-specific integrated circuit (ASIC) technology, and an ASIC chip was successfully developed. The dimensions of the analog circuits were 4.21 mm × 1.16 mm. To confirm the performance of the ASIC, a test system for the receiver was developed using the ASIC, an analog-to-digital converter, and a personal computer. The frequency resolutions for bands 1, 2, and 3 were 3.2, 32, and 320 Hz, respectively, and the average time resolution was 384 ms. These frequency and time resolutions are superior to those of conventional FFT-based receivers.

  14. Propagation and localization of acoustic waves in Fibonacci phononic circuits

    Energy Technology Data Exchange (ETDEWEB)

    Aynaou, H [Laboratoire de Dynamique et d' Optique des Materiaux, Departement de Physique, Faculte des Sciences, Universite Mohamed Premier, 60000 Oujda (Morocco); Boudouti, E H El [Laboratoire de Dynamique et d' Optique des Materiaux, Departement de Physique, Faculte des Sciences, Universite Mohamed Premier, 60000 Oujda (Morocco); Djafari-Rouhani, B [Laboratoire de Dynamique et Structure des Materiaux Moleculaires, UMR CNRS 8024, UFR de Physique, Universite de Lille 1, F-59655 Villeneuve d' Ascq (France); Akjouj, A [Laboratoire de Dynamique et Structure des Materiaux Moleculaires, UMR CNRS 8024, UFR de Physique, Universite de Lille 1, F-59655 Villeneuve d' Ascq (France); Velasco, V R [Instituto de Ciencia de Materiales de Madrid, CSIC, Sor Juana Ines de la Cruz 3, 28049 Madrid (Spain)

    2005-07-13

    A theoretical investigation is made of acoustic wave propagation in one-dimensional phononic bandgap structures made of slender tube loops pasted together with slender tubes of finite length according to a Fibonacci sequence. The band structure and transmission spectrum is studied for two particular cases. (i) Symmetric loop structures, which are shown to be equivalent to diameter-modulated slender tubes. In this case, it is found that besides the existence of extended and forbidden modes, some narrow frequency bands appear in the transmission spectra inside the gaps as defect modes. The spatial localization of the modes lying in the middle of the bands and at their edges is examined by means of the local density of states. The dependence of the bandgap structure on the slender tube diameters is presented. An analysis of the transmission phase time enables us to derive the group velocity as well as the density of states in these structures. In particular, the stop bands (localized modes) may give rise to unusual (strong normal) dispersion in the gaps, yielding fast (slow) group velocities above (below) the speed of sound. (ii) Asymmetric tube loop structures, where the loops play the role of resonators that may introduce transmission zeros and hence new gaps unnoticed in the case of simple diameter-modulated slender tubes. The Fibonacci scaling property has been checked for both cases (i) and (ii), and it holds for a periodicity of three or six depending on the nature of the substrates surrounding the structure.

  15. Energy scavenging system by acoustic wave and integrated wireless communication

    Science.gov (United States)

    Kim, Albert

    The purpose of the project was developing an energy-scavenging device for other bio implantable devices. Researchers and scientist have studied energy scavenging method because of the limitation of traditional power source, especially for bio-implantable devices. In this research, piezoelectric power generator that activates by acoustic wave, or music was developed. Follow by power generator, a wireless communication also integrated with the device for monitoring the power generation. The Lead Zirconate Titanate (PZT) bimorph cantilever with a proof mass at the free end tip was studied to convert acoustic wave to power. The music or acoustic wave played through a speaker to vibrate piezoelectric power generator. The LC circuit integrated with the piezoelectric material for purpose of wireless monitoring power generation. However, wireless monitoring can be used as wireless power transmission, which means the signal received via wireless communication also can be used for power for other devices. Size of 74 by 7 by 7cm device could generate and transmit 100mVp from 70 mm distance away with electrical resonant frequency at 420.2 kHz..

  16. SDN architecture for optical packet and circuit integrated networks

    Science.gov (United States)

    Furukawa, Hideaki; Miyazawa, Takaya

    2016-02-01

    We have been developing an optical packet and circuit integrated (OPCI) network, which realizes dynamic optical path, high-density packet multiplexing, and flexible wavelength resource allocation. In the OPCI networks, a best-effort service and a QoS-guaranteed service are provided by employing optical packet switching (OPS) and optical circuit switching (OCS) respectively, and users can select these services. Different wavelength resources are assigned for OPS and OCS links, and the amount of their wavelength resources are dynamically changed in accordance with the service usage conditions. To apply OPCI networks into wide-area (core/metro) networks, we have developed an OPCI node with a distributed control mechanism. Moreover, our OPCI node works with a centralized control mechanism as well as a distributed one. It is therefore possible to realize SDN-based OPCI networks, where resource requests and a centralized configuration are carried out. In this paper, we show our SDN architecture for an OPS system that configures mapping tables between IP addresses and optical packet addresses and switching tables according to the requests from multiple users via a web interface. While OpenFlow-based centralized control protocol is coming into widespread use especially for single-administrative, small-area (LAN/data-center) networks. Here, we also show an interworking mechanism between OpenFlow-based networks (OFNs) and the OPCI network for constructing a wide-area network, and a control method of wavelength resource selection to automatically transfer diversified flows from OFNs to the OPCI network.

  17. Laser Direct Writing and Selective Metallization of Metallic Circuits for Integrated Wireless Devices.

    Science.gov (United States)

    Cai, Jinguang; Lv, Chao; Watanabe, Akira

    2018-01-10

    Portable and wearable devices have attracted wide research attention due to their intimate relations with human daily life. As basic structures in the devices, the preparation of high-conductive metallic circuits or micro-circuits on flexible substrates should be facile, cost-effective, and easily integrated with other electronic units. In this work, high-conductive carbon/Ni composite structures were prepared by using a facile laser direct writing method, followed by an electroless Ni plating process, which exhibit a 3-order lower sheet resistance of less than 0.1 ohm/sq compared to original structures before plating, showing the potential for practical use. The carbon/Ni composite structures exhibited a certain flexibility and excellent anti-scratch property due to the tight deposition of Ni layers on carbon surfaces. On the basis of this approach, a wireless charging and storage device on a polyimide film was demonstrated by integrating an outer rectangle carbon/Ni composite coil for harvesting electromagnetic waves and an inner carbon micro-supercapacitor for energy storage, which can be fast charged wirelessly by a commercial wireless charger. Furthermore, a near-field communication (NFC) tag was prepared by combining a carbon/Ni composite coil for harvesting signals and a commercial IC chip for data storage, which can be used as an NFC tag for practical application.

  18. Wave regularity in curve integrable spacetimes

    CERN Document Server

    Sanchez, Yafet Sanchez

    2015-01-01

    The idea of defining a gravitational singularity as an obstruction to the dynamical evolution of a test field (described by a PDE) rather than the dynamical evolution of a particle (described by a geodesics) is explored. In particular, the concept of wave regularity is introduced which serves to show that the classical singularities in curve integrable spacetimes do not interrupt the well-posedness of the wave equation. The techniques used also provide arguments that can be extended to establish when a classically singular spacetime remains singular in a semi-classical picture.

  19. High-speed coherent silicon modulator module using photonic integrated circuits: from circuit design to packaged module

    Science.gov (United States)

    Bernabé, S.; Olivier, S.; Myko, A.; Fournier, M.; Blampey, B.; Abraham, A.; Menezo, S.; Hauden, J.; Mottet, A.; Frigui, K.; Ngoho, S.; Frigui, B.; Bila, S.; Marris-Morini, D.; Pérez-Galacho, D.; Brindel, P.; Charlet, G.

    2016-05-01

    Silicon photonics technology is an enabler for the integration of complex circuits on a single chip, for various optical link applications such as routing, optical networks on chip, short range links and long haul transmitters. Quadrature Phase Shift Keying (QPSK) transmitters is one of the typical circuits that can be achieved using silicon photonics integrated circuits. The achievement of 25GBd QPSK transmitter modules requires several building blocks to be optimized: the pn junction used to build a BPSK (Binary Shift Phase Keying) modulator, the RF access and the optical interconnect at the package level. In this paper, we describe the various design steps of a BPSK module and the related tests that are needed at every stage of the fabrication process.

  20. 77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

    Science.gov (United States)

    2012-10-04

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of... importation, and the sale within the United States after importation of certain semiconductor integrated circuit devices and products containing same by reason of infringement of certain claims of U.S. Patent...

  1. Experimental Demonstration of 7 Tb/s Switching Using Novel Silicon Photonic Integrated Circuit

    DEFF Research Database (Denmark)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

    2016-01-01

    We demonstrate BER performance <10^-9 for a 1 Tb/s/core transmission over 7-core fiber and SDM switching using a novel silicon photonic integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers.......We demonstrate BER performance integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers....

  2. 77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

    Science.gov (United States)

    2012-05-01

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of... devices and products containing same by reason of infringement of certain claims of U.S. Patent No. 7,225... semiconductor integrated circuit devices and products containing same that infringe one or more of claims 1, 2...

  3. Vertical chip-to-chip coupling between silicon photonic integrated circuits using cantilever couplers.

    Science.gov (United States)

    Sun, Peng; Reano, Ronald M

    2011-02-28

    We demonstrate vertical chip-to-chip light coupling using silicon strip waveguide cantilever couplers. The guided-wave couplers consist of silicon strip waveguides embedded within silicon dioxide cantilevers. The cantilevers deflect 90° out-of-plane via residual stress, allowing vertical light coupling between separate chips. A chip-to-chip coupling loss of 2.5 dB per connection is measured for TE polarization and 1.1 dB for TM polarization at 1550 nm wavelength. The coupling loss varies by less than±0.8 dB within the wavelength range from 1500 nm to 1565 nm for both polarizations. The couplers enable broadband and compact system architectures involving high speed vertical data transport between photonic integrated circuits.

  4. Design structure for in-system redundant array repair in integrated circuits

    Science.gov (United States)

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

    2008-11-25

    A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  5. Mathematical model of an integrated circuit cooling through cylindrical rods

    Directory of Open Access Journals (Sweden)

    Beltrán-Prieto Luis Antonio

    2017-01-01

    Full Text Available One of the main challenges in integrated circuits development is to propose alternatives to handle the extreme heat generated by high frequency of electrons moving in a reduced space that cause overheating and reduce the lifespan of the device. The use of cooling fins offers an alternative to enhance the heat transfer using combined a conduction-convection systems. Mathematical model of such process is important for parametric design and also to gain information about temperature distribution along the surface of the transistor. In this paper, we aim to obtain the equations for heat transfer along the chip and the fin by performing energy balance and heat transfer by conduction from the chip to the rod, followed by dissipation to the surrounding by convection. Newton's law of cooling and Fourier law were used to obtain the equations that describe the profile temperature in the rod and the surface of the chip. Ordinary differential equations were obtained and the respective analytical solutions were derived after consideration of boundary conditions. The temperature along the rod decreased considerably from the initial temperature (in contatct with the chip surface. This indicates the benefit of using a cilindrical rod to distribute the heat generated in the chip.

  6. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    Science.gov (United States)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  7. Graphene-on-silicon hybrid plasmonic-photonic integrated circuits.

    Science.gov (United States)

    Xiao, Ting-Hui; Cheng, Zhenzhou; Goda, Keisuke

    2017-06-16

    Graphene surface plasmons (GSPs) have shown great potential in biochemical sensing, thermal imaging, and optoelectronics. To excite GSPs, several methods based on the near-field optical microscope and graphene nanostructures have been developed in the past few years. However, these methods suffer from their bulky setups and low GSP-excitation efficiency due to the short interaction length between free-space vertical excitation light and the atomic layer of graphene. Here we present a CMOS-compatible design of graphene-on-silicon hybrid plasmonic-photonic integrated circuits that achieve the in-plane excitation of GSP polaritons as well as localized surface plasmon (SP) resonance. By employing a suspended membrane slot waveguide, our design is able to excite GSP polaritons on a chip. Moreover, by utilizing a graphene nanoribbon array, we engineer the transmission spectrum of the waveguide by excitation of localized SP resonance. Our theoretical and computational study paves a new avenue to enable, modulate, and monitor GSPs on a chip, potentially applicable for the development of on-chip electro-optic devices.

  8. An integrated modelling framework for neural circuits with multiple neuromodulators.

    Science.gov (United States)

    Joshi, Alok; Youssofzadeh, Vahab; Vemana, Vinith; McGinnity, T M; Prasad, Girijesh; Wong-Lin, KongFatt

    2017-01-01

    Neuromodulators are endogenous neurochemicals that regulate biophysical and biochemical processes, which control brain function and behaviour, and are often the targets of neuropharmacological drugs. Neuromodulator effects are generally complex partly owing to the involvement of broad innervation, co-release of neuromodulators, complex intra- and extrasynaptic mechanism, existence of multiple receptor subtypes and high interconnectivity within the brain. In this work, we propose an efficient yet sufficiently realistic computational neural modelling framework to study some of these complex behaviours. Specifically, we propose a novel dynamical neural circuit model that integrates the effective neuromodulator-induced currents based on various experimental data (e.g. electrophysiology, neuropharmacology and voltammetry). The model can incorporate multiple interacting brain regions, including neuromodulator sources, simulate efficiently and easily extendable to large-scale brain models, e.g. for neuroimaging purposes. As an example, we model a network of mutually interacting neural populations in the lateral hypothalamus, dorsal raphe nucleus and locus coeruleus, which are major sources of neuromodulator orexin/hypocretin, serotonin and norepinephrine/noradrenaline, respectively, and which play significant roles in regulating many physiological functions. We demonstrate that such a model can provide predictions of systemic drug effects of the popular antidepressants (e.g. reuptake inhibitors), neuromodulator antagonists or their combinations. Finally, we developed user-friendly graphical user interface software for model simulation and visualization for both fundamental sciences and pharmacological studies. © 2017 The Authors.

  9. Experimental demonstration of interferometric imaging using photonic integrated circuits.

    Science.gov (United States)

    Su, Tiehui; Scott, Ryan P; Ogden, Chad; Thurman, Samuel T; Kendrick, Richard L; Duncan, Alan; Yu, Runxiang; Yoo, S J B

    2017-05-29

    This paper reports design, fabrication, and demonstration of a silica photonic integrated circuit (PIC) capable of conducting interferometric imaging with multiple baselines around λ = 1550 nm. The PIC consists of four sets of five waveguides (total of twenty waveguides), each leading to a three-band spectrometer (total of sixty waveguides), after which a tunable Mach-Zehnder interferometer (MZI) constructs interferograms from each pair of the waveguides. A total of thirty sets of interferograms (ten pairs of three spectral bands) is collected by the detector array at the output of the PIC. The optical path difference (OPD) of each interferometer baseline is kept to within 1 µm to maximize the visibility of the interference measurement. We constructed an experiment to utilize the two baselines for complex visibility measurement on a point source and a variable width slit. We used the point source to demonstrate near unity value of the PIC instrumental visibility, and used the variable slit to demonstrate visibility measurement for a simple extended object. The experimental result demonstrates the visibility of baseline 5 and 20 mm for a slit width of 0 to 500 µm in good agreement with theoretical predictions.

  10. Modularized construction of general integrated circuits on individual carbon nanotubes.

    Science.gov (United States)

    Pei, Tian; Zhang, Panpan; Zhang, Zhiyong; Qiu, Chenguang; Liang, Shibo; Yang, Yingjun; Wang, Sheng; Peng, Lian-Mao

    2014-06-11

    While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8-transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future.

  11. Integrated circuits and electrode interfaces for noninvasive physiological monitoring.

    Science.gov (United States)

    Ha, Sohmyung; Kim, Chul; Chi, Yu M; Akinin, Abraham; Maier, Christoph; Ueno, Akinori; Cauwenberghs, Gert

    2014-05-01

    This paper presents an overview of the fundamentals and state of the-art in noninvasive physiological monitoring instrumentation with a focus on electrode and optrode interfaces to the body, and micropower-integrated circuit design for unobtrusive wearable applications. Since the electrode/optrode-body interface is a performance limiting factor in noninvasive monitoring systems, practical interface configurations are offered for biopotential acquisition, electrode-tissue impedance measurement, and optical biosignal sensing. A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-the-art IAs. Furthermore, fundamental principles and state-of-the-art technologies for electrode-tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission. Examples are presented of practical dry-contact and noncontact cardiac, respiratory, muscle and brain monitoring systems, and their clinical applications.

  12. GaAs integrated circuits and heterojunction devices

    Science.gov (United States)

    Fowlis, Colin

    1986-06-01

    The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

  13. PETRIC - A positron emission tomography readout integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

    2000-11-05

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

  14. Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS

    Science.gov (United States)

    1996-01-01

    Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful

  15. Integrated reconfigurable high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2015-01-01

    In this paper a high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in scanners for medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The transmitting circuit is reconfigurable externally making it able...

  16. High-speed Integrated Circuits for electrical/Optical Interfaces

    DEFF Research Database (Denmark)

    Jespersen, Christoffer Felix

    2008-01-01

    of LC-oscillators with oscillator criteria, phase noise and different topologies are given as background. The theory of PLL circuits is also presented. Guidelines and suggestions for static divider, VCO, LA and CDR design are presented using static divider, 50-100 GHz VCO and 100Gb/s LA+CDR circuits......This thesis is a continuation of the effort to increase the bandwidth of communicationnetworks. The thesis presents the results of the design of several high-speed electrical ircuits for an electrical/optical interface. These circuits have been a contribution to the ESTA project in collaboration...... circuits at the receiver interface, though VCOs are also found in the transmitter where a multitude of independent sources have to be mutually synchronized before multiplexing. The circuits are based on an InP DHBT process (VIP-2) supplied by Vitesse and made publicly available as MPW. The VIP-2 process...

  17. Planar resonator and integrated oscillator using magnetostatic waves.

    Science.gov (United States)

    Kinoshita, Y; Kubota, S; Takeda, S; Nakagoshi, A

    1990-01-01

    A simple planar resonator using a magnetostatic wave (MSW) excited by aluminum finger electrodes with two bonding pads was realized on YIG/GGG (yttrium-iron-garnet film on a gadolinium-gallium-garnet crystal) substrate with two reflection edges. The tunable MSW resonator chip (2 mmx5 mm) exhibited a sharp notch filter response, as deep as 20-35 dB, and a high loaded Q up to 2000, which was tunable over the microwave frequency range from 2 to 4 GHz. A small tunable oscillator (8 cm(3)) was experimentally demonstrated using the MSW planar resonator and a silicon bipolar transistor integrated on a ceramic microwave circuit substrate. Microwave oscillation with spectral purity, at the same level as that of YIG sphere technology, was observed at 3 GHz. The experimental results indicate the technical areas where improvement must be made to realize a practical oscillator configuration.

  18. Using COMSOL Multiphysics Software to Model Anisotropic Dielectric and Metamaterial Effects in Folded-Waveguide Traveling-Wave Tube Slow-Wave Circuits

    Science.gov (United States)

    Starinshak, David P.; Smith, Nathan D.; Wilson, Jeffrey D.

    2008-01-01

    The electromagnetic effects of conventional dielectrics, anisotropic dielectrics, and metamaterials were modeled in a terahertz-frequency folded-waveguide slow-wave circuit. Results of attempts to utilize these materials to increase efficiency are presented.

  19. W-band Phased Array Systems using Silicon Integrated Circuits

    Science.gov (United States)

    Kim, Sang Young

    This thesis presents the silicon-based on-chip W-band phased array systems. An improved quadrature all-pass filter (QAF) and its implementation in 60--80 GHz active phase shifter using 0.13 microm SiGe BiCMOS technology is presented. It is demonstrated that with the inclusion of an Rs/R in the high Q branches of C and L, the sensitivity to the loading capacitance, therefore the I/Q phase and amplitude errors are minimized. This technique is especially suited for wideband millimeter-wave circuits where the loading capacitance (CL) is comparable to the filter capacitance (C). A prototype 60--80 GHz active phased shifter using the improved QAF is demonstrated. The overall chip size is 1.15 x 0.92 mm2 with the power consumption of 108 mW. The measured S11 and S22 are pass pi-network. The chip size is 0.45 x 0.3 mm2 without pads and consumes virtually no power. The measured S11 and S22 is 8 dBm and the simulated IIP3 is > 22 dBm. A low-power 76--84 GHz 4-element phased array receiver using the designed passive phase shifter is presented. The power consumption is minimized by using a single-ended design and alternating the amplifiers and phase shifter cells to result in a low noise figure at a low power consumption. A variable gain amplifier and the 11° phase shifter are used to correct for the rms gain and phase errors at different operating frequencies. The overall chip size is 2.0 x 2.7 mm2 with the current consumption of 18 mA/channel with 1.8 V supply voltage. The measured S11 and S 22 is circuits are designed differentially to result in less sensitivity to packaging effect and high channel-to-channel isolation. The overall chip size is 5.0 x 5.8 mm 2 with the power consumption of 500--600 mA from 2 V supply voltage. The measured S11 and S22 for all 16 phase states is 10 dB for 76.4--90 GHz with the rms gain error of -45 dB. The measured NF is 11.2--13 dB at 77--87 GHz at the maximum gain state. And the measured input P1dB is 20 dBm at 77 GHz and -25.8 dBm at the

  20. Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

    Science.gov (United States)

    Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

    2016-07-26

    A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

  1. Silicon-based photonic integrated circuit for label-free biosensing

    OpenAIRE

    Samusenko, Alina

    2016-01-01

    Silicon-based Photonic Integrated Circuit (PIC) is a device that integrates several optical components using the mature semiconductor technology platform, developed through years for the needs of electronic integrated circuits. In recent years, silicon PICs have been demonstrated as a powerful platform for biosensing systems - devices which play an omnipresent role in such essential life aspects as health care, environmental monitoring, food safety, etc. The growing importance of silicon phot...

  2. Laser Integration on Silicon Photonic Circuits Through Transfer Printing

    Science.gov (United States)

    2017-03-10

    for small- and medium-sized enterprises (SMEs) and universities , through multiproject wafer services such as Europractice and IME. The AIM...photonic circuits through transfer printing Grant number: FA9550-15-1-0460 PI: Gunther Roelkens Photonics Research Group, Ghent University -imec Period of...Circuit CMOS Complementary Metal Oxide Semiconductor SME small- and medium-sized enterprises DFB distributed feedback laser DISTRIBUTION A. Approved for public release: distribution unlimited.

  3. Miniaturized Ultrasound Imaging Probes Enabled by CMUT Arrays with Integrated Frontend Electronic Circuits

    Science.gov (United States)

    Khuri-Yakub, B. (Pierre) T.; Oralkan, Ömer; Nikoozadeh, Amin; Wygant, Ira O.; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N.; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O’Donnell, Matthew; Truong, Uyen; Sahn, David J.

    2010-01-01

    Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics. PMID:21097106

  4. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    Science.gov (United States)

    Heck, Martijn J. R.

    2017-01-01

    Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  5. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    Directory of Open Access Journals (Sweden)

    Heck Martijn J.R.

    2016-06-01

    Full Text Available Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  6. Aluminum heat sink enables power transistors to be mounted integrally with printed circuit board

    Science.gov (United States)

    Seaward, R. C.

    1967-01-01

    Power transistor is provided with an integral flat plate aluminum heat sink which mounts directly on a printed circuit board containing associated circuitry. Standoff spacers are used to attach the heat sink to the printed circuit board containing the remainder of the circuitry.

  7. A new monolithic integrated circuit for multiwire proportional chamber (MWPC) read-out system

    CERN Document Server

    Bareyre, P; Borel, J; Borgeaud, P; Brisson, J C; Merckel, G; Meunier, P; Ollivier, B; Poinsignon, J; Prunier, J

    1976-01-01

    A new monolithic 8-channel PMOS integrated circuit has been developed for an experiment to be carried out on the CERN 300 GeV accelerator. The circuit, read-out electronics and tests performed on 12 large MWPC (total of 48000 channels) are described and the results are presented. (3 refs).

  8. Ultra low-power integrated circuit design for wireless neural interfaces

    CERN Document Server

    Holleman, Jeremy; Otis, Brian

    2014-01-01

    Presenting results from real prototype systems, this volume provides an overview of ultra low-power integrated circuits and systems for neural signal processing and wireless communication. Topics include analog, radio, and signal processing theory and design for ultra low-power circuits.

  9. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  10. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Document Server

    Garcia-Sciveres, M; CERN. Geneva. The LHC experiments Committee; LHCC

    2013-01-01

    Letter of Intent for RD Collaboration Proposal focused on development of a next generation pixel readout integrated circuits needed for high luminosity LHC detector upgrades. Brings together ATLAS and CMS pixel chip design communities.

  11. A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

    Science.gov (United States)

    Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

    2008-02-01

    Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

  12. An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

    Science.gov (United States)

    Muyskens, Mark A.

    1997-01-01

    Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

  13. Waveguide Phase Modulator for Integrated Planar Lightwave Circuits in KTP Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This SBIR Phase II effort proposes the development and integration of a Planar Lightwave Circuit (PLC) into an all fiber-based seed laser system used in high...

  14. Localized In Situ Cladding Annealing for Post Fabrication Trimming of Silicon Photonic Integrated Circuits

    Science.gov (United States)

    2016-03-21

    In-Situ Cladding Annealing for Post-Fabrication Trimming of Silicon Photonic Integrated Circuits Steven Spector1, Jeffrey M. Knecht, and Paul W...calibration process rather than adjusting it continuously by applying power to a heater during operation of the circuit . When compared to other methods...is especially well suited to the low-cost integration of large numbers of optical components. One great challenge to fully realizing this potential

  15. Integrated-Circuit Controller For Brushless dc Motor

    Science.gov (United States)

    Le, Dong Tuan

    1994-01-01

    Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

  16. V-band low-noise integrated circuit receiver. [for space communication systems

    Science.gov (United States)

    Chang, K.; Louie, K.; Grote, A. J.; Tahim, R. S.; Mlinar, M. J.; Hayashibara, G. M.; Sun, C.

    1983-01-01

    A compact low-noise V-band integrated circuit receiver has been developed for space communication systems. The receiver accepts an RF input of 60-63 GHz and generates an IF output of 3-6 GHz. A Gunn oscillator at 57 GHz is phaselocked to a low-frequency reference source to achieve high stability and low FM noise. The receiver has an overall single sideband noise figure of less than 10.5 dB and an RF to IF gain of 40 dB over a 3-GHz RF bandwidth. All RF circuits are fabricated in integrated circuits on a Duroid substrate.

  17. Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

    Directory of Open Access Journals (Sweden)

    Yuharu Shinki

    2017-08-01

    Full Text Available This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

  18. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  19. Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Lun Li

    2006-04-01

    Full Text Available The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stages can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses upon a technique that integrates the best characteristics of both simulation and formal verification methods to provide an effective design validation tool, referred as Integrated Design Validation (IDV. The novelty in this approach consists of three components, circuit complexity analysis, partitioning based on design hierarchy, and coverage analysis. The circuit complexity analyzer and partitioning decompose a large design into sub-components and feed sub-components to different verification and/or simulation tools based upon known existing strengths of modern verification and simulation tools. The coverage analysis unit computes the coverage of design validation and improves the coverage by further partitioning. Various simulation and verification tools comprising IDV are evaluated and an example is used to illustrate the overall validation process. The overall process successfully validates the example to a high coverage rate within a short time. The experimental result shows that our approach is a very promising design validation method.

  20. High-voltage integrated transmitting circuit with differential driving for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz

    2016-01-01

    In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... is designed and implemented in AMS 0.35 μ m high-voltage process. Measurements are performed on the fabricated integrated circuit in order to assess its performance. The transmitting circuit consists of a low-voltage control logic, pulse-triggered level shifters and a differential output stage that generates...... conditions is 0.936 mW including the load. The integrated circuits measured prove to be consistent and robust to local process variations by measurements....

  1. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

    Science.gov (United States)

    Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

    2009-12-15

    Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

  2. Signal Digitizer and Cross-Correlation Application Specific Integrated Circuit

    Science.gov (United States)

    Baranauskas, Dalius (Inventor); Baranauskas, Gytis (Inventor); Zelenin, Denis (Inventor); Kangaslahti, Pekka (Inventor); Tanner, Alan B. (Inventor); Lim, Boon H. (Inventor)

    2017-01-01

    According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.

  3. Refinement and Pattern Formation in Neural Circuits by the Interaction of Traveling Waves with Spike-Timing Dependent Plasticity

    Science.gov (United States)

    Bennett, James E. M.; Bair, Wyeth

    2015-01-01

    Traveling waves in the developing brain are a prominent source of highly correlated spiking activity that may instruct the refinement of neural circuits. A candidate mechanism for mediating such refinement is spike-timing dependent plasticity (STDP), which translates correlated activity patterns into changes in synaptic strength. To assess the potential of these phenomena to build useful structure in developing neural circuits, we examined the interaction of wave activity with STDP rules in simple, biologically plausible models of spiking neurons. We derive an expression for the synaptic strength dynamics showing that, by mapping the time dependence of STDP into spatial interactions, traveling waves can build periodic synaptic connectivity patterns into feedforward circuits with a broad class of experimentally observed STDP rules. The spatial scale of the connectivity patterns increases with wave speed and STDP time constants. We verify these results with simulations and demonstrate their robustness to likely sources of noise. We show how this pattern formation ability, which is analogous to solutions of reaction-diffusion systems that have been widely applied to biological pattern formation, can be harnessed to instruct the refinement of postsynaptic receptive fields. Our results hold for rich, complex wave patterns in two dimensions and over several orders of magnitude in wave speeds and STDP time constants, and they provide predictions that can be tested under existing experimental paradigms. Our model generalizes across brain areas and STDP rules, allowing broad application to the ubiquitous occurrence of traveling waves and to wave-like activity patterns induced by moving stimuli. PMID:26308406

  4. Stochastic Simulation of Integrated Circuits with Nonlinear Black-Box Components via Augmented Deterministic Equivalents

    Directory of Open Access Journals (Sweden)

    MANFREDI, P.

    2014-11-01

    Full Text Available This paper extends recent literature results concerning the statistical simulation of circuits affected by random electrical parameters by means of the polynomial chaos framework. With respect to previous implementations, based on the generation and simulation of augmented and deterministic circuit equivalents, the modeling is extended to generic and ?black-box? multi-terminal nonlinear subcircuits describing complex devices, like those found in integrated circuits. Moreover, based on recently-published works in this field, a more effective approach to generate the deterministic circuit equivalents is implemented, thus yielding more compact and efficient models for nonlinear components. The approach is fully compatible with commercial (e.g., SPICE-type circuit simulators and is thoroughly validated through the statistical analysis of a realistic interconnect structure with a 16-bit memory chip. The accuracy and the comparison against previous approaches are also carefully established.

  5. Integrated circuits and logic operations based on single-layer MoS2.

    Science.gov (United States)

    Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

    2011-12-27

    Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

  6. Relationships among classes of self-oscillating transistor parallel inverters. [dc to square wave converter circuits for power conditioning

    Science.gov (United States)

    Wilson, T. G.; Lee, F. C. Y.; Burns, W. W., III; Owen, H. A., Jr.

    1974-01-01

    A procedure is developed for classifying dc-to-square-wave two-transistor parallel inverters used in power conditioning applications. The inverters are reduced to equivalent RLC networks and are then grouped with other inverters with the same basic equivalent circuit. Distinction between inverter classes is based on the topology characteristics of the equivalent circuits. Information about one class can then be extended to another class using the basic oscillation theory and the concept of duality. Oscillograms from test circuits confirm the validity of the procedure adopted.

  7. Rapid mapping of digital integrated circuit logic gates via multi-spectral backside imaging

    CERN Document Server

    Adato, Ronen; Zangeneh, Mahmoud; Zhou, Boyou; Joshi, Ajay; Goldberg, Bennett; Unlu, M Selim

    2016-01-01

    Modern semiconductor integrated circuits are increasingly fabricated at untrusted third party foundries. There now exist myriad security threats of malicious tampering at the hardware level and hence a clear and pressing need for new tools that enable rapid, robust and low-cost validation of circuit layouts. Optical backside imaging offers an attractive platform, but its limited resolution and throughput cannot cope with the nanoscale sizes of modern circuitry and the need to image over a large area. We propose and demonstrate a multi-spectral imaging approach to overcome these obstacles by identifying key circuit elements on the basis of their spectral response. This obviates the need to directly image the nanoscale components that define them, thereby relaxing resolution and spatial sampling requirements by 1 and 2 - 4 orders of magnitude respectively. Our results directly address critical security needs in the integrated circuit supply chain and highlight the potential of spectroscopic techniques to addres...

  8. Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

    Science.gov (United States)

    LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

    2014-06-02

    We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

  9. HBT and Schottky diode table-based nonlinear models for microwave integrated circuits design

    OpenAIRE

    Rodriguez Testera, Alejandro

    2012-01-01

    Accurate active device nonlinear models are key elements in the design of Microwave Integrated Circuits (MICs) with Circuit Aided Design (CAD) tools. There is a large diversity of nonlinear models proposals, each one with their own formulation and characteristics. The most popular ones are empirical, in the sense that model parameters are extracted from electrical measurements, and they could be classified in analytical/compact and black-box (both, table-based and behavioral). Analytical ...

  10. Local and nonlocal optically induced transparency effects in graphene-silicon hybrid nanophotonic integrated circuits.

    Science.gov (United States)

    Yu, Longhai; Zheng, Jiajiu; Xu, Yang; Dai, Daoxin; He, Sailing

    2014-11-25

    Graphene is well-known as a two-dimensional sheet of carbon atoms arrayed in a honeycomb structure. It has some unique and fascinating properties, which are useful for realizing many optoelectronic devices and applications, including transistors, photodetectors, solar cells, and modulators. To enhance light-graphene interactions and take advantage of its properties, a promising approach is to combine a graphene sheet with optical waveguides, such as silicon nanophotonic wires considered in this paper. Here we report local and nonlocal optically induced transparency (OIT) effects in graphene-silicon hybrid nanophotonic integrated circuits. A low-power, continuous-wave laser is used as the pump light, and the power required for producing the OIT effect is as low as ∼0.1 mW. The corresponding power density is several orders lower than that needed for the previously reported saturated absorption effect in graphene, which implies a mechanism involving light absorption by the silicon and photocarrier transport through the silicon-graphene junction. The present OIT effect enables low power, all-optical, broadband control and sensing, modulation and switching locally and nonlocally.

  11. An analog memory integrated circuit for waveform acquisition up to 900 MHz

    Science.gov (United States)

    Haller, G. M.; Wooley, B. A.

    1993-12-01

    The design and implementation of a switched-capacitor memory suitable for capturing high-speed analog waveforms is described. Highlights of the presented circuit are a 900 MHz sampling frequency (generated on chip), input signal independent cell pedestals and sampling instances, and cell gains that are insensitive to component sizes. A two-channel version of the memory with 32 cells for each channel has been integrated in a 2-micron complementary metal oxide semiconductor (CMOS) process with poly-to-poly capacitors. The measured rms cel pedestal variation in a channel after baseline subtraction is less than 0.3 mV across the full input signal range. The cell-to-cell gain matching is better than 0.01% rms, and the nonlinearity is less than 0.03% for a 2.5-V input range. The dynamic range of the memory exceeds 13 bits, and the peak signal-to-(noise+distortion) ratio for a 21.4 MHz sine wave sampled at 900 MHz is 59 dB.

  12. Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

    Science.gov (United States)

    Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

    2012-01-01

    Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

  13. Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

    Science.gov (United States)

    Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

    2012-10-21

    Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

  14. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

    Science.gov (United States)

    Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

    2008-07-24

    The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of

  15. Sensory integration in mouse insular cortex reflects GABA circuit maturation

    National Research Council Canada - National Science Library

    Gogolla, Nadine; Takesian, Anne E; Feng, Guoping; Fagiolini, Michela; Hensch, Takao K

    2014-01-01

    Insular cortex (IC) contributes to a variety of complex brain functions, such as communication, social behavior, and self-awareness through the integration of sensory, emotional, and cognitive content...

  16. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  17. Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits

    Science.gov (United States)

    Campbell, Ann. N.; Anderson, Richard E.; Cole, Jr., Edward I.

    1995-01-01

    A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits.

  18. An integrated energy-efficient capacitive sensor digital interface circuit

    KAUST Repository

    Omran, Hesham

    2014-06-19

    In this paper, we propose an energy-efficient 13-bit capacitive sensor interface circuit. The proposed design fully relies on successive approximation algorithm, which eliminates the need for oversampling and digital decimation filtering, and thus low-power consumption is achieved. The proposed architecture employs a charge amplifier stage to acheive parasitic insensitive operation and fine absolute resolution. Moreover, the output code is not affected by offset voltages or charge injection. The successive approximation algorithm is implemented in the capacitance-domain using a coarse-fine programmable capacitor array, which allows digitizing wide capacitance range in compact area. Analysis for the maximum achievable resolution due to mismatch is provided. The proposed design is insensitive to any reference voltage or current which translates to low temperature sensitivity. The operation of a prototype fabricated in a standard CMOS technology is experimentally verified using both on-chip and off-chip capacitive sensors. Compared to similar prior work, the fabricated prototype achieves and excellent energy efficiency of 34 pJ/step.

  19. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Science.gov (United States)

    Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

    2017-05-01

    Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  20. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  1. Traveling-wave-tube simulation: The IBC (Interactive Beam-Circuit) code

    Energy Technology Data Exchange (ETDEWEB)

    Morey, I.J.; Birdsall, C.K.

    1989-09-26

    Interactive Beam-Circuit (IBC) is a one-dimensional many particle simulation code which has been developed to run interactively on a PC or Workstation, and displaying most of the important physics of a traveling-wave-tube. The code is a substantial departure from previous efforts, since it follows all of the particles in the tube, rather than just those in one wavelength, as commonly done. This step allows for nonperiodic inputs in time, a nonuniform line and a large set of spatial diagnostics. The primary aim is to complement a microwave tube lecture course, although past experience has shown that such codes readily become research tools. Simple finite difference methods are used to model the fields of the coupled slow-wave transmission line. The coupling between the beam and the transmission line is based upon the finite difference equations of Brillouin. The space-charge effects are included, in a manner similar to that used by Hess; the original part is use of particle-in-cell techniques to model the space-charge fields. 11 refs., 11 figs.

  2. Quantum dash based single section mode locked lasers for photonic integrated circuits.

    Science.gov (United States)

    Joshi, Siddharth; Calò, Cosimo; Chimot, Nicolas; Radziunas, Mindaugas; Arkhipov, Rostislav; Barbet, Sophie; Accard, Alain; Ramdane, Abderrahim; Lelarge, Francois

    2014-05-05

    We present the first demonstration of an InAs/InP Quantum Dash based single-section frequency comb generator designed for use in photonic integrated circuits (PICs). The laser cavity is closed using a specifically designed Bragg reflector without compromising the mode-locking performance of the self pulsating laser. This enables the integration of single-section mode-locked laser in photonic integrated circuits as on-chip frequency comb generators. We also investigate the relations between cavity modes in such a device and demonstrate how the dispersion of the complex mode frequencies induced by the Bragg grating implies a violation of the equi-distance between the adjacent mode frequencies and, therefore, forbids the locking of the modes in a classical Bragg Device. Finally we integrate such a Bragg Mirror based laser with Semiconductor Optical Amplifier (SOA) to demonstrate the monolithic integration of QDash based low phase noise sources in PICs.

  3. Integrative Strategy for Effective Teaching of Alternating Circuits in ...

    African Journals Online (AJOL)

    One of the reasons advanced for the low enrolment and achievement of students in Physics at both secondary and post-secondary schools is poor teaching strategies used by teachers of Physics particularly in teaching Physics concepts classified by students as being difficult. In this paper, integrative strategy for effective ...

  4. Matlab/Simulink Implementation of Wave-based Models for Microstrip Structures utilizing Short-circuited and Opened Stubs

    Directory of Open Access Journals (Sweden)

    Biljana P. Stošić

    2011-12-01

    Full Text Available This paper describes modeling and analyzing procedures for microstrip filters based on use of one-dimensional wave digital approach. Different filter structures are observed. One filter is based on quarter-wave length short-circuited stubs and connecting transmission lines. The other one is based on cross-junction opened stubs. Frequency responses are obtained by direct analysis of the block-based networks formed in Simulink toolbox of MATLAB environment. This wave-based method allows an accurate and efficient analysis of different microwave structures.

  5. Restoring heart function and electrical integrity: closing the circuit

    Science.gov (United States)

    Monteiro, Luís Miguel; Vasques-Nóvoa, Francisco; Ferreira, Lino; Pinto-do-Ó, Perpétua; Nascimento, Diana Santos

    2017-04-01

    Cardiovascular diseases are the main cause of death in the world and are often associated with the occurrence of arrhythmias due to disruption of myocardial electrical integrity. Pathologies involving dysfunction of the specialized cardiac excitatory/conductive tissue are also common and constitute an added source of morbidity and mortality since current standard therapies withstand a great number of limitations. As electrical integrity is essential for a well-functioning heart, innovative strategies have been bioengineered to improve heart conduction and/or promote myocardial repair, based on: (1) gene and/or cell delivery; or (2) conductive biomaterials as tools for cardiac tissue engineering. Herein we aim to review the state-of-art in the area, while briefly describing the biological principles underlying the heart electrical/conduction system and how this system can be disrupted in heart disease. Suggestions regarding targets for future studies are also presented.

  6. Harmonic analysis approach to the 'TunneLadder' - A modified Karp circuit for millimeter-wave TWTA's

    Science.gov (United States)

    Kosmahl, H. G.; Palmer, R. W.

    1982-05-01

    A field approach to the summed harmonic analysis of the TunneLadder structure, or modified forward-wave Karp circuit, is developed by combining TM(01) and TE(11) modes. Results suggest the suitability of this structure as a high-impedance, about 1-% bandwidth circuit, millimeter-wave forward-wave-type amplifier that is voltage tunable over about a 5-% frequency range and has excellent power handling ability. Theory gives good agreement with experimental results obtained by Karp in omega-beta dispersion and predicts qualitatively the appearances of the antisymmetric mode discussed and of the so called Hightron mode that was discussed earlier in White, Enderby and Birdsall (1964), and Enderby (1964), in addition to the desired symmetric mode.

  7. Harmonic analysis approach to the 'TunneLadder' - A modified Karp circuit for millimeter-wave TWTA's

    Science.gov (United States)

    Kosmahl, H. G.; Palmer, R. W.

    1982-01-01

    A field approach to the summed harmonic analysis of the TunneLadder structure, or modified forward-wave Karp circuit, is developed by combining TM(01) and TE(11) modes. Results suggest the suitability of this structure as a high-impedance, about 1-% bandwidth circuit, millimeter-wave forward-wave-type amplifier that is voltage tunable over about a 5-% frequency range and has excellent power handling ability. Theory gives good agreement with experimental results obtained by Karp in omega-beta dispersion and predicts qualitatively the appearances of the antisymmetric mode discussed and of the so called Hightron mode that was discussed earlier in White, Enderby and Birdsall (1964), and Enderby (1964), in addition to the desired symmetric mode.

  8. An adaptive metamaterial beam with hybrid shunting circuits for extremely broadband control of flexural wave (Conference Presentation)

    Science.gov (United States)

    Chen, Yangyang; Huang, Guoliang

    2017-04-01

    A great deal of research has been devoted to controlling the dynamic behaviors of phononic crystals and metamaterials by directly tuning the frequency regions and/or widths of their inherent band gaps. Here, we present a novel approach to achieve extremely broadband flexural wave/vibration attenuation based on tunable local resonators made of piezoelectric stacks shunted by hybrid negative capacitance and negative inductance circuits with proof masses attached on a host beam. First, wave dispersion relations of the adaptive metamaterial beam are calculated analytically by using the transfer matrix method. The unique modulus tuning properties induced by the hybrid shunting circuits are then characterized conceptually, from which the frequency dependent modulus tuning curves of the piezoelectric stack located within wave attenuation frequency regions are quantitatively identified. As an example, a flexural wave high-pass band filter with a wave attenuation region from 0 to 23.0 kHz is demonstrated analytically and numerically by using the hybrid shunting circuit, in which the two electric components are connected in series. By changing the connection pattern to be parallel, another super wide wave attenuation region from 13.5 to 73.0 kHz is demonstrated to function as a low-pass filter at a subwavelength scale. The proposed adaptive metamaterial possesses a super wide band gap created both naturally and artificially. Therefore, it can be used for the transient wave mitigation at extremely broadband frequencies such as blast or impact loadings. We envision that the proposed design and approach can open many possibilities in broadband vibration and wave control.

  9. The Hybrid Integrated Circuit of the ALICE Inner Tracking System upgrade

    CERN Document Server

    Fiorenza, G; Pastore, C; Valentino, V

    2016-01-01

    The upgrade of the Inner Tracking System scheduled during the second long shutdown is an important milestone of the ALICE upgrade and it will provide a high improvement of its performances. In this contribution the smallest operator unit of the detector, the Hybrid Integrated Circuits, is presented.

  10. The impact of very high performance integrated circuits on avionics system readiness

    Science.gov (United States)

    Strull, G.

    1985-08-01

    Very high performance integrated circuits (VHPIC) represent more than an integrated circuit technology advance- VHPIC really represents a new systems/technology culture. With a philosophy of top-down design and bottom-up build, a vehicle is provided to avoid rapid obsolescence so prevalent in the fast moving integrated circuit industry. However, to successfully and effectively design advanced systems in this manner, a design methodology is required that adequately addresses the challenge. Since everything from chip definition through application analysis is interactive with everything else, the challenge is to adequately keep track of all the perimeters and their relationship. The methodology by which design and analysis are accomplished is discussed. The starting point is the systems architecture and its application software. From the architecture and application software the partitioning of the system into appropriate modules can be derived. From this an idea of the integrated circuits needed can be determined. The elements of system readiness are described. They are design, implementation, insertion, maintenance, and (Preplanned Product Improvement).

  11. Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

    Science.gov (United States)

    Aziz, Syed Mahfuzul; Sicard, Etienne; Ben Dhia, Sonia

    2010-01-01

    This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied…

  12. 77 FR 67833 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission...

    Science.gov (United States)

    2012-11-14

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission Determination Not To Review an Initial Determination Terminating the Investigation in its Entirety AGENCY: U.S...

  13. Wideband Monolithic Microwave Integrated Circuit Frequency Converters with GaAs mHEMT Technology

    DEFF Research Database (Denmark)

    Krozer, Viktor; Johansen, Tom Keinicke; Djurhuus, Torsten

    2005-01-01

    We present monolithic microwave integrated circuit (MMIC) frequency converter, which can be used for up and down conversion, due to the large RF and IF port bandwidth. The MMIC converters are based on commercially available GaAs mHEMT technology and are comprised of a Gilbert mixer cell core...

  14. 77 FR 40381 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice...

    Science.gov (United States)

    2012-07-09

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice... conditions in the U.S. economy or U.S. consumers. No petitions for review were received.The Commission has...

  15. SPICE Modeling of Body Bias Effect in 4H-SiC Integrated Circuit Resistors

    Science.gov (United States)

    Neudeck, Philip G.

    2017-01-01

    The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

  16. Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6

    NARCIS (Netherlands)

    Roozeboom, F.; Narayanan, V.; Kakushima, K.; Timans, P.J.; Gusev, E.P.; Karim, Z.; Gendt, S. De

    2016-01-01

    The topics of this annual symposium continue to describe the evolution of traditional scaling in CMOS integrated circuit manufacturing (More Moore for short), combined with the opportunities from growing diversification and embedded functionality (More than Moore). Once again, the main objective was

  17. A METHOD AND AN APPARATUS FOR PROVIDING TIMING SIGNALS TO A NUMBER OF CIRCUITS, AN INTEGRATED CIRCUIT AND A NODE

    DEFF Research Database (Denmark)

    2006-01-01

    A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing...... signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier....

  18. Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability.

    Science.gov (United States)

    Lu, Zeqin; Jhoja, Jaspreet; Klein, Jackson; Wang, Xu; Liu, Amy; Flueckiger, Jonas; Pond, James; Chrostowski, Lukas

    2017-05-01

    This work develops an enhanced Monte Carlo (MC) simulation methodology to predict the impacts of layout-dependent correlated manufacturing variations on the performance of photonics integrated circuits (PICs). First, to enable such performance prediction, we demonstrate a simple method with sub-nanometer accuracy to characterize photonics manufacturing variations, where the width and height for a fabricated waveguide can be extracted from the spectral response of a racetrack resonator. By measuring the spectral responses for a large number of identical resonators spread over a wafer, statistical results for the variations of waveguide width and height can be obtained. Second, we develop models for the layout-dependent enhanced MC simulation. Our models use netlist extraction to transfer physical layouts into circuit simulators. Spatially correlated physical variations across the PICs are simulated on a discrete grid and are mapped to each circuit component, so that the performance for each component can be updated according to its obtained variations, and therefore, circuit simulations take the correlated variations between components into account. The simulation flow and theoretical models for our layout-dependent enhanced MC simulation are detailed in this paper. As examples, several ring-resonator filter circuits are studied using the developed enhanced MC simulation, and statistical results from the simulations can predict both common-mode and differential-mode variations of the circuit performance.

  19. On-chip synthesis of circularly polarized emission of light with integrated photonic circuits.

    Science.gov (United States)

    He, Li; Li, Mo

    2014-05-01

    The helicity of circularly polarized (CP) light plays an important role in the light-matter interaction in magnetic and quantum material systems. Exploiting CP light in integrated photonic circuits could lead to on-chip integration of novel optical helicity-dependent devices for applications ranging from spintronics to quantum optics. In this Letter, we demonstrate a silicon photonic circuit coupled with a 2D grating emitter operating at a telecom wavelength to synthesize vertically emitting, CP light from a quasi-TE waveguide mode. Handedness of the emitted circular polarized light can be thermally controlled with an integrated microheater. The compact device footprint enables a small beam diameter, which is desirable for large-scale integration.

  20. CMOS-based carbon nanotube pass-transistor logic integrated circuits

    Science.gov (United States)

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-01-01

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

  1. Analog Integrated Circuit Design for Spike Time Dependent Encoder and Reservoir in Reservoir Computing Processors

    Science.gov (United States)

    2018-01-01

    ORGANIZATION NAME(S) AND ADDRESS(ES) University of Kansas Center for Research, Inc. 2385 Irving Hill Rd Lawrence KS 66045-7552 8. PERFORMING... ORGANIZATION REPORT NUMBER 9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) Air Force Research Laboratory/RITB 525 Brooks Road Rome NY 13441-4505 10...multidisciplinary effort encompassed high-performance computing, nanotechnology, integrated circuits, and integrated systems. The project’s architecture was

  2. Power Management Integrated Circuit for Indoor Photovoltaic Energy Harvesting System

    Science.gov (United States)

    Jain, Vipul

    In today's world, power dissipation is a main concern for battery operated mobile devices. Key design decisions are being governed by power rather than area/delay because power requirements are growing more stringent every year. Hence, a hybrid power management system is proposed, which uses both a solar panel to harvest energy from indoor lighting and a battery to power the load. The system tracks the maximum power point of the solar panel and regulates the battery and microcontroller output load voltages through the use of an on-chip switched-capacitor DC-DC converter. System performance is verified through simulation at the 180nm technology node and is made to be integrated on-chip with 0.25 second startup time, 79% efficiency, --8/+14% ripple on the load, an average 1micro A of quiescent current (3.7micro W of power) and total on-chip area of 1.8mm2 .

  3. Scattering of surface waves modelled by the integral equation method

    Science.gov (United States)

    Lu, Laiyu; Maupin, Valerie; Zeng, Rongsheng; Ding, Zhifeng

    2008-09-01

    The integral equation method is used to model the propagation of surface waves in 3-D structures. The wavefield is represented by the Fredholm integral equation, and the scattered surface waves are calculated by solving the integral equation numerically. The integration of the Green's function elements is given analytically by treating the singularity of the Hankel function at R = 0, based on the proper expression of the Green's function and the addition theorem of the Hankel function. No far-field and Born approximation is made. We investigate the scattering of surface waves propagating in layered reference models imbedding a heterogeneity with different density, as well as Lamé constant contrasts, both in frequency and time domains, for incident plane waves and point sources.

  4. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    Science.gov (United States)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  5. SEMICONDUCTOR DEVICES: A novel high voltage start up circuit for an integrated switched mode power supply

    Science.gov (United States)

    Hao, Hu; Xingbi, Chen

    2010-09-01

    A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions.

  6. A thermal protection module for automotive integrated circuits

    Science.gov (United States)

    Han, Yifeng; Zhai, Mingjing; Zhou, Junfeng

    2017-07-01

    Automotive ICs work in wide ambient temperature range up to 150∘C. It is important to design an over temperature protection mechanism for the reliability of ICs and systems. A thermal protection module for the automotive ICs is reported in this paper. Dual channel detection and decision scheme was designed based on band gap voltage reference. Precision thermal protection point was set by serial resistors and the variations of power supply, temperature and the process were removed by the resistor ratio. The thermal protection module was implemented in CSMC 0.5 μm 60 V BCD process, incorporated in a CAN transceiver chip. The area of the module was about 0.02 mm2 and thus it was very compact and low cost to integrate in chips. The performance of the thermal protection parameters was measured in incubators. The thermal shutdown temperature was about 164.4∘C and the thermal recovery temperature was about 153∘C with hysteresis temperature of 10 K. Additionally, the thermal protection module showed good consistency with different chips.

  7. Impact-Based Area Allocation for Yield Optimization in Integrated Circuits

    Science.gov (United States)

    Abraham, Billion; Widodo, Arif; Chen, Poki

    2016-06-01

    In analog integrated circuit (IC) layout, area allocation is a very important issue for achieving good mismatch cancellation. However, most IC layout papers focus only on layout strategy to reduce systematic mismatch. In 2006, an outstanding paper presenting area allocation strategy was published to introduce technique for random mismatch reduction. Instead of using general theoretical study to prove the strategy, this research presented close-to-optimum simulations only on case-bycase basis. The impact-based area allocation for yield optimization in integrated circuits is proposed in this chapter. To demonstrate the corresponding strategy, not only a theoretical analysis but also an integral nonlinearity-based yield simulation will be given to derive optimum area allocation for binary weighted current steering digital-to-analog converter (DAC). The result will be concluded to convince IC designers how to allocate area for critical devices in an optimum way.

  8. Deterministic Integration of Single Photon Sources in Silicon Based Photonic Circuits.

    Science.gov (United States)

    Zadeh, Iman Esmaeil; Elshaari, Ali W; Jöns, Klaus D; Fognini, Andreas; Dalacu, Dan; Poole, Philip J; Reimer, Michael E; Zwiller, Val

    2016-04-13

    A major step toward fully integrated quantum optics is the deterministic incorporation of high quality single photon sources in on-chip optical circuits. We show a novel hybrid approach in which preselected III-V single quantum dots in nanowires are transferred and integrated in silicon based photonic circuits. The quantum emitters maintain their high optical quality after integration as verified by measuring a low multiphoton probability of 0.07 ± 0.07 and emission line width as narrow as 3.45 ± 0.48 GHz. Our approach allows for optimum alignment of the quantum dot light emission to the fundamental waveguide mode resulting in very high coupling efficiencies. We estimate a coupling efficiency of 24.3 ± 1.7% from the studied single-photon source to the photonic channel and further show by finite-difference time-domain simulations that for an optimized choice of material and design the efficiency can exceed 90%.

  9. CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

    Science.gov (United States)

    Domingues, Suzana; Perenzoni, Daniele; Perenzoni, Matteo; Stoppa, David

    2017-06-01

    In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm2 and 36 μW).

  10. Fiber-Coupled Planar Light-Wave Circuit for Seed Laser Control in High Spectral Resolution Lidar Systems

    Science.gov (United States)

    Cook, Anthony; McNeil, Shirley; Switzer, Gregg; Battle, Philip

    2010-01-01

    Precise laser remote sensing of aerosol extinction and backscatter in the atmosphere requires a high-power, pulsed, frequency doubled Nd:YAG laser that is wavelength- stabilized to a narrow absorption line such as found in iodine vapor. One method for precise wavelength control is to injection seed the Nd:YAG laser with a low-power CW laser that is stabilized by frequency converting a fraction of the beam to 532 nm, and to actively frequency-lock it to an iodine vapor absorption line. While the feasibility of this approach has been demonstrated using bulk optics in NASA Langley s Airborne High Spectral Resolution Lidar (HSRL) program, an ideal, lower cost solution is to develop an all-waveguide, frequency-locked seed laser in a compact, robust package that will withstand the temperature, shock, and vibration levels associated with airborne and space-based remote sensing platforms. A key technology leading to this miniaturization is the integration of an efficient waveguide frequency doubling element, and a low-voltage phase modulation element into a single, monolithic, planar light-wave circuit (PLC). The PLC concept advances NASA's future lidar systems due to its compact, efficient and reliable design, thus enabling use on small aircraft and satellites. The immediate application for this technology is targeted for NASA Langley's HSRL system for aerosol and cloud characterization. This Phase I effort proposes the development of a potassium titanyl phosphate (KTP) waveguide phase modulator for future integration into a PLC. For this innovation, the proposed device is the integration of a waveguide-based frequency doubler and phase modulator in a single, fiber pigtail device that will be capable of efficient second harmonic generation of 1,064-nm light and subsequent phase modulation of the 532 nm light at 250 MHz, providing a properly spectrally formatted beam for HSRL s seed laser locking system. Fabrication of the integrated PLC chip for NASA Langley, planned for

  11. Multicomponent integrable wave equations: II. Soliton solutions

    Energy Technology Data Exchange (ETDEWEB)

    Degasperis, A [Dipartimento di Fisica, Universita di Roma ' La Sapienza' , and Istituto Nazionale di Fisica Nucleare, Sezione di Roma, Rome (Italy); Lombardo, S [School of Mathematics, University of Manchester, Alan Turing Building, Upper Brook Street, Manchester M13 9EP (United Kingdom)], E-mail: antonio.degasperis@roma1.infn.it, E-mail: sara.lombardo@manchester.ac.uk, E-mail: sara@few.vu.nl

    2009-09-25

    The Darboux-dressing transformations developed in Degasperis and Lombardo (2007 J. Phys. A: Math. Theor. 40 961-77) are here applied to construct soliton solutions for a class of boomeronic-type equations. The vacuum (i.e. vanishing) solution and the generic plane wave solution are both dressed to yield one-soliton solutions. The formulae are specialized to the particularly interesting case of the resonant interaction of three waves, a well-known model which is of boomeronic type. For this equation a novel solution which describes three locked dark pulses (simulton) is introduced.

  12. Integration of Wave Power in Hadai Gwaii

    NARCIS (Netherlands)

    Boronowski, S.; Rowe, A.; Wild, Peter

    2010-01-01

    Remote communities, such as Haida Gwaii, Canada, often have high energy costs due to their dependence on diesel fuel for generation. Haida Gwaii's lengthy coastline, exposed to the northeast Pacific Ocean, provides opportunities for capturing wave energy to potentially reduce energy costs. A mixed

  13. Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

    Science.gov (United States)

    Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

    2016-08-10

    Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

  14. Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

    Science.gov (United States)

    McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

    2017-03-28

    Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

  15. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  16. Superluminal pulse propagation and amplification without inversion of microwave radiation via four-wave mixing in superconducting phase quantum circuits

    Science.gov (United States)

    Amini Sabegh, Z.; Vafafard, A.; Maleki, M. A.; Mahmoudi, M.

    2015-08-01

    We study the interaction of the microwave fields with an array of superconducting phase quantum circuits. It is shown that the different four-level configurations i.e. cascade, N-type, diamond, Y-type and inverted Y-type systems can be obtained in the superconducting phase quantum circuits by keeping the third order of the Josephson junction potential expansion whereas by dropping the third order term, just the cascade configuration can be established. We study the propagation and amplification of a microwave field in a four-level cascade quantum system, which is realized in an array of superconducting phase quantum circuits. We find that by increasing the microwave pump tones feeding the system, the normal dispersion switches to the anomalous and the gain-assisted superluminal microwave propagation is obtained in an array of many superconducting phase quantum circuits. Moreover, it is demonstrated that the stimulated microwave field is generated via four-wave mixing without any inversion population in the energy levels of the system (amplification without inversion) and the group velocity of the generated pulse can be controlled by the external oscillating magnetic fluxes. We also show that in some special set of parameters, the absorption-free superluminal generated microwave propagation is obtained in superconducting phase quantum circuit system.

  17. Common-signal-induced synchronization in photonic integrated circuits and its application to secure key distribution.

    Science.gov (United States)

    Sasaki, Takuma; Kakesu, Izumi; Mitsui, Yusuke; Rontani, Damien; Uchida, Atsushi; Sunada, Satoshi; Yoshimura, Kazuyuki; Inubushi, Masanobu

    2017-10-16

    We experimentally achieve common-signal-induced synchronization in two photonic integrated circuits with short external cavities driven by a constant-amplitude random-phase light. The degree of synchronization can be controlled by changing the optical feedback phase of the two photonic integrated circuits. The change in the optical feedback phase leads to a significant redistribution of the spectral energy of optical and RF spectra, which is a unique characteristic of PICs with the short external cavity. The matching of the RF and optical spectra is necessary to achieve synchronization between the two PICs, and stable synchronization can be obtained over an hour in the presence of optical feedback. We succeed in generating information-theoretic secure keys and achieving the final key generation rate of 184 kb/s using the PICs.

  18. Fully Printed Stretchable Thin-Film Transistors and Integrated Logic Circuits.

    Science.gov (United States)

    Cai, Le; Zhang, Suoming; Miao, Jinshui; Yu, Zhibin; Wang, Chuan

    2016-12-27

    This paper reports intrinsically stretchable thin-film transistors (TFTs) and integrated logic circuits directly printed on elastomeric polydimethylsiloxane (PDMS) substrates. The printed devices utilize carbon nanotubes and a type of hybrid gate dielectric comprising PDMS and barium titanate (BaTiO3) nanoparticles. The BaTiO3/PDMS composite simultaneously provides high dielectric constant, superior stretchability, low leakage, as well as good printability and compatibility with the elastomeric substrate. Both TFTs and logic circuits can be stretched beyond 50% strain along either channel length or channel width directions for thousands of cycles while showing no significant degradation in electrical performance. This work may offer an entry into more sophisticated stretchable electronic systems with monolithically integrated sensors, actuators, and displays, fabricated by scalable and low-cost methods for real life applications.

  19. Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

    Science.gov (United States)

    Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

    2016-09-19

    Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

  20. Experimental and theoretical analysis of integrated circuit (IC) chips on flexible substrates subjected to bending

    Science.gov (United States)

    Chen, Ying; Yuan, Jianghong; Zhang, Yingchao; Huang, Yonggang; Feng, Xue

    2017-10-01

    The interfacial failure of integrated circuit (IC) chips integrated on flexible substrates under bending deformation has been studied theoretically and experimentally. A compressive buckling test is used to impose the bending deformation onto the interface between the IC chip and the flexible substrate quantitatively, after which the failed interface is investigated using scanning electron microscopy. A theoretical model is established based on the beam theory and a bi-layer interface model, from which an analytical expression of the critical curvature in relation to the interfacial failure is obtained. The relationships between the critical curvature, the material, and the geometric parameters of the device are discussed in detail, providing guidance for future optimization flexible circuits based on IC chips.

  1. High-dimensional quantum key distribution based on multicore fiber using silicon photonic integrated circuits

    DEFF Research Database (Denmark)

    Ding, Yunhong; Bacco, Davide; Dalgaard, Kjeld

    2017-01-01

    -dimensional quantum states, and enables breaking the information efficiency limit of traditional quantum key distribution protocols. In addition, the silicon photonic circuits used in our work integrate variable optical attenuators, highly efficient multicore fiber couplers, and Mach-Zehnder interferometers, enabling......Quantum key distribution provides an efficient means to exchange information in an unconditionally secure way. Historically, quantum key distribution protocols have been based on binary signal formats, such as two polarization states, and the transmitted information efficiency of the quantum key...... is intrinsically limited to 1 bit/photon. Here we propose and experimentally demonstrate, for the first time, a high-dimensional quantum key distribution protocol based on space division multiplexing in multicore fiber using silicon photonic integrated lightwave circuits. We successfully realized three mutually...

  2. Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

    KAUST Repository

    Hanna, Amir

    2015-12-04

    High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

  3. Design and characterization of integrated components for SiN photonic quantum circuits.

    Science.gov (United States)

    Poot, Menno; Schuck, Carsten; Ma, Xiao-Song; Guo, Xiang; Tang, Hong X

    2016-04-04

    The design, fabrication, and detailed calibration of essential building blocks towards fully integrated linear-optics quantum computation are discussed. Photonic devices are made from silicon nitride rib waveguides, where measurements on ring resonators show small propagation losses. Directional couplers are designed to be insensitive to fabrication variations. Their offset and coupling lengths are measured, as well as the phase difference between the transmitted and reflected light. With careful calibrations, the insertion loss of the directional couplers is found to be small. Finally, an integrated controlled-NOT circuit is characterized by measuring the transmission through different combinations of inputs and outputs. The gate fidelity for the CNOT operation with this circuit is estimated to be 99.81% after post selection. This high fidelity is due to our robust design, good fabrication reproducibility, and extensive characterizations.

  4. Advanced field-solver techniques for RC extraction of integrated circuits

    CERN Document Server

    Yu, Wenjian

    2014-01-01

    Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering, as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of ...

  5. Single Molecule Detection Using a Silicon Nanopore-Nanotransistor Integrated Circuit

    Science.gov (United States)

    2006-01-01

    CONTRACT NUMBER Single Molecule Detection Using a Silicon Nanopore-Nanotransistor Integrated Circuit 5b.GRANTNUMBER FA9550-04-1-0214 5c. PROGRAMWELEMENT...electrolyte, and the small pore volume (-20nm 3), D (200mV) we suppose that each of these electrical (i) signatures is indicative of a single molecule 60...polynucleotide. Most of the experimental work using a nanopore W - as a transducer for single molecule detection uses electronics D - K borrowed from

  6. High figure-of-merit SOI power LDMOS for power integrated circuits

    OpenAIRE

    Singh, Yashvir; Rawat, Rahul Singh

    2015-01-01

    The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS) are carried out to improve the breakdown voltage, on-resistance, gate-charge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two sepa...

  7. Proposal for combined conducted and radiated emission modelling for Integrated Circuit

    OpenAIRE

    Serpaud, Sébastien; Ghfiri, C.; Boyer, Alexandre; Durier, A

    2017-01-01

    International audience; This paper describes a methodology to build a combined conducted and radiated emission model for integrated circuits. The development of emission models of a FPGA extracted from two different approaches is presented and discussed. The first approach allows to build a predictable model from FPGA implementation and some passive measurement on FPGA device. The second approach allows to build a model from only the near field measurement. In conclusion, the accuracy of both...

  8. Towards synthetic gene circuits with enhancers: biology's multi-input integrators.

    Science.gov (United States)

    Amit, Roee

    2012-01-01

    One of the greatest challenges facing synthetic biology is to develop a technology that allows gene regulatory circuits in microbes to integrate multiple inputs or stimuli using a small DNA sequence "foot-print", and which will generate precise and reproducible outcomes. Achieving this goal is hindered by the routine utilization of the commonplace σ(70) promoters in gene-regulatory circuits. These promoters typically are not capable of integrating binding of more than two or three transcription factors in natural examples, which has limited the field to developing integrated circuits made of two-input biological "logic" gates. In natural examples the regulatory elements, which integrate multiple inputs are called enhancers. These regulatory elements are ubiquitous in all organisms in the tree of life, and interestingly metazoan and bacterial enhancers are significantly more similar in terms of both Transcription Factor binding site arrangement and biological function than previously thought. These similarities imply that there may be underlying enhancer design principles or grammar rules by which one can engineer novel gene regulatory circuits. However, at present our current understanding of enhancer structure-function relationship in all organisms is limited, thus preventing us from using these objects routinely in synthetic biology application. In order to alleviate this problem, in this book chapter, I will review our current view of bacterial enhancers, allowing us to first highlight the potential of enhancers to be a game-changing tool in synthetic biology application, and subsequently to draw a road-map for developing the necessary quantitative understanding to reach this goal.

  9. Integrated genomic and gene expression profiling identifies two major genomic circuits in urothelial carcinoma.

    Directory of Open Access Journals (Sweden)

    David Lindgren

    Full Text Available Similar to other malignancies, urothelial carcinoma (UC is characterized by specific recurrent chromosomal aberrations and gene mutations. However, the interconnection between specific genomic alterations, and how patterns of chromosomal alterations adhere to different molecular subgroups of UC, is less clear. We applied tiling resolution array CGH to 146 cases of UC and identified a number of regions harboring recurrent focal genomic amplifications and deletions. Several potential oncogenes were included in the amplified regions, including known oncogenes like E2F3, CCND1, and CCNE1, as well as new candidate genes, such as SETDB1 (1q21, and BCL2L1 (20q11. We next combined genome profiling with global gene expression, gene mutation, and protein expression data and identified two major genomic circuits operating in urothelial carcinoma. The first circuit was characterized by FGFR3 alterations, overexpression of CCND1, and 9q and CDKN2A deletions. The second circuit was defined by E3F3 amplifications and RB1 deletions, as well as gains of 5p, deletions at PTEN and 2q36, 16q, 20q, and elevated CDKN2A levels. TP53/MDM2 alterations were common for advanced tumors within the two circuits. Our data also suggest a possible RAS/RAF circuit. The tumors with worst prognosis showed a gene expression profile that indicated a keratinized phenotype. Taken together, our integrative approach revealed at least two separate networks of genomic alterations linked to the molecular diversity seen in UC, and that these circuits may reflect distinct pathways of tumor development.

  10. Integrated cascade of photovoltaic cells as a power supply for integrated circuits

    NARCIS (Netherlands)

    Mouthaan, A.J.

    1984-01-01

    ICs can be powered directly when a supply voltage source capable of generating a multiple of the open circuit voltage of one pn-junction is available on a chip. Two schemes have been investigated for cascading photovoltaic cells on the chip. The structures can be made compatible with standard

  11. Dielectric Spectroscopic Detection of Early Failures in 3-D Integrated Circuits.

    Science.gov (United States)

    Obeng, Yaw; Okoro, C A; Ahn, Jung-Joon; You, Lin; Kopanski, Joseph J

    The commercial introduction of three dimensional integrated circuits (3D-ICs) has been hindered by reliability challenges, such as stress related failures, resistivity changes, and unexplained early failures. In this paper, we discuss a new RF-based metrology, based on dielectric spectroscopy, for detecting and characterizing electrically active defects in fully integrated 3D devices. These defects are traceable to the chemistry of the insolation dielectrics used in the through silicon via (TSV) construction. We show that these defects may be responsible for some of the unexplained early reliability failures observed in TSV enabled 3D devices.

  12. A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

    Directory of Open Access Journals (Sweden)

    Daniel Pacheco Bautista

    2007-09-01

    Full Text Available The clock recovery circuit (CRC plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC wor-king at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL, current mode logic (MCML and a novel two stage ring-based voltage controlled oscillator (VCO. The design used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

  13. System Modeling of a MEMS Vibratory Gyroscope and Integration to Circuit Simulation.

    Science.gov (United States)

    Kwon, Hyukjin J; Seok, Seyeong; Lim, Geunbae

    2017-11-18

    Recently, consumer applications have dramatically created the demand for low-cost and compact gyroscopes. Therefore, on the basis of microelectromechanical systems (MEMS) technology, many gyroscopes have been developed and successfully commercialized. A MEMS gyroscope consists of a MEMS device and an electrical circuit for self-oscillation and angular-rate detection. Since the MEMS device and circuit are interactively related, the entire system should be analyzed together to design or test the gyroscope. In this study, a MEMS vibratory gyroscope is analyzed based on the system dynamic modeling; thus, it can be mathematically expressed and integrated into a circuit simulator. A behavioral simulation of the entire system was conducted to prove the self-oscillation and angular-rate detection and to determine the circuit parameters to be optimized. From the simulation, the operating characteristic according to the vacuum pressure and scale factor was obtained, which indicated similar trends compared with those of the experimental results. The simulation method presented in this paper can be generalized to a wide range of MEMS devices.

  14. System Modeling of a MEMS Vibratory Gyroscope and Integration to Circuit Simulation

    Directory of Open Access Journals (Sweden)

    Hyukjin J. Kwon

    2017-11-01

    Full Text Available Recently, consumer applications have dramatically created the demand for low-cost and compact gyroscopes. Therefore, on the basis of microelectromechanical systems (MEMS technology, many gyroscopes have been developed and successfully commercialized. A MEMS gyroscope consists of a MEMS device and an electrical circuit for self-oscillation and angular-rate detection. Since the MEMS device and circuit are interactively related, the entire system should be analyzed together to design or test the gyroscope. In this study, a MEMS vibratory gyroscope is analyzed based on the system dynamic modeling; thus, it can be mathematically expressed and integrated into a circuit simulator. A behavioral simulation of the entire system was conducted to prove the self-oscillation and angular-rate detection and to determine the circuit parameters to be optimized. From the simulation, the operating characteristic according to the vacuum pressure and scale factor was obtained, which indicated similar trends compared with those of the experimental results. The simulation method presented in this paper can be generalized to a wide range of MEMS devices.

  15. A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

    Directory of Open Access Journals (Sweden)

    Daniel Pacheco Bautista

    2010-04-01

    Full Text Available The clock recovery circuit (CRC plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC wor-king at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL, current mode logic (MCML and a novel two stage ring-based voltage controlled oscillator (VCO. The design used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

  16. Comparison of a new integrated current source with the modified Howland circuit for EIT applications.

    Science.gov (United States)

    Hong, Hongwei; Rahal, Mohamad; Demosthenous, Andreas; Bayford, Richard H

    2009-10-01

    Multi-frequency electrical impedance tomography (MF-EIT) systems require current sources that are accurate over a wide frequency range (1 MHz) and with large load impedance variations. The most commonly employed current source design in EIT systems is the modified Howland circuit (MHC). The MHC requires tight matching of resistors to achieve high output impedance and may suffer from instability over a wide frequency range in an integrated solution. In this paper, we introduce a new integrated current source design in CMOS technology and compare its performance with the MHC. The new integrated design has advantages over the MHC in terms of power consumption and area. The output current and the output impedance of both circuits were determined through simulations and measurements over the frequency range of 10 kHz to 1 MHz. For frequencies up to 1 MHz, the measured maximum variation of the output current for the integrated current source is 0.8% whereas for the MHC the corresponding value is 1.5%. Although the integrated current source has an output impedance greater than 1 MOmega up to 1 MHz in simulations, in practice, the impedance is greater than 160 kOmega up to 1 MHz due to the presence of stray capacitance.

  17. Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

    Science.gov (United States)

    Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

    2010-02-21

    Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings.

  18. SEMICONDUCTOR INTEGRATED CIRCUITS: Design and research of an LED driving circuit with accurate proportional current sampling mode

    Science.gov (United States)

    Wei, Guo; Xing, Yang; Dazhong, Zhu

    2010-04-01

    An LED driving circuit in accurate proportional current sampling mode is designed and fabricated based on CSMC 0.5 μm standard CMOS technology. It realizes accurate sensing of sampling current variation with output driving current. A better constant output current characteristic is achieved by using an amplifier to clamp the drain voltage of both the sampling MOSFET and power MOSFET to the same value with feedback control. Small signal equivalent circuit analysis shows that the small signal output resistance in the accurate proportional current sampling mode circuit is much larger than that in a traditional proportional current sampling mode circuit, and circuit stability could be assured. Circuit simulation and chip testing results show that when the LED driving current is 350 mA and the power supply is 6 V with ±10% variation, the stability of the output constant current of the accurate proportional current sampling mode LED driving IC will show 41% improvement over that of a traditional proportional current sampling mode LED driving IC.

  19. The functional significance of newly born neurons integrated into olfactory bulb circuits

    Directory of Open Access Journals (Sweden)

    Masayuki eSakamoto

    2014-05-01

    Full Text Available The olfactory bulb (OB is the first central processing center for olfactory information connecting with higher areas in the brain, and this neuronal circuitry mediates a variety of odor-evoked behavioral responses. In the adult mammalian brain, continuous neurogenesis occurs in two restricted regions, the subventricular zone (SVZ of the lateral ventricle and the hippocampal dentate gyrus. New neurons born in the SVZ migrate through the rostral migratory stream and are integrated into the neuronal circuits of the OB throughout life. The significance of this continuous supply of new neurons in the OB has been implicated in plasticity and memory regulation. Two decades of huge investigation in adult neurogenesis revealed the biological importance of integration of new neurons into the olfactory circuits. In this review, we highlight the recent findings about the physiological functions of newly generated neurons in rodent OB circuits and then discuss the contribution of neurogenesis in the brain function. Finally, we introduce cutting edge technologies to monitor and manipulate the activity of new neurons.

  20. 6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

    Science.gov (United States)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.; hide

    2008-01-01

    The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

  1. A contact lens with integrated telecommunication circuit and sensors for wireless and continuous tear glucose monitoring

    Science.gov (United States)

    Yao, H.; Liao, Y.; Lingley, A. R.; Afanasiev, A.; Lähdesmäki, I.; Otis, B. P.; Parviz, B. A.

    2012-07-01

    We present an integrated functional contact lens, composed of a differential glucose sensor module, metal interconnects, sensor read-out circuit, antenna and telecommunication circuit, to monitor tear glucose levels wirelessly, continuously and non-invasively. The electrochemical differential sensor module is based on immobilization of activated and de-activated glucose oxidase. We characterized the sensor on a model polymer eye and determined that it showed good repeatability, molecular interference rejection and linearity in the range of 0-2 mM glucose, covering normal tear glucose concentrations (0.1-0.6 mM). We also report the temperature, ageing and protein-fouling sensitivity of the sensor. We report the design and implementation of a low-power (3 µW) sensor read-out and telecommunication circuit to deliver wireless power and transmit data for the sensor module. Using this small chip (0.36 mm2), we produced an integrated contact lens with sensors and demonstrated wireless operation of the system and glucose read-out over the distance of several centimeters.

  2. The functional significance of newly born neurons integrated into olfactory bulb circuits.

    Science.gov (United States)

    Sakamoto, Masayuki; Kageyama, Ryoichiro; Imayoshi, Itaru

    2014-01-01

    The olfactory bulb (OB) is the first central processing center for olfactory information connecting with higher areas in the brain, and this neuronal circuitry mediates a variety of odor-evoked behavioral responses. In the adult mammalian brain, continuous neurogenesis occurs in two restricted regions, the subventricular zone (SVZ) of the lateral ventricle and the hippocampal dentate gyrus. New neurons born in the SVZ migrate through the rostral migratory stream and are integrated into the neuronal circuits of the OB throughout life. The significance of this continuous supply of new neurons in the OB has been implicated in plasticity and memory regulation. Two decades of huge investigation in adult neurogenesis revealed the biological importance of integration of new neurons into the olfactory circuits. In this review, we highlight the recent findings about the physiological functions of newly generated neurons in rodent OB circuits and then discuss the contribution of neurogenesis in the brain function. Finally, we introduce cutting edge technologies to monitor and manipulate the activity of new neurons.

  3. Engineering integrated digital circuits with allosteric ribozymes for scaling up molecular computation and diagnostics.

    Science.gov (United States)

    Penchovsky, Robert

    2012-10-19

    Here we describe molecular implementations of integrated digital circuits, including a three-input AND logic gate, a two-input multiplexer, and 1-to-2 decoder using allosteric ribozymes. Furthermore, we demonstrate a multiplexer-decoder circuit. The ribozymes are designed to seek-and-destroy specific RNAs with a certain length by a fully computerized procedure. The algorithm can accurately predict one base substitution that alters the ribozyme's logic function. The ability to sense the length of RNA molecules enables single ribozymes to be used as platforms for multiple interactions. These ribozymes can work as integrated circuits with the functionality of up to five logic gates. The ribozyme design is universal since the allosteric and substrate domains can be altered to sense different RNAs. In addition, the ribozymes can specifically cleave RNA molecules with triplet-repeat expansions observed in genetic disorders such as oculopharyngeal muscular dystrophy. Therefore, the designer ribozymes can be employed for scaling up computing and diagnostic networks in the fields of molecular computing and diagnostics and RNA synthetic biology.

  4. PCSIM: A Parallel Simulation Environment for Neural Circuits Fully Integrated with Python

    Science.gov (United States)

    Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

    2008-01-01

    The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations. PMID:19543450

  5. Structure of the EGF receptor transactivation circuit integrates multiple signals with cell context

    Energy Technology Data Exchange (ETDEWEB)

    Joslin, Elizabeth J.; Shankaran, Harish; Opresko, Lee K.; Bollinger, Nikki; Lauffenburger, Douglas A.; Wiley, H. S.

    2010-05-10

    Transactivation of the epidermal growth factor receptor (EGFR) has been proposed to be a mechanism by which a variety of cellular inputs can be integrated into a single signaling pathway, but the regulatory topology of this important system is unclear. To understand the transactivation circuit, we first created a “non-binding” reporter for ligand shedding. We then quantitatively defined how signals from multiple agonists were integrated both upstream and downstream of the EGFR into the extracellular signal regulated kinase (ERK) cascade in human mammary epithelial cells. We found that transactivation is mediated by a recursive autocrine circuit where ligand shedding drives EGFR-stimulated ERK that in turn drives further ligand shedding. The time from shedding to ERK activation is fast (<5 min) whereas the recursive feedback is slow (>15 min). Simulations showed that this delay in positive feedback greatly enhanced system stability and robustness. Our results indicate that the transactivation circuit is constructed so that the magnitude of ERK signaling is governed by the sum of multiple direct inputs, while recursive, autocrine ligand shedding controls signal duration.

  6. Integrated cascade of photovoltaic cells as a power supply for integrated circuits

    OpenAIRE

    Mouthaan, A.J.

    1984-01-01

    ICs can be powered directly when a supply voltage source capable of generating a multiple of the open circuit voltage of one pn-junction is available on a chip. Two schemes have been investigated for cascading photovoltaic cells on the chip. The structures can be made compatible with standard bipolar processes. Deep ion implantations have been used here to realize the multiple-junction structure. Power losses due to photocurrents originating from insulation junctions in the cascade can be kep...

  7. Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits

    Science.gov (United States)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2013-01-01

    A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.

  8. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  9. A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

    Directory of Open Access Journals (Sweden)

    Chyan-Chyi Wu

    2011-11-01

    Full Text Available A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

  10. SH-wave seismic reflection at a landslide (Patigno, NW Italy) integrated with P-wave

    Science.gov (United States)

    Stucchi, E.; Tognarelli, A.; Ribolini, A.

    2017-11-01

    The aim of this paper is to present the acquisition and processing up to the depth migrated section of an SH-wave reflection seismic profile. This experience is conducted on a deep-seated gravitational slope deformation located in the Northern Apennines in Italy. The SH-wave depth-migrated image in the investigated area provides a detailed description of the small reactivation slip surfaces delineating minor landslides at shallow depths, which are responsible for the major damages observed. These results are integrated with a recently acquired P-wave seismic reflection profile investigating the same slope and delineating the highly deformed layer at depth, liable for the deep-seated gravitational slope deformation. The combined use of P-waves and SH-waves allows to gain a deeper knowledge of the landslide internal setting that is necessary to mitigate the risk associated with the mass movement.

  11. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

    Science.gov (United States)

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-27

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

  12. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

    Science.gov (United States)

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-01

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956

  13. Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

    Science.gov (United States)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith Roger D.; Ferrier, Terry L.; Krasowski, Michael J.; hide

    2008-01-01

    NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

  14. SPICE Simulations of single event transients in bipolar analog integrated circuits using public information and free open source tools

    OpenAIRE

    Franco Peláez, Francisco Javier; Palomar Trives, Carlos; González Izquierdo, Jesús; Agapito Serrano, Juan Andrés

    2015-01-01

    This paper proposes a technique to build SPICE micromodels of integrated circuits in bipolar technology appropriate to simulate single event transients. First of all, we will show how to obtain SPICE models of the internal transistors from texts in the scientific and academic literature. Next, several strategies to figure out the internal structure of the integrated circuits and bias point will be shown. Finally, simulation results will be compared to data issue from experiments, either perfo...

  15. Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

    Science.gov (United States)

    Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

    2013-09-01

    A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

  16. Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

    Science.gov (United States)

    Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

    2011-12-19

    We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

  17. Design of a high-speed vertical transition in LTCC for interposers suitable for packaging photonic integrated circuits

    Science.gov (United States)

    Jezzini, M. A.; Marraccini, P. J.; Peters, F. H.

    2016-05-01

    The packaging of high speed Photonic Integrated Circuits (PICs) should maintain the electrical signal integrity. The standard packaging of high speed PICs relies on wire bonds. This is not desirable because wire bonds degrade the quality of the electrical signal. The research presented in this paper proposes to replace wire bonds with an interposer with multilevel transmission lines. By attaching the PIC by flip chip onto the interposer, the use of wire bonds is avoided. The main concern for designing an interposer with multilevel transmission lines is the vertical transition, which must be designed to avoid return and radiation losses. In this paper, a novel design of a high speed vertical transition for Low Temperature Co-fired Ceramic (LTCC) is presented. The proposed vertical transition is simpler than others recently published in the literature, due to eliminating the need for additional ceramic layers or air cavities. A LTCC board was fabricated with several variations of the presented transition to find the optimal dimensions of the structure. The structures were fabricated then characterized and have a 3 dB bandwidth of 37 GHz and an open eye diagram at 44 Gbps. A full wave electromagnetic simulation is described and compared with good agreement to the measurements. The results suggest that an LTCC board with this design can be used for 40 Gbps per channel applications. Keywords: Photonics packaging, Low Temperature Co-Fired Ceramics.

  18. An Integrated Circuit for Signal Processing of the AMS RICH Photmultipliers Tubes

    CERN Document Server

    Barrau, A; Pouxe, J; Rossetto, O

    1998-01-01

    An analog integrated circuit has been designed, in a BiCMOS 0.8 micron technology, for the feasability study of the signal processing of the AMS RICH photomultiplier tubes. This low power, three channel gated integrator includes its own gate and no external analog delay is requiered. It processes PMT pulses over a dynamic range of more than 100. A logic output that indicates whether the analog charge has to be considered is provided. This gated integrator is used with a compact DSP based acquisition system in a 132 channels RICH prototype. The charge calibration of each channel is carried out using a LED. The pedestal measurement is performed on activation of a dedicated input. The noise contribution study of the input RC network and amplifiers is presented.

  19. Design of two digital radiation tolerant integrated circuits for high energy physics experiments data readout

    CERN Document Server

    Bonacini, Sandro

    2003-01-01

    High Energy Physics research (HEP) involves the design of readout electron- ics for its experiments, which generate a high radiation ¯eld in the detectors. The several integrated circuits placed in the future Large Hadron Collider (LHC) experiments' environment have to resist the radiation and carry out their normal operation. In this thesis I will describe in detail what, during my 10-months partic- ipation in the digital section of the Microelectronics group at CERN, I had the possibility to work on: - The design of a radiation-tolerant data readout digital integrated cir- cuit in a 0.25 ¹m CMOS technology, called \\the Kchip", for the CMS preshower front-end system. This will be described in Chapter 3. - The design of a radiation-tolerant SRAM integrated circuit in a 0.13 ¹m CMOS technology, for technology radiation testing purposes and fu- ture applications in the HEP ¯eld. The SRAM will be described in Chapter 4. All the work has carried out under the supervision and with the help of Dr. Kostas Klouki...

  20. Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

    Science.gov (United States)

    Kim, Hyungseup; Park, Yunjong; Ko, Youngwoon; Mun, Yeongjin; Lee, Sangmin; Ko, Hyoungho

    2017-10-13

    Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

  1. Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits

    Science.gov (United States)

    Ker, Ming-Dou; Hsiao, Yuan-Wen

    An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.

  2. Modeling for infrared readout integrated circuit based on Verilog-A

    Science.gov (United States)

    Wang, Xiao; Shi, Zelin

    2015-04-01

    Infrared detectors are the core of infrared imaging systems, while readout integrated circuits are the key components of detectors. In order to grasp the performance of circuits quickly and accurately, a method of circuit modeling using Verilog-A language is proposed, which present a behavioral simulation model for the ROIC. At first, a typical capacitor trans-impedance amplifier(CTIA) ROIC unit is showed, then the two essential parts of it,operational amplifier and switch are modeled on behavioral level. The op amp model concludes these non-ideal factors, such as finite gain-bandwidth product, input and output offset, output resistance and so on. Non-deal factors that affect switches are considered in the switch behavioral model, such as rise and fall time, on-resistance and so on. At last time-domain modeling method for noise is presented, which is compared with the classical frequency domain method for difference. The analysis results shows that in the situation that noise interested bandwidth(NIBW) is more than 5MHz, the difference between the two methods leads to less than 1% if the sample rate of noise is larger 4 times of the NIBW

  3. Microfluidic pneumatic logic circuits and digital pneumatic microprocessors for integrated microfluidic systems.

    Science.gov (United States)

    Rhee, Minsoung; Burns, Mark A

    2009-11-07

    We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprocessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner.

  4. Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

    Science.gov (United States)

    Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

    2017-02-15

    An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si3N4) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si3N4 and the LN-Si3N4 waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

  5. Laser attacks on integrated circuits: from CMOS to FD-SOI

    OpenAIRE

    Dutertre, Jean-Max; De Castro, Stephan; Sarafianos, Alexandre; Boher, Noémie; Rouzeyre, Bruno; Lisart, Mathieu; Damiens, Joel; Candelier, Philippe; Flottes, Marie-Lise; Di Natale, Giorgio

    2014-01-01

    International audience; The use of a laser as a means to inject errors during the computations of a secure integrated circuit (IC) for the purpose of retrieving secret data was first reported in 2002. Since then, a lot of research work, mainly experimental, has been carried out to study this threat. This paper reports research conducted, in the framework of the french national project LIESSE, to obtain an electrical model of the laser effects on CMOS ICs. Based on simulation, a first model pe...

  6. Detection of alpha particle contamination on ultra low activity-grade integrated circuits

    Directory of Open Access Journals (Sweden)

    Fernandes Ana C.

    2016-01-01

    Full Text Available We propose to apply the superheated droplet detector (SDD technology to the measurement of alpha-particle emissivity on integrated circuits of ultra-low activity grade (< 1α/khcm2 for high reliability applications. This work is based on the SDDs employed within our team to the direct search for dark matter. We describe the modifications in the dark matter SDDs with respect to fabrication, signal analysis and characterization, in order to obtain a device with the adequate detection sensitivity and background noise.

  7. Organic–Inorganic Eu3+/Tb3+ codoped hybrid films for temperature mapping in integrated circuits

    Science.gov (United States)

    Brites, Carlos D. S.; Lima, Patrícia P.; Silva, Nuno J. O.; Millán, Angel; Amaral, Vitor S.; Palacio, Fernando; Carlos, Luís D.

    2013-01-01

    The continuous decrease on the geometric size of electronic devices and integrated circuits generates higher local power densities and localized heating problems that cannot be characterized by conventional thermographic techniques. Here, a self-referencing intensity-based molecular thermometer involving a di-ureasil organic-inorganic hybrid thin film co-doped with Eu3+ and Tb3+ tris (β-diketonate) chelates is used to obtain the temperature map of a FR4 printed wiring board with spatio-temporal resolutions of 0.42 μm/4.8 ms. PMID:24790938

  8. All-fiber hybrid photon-plasmon circuits: integrating nanowire plasmonics with fiber optics.

    Science.gov (United States)

    Li, Xiyuan; Li, Wei; Guo, Xin; Lou, Jingyi; Tong, Limin

    2013-07-01

    We demonstrate all-fiber hybrid photon-plasmon circuits by integrating Ag nanowires with optical fibers. Relying on near-field coupling, we realize a photon-to-plasmon conversion efficiency up to 92% in a fiber-based nanowire plasmonic probe. Around optical communication band, we assemble an all-fiber resonator and a Mach-Zehnder interferometer (MZI) with Q-factor of 6 × 10(6) and extinction ratio up to 30 dB, respectively. Using the MZI, we demonstrate fiber-compatible plasmonic sensing with high sensitivity and low optical power.

  9. Infrared and millimeter waves v.14 millimeter components and techniques, pt.V

    CERN Document Server

    Button, Kenneth J

    1985-01-01

    Infrared and Millimeter Waves, Volume 14: Millimeter Components and Techniques, Part V is concerned with millimeter-wave guided propagation and integrated circuits. In addition to millimeter-wave planar integrated circuits and subsystems, this book covers transducer configurations and integrated-circuit techniques, antenna arrays, optoelectronic devices, and tunable gyrotrons. Millimeter-wave gallium arsenide (GaAs) IMPATT diodes are also discussed. This monograph is comprised of six chapters and begins with a description of millimeter-wave integrated-circuit transducers, focusing on vario

  10. A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

    Science.gov (United States)

    DuMonthier, Jeffrey; Suarez, George

    2013-01-01

    Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the

  11. Integration issues of a photonic layer on top of a CMOS circuit

    Science.gov (United States)

    Fedeli, J. M.; Orobtchouk, R.; Seassal, C.; Vivien, L.

    2006-02-01

    Photonics on CMOS is the integration of CMOS technology and optics components to enable either improved functionality of the electronic circuit (e.g. optical clock distribution) or as a means to miniaturize optical functions (e.g. miniaturised transceiver). The Near Infra Red (NIR) wavelength range (1.3 or 1.55μm) was chosen for this to minimise the impact the light on the behaviour of the microelectronic components. The integration of a photonic layer on a CMOS circuit can be seen in different ways: A combined fabrication at the front end level, the wafer bonding of an SOI photonic circuit at the back-end level, or the insertion of an embedded photonic layer between metallization schemes. For combined fabrication, a silicon on insulator rib technology has been developed with low (0.4dB/cm) propagation loss, ultra-high speed Ge-on-Si photodetector and SiGe/Si modulators.. In the metal-semiconductor-metal (MSM) configuration, bandwith of 35 GHz at 1.3 μm and 1.55μm has been measured. In the second approach, a wafer bonding of silicon rib and stripe technologies was achieved above the metallization layers of a CMOS wafer. For the third method, direct fabrication of a photonic layer at the back-end level was achieved using low temperature processes. Waveguide technologies such as SiNx (loss 2dB/cm) or amorphous silicon (loss 5dB/cm) were developed and were followed by the molecular bonding of InP die, these were needed to create the optoelectronic components (sources and detectors). Using an InP microdisk, 50% coupling was achieved to a stripe silicon waveguide.

  12. Remote sensing of microbial volatile organic compounds with a bioluminescent bioreporter integrated circuit

    Science.gov (United States)

    Ripp, Steven A.; Daumer, Kathleen A.; Garland, Jay L.; Simpson, Michael L.; Sayler, Gary S.

    2004-03-01

    As a means towards advanced, early-warning detection of microbial growth in enclosed structures, we have constructed a bioluminescent bioreporter for the detection of the microbial volatile organic compound (MVOC) p-cymene. MVOCs are produced as metabolic by-products of bacteria and fungi and are detectable before any visible signs of microbial growth appear, thereby serving as very early indicators of potential biocontamination problems. The bioreporter, designated Pseudomonas putida UT93, contains a Vibrio fischeri luxCDABE gene fusion to a p-cymene/p-cumate inducible promoter. Exposure of strain UT93 to p-cymene from approximately 0.02 to 850 ppm produced self-generated bioluminescence in less than 1.5 hours. The bioreporter was also interfaced with an integrated circuit microluminometer to create a miniaturized hybrid sensor for remote monitoring of p-cymene signatures. This bioluminescent bioreporter integrated circuit (BBIC) device was capable of detecting fungal presence within approximately 3.5 hours of initial exposure to Penicillium roqueforti.

  13. Mode converter based on an inverse taper for multimode silicon nanophotonic integrated circuits.

    Science.gov (United States)

    Dai, Daoxin; Mao, Mao

    2015-11-02

    An inverse taper on silicon is proposed and designed to realize an efficient mode converter available for the connection between multimode silicon nanophotonic integrated circuits and few-mode fibers. The present mode converter has a silicon-on-insulator inverse taper buried in a 3 × 3μm(2) SiN strip waveguide to deal with not only for the fundamental mode but also for the higher-order modes. The designed inverse taper enables the conversion between the six modes (i.e., TE(11), TE(21), TE(31), TE(41), TM(11), TM(12)) in a 1.4 × 0.22μm(2) multimode SOI waveguide and the six modes (like the LP(01), LP(11a), LP(11b) modes in a few-mode fiber) in a 3 × 3μm(2) SiN strip waveguide. The conversion efficiency for any desired mode is higher than 95.6% while any undesired mode excitation ratio is lower than 0.5%. This is helpful to make multimode silicon nanophotonic integrated circuits (e.g., the on-chip mode (de)multiplexers developed well) available to work together with few-mode fibers in the future.

  14. Single-cell axotomy of cultured hippocampal neurons integrated in neuronal circuits.

    Science.gov (United States)

    Gomis-Rüth, Susana; Stiess, Michael; Wierenga, Corette J; Meyn, Liane; Bradke, Frank

    2014-05-01

    An understanding of the molecular mechanisms of axon regeneration after injury is key for the development of potential therapies. Single-cell axotomy of dissociated neurons enables the study of the intrinsic regenerative capacities of injured axons. This protocol describes how to perform single-cell axotomy on dissociated hippocampal neurons containing synapses. Furthermore, to axotomize hippocampal neurons integrated in neuronal circuits, we describe how to set up coculture with a few fluorescently labeled neurons. This approach allows axotomy of single cells in a complex neuronal network and the observation of morphological and molecular changes during axon regeneration. Thus, single-cell axotomy of mature neurons is a valuable tool for gaining insights into cell intrinsic axon regeneration and the plasticity of neuronal polarity of mature neurons. Dissociation of the hippocampus and plating of hippocampal neurons takes ∼2 h. Neurons are then left to grow for 2 weeks, during which time they integrate into neuronal circuits. Subsequent axotomy takes 10 min per neuron and further imaging takes 10 min per neuron.

  15. A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

    Directory of Open Access Journals (Sweden)

    Kyeonghwan Park

    2017-04-01

    Full Text Available This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

  16. SEMICONDUCTOR INTEGRATED CIRCUITS: Mixed-integrator-based bi-quad cell for designing a continuous time filter

    Science.gov (United States)

    Yong, Chen; Yumei, Zhou

    2010-04-01

    A new mixed-integrator-based bi-quad cell is proposed. An alternative synthesis mechanism of complex poles is proposed compared with source-follower-based bi-quad cells which is designed applying the positive feedback technique. Using the negative feedback technique to combine different integrators, the proposed bi-quad cell synthesizes complex poles for designing a continuous time filter. It exhibits various advantages including compact topology, high gain, no parasitic pole, no CMFB circuit, and high capability. The fourth-order Butterworth lowpass filter using the proposed cells has been fabricated in 0.18 μm CMOS technology. The active area occupied by the filter with test buffer is only 200 × 170 μm2. The proposed filter consumes a low power of 201 μW and achieves a 68.5 dB dynamic range.

  17. Full control of far-field radiation via photonic integrated circuits decorated with plasmonic nanoantennas.

    Science.gov (United States)

    Sun, Yi-Zhi; Feng, Li-Shuang; Bachelot, Renaud; Blaize, Sylvain; Ding, Wei

    2017-07-24

    We theoretically develop a hybrid architecture consisting of photonic integrated circuit and plasmonic nanoantennas to fully control optical far-field radiation with unprecedented flexibility. By exploiting asymmetric and lateral excitation from silicon waveguides, single gold nanorod and cascaded nanorod pair can function as component radiation pixels, featured by full 2π phase coverage and nanoscale footprint. These radiation pixels allow us to design scalable on-chip devices in a wavefront engineering fashion. We numerically demonstrate beam collimation with 30° out of the incident plane and nearly diffraction limited divergence angle. We also present high-numerical-aperture (NA) beam focusing with NA ≈0.65 and vector beam generation (the radially-polarized mode) with the mode similarity greater than 44%. This concept and approach constitutes a designable optical platform, which might be a future bridge between integrated photonics and metasurface functionalities.

  18. EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    S. A. Chizhik

    2013-01-01

    Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

  19. Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    Cheng-Yang Liu

    2009-12-01

    Full Text Available The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa.

  20. Operational Excellence through Schedule Optimization and Production Simulation of Application Specific Integrated Circuits.

    Energy Technology Data Exchange (ETDEWEB)

    Flory, John Andrew [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Padilla, Denise D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Gauthier, John H. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Zwerneman, April Marie [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Miller, Steven P [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2016-05-01

    Upcoming weapon programs require an aggressive increase in Application Specific Integrated Circuit (ASIC) production at Sandia National Laboratories (SNL). SNL has developed unique modeling and optimization tools that have been instrumental in improving ASIC production productivity and efficiency, identifying optimal operational and tactical execution plans under resource constraints, and providing confidence in successful mission execution. With ten products and unprecedented levels of demand, a single set of shared resources, highly variable processes, and the need for external supplier task synchronization, scheduling is an integral part of successful manufacturing. The scheduler uses an iterative multi-objective genetic algorithm and a multi-dimensional performance evaluator. Schedule feasibility is assessed using a discrete event simulation (DES) that incorporates operational uncertainty, variability, and resource availability. The tools provide rapid scenario assessments and responses to variances in the operational environment, and have been used to inform major equipment investments and workforce planning decisions in multiple SNL facilities.

  1. Length minimization design considerations in photonic integrated circuits incorporating directional couplers

    Science.gov (United States)

    Boyd, Joseph T.; Radens, Carl J.; Kauffman, Michael T.

    1991-01-01

    Because directional couplers involve channel waveguides which are very close to one another, transition regions to regions where channel waveguides are widely separated are utilized. The total length of a directional coupler and transition regions can be minimized for a particular degree of field confinement. Calculations presented for LiNbO3-, GaAlAs-, and SiO2/Si-based optical channel waveguides demonstrate the presence of a minimum total length corresponding to a particular degree of field confinement. The overall length at the minimum is shown to be significantly lower than for other values of field confinement allowing single-mode operation. This implies that either more devices can be integrated on a substrate or that less material is needed for an integrated optical circuit.

  2. On the Basis of Synaptic Integration Constancy during Growth of a Neuronal Circuit

    Directory of Open Access Journals (Sweden)

    Adriana De-La-Rosa Tovar

    2016-08-01

    Full Text Available We studied how a neuronal circuit composed of two neuron types connected by chemical and electrical synapses maintains constant its integrative capacities as neurons grow. For this we combined electrophysiological experiments with mathematical modeling in pairs of electrically-coupled Retzius neurons from postnatal to adult leeches. The electrically-coupled dendrites of both Retzius neurons receive a common chemical input, which produces excitatory postsynaptic potentials (EPSPs with varying amplitudes. Each EPSP spreads to the soma, but also crosses the electrical synapse to arrive at the soma of the coupled neuron. The leak of synaptic current across the electrical synapse reduces the amplitude of the EPSPs in proportion to the coupling ratio. In addition, summation of EPSPs generated in both neurons generates the baseline action potentials of these serotonergic neurons. To study how integration is adjusted as neurons grow, we first studied the characteristics of the chemical and electrical connections onto the coupled dendrites of neuron pairs with soma diameters ranging from 21 to 75 μm. Then by feeding a mathematical model with the neuronal voltage responses to pseudorandom noise currents we obtained the values of the coupling ratio, the membrane resistance of the soma (rm and dendrites (rdend, the space constant (λ and the characteristic dendritic length (L = l/λ. We found that the EPSPs recorded from the somata were similar regardless on the neuron size. However, the amplitude of the EPSPs and the firing frequency of the neurons were inversely proportional to the coupling ratio of the neuron pair, which also was independent from the neuronal size. This data indicated that the integrative constancy relied on the passive membrane properties. We show that the growth of Retzius neurons was compensated by increasing the membrane resistance of the dendrites and therefore the λ value. By solely increasing the dendrite resistance this circuit

  3. Test and diagnosis of analogue, mixed-signal and RF integrated circuits the system on chip approach

    CERN Document Server

    Sun, Yichuang

    2008-01-01

    This book provides a comprehensive discussion of automatic testing, diagnosis and tuning of analogue, mixed-signal and RF integrated circuits, and systems in a single source. The book contains eleven chapters written by leading researchers worldwide. As well as fundamental concepts and techniques, the book reports systematically the state of the arts and future research directions of these areas. A complete range of circuit components are covered and test issues are also addressed from the SoC perspective.

  4. Electrical and optoelectrical monolithically integrated circuits on InP based heterostructures; Elektrische und optoelektrische monolithisch integrierte Schaltungen auf InP-basierenden Heterostrukturen

    Energy Technology Data Exchange (ETDEWEB)

    Hodel, U.

    2001-03-01

    A key element in long distance data communication systems is the optoelectrical detector system for light with a wavelength between 1.3 {mu}m and 1.55 {mu}m, the dispersion and absorption minimum of a typical glasfiber. In this thesis InP-based heterostructures for integrating high frequency photodetectors and transistors for applications in data communication systems have been investigated. Rf-optimized pseudomorphic HEMTs have been produced on an InAlAs/InGaAs layer system and characterized. The addition of an InGaAs absorption layer to the HEMT layer system allows the production of transistors and photodetectors in parallel. The influence of the additional layer on the performance of the photodetectors and the transistors was investigated and the properties of the layer system has been optimized so that both devices still show a good high frequency performance. To demonstrate the capability for a monolithical integration a photoreceiver, consisting of an MSM-photodiode and a traveling wave amplifier with two HEMTS has been produced. The optoelectrical circuit reached a bandwidth of 13.5 GHz and a response of 0.7 A/W. It has been shown that the presented InGaAs/InAlAs layer system with an additional absorption layer provides a solution for a monolithical integration of MSM photodiodes and HEMTs. A demonstration circuit showed results comparable to existing solutions for integrating photodetectors with HEMTs while minimizing the technological effort. (orig.)

  5. Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

    Science.gov (United States)

    Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

    2011-02-22

    Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

  6. Extremely Fast Numerical Integration of Ocean Surface Wave Dynamics

    Science.gov (United States)

    2007-09-30

    Extremely Fast Numerical Integration of Ocean Surface Wave Dynamics A. R. Osborne Dipartimento di Fisica Generale , Università di Torino Via...WORK UNIT NUMBER 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) Dipartimento di Fisica Generale , Universit?i Torino,Via Pietro Giuria 1,10125...data. The approach may be viewed as a generalization of linear Fourier analysis and is loosely referred to as "Nonlinear Fourier Analysis or

  7. Integrated wave-current-sediment numerical tools in coastal areas

    Science.gov (United States)

    Carniel, S.; Bever, A.; Tondello, M.; Kantha, L. H.; Sclavo, M.

    2010-09-01

    The possibility of employing complex, integrated wave-current-sediment numerical models to correctly simulate near-shore processes requires the high-fidelity description of relevant issues such as wave-current interactions, turbulent mixing, wetting and drying processes, bottom-boundary layer interactions and sediment re-suspension and transport. The achievement of these capabilities is mostly welcome in a variety of applications ranging from beach protection to "search and rescue" activities and support to maritime engineering operations. In the last decade there has been a considerable advance in the development of these integrated models, both thanks to improvements in the theoretical background and to recent advances in the computer performances that allowed higher-resolution, long-term integrations and ensemble runs. The growing availability of long time-series and large forcing from meteorological and sea-state numerical models are now allowing to employ complex, integrated numerical tools to model coastal dynamical processes and to support decision makers in the field of coastal erosion and vulnerability. The contribution aims at presenting an application focused on the western Adriatic context, with appropriate links to state-of-the-art and cutting-edge research issues that represent the challenges for the next decades. Namely, the morphological modeling of a river outlet area near Ravenna (Northern Adriatic Sea) will be discussed. The numerical model adopted is ROMS,in its 3-D coupled version with the wave model SWAN and a sediment transport module, including wetting/drying and wave current interactions. The coupled model adopts a very high horizontal resolution, order of 5 meters, to model the hydrodynamic and morphological conditions of the river mouth under synthetic but realistic forcings, i.e. tidal cycle, river flooding and severe wind storms. Model results show how it is becoming possible to provide useful support for planning effective management

  8. Integration of thin film giant magnetoimpedance sensor and surface acoustic wave transponder

    KAUST Repository

    Li, Bodong

    2012-03-09

    Passive and remote sensing technology has many potential applications in implantable devices, automation, or structural monitoring. In this paper, a tri-layer thin film giant magnetoimpedance (GMI) sensor with the maximum sensitivity of 16%/Oe and GMI ratio of 44% was combined with a two-port surface acoustic wave(SAW) transponder on a common substrate using standard microfabrication technology resulting in a fully integrated sensor for passive and remote operation. The implementation of the two devices has been optimized by on-chip matching circuits. The measurement results clearly show a magnetic field response at the input port of the SAW transponder that reflects the impedance change of the GMI sensor.

  9. Flexible low-voltage organic integrated circuits with megahertz switching frequencies (Presentation Recording)

    Science.gov (United States)

    Zschieschang, Ute; Takimiya, Kazuo; Zaki, Tarek; Letzkus, Florian; Richter, Harald; Burghartz, Joachim N.; Klauk, Hagen

    2015-09-01

    A process for the fabrication of integrated circuits based on bottom-gate, top-contact organic thin-film transistors (TFTs) with channel lengths as short as 1 µm on flexible plastic substrates has been developed. In this process, all TFT layers (gate electrodes, organic semiconductors, source/drain contacts) are patterned with the help of high-resolution silicon stencil masks, thus eliminating the need for subtractive patterning and avoiding the exposure of the organic semiconductors to potentially harmful organic solvents or resists. The TFTs employ a low-temperature-processed gate dielectric that is sufficiently thin to allow the TFTs and circuits to operate with voltages of about 3 V. Using the vacuum-deposited small-molecule organic semiconductor 2,9-didecyl-dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (C10 DNTT), TFTs with an effective field-effect mobility of 1.2 cm2/Vs, an on/off current ratio of 107, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 nsec per stage at a supply voltage of 3 V have been obtained. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V. In addition to flexible ring oscillators, we have also demonstrated a 6-bit digital-to-analog converter (DAC) in a binary-weighted current-steering architecture, based on TFTs with a channel length of 4 µm and fabricated on a glass substrate. This DAC has a supply voltage of 3.3 V, a circuit area of 2.6 × 4.6 mm2, and a maximum sampling rate of 100 kS/s.

  10. A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

    Science.gov (United States)

    Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

    2014-10-01

    This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

  11. Materials and noncoplanar mesh designs for integrated circuits with linear elastic responses to extreme mechanical deformations

    Science.gov (United States)

    Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y.; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A.

    2008-01-01

    Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90° in ≈1 cm) and linear stretching to “rubber-band” levels of strain (e.g., up to ≈140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics. PMID:19015528

  12. GaAs Photonic Integrated Circuit (PIC) development for high performance communications

    Energy Technology Data Exchange (ETDEWEB)

    Sullivan, C.T.

    1998-03-01

    Sandia has established a foundational technology in photonic integrated circuits (PICs) based on the (Al,Ga,In)As material system for optical communication, radar control and testing, and network switching applications at the important 1.3{mu}m/1.55{mu}m wavelengths. We investigated the optical, electrooptical, and microwave performance characteristics of the fundamental building-block PIC elements designed to be as simple and process-tolerant as possible, with particular emphasis placed on reducing optical insertion loss. Relatively conventional device array and circuit designs were built using these PIC elements: (1) to establish a baseline performance standard; (2) to assess the impact of epitaxial growth accuracy and uniformity, and of fabrication uniformity and yield; (3) to validate our theoretical and numerical models; and (4) to resolve the optical and microwave packaging issues associated with building fully packaged prototypes. Novel and more complex PIC designs and fabrication processes, viewed as higher payoff but higher risk, were explored in a parallel effort with the intention of meshing those advances into our baseline higher-yield capability as they mature. The application focus targeted the design and fabrication of packaged solitary modulators meeting the requirements of future wideband and high-speed analog and digital data links. Successfully prototyped devices are expected to feed into more complex PICs solving specific problems in high-performance communications, such as optical beamforming networks for phased array antennas.

  13. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    De-Hao Lu

    2010-11-01

    Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  14. Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  15. Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

    Directory of Open Access Journals (Sweden)

    Ching-Liang Dai

    2010-03-01

    Full Text Available The study presents a micro carbon monoxide (CO sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively.

  16. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

  17. Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits

    OpenAIRE

    Lun Li; Mitchell Thornton; Stephen Szygenda

    2006-01-01

    The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stages can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses upon a technique that integrates the best characteristics of both simulation and formal verificati...

  18. Multi-octave spectral beam combiner on ultra-broadband photonic integrated circuit platform.

    Science.gov (United States)

    Stanton, Eric J; Heck, Martijn J R; Bovington, Jock; Spott, Alexander; Bowers, John E

    2015-05-04

    We present the design of a novel platform that is able to combine optical frequency bands spanning 4.2 octaves from ultraviolet to mid-wave infrared into a single, low M2 output waveguide. We present the design and realization of a key component in this platform that combines the wavelength bands of 350 nm - 1500 nm and 1500 nm - 6500 nm with demonstrated efficiency greater than 90% in near-infrared and mid-wave infrared. The multi-octave spectral beam combiner concept is realized using an integrated platform with silicon nitride waveguides and silicon waveguides. Simulated bandwidth is shown to be over four octaves, and measured bandwidth is shown over two octaves, limited by the availability of sources.

  19. Development of high speed integrated circuit for very high resolution timing measurements

    Energy Technology Data Exchange (ETDEWEB)

    Mester, Christian

    2009-10-15

    A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described. The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40 MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption. (orig.)

  20. Thick soi films by rapid thermal processing for high voltage integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Dilhac, J.M.; Cornibert, L.; Charitat, G.; Nolhier, N.; Zerrouk, D.; Ganibal, C.

    1997-05-01

    A structure for electrical insulation of control devices used in high voltage integrated circuits, is presented, combining junction and dielectric insulation for vertical and lateral insulation respectively. The insulation performances are first theoretically assessed to estimate the required oxide thickness; then, a method for creating the buried oxide layer is presented and experimentally verified; the method consists in re-crystallizing thick polysilicon films by Lateral Epitaxial Growth over Oxide (LEGO) in order to fabricate substrates with localized SOI (silicon on insulator) layers, and avoids any horizontal thermal gradient in the solid phase and therefore produces less defects, while allowing the formation of much thicker films than in any other melt-based technique

  1. Near-IR Spectral Imaging of Semiconductor Absorption Sites in Integrated Circuits

    Directory of Open Access Journals (Sweden)

    E. C. Samson

    2004-12-01

    Full Text Available We derive spectral maps of absorption sites in integrated circuits (ICs by varying the wavelength of the optical probe within the near-IR range. This method has allowed us to improve the contrast of the acquired images by revealing structures that have a different optical absorption from neighboring sites. A false color composite image from those acquired at different wavelengths is generated from which the response of each semiconductor structure can be deduced. With the aid of the spectral maps, nonuniform absorption was also observed in a semiconductor structure located near an electrical overstress defect. This method may prove important in failure analysis of ICs by uncovering areas exhibiting anomalous absorption, which could improve localization of defective edifices in the semiconductor parts of the microchip

  2. Vapor-solid-solid grown Ge nanowires at integrated circuit compatible temperature by molecular beam epitaxy

    Science.gov (United States)

    Zhu, Zhongyunshen; Song, Yuxin; Zhang, Zhenpu; Sun, Hao; Han, Yi; Li, Yaoyao; Zhang, Liyao; Xue, Zhongying; Di, Zengfeng; Wang, Shumin

    2017-09-01

    We demonstrate Au-assisted vapor-solid-solid (VSS) growth of Ge nanowires (NWs) by molecular beam epitaxy at the substrate temperature of ˜180 °C, which is compatible with the temperature window for Si-based integrated circuit. Low temperature grown Ge NWs hold a smaller size, similar uniformity, and better fit with Au tips in diameter, in contrast to Ge NWs grown at around or above the eutectic temperature of Au-Ge alloy in the vapor-liquid-solid (VLS) growth. Six ⟨110⟩ growth orientations were observed on Ge (110) by the VSS growth at ˜180 °C, differing from only one vertical growth direction of Ge NWs by the VLS growth at a high temperature. The evolution of NWs dimension and morphology from the VLS growth to the VSS growth is qualitatively explained by analyzing the mechanism of the two growth modes.

  3. A study on the recycling of scrap integrated circuits by leaching.

    Science.gov (United States)

    Lee, Ching-Hwa; Tang, Li-Wen; Popuri, Srinivasa R

    2011-07-01

    In order to minimize the problem of pollution and to conserve limited natural resources, a method to recover the valuable metals such as gold, silver and copper) present in the scrap integrated circuits (ICs) was developed in the present study. Roasting, grinding, screening, magnetic separation, melting and leaching were adopted to investigate the efficiency of recovery of gold, silver and copper from scrap ICs. The collected scrap IC samples were roasted at 850 °C to destroy their plastic resin sealing material, followed by screening and magnetic separation to separate the metals from the resin residue. The non-ferrous materials (0.840 mm) were mainly composed of copper and could be melted into a copper alloy. Non-ferrous materials containing gold (860.05 ppm), silver (1323.12 ppm) and copper (37259.7 ppm) (size less than 50 mesh) were recovered 100% by a leaching process and thiourea was used as a leaching reagent.

  4. An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement

    Science.gov (United States)

    Muyskens, Mark

    1997-07-01

    Our application of an integrated-circuit (IC) temperature sensor which is easy-to-use, inexpensive, rugged, easily computer-interfacable and has good precision is described. The design, based on the National Semiconductor LM35 IC chip, avoids some of the difficulties associated with conventional sensors (thermocouples, thermistors, and platinum resistance thermometers) and a previously described IC sensor. The sensor can be used with a variety of data-acquisition systems. Applications range from general chemistry to physical chemistry, particularly where computer interfaced, digital temperature measurement is desired. Included is a detailed description of our current design with suggestions for improvement and a performance evaluation of the precision in differential measurement and the time constant for responding to temperature change.

  5. Respiration detection chip with integrated temperature-insensitive MEMS sensors and CMOS signal processing circuits.

    Science.gov (United States)

    Wei, Chia-Ling; Lin, Yu-Chen; Chen, Tse-An; Lin, Ren-Yi; Liu, Tin-Hao

    2015-02-01

    An airflow sensing chip, which integrates MEMS sensors with their CMOS signal processing circuits into a single chip, is proposed for respiration detection. Three micro-cantilever-based airflow sensors were designed and fabricated using a 0.35 μm CMOS/MEMS 2P4M mixed-signal polycide process. Two main differences were present among these three designs: they were either metal-covered or metal-free structures, and had either bridge-type or fixed-type reference resistors. The performances of these sensors were measured and compared, including temperature sensitivity and airflow sensitivity. Based on the measured results, the metal-free structure with fixed-type reference resistors is recommended for use, because it has the highest airflow sensitivity and also can effectively reduce the output voltage drift caused by temperature change.

  6. INTEGRATED CIRCUITS FROM MOBILE PHONES AS POSSIBLE EMERGENCY OSL/TL DOSIMETERS.

    Science.gov (United States)

    Sholom, S; McKeever, S W S

    2016-09-01

    In this article, optically stimulated luminescence (OSL) data are presented from integrated circuits (ICs) extracted from mobile phones. The purpose is to evaluate the potential of using OSL from components in personal electronic devices such as smart phones as a means of emergency dosimetry in the event of a large-scale radiological incident. ICs were extracted from five different makes and models of mobile phone. Sample preparation procedures are described, and OSL from the IC samples following irradiation using a (90)Sr/(90)Y source is presented. Repeatability, sensitivity, dose responses, minimum measureable doses, stability and fading data were examined and are described. A protocol for measuring absorbed dose is presented, and it was concluded that OSL from these components is a viable method for assessing dose in the days following a radiological incident. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

  7. High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

    Science.gov (United States)

    Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

    2015-08-12

    Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

  8. Low-loss compact multilayer silicon nitride platform for 3D photonic integrated circuits.

    Science.gov (United States)

    Shang, Kuanping; Pathak, Shibnath; Guan, Binbin; Liu, Guangyao; Yoo, S J B

    2015-08-10

    We design, fabricate, and demonstrate a silicon nitride (Si(3)N(4)) multilayer platform optimized for low-loss and compact multilayer photonic integrated circuits. The designed platform, with 200 nm thick waveguide core and 700 nm interlayer gap, is compatible for active thermal tuning and applicable to realizing compact photonic devices such as arrayed waveguide gratings (AWGs). We achieve ultra-low loss vertical couplers with 0.01 dB coupling loss, multilayer crossing loss of 0.167 dB at 90° crossing angle, 50 μm bending radius, 100 × 2 μm(2) footprint, lateral misalignment tolerance up to 400 nm, and less than -52 dB interlayer crosstalk at 1550 nm wavelength. Based on the designed platform, we demonstrate a 27 × 32 × 2 multilayer star coupler.

  9. Rapidly reconfigurable high-fidelity optical arbitrary waveform generation in heterogeneous photonic integrated circuits.

    Science.gov (United States)

    Feng, Shaoqi; Qin, Chuan; Shang, Kuanping; Pathak, Shibnath; Lai, Weicheng; Guan, Binbin; Clements, Matthew; Su, Tiehui; Liu, Guangyao; Lu, Hongbo; Scott, Ryan P; Ben Yoo, S J

    2017-04-17

    This paper demonstrates rapidly reconfigurable, high-fidelity optical arbitrary waveform generation (OAWG) in a heterogeneous photonic integrated circuit (PIC). The heterogeneous PIC combines advantages of high-speed indium phosphide (InP) modulators and low-loss, high-contrast silicon nitride (Si3N4) arrayed waveguide gratings (AWGs) so that high-fidelity optical waveform syntheses with rapid waveform updates are possible. The generated optical waveforms spanned a 160 GHz spectral bandwidth starting from an optical frequency comb consisting of eight comb lines separated by 20 GHz channel spacing. The Error Vector Magnitude (EVM) values of the generated waveforms were approximately 16.4%. The OAWG module can rapidly and arbitrarily reconfigure waveforms upon every pulse arriving at 2 ns repetition time. The result of this work indicates the feasibility of truly dynamic optical arbitrary waveform generation where the reconfiguration rate or the modulator bandwidth must exceed the channel spacing of the AWG and the optical frequency comb.

  10. High-fidelity quantum state evolution in imperfect photonic integrated circuits

    Science.gov (United States)

    Mower, Jacob; Harris, Nicholas C.; Steinbrecher, Gregory R.; Lahini, Yoav; Englund, Dirk

    2015-09-01

    We propose and analyze the design of a programmable photonic integrated circuit for high-fidelity quantum computation and simulation. We demonstrate that the reconfigurability of our design allows us to overcome two major impediments to quantum optics on a chip: it removes the need for a full fabrication cycle for each experiment and allows for compensation of fabrication errors using numerical optimization techniques. Under a pessimistic fabrication model for the silicon-on-insulator process, we demonstrate a dramatic fidelity improvement for the linear optics controlled-not and controlled-phase gates and, showing the scalability of this approach, the iterative phase estimation algorithm built from individually optimized gates. We also propose and simulate an experiment that the programmability of our system would enable: a statistically robust study of the evolution of entangled photons in disordered quantum walks. Overall, our results suggest that existing fabrication processes are sufficient to build a quantum photonic processor capable of high-fidelity operation.

  11. Reducing image noise in computed tomography (CT) colonography: effect of an integrated circuit CT detector.

    Science.gov (United States)

    Liu, Yu; Leng, Shuai; Michalak, Gregory J; Vrieze, Thomas J; Duan, Xinhui; Qu, Mingliang; Shiung, Maria M; McCollough, Cynthia H; Fletcher, Joel G

    2014-01-01

    To investigate whether the integrated circuit (IC) detector results in reduced noise in computed tomography (CT) colonography (CTC). Three hundred sixty-six consecutive patients underwent clinically indicated CTC using the same CT scanner system, except for a difference in CT detectors (IC or conventional). Image noise, patient size, and scanner radiation output (volume CT dose index) were quantitatively compared between patient cohorts using each detector system, with separate comparisons for the abdomen and pelvis. For the abdomen and pelvis, despite significantly larger patient sizes in the IC detector cohort (both P noise was significantly lower (both P 0.18). Based on the observed image noise reduction, radiation dose could alternatively be reduced by approximately 20% to result in similar levels of image noise. Computed tomography colonography images acquired using the IC detector had significantly lower noise than images acquired using the conventional detector. This noise reduction can permit further radiation dose reduction in CTC.

  12. SEMICONDUCTOR INTEGRATED CIRCUITS: Design and noise analysis of a sigma-delta capacitive micromachined accelerometer

    Science.gov (United States)

    Yuntao, Liu; Xiaowei, Liu; Weiping, Chen; Qun, Wu

    2010-05-01

    A single-loop fourth-order sigma-delta (σ Δ) interface circuit for a closed-loop micromachined accelerometer is presented. Two additional electronic integrators are cascaded with the micromachined sensing element to form a fourth-order loop filter. The three main noise sources affecting the overall system resolution of a σ Δ accelerometer, mechanical noise, electronic noise and quantization noise, are analyzed in detail. Accurate mathematical formulas for electronic and quantization noise are established. The ASIC is fabricated in a 0.5 μm two-metal two-poly n-well CMOS process. The test results indicate that the mechanical noise and electronic noise are 1 μg/√Hz and 8 μV/√Hz respectively, and the theoretical models of electronic and quantization noise agree well with the test and simulation results.

  13. Black Box Model of Integrated Circuits for ESD Behavioral Simulation and Industrial Application Case

    Directory of Open Access Journals (Sweden)

    F. Lafon

    2015-11-01

    Full Text Available In order to design electronic products for Electro Static Discharges constraints, the use of simulation is fundamental. This is the only solution to justify the design and to manage properly the margin during the development. In order to do so, models are required and especially for the integrated circuits (IC. A Pspice model had been developed and validated for ESD performance prediction of IC implemented inside an electronic product. Nevertheless, the practical implementation of these modeling techniques for IC induced some issues, especially under Pspice, being the targeted tool for our simulation. Divergences issues during time domain simulation were frequently observed and sometimes irresolvable with model previously proposed. We propose in this article new implementation techniques in Pspice. A practical example is used to demonstrate the capability of our model.

  14. Micro-fabricated integrated coil and magnetic circuit and method of manufacturing thereof

    Science.gov (United States)

    Mihailovich, Robert E.; Papavasiliou, Alex P.; Mehrotra, Vivek; Stupar, Philip A.; Borwick, III, Robert L.; Ganguli, Rahul; DeNatale, Jeffrey F.

    2017-03-28

    A micro-fabricated electromagnetic device is provided for on-circuit integration. The electromagnetic device includes a core. The core has a plurality of electrically insulating layers positioned alternatingly between a plurality of magnetic layers to collectively form a continuous laminate having alternating magnetic and electrically insulating layers. The electromagnetic device includes a coil embedded in openings of the semiconductor substrate. An insulating material is positioned in the cavity and between the coil and an inner surface of the core. A method of manufacturing the electromagnetic device includes providing a semiconductor substrate having openings formed therein. Windings of a coil are electroplated and embedded in the openings. The insulating material is coated on or around an exposed surface of the coil. Alternating magnetic layers and electrically insulating layers may be micro-fabricated and electroplated as a single and substantially continuous segment on or around the insulating material.

  15. Coupling molecular spin centers to microwave planar resonators: towards integration of molecular qubits in quantum circuits.

    Science.gov (United States)

    Bonizzoni, C; Ghirri, A; Bader, K; van Slageren, J; Perfetti, M; Sorace, L; Lan, Y; Fuhr, O; Ruben, M; Affronte, M

    2016-11-14

    We present spectroscopic measurements looking for the coherent coupling between molecular magnetic centers and microwave photons. The aim is to find the optimal conditions and the best molecular features to achieve the quantum strong coupling regime, for which coherent dynamics of hybrid photon-spin states take place. To this end, we used a high critical temperature YBCO superconducting planar resonator working at 7.7 GHz and at low temperatures to investigate three molecular mononuclear coordination compounds, namely (PPh4)2[Cu(mnt)2] (where mnt2- = maleonitriledithiolate), [ErPc2]-TBA+ (where pc2- is the phtalocyaninato and TBA+ is the tetra-n-butylammonium cation) and Dy(trensal) (where H3trensal = 2,2',2''-tris(salicylideneimino)triethylamine). Although the strong coupling regime was not achieved in these preliminary experiments, the results provided several hints on how to design molecular magnetic centers to be integrated into hybrid quantum circuits.

  16. Rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC)

    Science.gov (United States)

    Li, Xiuling; Huang, Wen

    2015-04-28

    A rolled-up transmission line structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis, where the multilayer sheet comprises a conductive pattern layer on a strain-relieved layer. The conductive pattern layer comprises a first conductive film and a second conductive film separated from the first conductive film in a rolling direction. In the rolled configuration, the first conductive film surrounds the longitudinal axis, and the second conductive film surrounds the first conductive film. The first conductive film serves as a signal line and the second conductive film serves as a conductive shield for the rolled-up transmission line structure.

  17. Reduction of EMC Emissions in Mixed Signal Integrated Circuits with Embedded LIN Driver

    Directory of Open Access Journals (Sweden)

    P. Hartl

    2016-06-01

    Full Text Available This paper describes several methods for reduction of electromagnetic emissions (EME of mixed signal integrated circuits (IC. The focus is on the impact that a LIN bus communication block has on a complex IC which contains analog blocks, noisy digital block, micro-core (µC and several types of memories. It is used in an automotive environment, where EMC emission reduction is one of the key success factors. Several proposed methods for EME reduction are described and implemented on three test chips. These methods include current consumption reduction, internal on-chip decoupling, ground separation and different linear voltage regulator topologies. Measurement results of several fabricated test chips are shown and discussed.

  18. Data traffic performance of an integrated circuit- and packet-switched multiplex structure

    Science.gov (United States)

    Weinstein, C. J.; Malpass, M. L.; Fisher, M. J.

    1980-06-01

    Results are developed for data traffic performance in an integrated multiplex structure which includes circuit-switching for voice and packet-switching for data. The results are obtained both through simulation and analysis, and show that excessive data queues and delays will build up under heavy loading conditions. These large data delays occur during periods of time when the voice traffic load through the multiplexer exceeds its statistical average. A variety of flow control mechanisms to reduce data packet delays are investigated. These mechanisms include control of voice bit rate, limitation of the data buffer, and combinations of voice rate and data buffer control. Simulations indicate that these flow control mechanisms provide substantial improvements in system performance.

  19. High-resolution non-destructive three-dimensional imaging of integrated circuits.

    Science.gov (United States)

    Holler, Mirko; Guizar-Sicairos, Manuel; Tsai, Esther H R; Dinapoli, Roberto; Müller, Elisabeth; Bunk, Oliver; Raabe, Jörg; Aeppli, Gabriel

    2017-03-15

    Modern nanoelectronics has advanced to a point at which it is impossible to image entire devices and their interconnections non-destructively because of their small feature sizes and the complex three-dimensional structures resulting from their integration on a chip. This metrology gap implies a lack of direct feedback between design and manufacturing processes, and hampers quality control during production, shipment and use. Here we demonstrate that X-ray ptychography-a high-resolution coherent diffractive imaging technique-can create three-dimensional images of integrated circuits of known and unknown designs with a lateral resolution in all directions down to 14.6 nanometres. We obtained detailed device geometries and corresponding elemental maps, and show how the devices are integrated with each other to form the chip. Our experiments represent a major advance in chip inspection and reverse engineering over the traditional destructive electron microscopy and ion milling techniques. Foreseeable developments in X-ray sources, optics and detectors, as well as adoption of an instrument geometry optimized for planar rather than cylindrical samples, could lead to a thousand-fold increase in efficiency, with concomitant reductions in scan times and voxel sizes.

  20. Hybrid integration of laser source on silicon photonic integrated circuit for low-cost interferometry medical device

    Science.gov (United States)

    Duperron, Matthieu; Carroll, Lee; Rensing, Marc; Collins, Sean; Zhao, Yan; Li, Yanlu; Baets, Roel; O'Brien, Peter

    2017-02-01

    The cost-effective integration of laser sources on Silicon Photonic Integrated Circuits (Si-PICs) is a key challenge to realizing the full potential of on-chip photonic solutions for telecommunication and medical applications. Hybrid integration can offer a route to high-yield solutions, using only known-good laser-chips, and simple freespace micro-optics to transport light from a discrete laser-diode to a grating-coupler on the Si-PIC. In this work, we describe a passively assembled micro-optical bench (MOB) for the hybrid integration of a 1550nm 20MHz linewidth laser-diode on a Si-PIC, developed for an on-chip interferometer based medical device. A dual-lens MOB design minimizes aberrations in the laser spot transported to the standard grating-coupler (15 μm x 12 μm) on the Si-PIC, and facilitates the inclusion of a sub-millimeter latched-garnet optical-isolator. The 20dB suppression from the isolator helps ensure the high-frequency stability of the laser-diode, while the high thermal conductivity of the AlN submount (300/W=m.°C), and the close integration of a micro-bead thermistor, ensure the stable and efficient thermo-electric cooling of the laser-diode, which helps minimise low-frequency drift during the approximately 15s of operation needed for the point-of-care measurement. The dual-lens MOB is compatible with cost-effective passively-aligned mass-production, and can be optimised for alternative PIC-based applications.

  1. Inter digital transducer modelling through Mason equivalent circuit model

    DEFF Research Database (Denmark)

    Mishra, Dipti; Singh, Abhishek; Hussain, Dil muhammed Akbar

    2016-01-01

    The frequency reliance of inter-digital transducer is analyzed with the help of MASON's Equivalent circuit which is based on Smith's Equivalent circuit which is further based on Foster's Network. An inter-digital transducer has been demonstrated as a RLC network. The circuit is simulated by Simul......The frequency reliance of inter-digital transducer is analyzed with the help of MASON's Equivalent circuit which is based on Smith's Equivalent circuit which is further based on Foster's Network. An inter-digital transducer has been demonstrated as a RLC network. The circuit is simulated...... by Simulation program with Integrated Circuit Emphasis (HSPICE), a well-liked electronic path simulator. The acoustic wave devices are not suitable to simulation through circuit simulator. In this paper, an electrical model of Mason's Equivalent electrical circuit for an inter-digital transducer (IDT...

  2. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    Science.gov (United States)

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

  3. Study of an automatic readout integrated circuit for the signal shaping of the ATLAS electromagnetic calorimeter; Etude d`un circuit integre de commutation automatique de gain pour le circuit de mise en forme du signal du calorimetre electromagnetique d`ATLAS

    Energy Technology Data Exchange (ETDEWEB)

    Bussat, J.M. [Laboratoire d`Annecy-le-Vieux de Physique des Particules, 74 - Annecy-le-Vieux (France)

    1996-12-01

    This paper describes the present state of the development of an automatic readout integrated circuit that can be used, connected to the four gain shaper of LAL, at the ATLAS electromagnetic calorimeter.

  4. Vertically integrated logic circuits constructed using ZnO-nanowire-based field-effect transistors on plastic substrates.

    Science.gov (United States)

    Kang, Jeongmin; Moon, Taeho; Jeon, Youngin; Kim, Hoyoung; Kim, Sangsig

    2013-05-01

    ZnO-nanowire-based logic circuits were constructed by the vertical integration of multilayered field-effect transistors (FETs) on plastic substrates. ZnO nanowires with an average diameter of -100 nm were synthesized by thermal chemical vapor deposition for use as the channel material in FETs. The ZnO-based FETs exhibited a high I(ON)/I(OFF) of > 10(6), with the characteristic of n-type depletion modes. For vertically integrated logic circuits, three multilayer FETs were sequentially prepared. The stacked FETs were connected in series via electrodes, and C-PVPs were used for the layer-isolation material. The NOT and NAND gates exhibited large logic-swing values of -93%. These results demonstrate the feasibility of three dimensional flexible logic circuits.

  5. Neural Circuits for Peristaltic Wave Propagation in Crawling Drosophila Larvae: Analysis and Modeling

    Directory of Open Access Journals (Sweden)

    Julijana eGjorgjieva

    2013-04-01

    Full Text Available Drosophila larvae crawl by peristaltic waves of muscle contractions, which propagate along the animal body and involve the simultaneous contraction of the left and right side of each segment. Coordinated propagation of contraction does not require sensory input, suggesting that movement is generated by a central pattern generator (CPG. We characterized crawling behavior of newly hatched Drosophila larvae by quantifying timing and duration of segmental boundary contractions. We developed a CPG network model that recapitulates these patterns based on segmentally repeated units of excitatory and inhibitory neuronal populations coupled with immediate neighboring segments. A single network with symmetric coupling between neighboring segments succeeded in generating both forward and backward propagation of activity. The CPG network was robust to changes in amplitude and variability of connectivity strength. Introducing sensory feedback via `stretch-sensitive' neurons improved wave propagation properties such as speed of propagation and segmental contraction duration as observed experimentally. Sensory feedback also restored propagating activity patterns when an inappropriately tuned CPG network failed to generate waves. Finally, in a two-sided CPG model we demonstrated that two types of connectivity could synchronize the activity of two independent networks: connections from excitatory neurons on one side to excitatory contralateral neurons (E to E, and connections from inhibitory neurons on one side to excitatory contralateral neurons (I to E. To our knowledge, such I to E connectivity has not yet been found in any experimental system; however, it provides the most robust mechanism to synchronize activity between contralateral CPGs in our model. Our model provides a general framework for studying the conditions under which a single locally coupled network generates bilaterally synchronized and longitudinally propagating waves in either direction.

  6. Two-Dimensional Metal-Free Organic Multiferroic Material for Design of Multifunctional Integrated Circuits.

    Science.gov (United States)

    Tu, Zhengyuan; Wu, Menghao; Zeng, Xiao Cheng

    2017-05-04

    Coexistence of ferromagnetism and ferroelectricity in a single 2D material is highly desirable for integration of multifunctional units in 2D material-based circuits. We report theoretical evidence of C6N8H organic network as being the first 2D organic multiferroic material with coexisting ferromagnetic and ferroelectric properties. The ferroelectricity stems from multimode proton-transfer within the 2D C6N8H network, in which a long-range proton-transfer mode is enabled by the facilitation of oxygen molecule when the network is exposed to the air. Such oxygen-assisted ferroelectricity also leads to a high Curie temperature and coupling between ferroelectricity and ferromagnetism. We also find that hydrogenation and carbon doping can transform the 2D g-C3N4 network from an insulator to an n-type/p-type magnetic semiconductor with modest bandgap. Akin to the dopant induced n/p channels in silicon wafer, a variety of dopant created functional units can be integrated into the g-C3N4 wafer by design for nanoelectronic applications.

  7. Measurement of the Boltzmann constant by Johnson noise thermometry using a superconducting integrated circuit

    Science.gov (United States)

    Urano, C.; Yamazawa, K.; Kaneko, N.-H.

    2017-12-01

    We report on our measurement of the Boltzmann constant by Johnson noise thermometry (JNT) using an integrated quantum voltage noise source (IQVNS) that is fully implemented with superconducting integrated circuit technology. The IQVNS generates calculable pseudo white noise voltages to calibrate the JNT system. The thermal noise of a sensing resistor placed at the temperature of the triple point of water was measured precisely by the IQVNS-based JNT. We accumulated data of more than 429 200 s in total (over 6 d) and used the Akaike information criterion to estimate the fitting frequency range for the quadratic model to calculate the Boltzmann constant. Upon detailed evaluation of the uncertainty components, the experimentally obtained Boltzmann constant was k=1.380 6436× {{10}-23} J K-1 with a relative combined uncertainty of 10.22× {{10}-6} . The value of k is relatively -3.56× {{10}-6} lower than the CODATA 2014 value (Mohr et al 2016 Rev. Mod. Phys. 88 035009).

  8. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

    CERN Document Server

    Lim, Sung Kyu

    2013-01-01

    This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits.  It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs.  Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process. Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability. Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the e...

  9. Low-power analog integrated circuits for wireless ECG acquisition systems.

    Science.gov (United States)

    Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

    2012-09-01

    This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

  10. Soft, smart contact lenses with integrations of wireless circuits, glucose sensors, and displays.

    Science.gov (United States)

    Park, Jihun; Kim, Joohee; Kim, So-Yun; Cheong, Woon Hyung; Jang, Jiuk; Park, Young-Geun; Na, Kyungmin; Kim, Yun-Tae; Heo, Jun Hyuk; Lee, Chang Young; Lee, Jung Heon; Bien, Franklin; Park, Jang-Ung

    2018-01-01

    Recent advances in wearable electronics combined with wireless communications are essential to the realization of medical applications through health monitoring technologies. For example, a smart contact lens, which is capable of monitoring the physiological information of the eye and tear fluid, could provide real-time, noninvasive medical diagnostics. However, previous reports concerning the smart contact lens have indicated that opaque and brittle components have been used to enable the operation of the electronic device, and this could block the user's vision and potentially damage the eye. In addition, the use of expensive and bulky equipment to measure signals from the contact lens sensors could interfere with the user's external activities. Thus, we report an unconventional approach for the fabrication of a soft, smart contact lens in which glucose sensors, wireless power transfer circuits, and display pixels to visualize sensing signals in real time are fully integrated using transparent and stretchable nanostructures. The integration of this display into the smart lens eliminates the need for additional, bulky measurement equipment. This soft, smart contact lens can be transparent, providing a clear view by matching the refractive indices of its locally patterned areas. The resulting soft, smart contact lens provides real-time, wireless operation, and there are in vivo tests to monitor the glucose concentration in tears (suitable for determining the fasting glucose level in the tears of diabetic patients) and, simultaneously, to provide sensing results through the contact lens display.

  11. Synaptic and intrinsic homeostasis cooperate to optimize single neuron response properties and tune integrator circuits

    Science.gov (United States)

    2016-01-01

    Homeostatic processes that provide negative feedback to regulate neuronal firing rate are essential for normal brain function, and observations suggest that multiple such processes may operate simultaneously in the same network. We pose two questions: why might a diversity of homeostatic pathways be necessary, and how can they operate in concert without opposing and undermining each other? To address these questions, we perform a computational and analytical study of cell-intrinsic homeostasis and synaptic homeostasis in single-neuron and recurrent circuit models. We demonstrate analytically and in simulation that when two such mechanisms are controlled on a long time scale by firing rate via simple and general feedback rules, they can robustly operate in tandem to tune the mean and variance of single neuron's firing rate to desired goals. This property allows the system to recover desired behavior after chronic changes in input statistics. We illustrate the power of this homeostatic tuning scheme by using it to regain high mutual information between neuronal input and output after major changes in input statistics. We then show that such dual homeostasis can be applied to tune the behavior of a neural integrator, a system that is notoriously sensitive to variation in parameters. These results are robust to variation in goals and model parameters. We argue that a set of homeostatic processes that appear to redundantly regulate mean firing rate may work together to control firing rate mean and variance and thus maintain performance in a parameter-sensitive task such as integration. PMID:27306675

  12. Radiation effects for high-energy protons and X-ray in integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Silveira, M.A.G.; Santos, R.B.B. [Centro Universitario da FEI, Sao Bernardo do Campo, SP (Brazil); Medina, N.H.; Added, N.; Tabacniks, M.H. [Universidade de Sao Paulo (IF/USP), SP (Brazil). Inst. de Fisica; Lima, J.A. de [Universidade Federal de Santa Catarina (UFSC), Florianopolis, SC (Brazil); Cirne, K.H. [Empresa Brasileira de Aeronautica S.A. (EMBRAER), Sao Jose dos Campos, SP (Brazil)

    2012-07-01

    Full text: Electronic circuits are strongly influenced by ionizing radiation. The necessity to develop integrated circuits (IC's) featuring radiation hardness is largely growing to meet the stringent environment in space electronics [1]. This work aims to development a test platform to qualify electronic devices under the influence of high radiation dose, for aerospace applications. To understand the physical phenomena responsible for changes in devices exposed to ionizing radiation several kinds of radiation should then be considered, among them heavy ions, alpha particles, protons, gamma and X-rays. Radiation effects on the ICs are usually divided into three categories: Total Ionizing Dose (TID), a cumulative dose that shifts the threshold voltage and increases transistor's off-state current; Single Events Effects (SEE), a transient effect which can deposit charge directly into the device and disturb the properties of electronic circuits and Displacement Damage (DD) which can change the arrangement of the atoms in the lattice [2]. In this study we are investigating the radiation effects in rectangular-gate and circular-gate MOSFETs, manufactured with standard CMOS fabrication process, using particle beams produced in electrostatic tandem accelerators and X-rays. Initial tests for TID effects were performed using the 1.7 MV 5SDH tandem Pelletron accelerator of the Instituto de Fisica da USP with a proton beam of 2.6 MeV. The devices were exposed to different doses, varying the beam current, and irradiation time with the accumulated dose reaching up to Grad. To study the effect of X-rays on the electronic devices, an XRD-7000 (Shimadzu) X-ray setup was used as a primary X-ray source. The devices were irradiated with a total dose from krad to Grad using different dose rates. The results indicate that changes of the I-V characteristic curve are strongly dependents on the geometry of the devices. [1] Duzellier, S., Aerospace Science and Technology 9, p. 93

  13. Inkjet-printing-based soft-etching technique for high-speed polymer ambipolar integrated circuits.

    Science.gov (United States)

    Khim, Dongyoon; Baeg, Kang-Jun; Kang, Minji; Lee, Seung-Hoon; Kim, Nam-Koo; Kim, Jihong; Lee, Geon-Woong; Liu, Chuan; Kim, Dong-Yu; Noh, Yong-Young

    2013-12-11

    Here, we report the so-called soft-etching process based on an inkjet-printing technique for realizing high-performance printed and flexible organic electronic circuits with conjugated polymer semiconductors. The soft-etching process consists of selective etching of the gate made of a dielectric polymer and deposition of another gate dielectric layer. The method enables the use of a more desirable polymer dielectric layer for the p-channel and n-channel organic field-effect transistors (OFETs) in complementary integrated circuits. We fabricated high-performance ambipolar complementary inverters and ring oscillators (ROs) using poly([N,N'-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5'-(2,2'-bithiophene)) (P(NDI2OD-T2)) as the active layer as well as poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and polystyrene ((PS)/P(VDF-TrFE)) as dielectric materials for the p-channel (pull-up transistor) and n-channel (pull-down transistor) OFETs, respectively. The PS dielectric polymer was selectively etched by inkjetting of n-butyl acetate as an orthogonal solvent for P(NDI2OD-T2). Employing this methodology, the five-stage ambipolar ROs with P(NDI2OD-T2) exhibited an oscillation frequency of ∼16.7 kHz, which was much higher than that of non-soft-etched ROs with a single dielectric layer (P(VDF-TrFE); ∼3 kHz).

  14. Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

    Science.gov (United States)

    Spry, David; Neudeck, Phil; Chen, Liangyu; Chang, Carl; Lukco, Dorothy; Beheim, Glenn M

    2016-01-01

    We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

  15. An Integrated Circuit for Simultaneous Extracellular Electrophysiology Recording and Optogenetic Neural Manipulation.

    Science.gov (United States)

    Chen, Chang Hao; McCullagh, Elizabeth A; Pun, Sio Hang; Mak, Peng Un; Vai, Mang I; Mak, Pui In; Klug, Achim; Lei, Tim C

    2017-03-01

    The ability to record and to control action potential firing in neuronal circuits is critical to understand how the brain functions. The objective of this study is to develop a monolithic integrated circuit (IC) to record action potentials and simultaneously control action potential firing using optogenetics. A low-noise and high input impedance (or low input capacitance) neural recording amplifier is combined with a high current laser/light-emitting diode (LED) driver in a single IC. The low input capacitance of the amplifier (9.7 pF) was achieved by adding a dedicated unity gain stage optimized for high impedance metal electrodes. The input referred noise of the amplifier is [Formula: see text], which is lower than the estimated thermal noise of the metal electrode. Thus, the action potentials originating from a single neuron can be recorded with a signal-to-noise ratio of at least 6.6. The LED/laser current driver delivers a maximum current of 330 mA, which is adequate for optogenetic control. The functionality of the IC was tested with an anesthetized Mongolian gerbil and auditory stimulated action potentials were recorded from the inferior colliculus. Spontaneous firings of fifth (trigeminal) nerve fibers were also inhibited using the optogenetic protein Halorhodopsin. Moreover, a noise model of the system was derived to guide the design. A single IC to measure and control action potentials using optogenetic proteins is realized so that more complicated behavioral neuroscience research and the translational neural disorder treatments become possible in the future.

  16. Inclusion of Body-Bias Effect in SPICE Modeling of 4H-SiC Integrated Circuit Resistors

    Science.gov (United States)

    Neudeck, Philip G.

    2017-01-01

    The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500 C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

  17. An amplitude-channel hodoscope based on programmable logic integral circuits for the Baksan Underground Scintillation Telescope

    NARCIS (Netherlands)

    Yanin, AF; Kompaniets, KG; Amel'chakov, MB; Gorbacheva, EA; Dzaparova, IM; Kindin, VV; Novosel'tsev, YF; Striganov, PS

    2004-01-01

    A schematic diagram of a hodoscope with 3200 amplitude channels is described. The hodoscope is based on state-of-the-art programmable logic integral circuits (PLICs). Thanks to the use of PLICs, it is capable of measuring the lengths of input signals in each channel and monitoring their shape. In

  18. Wireless transceiver circuits system perspectives and design aspects

    CERN Document Server

    Rhee, Woogeun

    2015-01-01

    This cutting-edge work contains comprehensive coverage of integrated circuit (IC) design for modern transceiver circuits and wireless systems. Ranging in scope from system perspectives to practical circuit design for emerging wireless applications, the book includes detailed discussions of transceiver architectures and system parameters, mm-wave circuits, ultra-low-power radios for biomedical and sensor applications, and the latest circuit techniques. Written by renowned international experts in IC industry and academia, the text is an ideal reference for engineers and researchers in the area

  19. Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

    Science.gov (United States)

    Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

    2011-01-01

    Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

  20. Continuous-Wave Single-Photon Transistor Based on a Superconducting Circuit

    DEFF Research Database (Denmark)

    Kyriienko, Oleksandr; Sørensen, Anders Søndberg

    2016-01-01

    We propose a microwave frequency single-photon transistor which can operate under continuous wave probing and represents an efficient single microwave photon detector. It can be realized using an impedance matched system of a three level artificial ladder-type atom coupled to two microwave cavities...... and the appearance of a photon flux leaving the second cavity through a separate input-output port. The proposal does not require time variation of the probe signals, thus corresponding to a passive version of a single-photon transistor. The resulting device is robust to qubit dephasing processes, possesses low dark...

  1. F2-laser microfabrication for integrating optical circuits with microfluidic biochips

    Science.gov (United States)

    Ho, Stephen; Aitchison, J. S.; Eaton, Shane; Herman, Peter R.; Li, Jianzhao

    2004-12-01

    Lasers microprocessing is attractive for the custom fabrication of novel lab-on-a-chip designs. However, processing of glass biochips is challenging for most lasers because of the weak light interactions inherent in such transparent substrates. The F2-laser generates a high 7.9-eV photon energy that drives strong absorption in glasses, while the short 157-nm wavelength offers high-resolution patterning on the 100-nm scale. With these benefits, F2-laser ablation is well suited to the fabrication of high aspect ratio microfluidic channels and other biochip functions. F2-laser radiation also produces a strong photosensitivity response in fused silica and other glasses that enable the fabrication of buried optical waveguides, Bragg grating filters and other refractive index structures inside the glass. In this paper, we combine laser micromachining and refractive index profiling to enable single-step integration of photonic functions with microfluidic functions on a single chip. Optical waveguides were written to intercept microfluidic channels for optical sensing of cells and other bio-materials. An integrated biophotonic sensor is demonstrated for polystyrene spheres. The sensor is optically characterized for insertion loss, propagation loss, and particle sensitivity. The demonstration and analysis of this simple device offers insight into the capabilities and potential applications for laser fabricated glass lab-on-a-chip devices. Moreover, the groundwork is laid for rapid laser prototyping of custom-designed microfluidic biochips interlaced with integrated-optical circuits to define a new generation of highly functional bio-sensor and lab-on-a-chip devices.

  2. On integrable models from pp-wave string backgrounds

    CERN Document Server

    Bakas, Ioannis; Bakas, Ioannis; Sonnenschein, Jacob

    2002-01-01

    We construct solutions of type IIB supergravity with non-trivial Ramond-Ramond 5-form in ten dimensions by replacing the transverse flat space of pp-wave backgrounds with exact $N=(4,4)$ $c=4$ superconformal field theory blocks. These solutions, which also include a dilaton and (in some cases) an anti-symmetric tensor field, lead to integrable models on the world-sheet in the light-cone gauge of string theory. In one instance we demonstrate explicitly the emergence of the complex sine-Gordon model, which coincides with integrable perturbations of the corresponding superconformal building blocks in the transverse space. In other cases we arrive at the supersymmetric Liouville theory or at the complex sine-Liouville model. For axionic instantons in the transverse space, as for the (semi)-wormhole geometry, we obtain an entire class of supersymmetric pp-wave backgrounds by solving the Killing spinor equations as in flat space, supplemented by the appropriate chiral projections; as such, they generalize the usual...

  3. Characterization of Novel Thin-Films and Structures for Integrated Circuit and Photovoltaic Applications

    Science.gov (United States)

    Zhao, Zhao

    Thin films have been widely used in various applications. This research focuses on the characterization of novel thin films in the integrated circuits and photovoltaic techniques. The ion implanted layer in silicon can be treated as ion implanted thin film, which plays an essential role in the integrated circuits fabrication. Novel rapid annealing methods, i.e. microwave annealing and laser annealing, are conducted to activate ion dopants and repair the damages, and then are compared with the conventional rapid thermal annealing (RTA). In terms of As+ and P+ implanted Si, the electrical and structural characterization confirms that the microwave and laser annealing can achieve more efficient dopant activation and recrystallization than conventional RTA. The efficient dopant activation in microwave annealing is attributed to ion hopping under microwave field, while the liquid phase growth in laser annealing provides its efficient dopant activation. The characterization of dopants diffusion shows no visible diffusion after microwave annealing, some extent of end range of diffusion after RTA, and significant dopant diffusion after laser annealing. For photovoltaic applications, an indium-free novel three-layer thin-film structure (transparent composited electrode (TCE)) is demonstrated as a promising transparent conductive electrode for solar cells. The characterization of TCE mainly focuses on its optical and electrical properties. Transfer matrix method for optical transmittance calculation is validated and proved to be a desirable method for predicting transmittance of TCE containing continuous metal layer, and can estimate the trend of transmittance as the layer thickness changes. TiO2/Ag/TiO2 (TAgT) electrode for organic solar cells (OSCs) is then designed using numerical simulation and shows much higher Haacke figure of merit than indium tin oxide (ITO). In addition, TAgT based OSC shows better performance than ITO based OSC when compatible hole transfer layer

  4. Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

    Science.gov (United States)

    Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

    2013-08-21

    For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge

  5. Rapid virtual prototyping of complex photonic integrated circuits using layout-aware schematic-driven design methodology

    Science.gov (United States)

    Mingaleev, S.; Richter, A.; Sokolov, E.; Savitzki, S.; Polatynski, A.; Farina, J.; Koltchanov, I.

    2017-02-01

    We present our versatile simulation framework for the schematic-driven and layout-aware design of photonic integrated circuits (PICs) realizing a fast and user-friendly design flow for large-scale PICs comprising passive and active building blocks (BBs). We show how the seamless interaction of circuit simulation with photonic layout design tools allows to specify and utilize directly physical locations and orientations of BBs of standardized process design kits (PDKs). We demonstrate how to combine graphical schematic capture and automated waveguide routing, and discuss by means of typical design applications how an optimized design flow can speed-up the virtual prototyping of complex PICs and optoelectronic applications.

  6. Integrability: mathematical methods for studying solitary waves theory

    Science.gov (United States)

    Wazwaz, Abdul-Majid

    2014-03-01

    In recent decades, substantial experimental research efforts have been devoted to linear and nonlinear physical phenomena. In particular, studies of integrable nonlinear equations in solitary waves theory have attracted intensive interest from mathematicians, with the principal goal of fostering the development of new methods, and physicists, who are seeking solutions that represent physical phenomena and to form a bridge between mathematical results and scientific structures. The aim for both groups is to build up our current understanding and facilitate future developments, develop more creative results and create new trends in the rapidly developing field of solitary waves. The notion of the integrability of certain partial differential equations occupies an important role in current and future trends, but a unified rigorous definition of the integrability of differential equations still does not exist. For example, an integrable model in the Painlevé sense may not be integrable in the Lax sense. The Painlevé sense indicates that the solution can be represented as a Laurent series in powers of some function that vanishes on an arbitrary surface with the possibility of truncating the Laurent series at finite powers of this function. The concept of Lax pairs introduces another meaning of the notion of integrability. The Lax pair formulates the integrability of nonlinear equation as the compatibility condition of two linear equations. However, it was shown by many researchers that the necessary integrability conditions are the existence of an infinite series of generalized symmetries or conservation laws for the given equation. The existence of multiple soliton solutions often indicates the integrability of the equation but other tests, such as the Painlevé test or the Lax pair, are necessary to confirm the integrability for any equation. In the context of completely integrable equations, studies are flourishing because these equations are able to describe the

  7. Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

    Science.gov (United States)

    Alt, Shannon

    2016-01-01

    Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

  8. Evaluation of Electromigration Behaviors of Pb-Free Microbumps in Three-Dimensional Integrated Circuit Packaging

    Science.gov (United States)

    Hsu, Hao; Lin, Tzu-Yang; Ouyang, Fan-Yi

    2014-01-01

    This study investigated electromigration (EM) behaviors of Pb-free microbumps in three-dimensional integrated circuit (3D IC) packaging under electrical current stressing from 1 × 104 A/cm2 to 1 × 105 A/cm2 at ambient temperature of 150°C. EM-induced fast under bump metallization consumption at the cathode of the microbumps was observed when the current density was higher than 8 × 104 A/cm2, whereas no EM-induced damage of the microbumps was found after 14,416 h when the current density was below 1.5 × 104 A/cm2. We propose that the different EM behaviors of the microbumps were mainly due to the effect of back stress. The critical microbump height to trigger EM for different current densities is discussed, and the resistance evolution of samples during current stressing was found to be correlated with the microstructure of the samples. When the resistance was stable through the whole test period, microscopic inspection of the 3D IC samples indicated that the whole microbumps were transformed to intermetallic compounds without significant EM-induced damage. However, the resistance evolution of some misaligned microbumps exhibited a feature of an early spike along with a huge resistance fluctuation during current stressing. When the resistance abruptly increased after lengthy stressing, EM-induced void formation was observed at the cathode side of the Al trace.

  9. Development of high-performance printed organic field-effect transistors and integrated circuits.

    Science.gov (United States)

    Xu, Yong; Liu, Chuan; Khim, Dongyoon; Noh, Yong-Young

    2015-10-28

    Organic electronics is regarded as an important branch of future microelectronics especially suited for large-area, flexible, transparent, and green devices, with their low cost being a key benefit. Organic field-effect transistors (OFETs), the primary building blocks of numerous expected applications, have been intensively studied, and considerable progress has recently been made. However, there are still a number of challenges to the realization of high-performance OFETs and integrated circuits (ICs) using printing technologies. Therefore, in this perspective article, we investigate the main issues concerning developing high-performance printed OFETs and ICs and seek strategies for further improvement. Unlike many other studies in the literature that deal with organic semiconductors (OSCs), printing technology, and device physics, our study commences with a detailed examination of OFET performance parameters (e.g., carrier mobility, threshold voltage, and contact resistance) by which the related challenges and potential solutions to performance development are inspected. While keeping this complete understanding of device performance in mind, we check the printed OFETs' components one by one and explore the possibility of performance improvement regarding device physics, material engineering, processing procedure, and printing technology. Finally, we analyze the performance of various organic ICs and discuss ways to optimize OFET characteristics and thus develop high-performance printed ICs for broad practical applications.

  10. Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

    Directory of Open Access Journals (Sweden)

    Mohammed Darmi

    2017-10-01

    Full Text Available As we increasingly use advanced technology nodes to design integrated circuits (ICs, physical designers and electronic design automation (EDA providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR. An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics’ physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS and total negative slack (TNS improved up to 13% and 56%, respectively, compared to the baseline flow.

  11. Neuron Stimulation Device Integrated with Silicon Nanowire-Based Photodetection Circuit on a Flexible Substrate

    Directory of Open Access Journals (Sweden)

    Suk Won Jung

    2016-12-01

    Full Text Available This paper proposes a neural stimulation device integrated with a silicon nanowire (SiNW-based photodetection circuit for the activation of neurons with light. The proposed device is comprised of a voltage divider and a current driver in which SiNWs are used as photodetector and field-effect transistors; it has the functions of detecting light, generating a stimulation signal in proportion to the light intensity, and transmitting the signal to a micro electrode. To show the applicability of the proposed neural stimulation device as a high-resolution retinal prosthesis system, a high-density neural stimulation device with a unit cell size of 110 × 110 μ m and a resolution of 32 × 32 was fabricated on a flexible film with a thickness of approximately 50 μm. Its effectiveness as a retinal stimulation device was then evaluated using a unit cell in an in vitro animal experiment involving the retinal tissue of retinal Degeneration 1 (rd1 mice. Experiments wherein stimulation pulses were applied to the retinal tissues successfully demonstrate that the number of spikes in neural response signals increases in proportion to light intensity.

  12. Manipulating mammalian cell morphologies using chemical-mechanical polished integrated circuit chips.

    Science.gov (United States)

    Moussa, Hassan I; Logan, Megan; Siow, Geoffrey C; Phann, Darron L; Rao, Zheng; Aucoin, Marc G; Tsui, Ting Y

    2017-01-01

    Tungsten chemical-mechanical polished integrated circuits were used to study the alignment and immobilization of mammalian (Vero) cells. These devices consist of blanket silicon oxide thin films embedded with micro- and nano-meter scale tungsten metal line structures on the surface. The final surfaces are extremely flat and smooth across the entire substrate, with a roughness in the order of nanometers. Vero cells were deposited on the surface and allowed to adhere. Microscopy examinations revealed that cells have a strong preference to adhere to tungsten over silicon oxide surfaces with up to 99% of cells adhering to the tungsten portion of the surface. Cells self-aligned and elongated into long threads to maximize contact with isolated tungsten lines as thin as 180 nm. The orientation of the Vero cells showed sensitivity to the tungsten line geometric parameters, such as line width and spacing. Up to 93% of cells on 10 μm wide comb structures were aligned within ± 20° of the metal line axis. In contrast, only ~22% of cells incubated on 0.18 μm comb patterned tungsten lines were oriented within the same angular interval. This phenomenon is explained using a simple model describing cellular geometry as a function of pattern width and spacing, which showed that cells will rearrange their morphology to maximize their contact to the embedded tungsten. Finally, it was discovered that the materials could be reused after cleaning the surfaces, while maintaining cell alignment capability.

  13. DCal: A custom integrated circuit for calorimetry at the International Linear Collider

    Energy Technology Data Exchange (ETDEWEB)

    Hoff, James R.; Mekkaoui, Abderrazek; Yarema, Ray; /Fermilab; Drake, Gary; Repond, Jose; /Argonne

    2005-10-01

    A research and development collaboration has been started with the goal of producing a prototype hadron calorimeter section for the purpose of proving the Particle Flow Algorithm concept for the International Linear Collider. Given the unique requirements of a Particle Flow Algorithm calorimeter, custom readout electronics must be developed to service these detectors. This paper introduces the DCal or Digital Calorimetry Chip, a custom integrated circuit developed in a 0.25um CMOS process specifically for this International Linear Collider project. The DCal is capable of handling 64 channels, producing a 1-bit Digital-to-Analog conversion of the input (i.e. hit/no hit). It maintains a 24-bit timestamp and is capable of operating either in an externally triggered mode or in a self-triggered mode. Moreover, it is capable of operating either with or without a pipeline delay. Finally, in order to permit the testing of different calorimeter technologies, its analog front end is capable of servicing Particle Flow Algorithm calorimeters made from either Resistive Plate Chambers or Gaseous Electron Multipliers.

  14. Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-Il Dan; Ko, Hyoungho

    2015-10-14

    Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

  15. Testing of interposer-based 2.5D integrated circuits

    CERN Document Server

    Wang, Ran

    2017-01-01

    This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and dela...

  16. High figure-of-merit SOI power LDMOS for power integrated circuits

    Directory of Open Access Journals (Sweden)

    Yashvir Singh

    2015-06-01

    Full Text Available The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS are carried out to improve the breakdown voltage, on-resistance, gate-charge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two separate trenches build in the drift region and single source and drain contacts are taken on the top. The trench structure reduces the electric field inside the drift region and allow increased drift layer doping concentration leading to higher breakdown voltage, lower specific on-resistance, reduced gate-drain charge, and substantial improvement in the figure-of-merits. Using two-dimensional simulations, the performance of the proposed LDMOS is optimized and results are compared with the conventional LDMOS. Our simulation results show that the proposed device exhibits 110% higher breakdown voltage, 40% reduction in cell pitch, 19% lower specific on-resistance, 30% lower gate-to-drain charge leading to 5.5 times improvement in Baliga's figure-of-merit and 43% reduction in dynamic figure-of-merit over the conventional device.

  17. Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-10-01

    Full Text Available Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

  18. Warpage of QFN Package in Post Mold Cure Process of integrated circuit packaging

    Science.gov (United States)

    Sriwithoon, Nattha; Ugsornrat, Kessararat; Srisuwitthanon, Warayoot; Thonglor, Panakamon

    2017-09-01

    This research studied about warpage of QFN package in post mold cure process of integrated circuit (IC) packages using pre-plated (PPF) leadframe. For IC package, epoxy molding compound (EMC) are molded by cross linking of compound stiffness but incomplete crosslinked network and leading the fully cured thermoset by post mold cure (PMC) process. The cure temperature of PMC can change microstructure of EMC in term of stress inside the package and effect to warpage of the package due to coefficient of thermal expansion (CTE) between EMC and leadframe. In experiment, cure temperatures were varied to check the effect of internal stress due to different cure temperature after completed post mold cure for TDFN 2×3 8L. The cure temperature were varied with 180 °C, 170 °C, 160 °C, and 150°C with cure time 4 and 6 hours, respectively. For analysis, the TDFN 2×3 8L packages were analyzed the warpage by thickness gauge and scanning acoustic microscope (SAM) after take the test samples out from the oven cure. The results confirmed that effect of different CTE between EMC and leadframe due to different cure temperature resulting to warpage of the TDFN 2×3 8L packages.

  19. Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

    Science.gov (United States)

    Chen, Meng; Lei, Jiefeng; Huang, Shengxiang; Liao, Congwei; Deng, Lianwen

    2017-06-01

    A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive {V}{TH} shift within 0.4 V and negative {V}{TH} shift within -1.2 V and it is robust and promising for high-resolution display. Project supported by the Science and Technology Project of Hunan Province, China (No. 2015JC3401)

  20. Prolonged silicon carbide integrated circuit operation in Venus surface atmospheric conditions

    Directory of Open Access Journals (Sweden)

    Philip G. Neudeck

    2016-12-01

    Full Text Available The prolonged operation of semiconductor integrated circuits (ICs needed for long-duration exploration of the surface of Venus has proven insurmountably challenging to date due to the ∼ 460 °C, ∼ 9.4 MPa caustic environment. Past and planned Venus landers have been limited to a few hours of surface operation, even when IC electronics needed for basic lander operation are protected with heavily cumbersome pressure vessels and cooling measures. Here we demonstrate vastly longer (weeks electrical operation of two silicon carbide (4H-SiC junction field effect transistor (JFET ring oscillator ICs tested with chips directly exposed (no cooling and no protective chip packaging to a high-fidelity physical and chemical reproduction of Venus’ surface atmosphere. This represents more than 100-fold extension of demonstrated Venus environment electronics durability. With further technology maturation, such SiC IC electronics could drastically improve Venus lander designs and mission concepts, fundamentally enabling long-duration enhanced missions to the surface of Venus.

  1. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Multimedia

    Loddo, F; Liberali, V; Rizzi, A; Re, V; Minuti, M; De canio, F; Pangaud, P; Barbero, M B; Pacher, L; Kluit, R; Hinchliffe, I; Manghisoni, M; Giubilato, P; Faccio, F; Pernegger, H; Krueger, H; Gensolen, F D; Bilei, G M; Da rocha rolo, M D; Prydderch, M L; Fanucci, L; Grillo, A A; Bellazzini, R; Palomo pinto, F R; Michelis, S; Huegging, F G; Kishishita, T; Marchiori, G; Christian, D C; Kaestli, H C; Meier, B; Andreazza, A; Key-charriere, M; Linssen, L; Dannheim, D; Conti, E; Hemperek, T; Menouni, M; Fougeron, D; Genat, J; Bomben, M; Marzocca, C; Demaria, N; Mazza, G; Van bakel, N A; Palla, F; Grippo, M T; Magazzu, G; Ratti, L; Abbaneo, D; Crescioli, F; Deptuch, G W; Neue, G; De robertis, G; Passeri, D; Placidi, P; Gromov, V; Morsani, F; Paccagnella, A; Christiansen, J; Dho, E; Wermes, N; Rymaszewski, P; Rozanov, A; Wang, A; Lipton, R J; Havranek, M; Neviani, A; Karagounis, M; Godiot, S; Calderini, G; Seidel, S C; Horisberger, R P; Garcia-sciveres, M A; Stabile, A; Beccherle, R; Bacchetta, N

    The present hybrid pixel detectors in operation at the LHC represent a major achievement. They deployed a new technology on an unprecedented scale and their success firmly established pixel tracking as indispensable for future HEP experiments. However, extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. We propose a new RD collaboration specifically focused on the development of pixel readout Integrated Circuits (IC). The IC challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm$^{2}$), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. We propose a collaboration to design the next generation of hybrid pixel readout chips to enable the ATLAS and CMS Phase 2 pixel upgrades. This does not imply that ATLAS and CMS must use the same exact pixel readout chip, as most of the dev...

  2. Effecting aging time of epoxy molding compound to molding process for integrated circuit packaging

    Science.gov (United States)

    Tachapitunsuk, Jirayu; Ugsornrat, Kessararat; Srisuwitthanon, Warayoot; Thonglor, Panakamon

    2017-09-01

    This research studied about effecting aging time of epoxy molding compound (EMC) that effect to reliability performance of integrated circuit (IC) package in molding process. Molding process is so important of IC packaging process for protecting IC chip (or die) from temperature and humidity environment using encapsulated EMC. For general molding process, EMC are stored in the frozen at 5°C and left at room temperature at 25 °C for aging time on self before molding of die onto lead frame is 24 hours. The aging time effect to reliability performance of IC package due to different temperature and humidity inside the package. In experiment, aging time of EMC were varied from 0 to 24 hours for molding process of SOIC-8L packages. For analysis, these packages were tested by x-ray and scanning acoustic microscope to analyze properties of EMC with an aging time and also analyzed delamination, internal void, and wire sweep inside the packages with different aging time. The results revealed that different aging time of EMC effect to properties and reliability performance of molding process.

  3. Exploring the Technological Collaboration Characteristics of the Global Integrated Circuit Manufacturing Industry

    Directory of Open Access Journals (Sweden)

    Yun Liu

    2018-01-01

    Full Text Available With the intensification of international competition, there are many international technological collaborations in the integrated circuit manufacturing (ICM industry. The importance of improving the level of international technological collaboration is becoming more and more prominent. Therefore, it is vital for a country, a region, or an institution to understand the international technological collaboration characteristics of the ICM industry and, thus, to know how to enhance its own international technological collaboration. This paper depicts the international technological collaboration characteristics of the ICM industry based on patent analysis. Four aspects, which include collaboration patterns, collaboration networks, collaboration institutions, and collaboration impacts, are analyzed by utilizing patent association analysis and social network analysis. The findings include the following: first, in regard to international technological collaboration, the USA has the highest level, while Germany has great potential for future development; second, Asia and Europe have already formed clusters, respectively, in the cooperative network; last, but not least, research institutions, colleges, and universities should also actively participate in international collaboration. In general, this study provides an objective reference for policy making, competitiveness, and sustainability in the ICM industry. The framework presented in this paper could be applied to examine other industrial international technological collaborations.

  4. A Broadband Polyvinylidene Difluoride-Based Hydrophone with Integrated Readout Circuit for Intravascular Photoacoustic Imaging.

    Science.gov (United States)

    Daeichin, Verya; Chen, Chao; Ding, Qing; Wu, Min; Beurskens, Robert; Springeling, Geert; Noothout, Emile; Verweij, Martin D; van Dongen, Koen W A; Bosch, Johan G; van der Steen, Antonius F W; de Jong, Nico; Pertijs, Michiel; van Soest, Gijs

    2016-05-01

    Intravascular photoacoustic (IVPA) imaging can visualize the coronary atherosclerotic plaque composition on the basis of the optical absorption contrast. Most of the photoacoustic (PA) energy of human coronary plaque lipids was found to lie in the frequency band between 2 and 15 MHz requiring a very broadband transducer, especially if a combination with intravascular ultrasound is desired. We have developed a broadband polyvinylidene difluoride (PVDF) transducer (0.6 × 0.6 mm, 52 μm thick) with integrated electronics to match the low capacitance of such a small polyvinylidene difluoride element (<5 pF/mm(2)) with the high capacitive load of the long cable (∼100 pF/m). The new readout circuit provides an output voltage with a sensitivity of about 3.8 μV/Pa at 2.25 MHz. Its response is flat within 10 dB in the range 2 to 15 MHz. The root mean square (rms) output noise level is 259 μV over the entire bandwidth (1-20 MHz), resulting in a minimum detectable pressure of 30 Pa at 2.25 MHz. Copyright © 2016 World Federation for Ultrasound in Medicine & Biology. Published by Elsevier Inc. All rights reserved.

  5. A 64-channel integrated circuit for signal readout from coordinate detectors

    Science.gov (United States)

    Aulchenko, V.; Shekhtman, L.; Zhulanov, V.

    2017-05-01

    A specialized integrated circuit was developed for the readout of signal from coordinate detectors of different types, including gas micro-pattern detectors and silicon microstrip detectors. The ASIC includes 64 channels, each containing a low-noise charge-sensitive amplifier with a connectable feedback capacitor and resistor, and fast reset of the feedback capacitor. Each channel of the ASIC also contains 100 cells of analogue memory where the signal can be stored at a rate of 10 MHz. The pitch of input pads is 50 μm and the chip size is 5× 5 mm2. The equivalent noise charge of the ASIC channel is about 2000 electrons with 10 pF capacitance at the input and maximal signal before saturation corresponds to 2× 106 electrons. The first application for this ASIC is the detector for imaging of explosions at a synchrotron radiation beam (DIMEX), where it has to substitute the old and slower APC128 ASIC. The full-size electronics including 8 ASICs for 512 channels was assembled and tested.

  6. Prolonged silicon carbide integrated circuit operation in Venus surface atmospheric conditions

    Science.gov (United States)

    Neudeck, Philip G.; Meredith, Roger D.; Chen, Liangyu; Spry, David J.; Nakley, Leah M.; Hunter, Gary W.

    2016-12-01

    The prolonged operation of semiconductor integrated circuits (ICs) needed for long-duration exploration of the surface of Venus has proven insurmountably challenging to date due to the ˜ 460 °C, ˜ 9.4 MPa caustic environment. Past and planned Venus landers have been limited to a few hours of surface operation, even when IC electronics needed for basic lander operation are protected with heavily cumbersome pressure vessels and cooling measures. Here we demonstrate vastly longer (weeks) electrical operation of two silicon carbide (4H-SiC) junction field effect transistor (JFET) ring oscillator ICs tested with chips directly exposed (no cooling and no protective chip packaging) to a high-fidelity physical and chemical reproduction of Venus' surface atmosphere. This represents more than 100-fold extension of demonstrated Venus environment electronics durability. With further technology maturation, such SiC IC electronics could drastically improve Venus lander designs and mission concepts, fundamentally enabling long-duration enhanced missions to the surface of Venus.

  7. Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

    Science.gov (United States)

    Bellofatto, Ralph E [Ridgefield, CT; Ellavsky, Matthew R [Rochester, MN; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Gooding, Thomas M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Hehenberger, Lance G [Leander, TX; Ohmacht, Martin [Yorktown Heights, NY

    2012-03-20

    An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

  8. Inter Digital Transducer Modelling through Mason Equivalent Circuit Model

    DEFF Research Database (Denmark)

    Mishra, Dipti; Singh, Abhishek; Hussain, Dil muhammed Akbar

    2016-01-01

    The frequency reliance of inter-digital transducer is analyzed with the help of MASON’s Equivalent circuit which is based on Smith’s Equivalent circuit which is further based on Foster’sNetwork. An inter-digital transducer has been demonstratedas a RLC network. The circuit is simulated by Simulat......The frequency reliance of inter-digital transducer is analyzed with the help of MASON’s Equivalent circuit which is based on Smith’s Equivalent circuit which is further based on Foster’sNetwork. An inter-digital transducer has been demonstratedas a RLC network. The circuit is simulated...... by Simulation program with Integrated Circuit Emphasis (HSPICE), a well-liked electronic path simulator. The acoustic wave devices are not suitable to simulation through circuit simulator.In this paper, an electrical model of Mason’s Equivalent electricalcircuit for an inter-digital transducer (IDT...

  9. Technological Literacy Learning with Cumulative and Stepwise Integration of Equations into Electrical Circuit Diagrams

    Science.gov (United States)

    Ozogul, G.; Johnson, A. M.; Moreno, R.; Reisslein, M.

    2012-01-01

    Technological literacy education involves the teaching of basic engineering principles and problem solving, including elementary electrical circuit analysis, to non-engineering students. Learning materials on circuit analysis typically rely on equations and schematic diagrams, which are often unfamiliar to non-engineering students. The goal of…

  10. An evaluation of the Intel 2920 digital signal processing integrated circuit

    Science.gov (United States)

    Heller, J.

    1981-01-01

    The circuit consists of a digital to analog converter, accumulator, read write memory and UV erasable read only memory. The circuit can convert an analog signal to a digital representation, perform mathematical operations on the digital signal and subsequently convert the digital signal to an analog output. Development software tailored for programming the 2920 is presented.

  11. A Class of Nonlinear RLC Circuits Globally Stabilizable by Proportional plus Integral Controllers

    NARCIS (Netherlands)

    Castanos, F.; Jayawardhana, B.; Ortega, R.; Garcia-Canseco, E.

    In this note we identify graph-theoretic conditions which allow to write an RLC circuit as port-Hamiltonian with constant input matrices. We show that under additional monotonicity conditions of the network’s components, the circuit enjoys the property of relative passivity, an extended notion of

  12. 2 μm wavelength range InP-based type-II quantum well photodiodes heterogeneously integrated on silicon photonic integrated circuits.

    Science.gov (United States)

    Wang, Ruijun; Sprengel, Stephan; Muneeb, Muhammad; Boehm, Gerhard; Baets, Roel; Amann, Markus-Christian; Roelkens, Gunther

    2015-10-05

    The heterogeneous integration of InP-based type-II quantum well photodiodes on silicon photonic integrated circuits for the 2 µm wavelength range is presented. A responsivity of 1.2 A/W at a wavelength of 2.32 µm and 0.6 A/W at 2.4 µm wavelength is demonstrated. The photodiodes have a dark current of 12 nA at -0.5 V at room temperature. The absorbing active region of the integrated photodiodes consists of six periods of a "W"-shaped quantum well, also allowing for laser integration on the same platform.

  13. Integration of electroluminescent displays on multilayer ceramic-on-metal circuit boards for application in military vehicles

    Science.gov (United States)

    Riddle, George H. N.; Sreeram, A. N.; Staebler, David L.; Mahdi, Ken F.; Sun, Sey-Shing; Morton, David C.

    1998-09-01

    Display system requirements for deployment in military vehicles are very demanding. Multilayer ceramic-on-metal circuit board technology is being applied to enable the fabrication of electroluminescent displays with enhanced performance, ruggedness, and functionality. The circuit board is utilized as the display substrate. The metal core of the circuit board provides a highly rugged panel with excellent thermal dissipation. Display packaging is simplified and display system size and weight are reduced by integrating drivers onto the display. This approach enables increases in display brightness by addressing the EL display in multiple segments with conductive vias through the circuit board. System cost is reduced by eliminating flex-cable edge connectors and by simplifying the package. Display functionality can be extended by integrating related electronics onto the display panel. Monochrome display samples have been demonstrated with performance similar to samples fabricated on traditional glass substrates. Current efforts are directed toward demonstrating high-performance color EL, utilizing the ability of the ceramic substrates to accommodate high-temperature phosphor annealing required to fully activate blue phosphors.

  14. Applications of Raman spectroscopy for silicon stress characterization in integrated circuits

    Science.gov (United States)

    McDonough, Colin J.

    2011-12-01

    The introduction of mechanical stress in Si-based integrated circuits (ICs), whether desired or undesired, is intrinsic to IC fabrication. The origins are diverse and result from the numerous materials, geometries, and processes involved in fabrication. These stresses can lead to such effects as delamination, void formation and migration, and fracture, and can significantly affect device performance. As a result, stress development is a major concern for reliability, process control, and device design. It is necessary to investigate and characterize the origins and levels of the induced stresses. A more complete fundamental understanding of the evolution of stress in ICs and novel ways in which it can be characterized can lead to more effective strategies to mitigate or control stress development. Equivalent scaling strategies such as strain-engineered MOSFET channels and 3D integration schemes are important for maintaining IC performance increases at current and future semiconductor technology nodes. Strained Si can affect carrier mobility, either negatively or positively, depending on direction and magnitude of strain and the majority carrier type. This is of benefit in strain engineering of the MOSFET channel region. However, in 3D architectures, the integration of Cu TSVs through the active region can induce thermo-mechanical residual stresses in the nearby Si, which could lead to undesirable performance variations. Therefore, it is important to have instrumentation available for characterizing the stresses in the MOSFET channel regions as well as in Si regions surrounding TSV structures in 3D-ICs. Raman spectroscopy is an all-optical technique that is applicable for measuring stress in Si based on changes in the crystalline vibrational modes. Part of this dissertation covers work completed in evaluation of so-called tip-enhanced Raman spectroscopy (TERS) for sub-diffraction limited, localized stress characterization for FEOL applications. This includes

  15. Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

    Science.gov (United States)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2016-01-01

    This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

  16. Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

    2014-10-28

    The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

  17. Sol-Gel Zinc Oxide Humidity Sensors Integrated with a Ring Oscillator Circuit On-a-Chip

    Directory of Open Access Journals (Sweden)

    Ming-Zhi Yang

    2014-10-01

    Full Text Available The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

  18. G-s0 mode converter with lateral gold mirrors for nano-plasmonic integrated circuits.

    Science.gov (United States)

    Lee, Dong Hun; Son, Jung-Han; Park, Hae-Ryeong; Kim, Min-Su; Leel, Myung-Hyun

    2014-11-01

    We propose a waveguide-typed plasmonic mode converter with lateral gold mirrors (LGMs) at a wavelength of 1.55 μm. The 17.5 μm-long gap-s0 mode converter (G-s0 MC) is composed of an input 4.5 μm-wide insulator-metal-insulator-metal-insulator waveguide (IMIMI-W) and an output 2.0 μm-wide metal-insulator-metal waveguide (MIM-W) with LGMs connected by a laterally tapered (LT) IMIMI-W with LGMs. The strip thicknesses of the IMIMI-Ws and MIM-W are 20 nm and 50 nm, respectively. The 12.0 μm-long LGMs with 1.5 μm thickness are located beside the LT-IMIMI-W and MIM-W. All metals in the IMIMI-Ws, MIM-W, and LGMs are designed with gold. A low-loss polymer is used for the 30 μm-thick upper and lower cladding layers. The thickness of the central insulator in both the IMIMI-Ws and MIM-W was designed to be 500 nm. The input Ss0 mode with the size of -5.9 μm x 4.8 μm is converted to the output G-s0 mode with the size of 1.1 μm x 0.5 μm. The total loss of the G-s0 MC, including conversion loss, is -6.96 dB in simulation. The proposed G-s0 MC may be potentially useful for bridging micro- to nano-plasmonic integrated circuits.

  19. How thin barrier metal can be used to prevent Co diffusion in the modern integrated circuits?

    Science.gov (United States)

    Dixit, Hemant; Konar, Aniruddha; Pandey, Rajan; Ethirajan, Tamilmani

    2017-11-01

    In modern integrated circuits (ICs), billions of transistors are connected to each other via thin metal layers (e.g. copper, cobalt, etc) known as interconnects. At elevated process temperatures, inter-diffusion of atomic species can occur among these metal layers, causing sub-optimal performance of interconnects, which may lead to the failure of an IC. Thus, typically a thin barrier metal layer is used to prevent the inter-diffusion of atomic species within interconnects. For ICs with sub-10 nm transistors (10 nm technology node), the design rule (thickness scaling) demands the thinnest possible barrier layer. Therefore, here we investigate the critical thickness of a titanium–nitride (TiN) barrier that can prevent the cobalt diffusion using multi-scale modeling and simulations. First, we compute the Co diffusion barrier in crystalline and amorphous TiN with the nudged elastic band method within first-principles density functional theory simulations. Later, using the calculated activation energy barriers, we quantify the Co diffusion length in the TiN metal layer with the help of kinetic Monte Carlo simulations. Such a multi-scale modelling approach yields an exact critical thickness of the metal layer sufficient to prevent the Co diffusion in IC interconnects. We obtain a diffusion length of a maximum of 2 nm for a typical process of thermal annealing at 400 °C for 30 min. Our study thus provides useful physical insights for the Co diffusion in the TiN layer and further quantifies the critical thickness (~2 nm) to which the metal barrier layer can be thinned down for sub-10 nm ICs.

  20. Predictive Direct Torque Control Application-Specific Integrated Circuit of an Induction Motor Drive with a Fuzzy Controller

    OpenAIRE

    Guo-Ming Sung; Wei-Yu Wang; Wen-Sheng Lin; Chih-Ping Yu

    2017-01-01

    This paper proposes a modified predictive direct torque control (PDTC) application-specific integrated circuit (ASIC) of a motor drive with a fuzzy controller for eliminating sampling and calculating delay times in hysteresis controllers. These delay times degrade the control quality and increase both torque and flux ripples in a motor drive. The proposed fuzzy PDTC ASIC calculates the stator’s magnetic flux and torque by detecting the three-phase current, three-phase voltage, and rotor speed...

  1. Direct intertectal inputs are an integral component of the bilateral sensorimotor circuit for behavior in Xenopus tadpoles.

    Science.gov (United States)

    Gambrill, Abigail C; Faulkner, Regina L; Cline, Hollis T

    2018-02-14

    The circuit controlling visually-guided behavior in non-mammalian vertebrates, like Xenopus tadpoles, includes retinal projections to the contralateral optic tectum, where visual information is processed, and tectal motor outputs projecting ipsilaterally to hindbrain and spinal cord. Tadpoles have an intertectal commissure whose function is unknown, but it might transfer information between the tectal lobes. Differences in visual experience between the two eyes have profound effects on the development and function of visual circuits in animals with binocular vision, but the effects on animals with fully-crossed retinal projections are not clear. We tested the effect of monocular visual experience on the visuomotor circuit in Xenopus tadpoles. We show that cutting the intertectal commissure or providing visual experience to one eye (monocular visual experience) are both sufficient to disrupt tectally-mediated visual avoidance behavior. Monocular visual experience induces asymmetry in tectal circuit activity across the midline. Repeated exposure to monocular visual experience drives maturation of the stimulated retinotectal synapses, seen as increased AMPA/NMDA ratios, induces synaptic plasticity in intertectal synaptic connections and induces bilaterally asymmetric changes in the tectal excitation/inhibition ratio (E/I). We show that unilateral expression of peptides that interfere with AMPA or GABAA receptor trafficking alters E/I in the transfected tectum and is sufficient to degrade visuomotor behavior. Our study demonstrates that monocular visual experience in animals with fully-crossed visual systems produces asymmetric circuit function across the midline and degrades visuomotor behavior. The data further suggest that intertectal inputs are an integral component of a bilateral visuomotor circuit critical for behavior.

  2. Integrated Planar Lightwave Circuits for UV Generation and Phase Modulation Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This SBIR Phase I effort proposes to establish the feasibility of developing a UV Planar Lightwave Circuit (PLC); a compact, highly efficient, waveguide-based...

  3. Variable time constant frequency meter with MECL integrated circuits; Frequencemetre numerique a constantes de temps variables et en circuits integres MECL

    Energy Technology Data Exchange (ETDEWEB)

    Fuan, J.; Kaiser, J. [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

    1968-07-01

    The point of interest of this frequency meter is that its accuracy is fixed in advance for the whole frequency range which is to be measured. For this, it is possible for the measurement range to be changed several times by changing the time constant which varies over discrete values and adopts that corresponding to the measured frequency for a given accuracy. The frequency meter which we present here gives three values of the accuracy, i. e. three groups of variable time constants, and operates as a chronometer and as a conventional frequency meter. The object is to describe the construction of a variable time-constant system and it is obvious that further work would lead, because of new industrial circuits, to great improvements in the design of the apparatus. (authors) [French] L'interet de ce frequencemetre est de limiter sa precision a une valeur fixee a l'avance pour toute la gamme de frequence a mesurer. Pour cela, il lui est possible de changer la gamme de mesure plusieurs fois en changeant sa constante de temps qui varie par valeurs discretes pour prendre celle correspondante a la frequence mesuree pour une precision donnee. Le frequencemetre que nous proposons affiche trois valeurs de precision, donc trois groupes de constantes, de temps variables et fonctionne en chronometre et en frequencemetre classique. Son but est de montrer la realisation du systeme a constance de temps variable et il est evident qu'une seconde etude amenerait, de par les circuits industriels nouveaux, de grandes ameliorations, dans la conception de l'appareil. (auteurs)

  4. A Alternative Analog Circuit Design Methodology Employing Integrated Artificial Intelligence Techniques

    Science.gov (United States)

    Tuttle, Jeffery L.

    In consideration of the computer processing power now available to the designer, an alternative analog circuit design methodology is proposed. Computer memory capacities no longer require the reduction of the transistor operational characteristics to an imprecise formulation. Therefore, it is proposed that transistor modelling be abandoned in favor of fully characterized transistor data libraries. Secondly, availability of the transistor libraries would facilitate an automated selection of the most appropriate device(s) for the circuit being designed. More specifically, a preprocessor computer program to a more sophisticated circuit simulator (e.g. SPICE) is developed to assist the designer in developing the basic circuit topology and the selection of the most appropriate transistor. Once this is achieved, the circuit topology and selected transistor data library would be downloaded to the simulator for full circuit operational characterization and subsequent design modifications. It is recognized that the design process is enhanced by the use of heuristics as applied to iterative design results. Accordingly, an artificial intelligence (AI) interface is developed to assist the designer in applying the preprocessor results. To demonstrate the retrofitability of the AI interface to established programs, the interface is specifically designed to be as non-intrusive to the host code as possible. Implementation of the proposed methodology offers the potential to speed the design process, since the preprocessor both minimizes the required number of simulator runs and provides a higher acceptance potential of the initial and subsequent simulator runs. Secondly, part count reductions may be realizable since the circuit topologies are not as strongly driven by transistor limitations. Thirdly, the predicted results should more closely match actual circuit operations since the inadequacies of the transistor models have been virtually eliminated. Finally, the AI interface

  5. Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

    Science.gov (United States)

    Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

    2017-05-01

    A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

  6. The use of a new PMOS monolithic integrated circuit for the electronic equipment of a large multiwire proportional chamber (MWPC) detection system

    CERN Document Server

    Bareyre, P; Borgeaud, P; Poinsignon, J

    1975-01-01

    A new monolithic 8-channel PMOS integrated circuit has been developed for an experiment to be carried out on the CERN 300 GeV accelerator. The circuit, read-out electronics and tests performed on 12 large MWPCs (total of 48000 channels) are described and the results are presented. (3 refs).

  7. Electronic meter with custom integrated circuit for electric energy measurement; Medidor eletronico de energia eletrica com circuito integrado dedicado

    Energy Technology Data Exchange (ETDEWEB)

    Caldas, Roberto Pereira

    1990-04-01

    The design and implementation of an electrical energy electronic meter for operation at low voltages, according to two steps of development carried out in Centro de Pesquisas de Energia Eletrica - CEPEL is described. In the first step, an electronic meter with discrete commercial components has been developed, in order to demonstrate to the Brazilian power suppliers the feasibility of such a device for electrical energy metering and charging. The second step was constituted by the design of an integrated circuit, aiming the reduction of the cost of the meter as well as the enhancement of its reliability. Several techniques of electrical energy measurement are presented. The meter with discrete components makes use of a time division multiplier (TDM), in order to determine the active power in the load. Voltage and current levels have been reduced through the use of voltage and current sensors compatible with the TDM's inputs. A V-F converter employing continuos integration, has been used for the determination of the energy consumed by the load through the integration of the TDM's output signal. Most of the discrete components of the meter have been replaced by the dedicated integrated circuit. The TDM has remained essentially the same, but the V-F converter has been changed into a dual-slope one, which is more adequate for implementation in a single chip. The tests performed with the prototypes of the meter including both the meter with discrete components and the meter with the custom-made integrated circuit have presented measurement errors of less the 0,2 %. The initial goal, according to Brazilian specifications of electromechanical meters and international specifications for electronic meters, was 1 %. (author)

  8. An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

    Science.gov (United States)

    Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

    2017-07-01

    This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

  9. An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

    Science.gov (United States)

    D'Addario, Larry R.; Wang, Douglas

    2016-03-01

    Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlation are proportional to N2 and dominate at sufficiently large N. Here, we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope’s bandwidth (the so-called “FX” structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with two opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chip memory and the CMACs are reused as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the ICs size and power consumption. It is intended for fabrication in a 32nm silicon-on-insulator process, where it will require less than 12mm2 of silicon area and achieve an energy efficiency of 1.76-3.3pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to N=4096. The system-level energy efficiency, including board-level I/O, power supplies, and controls, is expected to be 5-7pJ per CMAC operation. Existing correlators for the JVLA (N=32) and ALMA (N=64) telescopes achieve about 5000pJ and 1000pJ, respectively using application-specific ICs (ASICs) in older technologies. To our knowledge, the largest-N existing correlator is LEDA at N=256; it

  10. An Integrated Circuit for Radio Astronomy Correlators Supporting Large Arrays of Antennas

    Science.gov (United States)

    D'Addario, Larry R.; Wang, Douglas

    2016-01-01

    Radio telescopes that employ arrays of many antennas are in operation, and ever larger ones are being designed and proposed. Signals from the antennas are combined by cross-correlation. While the cost of most components of the telescope is proportional to the number of antennas N, the cost and power consumption of cross-correlationare proportional to N2 and dominate at sufficiently large N. Here we report the design of an integrated circuit (IC) that performs digital cross-correlations for arbitrarily many antennas in a power-efficient way. It uses an intrinsically low-power architecture in which the movement of data between devices is minimized. In a large system, each IC performs correlations for all pairs of antennas but for a portion of the telescope's bandwidth (the so-called "FX" structure). In our design, the correlations are performed in an array of 4096 complex multiply-accumulate (CMAC) units. This is sufficient to perform all correlations in parallel for 64 signals (N=32 antennas with 2 opposite-polarization signals per antenna). When N is larger, the input data are buffered in an on-chipmemory and the CMACs are re-used as many times as needed to compute all correlations. The design has been synthesized and simulated so as to obtain accurate estimates of the IC's size and power consumption. It isintended for fabrication in a 32 nm silicon-on-insulator process, where it will require less than 12mm2 of silicon area and achieve an energy efficiency of 1.76 to 3.3 pJ per CMAC operation, depending on the number of antennas. Operation has been analyzed in detail up to N = 4096. The system-level energy efficiency, including board-levelI/O, power supplies, and controls, is expected to be 5 to 7 pJ per CMAC operation. Existing correlators for the JVLA (N = 32) and ALMA (N = 64) telescopes achieve about 5000 pJ and 1000 pJ respectively usingapplication-specific ICs in older technologies. To our knowledge, the largest-N existing correlator is LEDA atN = 256; it

  11. Low power current sources for bioimpedance measurements: A comparison between Howland and integrated CMOS OTA circuits

    Directory of Open Access Journals (Sweden)

    Pedro Bertemes-Filho

    2012-10-01

    Full Text Available Electrical Bioimpedance Analysis has been widely used as a non-invasive technique for characterizing tissues. Most systems use a wideband and a high precision instrumentation, specially the current source. The objective of this work is to compare the Howland circuit with three OTA-based floating voltage controlled current sources. The results show that both Current Conveyor and class-AB OTA have a wider output current frequency response and both output impedance is 226 % bigger than the Howland circuit at 1 MHz. The class-AB OTA circuit presents a power consumption of 4.6 mW whereas 1.6 mW for the Current Conveyor. The results might be useful for cell impedance measurements and for very low power bioimpedance applications.

  12. Thermoacoustic and thermoreflectance imaging of biased integrated circuits: Voltage and temperature maps

    Science.gov (United States)

    Hernández-Rosales, E.; Cedeño, E.; Hernandez-Wong, J.; Rojas-Trigos, J. B.; Marin, E.; Gandra, F. C. G.; Mansanares, A. M.

    2016-07-01

    In this work a combined thermoacoustic and thermoreflectance set-up was designed for imaging biased microelectronic circuits. In particular, it was used with polycrystalline silicon resistive tracks grown on a monocrystalline Si substrate mounted on a test chip. Thermoreflectance images, obtained by scanning a probe laser beam on the sample surface, clearly show the regions periodically heated by Joule effect, which are associated to the electric current distribution in the circuit. The thermoacoustic signal, detected by a pyroelectric/piezoelectric sensor beneath the chip, also discloses the Joule contribution of the whole sample. However, additional information emerges when a non-modulated laser beam is focused on the sample surface in a raster scan mode allowing imaging of the sample. The distribution of this supplementary signal is related to the voltage distribution along the circuit.

  13. Thermoacoustic and thermoreflectance imaging of biased integrated circuits: Voltage and temperature maps

    Energy Technology Data Exchange (ETDEWEB)

    Hernández-Rosales, E.; Cedeño, E. [Gleb Wataghin Physics Institute, University of Campinas - Unicamp, 13083-859 Campinas, SP (Brazil); Instituto Politécnico Nacional, Centro de Investigación en Ciencia Aplicada y Tecnología Avanzada, Legaria 694, Colonia Irrigación, CP 11500, México, DF (Mexico); Hernandez-Wong, J. [Instituto Politécnico Nacional, Centro de Investigación en Ciencia Aplicada y Tecnología Avanzada, Legaria 694, Colonia Irrigación, CP 11500, México, DF (Mexico); CONACYT, México, DF, México (Mexico); Rojas-Trigos, J. B.; Marin, E. [Instituto Politécnico Nacional, Centro de Investigación en Ciencia Aplicada y Tecnología Avanzada, Legaria 694, Colonia Irrigación, CP 11500, México, DF (Mexico); Gandra, F. C. G.; Mansanares, A. M., E-mail: manoel@ifi.unicamp.br [Gleb Wataghin Physics Institute, University of Campinas - Unicamp, 13083-859 Campinas, SP (Brazil)

    2016-07-25

    In this work a combined thermoacoustic and thermoreflectance set-up was designed for imaging biased microelectronic circuits. In particular, it was used with polycrystalline silicon resistive tracks grown on a monocrystalline Si substrate mounted on a test chip. Thermoreflectance images, obtained by scanning a probe laser beam on the sample surface, clearly show the regions periodically heated by Joule effect, which are associated to the electric current distribution in the circuit. The thermoacoustic signal, detected by a pyroelectric/piezoelectric sensor beneath the chip, also discloses the Joule contribution of the whole sample. However, additional information emerges when a non-modulated laser beam is focused on the sample surface in a raster scan mode allowing imaging of the sample. The distribution of this supplementary signal is related to the voltage distribution along the circuit.

  14. The Systematic Integration of Very Large Scale Integrated Circuit Computer-Aided Design Tools into a Toolkit Optimized for Academic Applications.

    Science.gov (United States)

    1984-12-01

    line (DIP) IC package. 1965: Robert Widlar, a designer with Fairchild, develops the first practical integrated circuit operational amplifier ( opamp ...the uA709. Widlar also designed the uA702, uA710, and the uA741 11-2 .*~~~~ .* . . . . . . . .. .* . . . ... . . . . - opamps . 1966: Autonetics...There was resistance to the implementa- tion of automated design aids [17,40]. The reluctance to use CAD programs was partly due to numerous software fail

  15. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    Energy Technology Data Exchange (ETDEWEB)

    Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu [Department of Materials Science and Engineering, Beckman Institute for Advanced Science and Technology, and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 S Goodwin Ave., Urbana, Illinois 61801 (United States); Bozler, Carl [Lincoln Laboratory, Massachusetts Institute of Technology, 244 Wood Street, Lexington, Massachusetts 02420 (United States); Omenetto, Fiorenzo [Department of Biomedical Engineering, Department of Physics, Tufts University, 4 Colby St., Medford, Massachusetts 02155 (United States)

    2015-01-05

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  16. HCMT interaction of whispering gallery modes in circuits of integrated optical microring or -disk resonators

    NARCIS (Netherlands)

    Franchimon, Ellen F.; Hiremath, K.R.; Stoffer, Remco; Hammer, Manfred

    Whispering gallery modes (WGMs) supported by open circular dielectric cavities are embedded into a 2-D hybrid coupled mode theory (HCMT) framework. The model enables convenient studies of supermode formation in composite circuits (CROWS, photonic molecules), and of their excitation by straight

  17. Integrated mechanisms of anticipation and rate-of-change computations in cortical circuits.

    Directory of Open Access Journals (Sweden)

    Gabriel D Puccini

    2007-05-01

    Full Text Available Local neocortical circuits are characterized by stereotypical physiological and structural features that subserve generic computational operations. These basic computations of the cortical microcircuit emerge through the interplay of neuronal connectivity, cellular intrinsic properties, and synaptic plasticity dynamics. How these interacting mechanisms generate specific computational operations in the cortical circuit remains largely unknown. Here, we identify the neurophysiological basis of both the rate of change and anticipation computations on synaptic inputs in a cortical circuit. Through biophysically realistic computer simulations and neuronal recordings, we show that the rate-of-change computation is operated robustly in cortical networks through the combination of two ubiquitous brain mechanisms: short-term synaptic depression and spike-frequency adaptation. We then show how this rate-of-change circuit can be embedded in a convergently connected network to anticipate temporally incoming synaptic inputs, in quantitative agreement with experimental findings on anticipatory responses to moving stimuli in the primary visual cortex. Given the robustness of the mechanism and the widespread nature of the physiological machinery involved, we suggest that rate-of-change computation and temporal anticipation are principal, hard-wired functions of neural information processing in the cortical microcircuit.

  18. Integrated Circuit Design of a Video Reconstructor for a Range-Gated Moving Target Indicator.

    Science.gov (United States)

    1979-12-01

    processing concepts. The author expresses his gratitude to Professor Rudolf Panholzer who gave him the opportunity to meet the semi- conductor world...1976. 5. Clark- Hess , Communication Circuits, Prentice Hall, 1971. 6. Ferrel G. Stremler, Introduction to Communication Systems, McGraw Hill. 7. N. I

  19. Devices and architectures for large-scale integrated silicon photonics circuits

    Science.gov (United States)

    Beausoleil, Raymond G.; Faraon, Andrei; Fattal, David; Fiorentino, Marco; Peng, Zhen; Santori, Charles

    2011-01-01

    We present DWDM nanophotonics architectures based on microring resonator modulators and detectors. We focus on two implementations: an on chip interconnect for multicore processor (Corona) and a high radix network switch (HyperX). Based on the requirements of these applications we discuss the key constraints on the photonic circuits' devices and fabrication techniques as well as strategies to improve their performance.

  20. Monolithically integrated light feedback control circuit for blue/UV LED smart package

    NARCIS (Netherlands)

    Kolahdouz Esfahani, Zahra; Tohidian, M.; van Zeijl, H.W.; Kolahdouz, Mohammadreza; Zhang, G.Q.

    2017-01-01

    Given the performance decay of high-power light-emitting diode (LED) chips over time and package condition changes, having a reliable output light for sensitive applications is a point of concern. In this study, a light feedback control circuit, including blue-selective photodiodes, for

  1. Slow wave structures integrated with ferromagnetic and ferro-electric thin films for smart RF applications

    Science.gov (United States)

    Rahman, B. M. Farid

    wavelength has been reduced from 14.86mm to 4.7mm at 2GHz. DC current which is the most convenient and available tuning parameter in a practical circuit board has been used, the developed SWS can function as quarter wave transmission line from 2GHz to 1.80GHz (i.e. 10%). Lead Zirconium Titanate (PZT) is grown and patterned on top of the section with standard sol-gel method to increase capacitance value. The inter digit capacitor type structure along with PZT thin film has been adopted and results showed capacitance value increment by 36%. An electric field between signal and ground has been applied to change the polarization of the thin film which resulted in a tuning of center frequency by 15% (1.75GHz to 2GHz). In addition, a novel approach has been implemented by integrating both the ferromagnetic and the ferroelectric thin films simultaneously to achieve higher slow wave effect, wider tuning range and smaller variation in Characteristics Impedance. The size of the final structure for a quarter wavelengths has been reduced from 14.86mm to 3.98mm while the center frequency has been tuned from 2GHz to 1.5GHz (i.e. 25%). Tunable RF applications of the ferro-magnetic thin films are also demonstrated as a DC current band pass filter, tunable noise suppressor and meander line inductor. A well designed frequency tunable band pass filter (BPF) is implemented at 4GHz with patterned Permalloy. The pass band frequency of a band pass filter has been tuned from 4GHz to 4.02GHz by applying a DC current. The suppression frequency of the developed noise suppressor is tuned from 4.8GHz to 6GHz and 4GHz to 6GHz by changing the aspect ratio of the Py bars and the gap in between them. Moreover, a novel way of tuning the stop band frequency of the noise suppressor by using an external direct current changed the suppression frequency from 6GHz to 4.3GHz. A pass band loss of 1.5%, less than 2° transmitted signal phase distortion, and 3 dB extra return loss of the designed noise suppressor

  2. Silicon/III-V laser with super-compact diffraction grating for WDM applications in electronic-photonic integrated circuits.

    Science.gov (United States)

    Wang, Yadong; Wei, Yongqiang; Huang, Yingyan; Tu, Yongming; Ng, Doris; Lee, Cheewei; Zheng, Yunan; Liu, Boyang; Ho, Seng-Tiong

    2011-01-31

    We have demonstrated a heterogeneously integrated III-V-on-Silicon laser based on an ultra-large-angle super-compact grating (SCG). The SCG enables single-wavelength operation due to its high-spectral-resolution aberration-free design, enabling wavelength division multiplexing (WDM) applications in Electronic-Photonic Integrated Circuits (EPICs). The SCG based Si/III-V laser is realized by fabricating the SCG on silicon-on-insulator (SOI) substrate. Optical gain is provided by electrically pumped heterogeneous integrated III-V material on silicon. Single-wavelength lasing at 1550 nm with an output power of over 2 mW and a lasing threshold of around 150 mA were achieved.

  3. Unraveling the High Open Circuit Voltage and High Performance of Integrated Perovskite/Organic Bulk-Heterojunction Solar Cells.

    Science.gov (United States)

    Dong, Shiqi; Liu, Yongsheng; Hong, Ziruo; Yao, Enping; Sun, Pengyu; Meng, Lei; Lin, Yuze; Huang, Jinsong; Li, Gang; Yang, Yang

    2017-08-09

    We have demonstrated high-performance integrated perovskite/bulk-heterojunction (BHJ) solar cells due to the low carrier recombination velocity, high open circuit voltage (VOC), and increased light absorption ability in near-infrared (NIR) region of integrated devices. In particular, we find that the VOC of the integrated devices is dominated by (or pinned to) the perovskite cells, not the organic photovoltaic cells. A Quasi-Fermi Level Pinning Model was proposed to understand the working mechanism and the origin of the VOC of the integrated perovskite/BHJ solar cell, which following that of the perovskite solar cell and is much higher than that of the low bandgap polymer based organic BHJ solar cell. Evidence for the model was enhanced by examining the charge carrier behavior and photovoltaic behavior of the integrated devices under illumination of monochromatic light-emitting diodes at different characteristic wavelength. This finding shall pave an interesting possibility for integrated photovoltaic devices to harvest low energy photons in NIR region and further improve the current density without sacrificing VOC, thus providing new opportunities and significant implications for future industry applications of this kind of integrated solar cells.

  4. Encapsulate-and-peel: fabricating carbon nanotube CMOS integrated circuits in a flexible ultra-thin plastic film.

    Science.gov (United States)

    Gao, Pingqi; Zhang, Qing

    2014-02-14

    Fabrication of single-walled carbon nanotube thin film (SWNT-TF) based integrated circuits (ICs) on soft substrates has been challenging due to several processing-related obstacles, such as printed/transferred SWNT-TF pattern and electrode alignment, electrical pad/channel material/dielectric layer flatness, adherence of the circuits onto the soft substrates etc. Here, we report a new approach that circumvents these challenges by encapsulating pre-formed SWNT-TF-ICs on hard substrates into polyimide (PI) and peeling them off to form flexible ICs on a large scale. The flexible SWNT-TF-ICs show promising performance comparable to those circuits formed on hard substrates. The flexible p- and n-type SWNT-TF transistors have an average mobility of around 60 cm(2) V(-1) s(-1), a subthreshold slope as low as 150 mV dec(-1), operating gate voltages less than 2 V, on/off ratios larger than 10(4) and a switching speed of several kilohertz. The post-transfer technique described here is not only a simple and cost-effective pathway to realize scalable flexible ICs, but also a feasible method to fabricate flexible displays, sensors and solar cells etc.

  5. High-performance integrated pick-up circuit for SPAD arrays in time-correlated single photon counting

    Science.gov (United States)

    Acconcia, Giulia; Cominelli, Alessandro; Peronio, Pietro; Rech, Ivan; Ghioni, Massimo

    2017-05-01

    The analysis of optical signals by means of Single Photon Avalanche Diodes (SPADs) has been subject to a widespread interest in recent years. The development of multichannel high-performance Time Correlated Single Photon Counting (TCSPC) acquisition systems has undergone a fast trend. Concerning the detector performance, best in class results have been obtained resorting to custom technologies leading also to a strong dependence of the detector timing jitter from the threshold used to determine the onset of the photogenerated current flow. In this scenario, the avalanche current pick-up circuit plays a key role in determining the timing performance of the TCSPC acquisition system, especially with a large array of SPAD detectors because of electrical crosstalk issues. We developed a new current pick-up circuit based on a transimpedance amplifier structure able to extract the timing information from a 50-μm-diameter custom technology SPAD with a state-of-art timing jitter as low as 32ps and suitable to be exploited with SPAD arrays. In this paper we discuss the key features of this structure and we present a new version of the pick-up circuit that also provides quenching capabilities in order to minimize the number of interconnections required, an aspect that becomes more and more crucial in densely integrated systems.

  6. Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom

    Directory of Open Access Journals (Sweden)

    Hang Song

    2017-01-01

    Full Text Available A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

  7. High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

    Science.gov (United States)

    Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

    2017-04-25

    Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

  8. Integrated analysis of energy transfers in elastic-wave turbulence.

    Science.gov (United States)

    Yokoyama, Naoto; Takaoka, Masanori

    2017-08-01

    In elastic-wave turbulence, strong turbulence appears in small wave numbers while weak turbulence does in large wave numbers. Energy transfers in the coexistence of these turbulent states are numerically investigated in both the Fourier space and the real space. An analytical expression of a detailed energy balance reveals from which mode to which mode energy is transferred in the triad interaction. Stretching energy excited by external force is transferred nonlocally and intermittently to large wave numbers as the kinetic energy in the strong turbulence. In the weak turbulence, the resonant interactions according to the weak turbulence theory produce cascading net energy transfer to large wave numbers. Because the system's nonlinearity shows strong temporal intermittency, the energy transfers are investigated at active and moderate phases separately. The nonlocal interactions in the Fourier space are characterized by the intermittent bundles of fibrous structures in the real space.

  9. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    Science.gov (United States)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  10. Method and apparatus for increasing resistance of bipolar buried layer integrated circuit devices to single-event upsets

    Science.gov (United States)

    Zoutendyk, John A. (Inventor)

    1991-01-01

    Bipolar transistors fabricated in separate buried layers of an integrated circuit chip are electrically isolated with a built-in potential barrier established by doping the buried layer with a polarity opposite doping in the chip substrate. To increase the resistance of the bipolar transistors to single-event upsets due to ionized particle radiation, the substrate is biased relative to the buried layer with an external bias voltage selected to offset the built-in potential just enough (typically between about +0.1 to +0.2 volt) to prevent an accumulation of charge in the buried-layer-substrate junction.

  11. A fast shaping amplifier-comparator integrated circuit for silicon strip detectors

    Energy Technology Data Exchange (ETDEWEB)

    Barberis, E.; Cartiglia, N.; Dorfan, D.E.; Rahn, J.; Spencer, E.N.; Wilder, M. (Univ. of California, Santa Cruz, CA (United States). Santa Cruz Inst. for Particle Physics)

    1993-08-01

    The use of silicon strip detectors at hadron colliders with high collision rates, such as HERA, Fermi Collider Upgrade, and the SSC, presents five stringent requirements for its front-end electronics system. The circuitry must have microminiature size, very low power, fast shaping, near optimum noise, and radiation resistance. The authors describe a 64 channel amplifier-comparator for silicon strip detector fabricated on Tektronix SHPi bipolar process. This device is particularly useful in high rate colliders with silicon strip vertex detection. The design requirements include near optimum noise performance, very low power use, proton radiation resistance, and microminiature size. Additionally, the detector and amplifier can be DC coupled, since the amplifier is capable of absorbing increasing detector leakage current under irradiation. Circuit measurements show that the circuit will perform properly in its expected environment.

  12. Integrated axial and tangential serpentine cooling circuit in a turbine airfoil

    Science.gov (United States)

    Lee, Ching-Pang; Jiang, Nan; Marra, John J; Rudolph, Ronald J; Dalton, John P

    2015-05-05

    A continuous serpentine cooling circuit forming a progression of radial passages (44, 45, 46, 47A, 48A) between pressure and suction side walls (52, 54) in a MID region of a turbine airfoil (24). The circuit progresses first axially, then tangentially, ending in a last radial passage (48A) adjacent to the suction side (54) and not adjacent to the pressure side (52). The passages of the axial progression (44, 45, 46) may be adjacent to both the pressure and suction side walls of the airfoil. The next to last radial passage (47A) may be adjacent to the pressure side wall and not adjacent to the suction side wall. The last two radial passages (47A, 48A) may be longer along the pressure and suction side walls respectively than they are in a width direction, providing increased direct cooling surface area on the interiors of these hot walls.

  13. SEMICONDUCTOR INTEGRATED CIRCUITS: An offset-insensitive switched-capacitor bandgap reference with continuous output

    Science.gov (United States)

    Peng, Zheng; Wei, Yan; Ke, Zhang; Wenhong, Li

    2009-08-01

    An improved switched-capacitor bandgap reference with a continuous output voltage of 1.26 V has been implemented with Chartered 0.35-μm 5-V CMOS process. The output offset voltage, induced by non-ideal characteristics of operational amplifier and bias current generator, is suppressed by the proposed sample-and-hold circuit and self-bias technique. Experimental results show that the proposed circuit operates properly under a supply voltage varying from 3 to 5 V. The measured temperature coefficient is 112 ppm/°C and the power supply rejection ratio of output voltage without any filtering capacitor is -40 dB and -33 dB at 100 Hz and 10 MHz, respectively.

  14. Integrated circuits and molecular components for stress and feeding: implications for eating disorders.

    Science.gov (United States)

    Hardaway, J A; Crowley, N A; Bulik, C M; Kash, T L

    2015-01-01

    Eating disorders are complex brain disorders that afflict millions of individuals worldwide. The etiology of these diseases is not fully understood, but a growing body of literature suggests that stress and anxiety may play a critical role in their development. As our understanding of the genetic and environmental factors that contribute to disease in clinical populations like anorexia nervosa, bulimia nervosa and binge eating disorder continue to grow, neuroscientists are using animal models to understand the neurobiology of stress and feeding. We hypothesize that eating disorder clinical phenotypes may result from stress-induced maladaptive alterations in neural circuits that regulate feeding, and that these circuits can be neurochemically isolated using animal model of eating disorders. © 2014 John Wiley & Sons Ltd and International Behavioural and Neural Genetics Society.

  15. High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes

    Science.gov (United States)

    Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

    2017-09-01

    As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

  16. Investigation of a Hybrid Wafer Scale Integration Technique that Mounts Discrete Integrated Circuit Die in a Silicon Substrate.

    Science.gov (United States)

    1988-03-01

    preparation of wafers for the etching study: 1. Chemicals for Standard Clean #1: Sulphuric acid (H 2SO4) Hydrogen Peroxide (H20 2 ) Hydrofluoric Acid (HF) 2...between the die and the substrate, applying a conformal dielectric smoothing layer, and then interconnecting the circuit die using a patterned thin...continued processing. A dielectric polvimide coating is spun-on and cured. Multilevel electrical a- interconnect ions are now possible (3:845-851

  17. Low power current sources for bioimpedance measurements: A comparison between Howland and integrated CMOS OTA circuits

    OpenAIRE

    Pedro Bertemes-Filho; Volney Coelho Vincence; Marcio S Santos; Ilson Xavier Zanatta

    2012-01-01

    Electrical Bioimpedance Analysis has been widely used as a non-invasive technique for characterizing tissues. Most systems use a wideband and a high precision instrumentation, specially the current source. The objective of this work is to compare the Howland circuit with three OTA-based floating voltage controlled current sources. The results show that both Current Conveyor and class-AB OTA have a wider output current frequency response and both output impedance is 226 % bigger than the Howla...

  18. A Physics-Based Heterojunction Bipolar Transistor Model for Integrated Circuit Simulation

    Science.gov (United States)

    1993-12-01

    Conclusions and Recommendations ....... ............... ... 147 Appendix A: Mathcad Files ............ ................... ... A-1 Appendix B: HSPICE...and layer thicknesses. Solutions to the semiconductor physics equations depend on all three types of parameters. Mathcad 3.1 [38] was used to solve...Ebers-Moll or Gummel-Poon junction trensistor equivalent circuit topology. 4.4 Determination of SPICE Model Parameters A Mathcad 3.1 [38] program

  19. Organic integrated circuits for information storage based on ambipolar polymers and charge injection engineering

    Science.gov (United States)

    Dell'Erba, Giorgio; Luzio, Alessandro; Natali, Dario; Kim, Juhwan; Khim, Dongyoon; Kim, Dong-Yu; Noh, Yong-Young; Caironi, Mario

    2014-04-01

    Ambipolar semiconducting polymers, characterized by both high electron (μe) and hole (μh) mobility, offer the advantage of realizing complex complementary electronic circuits with a single semiconducting layer, deposited by simple coating techniques. However, to achieve complementarity, one of the two conduction paths in transistors has to be suppressed, resulting in unipolar devices. Here, we adopt charge injection engineering through a specific interlayer in order to tune injection into frontier energy orbitals of a high mobility donor-acceptor co-polymer. Starting from field-effect transistors with Au contacts, showing a p-type unbalanced behaviour with μh = 0.29 cm2/V s and μe = 0.001 cm2/V s, through the insertion of a caesium salt interlayer with optimized thickness, we obtain an n-type unbalanced transistor with μe = 0.12 cm2/V s and μh = 8 × 10-4 cm2/V s. We applied this result to the development of the basic pass-transistor logic building blocks such as inverters, with high gain and good noise margin, and transmission-gates. In addition, we developed and characterized information storage circuits like D-Latches and D-Flip-Flops consisting of 16 transistors, demonstrating both their static and dynamic performances and thus the suitability of this technology for more complex circuits such as display addressing logic.

  20. Design of CMOS analog integrated fractional-order circuits applications in medicine and biology

    CERN Document Server

    Tsirimokou, Georgia; Elwakil, Ahmed

    2017-01-01

    This book describes the design and realization of analog fractional-order circuits, which are suitable for on-chip implementation, capable of low-voltage operation and electronic adjustment of their characteristics. The authors provide a brief introduction to fractional-order calculus, followed by design issues for fractional-order circuits of various orders and types. The benefits of this approach are demonstrated with current-mode and voltage-mode filter designs. Electronically tunable emulators of fractional-order capacitors and inductors are presented, where the behavior of the corresponding chips fabricated using the AMS 0.35um CMOS process has been experimentally verified. Applications of fractional-order circuits are demonstrated, including a pre-processing stage suitable for the implementation of the Pan-Tompkins algorithm for detecting the QRS complexes of an electrocardiogram (ECG), a fully tunable implementation of the Cole-Cole model used for the modeling of biological tissues, and a simple, non-i...