Industry-Oriented Laboratory Development for Mixed-Signal IC Test Education

Science.gov (United States)

Hu, J.; Haffner, M.; Yoder, S.; Scott, M.; Reehal, G.; Ismail, M.

2010-01-01

The semiconductor industry is lacking qualified integrated circuit (IC) test engineers to serve in the field of mixed-signal electronics. The absence of mixed-signal IC test education at the collegiate level is cited as one of the main sources for this problem. In response to this situation, the Department of Electrical and Computer Engineering at…

Wafer level packaging of MEMS

International Nuclear Information System (INIS)

Esashi, Masayoshi

2008-01-01

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

International Nuclear Information System (INIS)

Khan, M F; Ghavanini, F A; Enoksson, P; Haasl, S; Löfgren, L; Persson, K; Rusu, C; Schjølberg-Henriksen, K

2010-01-01

This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

NARCIS (Netherlands)

Tilmans, H.A.C.; Ziad, H.; Jansen, Henricus V.; Di Monaco, O.; Jourdain, A.; De Raedt, W.; Rottenberg, X.; De Backer, E.; Decoussernaeker, A.; Baert, K.

2001-01-01

Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as

Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

2015-01-01

The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

Directory of Open Access Journals (Sweden)

Azrul Azlan Hamzah

2008-11-01

Full Text Available This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

PELE-IC test problems

International Nuclear Information System (INIS)

Gong, E.Y.; Alexander, E.E.; McMaster, W.H.; Quinones, D.F.

1979-01-01

This report provides prospective users of the Lawrence Livermore Laboratory (LLL) fluid-structure interaction computer code, PELE-IC, a variety of test problems for verifying the code on CDC 7600 computer systems at facilities external to the LLL environment. The test problems have been successfully run on CDC 7600 computers at the LLL and Lawrence Berkeley Laboratory (LBL) computer centers

A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

Science.gov (United States)

Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

2018-03-01

In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each wafer and on every layer during the

Novel SU-8 based vacuum wafer-level packaging for MEMS devices

DEFF Research Database (Denmark)

Murillo, Gonzalo; Davis, Zachary James; Keller, Stephan Urs

2010-01-01

This work presents a simple and low-cost SU-8 based wafer-level vacuum packaging method which is CMOS and MEMS compatible. Different approaches have been investigated by taking advantage of the properties of SU-8, such as chemical resistance, optical transparence, mechanical reliability and versa......This work presents a simple and low-cost SU-8 based wafer-level vacuum packaging method which is CMOS and MEMS compatible. Different approaches have been investigated by taking advantage of the properties of SU-8, such as chemical resistance, optical transparence, mechanical reliability...

Generic test platform for representative tests of safety I/C systems - 15546

International Nuclear Information System (INIS)

Fourestie, B.; Kuck, H.; Richter, J.; Rieche, S.; Waitz, M.

2015-01-01

In compliance with the IEC 61513 safety Instrumentation and Control (I/C) systems must be successfully validated in their final configuration prior to installation on site and commissioning. However the contingent need for modifications during system validation activities or subsequently during the commissioning phase may entail long and costly re-engineering of the I/C systems. With the view to ease these possible modifications, a Generic Test Platform has been developed by AREVA which allows combining a real I/C system subpart with an emulation server. This platform provides a faithful representation of the I/C System allowing crediting the validation test results carried out on this platform. (authors)

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

Science.gov (United States)

Buehler, Martin G.

1988-01-01

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Wafer-level packaging with compression-controlled seal ring bonding

Science.gov (United States)

Farino, Anthony J

2013-11-05

A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

Propagation of resist heating mask error to wafer level

Science.gov (United States)

Babin, S. V.; Karklin, Linard

2006-10-01

As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the

Probing and irradiation tests of ALICE pixel chip wafers and sensors

CERN Document Server

Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

2004-01-01

In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

Prediction of thermo-mechanical reliability of wafer backend processes

NARCIS (Netherlands)

Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; van Driel, W.D.; Hoofman, R.J.O.M.; Ernst, L.J.

2004-01-01

More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

Prediction of thermo-mechanical integrity of wafer backend processes

NARCIS (Netherlands)

Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; Hoofman, R.J.O.M.; Ernst, L.J.; Ernst, L.J.

2003-01-01

More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

Bond strength tests between silicon wafers and duran tubes (fusion bonded fluidic interconnects)

NARCIS (Netherlands)

Fazal, I.; Berenschot, Johan W.; de Boer, J.H.; Jansen, Henricus V.; Elwenspoek, Michael Curt

2005-01-01

The fusion bond strength of glass tubes with standard silicon wafers is presented. Experiments with plain silicon wafers and those coated with silicon oxide and silicon nitride are presented. Results obtained are discussed in terms of homogeneity and strength of fusion bond. High pressure testing

Wafer-level manufacturing technology of glass microlenses

Science.gov (United States)

Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

2014-08-01

In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

Investigation of Surface Pre-Treatment Methods for Wafer-Level Cu-Cu Thermo-Compression Bonding

Directory of Open Access Journals (Sweden)

Koki Tanaka

2016-12-01

Full Text Available To increase the yield of the wafer-level Cu-Cu thermo-compression bonding method, certain surface pre-treatment methods for Cu are studied which can be exposed to the atmosphere before bonding. To inhibit re-oxidation under atmospheric conditions, the reduced pure Cu surface is treated by H2/Ar plasma, NH3 plasma and thiol solution, respectively, and is covered by Cu hydride, Cu nitride and a self-assembled monolayer (SAM accordingly. A pair of the treated wafers is then bonded by the thermo-compression bonding method, and evaluated by the tensile test. Results show that the bond strengths of the wafers treated by NH3 plasma and SAM are not sufficient due to the remaining surface protection layers such as Cu nitride and SAMs resulting from the pre-treatment. In contrast, the H2/Ar plasma–treated wafer showed the same strength as the one with formic acid vapor treatment, even when exposed to the atmosphere for 30 min. In the thermal desorption spectroscopy (TDS measurement of the H2/Ar plasma–treated Cu sample, the total number of the detected H2 was 3.1 times more than the citric acid–treated one. Results of the TDS measurement indicate that the modified Cu surface is terminated by chemisorbed hydrogen atoms, which leads to high bonding strength.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

Science.gov (United States)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Wafer-level chip-scale packaging analog and power semiconductor applications

CERN Document Server

Qu, Shichun

2015-01-01

This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

Science.gov (United States)

Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

2013-12-03

In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

OpenAIRE

Zhuhao Gong; Yulong Zhang; Xin Guo; Zewen Liu

2018-01-01

A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to gener...

Examination of optimum test conditions for a 3-point bending and cutting test to evaluate sound emission of wafer during deformation

Directory of Open Access Journals (Sweden)

Erdem Carsanba

2018-04-01

Full Text Available The purpose of this study was to investigate optimum test conditions of acoustical-mechanical measurement of wafer analysed by Acoustic Envelope Detector attached to the Texture Analyser. Force-displacement and acoustic signals were simultaneously recorded applying two different methods (3-point bending and cutting test. In order to study acoustical-mechanical behaviour of wafers, the parameters “maximum sound pressure”, “total count peaks” and “mean sound value” were used and optimal test conditions of microphone position and test speed were examined. With a microphone position of 45° angle and 1 cm distance and at a low test speed of 0.5 mm/s wafers of different quality could be distinguished best. The angle of microphone did not have significant effect on acoustic results and the number of peaks of the force and acoustic signal decreased with increasing distance and test speed.

Self-adaptive phosphor coating technology for wafer-level scale chip packaging

International Nuclear Information System (INIS)

Zhou Linsong; Rao Haibo; Wang Wei; Wan Xianlong; Liao Junyuan; Wang Xuemei; Zhou Da; Lei Qiaolin

2013-01-01

A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP. (semiconductor devices)

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

International Nuclear Information System (INIS)

Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

2014-01-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

Elevated voltage level I{sub DDQ} failure testing of integrated circuits

Science.gov (United States)

Righter, A.W.

1996-05-21

Burn in testing of static CMOS IC`s is eliminated by I{sub DDQ} testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip. 4 figs.

Optical transceiver ICs based on 3D die-stacking of opto-electronic devices

NARCIS (Netherlands)

Duan, P.; Raz, O.; Smalbrugge, B.E.; Plassche, van de K.L.; Dorren, H.J.S.

2013-01-01

Wafer scale fabrication of the 3D stacked transceivers is discussed. Uniform open eye patterns at 10 Gb/s/channel of both 3D stacked transmitter and receiver ICs indicates that the interconnection technology is robust.

Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

Science.gov (United States)

Gagnard, Xavier; Bonnaud, Olivier

2000-08-01

We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

Science.gov (United States)

Lee, Jeffrey; McGarvey, Steve

2013-04-01

The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the

Prediction of fracture toughness K/sub Ic/ of steel from Charpy impact test results

Energy Technology Data Exchange (ETDEWEB)

Iwadate, Tadao; Tanaka, Yasuhiko; Takemata, Hiroyuki; Terashima, Shuhei

1986-08-01

This paper presents a method to predict the fracture toughness K/sub Ic/ and/or K/sub Id/ of steels using their Charpy impact test results and tensile properties. The fracture toughness, Charpy impact and tensile properties of 2 1/4 Cr-1Mo, ASTM A508 Cl.1, A508 Cl.2 A508 Cl.3 and A533 Gr.B Cl.1 steels were measured and analysed on the basis of the excess temperature (test temperature minus FATT) and Rolfe-Novak correlation. The relationship between K/sub Ic//K/sub Ic-us/ and the excess temperature, where K/sub Ic-us/ is the upper-shelf fracture toughness K/sub Ic/ predicted by Rolfe-Novak correlation, discloses that the K/sub Ic/ transition curves of several steels are representable by only one trend curve of K/sub Ic//K/sub Ic-us/ or K/sub Id//K/sub Id-us/ versus excess temperature relation. This curve is denoted as a ''master curve''. By using this curve, the fracture toughness of steel can be predicted using Charpy impact and tensile test results. By taking account of the scattering of both the fracture toughness and Charpy impact test results, the confidence limits of the master curve were also determined. Another approach to develop more general procedure of predicting the fracture toughness K/sub Ic/ is also discussed.

A wafer-level 3D packaging structure with Benzocyclobutene as a dielectric for multichip module fabrication

International Nuclear Information System (INIS)

Geng Fei; Ding Xiaoyun; Xu Gaowei; Luo Le

2009-01-01

A new wafer-level 3D packaging structure with Benzocyclobutene (BCB) as interlayer dielectrics (ILDs) for multichip module fabrication is proposed for application in the Ku-band wave. The packaging structure consists of two layers of BCB films and three layers of metallized films, in which the monolithic microwave IC (MMIC), thin film resistors, striplines and microstrip lines are integrated. Wet etched cavities fabricated on the silicon substrate are used for mounting active and passive components. BCB layers cover the components and serve as ILDs for interconnections. Gold bumps are used as electric interconnections between different layers, which eliminates the need to prepare vias by costly dry etching and deposition processes. In order to get high-quality BCB films for the subsequent chemical mechanical planarization (CMP) and multilayer metallization processes, the BCB curing profile is optimized and the roughness of the BCB film after the CMP process is kept lower than 10 nm. The thermal, mechanical and electrical properties of the packaging structure are investigated. The thermal resistance can be controlled below 2 0 C/W. The average shear strength of the gold bumps on the BCB surface is around 70 N/mm 2 . The performances of MMIC and interconnection structure at high frequencies are optimized and tested. The S-parameters curves of the packaged MMIC shift slightly showing perfect transmission character. The insertion loss change after the packaging process is less than 1 dB range at the operating frequency and the return loss is less than -8 dB from 10 to 15 GHz.

Evaluation of accelerated test parameters for CMOS IC total dose hardness prediction

International Nuclear Information System (INIS)

Sogoyan, A.V.; Nikiforov, A.Y.; Chumakov, A.I.

1999-01-01

The approach to accelerated test parameters evaluation is presented in order to predict CMOS IC total dose behavior in variable dose-rate environment. The technique is based on the analytical model of MOSFET parameters total dose degradation. The simple way to estimate model parameter is proposed using IC's input-output MOSFET radiation test results. (authors)

Tests of a silicon wafer based neutron collimator

International Nuclear Information System (INIS)

Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

2001-01-01

A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

Tests of a silicon wafer based neutron collimator

CERN Document Server

Cussen, L D; Anderson, I S; Hoeghoj, P

2001-01-01

A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

Simulation of design dependent failure exposure levels for CMOS ICs

International Nuclear Information System (INIS)

Kaul, N.; Bhuva, B.L.; Rangavajjhala, V.; van der Molen, H.; Kerns, S.E.

1990-01-01

The total dose exposure of CMOS ICs introduces bias-dependent parameter shifts in individual devices. The bias dependency of individual parameter shifts of devices cause different designs to behave differently under identical testing conditions. This paper studies the effect of design and bias on the radiation tolerance of ICs and presents an automated design tool that produces different designs for a logic function, and presents important parameters of each design to circuit designer for trade off analysis

Automotive SOI-BCD Technology Using Bonded Wafers

International Nuclear Information System (INIS)

Himi, H.; Fujino, S.

2008-01-01

The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

Elevated voltage level I.sub.DDQ failure testing of integrated circuits

Science.gov (United States)

Righter, Alan W.

1996-01-01

Burn in testing of static CMOS IC's is eliminated by I.sub.DDQ testing at elevated voltage levels. These voltage levels are at least 25% higher than the normal operating voltage for the IC but are below voltage levels that would cause damage to the chip.

Polymer-based 2D/3D wafer level heterogeneous integration for SSL module

NARCIS (Netherlands)

Yuan, C.; Wei, J.; Ye, H.; Koh, S.; Harianto, S.; Nieuwenhof, M.A. van den; Zhang, G.Q.

2012-01-01

This paper demonstrates a heterogeneous integration of solid state lighting (SSL) module, including light source (LED) and driver/control components. Such integration has been realized by the polymer-based reconfigured wafer level package technologies and such structure has been prototyped and

A wafer-level multi-chip module process with thick photosensitive benzocyclobutene as the dielectric for microwave application

International Nuclear Information System (INIS)

Tang, Jiajie; Sun, Xiaowei; Luo, Le

2011-01-01

A wafer-level microwave multi-chip module (MMCM) packaging process is presented. Thick photosensitive-benzocyclobutene (photo-BCB) polymer (about 25 µm/layer) is used as the dielectric for its simplified process and the capability of obtaining desirable electrical, chemical and mechanical properties at high frequencies. The MMCM packaging structure contains a monolithic microwave integrated circuit (MMIC) chip embedded in a lossy-silicon wafer, a microwave band-pass filter (BPF) and two layers of BCB/Au interconnection. Key processes of fabrication are described in detail. The non-uniformity of BCB film and the sidewall angle of the via-holes for inter-layer connection are tested. Via-chains prepared by metal/BCB multilayer structures are tested through the Kelvin test structure to investigate the resistances of inter-layer connection. The average value is measured to be 73.5 mΩ. The electrical characteristic of this structure is obtained by a microwave transmission performance test from 15 to 30 GHz. The measurement results show good consistency between the bare MMIC die and the packaged die in the test frequency band. The gain of the MMIC chip after packaging is better than 18 dB within the designed operating frequency range (from 23 to 25 GHz). When the packaged MMIC chip is connected to a BPF, the maximum gain is still measured to reach 11.95 dB at 23.8 GHz

Synchronizing decentralized control loops for overall performance enhancement : a Youla framework applied to a wafer scanner

NARCIS (Netherlands)

Evers, E.; van de Wal, M.M.J.; Oomen, T.A.E.

2017-01-01

Manufacturing equipment often consists of multiple subsystems. For instance, in lithographic IC manufacturing, both a reticle stage and a wafer stage move synchronously. Traditionally, these subsystems are divided into manageable subproblems, at the expense of a suboptimal overall solution. The aim

Reliable four-point flexion test and model for die-to-wafer direct bonding

Energy Technology Data Exchange (ETDEWEB)

Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.; Moriceau, H. [Univ. Grenoble Alpes, F-38000 Grenoble, France and CEA, LETI, MINATEC Campus, F-38054 Grenoble (France)

2015-07-07

For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, both D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.

A wafer mapping technique for residual stress in surface micromachined films

International Nuclear Information System (INIS)

Schiavone, G; Murray, J; Smith, S; Walton, A J; Desmulliez, M P Y; Mount, A R

2016-01-01

The design of MEMS devices employing movable structures is crucially dependant on the mechanical behaviour of the deposited materials. It is therefore important to be able to fully characterize the micromachined films and predict with confidence the mechanical properties of patterned structures. This paper presents a characterization technique that enables the residual stress in MEMS films to be mapped at the wafer level by using microstructures released by surface micromachining. These dedicated MEMS test structures and the associated measurement techniques are used to extract localized information on the strain and Young’s modulus of the film under investigation. The residual stress is then determined by numerically coupling this data with a finite element analysis of the structure. This paper illustrates the measurement routine and demonstrates it with a case study using electrochemically deposited alloys of nickel and iron, particularly prone to develop high levels of residual stress. The results show that the technique enables wafer mapping of film non-uniformities and identifies wafer-to-wafer differences. A comparison between the results obtained from the mapping technique and conventional wafer bow measurements highlights the benefits of using a procedure tailored to films that are non-uniform, patterned and surface-micromachined, as opposed to simple standard stress extraction methods. The presented technique reveals detailed information that is generally unexplored when using conventional stress extraction methods such as wafer bow measurements. (paper)

Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

Science.gov (United States)

Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

2018-07-01

This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

International Nuclear Information System (INIS)

Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

2006-01-01

A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

Science.gov (United States)

Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

2005-01-01

Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

Wafer-Level Patterned and Aligned Polymer Nanowire/Micro- and Nanotube Arrays on any Substrate

KAUST Repository

Morber, Jenny Ruth

2009-05-25

A study was conducted to fabricate wafer-level patterned and aligned polymer nanowire (PNW), micro- and nanotube arrays (PNT), which were created by exposing the polymer material to plasma etching. The approach for producing wafer-level aligned PNWs involved a one-step inductively coupled plasma (ICP) reactive ion etching process. The polymer nanowire array was fabricated in an ICP reactive ion milling chamber with a pressure of 10mTorr. Argon (Ar), O 2, and CF4 gases were released into the chamber as etchants at flow rates of 15 sccm, 10 sccm, and 40 sccm. Inert gasses, such as Ar-form positive ions were incorporated to serve as a physical component to assist in the material degradation process. One power source (400 W) was used to generate dense plasma from the input gases, while another power source applied a voltage of approximately 600V to accelerate the plasma toward the substrate.

Wafer-level hermetic thermo-compression bonding using electroplated gold sealing frame planarized by fly-cutting

Science.gov (United States)

Farisi, Muhammad Salman Al; Hirano, Hideki; Frömel, Jörg; Tanaka, Shuji

2017-01-01

In this paper, a novel wafer-level hermetic packaging technology for heterogeneous device integration is presented. Hermetic sealing is achieved by low-temperature thermo-compression bonding using electroplated Au micro-sealing frame planarized by single-point diamond fly-cutting. The proposed technology has significant advantages compared to other established processes in terms of integration of micro-structured wafer, vacuum encapsulation and electrical interconnection, which can be achieved at the same time. Furthermore, the technology is also achievable for a bonding frame width as narrow as 30 μm, giving it an advantage from a geometry perspective, and bonding temperatures as low as 300 °C, making it advantageous for temperature-sensitive devices. Outgassing in vacuum sealed cavities is studied and a cavity pressure below 500 Pa is achieved by introducing annealing steps prior to bonding. The pressure of the sealed cavity is measured by zero-balance method utilizing diaphragm-structured bonding test devices. The leak rate into the packages is determined by long-term sealed cavity pressure measurement for 1500 h to be less than 2.0× {{10}-14} Pa m3s-1. In addition, the bonding shear strength is also evaluated to be higher than 100 MPa.

IC modelling in the IRSN EPR level 1 PSA

International Nuclear Information System (INIS)

Delache, J.

2012-01-01

Today in France, an EPR (European Pressurized Water Reactor) Unit is under construction at the Flamanville site. The creation authorization was granted in April 2007 and the plant commissioning is planned for 2012. The plant operator (EDF) provided for the construction license several PSA (Probabilistic Safety Assessment) studies. IRSN, as TSO (Technical Safety Organisation), wishes to dispose of the appropriate knowledge and tools for the independent verification of the operator studies and so developed its own model of PSA level 1. The goal is not to rebuild the plant operator PSA (with a full scope...) but to dispose of a simplified model able to clearly point out specific important issues. In the IRSN model a particular effort has recently been done on the Digital IC modelling. The IC (Instrumentation and Control) is modelled in the IRSN EPR PSA by using Fault Trees. Instead, EDF EPR PSA applies the COMPACT model to simplify the command and instrumentation logics. The IRSN model is more detailed in order to be more accurate in the global analysis of the Digital IC. For instance the communication ways between automates are considered as well as the failure of support systems. The model is still under development mainly in order to define the CCF (Common Cause Failure) which may be considered. (authors)

Increasing reticle inspection efficiency and reducing wafer print-checks using automated defect classification and simulation

Science.gov (United States)

Ryu, Sung Jae; Lim, Sung Taek; Vacca, Anthony; Fiekowsky, Peter; Fiekowsky, Dan

2013-09-01

IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the "requal" phase for extended, non-productive periods of time. The overall "requal" cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs. Fortunately, a software program has been developed which automates defect classification with simulated printability measurement greatly reducing requal cycle time and improving overall disposition accuracy. This product, called ADAS (Auto Defect Analysis System), has been tested in both engineering and high-volume production environments with very successful results. In this paper, data is presented supporting significant reduction for costly wafer print checks, improved inspection area productivity, and minimized risk of misclassified yield limiting defects.

Guided ultrasonic wave beam skew in silicon wafers

Science.gov (United States)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2018-04-01

In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster

OpenAIRE

Zoschke, Kai; Güttler, Maurice; Böttcher, Lars; Grübl, Andreas; Husmann, Dan; Schemmel, Johannes; Meier, Karlheinz; Ehrmann, Oswin

2018-01-01

Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the KIP and the associated hardware requirements which drove the described technological developments. In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a ...

Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology

International Nuclear Information System (INIS)

Cao Yuhan; Luo Le

2009-01-01

A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu 6 Sn 5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 x 10 -9 atm cc/s are possible, meeting the demands of MIL-STD-883E. (semiconductor technology)

Coaxial twin-shaft magnetic fluid seals applied in vacuum wafer-handling robot

Science.gov (United States)

Cong, Ming; Wen, Haiying; Du, Yu; Dai, Penglei

2012-07-01

Compared with traditional mechanical seals, magnetic fluid seals have unique characters of high airtightness, minimal friction torque requirements, pollution-free and long life-span, widely used in vacuum robots. With the rapid development of Integrate Circuit (IC), there is a stringent requirement for sealing wafer-handling robots when working in a vacuum environment. The parameters of magnetic fluid seals structure is very important in the vacuum robot design. This paper gives a magnetic fluid seal device for the robot. Firstly, the seal differential pressure formulas of magnetic fluid seal are deduced according to the theory of ferrohydrodynamics, which indicate that the magnetic field gradient in the sealing gap determines the seal capacity of magnetic fluid seal. Secondly, the magnetic analysis model of twin-shaft magnetic fluid seals structure is established. By analyzing the magnetic field distribution of dual magnetic fluid seal, the optimal value ranges of important parameters, including parameters of the permanent magnetic ring, the magnetic pole tooth, the outer shaft, the outer shaft sleeve and the axial relative position of two permanent magnetic rings, which affect the seal differential pressure, are obtained. A wafer-handling robot equipped with coaxial twin-shaft magnetic fluid rotary seals and bellows seal is devised and an optimized twin-shaft magnetic fluid seals experimental platform is built. Test result shows that when the speed of the two rotational shafts ranges from 0-500 r/min, the maximum burst pressure is about 0.24 MPa. Magnetic fluid rotary seals can provide satisfactory performance in the application of wafer-handling robot. The proposed coaxial twin-shaft magnetic fluid rotary seal provides the instruction to design high-speed vacuum robot.

Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

Directory of Open Access Journals (Sweden)

Zhuhao Gong

2018-02-01

Full Text Available A radio-frequency micro-electro-mechanical system (RF MEMS wafer-level packaging (WLP method using pre-patterned benzo-cyclo-butene (BCB polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to generate the housing cavity, the BCB sealing ring was protected by a sputtered Cr/Au (chromium/gold layer. The average measured thickness of the BCB layer was 5.9 μm. In contrast to the conventional methods of spin-coating BCB after fabricating cavities, the pre-patterned BCB method presented BCB bonding layers with better quality on severe topography surfaces in terms of increased uniformity of thickness and better surface flatness. The observation of the bonded layer showed that no void or gap formed on the protruding coplanar waveguide (CPW lines. A shear strength test was experimentally implemented as a function of the BCB widths in the range of 100–400 μm. The average shear strength of the packaged device was higher than 21.58 MPa. A RF MEMS switch was successfully packaged using this process with a negligible impact on the microwave characteristics and a significant improvement in the lifetime from below 10 million to over 1 billion. The measured insertion loss of the packaged RF MEMS switch was 0.779 dB and the insertion loss deterioration caused by the package structure was less than 0.2 dB at 30 GHz.

Si-to-Si wafer bonding using evaporated glass

DEFF Research Database (Denmark)

Reus, Roger De; Lindahl, M.

1997-01-01

Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

NARCIS (Netherlands)

Rajaraman, V.; Pakula, L.S.; Pham, H.T.M.; Sarro, P.M.; French, P.J.

2009-01-01

This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide

Modelling deformation and fracture in confectionery wafers

Energy Technology Data Exchange (ETDEWEB)

Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

2015-01-22

The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

Trace analysis for 300 MM wafers and processes with TXRF

International Nuclear Information System (INIS)

Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

2000-01-01

Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

The Implications Related to Different IC, Different Projects and Different Thinking Addressing the Common Core of IC

DEFF Research Database (Denmark)

Lindgren, Peter; Saghaug, Kristin Margrethe

2009-01-01

challenge the development of IC: - The IC at the organizational level seems to diminish when innovation gets highly dispersed and is operated outside the core of the organization - The attractiveness of the organization to different ICA, which is one fundament to sustainable and successful innovation, seems...... to fall when the IC at the organizational core level diminishes The objective of this paper is therefore to understand 1) How the IC at the organizational core level may continue to be developed, when at the same time innovation is taking place in dispersed groups and projects. 2) How to motivate...... the different ICA´s to bring learning and knowledge back to the core with the purpose to develop IC at the organizational core level....

Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

International Nuclear Information System (INIS)

Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

2006-01-01

The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

Science.gov (United States)

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

2013-09-01

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging

International Nuclear Information System (INIS)

Lee, Ju-Yong; Lee, Sung-Woo; Lee, Seung-Ki; Park, Jae-Hyoung

2013-01-01

We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 mΩ. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test. (paper)

Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

DEFF Research Database (Denmark)

Rasmussen, Frank Engel; Frech, J.; Heschel, M.

2003-01-01

A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr...

Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

Science.gov (United States)

Turner, K. T.; Spearing, S. M.

2002-12-01

Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

Accurate characterization of wafer bond toughness with the double cantilever specimen

Science.gov (United States)

Turner, Kevin T.; Spearing, S. Mark

2008-01-01

The displacement loaded double cantilever test, also referred to as the "Maszara test" and the "crack opening method" by the wafer bonding community, is a common technique used to evaluate the interface toughness or surface energy of direct wafer bonds. While the specimen is widely used, there has been a persistent question as to the accuracy of the method since the actual specimen geometry differs from the ideal beam geometry assumed in the expression used for data reduction. The effect of conducting the test on whole wafer pairs, in which the arms of cantilevers are wide plates rather than slender beams, is examined in this work using finite element analysis. A model is developed to predict the equilibrium shape of the crack front and to develop a corrected expression for calculating interface toughness from crack length measurements obtained in tests conducted on whole wafer pairs. The finite element model, which is validated through comparison to experiments, demonstrates that using the traditional beam theory-based expressions for data reduction can lead to errors of up to 25%.

Palladium-based on-wafer electroluminescence studies of GaN-based LED structures

Energy Technology Data Exchange (ETDEWEB)

Salcianu, C.O.; Thrush, E.J.; Humphreys, C.J. [Department of Materials Science and Metallurgy, University of Cambridge, Pembroke Street, Cambridge CB2 3QZ (United Kingdom); Plumb, R.G. [Centre for Photonic Systems, Department of Engineering, University of Cambridge, Cambridge CB3 0FD (United Kingdom); Boyd, A.R.; Rockenfeller, O.; Schmitz, D.; Heuken, M. [AIXTRON AG, Kackertstr. 15-17, 52072 Aachen (Germany)

2008-07-01

Electroluminescence (EL) testing of Light Emitting Diode (LED) structures is usually done at the chip level. Assessing the optical and electrical properties of LED structures at the wafer scale prior to their processing would improve the cost effectiveness of producing LED-lamps. A non-destructive method for studying the luminescence properties of the structure at the wafer-scale is photoluminescence (PL). However, the relationship between the on-wafer PL data and the final device EL can be less than straightforward (Y. H Aliyu et al., Meas. Sci. Technol. 8, 437 (1997)) as the two techniques employ different carrier injection mechanisms. This paper provides an overview of some different techniques in which palladium is used as a contact in order to obtain on-wafer electroluminescence information which could be used to screen wafers prior to processing into final devices. Quick mapping of the electrical and optical characteristics was performed using either palladium needle electrodes directly, or using the latter in conjunction with evaporated palladium contacts to inject both electrons and holes into the active region via the p-type capping layer of the structure. For comparison, indium was also used to make contact to the n-layer so that electrons could be directly injected into that layer. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Electrical Interconnections Through CMOS Wafers

DEFF Research Database (Denmark)

Rasmussen, Frank Engel

2003-01-01

Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

Science.gov (United States)

Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

2017-10-01

Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

Study of Si wafer surfaces irradiated by gas cluster ion beams

International Nuclear Information System (INIS)

Isogai, H.; Toyoda, E.; Senda, T.; Izunome, K.; Kashima, K.; Toyoda, N.; Yamada, I.

2007-01-01

The surface structures of Si (1 0 0) wafers subjected to gas cluster ion beam (GCIB) irradiation have been analyzed by cross-sectional transmission electron microscopy (XTEM) and atomic force microscopy (AFM). GCIB irradiation is a promising technique for both precise surface etching and planarization of Si wafers. However, it is very important to understand the crystalline structure of Si wafers after GCIB irradiation. An Ar-GCIB used for the physically sputtering of Si atoms and a SF 6 -GCIB used for the chemical etching of the Si surface are also analyzed. The GCIB irradiation increases the surface roughness of the wafers, and amorphous Si layers are formed on the wafer surface. However, when the Si wafers are annealed in hydrogen at a high temperature after the GCIB irradiation, the surface roughness decreases to the same level as that before the irradiation. Moreover, the amorphous Si layers disappear completely

High throughput batch wafer handler for 100 to 200 mm wafers

International Nuclear Information System (INIS)

Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

1989-01-01

A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

Simplified design of IC amplifiers

CERN Document Server

Lenk, John

1996-01-01

Simplified Design of IC Amplifiers has something for everyone involved in electronics. No matter what skill level, this book shows how to design and experiment with IC amplifiers. For experimenters, students, and serious hobbyists, this book provides sufficient information to design and build IC amplifier circuits from 'scratch'. For working engineers who design amplifier circuits or select IC amplifiers, the book provides a variety of circuit configurations to make designing easier.Provides basics for all phases of practical design.Covers the most popular forms for amplif

Utilizing an Adaptive Grey Model for Short-Term Time Series Forecasting: A Case Study of Wafer-Level Packaging

Directory of Open Access Journals (Sweden)

Che-Jung Chang

2013-01-01

Full Text Available The wafer-level packaging process is an important technology used in semiconductor manufacturing, and how to effectively control this manufacturing system is thus an important issue for packaging firms. One way to aid in this process is to use a forecasting tool. However, the number of observations collected in the early stages of this process is usually too few to use with traditional forecasting techniques, and thus inaccurate results are obtained. One potential solution to this problem is the use of grey system theory, with its feature of small dataset modeling. This study thus uses the AGM(1,1 grey model to solve the problem of forecasting in the pilot run stage of the packaging process. The experimental results show that the grey approach is an appropriate and effective forecasting tool for use with small datasets and that it can be applied to improve the wafer-level packaging process.

A 45° saw-dicing process applied to a glass substrate for wafer-level optical splitter fabrication for optical coherence tomography

Science.gov (United States)

Maciel, M. J.; Costa, C. G.; Silva, M. F.; Gonçalves, S. B.; Peixoto, A. C.; Ribeiro, A. Fernando; Wolffenbuttel, R. F.; Correia, J. H.

2016-08-01

This paper reports on the development of a technology for the wafer-level fabrication of an optical Michelson interferometer, which is an essential component in a micro opto-electromechanical system (MOEMS) for a miniaturized optical coherence tomography (OCT) system. The MOEMS consists on a titanium dioxide/silicon dioxide dielectric beam splitter and chromium/gold micro-mirrors. These optical components are deposited on 45° tilted surfaces to allow the horizontal/vertical separation of the incident beam in the final micro-integrated system. The fabrication process consists of 45° saw dicing of a glass substrate and the subsequent deposition of dielectric multilayers and metal layers. The 45° saw dicing is fully characterized in this paper, which also includes an analysis of the roughness. The optimum process results in surfaces with a roughness of 19.76 nm (rms). The actual saw dicing process for a high-quality final surface results as a compromise between the dicing blade’s grit size (#1200) and the cutting speed (0.3 mm s-1). The proposed wafer-level fabrication allows rapid and low-cost processing, high compactness and the possibility of wafer-level alignment/assembly with other optical micro components for OCT integrated imaging.

Note on a simple test method for estimaing J/sub Ic/

International Nuclear Information System (INIS)

Whipple, T.A.; McHenry, H.I.

1980-01-01

Fracture toughness testing is generally a time-consuming and expensive procedure; therefore, there has been a significant amount of effort directed toward developing an inexpensive and rapid method of estimating the fracture toughness of materials. In this paper, a simple method for estimating J/sub Ic/ through the use of small, notched, bend bars is evaluated. The test only involves the measurement of the energy necessary to fracture the sample. Initial tests on Fe-18Cr-3Ni-13Mn and 304L stainless steel at 76 and 4 0 K have yielded results consistent with other fracture toughness tests, for materials in the low- to medium-toughness range

Jsub(Ic)-testing of A-533 B - statistical evaluation of some different testing techniques

International Nuclear Information System (INIS)

Nilsson, F.

1978-01-01

The purpose of the present study was to compare statistically some different methods for the evaluation of fracture toughness of the nuclear reactor material A-533 B. Since linear elastic fracture mechanics is not applicable to this material at the interesting temperature (275 0 C), the so-called Jsub(Ic) testing method was employed. Two main difficulties are inherent in this type of testing. The first one is to determine the quantity J as a function of the deflection of the three-point bend specimens used. Three different techniques were used, the first two based on the experimentally observed input of energy to the specimen and the third employing finite element calculations. The second main problem is to determine the point when crack growth begins. For this, two methods were used, a direct electrical method and the indirect R-curve method. A total of forty specimens were tested at two laboratories. No statistically significant different results were obtained from the respective laboratories. The three methods of calculating J yielded somewhat different results, although the discrepancy was small. Also the two methods of determination of the growth initiation point yielded consistent results. The R-curve method, however, exhibited a larger uncertainty as measured by the standard deviation. The resulting Jsub(Ic) value also agreed well with earlier presented results. The relative standard deviation was of the order of 25%, which is quite small for this type of experiment. (author)

Development of thin film measurement program of wafer for spin etcher

International Nuclear Information System (INIS)

Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

2001-01-01

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

Development of thin film measurement program of wafer for spin etcher

Energy Technology Data Exchange (ETDEWEB)

Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

2001-11-15

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

The next generation in optical transport semiconductors: IC solutions at the system level

Science.gov (United States)

Gomatam, Badri N.

2005-02-01

In this tutorial overview, we survey some of the challenging problems facing Optical Transport and their solutions using new semiconductor-based technologies. Advances in 0.13um CMOS, SiGe/HBT and InP/HBT IC process technologies and mixed-signal design strategies are the fundamental breakthroughs that have made these solutions possible. In combination with innovative packaging and transponder/transceiver architectures IC approaches have clearly demonstrated enhanced optical link budgets with simultaneously lower (perhaps the lowest to date) cost and manufacturability tradeoffs. This paper will describe: *Electronic Dispersion Compensation broadly viewed as the overcoming of dispersion based limits to OC-192 links and extending link budgets, *Error Control/Coding also known as Forward Error Correction (FEC), *Adaptive Receivers for signal quality monitoring for real-time estimation of Q/OSNR, eye-pattern, signal BER and related temporal statistics (such as jitter). We will discuss the theoretical underpinnings of these receiver and transmitter architectures, provide examples of system performance and conclude with general market trends. These Physical layer IC solutions represent a fundamental new toolbox of options for equipment designers in addressing systems level problems. With unmatched cost and yield/performance tradeoffs, it is expected that IC approaches will provide significant flexibility in turn, for carriers and service providers who must ultimately manage the network and assure acceptable quality of service under stringent cost constraints.

Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications

International Nuclear Information System (INIS)

Ngo, H-D; Hiess, Andre; Seidemann, Volker; Studzinski, Daniel; Lange, Martin; Leib, Juergen; Shariff, Dzafir; Ashraf, Huma; Steel, Mike; Atabo, Lilian; Reast, Jon

2006-01-01

This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained and plasma configurations are described elsewhere. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters

Irregular Dwarf Galaxy IC 1613

Science.gov (United States)

2005-01-01

Ultraviolet image (left) and visual image (right) of the irregular dwarf galaxy IC 1613. Low surface brightness galaxies, such as IC 1613, are more easily detected in the ultraviolet because of the low background levels compared to visual wavelengths.

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

Science.gov (United States)

Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

2015-01-01

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

Wafer-level hermetic vacuum packaging by bonding with a copper-tin thin film sealing ring

Science.gov (United States)

Akashi, Teruhisa; Funabashi, Hirofumi; Takagi, Hideki; Omura, Yoshiteru; Hata, Yoshiyuki

2018-04-01

A wafer-level hermetic vacuum packaging technology intended for use with MEMS devices was developed based on a copper-tin (CuSn) thin film sealing ring. To allow hermetic packaging, the shear strength of the CuSn thin film bond was improved by optimizing the pretreatment conditions. As a result, an average shear strength of 72.3 MPa was obtained and a cavity that had been hermetically sealed using wafer-level packaging (WLP) maintained its vacuum for 1.84 years. The total pressures in the cavities and the partial pressures of residual gases were directly determined with an ultra-low outgassing residual gas analyzer (RGA) system. Hermeticity was evaluated based on helium leak rates, which were calculated from helium pressures determined with the RGA system. The resulting data showed that a vacuum cavity following 1.84 years storage had a total pressure of 83.1 Pa, contained argon as the main residual gas and exhibited a helium leak rate as low as 1.67  ×  10-17 Pa · m3 s-1, corresponding to an air leak rate of 6.19  ×  10-18 Pa · m3 s-1. The RGA data demonstrate that WLP using a CuSn thin film sealing ring permits ultra-high hermeticity in conjunction with long-term vacuum packaging that is applicable to MEMS devices.

Multiproject wafers: not just for million-dollar mask sets

Science.gov (United States)

Morse, Richard D.

2003-06-01

With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

Energy Technology Data Exchange (ETDEWEB)

Anon.

2014-09-15

The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

Molded, wafer level optics for long wave infra-red applications

Science.gov (United States)

Franks, John

2016-05-01

For many years, the Thermal Imaging market has been driven by the high volume consumer market. The first signs of this came with the launch of night vision systems for cars, first by Cadillac and Honda and then, more successfully by BMW, Daimler and Audi. For the first time, simple thermal imaging systems were being manufactured at the rate of more than 10,000 units a year. This step change in volumes enabled a step change in system costs, with thermal imaging moving into the consumer's price range. Today we see that the consumer awareness and the consumer market continues to increase with the launch of a number of consumer focused smart phone add-ons. This has brought a further step change in system costs, with the possibility to turn your mobile phone into a thermal imager for under $250. As the detector technology has matured, the pixel pitches have dropped from 50μm in 2002 to 12 μm or even 10μm in today's detectors. This dramatic shrinkage in size has had an equally dramatic effect on the optics required to produce the image on the detector. A moderate field of view that would have required a focal length of 40mm in 2002 now requires a focal length of 8mm. For wide field of view applications and small detector formats, focal lengths in the range 1mm to 5mm are becoming common. For lenses, the quantity manufactured, quality and costs will require a new approach to high volume Infra-Red (IR) manufacturing to meet customer expectations. This, taken with the SwaP-C requirements and the emerging requirement for very small lenses driven by the new detectors, suggests that wafer scale optics are part of the solution. Umicore can now present initial results from an intensive research and development program to mold and coat wafer level optics, using its chalcogenide glass, GASIR®.

Wafer-scale micro-optics fabrication

Science.gov (United States)

Voelkel, Reinhard

2012-07-01

Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

CERN Document Server

Bronuzzi, J.; Moll, M.; Sallese, J.M.

2016-01-01

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

High-κ Al{sub 2}O{sub 3} material in low temperature wafer-level bonding for 3D integration application

Energy Technology Data Exchange (ETDEWEB)

Fan, J., E-mail: fanji@hust.edu.cn; Tu, L. C. [MOE Key Laboratory of Fundamental Physical Quantities Measurement, School of Physics, Huazhong University of Science and Technology, Wuhan 430074 (China); Tan, C. S. [School of Electrical and Electronics Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

2014-03-15

This work systematically investigated a high-κ Al{sub 2}O{sub 3} material for low temperature wafer-level bonding for potential applications in 3D microsystems. A clean Si wafer with an Al{sub 2}O{sub 3} layer thickness of 50 nm was applied as our experimental approach. Bonding was initiated in a clean room ambient after surface activation, followed by annealing under inert ambient conditions at 300 °C for 3 h. The investigation consisted of three parts: a mechanical support study using the four-point bending method, hermeticity measurements using the helium bomb test, and thermal conductivity analysis for potential heterogeneous bonding. Compared with samples bonded using a conventional oxide bonding material (SiO{sub 2}), a higher interfacial adhesion energy (∼11.93 J/m{sup 2}) and a lower helium leak rate (∼6.84 × 10{sup −10} atm.cm{sup 3}/sec) were detected for samples bonded using Al{sub 2}O{sub 3}. More importantly, due to the excellent thermal conductivity performance of Al{sub 2}O{sub 3}, this technology can be used in heterogeneous direct bonding, which has potential applications for enhancing the performance of Si photonic integrated devices.

Wafer scale oblique angle plasma etching

Science.gov (United States)

Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

2017-05-23

Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

Laser wafering for silicon solar

International Nuclear Information System (INIS)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-01-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

Laser wafering for silicon solar.

Energy Technology Data Exchange (ETDEWEB)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

Carbon dioxide capture using resin-wafer electrodeionization

Science.gov (United States)

Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

2015-09-08

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

SEM probe of IC radiation sensitivity

Science.gov (United States)

Gauthier, M. K.; Stanley, A. G.

1979-01-01

Scanning Electron Microscope (SEM) used to irradiate single integrated circuit (IC) subcomponent to test for radiation sensitivity can localize area of IC less than .03 by .03 mm for determination of exact location of radiation sensitive section.

Dynamical Competition of IC-Industry Clustering from Taiwan to China

Science.gov (United States)

Tsai, Bi-Huei; Tsai, Kuo-Hui

2009-08-01

Most studies employ qualitative approach to explore the industrial clusters; however, few research has objectively quantified the evolutions of industry clustering. The purpose of this paper is to quantitatively analyze clustering among IC design, IC manufacturing as well as IC packaging and testing industries by using the foreign direct investment (FDI) data. The Lotka-Volterra system equations are first adopted here to capture the competition or cooperation among such three industries, thus explaining their clustering inclinations. The results indicate that the evolution of FDI into China for IC design industry significantly inspire the subsequent FDI of IC manufacturing as well as IC packaging and testing industries. Since IC design industry lie in the upstream stage of IC production, the middle-stream IC manufacturing and downstream IC packing and testing enterprises tend to cluster together with IC design firms, in order to sustain a steady business. Finally, Taiwan IC industry's FDI amount into China is predicted to cumulatively increase, which supports the industrial clustering tendency for Taiwan IC industry. Particularly, the FDI prediction of Lotka-Volterra model performs superior to that of the conventional Bass model after the forecast accuracy of these two models are compared. The prediction ability is dramatically improved as the industrial mutualism among each IC production stage is taken into account.

Methane production using resin-wafer electrodeionization

Science.gov (United States)

Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

2014-03-25

The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

Improving IC process efficiency with critical materials management

Science.gov (United States)

Hanson, Kathy L.; Andrews, Robert E.

2003-06-01

The management of critical materials in a high technology manufacturing facility is crucial to obtaining consistently high production yield. This is especially true in an industry like semiconductors where the success of the product is so dependent on the integrity of the critical production materials. Bar code systems, the traditional management tools, are voluntary, defeatable, and do not continuously monitor materials when in use. The significant costs associated with mis-management of chemicals can be captured with a customized model resulting in highly favorable ROI"s for the NOWTrak RFID chemical management system. This system transmits reliable chemical data about each individual container and generates information that can be used to increase wafer production efficiency and yield. The future of the RFID system will expand beyond the benefits of chemical management and into dynamic IC process management

In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

Science.gov (United States)

Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

2013-01-01

Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

Temperature Dependent Electrical Properties of PZT Wafer

Science.gov (United States)

Basu, T.; Sen, S.; Seal, A.; Sen, A.

2016-04-01

The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

Porous solid ion exchange wafer for immobilizing biomolecules

Science.gov (United States)

Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

2007-12-11

A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

K/sub Ic/ and J/sub Ic/ of Westerly granite: effects of thickness and in-plane dimensions

International Nuclear Information System (INIS)

Schmidt, R.A.; Lutz, T.J.

1978-01-01

An investigation is described in which tensile properties, fracture toughness, and critical J integral are measured for Westerly granite, a rock that is widely used in rock mechanics studies. This was primarily a parameter sensitivity study in which the effects of specimen dimensions and testing techniques were assessed. It is hoped that this study will aid in establishing tentative standards and guidelines for fracture toughness testing of rock as well as indicate the feasibility of using a J integral fracture criterion for this material. ASTM standard specimen configurations of the compact and bend types were tested with compact specimens ranging in width from W = 25.4 mm to W = 406.4 mm (0.5T to 8T) and with thickness ranging from 13 mm to 100 mm. A series of 4T compact specimens were tested to assess the effects of thickness and fatigue precracking. Techniques are described that enable several values of K/sub Ic/, a complete J vs crack growth curve, and a J/sub Ic/ value to be obtained from each sample. Direct-pull tension tests on shaped specimens of Westerly granite are described which indicate a high degree of nonlinear, inelastic behavior. This fact raises questions about the use of LEFM, but the J/sub Ic/ data presented appear to validate the K/sub Ic/ measurements

Wafer bonding applications and technology

CERN Document Server

Gösele, Ulrich

2004-01-01

During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

Science.gov (United States)

Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

2012-05-01

In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

Science.gov (United States)

Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

2013-03-01

The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

System level ESD protection

CERN Document Server

Vashchenko, Vladislav

2014-01-01

This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection.  It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD...

Assessing the organizational context for EBP implementation: the development and validity testing of the Implementation Climate Scale (ICS).

Science.gov (United States)

Ehrhart, Mark G; Aarons, Gregory A; Farahnak, Lauren R

2014-10-23

Although the importance of the organizational environment for implementing evidence-based practices (EBP) has been widely recognized, there are limited options for measuring implementation climate in public sector health settings. The goal of this research was to develop and test a measure of EBP implementation climate that would both capture a broad range of issues important for effective EBP implementation and be of practical use to researchers and managers seeking to understand and improve the implementation of EBPs. Participants were 630 clinicians working in 128 work groups in 32 US-based mental health agencies. Items to measure climate for EBP implementation were developed based on past literature on implementation climate and other strategic climates and in consultation with experts on the implementation of EBPs in mental health settings. The sample was randomly split at the work group level of analysis; half of the sample was used for exploratory factor analysis (EFA), and the other half was used for confirmatory factor analysis (CFA). The entire sample was utilized for additional analyses assessing the reliability, support for level of aggregation, and construct-based evidence of validity. The EFA resulted in a final factor structure of six dimensions for the Implementation Climate Scale (ICS): 1) focus on EBP, 2) educational support for EBP, 3) recognition for EBP, 4) rewards for EBP, 5) selection for EBP, and 6) selection for openness. This structure was supported in the other half of the sample using CFA. Additional analyses supported the reliability and construct-based evidence of validity for the ICS, as well as the aggregation of the measure to the work group level. The ICS is a very brief (18 item) and pragmatic measure of a strategic climate for EBP implementation. It captures six dimensions of the organizational context that indicate to employees the extent to which their organization prioritizes and values the successful implementation of EBPs

Wafer-level vacuum packaged resonant micro-scanning mirrors for compact laser projection displays

Science.gov (United States)

Hofmann, Ulrich; Oldsen, Marten; Quenzer, Hans-Joachim; Janes, Joachim; Heller, Martin; Weiss, Manfred; Fakas, Georgios; Ratzmann, Lars; Marchetti, Eleonora; D'Ascoli, Francesco; Melani, Massimiliano; Bacciarelli, Luca; Volpi, Emilio; Battini, Francesco; Mostardini, Luca; Sechi, Francesco; De Marinis, Marco; Wagner, Bernd

2008-02-01

Scanning laser projection using resonant actuated MEMS scanning mirrors is expected to overcome the current limitation of small display size of mobile devices like cell phones, digital cameras and PDAs. Recent progress in the development of compact modulated RGB laser sources enables to set up very small laser projection systems that become attractive not only for consumer products but also for automotive applications like head-up and dash-board displays. Within the last years continuous progress was made in increasing MEMS scanner performance. However, only little is reported on how mass-produceability of these devices and stable functionality even under harsh environmental conditions can be guaranteed. Automotive application requires stable MEMS scanner operation over a wide temperature range from -40° to +85°Celsius. Therefore, hermetic packaging of electrostatically actuated MEMS scanning mirrors becomes essential to protect the sensitive device against particle contamination and condensing moisture. This paper reports on design, fabrication and test of a resonant actuated two-dimensional micro scanning mirror that is hermetically sealed on wafer level. With resonant frequencies of 30kHz and 1kHz, an achievable Theta-D-product of 13mm.deg and low dynamic deformation <20nm RMS it targets Lissajous projection with SVGA-resolution. Inevitable reflexes at the vacuum package surface can be seperated from the projection field by permanent inclination of the micromirror.

P/N InP solar cells on Ge wafers

Science.gov (United States)

Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

1994-01-01

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

Penggunaan Limbah Kopi Sebagai Bahan Penyusun Ransum Itik Peking dalam Bentuk Wafer Ransum Komplit

Directory of Open Access Journals (Sweden)

Muhammad Daud

2013-04-01

Full Text Available Effect of coffee waste as component of compiler ration peking duck in the form of wafer complete ration ABSTRACT. Coffee waste is a by-product of coffee processing that potential to be used as feed stuff for peking duck. The weakness of this coffee waste, among others, is perishable, voluminous (bulky and the availability was fluctuated so the processing technology is needed to make this vegetable waste to be durable, easy to stored and to be given to livestock. To solve this problem vegetable waste could be formed as wafer. This research was conducted to study effectiveness of coffee waste as component of compiler ration peking duck in the form of wafer complete ration This experiment was run in completely randomized design which consist of 4 feed treatment and 3 replications.  Ration used was consisted of  P0 = wafer complete ration 0% coffee waste (control, P1 = wafer complete ration 2,5% coffee waste, P2 = wafer complete ration 5% coffee waste, and P3 = Wafer complete ration 7,5% coffee waste. The Variables observed were: physical characteristic (aroma, color, and wafer density and palatability of wafer complete ration. Data collected was analyzed with ANOVA and Duncan Range Test would be used if the result was significantly different. The result showed that the density of wafer complete ration coffee waste was significantly (P< 0.05 differences between of treatment. Mean density wafer complete ration equal to: P0= 0,52±0,03, P1 =0,67±0,04, P2 =0,72±0,03, and P3 = 0,76±0.05 g/cm3. Wafer complete ration coffee waste palatability was significantly (P< 0.05 differences between of treatment. It is concluded that of wafer complete ration composition 5 and 7,5% coffee waste was significantly wafer palatability and gave a highest wafer density. The ration P0 was the most palatable compare to other treatments for the experimental peking duck.

Lamb wave propagation in monocrystalline silicon wafers.

Science.gov (United States)

Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

2018-01-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

120 mm Single-crystalline perovskite and wafers: towards viable applications

Institute of Scientific and Technical Information of China (English)

Yucheng Liu; Bo Wang; Qingbo Wei; Fengwei Xiao; Haibo Fan; Hao Deng; Liangping Deng; Shengzhong (Frank) Liu; Xiaodong Ren; Jing Zhang; Zhou Yang; Dong Yang; Fengyang Yu; Jiankun Sun; Changming Zhao; Zhun Yao

2017-01-01

As the large single-crystalline silicon wafers have revolutionized many industries including electronics and solar cells,it is envisioned that the availability of large single-crystalline perovskite crystals and wafers will revolutionize its broad applications in photovoltaics,optoelectronics,lasers,photodetectors,light emitting diodes (LEDs),etc.Here we report a method to grow large single-crystalline perovskites including single-halide crystals:CH3NH3PbX3 (X=Ⅰ,Br,Cl),and dual-halide ones:CH3NH3Pb(ClxBr1-x)3 and CH3NH3Pb(BrxI1-x)3,with the largest crystal being 120 mm in length.Meanwhile,we have advanced a process to slice the large perovskite crystals into thin wafers.It is found that the wafers exhibit remarkable features:(1) its trap-state density is a million times smaller than that in the microcrystalline perovskite thin films (MPTF);(2) its carrier mobility is 410 times higher than its most popular organic counterpart P3HT;(3) its optical absorption is expanded to as high as 910 nm comparing to 797 nm for the MPTF;(4) while MPTF decomposes at 150 ℃,the wafer is stable at high temperature up to 270 ℃;(5) when exposed to high humidity (75％ RH),MPTF decomposes in 5 h while the wafer shows no change for overnight;(6) its photocurrent response is 250 times higher than its MPTF counterpart.A few electronic devices have been fabricated using the crystalline wafers.Among them,the Hall test gives low carrier concentration with high mobility.The trap-state density is measured much lower than common semiconductors.Moreover,the large SC-wafer is found particularly useful for mass production of integrated circuits.By adjusting the halide composition,both the optical absorption and the light emission can be fine-tuned across the entire visible spectrum from 400 nm to 800 nm.It is envisioned that a range of visible lasers and LEDs may be developed using the dual-halide perovskites.With fewer trap states,high mobility,broader absorption,and humidity resistance,it is

JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

International Nuclear Information System (INIS)

Montoya, Angela C.; Maji, Arup K.

2010-01-01

There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

Output blue light evaluation for phosphor based smart white LED wafer level packages.

Science.gov (United States)

Kolahdouz, Zahra; Rostamian, Ali; Kolahdouz, Mohammadreza; Ma, Teng; van Zeijl, Henk; Zhang, Kouchi

2016-02-22

This study presents a blue light detector for evaluating the output light of phosphor based white LED package. It is composed of a silicon stripe-shaped photodiode designed and implemented in a 2 μm BiCMOS process which can be used for wafer level integration of different passive and active devices all in just 5 lithography steps. The final device shows a high selectivity to blue light. The maximum responsivity at 480 nm is matched with the target blue LED illumination. The designed structure have better responsivity compared to simple photodiode structure due to reducing the effect of dead layer formation close to the surface because of implantation. It has also a two-fold increase in the responsivity and quantum efficiency compared to previously similar published sensors.

Nonuniformities of electrical resistivity in undoped 6H-SiC wafers

International Nuclear Information System (INIS)

Li, Q.; Polyakov, A.Y.; Skowronski, M.; Sanchez, E.K.; Loboda, M.J.; Fanton, M.A.; Bogart, T.; Gamble, R.D.

2005-01-01

Chemical elemental analysis, temperature-dependent Hall measurements, deep-level transient spectroscopy, and contactless resistivity mapping were performed on undoped semi-insulating (SI) and lightly nitrogen-doped conducting 6H-SiC crystals grown by physical vapor transport (PVT). Resistivity maps of commercial semi-insulating SiC wafers revealed resistivity variations across the wafers between one and two orders of magnitude. Two major types of variations were identified. First is the U-shape distribution with low resistivity in the center and high in the periphery of the wafer. The second type had an inverted U-shape distribution. Secondary-ion-mass spectrometry measurements of the distribution of nitrogen concentration along the growth axis and across the wafers sliced from different locations of lightly nitrogen-doped 6H-SiC boules were conducted. The measured nitrogen concentration gradually decreased along the growth direction and from the center to the periphery of the wafers. This change gives rise to the U-like distribution of resistivity in wafers of undoped SI-SiC. The concentrations of deep electron traps exhibited similar dependence. Compensation of nitrogen donors by these traps can result in the inverted U-like distribution of resistivity. Possible reasons for the observed nonuniformities include formation of a (0001) facet in PVT growth coupled with orientation-dependent nitrogen incorporation, systematic changes of the gas phase composition, and increase of the deposition temperature during boule growth

Dead-time free pixel readout architecture for ATLAS front-end IC

CERN Document Server

Einsweiler, Kevin F; Kleinfelder, S A; Luo, L; Marchesini, R; Milgrome, O; Pengg, F X

1999-01-01

A low power sparse scan readout architecture has been developed for the ATLAS pixel front-end IC. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address $9 of the hits associating them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The $9 events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 mu HP process to meet the $9 requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC provides dead-time-less ambiguity free readout at 40 MHz data rate.

Fabrication and Characterization of Capacitive Micromachined Ultrasonic Transducers with Low-Temperature Wafer Direct Bonding

Directory of Open Access Journals (Sweden)

Xiaoqing Wang

2016-12-01

Full Text Available This paper presents a fabrication method of capacitive micromachined ultrasonic transducers (CMUTs by wafer direct bonding, which utilizes both the wet chemical and O2plasma activation processes to decrease the bonding temperature to 400 °C. Two key surface properties, the contact angle and surface roughness, are studied in relation to the activation processes, respectively. By optimizing the surface activation parameters, a surface roughness of 0.274 nm and a contact angle of 0° are achieved. The infrared images and static deflection of devices are assessed to prove the good bonding effect. CMUTs having silicon membranes with a radius of 60 μm and a thickness of 2 μm are fabricated. Device properties have been characterized by electrical and acoustic measurements to verify their functionality and thus to validate this low-temperature process. A resonant frequency of 2.06 MHz is obtained by the frequency response measurements. The electrical insertion loss and acoustic signal have been evaluated. This study demonstrates that the CMUT devices can be fabricated by low-temperature wafer direct bonding, which makes it possible to integrate them directly on top of integrated circuit (IC substrates.

Low-cost silicon wafer dicing using a craft cutter

KAUST Repository

Fan, Yiqiang

2014-05-20

This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

CERN Multimedia

Honma, Alan

1999-01-01

Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

Using the Climbing Drum Peel (CDP) Test to Obtain a G(sub IC) value for Core/Facesheet Bonds

Science.gov (United States)

Nettles, A. T.; Gregory, Elizabeth D.; Jackson, Justin R.

2006-01-01

A method of measuring the Mode I fracture toughness of core/facesheet bonds in sandwich Structures is desired, particularly with the widespread use of models that need this data as input. This study examined if a critical strain energy release rate, G(sub IC), can be obtained from the climbing drum peel (CDP) test. The CDP test is relatively simple to perform and does not rely on measuring small crack lengths such as required by the double cantilever beam (DCB) test. Simple energy methods were used to calculate G(sub IC) from CDP test data on composite facesheets bonded to a honeycomb core. Facesheet thicknesses from 2 to 5 plies were tested to examine the upper and lower bounds on facesheet thickness requirements. Results from the study suggest that the CDP test, with certain provisions, can be used to find the GIG value of a core/facesheet bond.

Noncontact sheet resistance measurement technique for wafer inspection

Science.gov (United States)

Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

1995-12-01

A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

DEFF Research Database (Denmark)

Mackenzie, David; Buron, Jonas Christian Due; Whelan, Patrick Rebsdorf

2015-01-01

Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140......-effect mobility, doping level, on–off ratio, and conductance minimum before and after laser ablation fabrication....

Modeling the wafer temperature profile in a multiwafer LPCVD furnace

Energy Technology Data Exchange (ETDEWEB)

Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

1994-01-01

A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

Directory of Open Access Journals (Sweden)

Lim SCB

2013-04-01

Full Text Available Stephen CB Lim,1,3 Michael J Paech,2 Bruce Sunderland,3 Yandi Liu3 1Pharmacy Department, Armadale Health Service, Armadale, 2School of Medicine and Pharmacology, University of Western Australia, and Department of Anaesthesia and Pain Medicine, King Edward Memorial Hospital for Women, Subiaco, 3School of Pharmacy, Curtin Health Innovation Research Institute, Curtin University, Perth, WA, Australia Background: The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods: The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results: In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion: These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. Keywords: absolute bioavailability, fentanyl wafer, in vitro dissolution, in vivo study, pharmacokinetics, sublingual

Qualification of multi-crystalline silicon wafers by optical imaging for industrial use

Energy Technology Data Exchange (ETDEWEB)

Janssen, G.J.M.; Van der Borg, N.J.C.M.; Manshanden, P.; De Bruijne, M.; Bende, E.E. [ECN Solar Energy, Petten (Netherlands)

2012-09-15

We have developed a method to qualify multi-crystalline silicon (mc-Si) wafers that are being used in a production process. An optical image of an etched wafer is made. This etching can be a standard industrial acid etching for mc-Si wafers as is commonly used for saw damage removal and simultaneous iso-texturing. Digital image processing is then applied to identify the number of dislocations and their distribution over the wafer. This information is used as input for a cell performance prediction model, where the performance is characterized by the open circuit voltage (Voc) or the efficiency. The model can include various levels of sophistication, i.e. from using an average density of dislocations to the full spatial resolution of the dislocations in a 2D simulation that includes also the metallization pattern on the cell. The predicted performance is then evaluated against pre-selected criteria. The possibility to apply this optical qualification method in an initial stage in the production enables early rejection of the wafers, further tailoring of the cell production process or identification of instabilities in the production process.

Surface etching technologies for monocrystalline silicon wafer solar cells

Science.gov (United States)

Tang, Muzhi

With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

On the design and implementation of a wafer yield editor

NARCIS (Netherlands)

Pineda de Gyvez, J.; Jess, J.A.G.

1989-01-01

An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and

Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

International Nuclear Information System (INIS)

Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

2013-01-01

The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

Preliminary I&C Design for LORELEI

International Nuclear Information System (INIS)

Korotkin, S.; Kaufman, Y.; Guttmann, E. B.; Levy, S.; Amidan, D.; Gdalyho, B.; Cahana, T.; Ellenbogen, A.; Arad, M.; Weiss, Y.; Sasson, A.; Ferry, L.; Bourrelly, F.; Cohen, Y.

2014-01-01

This document summarizes the preliminary I&C design for LORELEI experiment The preliminary design deals with considerations regarding appropriate safety and service instrumentation. The determined closed loop control rules for temperature and position will be implemented in the detailed design. The Computer Aided Operator Decisions System (CAODS) will be used for prediction of hot spot temperature and thickness of oxidation layer using Baker-Just correlation. The proposed hybrid simulation system comprising of both virtual and real hardware will be in-cooperated for LORELEI verification. It will perform both integration cold tests for a partial hardware loop and virtual tests for the final I&C design

Mod 1 ICS TI Report: ICS Conversion of a 140% HPGe Detector

Energy Technology Data Exchange (ETDEWEB)

Bounds, John Alan [Los Alamos National Lab. (LANL), Los Alamos, NM (United States)

2016-07-05

This report evaluates the Mod 1 ICS, an electrically cooled 140% HPGe detector. It is a custom version of the ORTEC Integrated Cooling System (ICS) modified to make it more practical for us to use in the field. Performance and operating characteristics of the Mod 1 ICS are documented, noting both pros and cons. The Mod 1 ICS is deemed a success. Recommendations for a Mod 2 ICS, a true field prototype, are provided.

Optical cavity furnace for semiconductor wafer processing

Science.gov (United States)

Sopori, Bhushan L.

2014-08-05

An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

Increasing reticle inspection efficiency and reducing wafer printchecks at 14nm using automated defect classification and simulation

Science.gov (United States)

Paracha, Shazad; Goodman, Eliot; Eynon, Benjamin G.; Noyes, Ben F.; Ha, Steven; Kim, Jong-Min; Lee, Dong-Seok; Lee, Dong-Heok; Cho, Sang-Soo; Ham, Young M.; Vacca, Anthony D.; Fiekowsky, Peter J.; Fiekowsky, Daniel I.

2014-10-01

IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the "requal" phase for extended, non-productive periods of time. The overall "requal" cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs An automatic defect analysis system (ADAS), which has been in fab production for numerous years, has been improved to handle the new challenges of 14nm node automate reticle defect classification by simulating each defect's printability under the intended illumination conditions. In this study, we have created programmed defects on a production 14nm node critical-layer reticle. These defects have been analyzed with lithographic simulation software and compared to the results of both AIMS optical simulation and to actual wafer prints.

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

Science.gov (United States)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

Peptide and protein loading into porous silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

2008-02-15

The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Wafer of Intel Pentium 4 Prescott Chips

CERN Multimedia

Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

Wafer edge overlay control solution for N7 and beyond

Science.gov (United States)

van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

2018-03-01

Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

Automated reticle inspection data analysis for wafer fabs

Science.gov (United States)

Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

2009-04-01

To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

International Nuclear Information System (INIS)

Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

2014-01-01

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

Science.gov (United States)

Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

2014-07-07

Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

Contacting graphene in a 200 mm wafer silicon technology environment

Science.gov (United States)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

Controllable laser thermal cleavage of sapphire wafers

Science.gov (United States)

Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

2018-03-01

Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

Eutectic-based wafer-level-packaging technique for piezoresistive MEMS accelerometers and bond characterization using molecular dynamics simulations

Science.gov (United States)

Aono, T.; Kazama, A.; Okada, R.; Iwasaki, T.; Isono, Y.

2018-03-01

We developed a eutectic-based wafer-level-packaging (WLP) technique for piezoresistive micro-electromechanical systems (MEMS) accelerometers on the basis of molecular dynamics analyses and shear tests of WLP accelerometers. The bonding conditions were experimentally and analytically determined to realize a high shear strength without solder material atoms diffusing to adhesion layers. Molecular dynamics (MD) simulations and energy dispersive x-ray (EDX) spectrometry done after the shear tests clarified the eutectic reaction of the solder materials used in this research. Energy relaxation calculations in MD showed that the diffusion of solder material atoms into the adhesive layer was promoted at a higher temperature. Tensile creep MD simulations also suggested that the local potential energy in a solder material model determined the fracture points of the model. These numerical results were supported by the shear tests and EDX analyses for WLP accelerometers. Consequently, a bonding load of 9.8 kN and temperature of 300 °C were found to be rational conditions because the shear strength was sufficient to endure the polishing process after the WLP process and there was little diffusion of solder material atoms to the adhesion layer. Also, eutectic-bonding-based WLP was effective for controlling the attenuation of the accelerometers by determining the thickness of electroplated solder materials that played the role of a cavity between the accelerometers and lids. If the gap distance between the two was less than 6.2 µm, the signal gains for x- and z-axis acceleration were less than 20 dB even at the resonance frequency due to air-damping.

Simulation of SEU transients in CMOS ICs

International Nuclear Information System (INIS)

Kaul, N.; Bhuva, B.L.; Kerns, S.E.

1991-01-01

This paper reports that available analytical models of the number of single-event-induced errors (SEU) in combinational logic systems are not easily applicable to real integrated circuits (ICs). An efficient computer simulation algorithm set, SITA, predicts the vulnerability of data stored in and processed by complex combinational logic circuits to SEU. SITA is described in detail to allow researchers to incorporate it into their error analysis packages. Required simulation algorithms are based on approximate closed-form equations modeling individual device behavior in CMOS logic units. Device-level simulation is used to estimate the probability that ion-device interactions produce erroneous signals capable of propagating to a latch (or n output node), and logic-level simulation to predict the spread of such erroneous, latched information through the IC. Simulation results are compared to those from SPICE for several circuit and logic configurations. SITA results are comparable to this established circuit-level code, and SITA can analyze circuits with state-of-the-art device densities (which SPICE cannot). At all IC complexity levels, SITAS offers several factors of 10 savings in simulation time over SPICE

Growth of misfit dislocation-free p/p+ thick epitaxial silicon wafers on Ge-B-codoped substrates

International Nuclear Information System (INIS)

Jiang Huihua; Yang Deren; Ma Xiangyang; Tian Daxi; Li Liben; Que Duanlin

2006-01-01

The growth of p/p + silicon epitaxial silicon wafers (epi-wafers) without misfit dislocations has been successfully achieved by using heavily boron-doped Czochralski (CZ) silicon wafers codoped with desirable level of germanium as the substrates. The lattice compensation by codoping of germanium and boron into the silicon matrix to reduce the lattice mismatch between the substrate (heavily boron-doped) and epi-layer (lightly boron-doped) is the basic idea underlying in the present achievement. In principle, the codoping of germanium and boron in the CZ silicon can be tailored to achieve misfit dislocation-free epi-layer with required thickness. It is reasonably expected that the presented solution to elimination of misfit dislocations in the p/p + silicon wafers can be applied in the volume production

Wafer plane inspection with soft resist thresholding

Science.gov (United States)

Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

2008-10-01

Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

Thermoelectric properties of boron and boron phosphide CVD wafers

Energy Technology Data Exchange (ETDEWEB)

Kumashiro, Y.; Yokoyama, T.; Sato, A.; Ando, Y. [Yokohama National Univ. (Japan)

1997-10-01

Electrical and thermal conductivities and thermoelectric power of p-type boron and n-type boron phosphide wafers with amorphous and polycrystalline structures were measured up to high temperatures. The electrical conductivity of amorphous boron wafers is compatible to that of polycrystals at high temperatures and obeys Mott`s T{sup -{1/4}} rule. The thermoelectric power of polycrystalline boron decreases with increasing temperature, while that of amorphous boron is almost constant in a wide temperature range. The weak temperature dependence of the thermal conductivity of BP polycrystalline wafers reflects phonon scattering by grain boundaries. Thermal conductivity of an amorphous boron wafer is almost constant in a wide temperature range, showing a characteristic of a glass. The figure of merit of polycrystalline BP wafers is 10{sup -7}/K at high temperatures while that of amorphous boron is 10{sup -5}/K.

PDC IC WELD FAILURE EVALUATION AND RESOLUTION

Energy Technology Data Exchange (ETDEWEB)

Korinko, P.; Howard, S.; Maxwell, D.; Fiscus, J.

2012-04-16

During final preparations for start of the PDCF Inner Can (IC) qualification effort, welding was performed on an automated weld system known as the PICN. During the initial weld, using a pedigree canister and plug, a weld defect was observed. The defect resulted in a hole in the sidewall of the canister, and it was observed that the plug sidewall had not been consumed. This was a new type of failure not seen during development and production of legacy Bagless Transfer Cans (FB-Line/Hanford). Therefore, a team was assembled to determine the root cause and to determine if the process could be improved. After several brain storming sessions (MS and T, R and D Engineering, PDC Project), an evaluation matrix was established to direct this effort. The matrix identified numerous activities that could be taken and then prioritized those activities. This effort was limited by both time and resources (the number of canisters and plugs available for testing was limited). A discovery process was initiated to evaluate the Vendor's IC fabrication process relative to legacy processes. There were no significant findings, however, some information regarding forging/anneal processes could not be obtained. Evaluations were conducted to compare mechanical properties of the PDC canisters relative to the legacy canisters. Some differences were identified, but mechanical properties were determined to be consistent with legacy materials. A number of process changes were also evaluated. A heat treatment procedure was established that could reduce the magnetic characteristics to levels similar to the legacy materials. An in-situ arc annealing process was developed that resulted in improved weld characteristics for test articles. Also several tack welds configurations were addressed, it was found that increasing the number of tack welds (and changing the sequence) resulted in decreased can to plug gaps and a more stable weld for test articles. Incorporating all of the process

Dislocation behavior of surface-oxygen-concentration controlled Si wafers

International Nuclear Information System (INIS)

Asazu, Hirotada; Takeuchi, Shotaro; Sannai, Hiroya; Sudo, Haruo; Araki, Koji; Nakamura, Yoshiaki; Izunome, Koji; Sakai, Akira

2014-01-01

We have investigated dislocation behavior in the surface area of surface-oxygen-concentration controlled Si wafers treated by a high temperature rapid thermal oxidation (HT-RTO). The HT-RTO process allows us to precisely control the interstitial oxygen concentration ([O i ]) in the surface area of the Si wafers. Sizes of rosette patterns, generated by nano-indentation and subsequent thermal annealing at 900 °C for 1 h, were measured for the Si wafers with various [O i ]. It was found that the rosette size decreases in proportion to the − 0.25 power of [O i ] in the surface area of the Si wafers, which were higher than [O i ] of 1 × 10 17 atoms/cm 3 . On the other hand, [O i ] of lower than 1 × 10 17 atoms/cm 3 did not affect the rosette size very much. These experimental results demonstrate the ability of the HT-RTO process to suppress the dislocation movements in the surface area of the Si wafer. - Highlights: • Surface-oxygen-concentration controlled Si wafers have been made. • The oxygen concentration was controlled by high temperature rapid thermal oxidation. • Dislocation behavior in the surface area of the Si wafers has been investigated. • Rosette size decreased with increasing of interstitial oxygen atoms. • The interstitial oxygen atoms have a pinning effect of dislocations at the surface

Non-axisymmetric flexural vibrations of free-edge circular silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Dmitriev, A.V., E-mail: dmitriev@hbar.phys.msu.ru; Gritsenko, D.S.; Mitrofanov, V.P., E-mail: mitr@hbar.phys.msu.ru

2014-02-07

Non-axisymmetric flexural vibrations of circular silicon (111) wafers are investigated. The modes with azimuthal index 2⩽k⩽30 are electrostatically excited and monitored by a capacitive sensor. The splitting of the mode frequencies associated with imperfection of the wafer is observed. The measured loss factors for the modes with 6≲k≲26 are close to those calculated according to the thermoelastic damping theory, while clamping losses likely dominate for k≲6, and surface losses at the level of inverse Q-factor Q{sup −1}≈4×10{sup −6} prevail for the modes with large k. The modes demonstrate nonlinear behavior of mainly geometrical origin at large amplitudes.

Cohesive zone model for direct silicon wafer bonding

Science.gov (United States)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Evaluation of a cyanoacrylate dressing to manage peristomal skin alterations under ostomy skin barrier wafers.

Science.gov (United States)

Milne, Catherine T; Saucier, Darlene; Trevellini, Chenel; Smith, Juliet

2011-01-01

Peristomal skin alterations under ostomy barrier wafers are a commonly reported problem. While a number of interventions to manage this issue have been reported, the use of a topically applied cyanoacrylate has received little attention. This case series describes the use of a topical cyanoacrylate for the management of peristomal skin alterations in persons living with an ostomy. Using a convenience sample, the topical cyanoacrylate dressing was applied to 11 patients with peristomal skin disruption under ostomy wafers in acute care and outpatient settings. The causes of barrier function interruption were also addressed to enhance outcomes. Patients were assessed for wound discomfort using a Likert Scale, time to healing, and number of appliance changes. Patient satisfaction was also examined. Average reported discomfort levels were 9.5 out of 10 at the initial peristomal irritation assessment visit decreased to 3.5 at the first wafer change and were absent by the second wafer change. Wafers had increasing wear time between changes in both settings with acute care patients responding faster. Epidermal resurfacing occurred within 10.2 days in outpatients and within 7 days in acute care patients. Because of the skin sealant action of this dressing, immediate adherence of the wafer was reported at all pouch changes.

First thin AC-coupled silicon strip sensors on 8-inch wafers

Energy Technology Data Exchange (ETDEWEB)

Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

2016-09-11

The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

A study of UO2 wafer fuel for very high-power research reactors

International Nuclear Information System (INIS)

Hsieh, T.C.; Jankus, V.Z.; Rest, J.; Billone, M.C.

1983-01-01

The Reduced Enrichment Research and Test Reactor Program is aimed at reducing fuel enrichment to 2 caramel fuel is one of the most promising new types of reduced-enrichment fuel for use in research reactors with very high power density. Parametric studies have been carried out to determine the maximum specific power attainable without significant fission-gas release for UO 2 wafers ranging from 0.75 to 1.50 mm in thickness. The results indicate that (1) all the fuel designs considered in this study are predicted not to fail under full power operation up to a burnup, of 1.9x10 21 fis/cm 3 ; (2) for all fuel designs, failure is predicted at approximately the same fuel centerline temperature for a given burnup; (3) the thinner the wafer, the wider the margin for fuel specific power between normal operation and increased-power operation leading to fuel failure; (4) increasing the coolant pressure in the reactor core could improve fuel performance by maintaining the fuel at a higher power level without failure for a given burnup; and (5) for a given power level, fuel failure will occur earlier at a higher cladding surface temperature and/or under power-cycling conditions. (author)

Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

Science.gov (United States)

Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

2004-10-01

The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

Silicon wafers for integrated circuit process

OpenAIRE

Leroy , B.

1986-01-01

Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

Directory of Open Access Journals (Sweden)

Bo Xie

2015-09-01

Full Text Available This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months, a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

Transient SEU characterization of analog IC's for ESA's satellite

International Nuclear Information System (INIS)

Harboe-Soerensen, R.; Van Dooren, J.; Guerre, F.X.; Constans, H.; Berger, G.; Hajdas, W.

1999-01-01

Data analysis of four self switch-off power supply events in the SOHO satellite pointed strongly in the direction of being Cosmic Ray or Proton induced. Further analysis of the relevant power supply schematics identified a number of analog IC's capable of causing or contributing to such events. This paper concentrates on the testing aspects of these analog IC's and presents the results of a Single Event Effects (SEEs) test program. Ground testing, simulating the flight conditions, were carried out at both heavy ion and proton accelerators. (authors)

Reticle variation influence on manufacturing line and wafer device performance

Science.gov (United States)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

LENUS (Irish Health Repository)

O'Brien, Deirdre

2012-02-01

A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

LENUS (Irish Health Repository)

O'brien, Deirdre

2010-12-15

A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

High frequency guided wave propagation in monocrystalline silicon wafers

OpenAIRE

Pizzolato, M.; Masserey, B.; Robyr, J. L.; Fromme, P.

2017-01-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full...

Children and IC

Science.gov (United States)

... Cola, and Orange Crush, for example), Kool-Aid, chocolate, and many fruits, fruit juices and drinks (including ... Guideline IC Treatments IC Diet & Self Management Physical Therapy Antidepressants Antihistamines Pentosan Polysulfate Sodium Bladder Instillations Immunosuppresants ...

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

Science.gov (United States)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Direct Electroplating on Highly Doped Patterned Silicon Wafers

NARCIS (Netherlands)

Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

Nickel thin films have been electrodeposited directly on highly doped silicon wafers after removal of the native oxide layer. These substrates conduct sufficiently well to allow deposition using a periferical electrical contact on the wafer. Films 2 μm thick were deposited using a nickel sulfamate

Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

Science.gov (United States)

Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

2018-01-01

Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

A facility for plastic deformation of germanium single-crystal wafers

DEFF Research Database (Denmark)

Lebech, B.; Theodor, K.; Breiting, B.

1998-01-01

. All movements and temperature changes are done by a robot via a PLC-control system. Two nine-crystal focusing monochromators (54 x 116 and 70 x 116 mm(2)) made from 100 wafers with average mosaicity similar to 13' have been constructed. Summaries of the test results are presented. (C) 1998 Elsevier...

Men and IC

Science.gov (United States)

... Bowel Syndrome Lupus Pelvic Floor Dysfunction Pudendal Neuralgia Sjogren’s Syndrome Vulvodynia Newly Diagnosed Toolkit IC Awareness Toolkit Know ... Bowel Syndrome Lupus Pelvic Floor Dysfunction Pudendal Neuralgia Sjogren’s Syndrome Vulvodynia Newly Diagnosed Toolkit IC Awareness Toolkit Know ...

General IC Symptoms

Science.gov (United States)

... Bowel Syndrome Lupus Pelvic Floor Dysfunction Pudendal Neuralgia Sjogren’s Syndrome Vulvodynia Newly Diagnosed Toolkit IC Awareness Toolkit Know ... Bowel Syndrome Lupus Pelvic Floor Dysfunction Pudendal Neuralgia Sjogren’s Syndrome Vulvodynia Newly Diagnosed Toolkit IC Awareness Toolkit Know ...

Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

Science.gov (United States)

Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

2014-06-01

Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

Pregnancy and IC

Science.gov (United States)

... have not already done so, try to identify foods, beverages, and supplements that are irritating to your bladder ... Other Medicines Over-the-counter Medicines Pain Management Management of IC ... Diet Food Diaries Least and Most Bothersome Foods IC-Friendly ...

Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

Science.gov (United States)

Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

2004-08-01

The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

Wafer Cakes of Improved Amino Acid Structure

Directory of Open Access Journals (Sweden)

Roksolana Boidunyk

2017-11-01

Full Text Available The article presents the results of the study of the amino acid composition of newly developed wafer cakes with adipose fillings combined with natural additives. The appropriateness of the using non-traditional raw materials (powder of willow herb, poppy oilcake, carob, as well as skimmed milk powder in order to increase the biological value of wafer cakes and improve their amino acid composition is proven.

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

Science.gov (United States)

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

An electret-based energy harvesting device with a wafer-level fabrication process

DEFF Research Database (Denmark)

Crovetto, Andrea; Wang, Fei; Hansen, Ole

2013-01-01

This paper presents a MEMS energy harvesting device which is able to generate power from two perpendicular ambient vibration directions. A CYTOP polymer is used both as the electret material for electrostatic transduction and as a bonding interface for low-temperature wafer bonding. The device...... is also discussed. With a final chip size of about 1 cm2, a power output of 32.5 nW is successfully harvested with an external load of 17 MΩ, when a harmonic vibration source with an RMS acceleration amplitude of 0.03 g (∼0.3 m s−2) and a resonant frequency of 179 Hz is applied. These results can...

Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

Science.gov (United States)

Sun, Q. M.; Melnikov, A.; Mandelis, A.

2015-06-01

Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

International Nuclear Information System (INIS)

Bronuzzi, J.; Mapelli, A.; Moll, M.; Sallese, J.M.

2016-01-01

In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations.

Development of brain injury criteria (BrIC).

Science.gov (United States)

Takhounts, Erik G; Craig, Matthew J; Moorhouse, Kevin; McFadden, Joe; Hasija, Vikas

2013-11-01

Rotational motion of the head as a mechanism for brain injury was proposed back in the 1940s. Since then a multitude of research studies by various institutions were conducted to confirm/reject this hypothesis. Most of the studies were conducted on animals and concluded that rotational kinematics experienced by the animal's head may cause axonal deformations large enough to induce their functional deficit. Other studies utilized physical and mathematical models of human and animal heads to derive brain injury criteria based on deformation/pressure histories computed from their models. This study differs from the previous research in the following ways: first, it uses two different detailed mathematical models of human head (SIMon and GHBMC), each validated against various human brain response datasets; then establishes physical (strain and stress based) injury criteria for various types of brain injury based on scaled animal injury data; and finally, uses Anthropomorphic Test Devices (ATDs) (Hybrid III 50th Male, Hybrid III 5th Female, THOR 50th Male, ES-2re, SID-IIs, WorldSID 50th Male, and WorldSID 5th Female) test data (NCAP, pendulum, and frontal offset tests) to establish a kinematically based brain injury criterion (BrIC) for all ATDs. Similar procedures were applied to college football data where thousands of head impacts were recorded using a six degrees of freedom (6 DOF) instrumented helmet system. Since animal injury data used in derivation of BrIC were predominantly for diffuse axonal injury (DAI) type, which is currently an AIS 4+ injury, cumulative strain damage measure (CSDM) and maximum principal strain (MPS) were used to derive risk curves for AIS 4+ anatomic brain injuries. The AIS 1+, 2+, 3+, and 5+ risk curves for CSDM and MPS were then computed using the ratios between corresponding risk curves for head injury criterion (HIC) at a 50% risk. The risk curves for BrIC were then obtained from CSDM and MPS risk curves using the linear relationship

High Throughput, High Precision Hot Testing Tool for HBLED Wafer Level Testing

Energy Technology Data Exchange (ETDEWEB)

Solarz, Richard [KLA-Tencor Corporation, Milpitas, CA (United States); McCord, Mark [KLA-Tencor Corporation, Milpitas, CA (United States)

2015-12-31

The Socrates research effort developed an in depth understanding and demonstrated in a prototype tool new precise methods for teh characterization of color characteristics and flux from individual LEDs for the production of uniform quality lighting. This effort was focused on improving the color quality and consistency of solid state lighting and potentially reducing characterization costs for all LED product types. The patented laser hot testing method was demonstrated to be far more accurate than all current state of the art color and flux characterization methods in use by the solid state lighting industry today. A seperately patented LED grouping method (statistical binning) was demonstrated to be a useful approach to improving utilization of entire lots of large color and flux distributions of manufactured LEDs for high quality color solid-state lighting. At the conclusion of the research in late 2015 the solid-state lighting industry was however generally satisfied with its existing production methods for high quality color products for the small segment of customers that demand it, albeit with added costs.

Lamb wave propagation in monocrystalline silicon wafers

OpenAIRE

Fromme, P.; Pizzolato, M.; Robyr, J-L; Masserey, B.

2018-01-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness a...

Characterizing SOI Wafers By Use Of AOTF-PHI

Science.gov (United States)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Extreme low-power mixed signal IC design

CERN Document Server

Tajalli, Armin

2010-01-01

This book describes a completely novel class of techniques for designing ultra-low-power integrated circuits (ICs). In many applications such as battery operated systems and battery-less (energy-scavenging) systems, power dissipation is a critical parameter. As a result, there is a growing demand for reducing the power (energy) consumption in ICs to extremely low levels, not achievable by using classical ""subthreshold CMOS"" techniques. This book introduces a new family of ""subthreshold circuits"" called ""source-coupled circuits"". This family of circuits can be used for implementing digita

I-line stepper based overlay evaluation method for wafer bonding applications

Science.gov (United States)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

Abundances of Planetary Nebulae IC 418, IC 2165 and NGC 5882

NARCIS (Netherlands)

Pottasch, [No Value; Bernard-Salas, J; Beintema, DA; Feibelman, WA

The ISO and IUE spectra of the elliptical nebulae NGC 5882, IC 418 and IC 2165 are presented. These spectra are combined with the spectra in the visual wavelength region to obtain a complete, extinction corrected, spectrum. The chemical composition of the nebulae is then calculated and compared to

Making Porous Luminescent Regions In Silicon Wafers

Science.gov (United States)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Sol-gel bonding of silicon wafers

International Nuclear Information System (INIS)

Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

2005-01-01

Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

Wafer plane inspection for advanced reticle defects

Science.gov (United States)

Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

2008-05-01

Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

A Review on Key Issues and Challenges in Devices Level MEMS Testing

Directory of Open Access Journals (Sweden)

Muhammad Shoaib

2016-01-01

Full Text Available The present review provides information relevant to issues and challenges in MEMS testing techniques that are implemented to analyze the microelectromechanical systems (MEMS behavior for specific application and operating conditions. MEMS devices are more complex and extremely diverse due to the immersion of multidomains. Their failure modes are distinctive under different circumstances. Therefore, testing of these systems at device level as well as at mass production level, that is, parallel testing, is becoming very challenging as compared to the IC test, because MEMS respond to electrical, physical, chemical, and optical stimuli. Currently, test systems developed for MEMS devices have to be customized due to their nondeterministic behavior and complexity. The accurate measurement of test systems for MEMS is difficult to quantify in the production phase. The complexity of the device to be tested required maturity in the test technique which increases the cost of test development; this practice is directly imposed on the device cost. This factor causes a delay in time-to-market.

Low-cost silicon wafer dicing using a craft cutter

KAUST Repository

Fan, Yiqiang; Carreno, Armando Arpys Arevalo; Li, Huawei; Foulds, Ian G.

2014-01-01

feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared

The uses of Man-Made diamond in wafering applications

Science.gov (United States)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

RD53A Integrated Circuit Specifications

CERN Document Server

Garcia-Sciveres, Mauricio

2015-01-01

Specifications for the RD53 collaboration’s first engineering wafer run of an integrated circuit (IC) for hybrid pixel detector readout, called RD53A. RD53A is intended to demonstrate in a large format IC the suitability of the technology (including radiation tolerance), the stable low threshold operation, and the high hit and trigger rate capabilities, required for HL-LHC upgrades of ATLAS and CMS. The wafer scale production will permit the experiments to prototype bump bonding assembly with realistic sensors in this new technology and to measure the performance of hybrid assemblies. RD53A is not intended to be a final production IC for use in an experiment, and will contain design variations for testing purposes, making the pixel matrix non-uniform.

Study of the semiconductor properties by irradiation, 8. Study of trapping center by. gamma. -ray on Si wafer

Energy Technology Data Exchange (ETDEWEB)

Nakamura, Koji; Shioya, Hitoshi; Nagamatsu, Yasuhiko; Ogura, Shoji [Miyazaki Univ. (Japan). Faculty of Engineering

1983-08-01

In order to know the effects of ..gamma..-ray irradiation on n-type Si-wafers, the author did ..gamma..-ray irradiation experiments on n-type Si-wafers. They then observed the trapping center by using DLTS and ICTS equipments. The trapping center level, which is produced by ..gamma..-ray, is about 0.49 eV. In addition, the authors discuss the recombination rate.

Packaging of MEMS/MOEMS and nanodevices: reliability, testing, and characterization aspects

Science.gov (United States)

Tekin, Tolga; Ngo, Ha-Duong; Wittler, Olaf; Bouhlal, Bouchaib; Lang, Klaus-Dieter

2011-02-01

The last decade witnessed an explosive growth in research and development efforts devoted to MEMS devices and packaging. The successfully developed MEMS devices are, for example inkjet, pressure sensors, silicon microphones, accelerometers, gyroscopes, MOEMS, micro fuel cells and emerging MEMS. For the next decade, MEMS/MOEMS and nanodevice based products will penetrate into IT, telecommunications, automotive, defense, life sciences, medical and implantable applications. Forecasts say the MEMS market to be $14 billion by 2012. The packaging cost of MEMS/MOEMS products in general is about 70 percent. Unlike today's electronics IC packaging, their packaging are custom-built and difficult due to the moving structural elements. In order for the moving elements of a MEMS device to move effectively in a well-controlled atmosphere, hermetic sealing of the MEMS device in a cap is necessary. For some MEMS devices, such as resonators and gyroscopes, vacuum packaging is required. Usually, the cap is processed at the wafer level, and thus MEMS packaging is truly a wafer level packaging. In terms of MEMS/MOEMS and nanodevice packaging, there are still many critical issues need to be addressed due to the increasing integration density supported by 3D heterogeneous integration of multi-physic components/layers consisting of photonics, electronics, rf, plasmonics, and wireless. The infrastructure of MEMS/MOEMS and nanodevices and their packaging is not well established yet. Generic packaging platform technologies are not available. Some of critical issues have been studied intensively in the last years. In this paper we will discuss about processes, reliability, testing and characterization of MEMS/MOEMS and nanodevice packaging.

Current status of ITER I&C system as integration begins

Energy Technology Data Exchange (ETDEWEB)

Davis, William, E-mail: william.davis@iter.org [ITER Organisation, Route de Vinon-sur Verdon, CS 90 046, 13067 St. Paul Lez Durance Cedex (France); Wallander, Anders [ITER Organisation, Route de Vinon-sur Verdon, CS 90 046, 13067 St. Paul Lez Durance Cedex (France); Yonekawa, Izuru [Nippon Advanced Technology Ltd., 3129-45 Hibara Muramatsu, Tokai, Naka-gun, Ibaraki 319-1112 (Japan)

2016-11-15

Highlights: • The ITER I&C system is organisationally complicated and technically challenging. • Standard technologies for the ITER I&C systems have been selected. • Supply of non-standard technologies will cause serious issues. • Differing levels of design maturity of plant I&C systems is a serious challenge. • Systems are in the final stages of design and are being delivered to site. - Abstract: The ITER I&C system is organisationally complicated and technically challenging, and integrating its many sub-systems into a single coherent system is critical for the ITER project to meet its objectives. This paper explains the integration risks being faced now and anticipated in the near future. Standardisation initiatives by the ITER central team to mitigate these risks are described. The paper also presents the architecture of the ITER I&C system, the current status of design and manufacture key developments made in recent years, and the current and future activities of the central I&C teams. Finally, a short description is given of the plant I&C systems that will be delivered to ITER in the near future.

Edge printability: techniques used to evaluate and improve extreme wafer edge printability

Science.gov (United States)

Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

2004-05-01

The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

CMOS Analog IC Design: Fundamentals

OpenAIRE

Bruun, Erik

2018-01-01

This book is intended for use as the main textbook for an introductory course in CMOS analog integrated circuit design. It is aimed at electronics engineering students who have followed basic courses in mathematics, physics, circuit theory, electronics and signal processing. It takes the students directly from a basic level to a level where they can start working on simple analog IC design projects or continue their studies using more advanced textbooks in the field. A distinct feature of thi...

Wafer-shape metrics based foundry lithography

Science.gov (United States)

Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

2017-03-01

As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

Science.gov (United States)

Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

2016-03-01

With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

Science.gov (United States)

Ostapenko, S.; Tarasov, I.

2000-04-01

A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

Wiping frictional properties of electrospun hydrophobic/hydrophilic polyurethane nanofiber-webs on soda-lime glass and silicon-wafer.

Science.gov (United States)

Watanabe, Kei; Wei, Kai; Nakashima, Ryu; Kim, Ick Soo; Enomoto, Yuji

2013-04-01

In the present work, we conducted the frictional tests of hydrophobic and hydrophilic polyurethane (PUo and PUi) nanofiber webs against engineering materials; soda-lime glass and silicon wafer. PUi/glass combination, with highest hydrophilicity, showed the highest friction coefficient which decrease with the increase of the applied load. Furthermore, the effects of fluorine coating are also investigated. The friction coefficient of fluorine coated hydrophobic PU nanofiber (PUof) shows great decrease against the silicon wafer. Finally, wiping ability and friction property are investigated when the substrate surface is contaminated. Nano-particle dusts are effectively collected into the pores by wiping with PUo and PUi nanofiber webs both on glass and silicon wafer. The friction coefficient gradually increased with the increase of the applied load.

Development of grouped icEEG for the study of cognitive processing

Directory of Open Access Journals (Sweden)

Cihan Mehmet Kadipasaoglu

2015-07-01

Full Text Available Invasive intracranial EEG (icEEG offers a unique opportunity to study human cognitive networks at an unmatched spatiotemporal resolution. To date, the contributions of icEEG have been limited to the individual-level analyses or cohorts whose data are not integrated in any way. Here we discuss how grouped approaches to icEEG overcome challenges related to sparse-sampling, correct for individual variations in response and provide statistically valid models of brain activity in a population. By the generation of whole-brain activity maps, grouped icEEG enables the study of intra and interregional dynamics between distributed cortical substrates exhibiting task-dependent activity. In this fashion, grouped icEEG analyses can provide significant advances in understanding the mechanisms by which cortical networks give rise to cognitive functions.

The effect of electroacupuncture at the MA-IC 3 endocrine ear acupoint on fasting blood glucose levels in type 2 diabetes mellitus patients

Science.gov (United States)

Simadibrata, C.; Budihardjo, F. A.; Srilestari, A.

2017-08-01

The management of diabetes mellitus (DM) involves education, nutritional intervention, and physical exercise, in addition to pharmacological interventions, with the long-term goal of preventing complications through the control of blood glucose levels. Several studies have shown that acupuncture, both conventional acupuncture and electroacupuncture, is useful for lowering blood glucose levels in patients with DM. This study aimed to determine the additional effect of electroacupuncture at the MA-IC 3 Endocrine ear acupoint on fasting blood glucose levels in patients with Type 2 DM who were receiving oral hypoglycemic agents at Banjar General Hospital. In this randomized controlled study, fifty-four study participants who were being treated with oral antidiabetics were allocated into two groups, receiving either electroacupuncture (EA) at the MA-IC 3 ear acupoint with dense disperse wave for 30 minutes or acupuncture at the same point and for the same duration but without EA (No EA). Fasting blood glucose levels were measured before and after the intervention. In Group A (EA), the mean fasting blood glucose (FBG) level decreased from 157.26±24.485 to 142.59±26.771 (p < 0.05), whereas in Group B (No EA), the mean FBG decreased from 149.67±21.485 to 148.74±21.326 (p < 0.05). The difference in the amount of FBG decrease between Group A (EA) and Group B (No EA) was statistically significant (p < 0.05). EA at the MA-IC 3 Endocrine lowers FBG levels to a greater degree than acupuncture with no EA in patients with type 2 DM.

Wafer size effect on material removal rate in copper CMP process

Energy Technology Data Exchange (ETDEWEB)

Yuh, Minjong; Jang, Soocheon; Park, Inho; Jeong, Haedo [Pusan National University, Busan (Korea, Republic of)

2017-06-15

The semiconductor industry has employed the Chemical mechanical planarization (CMP) to enable surface topography control. Copper has been used to build interconnects because of its low-resistivity and high-electromigration. In this study, the effect of wafer size on the Material removal rate (MRR) in copper CMP process was investigated. CMP experiments were conducted using copper blanket wafers with diameter of 100, 150, 200 and 300 mm, while temperature and friction force were measured by infrared and piezoelectric sen-sors. The MRR increases with an increase in wafer size under the same process conditions. The wafer size increased the sliding distance of pad, resulting in an increase in the process temperature. This increased the process temperature, accelerating the chemical etching rate and the dynamic etch rate. The sliding distance of the pad was proportional to the square of the wafer radius; it may be used to predict CMP results and design a CMP machine.

Comparative study on the predictability of statistical models (RSM and ANN) on the behavior of optimized buccoadhesive wafers containing Loratadine and their in vivo assessment.

Science.gov (United States)

Chakraborty, Prithviraj; Parcha, Versha; Chakraborty, Debarupa D; Ghosh, Amitava

2016-01-01

Buccoadhesive wafer dosage form containing Loratadine is formulated utilizing Formulation by Design (FbD) approach incorporating sodium alginate and lactose monohydrate as independent variable employing solvent casting method. The wafers were statistically optimized using Response Surface Methodology (RSM) and Artificial Neural Network algorithm (ANN) for predicting physicochemical and physico-mechanical properties of the wafers as responses. Morphologically wafers were tested using SEM. Quick disintegration of the samples was examined employing Optical Contact Angle (OCA). The comparison of the predictability of RSM and ANN showed a high prognostic capacity of RSM model over ANN model in forecasting mechanical and physicochemical properties of the wafers. The in vivo assessment of the optimized buccoadhesive wafer exhibits marked increase in bioavailability justifying the administration of Loratadine through buccal route, bypassing hepatic first pass metabolism.

GeSn-on-insulator substrate formed by direct wafer bonding

Energy Technology Data Exchange (ETDEWEB)

Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

2016-07-11

GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

Wafer-level integration of NiTi shape memory alloy on silicon using Au–Si eutectic bonding

International Nuclear Information System (INIS)

Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; Van der Wijngaart, Wouter

2013-01-01

This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au–Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more than 1 μm thickness before bonding gives the most promising results. Through patterning of the SMA sheet and by limiting bonding to small areas, stresses created by the thermal mismatch between Si and NiTi are reduced. With a gold layer of 1 μm thickness and bond areas between 200 × 200 and 800 × 800 μm 2 a high bond strength and a yield above 90% is demonstrated. (paper)

IC Treatment: Surgical Procedures

Science.gov (United States)

... Bowel Syndrome Lupus Pelvic Floor Dysfunction Pudendal Neuralgia Sjogren’s Syndrome Vulvodynia Newly Diagnosed Toolkit IC Awareness Toolkit Know ... Bowel Syndrome Lupus Pelvic Floor Dysfunction Pudendal Neuralgia Sjogren’s Syndrome Vulvodynia Newly Diagnosed Toolkit IC Awareness Toolkit Know ...

IC: Frequently Asked Questions

Science.gov (United States)

... Bowel Syndrome Lupus Pelvic Floor Dysfunction Pudendal Neuralgia Sjogren’s Syndrome Vulvodynia Newly Diagnosed Toolkit IC Awareness Toolkit Know ... Bowel Syndrome Lupus Pelvic Floor Dysfunction Pudendal Neuralgia Sjogren’s Syndrome Vulvodynia Newly Diagnosed Toolkit IC Awareness Toolkit Know ...

Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

International Nuclear Information System (INIS)

Brehm, L.; Kregsamer, P.; Pianetta, P.

2000-01-01

It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

Wafer-scale fabrication of polymer distributed feedback lasers

DEFF Research Database (Denmark)

Christiansen, Mads Brøkner; Schøler, Mikkel; Balslev, Søren

2006-01-01

The authors demonstrate wafer-scale, parallel process fabrication of distributed feedback (DFB) polymer dye lasers by two different nanoimprint techniques: By thermal nanoimprint lithography (TNIL) in polymethyl methacrylate and by combined nanoimprint and photolithography (CNP) in SU-8. In both...... techniques, a thin film of polymer, doped with rhodamine-6G laser dye, is spin coated onto a Borofloat glass buffer substrate and shaped into a planar waveguide slab with first order DFB surface corrugations forming the laser resonator. When optically pumped at 532 nm, lasing is obtained in the wavelength...... range between 576 and 607 nm, determined by the grating period. The results, where 13 laser devices are defined across a 10 cm diameter wafer substrate, demonstrate the feasibility of NIL and CNP for parallel wafer-scale fabrication of advanced nanostructured active optical polymer components...

High Speed On-Wafer Characterization Laboratory

Data.gov (United States)

Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

NARCIS (Netherlands)

Moh, T.S.Y.

2013-01-01

In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

Magnetron target designs to improve wafer edge trench filling in ionized metal physical vapor deposition

International Nuclear Information System (INIS)

Lu Junqing; Yoon, Jae-Hong; Shin, Keesam; Park, Bong-Gyu; Yang Lin

2006-01-01

Severe asymmetry of the metal deposits on the trench sidewalls occurs near the wafer edge during low pressure ionized metal physical vapor deposition of Cu seed layer for microprocessor interconnects. To investigate this process and mitigate the asymmetry, an analytical view factor model based on the analogy between metal sputtering and diffuse thermal radiation was constructed. The model was validated based on the agreement between the model predictions and the reported experimental values for the asymmetric metal deposition at trench sidewalls near the wafer edge for a 200 mm wafer. This model could predict the thickness of the metal deposits across the wafer, the symmetry of the deposits on the trench sidewalls at any wafer location, and the angular distributions of the metal fluxes arriving at any wafer location. The model predictions for the 300 mm wafer indicate that as the target-to-wafer distance is shortened, the deposit thickness increases and the asymmetry decreases, however the overall uniformity decreases. Up to reasonable limits, increasing the target size and the sputtering intensity for the outer target portion significantly improves the uniformity across the wafer and the symmetry on the trench sidewalls near the wafer edge

Impact of SiO2 on Al–Al thermocompression wafer bonding

International Nuclear Information System (INIS)

Malik, Nishant; Finstad, Terje G; Schjølberg-Henriksen, Kari; Poppe, Erik U; Taklo, Maaike M V

2015-01-01

Al–Al thermocompression bonding suitable for wafer level sealing of MEMS devices has been investigated. This paper presents a comparison of thermocompression bonding of Al films deposited on Si with and without a thermal oxide (SiO 2 film). Laminates of diameter 150 mm containing device sealing frames of width 200 µm were realized. The wafers were bonded by applying a bond force of 36 or 60 kN at bonding temperatures ranging from 300–550 °C for bonding times of 15, 30 or 60 min. The effects of these process variations on the quality of the bonded laminates have been studied. The bond quality was estimated by measurements of dicing yield, tensile strength, amount of cohesive fracture in Si and interfacial characterization. The mean bond strength of the tested structures ranged from 18–61 MPa. The laminates with an SiO 2 film had higher dicing yield and bond strength than the laminates without SiO 2 for a 400 °C bonding temperature. The bond strength increased with increasing bonding temperature and bond force. The laminates bonded for 30 and 60 min at 400 °C and 60 kN had similar bond strength and amount of cohesive fracture in the bulk silicon, while the laminates bonded for 15 min had significantly lower bond strength and amount of cohesive fracture in the bulk silicon. (paper)

Prion seeding activities of mouse scrapie strains with divergent PrPSc protease sensitivities and amyloid plaque content using RT-QuIC and eQuIC.

Directory of Open Access Journals (Sweden)

Sarah Vascellari

Full Text Available Different transmissible spongiform encephalopathy (TSE-associated forms of prion protein (e.g. PrP(Sc can vary markedly in ultrastructure and biochemical characteristics, but each is propagated in the host. PrP(Sc propagation involves conversion from its normal isoform, PrP(C, by a seeded or templated polymerization mechanism. Such a mechanism is also the basis of the RT-QuIC and eQuIC prion assays which use recombinant PrP (rPrP(Sen as a substrate. These ultrasensitive detection assays have been developed for TSE prions of several host species and sample tissues, but not for murine models which are central to TSE pathogenesis research. Here we have adapted RT-QuIC and eQuIC to various murine prions and evaluated how seeding activity depends on glycophosphatidylinositol (GPI anchoring and the abundance of amyloid plaques and protease-resistant PrP(Sc (PrP(Res. Scrapie brain dilutions up to 10(-8 and 10(-13 were detected by RT-QuIC and eQuIC, respectively. Comparisons of scrapie-affected wild-type mice and transgenic mice expressing GPI anchorless PrP showed that, although similar concentrations of seeding activity accumulated in brain, the heavily amyloid-laden anchorless mouse tissue seeded more rapid reactions. Next we compared seeding activities in the brains of mice with similar infectivity titers, but widely divergent PrP(Res levels. For this purpose we compared the 263K and 139A scrapie strains in transgenic mice expressing P101L PrP(C. Although the brains of 263K-affected mice had little immunoblot-detectable PrP(Res, RT-QuIC indicated that seeding activity was comparable to that associated with a high-PrP(Res strain, 139A. Thus, in this comparison, RT-QuIC seeding activity correlated more closely with infectivity than with PrP(Res levels. We also found that eQuIC, which incorporates a PrP(Sc immunoprecipitation step, detected seeding activity in plasma from wild-type and anchorless PrP transgenic mice inoculated with 22L, 79A and/or RML

PENGARUH MEKANISME CORPORATE GOVERNANCE TERHADAP PENGUNGKAPAN INTELLECTUAL CAPITAL: PADA PERUSAHAAN IC INTENSIVE

Directory of Open Access Journals (Sweden)

Dista Amalia Arifah

2012-12-01

Full Text Available Intangible asset proxied by Intellectual Capital has important role to drive companies values creation. Although many companies have applied corporate governance mechanism in order to have IC disclosure recognition, most of them do not focus on Intellectual Capital disclosure yet. The aim of this study is to analyze the influence of corporate governance mechanisms consisting of size of the board commissioners, the independence level of independent commissioner, the activities of independent commissioners, and audit committee on the intellectual capital disclosures of the companies listed in BEI in 2009 using intensive ICs category with the adding of kontrol variables. This study will provide an illustration on how the mechanisms of corporate governance practices and IC disclosure become a value creation source for the company. There are a total of 176 companies categorized as IC intensive. Using a purposive sampling method, 45 companies were selected as samples. The 2009 annual reports of the companies are used as secondary data source of this research. Furthermore, to get ICs disclosure data content analysis technique was used both for quantity and quality terms. The results indicate that audit committee is the only corporate governance mechanism that significantly affects the level of IC disclosures.

LD to IC

CERN Multimedia

Association du personnel

2010-01-01

LC to IC – Publication of posts: Following the publication of new LD to IC posts, we regret that a large number of post descriptions are not available in both CERN official languages, English and French. Consequently, the Staff Association has decided to provide assistance to those who need it with the translation of one or more posts of interest. To do this, please contact the Staff Association secretariat, tel. 72819 or 72761 or 74224.

PENGARUH IC TERHADAP KINERJA KEUANGAN PERUSAHAAN PERBANKAN PERIODE 2005-2007

Directory of Open Access Journals (Sweden)

Subkhan -

2012-03-01

Full Text Available Tujuan dari penelitian ini adalah untuk meneliti pengaruh intellectual capital (IC perusahaan pada kinerja keuangan mereka. Penelitian ini menggunakan Public Framework dan data dari 57 sektor perbankan Indonesia yang tercatat antara tahun 2005 dan 2007 pada Indonesian Stock Exchange. Penelitian ini menggunakan partial least square (PLS untuk menganalisis data. 3 elemen IC dan kinerja perusahaan dites dalam penelitian ini. Hasilnya memperlihatkan bahwa IC dan kinerja keuangan mempunyai pengaruh yang signifikan, VACA mempunyai pengaruh yang signifikan terhadap kinerja keuangan, VAHU mempuyai pengaruh yang signifikan  terhadap kinerja keuangan, dan STVA mempunyai pengaruh yang signifikan terhadap kinerja keuangan. Abstract The objective of this study is to investigate the influence of firm’s intellectual capital (IC on their financial performance. This paper uses Public Framework and data from 57 Indonesian banking sectors listed between 2005 and 2007 on the Indonesian Stock Exchange. This study uses partial least square (PLS for data analysis. Three elements of IC and company performances are tested by this study. The results show that IC and financial performance have significant influence, VACA has significant influence to financial performance, VAHU has significant influence to financial performance, and STVA has significant influence to financial performance.Keywords: intellectual capital; financial performance

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

2015-01-01

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

High frequency guided wave propagation in monocrystalline silicon wafers

Science.gov (United States)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2017-04-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

The oiling of ICS

International Nuclear Information System (INIS)

Hunter, S.

1993-01-01

The incident command system (ICS) works for oil spills. It should be the industry standard and some will argue that it already is. But there are a number of temptations to fiddle with it. Fueling these inclinations is the fundamental difference between oil spills and natural disasters: Oil spills make the perpetrator fix the problem - under heavy oversight. Add to this difference the public outcry that attends oil spills and the dual role of government as both helper and prosecutor. From these conditions emerge adaptations of ICS which both weaken and strengthen it. The benefits of ICS are diminished by deputy incident commanders who block unified commanders from access to section chiefs, over-zealous crisis managers who displace command post decisions or its information office, separate press offices with party line slants, government law enforcement activity mixed into spill response, nonstandard operations terminology and structure involving open-quotes containment and clean upclose quotes or open-quotes salvage,close quotes and the commingling of public and private response funds. ICS's application to oil spill response is strengthened by the use of trained unified commanders, deputy incident commanders who operate as staff rather than line, crisis managers who support on-scene objectives, joint information centers, and heavy involvement of skilled, prepared environmental assessment teams in the planning section who generate priorities, strategies, and (operationally coordinated) tactics. Technically, not all these points constitute alterations of ICS, but most do and the others come close. This mixed bag of strengthening and weakening tweaks to oil spill ICS provides an opportunity to take a new look at this faithful friend to the crisis responder

Development of parametric material, energy, and emission inventories for wafer fabrication in the semiconductor industry.

Science.gov (United States)

Murphy, Cynthia F; Kenig, George A; Allen, David T; Laurent, Jean-Philippe; Dyer, David E

2003-12-01

Currently available data suggest that most of the energy and material consumption related to the production of an integrated circuit is due to the wafer fabrication process. The complexity of wafer manufacturing, requiring hundreds of steps that vary from product to product and from facility to facility and which change every few years, has discouraged the development of material, energy, and emission inventory modules for the purpose of insertion into life cycle assessments. To address this difficulty, a flexible, process-based system for estimating material requirements, energy requirements, and emissions in wafer fabrication has been developed. The method accounts for mass and energy use atthe unit operation level. Parametric unit operation modules have been developed that can be used to predict changes in inventory as the result of changes in product design, equipment selection, or process flow. A case study of the application of the modules is given for energy consumption, but a similar methodology can be used for materials, individually or aggregated.

Influence of Si wafer thinning processes on (sub)surface defects

Energy Technology Data Exchange (ETDEWEB)

Inoue, Fumihiro, E-mail: fumihiro.inoue@imec.be [Imec, Kapeldreef 75, 3001 Leuven (Belgium); Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric [Imec, Kapeldreef 75, 3001 Leuven (Belgium); Uedono, Akira [Division of Applied Physics, Faculty of Pure and Applied Science, University of Tsukuba, Tsukuba, Ibaraki 305-8573 (Japan)

2017-05-15

Highlights: • Mono-vacancy free Si-thinning can be accomplished by combining several thinning techniques. • The grinding damage needs to be removed prior to dry etching, otherwise vacancies remain in the Si at a depth around 0.5 to 2 μm after Si wafer thickness below 5 μm. • The surface of grinding + CMP + dry etching is equivalent mono vacancy level as that of grinding + CMP. - Abstract: Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5–2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in

A cell-level power management IC in BCD-SOI for partial power processing in Concentrating-PV systems

NARCIS (Netherlands)

Zaman, M.S.; Wen, Y.; Fernandes, R.; Buter, B.; Doorn, T.S.; Dijkstra, M.; Bergveld, H.J.; Trescases, O.

2014-01-01

This work presents a power management IC used to mitigate the effects of mismatch in Concentrating-Photovoltaic (CPV) systems. The IC contains a bi-directional dc-dc converter, an auxiliary boost converter to generate the internal 10 V power supply, as well as protection and monitoring circuits. The

Science and technology of plasma activated direct wafer bonding

Science.gov (United States)

Roberds, Brian Edward

This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

TXRF with synchrotron radiation. Analysis of Ni on Si-wafer surfaces

Energy Technology Data Exchange (ETDEWEB)

Wobrauschek, P [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Kregsamer, P [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Ladisich, W [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Streli, C [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Pahlke, S [Wacker Chemitronic GmbH, D-84479 Burghausen (Germany); Fabry, L [Wacker Chemitronic GmbH, D-84479 Burghausen (Germany); Garbe, S [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Haller, M [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Knoechel, A [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Radtke, M [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany)

1995-09-11

SR-TXRF (Synchrotron Radiation excited Total Reflection X-ray Fluorescence Analysis) with monoenergetic radiation produced by a W/C multilayer monochromator has been applied to the analysis of Ni on a Si-wafer surface. An intentionally contaminated wafer with 100 pg has been used to determine the detection limits. 13 fg have been achieved for Ni at a beam current of 73 mA and extrapolated to 1000 s. This technique simulates the sample preparation technique of Vapour Phase Decomposition (VPD) on a wafer surface. (orig.).

TXRF with synchrotron radiation. Analysis of Ni on Si-wafer surfaces

International Nuclear Information System (INIS)

Wobrauschek, P.; Kregsamer, P.; Ladisich, W.; Streli, C.; Pahlke, S.; Fabry, L.; Garbe, S.; Haller, M.; Knoechel, A.; Radtke, M.

1995-01-01

SR-TXRF (Synchrotron Radiation excited Total Reflection X-ray Fluorescence Analysis) with monoenergetic radiation produced by a W/C multilayer monochromator has been applied to the analysis of Ni on a Si-wafer surface. An intentionally contaminated wafer with 100 pg has been used to determine the detection limits. 13 fg have been achieved for Ni at a beam current of 73 mA and extrapolated to 1000 s. This technique simulates the sample preparation technique of Vapour Phase Decomposition (VPD) on a wafer surface. (orig.)

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

KAUST Repository

Yang, Xiaoming

2014-10-01

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

KAUST Repository

Yang, Xiaoming; Zhong, Zhaowei; Diallo, Elhadj; Wang, Zhihong; Yue, Weisheng

2014-01-01

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

Validating a High Performance Liquid Chromatography-Ion Chromatography (HPLC-IC) Method with Conductivity Detection After Chemical Suppression for Water Fluoride Estimation.

Science.gov (United States)

Bondu, Joseph Dian; Selvakumar, R; Fleming, Jude Joseph

2018-01-01

A variety of methods, including the Ion Selective Electrode (ISE), have been used for estimation of fluoride levels in drinking water. But as these methods suffer many drawbacks, the newer method of IC has replaced many of these methods. The study aimed at (1) validating IC for estimation of fluoride levels in drinking water and (2) to assess drinking water fluoride levels of villages in and around Vellore district using IC. Forty nine paired drinking water samples were measured using ISE and IC method (Metrohm). Water samples from 165 randomly selected villages in and around Vellore district were collected for fluoride estimation over 1 year. Standardization of IC method showed good within run precision, linearity and coefficient of variance with correlation coefficient R 2  = 0.998. The limit of detection was 0.027 ppm and limit of quantification was 0.083 ppm. Among 165 villages, 46.1% of the villages recorded water fluoride levels >1.00 ppm from which 19.4% had levels ranging from 1 to 1.5 ppm, 10.9% had recorded levels 1.5-2 ppm and about 12.7% had levels of 2.0-3.0 ppm. Three percent of villages had more than 3.0 ppm fluoride in the water tested. Most (44.42%) of these villages belonged to Jolarpet taluk with moderate to high (0.86-3.56 ppm) water fluoride levels. Ion Chromatography method has been validated and is therefore a reliable method in assessment of fluoride levels in the drinking water. While the residents of Jolarpet taluk (Vellore distict) are found to be at a high risk of developing dental and skeletal fluorosis.

Bondability of processed glass wafers

NARCIS (Netherlands)

Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

1999-01-01

The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

Science.gov (United States)

Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

2016-05-01

printability of defects at wafer level and automates the process of defect dispositioning from images captured using high resolution inspection machine. It first eliminates false defects due to registration, focus errors, image capture errors and random noise caused during inspection. For the remaining real defects, actual mask-like contours are generated using the Calibre® ILT solution [1][2], which is enhanced to predict the actual mask contours from high resolution defect images. It enables accurate prediction of defect contours, which is not possible from images captured using inspection machine because some information is already lost due to optical effects. Calibre's simulation engine is used to generate images at wafer level using scanner optical conditions and mask-like contours as input. The tool then analyses simulated images and predicts defect printability. It automatically calculates maximum CD variation and decides which defects are severe to affect patterns on wafer. In this paper, we assess the printability of defects for the mask of advanced technology nodes. In particular, we will compare the recovered mask contours with contours extracted from SEM image of the mask and compare simulation results with AIMSTM for a variety of defects and patterns. The results of printability assessment and the accuracy of comparison are presented in this paper. We also suggest how this method can be extended to predict printability of defects identified on EUV photomasks.

Computing fundamentals IC3 edition

CERN Document Server

Wempen, Faithe

2014-01-01

Kick start your journey into computing and prepare for your IC3 certification With this essential course book you'll be sending e-mails, surfing the web and understanding the basics of computing in no time. Written by Faithe Wempen, a Microsoft Office Master Instructor and author of more than 120 books, this complete guide to the basics has been tailored to provide comprehensive instruction on the full range of entry-level computing skills. It is a must for students looking to move into almost any profession, as entry-level computing courses have become a compulsory requirement in the modern w

ON-LINE MONITORING OF I&C TRANSMITTERS AND SENSORS FOR CALIBRATION VERIFICATION AND RESPONSE TIME TESTING WAS SUCCESSFULLY IMPLEMENTED AT ATR

Energy Technology Data Exchange (ETDEWEB)

Erickson, Phillip A.; O' Hagan, Ryan; Shumaker, Brent; Hashemian, H. M.

2017-03-01

The Advanced Test Reactor (ATR) has always had a comprehensive procedure to verify the performance of its critical transmitters and sensors, including RTDs, and pressure, level, and flow transmitters. These transmitters and sensors have been periodically tested for response time and calibration verification to ensure accuracy. With implementation of online monitoring techniques at ATR, the calibration verification and response time testing of these transmitters and sensors are verified remotely, automatically, hands off, include more portions of the system, and can be performed at almost any time during process operations. The work was done under a DOE funded SBIR project carried out by AMS. As a result, ATR is now able to save the manpower that has been spent over the years on manual calibration verification and response time testing of its temperature and pressure sensors and refocus those resources towards more equipment reliability needs. More importantly, implementation of OLM will help enhance the overall availability, safety, and efficiency. Together with equipment reliability programs of ATR, the integration of OLM will also help with I&C aging management goals of the Department of Energy and long-time operation of ATR.

Electronic States of IC60BA and PC71BM

International Nuclear Information System (INIS)

Sheng Chun-Qi; Wang Peng; Shen Ying; Li Wen-Jie; Li Hong-Nian; Zhang Wen-Hua; Zhu Jun-Fa; Lai Guo-Qiao

2013-01-01

We investigate the electronic states of IC 60 BA and PC 71 BM using first-principles calculations and photoelectron spectroscopy (PES) measurements. The energy level structures for all possible isomers are reported and compared with those of C 60 , C 70 and PC 61 BM. The attachment of the side chains can raise the LUMO energies and decrease the HOMO-LUMO gaps, and thus helps to increase the power-conversion efficiency of bulk heterojunction solar cells. In the PES studies, we prepared IC 60 BA and PC 71 BM films on Si:H(111) substrates to construct adsorbate/substrate interfaces describable with the integer charge-transfer (ICT) model. Successful measurements then revealed that one of the most important material properties for an electron acceptor, the energy of the negative integer charge-transfer state (E ICT− ), is 4.31 eV below the vacuum level for PC 71 BM. The E ICT− of IC 60 BA is smaller than 4.14 eV

Determination of wafer center position during the transfer process by using the beam-breaking method

International Nuclear Information System (INIS)

Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

2014-01-01

A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human–machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions. (paper)

450mm wafer patterning with jet and flash imprint lithography

Science.gov (United States)

Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2013-09-01

The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

Determination of Na+ and K+ ions in the high-level liquid waste by ion chromatography (IC)

International Nuclear Information System (INIS)

Chen Lianzhong; Ma Guilan

1992-01-01

The determination of Na + and k + ions in the high-level liquid waste is investigated using ion chromatography. In order to protect the low capacity ion exchange resin in single column IC and remove the transition metal as well as other heavy metal ions that are contained in liquid waste, the pretreatment column with EDTA chelating resin is used. Those impurity metal ions are strongly absorbed by EDTA chelating resin and 100% of Na + and K + ions in the solution are eluted. The ability of the decontamination of EDTA chelating resin is satisfactory. The sample of the high-level liquid waste is diluted appropriately, then an aliquot of the sample is passed through the pretreatment column with EDTA chelating resin, the eluate is analysed by single column ion chromatography. The precision of this method is better than 5% for the determination of Na + and K + ions (at μg· ml -1 level)

Evaluation of the viscoelastic behaviour and glass/mould interface friction coefficient in the wafer based precision glass moulding

DEFF Research Database (Denmark)

Sarhadi, Ali; Hattel, Jesper Henri; Hansen, Hans Nørgaard

2014-01-01

-placements, internal diameter and thickness of the rings are measured during the tests. Viscoelastic andstructural relaxation behaviour of the glass are implemented into the ABAQUS FEM software through aFORTRAN material subroutine (UMAT) and the FE model is validated with a sandwich seal test. Then, byFE simulation...... of the ring compression test and comparison of the experimental creep with the simulatedone in an iterative procedure, viscoelastic parameters of the glass material are characterized. Finally,interfacial glass/mould friction coefficients at different temperatures are determined through FEM basedfriction...... curves combined with experimental data points. The obtained viscoelastic parameters and inter-facial friction coefficients can later be employed for prediction of the final shape/size as well as the stressdistribution in the glass wafer during a real wafer based precision glass moulding process. © 2014...

Preparation and characterisation of immobilised humic acid on silicon wafer

International Nuclear Information System (INIS)

Szabo, Gy.; Guczi, J.; Telegdi, J.; Pashalidis, I.; Szymczak, W.; Buckau, G.

2005-01-01

Full text of publication follows: The chemistry of the interactions of radionuclides with humic acid needs to be understood in details so that humate-mediated migration of radionuclides through the environment can be predicted. To achieve such a data in microscopic scale, several detective techniques, such as atomic force microscopy (AFM), chemical force microscopy (CFM), nuclear microprobe analysis (NMA) and X-ray photoelectron spectroscopy (XPS) can be used to measure intermolecular forces and to visualize the surface morphology. The main aim of this work was to provide humic material with specific properties in order to study with different spectroscopic techniques, the complexation behaviour of surface bound humic acid in microscopic scale. Namely, humic acid has been immobilised on silicon wafers in order to mimic surface bound humic substances in natural aquatic systems. In this communication, we present a simple protocol to immobilize humic acid on silicon wafer surface. A tri-functional silane reagent 3-amino-propyl-tri-methoxy-silane (APTES) was used to modify the surface of silicon wafers and appeared to be able to strongly attached soluble humic acid through their carboxylic groups to solid support. Characterisation of the surfaces, after any preparation steps, was done by ATR-FTIR, AFM and TOF-SIMS. These methods have proved that the humic acid forms a relatively homogeneous layer on the wafers. Immobilisation of humic acid on silicon wafer was further proved by binding isotherm of Am/Nd. (authors)

Synchrotron radiation induced TXRF of low Z elements on Si wafer surfaces at SSRL-comparison of excitation geometries and condition

International Nuclear Information System (INIS)

Streli, C.; Wobrauschek, P.; Kregsamer, P.; Pepponi, G.; Pianetta, P.; Pahlke, S.; Fabry, L.

2000-01-01

The determination of low Z elements, like Na and Al at ultra trace levels on Si wafer surfaces is demanded by semiconductor industry. SR-TXRF is a promising method to fulfill the task, if a special energy dispersive detector with an ultra thin window is used. Synchrotron radiation is the ideal suited excitation source for TXRF of low Z elements due to its intensive, natural collimated and linear polarized radiation with wide spectral range down to low energies even below 1 keV. TXRF offers some advantages for wafer surface analysis like nondestructive investigation and mapping capability. Experiments have been performed at SSRL beamline 3-4, a bending magnet beamline using white (<3 keV) and monochromatic radiation, as well as on beamline 3-3, using a crystal monochromator as well as a multilayer monochromator. A comparison of excitation detection geometries was performed, using a sidelooking detector with vertical positioned wafer as well as a downlooking detector with a horizontally arranged wafer. The advantages and disadvantages of the various geometries and excitation conditions are presented and the results compared. Detection limits are in the 100 fg range for Na, determined with droplet samples on Si wafer surfaces. (author)

Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

Science.gov (United States)

Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

2018-04-01

Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

Handbook of wafer bonding

CERN Document Server

Ramm, Peter; Taklo, Maaike M V

2011-01-01

Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

ICS logging solution for network-based attacks using Gumistix technology

Science.gov (United States)

Otis, Jeremy R.; Berman, Dustin; Butts, Jonathan; Lopez, Juan

2013-05-01

Industrial Control Systems (ICS) monitor and control operations associated with the national critical infrastructure (e.g., electric power grid, oil and gas pipelines and water treatment facilities). These systems rely on technologies and architectures that were designed for system reliability and availability. Security associated with ICS was never an inherent concern, primarily due to the protections afforded by network isolation. However, a trend in ICS operations is to migrate to commercial networks via TCP/IP in order to leverage commodity benefits and cost savings. As a result, system vulnerabilities are now exposed to the online community. Indeed, recent research has demonstrated that many exposed ICS devices are being discovered using readily available applications (e.g., ShodanHQ search engine and Google-esque queries). Due to the lack of security and logging capabilities for ICS, most knowledge about attacks are derived from real world incidents after an attack has already been carried out and the damage has been done. This research provides a method for introducing sensors into the ICS environment that collect information about network-based attacks. The sensors are developed using an inexpensive Gumstix platform that can be deployed and incorporated with production systems. Data obtained from the sensors provide insight into attack tactics (e.g., port scans, Nessus scans, Metasploit modules, and zero-day exploits) and characteristics (e.g., attack origin, frequency, and level of persistence). Findings enable security professionals to draw an accurate, real-time awareness of the threats against ICS devices and help shift the security posture from reactionary to preventative.

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

Energy Technology Data Exchange (ETDEWEB)

Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

2017-05-10

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

InP-based photonic integrated circuit platform on SiC wafer.

Science.gov (United States)

Takenaka, Mitsuru; Takagi, Shinichi

2017-11-27

We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

International Nuclear Information System (INIS)

Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

2005-01-01

Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

Physical mechanisms of copper-copper wafer bonding

International Nuclear Information System (INIS)

Rebhan, B.; Hingerl, K.

2015-01-01

The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing

ICECAP: an integrated, general-purpose, automation-assisted IC50/EC50 assay platform.

Science.gov (United States)

Li, Ming; Chou, Judy; King, Kristopher W; Jing, Jing; Wei, Dong; Yang, Liyu

2015-02-01

IC50 and EC50 values are commonly used to evaluate drug potency. Mass spectrometry (MS)-centric bioanalytical and biomarker labs are now conducting IC50/EC50 assays, which, if done manually, are tedious and error-prone. Existing bioanalytical sample preparation automation systems cannot meet IC50/EC50 assay throughput demand. A general-purpose, automation-assisted IC50/EC50 assay platform was developed to automate the calculations of spiking solutions and the matrix solutions preparation scheme, the actual spiking and matrix solutions preparations, as well as the flexible sample extraction procedures after incubation. In addition, the platform also automates the data extraction, nonlinear regression curve fitting, computation of IC50/EC50 values, graphing, and reporting. The automation-assisted IC50/EC50 assay platform can process the whole class of assays of varying assay conditions. In each run, the system can handle up to 32 compounds and up to 10 concentration levels per compound, and it greatly improves IC50/EC50 assay experimental productivity and data processing efficiency. © 2014 Society for Laboratory Automation and Screening.

Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

Science.gov (United States)

Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

2018-05-01

Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

An attempt to specify thermal history in CZ silicon wafers and possibilities for its modification

International Nuclear Information System (INIS)

Kissinger, G.; Sattler, A.; Mueller, T.; Ammon, W. von

2007-01-01

The term thermal history of silicon wafers represents the whole variety of process parameters of crystal growth. The aim of this contribution is an attempt to specify thermal history by one parameter that is directly correlated to the bulk microdefect density. The parameter that reflects thermal history and correlates it with nucleation of oxide precipitates is the concentration of VO 2 complexes. The VO 2 concentration in silicon wafers is too low to be measured by FTIR but it can be obtained from the loss of interstitial oxygen during a standardized thermal treatment. Based on this, the vacancy concentration frozen during crystal cooling in the ingot can be calculated. RTA treatments above 1150 deg. C create a well defined level of the VO 2 concentration in silicon wafers. This means that a well controlled modification of the thermal history is possible. We also investigated the kinetics of reduction of the as-grown excess VO 2 concentration during RTA treatments at 950 deg. C and 1050 deg. C and the effectiveness of this attempt to totally delete the thermal history

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

Science.gov (United States)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Studies on the pathogenesis of Aleutian disease of mink. X. demonstration of immune complexes by the /sup 125/I-C 1 q binding test after experimental infection

Energy Technology Data Exchange (ETDEWEB)

Mueller-Peddinghaus, R [Kali-Chemie Pharma G.m.b.H., Hannover (Germany, F.R.). Abt. fuer Experimentelle Pathologie; Meyer zu Schwabedissen, H [Medizinische Hochschule Hannover (Germany, F.R.). Abt. fuer Klinische Immunologie und Bluttransfusionswesen; Kalden, J R [Erlangen-Nuernberg Univ., Erlangen (Germany, F.R.). Inst. und Poliklinik fuer Klinische Immunologie; Trautwein, G; Ueberschaer, S [Tieraerztliche Hochschule Hannover (Germany, F.R.). Inst. fuer Pathologie

1980-01-01

Aleutian disease (AD) of mink most closely resembles systemic lupus erythematosus (SLE) in man; both are immune complex disease. In experimental AD serum immune complexes are determined by the /sup 125/J-C 1 q-binding test using human C 1 q. Mink (n = 12) infected intraperitoneally with Aleutian disease virus (ADV), grown in fetal mink kidney cells, developed during the course of infection a mean of /sup 125/I-C 1 q serum binding equivalent to 3.62 +- 1.68 mg./ml. aggr. HGG. (aggregated human immunoglobulin). Sera of mink (n = 8) which were infected with ADV grown in L-cells showed a less marked /sup 125/I-C 1 q binding with a mean equivalent to 2.52 +- 1.43 mg./ml. aggr. HGG. In contrast control animals (n = 8) treated with non-ADV-infected mink epidermal fibroblasts or Eagle's minimal essential medium substituted with fetal calf serum only bound /sup 125/I-C 1 q equivalent to 1.02 +- 0.99 mg./ml. aggr. HGG. In mink infected with ADV propagated in fetal mink kidney cells a constant increase in the /sup 125/I-C 1 q serum binding occurred from the 4th to the 7th and 13th week after ADV infection. Mink which were infected with ADV propagated in mouse L-cells exhibited a different pattern of the /sup 125/I-C 1 q serum binding capacity with a sharp increase from the 4th to the 7th week, followed by a decline towards the 13th week post infection. The serum /sup 125/I-C 1 q binding capacity of all experimental animal groups exhibited at different times of the experiment a significant correlation with the presence of hypergammaglobulinaemia and raised ADV-antibody titers. From the data obtained it appears that the /sup 125/I-C 1 q binding test, utilizing human C 1 q, is a suitable method for the detection of circulating serum immune complexes in mink during the course of ADV-infection.

Wafer integrated micro-scale concentrating photovoltaics

Science.gov (United States)

Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

2017-09-01

Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

Mechanics of wafer bonding: Effect of clamping

Science.gov (United States)

Turner, K. T.; Thouless, M. D.; Spearing, S. M.

2004-01-01

A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

Science.gov (United States)

Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); King, Glen C. (Inventor); Choi, Sang Hyouk (Inventor)

2017-01-01

An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

Design and implementation of a S-parameter wafer defect scanner

International Nuclear Information System (INIS)

Naik, P.S.; Beling, C.D.; Fung, S.

2004-01-01

We describe the design and implementation of a real-time automated scanning system that gives an S-parameter image of a semiconductor wafer, thus allowing the density of vacancy type defects to be shown as a function of position on the wafer. A conventional 22 Na positron source of 0.5 mm diameter rasters across 5 x 5 cm 2 region of two times per hour in rectilinear motion. Gamma ray energies E γ are processed using a standard HP Ge spectroscopy system and a 14 bit nuclear ADC. Over a period of 1-2 days a high resolution 128 x 128 pixel image with 256 colours (scaled to the S-parameter range) can be formed as a wafer defect map. The system is reliable, interactive and user-friendly (patent pending 2003). (orig.)

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

Science.gov (United States)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Simultaneous detection of three lily viruses using Triplex IC-RT-PCR.

Science.gov (United States)

Zhang, Yubao; Wang, Yajun; Xie, Zhongkui; Yang, Guo; Guo, Zhihong; Wang, Le

2017-11-01

Viruses commonly infecting lily (Lilium spp.) include: Lily symptomless virus (LSV), Cucumber mosaic virus (CMV) and Lily mottle virus (LMoV). These viruses usually co-infect lilies causing severe economic losses in terms of quantity and quality of flower and bulb production around the world. Reliable and precise detection systems need to be developed for virus identification. We describe the development of a triplex immunocapture (IC) reverse transcription (RT) polymerase chain reaction (PCR) assay for the simultaneous detection of LSV, CMV and LMoV. The triplex IC-RT-PCR was compared with a quadruplex RT-PCR assay. Relative to the quadruplex RT-PCR, the specificity of the triplex IC-RT-PCR system for LSV, CMV and LMoV was 100% for field samples. The sensitivity of the triplex IC-RT-PCR system was 99.4%, 81.4% and 98.7% for LSV, CMV and LMoV, respectively. Agreement (κ) between the results obtained from the two tests was 0.968, 0.844 and 0.984 for LSV, CMV and LMoV, respectively. This is the first report of the simultaneous detection of LSV, CMV and LMoV in a triplex IC-RT-PCR assay. In particular we believe this convenient and reliable triplex IC-RT-PCR method could be used routinely for large-scale field surveys or crop health monitoring of lily. Copyright © 2017. Published by Elsevier B.V.

The preparation and thermoelectric properties of molten salt electrodeposited boron wafers

International Nuclear Information System (INIS)

Kumashiro, Y.; Ozaki, S.; Sato, K.; Kataoka, Y.; Hirata, K.; Yokoyama, T.; Nagatani, S.; Kajiyama, K.

2004-01-01

We have prepared electrodeposited boron wafer by molten salts with KBF 4 -KF at 680 deg. C using graphite crucible for anode and silicon wafer and nickel plate for cathodes. Experiments were performed by various molar ratios KBF 4 /KF and current densities. Amorphous p-type boron wafers with purity 87% was deposited on nickel plate for 1 h. Thermal diffusivity by ring-flash method and heat capacity by DSC method produced thermal conductivity showing amorphous behavior in the entire temperature range. The systematical results on thermoelectric properties were obtained for the wafers prepared with KBF 4 -KF (66-34 mol%) under various current densities in the range 1-2 A/cm 2 . The temperature dependencies of electrical conductivity showed thermal activated type with activation energy of 0.5 eV. Thermoelectric power tended to increase with increasing temperature up to high temperatures with high values of (1-10) mV/K. Thermoelectric figure-of-merit was 10 -4 /K at high temperatures. Estimated efficiency of thermoelectric energy conversion would be calculated to be 4-5%

Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

2009-07-01

Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Scatterometry on pelliclized masks: an option for wafer fabs

Science.gov (United States)

Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

2007-03-01

Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

International Nuclear Information System (INIS)

Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

2006-01-01

An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

Silicon waveguides produced by wafer bonding

DEFF Research Database (Denmark)

Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

2005-01-01

X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

Wafer scale integration of catalyst dots into nonplanar microsystems

DEFF Research Database (Denmark)

Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

2007-01-01

In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

Science.gov (United States)

Miki, N.; Spearing, S. M.

2003-11-01

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

Science.gov (United States)

Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

2013-11-22

Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

Fabrication of Through via Holes in Ultra-Thin Fused Silica Wafers for Microwave and Millimeter-Wave Applications

Directory of Open Access Journals (Sweden)

Xiao Li

2018-03-01

Full Text Available Through via holes in fused silica are a key infrastructure element of microwave and millimeter-wave circuits and 3D integration. In this work, etching through via holes in ultra-thin fused silica wafers using deep reactive-ion etching (DRIE and laser ablation was developed and analyzed. The experimental setup and process parameters for both methods are presented and compared. For DRIE, three types of mask materials including KMPR 1035 (Nippon Kayaku, Tokyo, Japan photoresist, amorphous silicon and chromium—with their corresponding optimized processing recipes—were tested, aiming at etching through a 100 μm fused silica wafer. From the experiments, we concluded that using chromium as the masking material is the best choice when using DRIE. However, we found that the laser ablation method with a laser pulse fluence of 2.89 J/cm2 and a pulse overlap of 91% has advantages over DRIE. The laser ablation method has a simpler process complexity, while offering a fair etching result. In particular, the sidewall profile angle is measured to be 75° to the bottom surface of the wafer, which is ideal for the subsequent metallization process. As a demonstration, a two-inch wafer with 624 via holes was processed using both technologies, and the laser ablation method showed better efficiency compared to DRIE.

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

Science.gov (United States)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

International Nuclear Information System (INIS)

Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

2000-01-01

Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

Design and development of wafer-level near-infrared micro-camera

Science.gov (United States)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Haldar, Pradeep; Dhar, Nibir K.; Lewis, Jay S.; Wijewarnasuriya, Priyalal; Puri, Yash R.; Sood, Ashok K.

2015-08-01

SiGe offers a low-cost alternative to conventional infrared sensor material systems such as InGaAs, InSb, and HgCdTe for developing near-infrared (NIR) photodetector devices that do not require cooling and can offer high bandwidths and responsivities. As a result of the significant difference in thermal expansion coefficients between germanium and silicon, tensile strain incorporated into Ge epitaxial layers deposited on Si utilizing specialized growth processes can extend the operational range of detection to 1600 nm and longer wavelengths. We have fabricated SiGe based PIN detector devices on 300 mm diameter Si wafers in order to take advantage of high throughput, large-area complementary metal-oxide semiconductor (CMOS) technology. This device fabrication process involves low temperature epitaxial deposition of Ge to form a thin p+ seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. An n+-Ge layer formed by ion implantation of phosphorus, passivating oxide cap, and then top copper contacts complete the PIN photodetector design. Various techniques including transmission electron microscopy (TEM) and secondary ion mass spectrometry (SIMS) have been employed to characterize the material and structural properties of the epitaxial growth and fabricated detector devices. In addition, electrical characterization was performed to compare the I-V dark current vs. photocurrent response as well as the time and wavelength varying photoresponse properties of the fabricated devices, results of which are likewise presented.

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

Science.gov (United States)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

Science.gov (United States)

Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

2018-03-01

The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

Development of an ASD IC for the Micro Pixel Chamber

CERN Document Server

Orito, R; Kubo, H; Miuchi, K; Nagayoshi, T; Okada, Y; Takada, A; Takeda, A; Tanimori, T; Ueno, M

2004-01-01

A new amplifier-shaper-discriminator (ASD) chip was designed and manufactured for the Micro Pixel Chamber ($\\mu$-PIC). The design of this ASD IC is based on the ASD IC (TGC-ASD) for the Thin Gap Chamber in the LHC Atlas Experiment. The decay time constant of the preamplifier is 5-times longer than that of the TGC-ASD, and some other modifications have been made in order to improve the signal-to-noise ratio of the $\\mu$-PIC. The ASD IC uses SONY Analog Master Slice bipolar technology. The IC contains 4 channels in a QFP48 package. The decay time constant of the preamplifier is 80 ns and its gain is approximately 0.8 V/pC. The output from the preamplifier is received by a shaper (main-amplifier) with a gain of 7. A baseline restoration circuit is incorporated in the main-amplifier, and the current used for the baseline restoration is 5-times smaller than that of the TGC-ASD. The threshold voltage for the discriminator section is common to the 4 channels and their digital output level is LVDS-compatible. The ASD...

Temperature Uniformity of Wafer on a Large-Sized Susceptor for a Nitride Vertical MOCVD Reactor

International Nuclear Information System (INIS)

Li Zhi-Ming; Jiang Hai-Ying; Han Yan-Bin; Li Jin-Ping; Yin Jian-Qin; Zhang Jin-Cheng

2012-01-01

The effect of coil location on wafer temperature is analyzed in a vertical MOCVD reactor by induction heating. It is observed that the temperature distribution in the wafer with the coils under the graphite susceptor is more uniform than that with the coils around the outside wall of the reactor. For the case of coils under the susceptor, we find that the thickness of the susceptor, the distance from the coils to the susceptor bottom and the coil turns significantly affect the temperature uniformity of the wafer. An optimization process is executed for a 3-inch susceptor with this kind of structure, resulting in a large improvement in the temperature uniformity. A further optimization demonstrates that the new susceptor structure is also suitable for either multiple wafers or large-sized wafers approaching 6 and 8 inches

A modified occlusal wafer for managing partially dentate orthognathic patients--a case series.

Science.gov (United States)

Soneji, Bhavin Kiritkumar; Esmail, Zaid; Sharma, Pratik

2015-03-01

A multidisciplinary approach is essential in orthognathic surgery to achieve stable and successful outcomes. The model surgery planning is an important aspect in achieving the desired aims. An occlusal wafer used at the time of surgery aids the surgeon during correct placement of the jaws. When dealing with partially dentate patients, the design of the occlusal wafer requires modification to appropriately position the jaw. Two cases with partially dentate jaws are presented in which the occlusal wafer has been modified to provide stability at the time of surgery.

Computational Modeling in Plasma Processing for 300 mm Wafers

Science.gov (United States)

Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

1997-01-01

Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

The measurement of Ksub(IC) in single crystal SiC using the indentation method

International Nuclear Information System (INIS)

Henshall, J.L.; Brookes, C.A.

1985-01-01

The present work has concentrated on investigating the underlying fracture toughness behaviour of SiC single crystals. This material was chosen because of the commercial importance of the various polycrystalline forms of SiC and the relative ready availability of reasonably sized single crystals. This study has examined the feasibility of using the indentation technique to determine Ksub(IC) in SiC single crystals. This requires much more less complex experimentation and also affords the possibility of being able to use this method to study the orientation dependence of Ksub(IC) in a similar manner to that used to investigate anisotropy in indentation hardness behaviour. A single crystal of 6H-SiC was used for all the hardness and conventional Ksub(IC) results reported here. The particular polytype and orientation were determined using the Laue X-ray method. All the measurements were made under ambient conditions. Three-point bend tests, with a 6 mm span on single edge notched beams, SENB, orientated such that the plane of the notch was brace 112-bar0 brace and the crack propagation direction were used for the conventional Ksub(IC) tests. The hardness indentations were all made on one particular SENB test piece after it had been fractured. The results are discussed. (author)

Dicty_cDB: FC-IC0102 [Dicty_cDB

Lifescience Database Archive (English)

Full Text Available FC-IC (Link to library) FC-IC0102 (Link to dictyBase) - - - Contig-U16527-1 FC-IC01...02F (Link to Original site) FC-IC0102F 434 - - - - - - Show FC-IC0102 Library FC-IC (Link to library) Clone ...ID FC-IC0102 (Link to dictyBase) Atlas ID - NBRP ID - dictyBase ID - Link to Contig Contig-U16527-1 Original site URL http://dict... (bits) Value N AB088483 |AB088483.1 Dictyostelium discoideum gene for gamete and mating-type specific prote...oducing significant alignments: (bits) Value AB088483_1( AB088483 |pid:none) Dictyostelium discoideum gmsA g

Chemical strategies for modifications of the solar cell process, from wafering to emitter diffusion; Chemische Ansaetze zur Neuordnung des Solarzellenprozesses ausgehend vom Wafering bis hin zur Emitterdiffusion

Energy Technology Data Exchange (ETDEWEB)

Mayer, Kuno

2009-11-06

The paper describes the classic standard industrial solar cell based on monocrystalline silicon and describes new methods of fabrication. The first is an alternative wafering concept using laser microjet cutting instead of multiwire cutting. This method originally uses pure, deionized water; it was modified so that the liquid jet will not only be a liquid light conductor but also a transport medium for etching fluids supporting thermal abrasion of silicon by the laser jet. Two etching fluids were tested experimentally; it was found that water-free fluids based on perfluorinated solvents with very slight additions of gaseous chlorine are superior to all other options. In the second section, the wet chemical process steps between wafering and emitter diffusion (i.e. the first high-temperature step) was to be modified. Alternatives to 2-propanol were to be found in the experimental part. Purification after texturing was to be rationalized in order to reduce the process cost, either by using less chemical substances or by achieving shorter process times. 1-pentanol and p-toluolsulfonic acid were identified as two potential alternatives to 2-propanol as texture additives. Finally, it could be shown that wire-cut substrates processed with the new texturing agents have higher mechanical stabilities than substrates used with the classic texturing agent 2-propanol. [German] Im ersten Kapitel wird die klassische Standard-Industrie-Solarzelle auf der Basis monokristallinen Siliziums vorgestellt. Der bisherige Herstellungsprozess der Standard-Industrie-Solarzelle, der in wesentlichen Teilen darauf abzielt, diese Verluste zu minimieren, dient als Referenz fuer die Entwicklung neuer Fertigungsverfahren, wie sie in dieser Arbeit vorgestellt werden. Den ersten thematischen Schwerpunkt bildet die Entwicklung eines alternativen Wafering-Konzeptes zum Multi-Drahtsaegen. Die Basis des neuen, hier vorgestellten Wafering-Prozesses bildet das Laser-Micro-Jet-Verfahren. Dieses System

Determining the size and concentration dependence of gold nanoparticles in vitro cytotoxicity (IC50) test using WST-1 assay

International Nuclear Information System (INIS)

Rosli, Nur Shafawati binti; Rahman, Azhar Abdul; Aziz, Azlan Abdul; Shamsuddin, Shaharum

2015-01-01

Gold nanoparticles (AuNPs) received a great deal of attention for biomedical applications, especially in diagnostic imaging and therapeutics. Even though AuNPs have potential benefits in biomedical applications, the impact of AuNPs on human and environmental health still remains unclear. The use of AuNPs which is a high-atomic-number materials, provide advantages in terms of radiation dose enhancement. However, before this can become a clinical reality, cytotoxicity of the AuNPs has to be carefully evaluated. Cytotoxicity test is a rapid, standardized test that is very sensitive to determine whether the nanoparticles produced are harmful or benign on cellular components. In this work the size and concentration dependence of AuNPs cytotoxicity in breast cancer cell lines (MCF-7) are tested by using WST-1 assay. The sizes of AuNPs tested were 13 nm, 50 nm, and 70 nm. The cells were seeded in the 96-well plate and were treated with different concentrations of AuNPs by serial dilution for each size of AuNPs. The high concentration of AuNPs exhibit lower cell viability compared to low concentration of AuNPs. We quantified the toxicity of AuNPs in MCF-7 cell lines by determining the IC 50 values in WST-1 assays. The IC 50 values (inhibitory concentrations that effected 50% growth inhibition) of 50 nm AuNPs is lower than 13 nm and 70 nm AuNPs. Mean that, 50nm AuNPs are more toxic to the MCF-7 cells compared to smaller and larger sizes AuNPs. The presented results clearly indicate that the cytotoxicity of AuNPs depend not only on the concentration, but also the size of the nanoparticles

Vapor phase treatment–total reflection X-ray fluorescence for trace elemental analysis of silicon wafer surface

International Nuclear Information System (INIS)

Takahara, Hikari; Mori, Yoshihiro; Shibata, Harumi; Shimazaki, Ayako; Shabani, Mohammad B.; Yamagami, Motoyuki; Yabumoto, Norikuni; Nishihagi, Kazuo; Gohshi, Yohichi

2013-01-01

Vapor phase treatment (VPT) was under investigation by the International Organization for Standardization/Technical Committee 201/Working Group 2 (ISO/TC201/WG2) to improve the detection limit of total reflection X-ray fluorescence spectroscopy (TXRF) for trace metal analysis of silicon wafers. Round robin test results have confirmed that TXRF intensity increased by VPT for intentional contamination with 5 × 10 9 and 5 × 10 10 atoms/cm 2 Fe and Ni. The magnification of intensity enhancement varied greatly (1.2–4.7 in VPT factor) among the participating laboratories, though reproducible results could be obtained for average of mapping measurement. SEM observation results showed that various features, sizes, and surface densities of particles formed on the wafer after VPT. The particle morphology seems to have some impact on the VPT efficiency. High resolution SEM observation revealed that a certain number of dots with SiO 2 , silicate and/or carbon gathered to form a particle and heavy metals, Ni and Fe in this study were segregated on it. The amount and shape of the residue should be important to control VPT factor. - Highlights: • This paper presents a summary of study results of VPT–TXRF using ISO/TC201/WG2. • Our goal is to analyze the trace metallic contamination on silicon wafer with concentrations below 1 × 10 10 atoms/cm 2 . • The efficiency and mechanism of VPT are discussed under several round robin tests and systematic studies

Sweeping total reflection X-ray fluorescence optimisation to monitor the metallic contamination into IC manufacturing

International Nuclear Information System (INIS)

Borde, Yannick; Danel, Adrien; Roche, Agnes; Veillerot, Marc

2008-01-01

Among the methods available on the market today to control as metallic contamination in integrated circuit manufacturing, Sweeping Total reflection X-ray Fluorescence mode appears a very good method, providing fast and entire wafer mapping. With the goal of a pertinent use of Sweeping Total reflection X-ray Fluorescence in advanced Integrated Circuit manufacturing this work discusses how acceptable levels of contamination specified by the production (low levels to be detected) can be taken into account. The relation between measurement results (surface coverage, throughput, low limit of detection, limit of quantification, quantification of localized contamination) and Sweeping Total reflection X-ray Fluorescence parameters (number of measurement points and integration time per point) is presented in details. In particular, a model is proposed to explain the mismatch between actual surface contamination in a localized spot on wafer and Total reflection X-ray Fluorescence reading. Both calibration and geometric issues have been taken into account

Characterization of silicon-on-insulator wafers

Science.gov (United States)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Graphene-Decorated Nanocomposites for Printable Electrodes in Thin Wafer Devices

Science.gov (United States)

Bakhshizadeh, N.; Sivoththaman, S.

2017-12-01

Printable electrodes that induce less stress and require lower curing temperatures compared to traditional screen-printed metal pastes are needed in thin wafer devices such as future solar cells, and in flexible electronics. The synthesis of nanocomposites by incorporating graphene nanopowders as well as silver nanowires into epoxy-based electrically conductive adhesives (ECA) is examined to improve electrical conductivity and to develop alternate printable electrode materials that induce less stress on the wafer. For the synthesized graphene and Ag nanowire-decorated ECA nanocomposites, the curing kinetics were studied by dynamic and isothermal differential scanning calorimetry measurements. Thermogravimetric analysis on ECA, ECA-AG and ECA/graphene nanopowder nanocomposites showed that the temperatures for onset of decomposition are higher than their corresponding glass transition temperature ( T g) indicating an excellent thermal resistance. Printed ECA/Ag nanowire nanocomposites showed 90% higher electrical conductivity than ECA films, whereas the ECA/graphene nanocomposites increased the conductivity by over two orders of magnitude. Scanning electron microscopy results also revealed the effect of fillers morphology on the conductivity improvement and current transfer mechanisms in nanocomposites. Residual stress analysis performed on Si wafers showed that the ECA and nanocomposite printed wafers are subjected to much lower stress compared to those printed with metallic pastes. The observed parameters of low curing temperature, good thermal resistance, reasonably high conductivity, and low residual stress in the ECA/graphene nanocomposite makes this material a promising alternative in screen-printed electrode formation in thin substrates.

The Effects of Industry Type, Company Size and Performance on Chinese Companies’ IC Disclosure: A Research Note

Directory of Open Access Journals (Sweden)

Yi An

2011-09-01

Full Text Available This paper examines the effects of industry type, firm size and corporate performance on intellectual capital (IC disclosure among Chinese (mainland companies. It was found that industry type did not have a significant influence on IC reporting practices of Chinese firms; the larger firms generally reported more IC information than the relatively smaller firms; and there was a positive relationship between corporate performance and IC disclosure. This paper contributes to fairly limited literature regarding the associations between the level of IC disclosure and a variety of relevant impact factors, in particular in the Chinese mainland context. In addition, the findings of this research provide some references for policy-makers while developing an IC reporting framework applicable to the Chinese environment.

Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

International Nuclear Information System (INIS)

Wang, D.; Ueda, A.; Takada, H.; Nakashima, H.

2006-01-01

A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τ g ) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron-hole droplet in the band-edge emission

IC Associated Conditions

Science.gov (United States)

... Bowel Syndrome Lupus Pelvic Floor Dysfunction Pudendal Neuralgia Sjogren’s Syndrome Vulvodynia Newly Diagnosed Toolkit IC Awareness Toolkit Know ... Bowel Syndrome Lupus Pelvic Floor Dysfunction Pudendal Neuralgia Sjogren’s Syndrome Vulvodynia Click to learn more about these and ...

development and evaluation of lyophilized thiolated-chitosan wafers

African Journals Online (AJOL)

User

THIOLATED-CHITOSAN WAFERS FOR BUCCAL DELIVERY. OF PROTEIN ... of the thiolated polymer incorporating per polymer weight, 10 % each of glycerol as plasticizer, D-mannitol as ..... delivery systems: in vitro stability, in vivo fate, and ...

Purification, crystallization and preliminary X-ray analysis of aminoglycoside-2′′-phosphotransferase-Ic [APH(2′′)-Ic] from Enterococcus gallinarum

International Nuclear Information System (INIS)

Byrnes, Laura J.; Badarau, Adriana; Vakulenko, Sergei B.; Smith, Clyde A.

2008-01-01

APH(2′′)-Ic is an enzyme that is responsible for high-level gentamicin resistance in E. gallinarum isolates. Crystals of the wild-type enzyme and three mutants have been prepared and a complete X-ray diffraction data set was collected to 2.15 Å resolution from an F108L crystal. Bacterial resistance to aminoglycoside antibiotics is primarily the result of deactivation of the drugs. Three families of enzymes are responsible for this activity, with one such family being the aminoglycoside phosphotransferases (APHs). The gene encoding one of these enzymes, aminoglycoside-2′′-phosphotransferase-Ic [APH(2′′)-Ic] from Enterococcus gallinarum, has been cloned and the wild-type protein (comprising 308 amino-acid residues) and three mutants that showed elevated minimum inhibitory concentrations towards gentamicin (F108L, H258L and a double mutant F108L/H258L) were expressed in Escherichia coli and subsequently purified. All APH(2′′)-Ic variants were crystallized in the presence of 14–20%(w/v) PEG 4000, 0.25 M MgCl 2 , 0.1 M Tris–HCl pH 8.5 and 1 mM Mg 2 GTP. The crystals belong to the monoclinic space group C2, with one molecule in the asymmetric unit. The approximate unit-cell parameters are a = 82.4, b = 54.2, c = 77.0 Å, β = 108.8°. X-ray diffraction data were collected to approximately 2.15 Å resolution from an F108L crystal at beamline BL9-2 at SSRL, Stanford, California, USA

Comparative TEM study of bonded silicon/silicon interfaces fabricated by hydrophilic, hydrophobic and UHV wafer bonding

International Nuclear Information System (INIS)

Reznicek, A.; Scholz, R.; Senz, S.; Goesele, U.

2003-01-01

Wafers of Czochralski-grown silicon were bonded hydrophilically, hydrophobically and in ultrahigh vacuum (UHV) at room temperature. Wafers bonded hydrophilically adhere together by hydrogen bonds, those bonded hydrophobically by van der Waals forces and UHV-bonded ones by covalent bonds. Annealing the pre-bonded hydrophilic and hydrophobic wafer pairs in argon for 2 h at different temperatures increases the initially low bonding energy. UHV-bonded wafer pairs were also annealed to compare the results. Transmission electron microscopy (TEM) investigations show nano-voids at the interface. The void density depends on the initial bonding strength. During annealing the shape, coverage and density of the voids change significantly

Determining the size and concentration dependence of gold nanoparticles in vitro cytotoxicity (IC{sub 50}) test using WST-1 assay

Energy Technology Data Exchange (ETDEWEB)

Rosli, Nur Shafawati binti; Rahman, Azhar Abdul [School of Physics, Universiti Sains Malaysia, 11800, Pulau Pinang (Malaysia); Aziz, Azlan Abdul [School of Physics, Universiti Sains Malaysia, 11800, Pulau Pinang (Malaysia); Nano-Biotechnology Research and Innovation (NanoBRI), Institute for Research in Molecular Medicine (INFORMM), Universiti Sains Malaysia, 11800, Pulau Pinang (Malaysia); Shamsuddin, Shaharum [Nano-Biotechnology Research and Innovation (NanoBRI), Institute for Research in Molecular Medicine (INFORMM), Universiti Sains Malaysia, 11800, Pulau Pinang (Malaysia); School of Health Sciences, Health Campus, Universiti Sains Malaysia, 16150 Kubang Kerian, Kelantan (Malaysia)

2015-04-24

Gold nanoparticles (AuNPs) received a great deal of attention for biomedical applications, especially in diagnostic imaging and therapeutics. Even though AuNPs have potential benefits in biomedical applications, the impact of AuNPs on human and environmental health still remains unclear. The use of AuNPs which is a high-atomic-number materials, provide advantages in terms of radiation dose enhancement. However, before this can become a clinical reality, cytotoxicity of the AuNPs has to be carefully evaluated. Cytotoxicity test is a rapid, standardized test that is very sensitive to determine whether the nanoparticles produced are harmful or benign on cellular components. In this work the size and concentration dependence of AuNPs cytotoxicity in breast cancer cell lines (MCF-7) are tested by using WST-1 assay. The sizes of AuNPs tested were 13 nm, 50 nm, and 70 nm. The cells were seeded in the 96-well plate and were treated with different concentrations of AuNPs by serial dilution for each size of AuNPs. The high concentration of AuNPs exhibit lower cell viability compared to low concentration of AuNPs. We quantified the toxicity of AuNPs in MCF-7 cell lines by determining the IC{sub 50} values in WST-1 assays. The IC{sub 50} values (inhibitory concentrations that effected 50% growth inhibition) of 50 nm AuNPs is lower than 13 nm and 70 nm AuNPs. Mean that, 50nm AuNPs are more toxic to the MCF-7 cells compared to smaller and larger sizes AuNPs. The presented results clearly indicate that the cytotoxicity of AuNPs depend not only on the concentration, but also the size of the nanoparticles.

Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods

Directory of Open Access Journals (Sweden)

Hai Au Huynh

2015-01-01

Full Text Available Direct power injection (DPI and bulk current injection (BCI methods are defined in IEC 62132-3 and IEC 62132-4 as the electromagnetic immunity test method of integrated circuits (IC. The forward power measured at the RF noise generator when the IC malfunctions is used as the measure of immunity level of the IC. However, the actual power that causes failure in ICs is different from forward power measured at the noise source. Power transfer efficiency is used as a measure of power loss of the noise injection path. In this paper, the power transfer efficiencies of DPI and BCI methods are derived and validated experimentally with immunity test setup of a clock divider IC. Power transfer efficiency varies significantly over the frequency range as a function of the test method used and the IC input impedance. For the frequency range of 15 kHz to 1 GHz, power transfer efficiency of the BCI test was constantly higher than that of the DPI test. In the DPI test, power transfer efficiency is particularly low in the lower test frequency range up to 10 MHz. When performing the IC immunity tests following the standards, these characteristics of the test methods need to be considered.

Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

Directory of Open Access Journals (Sweden)

Shisheng Cai

2017-03-01

Full Text Available In order to obtain excellent physical properties and ultrathin devices, thinning technique plays an important role in semiconductor industry with the rapid development of wearable electronic devices. This study presents a physical nano-diamond grinding technique without any chemistry to obtain ultrathin silicon substrate. The nano-diamond with spherical shape repeats nano-cutting and penetrating surface to physically etch silicon wafer during grinding process. Nano-diamond grinding induces an ultrathin “amorphous layer” on silicon wafer and thus the mismatch strain between the amorphous layer and substrate leads to stability transition from the spherical to non-spherical deformation of the wafer. Theoretical model is proposed to predict and analyze the deformation of amorphous layer/silicon substrate system. Furthermore, the deformation bifurcation behavior of amorphous layer/silicon substrate system is analyzed. As the mismatch strain increases or thickness decreases, the amorphous layer/silicon substrate system may transit to non-spherical deformation, which is consistent to the experimental results. The amorphous layer stresses are also obtained to predict the damage of silicon wafer.

Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

Science.gov (United States)

Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

2017-04-01

We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

Sample pretreatment for the determination of metal impurities in silicon wafer

International Nuclear Information System (INIS)

Chung, H. Y.; Kim, Y. H.; Yoo, H. D.; Lee, S. H.

1999-01-01

The analytical results obtained by microwave digestion and acid digestion methods for sample pretreatment to determine metal impurities in silicon wafer by inductively coupled plasma--mass spectrometry(ICP-MS) were compared. In order to decompose the silicon wafer, a mixed solution of HNO 3 and HF was added to the sample and the metal elements were determined after removing the silicon matrix by evaporating silicon in the form of Si-F. The recovery percentages of Ni, Cr and Fe were found to be 95∼106% for both microwave digestion and acid digestion methods. The recovery percentage of Cu obtained by the acid digestion method was higher than that obtained by the microwave digestion method. For Zn, however, the microwave digestion method gave better result than the acid digestion method. Fe was added to a silicon wafer using a spin coater. The concentration of Fe in this sample was determined by ICP-MS, and the same results were obtained in the two pretreatment methods

Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

International Nuclear Information System (INIS)

Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

2017-01-01

We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

Wafer-scale pixelated detector system

Science.gov (United States)

Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

2017-10-17

A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

Industrial Silicon Wafer Solar Cells

OpenAIRE

Neuhaus, Dirk-Holger; Münzer, Adolf

2007-01-01

In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future e...

Optimal Wafer Cutting in Shuttle Layout Problems

DEFF Research Database (Denmark)

Nisted, Lasse; Pisinger, David; Altman, Avri

2011-01-01

. The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

Science.gov (United States)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

Conceptualising Intellectual Capital (IC) as Language Game and Power

DEFF Research Database (Denmark)

Jørgensen, Kenneth Mølbjerg

2006-01-01

Intellectual Capital (IC) can be viewed as knowledge about knowledge, knowledge creation and how such processes might be leveraged into value. Developing a critical understanding of IC requires a historical and contextual understanding of how IC has emerged and how IC is used. This paper, drawing...... this process of social construction. The paper concludes by proposing some methodological guidelines for conducting critical genealogical research on intellectual capital....

Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

CERN Multimedia

Honma, Alan

1999-01-01

Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

Improvement of the thickness distribution of a quartz crystal wafer by numerically controlled plasma chemical vaporization machining

International Nuclear Information System (INIS)

Shibahara, Masafumi; Yamamura, Kazuya; Sano, Yasuhisa; Sugiyama, Tsuyoshi; Endo, Katsuyoshi; Mori, Yuzo

2005-01-01

To improve the thickness uniformity of thin quartz crystal wafer, a new machining process that utilizes an atmospheric pressure plasma was developed. In an atmospheric pressure plasma process, since the kinetic energy of ions that impinge to the wafer surface is small and the density of the reactive species is large, high-efficiency machining without damage is realized, and the thickness distribution is corrected by numerically controlled scanning of the quartz wafer to the localized high-density plasma. By using our developed machining process, the thickness distribution of an AT cut wafer was improved from 174 nm [peak to valley (p-v)] to 67 nm (p-v) within 94 s. Since there are no unwanted spurious modes in the machined quartz wafer, it was proved that the developed machining method has a high machining efficiency without any damage

Analysis Of Factors Affecting Gravity-Induced Deflection For Large And Thin Wafers In Flatness Measurement Using Three-Point-Support Method

Directory of Open Access Journals (Sweden)

Liu Haijun

2015-12-01

Full Text Available Accurate flatness measurement of silicon wafers is affected greatly by the gravity-induced deflection (GID of the wafers, especially for large and thin wafers. The three-point-support method is a preferred method for the measurement, in which the GID uniquely determined by the positions of the supports could be calculated and subtracted. The accurate calculation of GID is affected by the initial stress of the wafer and the positioning errors of the supports. In this paper, a finite element model (FEM including the effect of initial stress was developed to calculate GID. The influence of the initial stress of the wafer on GID calculation was investigated and verified by experiment. A systematic study of the effects of positioning errors of the support ball and the wafer on GID calculation was conducted. The results showed that the effect of the initial stress could not be neglected for ground wafers. The wafer positioning error and the circumferential error of the support were the most influential factors while the effect of the vertical positioning error was negligible in GID calculation.

Automatic Semiconductor Wafer Image Segmentation for Defect Detection Using Multilevel Thresholding

Directory of Open Access Journals (Sweden)

Saad N.H.

2016-01-01

Full Text Available Quality control is one of important process in semiconductor manufacturing. A lot of issues trying to be solved in semiconductor manufacturing industry regarding the rate of production with respect to time. In most semiconductor assemblies, a lot of wafers from various processes in semiconductor wafer manufacturing need to be inspected manually using human experts and this process required full concentration of the operators. This human inspection procedure, however, is time consuming and highly subjective. In order to overcome this problem, implementation of machine vision will be the best solution. This paper presents automatic defect segmentation of semiconductor wafer image based on multilevel thresholding algorithm which can be further adopted in machine vision system. In this work, the defect image which is in RGB image at first is converted to the gray scale image. Median filtering then is implemented to enhance the gray scale image. Then the modified multilevel thresholding algorithm is performed to the enhanced image. The algorithm worked in three main stages which are determination of the peak location of the histogram, segmentation the histogram between the peak and determination of first global minimum of histogram that correspond to the threshold value of the image. The proposed approach is being evaluated using defected wafer images. The experimental results shown that it can be used to segment the defect correctly and outperformed other thresholding technique such as Otsu and iterative thresholding.

A perspective on stage dynamics and control

NARCIS (Netherlands)

Butler, H.

2008-01-01

In the semiconductor industry, a wafer stepper is used to expose the pattern on a mask (‘reticle’) onto a wafer. Accurate positioning of the reticle and the wafer is of crucial importance for creating a working IC. This paper reflects on the stage dynamics and control design in Stepper technology,

External self-gettering of nickel in float zone silicon wafers

Science.gov (United States)

Gay, N.; Martinuzzi, S.

1997-05-01

During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

Exploring physical and chemical factors influencing the properties of recombinant prion protein and the real-time quaking-induced conversion (RT-QuIC) assay.

Science.gov (United States)

Cheng, Keding; Sloan, Angela; Avery, Kristen M; Coulthart, Michael; Carpenter, Michael; Knox, J David

2014-01-01

Real-time quaking-induced conversion (RT-QuIC), a highly specific and sensitive assay able to detect low levels of the disease-inducing isoform of the prion protein (PrP(d)) in brain tissue biopsies and cerebral spinal fluid, has great potential to become a method for diagnosing prion disease ante mortem. In order to standardize the assay method for routine analysis, an understanding of how physical and chemical factors affect the stability of the recombinant prion protein (rPrP) substrate and the RT-QuIC assay's sensitivity, specificity, and reproducibility is required. In this study, using sporadic Creutzfeldt-Jakob Disease brain homogenate to seed the reactions and an in vitro-expressed recombinant prion protein, hamster rPrP, as the substrate, the following factors affecting the RT-QuIC assay were examined: salt and substrate concentrations, substrate storage, and pH. Results demonstrated that both the generation of the quality and quantities of rPrP substrate critical to the reaction, as well as the RT-QuIC reaction itself required strict adherence to specific physical and chemical conditions. Once optimized, the RT-QuIC assay was confirmed to be a very specific and sensitive assay method for sCJD detection. Findings in this study indicate that further optimization and standardization of RT-QuIC assay is required before it can be adopted as a routine diagnostic test.

Fermi Non-detections of Four X-Ray Jet Sources and Implications for the IC/CMB Mechanism

Science.gov (United States)

Breiding, Peter; Meyer, Eileen T.; Georganopoulos, Markos; Keenan, M. E.; DeNigris, N. S.; Hewitt, Jennifer

2017-11-01

Since its launch in 1999, the Chandra X-ray observatory has discovered several dozen X-ray jets associated with powerful quasars. In many cases, the X-ray spectrum is hard and appears to come from a second spectral component. The most popular explanation for the kpc-scale X-ray emission in these cases has been inverse-Compton (IC) scattering of Cosmic Microwave Background (CMB) photons by relativistic electrons in the jet (the IC/CMB model). Requiring the IC/CMB emission to reproduce the observed X-ray flux density inevitably predicts a high level of gamma-ray emission, which should be detectable with the Fermi Large Area Telescope (LAT). In previous work, we found that gamma-ray upper limits from the large-scale jets of 3C 273 and PKS 0637-752 violate the predictions of the IC/CMB model. Here, we present Fermi/LAT flux density upper limits for the X-ray jets of four additional sources: PKS 1136-135, PKS 1229-021, PKS 1354+195, and PKS 2209+080. We show that these limits violate the IC/CMB predictions at a very high significance level. We also present new Hubble Space Telescope observations of the quasar PKS 2209+080 showing a newly detected optical jet, and Atacama Large Millimeter/submillimeter Array band 3 and 6 observations of all four sources, which provide key constraints on the spectral shape that enable us to rule out the IC/CMB model.

Extracción de cobre desde soluciones clorhídricas con LIX 860N-IC y LIX 84-IC

Directory of Open Access Journals (Sweden)

Navarro, Carlos María

2001-08-01

Full Text Available In this work, the extraction of copper from chloride solutions with two hydroxyoximes: 5- nonylsalicylaldoxime (LIX 860N-IC and 2-hydroxy-5-nonylacetophenona oxime (LIX 84-IC is discussed. The results showed that an increase in the acidity and an increase in the total concentration of chloride ions in the aqueous phase decreased significantly the extraction of copper as well as the extraction of iron for both extractants. This effect of the chloride ions can be explained by the formation of a series of chloro complexes of Cu(II and Fe(III in the aqueous phase. The effect of initial pH and total chloride concentration on the extraction of chloride by the organic phase suggests that LIX 860N-IC, and to a lesser extent LIX 84-IC, extract small amounts of the cationic complex, CuCl⁺. An increase in the concentration of chloride ions also produced a small decrease in the rate of copper extraction with both hydroxyoximes.

En este trabajo se discute el estudio de la extracción de cobre desde soluciones clorhídricas con dos hidroxioximas: 5-nonilsalicilaldoxima (LIX 860N-IC, y 2-hidroxi-5 nonilacetofenona oxima (LIX 84-IC. Los resultados indicaron que al aumentar la acidez o aumentar la concentración de cloruro en la fase acuosa se produce una significativa disminución en la extracción de cobre y hierro con ambas hidroxioximas. Este efecto del ion cloruro se explica por la formación de varios clorocomplejos de Cu(II y Fe(III en la solución acuosa. El efecto del pH y la concentración total de cloruro en la extracción de cloruro sugiere que el LIX 860N-IC, y en menor grado el LIX 84-IC extraen pequeñas cantidades del catión monovalente, CuCl⁺. Se determinó también que un aumento en la concentración de cloruro en la solución acuosa produce una leve disminución en la velocidad de extracción del cobre con ambas hidroxioximas.

Formation of III–V-on-insulator structures on Si by direct wafer bonding

International Nuclear Information System (INIS)

Yokoyama, Masafumi; Iida, Ryo; Ikku, Yuki; Kim, Sanghyeon; Takenaka, Mitsuru; Takagi, Shinichi; Takagi, Hideki; Yasuda, Tetsuji; Yamada, Hisashi; Ichikawa, Osamu; Fukuhara, Noboru; Hata, Masahiko

2013-01-01

We have studied the formation of III–V-compound-semiconductors-on-insulator (III–V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III–V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O 2 plasma-assisted DWB process with ECR sputtered SiO 2 BOX layers and a DWB process based on atomic-layer-deposition Al 2 O 3 (ALD-Al 2 O 3 ) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO 2 and ALD-Al 2 O 3 BOX layers are desorption of Ar and H 2 O gas, respectively. In order to suppress micro-void generation in the ECR-SiO 2 BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al 2 O 3 BOX layers to increase the deposition temperature of the ALD-Al 2 O 3 BOX layers. It is also another possible solution to deposit ALD-Al 2 O 3 BOX layers on thermally oxidized SiO 2 layers, which can absorb the desorption gas from ALD-Al 2 O 3 BOX layers. (invited paper)

Fabrication of high aspect ratio through-wafer copper interconnects by reverse pulse electroplating

International Nuclear Information System (INIS)

Gu, Changdong; Zhang, Tong-Yi; Xu, Hui

2009-01-01

This study aims to fabricate high aspect ratio through-wafer copper interconnects by a simple reverse pulse electroplating technique. High aspect-ratio (∼18) through-wafer holes obtained by a two-step deep reactive ion etching (DRIE) process exhibit a taper profile, which might automatically optimize the local current density distribution during the electroplating process, thereby achieving void-free high aspect-ratio copper vias

Measuring IC following a semi-qualitative approach: An integrated framework

Directory of Open Access Journals (Sweden)

Chiara Verbano

2013-09-01

Full Text Available Purpose: Considering the different IC measures adopted in literature, the advantages of adopting semi-qualitative measures, and the lack of an agreed system for IC evaluation, the purpose of the paper is to analyse literature on IC measurement following a semi-qualitative approach, with the final intent to build an IC measurement framework. Design/methodology/approach: A literature review on IC measurement system, following a semi-qualitative approach, has been conducted and analysed, in order to re-organize and synthesize all items used in previous researches. Findings: An integrated framework emerged from this research and it constitutes an IC  measurement system, created gathering and integrating different items previously adopted in literature. Each of these variables has been organized in categories belonging to one of the three main components of IC: human capital, internal structural capital and relational capital. Originality/value: This research provides an integrated tool for IC evaluation, fostering toward a well agreed measurement system that is still lacking in literature. This framework could be interesting  not only for the academic world, which in the last two decades reveals increasing attention to IC, but also for the management of the companies, that with IC measurement can increase awareness of the firm’s value and develop internal auditing system to support the management of these assets. Moreover, it could be a useful instrument for the communication of IC value to the external stakeholders, as customers, suppliers and especially shareholders, and to investors and financial analysts.

InGaAs-OI Substrate Fabrication on a 300 mm Wafer

Directory of Open Access Journals (Sweden)

Sebastien Sollier

2016-09-01

Full Text Available In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs wafer on insulator (InGaAs-OI substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM, scanning acoustic microscopy (SAM, and HR-XRD, to insure the crystalline quality of the post transferred layer.

Application Of The SPV-based Surface Lifetime Technique To In-Line Monitoring Of Surface Cu Contamination

Science.gov (United States)

D'Amico, John; Savtchouk, Alexandre; Wilson, Matthew; Kim, Chul Hong; Yoo, Hyung Won; Lee, Chang Hwan; Kim, Tae Kyoung; Son, Sang Hoon

2009-09-01

Implementation of Cu interconnects into Silicon Integrated Circuits (IC's) has been instrumental in the continuing improvement of IC device performance. Copper as a well known Gate Oxide Integrity (GOI) killer [1, 2] requires extensive protocols to minimize the possibility of cross contamination. Despite such protocols the risk for cross contamination exists, and consequently there is the need for in-line Cu cross-contamination detection metrology. Preferably the metrology will be non-destructive, fast, and capable of mapping on product wafers. Up to now the most common approaches for monitoring Cu contamination in IC fabrication lines either measure Cu in the bulk Si, which is not applicable to Cu cross-contamination monitoring because Back-End-of-the-Line thermal budgets restrict the ability to diffuse the surface Cu into the bulk Si; or the techniques are not optimal for in-line monitoring due to their destructive, time-consuming, or costly nature. In this work we demonstrate for the first time the application of the ac-Surface Photo Voltage (ac-SPV) surface lifetime approach [3] to in-line, full wafer coverage mapping of low level (metrology system. Furthermore, because the metrology is non-contact (utilizing edge-grip handling) and non-destructive, it is directly applicable to measurement of production wafers. In-line fab data acquired using this metrology is presented and compared to data from Inductively Coupled Plasma Mass Spectroscopy (ICP-MS).

Single-mode glass waveguide technology for optical interchip communication on board level

Science.gov (United States)

Brusberg, Lars; Neitz, Marcel; Schröder, Henning

2012-01-01

The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a

Linear Fresnel zone plate based two-state alignment system for 0.25 micron x-ray lithography

International Nuclear Information System (INIS)

Chen, G.

1993-01-01

X-ray lithography has proven to be a cost effective and promising technique for fabricating Integrated Circuits (ICs) with minimum feature sizes of less than 0.25 μm. Since IC fabrication is a multilevel process, to preserve the functionality of devices, circuit patterns printed at each lithography level must match existing patterns on the wafer with an accuracy of less than 1/3 ∼ 1/5 of the minimum feature size. An alignment system is used to position the mask relative to the wafer so that mask circuit patterns can be printed on the wafer at the designed position. As the minimum printed feature size shrinks, the overlay requirements of a lithography tool become more stringent. A stepper for 0.25 μm feature device fabrication requires an overlay accuracy of 0.075 μm, of which only 0.05 μm (mean + 3σ) is allocated to its alignment system. This thesis presents the development of a linear Fresnel zone late based two-state alignment (TSA) method for a 0.25 μm x-ray lithography tool. The authors first analyze the overlay requirement in a lithography process and the error allocation to the alignment system for a 0.25 μ feature x-ray lithography tool. They then describe the principle of the two-state alignment, its computer simulation and the optimal alignment mark design. They carried out an optical bench test for the one-axes alignment setup and experimentally evaluated the performance of the system. They developed a three-axes TSA system and integrated the system with the ES-3 x-ray beamline to construct the CXrL aligner, an experimental x-ray exposure system in CXrL. They measured the alignment accuracy of the exposure system to be better than 0.035 μm (3σ) on both metal and dielectric alignment mark substrates. They also studied the effect of processing coatings on the alignment signal with different wafer mark substrates. They successfully printed the 0.5 μm gate level patterns for the first NMOS test chip at CXrL

SiC epitaxial layer growth in a novel multi-wafer VPE reactor

Energy Technology Data Exchange (ETDEWEB)

Burk, A.A. Jr.; O`Loughlin, M.J. [Northrop Grumman Advanced Technology Lab., Baltimore, MD (United States); Mani, S.S. [Northrop Grumman Science and Technology Center, Pittsburgh, PA (United States)

1998-06-01

Preliminary results are presented for SiC epitaxial layer growth employing a unique planetary SiC-VPE reactor. The high-throughput, multi-wafer (7 x 2-inch) reactor, was designed for atmospheric and reduced pressure operation at temperatures up to and exceeding 1600 C. Specular epitaxial layers have been grown in the reactor at growth rates from 3-5 {mu}m/hr. The thickest layer grown to data was 42 {mu}m. The layers exhibit minimum unintentional n-type doping of {proportional_to}1 x 10{sup 15} cm{sup -3}, room temperature mobilities of {proportional_to}1000 cm{sup 2}/Vs, and intentional n-type doping from {proportional_to}5 x 10{sup 15} cm{sup -3} to >1 x 10{sup 19} cm{sup -3}. Intrawafer thickness and doping uniformities of 4% and 7% (standard deviation/mean) have been obtained, respectively, on 35 mm diameter substrates. Recently, 3% thickness uniformity has been demonstrated on a 50 mm substrate. Within a run, wafer-to-wafer thickness deviation is {proportional_to}4-14%. Doping variation is currently larger, ranging as much as a factor of two from the highest to the lowest doped wafer. Continuing efforts to improve the susceptor temperature uniformity and reduce unintentional hydrocarbon generation to improve layer uniformity and reproducibility, are presented. (orig.) 18 refs.

A Study of the Charge Trap Transistor (CTT) for Post-Fab Modification of Wafers

Science.gov (United States)

2018-04-01

AFRL-RY-WP-TR-2018-0030 A STUDY OF THE CHARGE TRAP TRANSISTOR (CTT) FOR POST- FAB MODIFICATION OF WAFERS Subramanian S. Iyer University of California...Final 13 June 2016 – 13 December 2017 4. TITLE AND SUBTITLE A STUDY OF THE CHARGE TRAP TRANSISTOR (CTT) FOR POST- FAB MODIFICATION OF WAFERS 5a. CONTRACT

Ultra-precision engineering in lithographic exposure equipment for the semiconductor industry.

Science.gov (United States)

Schmidt, Robert-H Munnig

2012-08-28

The developments in lithographic tools for the production of an integrated circuit (IC) are ruled by 'Moore's Law': the density of components on an IC doubles in about every two years. The corresponding size reduction of the smallest detail in an IC entails several technological breakthroughs. The wafer scanner, the exposure system that defines those details, is the determining factor in these developments. This review deals with those aspects of the positioning systems inside these wafer scanners that enable the extension of Moore's Law into the future. The design of these systems is increasingly difficult because of the accuracy levels in the sub-nanometre range coupled with motion velocities of several metres per second. In addition to the use of feedback control for the reduction of errors, high-precision model-based feed-forward control is required with an almost ideally reproducible motion-system behaviour and a strict limitation of random disturbing events. The full mastering of this behaviour even includes material drift on an atomic scale and is decisive for the future success of these machines.

ASD IC for the thin gap chambers in the LHC Atlas experiment

International Nuclear Information System (INIS)

Sasaki, Osamu; Yoshida, Mitsuhiro

1999-01-01

An amplifier-shaper-discriminator (ASD) chip was designed and built for Thin Gap Chambers in the forward muon trigger system of the LHC Atlas experiment. The ASD IC uses SONY Analog Master Slice bipolar technology. The IC contains 4 channels in a QFP48 package. The gain of its first stage (preamplifier) is approximately 0.8V/pC and output from the preamplifier is received by a shaper (main-amplifier) with a gain of 7. The baseline restoration circuit is incorporated in the main-amplifier. The threshold voltage for discriminator section is common to the 4 channels and their digital output level is LVDS-compatible. The IC also has analog output of the preamplifier. The equivalent noise charge at input capacitance of 150 pF is around 7,500 electrons. The power dissipation with LDVS outputs (100 Omega load) is 59mW/ch

ASD IC for the thin gap chambers in the LHC ATLAS experiment

CERN Document Server

Sasaki, O

1998-01-01

An amplifier-shaper-discriminator (ASD) chip was designed and built for Thin Gap Chambers in the forward muon trigger system of the LHC ATLAS experiment. The ASD IC uses SONY Analog Master Slice bipolar technology. The IC contains 4 $9 channels in a QFP48 package. The gain of its first stage (preamplifier) is approximately 0.8 V/pC and output from the preamplifier is received by a shaper (main-amplifier) with a gain of 7. The baseline restoration circuit is $9 incorporated in the main-amplifier. The threshold voltage for the discriminator section is common to the 4 channels and their digital output level is LVDS-compatible. The IC also has analog output for the preamplifier. The equivalent $9 noise charge at input capacitance of 150 pF is around 7500 electrons. The power dissipation with LDVS outputs (100 Omega load) is 59 mW/ch. (8 refs).

ASD IC for the thin gap chambers in the LHC ATLAS Experiment

CERN Document Server

Sasaki, O

1999-01-01

An amplifier-shaper-discriminator (ASD) chip was designed and built for Thin Gap Chambers in the forward muon trigger system of the LHC Atlas experiment. The ASD IC uses SONY Analog Master Slice bipolar technology. The IC contains 4 channels in a QFP48 package. The gain of its first stage (preamplifier) is approximately 0.8 V/pC and output from the preamplifier is received by a shaper (main-amplifier) with a gain of 7. The baseline restoration circuit is incorporated in the main-amplifier. The threshold voltage for discriminator section is common to the 4 channels and their digital output level is LVDS- compatible. The IC also has analog output of the preamplifier. The equivalent noise charge at input capacitance of 150 pF is around 7500 electrons. The power dissipation with LDVS outputs (100 Omega load) is 59 mW/ch.

Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

Science.gov (United States)

Kubair, D. V.; Spearing, S. M.

2006-03-01

Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

Science.gov (United States)

Kulshreshtha, Prashant Kumar

This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

3D Integration of MEMS and IC: Design, technology and simulations

OpenAIRE

Schjølberg-Henriksen, Kari

2009-01-01

* 3D integration: Opportunities and trends* e-CUBES: Tire pressure monitoring system (TPMS)* Package design including thermo-mechanical modeling* Technology development* Sensor packaging concept* Gold stud bump bonding* Device characterization and testing* Summary and outlook 3D Integration of MEMS and IC: Design, technology and simulations

Silicon-to-silicon wafer bonding using evaporated glass

DEFF Research Database (Denmark)

Weichel, Steen; Reus, Roger De; Lindahl, M.

1998-01-01

Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

Assessment of Electrodes Prepared from Wafers of Boron-doped Diamond for the Electrochemical Oxidation of Waste Lubricants

International Nuclear Information System (INIS)

Taylor, G.T.; Sullivan, I.A.; Newey, A.W.E.

2006-01-01

Electrochemical oxidation using boron-doped diamond electrodes is being investigated as a treatment process for radioactively contaminated oily wastes. Previously, it was shown that electrodes coated with a thin film of diamond were able to oxidise a cutting oil but not a mineral oil. These tests were inconclusive, because the electrodes lost their diamond coating during operation. Accordingly, an electrode prepared from a 'solid' wafer of boron-doped diamond is being investigated to determine whether it will oxidise mineral oils. The electrode has been tested with sucrose, a cutting oil and an emulsified mineral oil. Before and after each test, the state of the electrode was assessed by cyclic voltammetry with the ferro/ferricyanide redox couple. Analysis of the cyclic voltammogram suggested that material accumulated on the surface of the electrode during the tests. The magnitude of the effect was in the order: - emulsified mineral oil > cutting oil > sucrose. Despite this, the results indicated that the electrode was capable of oxidising the emulsified mineral oil. Confirmatory tests were undertaken in the presence of alkali to trap the carbon dioxide, but they had to be abandoned when the adhesive holding the diamond in the electrode was attacked by the alkali. Etching of the diamond wafer was also observed at the end of the tests. Surface corrosion is now regarded as an intrinsic part of the electrochemical oxidation on diamond, and it is expected that the rate of attack will determine the service life of the electrodes. (authors)

Desain dan Implementasi Virtual Laboratory Materi Osilator Analog berbasis IC OP-AMP

Directory of Open Access Journals (Sweden)

SYIFAUL FUADA

2016-08-01

Full Text Available ABSTRAK Laboratorium virtual merupakan salah satu platform laboratorium modern yang dapat mendukung kegiatan praktikum yang berjalan secara tradisional (Hand-on Laboratory.Penelitian ini bertujuan untuk mendesain dan mengimplementasikan Virtual Laboratory pada materi pembangkit sinyal dengan subtopik: Wien Bridge sebagai osilator RC, Hartley dan Colpitts sebagai osilator LC dan Astable Multivibrator sebagai osilator relaksasi,yang dibangun berbasis IC Operational Amplifier (OP-AMP.Jenis penelitian ini merupakan R&Dyang terdiri dari enam tahapan, yaitu:konsep, desain, pengumpulan bahan, pembuatan, pengujian dan pendistribusian. Aplikasi perangkat lunak berbasis dekstop ini telah diuji secara fungsional dengan 6 (enam aspek parameter yakni:uji polaritas kapastor; uji wiring; uji mode frekuensi dan mode perioda pada alat ukur frequency generator; uji specific decission pada trainer kit osilator hartley dan colpitts; uji kesesuaian antara frekuensi ouput dari masing-masing osilator dengan perhitungan teorema dan hasil percobaan sesungguhnya; dan uji kualitas media. Hasil secara keseluruhan telah sesuai dengan ekspektasi didalam story board. Kata kunci: IC OP-AMP, Osilator analog, Laboratorium virtual ABSTRACT The Virtual Laboratory is as one of modern laboratory platform which able to supportthe hand-on worklab. The goal of this research are for designing and implementing a Virtual Laboratory of signal generator material with subtopics i.e. the Wien Bridge as an RC oscillator, the Hartley and Colpitts as LC oscillator and the astable multivibrator as relaxation oscillator which assembled based on Operational Amplifier Integrated Circuit (OP-AMP.This research is R&D type which consists of six stages, i.e. concept, design, materials collection, assembling, testing and distribution. This desktop-based software application has been functionally tested with six aspect of parameters such as: capacitor polarity testing; wiring testing; testing of frequency

Wafer defect detection by a polarization-insensitive external differential interference contrast module.

Science.gov (United States)

Nativ, Amit; Feldman, Haim; Shaked, Natan T

2018-05-01

We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

Radon measurements at IC-09 well of Chingshui geothermal field (Taiwan): A case study

International Nuclear Information System (INIS)

Chen, Y.; Kuo, T.; Fan, K.; Liang, H.; Tsai, C.; Chiang, C.; Su, C.

2011-01-01

Radon concentration was monitored during the flow tests of well IC-09 at the Chingshui geothermal field. The radon concentration was found to increase from 54 ± 29 to 983 ± 65 Bq/m 3 as a step function of production time, or cumulative production. The observed radon behavior can be explained by a radial composite model with the carbonate scales deposited in the skin zone near the well. The radius of skin zone near well IC-09 can be estimated with radon data at about 20 m using a plug flow model. Monitoring natural radon during the well flow tests is a helpful tracer to diagnose the formation damage near the well.

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

International Nuclear Information System (INIS)

Sokolovskij, R; Liu, P; Van Zeijl, H W; Mimoun, B; Zhang, G Q

2015-01-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies. (paper)

Magnetically Suspended Linear Pulse Motor for Semiconductor Wafer Transfer in Vacuum Chamber

Science.gov (United States)

Moriyama, Shin-Ichi; Hiraki, Naoji; Watanabe, Katsuhide; Kanemitsu, Yoichi

1996-01-01

This paper describes a magnetically suspended linear pulse motor for a semiconductor wafer transfer robot in a vacuum chamber. The motor can drive a wafer transfer arm horizontally without mechanical contact. In the construction of the magnetic suspension system, four pairs of linear magnetic bearings for the lift control are used for the guidance control as well. This approach allows us to make the whole motor compact in size and light in weight. The tested motor consists of a double-sided stator and a transfer arm with a width of 50 mm and a total length of 700 mm. The arm, like a ladder in shape, is designed as the floating element with a tooth width of 4 mm (a tooth pitch of 8 mm). The mover mass is limited to about 1.6 kg by adopting such an arm structure, and the ratio of thrust to mover mass reaches to 3.2 N/kg under a broad air gap (1 mm) between the stator teeth and the mover teeth. The performance testing was carried out with a transfer distance less than 450 mm and a transfer speed less than 560 mm/s. The attitude of the arm was well controlled by the linear magnetic bearings with a combined use, and consequently the repeatability on the positioning of the arm reached to about 2 micron. In addition, the positioning accuracy was improved up to about 30 micron through a compensation of the 128-step wave current which was used for the micro-step drive with a step increment of 62.5 micron.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

Science.gov (United States)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

Directory of Open Access Journals (Sweden)

S. A. Chizhik

2013-01-01

Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

Wafer-Scale Integration of Systolic Arrays,

Science.gov (United States)

1985-10-01

hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

Photolithography diagnostic expert systems: a systematic approach to problem solving in a wafer fabrication facility

Science.gov (United States)

Weatherwax Scott, Caroline; Tsareff, Christopher R.

1990-06-01

One of the main goals of process engineering in the semiconductor industry is to improve wafer fabrication productivity and throughput. Engineers must work continuously toward this goal in addition to performing sustaining and development tasks. To accomplish these objectives, managers must make efficient use of engineering resources. One of the tools being used to improve efficiency is the diagnostic expert system. Expert systems are knowledge based computer programs designed to lead the user through the analysis and solution of a problem. Several photolithography diagnostic expert systems have been implemented at the Hughes Technology Center to provide a systematic approach to process problem solving. This systematic approach was achieved by documenting cause and effect analyses for a wide variety of processing problems. This knowledge was organized in the form of IF-THEN rules, a common structure for knowledge representation in expert system technology. These rules form the knowledge base of the expert system which is stored in the computer. The systems also include the problem solving methodology used by the expert when addressing a problem in his area of expertise. Operators now use the expert systems to solve many process problems without engineering assistance. The systems also facilitate the collection of appropriate data to assist engineering in solving unanticipated problems. Currently, several expert systems have been implemented to cover all aspects of the photolithography process. The systems, which have been in use for over a year, include wafer surface preparation (HMDS), photoresist coat and softbake, align and expose on a wafer stepper, and develop inspection. These systems are part of a plan to implement an expert system diagnostic environment throughout the wafer fabrication facility. In this paper, the systems' construction is described, including knowledge acquisition, rule construction, knowledge refinement, testing, and evaluation. The roles

Experimental and theoretical analysis of integrated circuit (IC) chips on flexible substrates subjected to bending

Science.gov (United States)

Chen, Ying; Yuan, Jianghong; Zhang, Yingchao; Huang, Yonggang; Feng, Xue

2017-10-01

The interfacial failure of integrated circuit (IC) chips integrated on flexible substrates under bending deformation has been studied theoretically and experimentally. A compressive buckling test is used to impose the bending deformation onto the interface between the IC chip and the flexible substrate quantitatively, after which the failed interface is investigated using scanning electron microscopy. A theoretical model is established based on the beam theory and a bi-layer interface model, from which an analytical expression of the critical curvature in relation to the interfacial failure is obtained. The relationships between the critical curvature, the material, and the geometric parameters of the device are discussed in detail, providing guidance for future optimization flexible circuits based on IC chips.

X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

International Nuclear Information System (INIS)

Cha, Bo Kyung; Jeon, Seongchae; Seo, Chang-Woo

2016-01-01

This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 µm 1-poly/4-metal CMOS process. The pixel size is 100 µm×100 µm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd_2O_2S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

Energy Technology Data Exchange (ETDEWEB)

Cha, Bo Kyung, E-mail: goldrain99@kaist.ac.kr [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Jeon, Seongchae [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Seo, Chang-Woo [Department of Radiological Science, Yonsei University, Gangwon-do 220-710 (Korea, Republic of)

2016-09-21

This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 µm 1-poly/4-metal CMOS process. The pixel size is 100 µm×100 µm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd{sub 2}O{sub 2}S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

Wafer-level MOCVD growth of AlGaN/GaN-on-Si HEMT structures with ultra-high room temperature 2DEG mobility

Directory of Open Access Journals (Sweden)

Xiaoqing Xu

2016-11-01

Full Text Available In this work, we investigate the influence of growth temperature, impurity concentration, and metal contact structure on the uniformity and two-dimensional electron gas (2DEG properties of AlGaN/GaN high electron mobility transistor (HEMT structure grown by metal-organic chemical vapor deposition (MOCVD on 4-inch Si substrate. High uniformity of 2DEG mobility (standard deviation down to 0.72% across the radius of the 4-inch wafer has been achieved, and 2DEG mobility up to 1740.3 cm2/V⋅s at room temperature has been realized at low C and O impurity concentrations due to reduced ionized impurity scattering. The 2DEG mobility is further enhanced to 2161.4 cm2/V⋅s which is comparable to the highest value reported to date when the contact structure is switched from a square to a cross pattern due to reduced piezoelectric scattering at lower residual strain. This work provides constructive insights and promising results to the field of wafer-scale fabrication of AlGaN/GaN HEMT on Si.

Clinical efficacy and safety of ICS/LABA in patients with combined idiopathic pulmonary fibrosis and emphysema.

Science.gov (United States)

Dong, Fushi; Zhang, Yimei; Chi, Fangzhou; Song, Qi; Zhang, Lijuan; Wang, Yupeng; Che, Chunli

2015-01-01

The study aim was to explore the clinical efficacy and safety of inhaled corticosteroids (ICS)/long-acting beta2-agonists (LABA) in combined with idiopathic pulmonary fibrosis and emphysema. 45 patients with combined idiopathic pulmonary fibrosis and emphysema (CPFE) who were treated with ICS/LABA (Group A), 24 patients with CPFE who were treated without ICS/LABA (Group B) and 35 patients with idiopathic pulmonary fibrosis (IPF) (Group C) were enrolled into this study. Then, clinical efficacy and safety of ICS/LABA was analyzed through lung function scores and lung high-resolution computed tomography (HRCT) scans. Compared with baseline levels, the FEV1%, FVC% and DLCO% levels were increased 11.2%, 13.53% and 12.8% respectively in group A, but declined 14.21%, 16.8% and 21.25% respectively in group B, meanwhile, lung HRCT score was declined 9.31 in group A but increased 14.87 in group B, and there was significant difference between group A and group B (P0.05). The incidence of adverse reaction was higher in group A than that in group B during this study, but there was no significant difference (P>0.05). ICS/LABA therapy could improve lung function condition in patients with CPFE and declined acute out-break frequency and severity of diseases during acute episode period.

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

Science.gov (United States)

Buehler, M. G. (Inventor)

1985-01-01

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Effects of gas-flow structures on radical and etch-product density distributions on wafers in magnetomicrowave plasma etching reactors

International Nuclear Information System (INIS)

Ikegawa, Masato; Kobayashi, Jun'ichi; Fukuyama, Ryoji

2001-01-01

To achieve high etch rate, uniformity, good selectivity, and etch profile control across large diameter wafers, the distributions of ions, radicals, and etch products in magnetomicrowave high-etch-rate plasma etching reactors must be accurately controlled. In this work the effects of chamber heights, a focus ring around the wafer, and gas supply structures (or gas flow structures) on the radicals and etch products flux distribution onto the wafer were examined using the direct simulation Monte Carlo method and used to determine the optimal reactor geometry. The pressure uniformity on the wafer was less than ±1% when the chamber height was taller than 60 mm. The focus ring around the wafer produced uniform radical and etch-product fluxes but increased the etch-product flux on the wafer. A downward-flow gas-supply structure (type II) produced a more uniform radical distribution than that produced by a radial gas-supply structure (type I). The impact flow of the type II structure removed etch products from the wafer effectively and produced a uniform etch-product distribution even without the focus ring. Thus the downward-flow gas-supply structure (type II) was adopted in the design for the second-generation of a magnetomicrowave plasma etching reactor with a higher etching rate

Monitoring System for Slope Stability under Rainfall by using MEMS Acceleration Sensor IC tags

International Nuclear Information System (INIS)

Murakami, S; Dairaku, A; Komine, H; Saito, O; Sakai, N; Isizawa, T; Maruyama, I

2013-01-01

Real-time warning system for slope failure under rainfall is available to disaster prevention and mitigation. Monitoring of multi-point and wireless measurements is effective because it is difficult to conclude the most dangerous part in a slope. The purpose of this study is to propose a method of monitoring system with multi-point and wireless measurements for a slope stability using MEMS acceleration sensor IC tags. MEMS acceleration sensor IC tag is an acceleration sensor microminiaturized by a technology of Micro Electro Mechanical Systems on board IC tag. Especially, low cost of the sensor will yield to the realization of the system. In order to investigate the applicability of the proposed system, a large-scale model test of artificial slope subjected to rainfall has been performed. MEMS acceleration sensor IC tags has been located on the slope and ground acceleration caused by forced vibration has been measured until the model slope collapses. The experimental results show that the MEMS acceleration sensor IC tag is comfortably available under rainfall, the characteristics of ground accelerations varies with changing the condition of the slope subjected to rainfall, and the proposed method can be applied to a real-time monitoring system for slope failure under rainfall.

HI observations of the irregular galaxy IC 10

International Nuclear Information System (INIS)

Shostak, G.S.; Woerden, H. van

1983-01-01

The authors have made radio synthesis observations of the galaxy IC 10 with resolutions of 30 arcsec and 8 km/sec in the neutral hydrogen line using the Westerbork telescope. These confirm Shostak's (1974) result that, in the central region of IC 10, the velocity gradient is opposite to that later measured by single-dish in the outer regions. The suggestion by Cohen (1979) that the velocity gradient reversal is due to IC 10 being nearly face-on and warped is consistent with the new data. (Auth.)

Bio-medical CMOS ICs

CERN Document Server

Yoo, Hoi-Jun

2011-01-01

This book is based on a graduate course entitled, Ubiquitous Healthcare Circuits and Systems, that was given by one of the editors. It includes an introduction and overview to biomedical ICs and provides information on the current trends in research.

Scalable IC Platform for Smart Cameras

Directory of Open Access Journals (Sweden)

Harry Broers

2005-08-01

Full Text Available Smart cameras are among the emerging new fields of electronics. The points of interest are in the application areas, software and IC development. In order to reduce cost, it is worthwhile to invest in a single architecture that can be scaled for the various application areas in performance (and resulting power consumption. In this paper, we show that the combination of an SIMD (single-instruction multiple-data processor and a general-purpose DSP is very advantageous for the image processing tasks encountered in smart cameras. While the SIMD processor gives the very high performance necessary by exploiting the inherent data parallelism found in the pixel crunching part of the algorithms, the DSP offers a friendly approach to the more complex tasks. The paper continues to motivate that SIMD processors have very convenient scaling properties in silicon, making the complete, SIMD-DSP architecture suitable for different application areas without changing the software suite. Analysis of the changes in power consumption due to scaling shows that for typical image processing tasks, it is beneficial to scale the SIMD processor to use the maximum level of parallelism available in the algorithm if the IC supply voltage can be lowered. If silicon cost is of importance, the parallelism of the processor should be scaled to just reach the desired performance given the speed of the silicon.

Xe{sup +} ion beam induced rippled structures on Si miscut wafers

Energy Technology Data Exchange (ETDEWEB)

Hanisch, Antje; Grenzer, Joerg [Forschungszentrum Dresden-Rossendorf, Dresden (Germany); Biermanns, Andreas; Pietsch, Ullrich [Institute of Physics, University of Siegen (Germany)

2009-07-01

We report on the influence of the initial roughness and crystallography of the substrate on the formation of self-organized ripple structures on semiconductors surfaces by noble gas ion bombardment. The Bradley-Harper theory predicts that an initial roughness is most important for starting the sputtering process which in the ends leads to the evolution of regular patterns. We produced periodic structures with intermediate Xe{sup +} ion energies (5-70 keV) at different incidence and azimuthal angles which lead to the assumption that also crystallography plays a role at the beginning of ripple evolution. Most of the previous investigations started from the original roughness of a polished silicon wafer. We used (001) silicon wafers with a miscut angle of 1 , 5 and 10 towards[110]. We studied the ripple formation keeping the ion beam parallel to the[111],[-1-11] or[-111] direction, i.e. parallel, antiparallel or perpendicular to the miscut direction[110]. The parallel and antiparallel case implies a variation of the incidence angle with increased roughness over the surface step terraces. The perpendicular orientation means almost no roughness. The results were compared to normal Si(001) and Si(111) wafers.

The role of Gliadel wafers in the treatment of newly diagnosed GBM: a meta-analysis

Directory of Open Access Journals (Sweden)

Xing WK

2015-06-01

Full Text Available Wei-kang Xing,1 Chuan Shao,2 Zhen-yu Qi,1 Chao Yang,1 Zhong Wang1 1Department of Neurosurgery, The First Affiliated Hospital of Soochow University, Suzhou, Jiangsu, 2Department of Neurosurgery, The Second Clinical Medical College of North Sichuan Medical College, Nanchong, Sichuan, People’s Republic of China Background: Standard treatment for high-grade glioma (HGG includes surgery followed by radiotherapy and/or chemotherapy. Insertion of carmustine wafers into the resection cavity as a treatment for malignant glioma is currently a controversial topic among neurosurgeons. Our meta-analysis focused on whether carmustine wafer treatment could significantly benefit the survival of patients with newly diagnosed glioblastoma multiforme (GBM.Method: We searched the PubMed and Web of Science databases without any restrictions on language using the keywords “Gliadel wafers”, “carmustine wafers”, “BCNU wafers”, or “interstitial chemotherapy” in newly diagnosed GBM for the period from January 1990 to March 2015. Randomized controlled trials (RCTs and cohort studies/clinical trials that compared treatments designed with and without carmustine wafers and which reported overall survival or hazard ratio (HR or survival curves were included in this study. Moreover, the statistical analysis was conducted by the STATA 12.0 software.Results: Six studies including two RCTs and four cohort studies, enrolling a total of 513 patients (223 with and 290 without carmustine wafers, matched the selection criteria. Carmustine wafers showed a strong advantage when pooling all the included studies (HR =0.63, 95% confidence interval (CI =0.49–0.81; P=0.019. However, the two RCTs did not show a statistical increase in survival in the group with carmustine wafer compared to the group without it (HR =0.51, 95% CI =0.18–1.41; P=0.426, while the cohort studies demonstrated a significant survival increase (HR =0.59, 95% CI =0.44–0.79; P<0.0001.Conclusion

Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

Directory of Open Access Journals (Sweden)

Prithviraj Chakraborty

2013-01-01

Full Text Available Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR. Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A, and lactose monohydrate as ingredient, of hydrophilic matrix former (B on the bioadhesive force, disintegration time, percent (% swelling index, and time taken for 70% drug release (t70%. The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design.

Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

Science.gov (United States)

Dey, Surajit; Parcha, Versha; Bhattacharya, Shiv Sankar; Ghosh, Amitava

2013-01-01

Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR). Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A), and lactose monohydrate as ingredient, of hydrophilic matrix former (B) on the bioadhesive force, disintegration time, percent (%) swelling index, and time taken for 70% drug release (t 70%). The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD) analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design. PMID:23781498

EM Simulation Accuracy Enhancement for Broadband Modeling of On-Wafer Passive Components

DEFF Research Database (Denmark)

Johansen, Tom Keinicke; Jiang, Chenhui; Hadziabdic, Dzenan

2007-01-01

This paper describes methods for accuracy enhancement in broadband modeling of on-wafer passive components using electromagnetic (EM) simulation. It is shown that standard excitation schemes for integrated component simulation leads to poor correlation with on-wafer measurements beyond the lower...... GHz frequency range. We show that this is due to parasitic effects and higher-order modes caused by the excitation schemes. We propose a simple equivalent circuit for the parasitic effects in the well-known ground ring excitation scheme. An extended L-2L calibration method is shown to improve...

Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 µm CMOS MEMS process

International Nuclear Information System (INIS)

Tseng, Sheng-Hsiang; Lu, Michael S-C; Wu, Po-Chang; Teng, Yu-Chen; Tsai, Hann-Huei; Juang, Ying-Zong

2012-01-01

This paper describes the design, fabrication and characterization of a complementary metal-oxide-semiconductor (CMOS) micro-electro-mechanical-system (MEMS) accelerometer implemented in a 0.18 µm multi-project wafer (MPW) CMOS MEMS process. In addition to the standard CMOS process, an additional aluminum layer and a thick photoresist masking layer are employed to achieve etching and microstructural release. The structural thickness of the accelerometer is up to 9 µm and the minimum structural spacing is 2.3 µm. The out-of-plane deflection resulted from the vertical stress gradient over the whole device is controlled to be under 0.2 µm. The chip area containing the micromechanical structure and switched-capacitor sensing circuit is 1.18 × 0.9 mm 2 , and the total power consumption is only 0.7 mW. Within the sensing range of ±6 G, the measured nonlinearity is 1.07% and the cross-axis sensitivities with respect to the in-plane and out-of-plane are 0.5% and 5.8%, respectively. The average sensitivity of five tested accelerometers is 191.4 mV G −1 with a standard deviation of 2.5 mV G −1 . The measured output noise floor is 354 µG Hz −1/2 , corresponding to a 100 Hz 1 G sinusoidal acceleration. The measured output offset voltage is about 100 mV at 27 °C, and the zero-G temperature coefficient of the accelerometer output is 0.94 mV °C −1 below 85 °C. (paper)

Hydrogel-forming microneedles prepared from "super swelling" polymers combined with lyophilised wafers for transdermal drug delivery.

Directory of Open Access Journals (Sweden)

Ryan F Donnelly

Full Text Available We describe, for the first time, hydrogel-forming microneedle arrays prepared from "super swelling" polymeric compositions. We produced a microneedle formulation with enhanced swelling capabilities from aqueous blends containing 20% w/w Gantrez S-97, 7.5% w/w PEG 10,000 and 3% w/w Na2CO3 and utilised a drug reservoir of a lyophilised wafer-like design. These microneedle-lyophilised wafer compositions were robust and effectively penetrated skin, swelling extensively, but being removed intact. In in vitro delivery experiments across excised neonatal porcine skin, approximately 44 mg of the model high dose small molecule drug ibuprofen sodium was delivered in 24 h, equating to 37% of the loading in the lyophilised reservoir. The super swelling microneedles delivered approximately 1.24 mg of the model protein ovalbumin over 24 h, equivalent to a delivery efficiency of approximately 49%. The integrated microneedle-lyophilised wafer delivery system produced a progressive increase in plasma concentrations of ibuprofen sodium in rats over 6 h, with a maximal concentration of approximately 179 µg/ml achieved in this time. The plasma concentration had fallen to 71±6.7 µg/ml by 24 h. Ovalbumin levels peaked in rat plasma after only 1 hour at 42.36±17.01 ng/ml. Ovalbumin plasma levels then remained almost constant up to 6 h, dropping somewhat at 24 h, when 23.61±4.84 ng/ml was detected. This work represents a significant advancement on conventional microneedle systems, which are presently only suitable for bolus delivery of very potent drugs and vaccines. Once fully developed, such technology may greatly expand the range of drugs that can be delivered transdermally, to the benefit of patients and industry. Accordingly, we are currently progressing towards clinical evaluations with a range of candidate molecules.

Nanometer CMOS ICs from basics to ASICs

CERN Document Server

J M Veendrick, Harry

2017-01-01

This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

Enhanced urothelial expression of human chorionic gonadotropin beta (hCGβ) in bladder pain syndrome/interstitial cystitis (BPS/IC).

Science.gov (United States)

Schwalenberg, Thilo; Stolzenburg, Jens-Uwe; Ho, Thi Phuc; Mallock, Tobias; Hartenstein, Siegurd; Alexander, Henry; Zimmermann, Gerolf; Hohenfellner, Rudolf; Denzinger, Stefan; Burger, Maximilian; Horn, Lars-Christian; Neuhaus, Jochen

2012-06-01

Bladder pain syndrome/interstitial cystitis (BPS/IC) is associated with urothelial lesions. Pathomechanisms of urothelial damage and factors for urothelial restoration are unknown. hCG is a factor for cellular differentiation, angiogenesis and immune competence of the endometrium during pregnancy. Clinical observations demonstrate improvement of BPS/IC symptoms during pregnancy or during infertility treatment with hCG. Our research aims were to examine the expression of hCG and luteinizing hormone receptor (LHR) in the urothelium of BPS/IC patients and compare the levels of hCGβ with healthy controls. Bladder biopsies of BPS/IC (CLSM: n = 10; qPCR: n = 15); Tumour-free control tissue from cystectomies (n = 12). hCGα, hCGβ and LHR expression were examined by confocal laser scanning microscopy (CLSM), and hCGβ expression was quantified. hCGβ5 and hCGβ7 mRNA splice variants were quantified in real-time polymerase chain reaction. We found constitutive expression of hCGα, hCGβ and LHR in healthy controls. HCGβ was significantly upregulated in BPS/IC patients in CLSM. PCR analysis revealed higher levels of hCGβ7 than hCGβ5 in controls and BPS/IC patients. The constitutive expression of hCG and LHR speaks in favour for a functional signalling in urothelial cells without any association with either pregnancy or tumour. We show for the first time that hCGβ is upregulated in BPS/IC urothelium and that hCGβ7 is the dominant splice variant in those cells. Our findings imply a major role of hCG for urothelial integrity and a disturbance of hCG signalling in case of BPS/IC. We conclude that hCG could gain therapeutical relevance in the future.

Optimization of corn, rice and buckwheat formulations for gluten-free wafer production.

Science.gov (United States)

Dogan, Ismail Sait; Yildiz, Onder; Meral, Raciye

2016-07-01

Gluten-free baked products for celiac sufferers are essential for healthy living. Cereals having gluten such as wheat and rye must be removed from the diet for the clinical and histological improvement. The variety of gluten-free foods should be offered for the sufferers. In the study, gluten-free wafer formulas were optimized using corn, rice and buckwheat flours, xanthan and guar gum blend as an alternative product for celiac sufferers. Wafer sheet attributes and textural properties were investigated. Considering all wafer sheet properties in gluten-free formulas, better results were obtained by using 163.5% water, 0.5% guar and 0.1% xanthan in corn formula; 173.3% water, 0.45% guar and 0.15% xanthan gum in rice formula; 176% water, 0.1% guar and 0.5% xanthan gum in buckwheat formula. Average desirability values in gluten-free formulas were between 0.86 and 0.91 indicating they had similar visual and textural profiles to control sheet made with wheat flour. © The Author(s) 2015.

RD53A Integrated Circuit Specifications

OpenAIRE

Garcia-Sciveres, Mauricio

2015-01-01

Specifications for the RD53 collaboration’s first engineering wafer run of an integrated circuit (IC) for hybrid pixel detector readout, called RD53A. RD53A is intended to demonstrate in a large format IC the suitability of the technology (including radiation tolerance), the stable low threshold operation, and the high hit and trigger rate capabilities, required for HL-LHC upgrades of ATLAS and CMS. The wafer scale production will permit the experiments to prototype bump bonding assembly with...

El contenido de los mensajes icónicos: El discurso icónico como totalidad (2)

OpenAIRE

Dr. Raymond Colle

1999-01-01

En el capítulo anterior, hemos hablado de los códigos icónicos de modo general, por cuanto tienen algunas características comunes, en particular el uso de figuras como factores de los significantes. Sin embargo, como lo hemos señalado al final, no todos se construyen ni articulan de la misma manera. Tal como las lenguas son muchas y los códigos lingüísticos se rigen por diferentes reglas -aunque sobre la base de fonemas unidos secuencialmente-, los códigos icónicos son también variados y regi...

Improving scanner wafer alignment performance by target optimization

Science.gov (United States)

Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

2016-03-01

In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

The Evolution of Wafer Bonding Moving from the back-end further to the front-end

Institute of Scientific and Technical Information of China (English)

Thomas Glinsner; Peter Hangweier

2009-01-01

@@ 1 Introduction As the nanoscale era progresses, innovative new materials and processes continue to be developed and implemented as a means of keeping the industry on the path of Moore's Law. Wafer bonding - literally, the temporary or permanent joining of two wafers or substrates using a suitable combination of process technologies, chemicals and adhesives - is one such innovation.

Migration to Current Open Source Technologies by MagIC Enables a More Responsive Website, Quicker Development Times, and Increased Community Engagement

Science.gov (United States)

Jarboe, N.; Minnett, R.; Koppers, A.; Constable, C.; Tauxe, L.; Jonestrask, L.

2017-12-01

The Magnetics Information Consortium (MagIC) supports an online database for the paleo, geo, and rock magnetic communities ( https://earthref.org/MagIC ). Researchers can upload data into the archive and download data as selected with a sophisticated search system. MagIC has completed the transition from an Oracle backed, Perl based, server oriented website to an ElasticSearch backed, Meteor based thick client website technology stack. Using JavaScript on both the sever and the client enables increased code reuse and allows easy offloading many computational operations to the client for faster response. On-the-fly data validation, column header suggestion, and spreadsheet online editing are some new features available with the new system. The 3.0 data model, method codes, and vocabulary lists can be browsed via the MagIC website and more easily updated. Source code for MagIC is publicly available on GitHub ( https://github.com/earthref/MagIC ). The MagIC file format is natively compatible with the PmagPy ( https://github.com/PmagPy/PmagPy) paleomagnetic analysis software. MagIC files can now be downloaded from the database and viewed and interpreted in the PmagPy GUI based tool, pmag_gui. Changes or interpretations of the data can then be saved by pmag_gui in the MagIC 3.0 data format and easily uploaded to the MagIC database. The rate of new contributions to the database has been increasing with many labs contributing measurement level data for the first time in the last year. Over a dozen file format conversion scripts are available for translating non-MagIC measurement data files into the MagIC format for easy uploading. We will continue to work with more labs until the whole community has a manageable workflow for contributing their measurement level data. MagIC will continue to provide a global repository for archiving and retrieving paleomagnetic and rock magnetic data and, with the new system in place, be able to more quickly respond to the community

Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

Science.gov (United States)

Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

Improvements to the solar cell efficiency and production yields of low-lifetime wafers with effective phosphorus gettering

International Nuclear Information System (INIS)

Lu, Jiunn-Chenn; Chen, Ping-Nan; Chen, Chih-Min; Wu, Chung-Han

2013-01-01

Highlights: • Variable-temperature gettering improves efficiencies when the wafer quality is poor. • High-quality wafers need not be used for variable-temperature gettering. • The proposed gettering method is based on an existing diffusion process. • It has a potential interest for hot-spot prevention. -- Abstract: This research focuses on the improvement of solar cell efficiencies in low-lifetime wafers by implementing an appropriate gettering method of the diffusion process. The study also considers a reduction in the value of the reverse current at −12 V, an important electrical parameter related to the hot-spot heating of solar cells and modules, to improve the product's quality during commercial mass production. A practical solar cell production case study is examined to illustrate the use of the proposed method. The results of this case study indicate that variable-temperature gettering significantly improves solar cell efficiencies by 0.14% compared to constant-temperature methods when the wafer quality is poor. Moreover, this study finds that variable-temperature gettering raises production yields of low quality wafers by more than 30% by restraining the measurement value of the reverse current at −12 V during solar cell manufacturing

Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

Institute of Scientific and Technical Information of China (English)

潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

2011-01-01

Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95％ active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

Bonding of Si wafers by surface activation method for the development of high efficiency high counting rate radiation detectors

International Nuclear Information System (INIS)

Kanno, Ikuo; Yamashita, Makoto; Onabe, Hideaki

2006-01-01

Si wafers with two different resistivities ranging over two orders of magnitude were bonded by the surface activation method. The resistivities of bonded Si wafers were measured as a function of annealing temperature. Using calculations based on a model, the interface resistivities of bonded Si wafers were estimated as a function of the measured resistivities of bonded Si wafers. With thermal treatment from 500degC to 900degC, all interfaces showed high resistivity, with behavior that was close to that of an insulator. Annealing at 1000degC decreased the interface resistivity and showed close to ideal bonding after thermal treatment at 1100degC. (author)

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

International Nuclear Information System (INIS)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-01-01

To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

Science.gov (United States)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

Synchrotron Radiation Total Reflection X-ray Fluorescence Spectroscopy for Microcontamination Analysis on Silicon Wafer Surfaces

Energy Technology Data Exchange (ETDEWEB)

Takaura, Norikatsu

1997-10-01

As dimensions in state-of-the-art CMOS devices shrink to less than 0.1 pm, even low levels of impurities on wafer surfaces can cause device degradation. Conventionally, metal contamination on wafer surfaces is measured using Total Reflection X-Ray Fluorescence Spectroscopy (TXRF). However, commercially available TXRF systems do not have the necessary sensitivity for measuring the lower levels of contamination required to develop new CMOS technologies. In an attempt to improve the sensitivity of TXRF, this research investigates Synchrotron Radiation TXRF (SR TXRF). The advantages of SR TXRF over conventional TXRF are higher incident photon flux, energy tunability, and linear polarization. We made use of these advantages to develop an optimized SR TXRF system at the Stanford Synchrotron Radiation Laboratory (SSRL). The results of measurements show that the Minimum Detection Limits (MDLs) of SR TXRF for 3-d transition metals are typically at a level-of 3x10{sup 8} atoms/cm{sup 2}, which is better than conventional TXRF by about a factor of 20. However, to use our SR TXRF system for practical applications, it was necessary to modify a commercially available Si (Li) detector which generates parasitic fluorescence signals. With the modified detector, we could achieve true MDLs of 3x10{sup 8} atoms/cm{sup 2} for 3-d transition metals. In addition, the analysis of Al on Si wafers is described. Al analysis is difficult because strong Si signals overlap the Al signals. In this work, the Si signals are greatly reduced by tuning the incident beam energy below the Si K edge. The results of our measurements show that the sensitivity for Al is limited by x-ray Raman scattering. Furthermore, we show the results of theoretical modeling of SR TXRF backgrounds consisting of the bremsstrahlung generated by photoelectrons, Compton scattering, and Raman scattering. To model these backgrounds, we extended conventional theoretical models by taking into account several aspects particular

A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

International Nuclear Information System (INIS)

Gao Baohong; Liu Yuling; Wang Chenwei; Wang Shengli; Zhou Qiang; Tan Baimei; Zhu Yadong

2010-01-01

This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO 4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection. (semiconductor technology)

Sacrificial wafer bonding for planarization after very deep etching

NARCIS (Netherlands)

Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

Prediction of UV spectra and UV-radiation damage in actual plasma etching processes using on-wafer monitoring technique

International Nuclear Information System (INIS)

Jinnai, Butsurin; Fukuda, Seiichi; Ohtake, Hiroto; Samukawa, Seiji

2010-01-01

UV radiation during plasma processing affects the surface of materials. Nevertheless, the interaction of UV photons with surface is not clearly understood because of the difficulty in monitoring photons during plasma processing. For this purpose, we have previously proposed an on-wafer monitoring technique for UV photons. For this study, using the combination of this on-wafer monitoring technique and a neural network, we established a relationship between the data obtained from the on-wafer monitoring technique and UV spectra. Also, we obtained absolute intensities of UV radiation by calibrating arbitrary units of UV intensity with a 126 nm excimer lamp. As a result, UV spectra and their absolute intensities could be predicted with the on-wafer monitoring. Furthermore, we developed a prediction system with the on-wafer monitoring technique to simulate UV-radiation damage in dielectric films during plasma etching. UV-induced damage in SiOC films was predicted in this study. Our prediction results of damage in SiOC films shows that UV spectra and their absolute intensities are the key cause of damage in SiOC films. In addition, UV-radiation damage in SiOC films strongly depends on the geometry of the etching structure. The on-wafer monitoring technique should be useful in understanding the interaction of UV radiation with surface and in optimizing plasma processing by controlling UV radiation.

An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

Science.gov (United States)

DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

2016-01-01

This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

Relationships between Charpy impact shelf energies and upper shelf Ksub(IC) values for reactor pressure vessel steels

International Nuclear Information System (INIS)

Witt, F.J.

1983-01-01

Charpy shelf data and lower bound estimates of Ksub(IC) shelf data for the same steels and test temperatures are given. Included are some typical reactor pressure vessel steels as well as some less tough or degraded steels. The data were evaluated with shelf estimates of Ksub(IC) up to and exceeding 550 MPa√m. It is shown that the high shelf fracture toughness representative of tough reactor pressure vessel steels may be obtained from a knowledge of the Charpy shelf energies. The toughness transition may be obtained either by testing small fracture toughness specimens or by Charpy energy indexing. (U.K.)

Advanced qualification techniques

International Nuclear Information System (INIS)

Winokur, P.S.; Shaneyfelt, M.R.; Meisenheimer, T.L.; Fleetwood, D.M.

1993-01-01

This paper demonstrates use of the Qualified Manufacturers List (QML) methodology to qualify commercial and military microelectronics for use in space applications. QML ''builds in'' the hardness of product through statistical process control (SPC) of technology parameters relevant to the radiation response, test structure to integrated circuit (IC) correlations, and techniques for extrapolating laboratory test results to low-dose-rate space scenarios. Each of these elements is demonstrated and shown to be a cost-effective alternative to expensive end-of-line IC testing. Several examples of test structured-IC correlations are provided and recent work on complications arising from transistor scaling and geometry is discussed. The use of a 10-keV x-ray wafer-level test system to support SPC and establish ''process capability'' is illustrated and a comparison of 10-keV x-ray and Co 60 gamma irradiations is provided for a wide range of CMOS technologies. The x-ray tester is shown to be cost-effective and its use in lot acceptance/qualification is recommended. Finally, a comparison is provided between MIL-STD-883D, Test Method 1019.4, which governs the testing of packaged semiconductor microcircuits in the DoD, and ESA/SSC Basic Specification No. 22900, Europe's Total Dose Steady-State Irradiation Test Method. Test Method 1019.4 focuses on conservative estimates of MOS hardness for space and tactical applications, while Basic Specification 22900 focuses on improved simulation of low-dose-rate space environments

Definition of intercultural competence (IC) in undergraduate students at a private university in the USA: A mixed-methods study.

Science.gov (United States)

Gierke, Lioba; Binder, Nadine; Heckmann, Mark; Odağ, Özen; Leiser, Anne; Kedzior, Karina Karolina

2018-01-01

Intercultural competence (IC) is an important skill to be gained from higher education. However, it remains unclear what IC means to students and what factors might influence their definitions of IC. The aim of the current study was to qualitatively assess how students at one higher education institution in the USA define IC and to quantitatively test for relationships among IC components and various demographic characteristics, including intercultural experience and study context. A further aim was to descriptively compare the IC definitions from the US sample with the definitions obtained from another sample of university students in Germany. A purposive sample of n = 93 undergraduate, second semester students at Dickinson College, USA, participated in the study by completing an online questionnaire. The qualitative data were content-analyzed to define the dimensions of IC. The quantitative data were cluster-analyzed to assess the multivariate relationships among the IC components and the demographic characteristics of the sample. The most important dimensions of IC were Knowledge, External Outcomes (interaction, communication), and Attitudes (respect, tolerance) according to the US sample. The most frequently chosen dimensions of IC differed between both samples: Knowledge was chosen by the sample in the USA while External Outcomes was chosen by the sample in Germany. Relative to the US sample, significantly more students chose Attitudes, External Outcomes, and Intrapersonal Skills in the sample in Germany. The relationships among IC components and demographic characteristics were only weak in the US sample. A person with IC was rated as Open-minded and Respectful by students who lived predominantly in the USA or Tolerant and Curious by those who lived outside the USA for at least six months. The current results suggest that students residing in two countries (USA or Germany) define IC using similar dimensions. However, IC definitions may depend on the

Profiles of the N II 6584 A line over the giant H II regions IC 1318b and c, NGC 7000 and IC 5070. 2

Energy Technology Data Exchange (ETDEWEB)

Canto, J; Johnson, P G; Meaburn, J; Mikhail, J S; Terrett, D L; White, N J [Manchester Univ. (UK). Dept of Astronomy

1979-06-01

Previously (Paper I) large-scale splitting of the (N II) line was discovered over an area of IC 1318b. The motions of the ionized material have now been mapped over a much larger region of this nebula and also IC 1318c. The splitting reaches a maximum value of 53 km/s over the faintest regions of IC 1318b and occurs over an area approximately > 20 pc across. However, few split (N II) lines were found over IC 1318c, but the motions of this whole ionized and neutral complex have been shown to be closely related. Wind-driven flows along neutral and ionized shells are proposed to explain the observations. Similar measurements have also been made on either side of the dark lane separating NGC 7000 from IC 5070.

The MusIC method: a fast and quasi-optimal solution to the muscle forces estimation problem

OpenAIRE

Muller , Antoine; Pontonnier , Charles; Dumont , Georges

2018-01-01

International audience; The present paper aims at presenting a fast and quasi-optimal method of muscle forces estimation: the MusIC method. It consists in interpolating a first estimation in a database generated offline thanks to a classical optimization problem, and then correcting it to respect the motion dynamics. Three different cost functions – two polynomial criteria and a min/max criterion – were tested on a planar musculoskeletal model. The MusIC method provides a computation frequenc...

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

Science.gov (United States)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

International Nuclear Information System (INIS)

Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

2017-01-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

Effect of diffraction and film-thickness gradients on wafer-curvature measurements of thin-film stress

International Nuclear Information System (INIS)

Breiland, W.G.; Lee, S.R.; Koleske, D.D.

2004-01-01

When optical measurements of wafer curvature are used to determine thin-film stress, the laser beams that probe the sample are usually assumed to reflect specularly from the curved surface of the film and substrate. Yet, real films are not uniformly thick, and unintended thickness gradients produce optical diffraction effects that steer the laser away from the ideal specular condition. As a result, the deflection of the laser in wafer-curvature measurements is actually sensitive to both the film stress and the film-thickness gradient. We present a Fresnel-Kirchhoff optical diffraction model of wafer-curvature measurements that provides a unified description of these combined effects. The model accurately simulates real-time wafer-curvature measurements of nonuniform GaN films grown on sapphire substrates by vapor-phase epitaxy. During thin-film growth, thickness gradients cause the reflected beam to oscillate asymmetrically about the ideal position defined by the stress-induced wafer curvature. This oscillating deflection has the same periodicity as the reflectance of the growing film, and the deflection amplitude is a function of the film-thickness gradient, the mean film thickness, the wavelength distribution of the light source, the illuminated spot size, and the refractive indices of the film and substrate. For typical GaN films grown on sapphire, misinterpretation of these gradient-induced oscillations can cause stress-measurement errors that approach 10% of the stress-thickness product; much greater errors occur in highly nonuniform films. Only transparent films can exhibit substantial gradient-induced deflections; strongly absorbing films are immune

Detection of trace contamination of copper on a silicon wafer with TXRF

International Nuclear Information System (INIS)

Yamada, T.; Matsuo, M.; Kohno, H.; Mori, Y.

2000-01-01

The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. When W-Lβ 1 (9.67 keV) line is used for the excitation in TXRF instrument and when Si(Li) is used as its detector, an escape peak appears at 7.93 keV which is close to the energy of Cu-Kα line(8.04 keV). When the concentration of copper is lower than 10 10 atoms/cm 2 , accurate quantitative analysis is difficult because of the overlapping of the peaks. When Au-Lβ 1 line(11.44 keV) is used for the excitation, the escape peak appears at 9.70 keV which is far enough from the energy of Cu-Ka line. We prepared silicon wafers intentionally contaminated with copper in a low concentration range of 10 8 to 10 10 atoms/cm 2 and measured them with a TXRF instrument having Au-Lβ 1 line for excitation. The contaminated samples were made with IAP method and their Cu concentrations were calibrated with VPD-AAS method (recovery solution: 2 % HF + 2 % H 2 O 2 ). A figure shows the correlation between the results with TXRF and those with AAS. The horizontal axis is the value of concentration decided by AAS and the vertical axis is the intensity of Cu-Kα line measured with the TXRF. Six wafers of different concentration were used and five points on each wafer including the center were measured with TXRF. Five points at each concentration in the figure correspond to the results measured on one wafer. Intensities of Cu-Kα line are weak in these low concentration ranges but the background of them are also very small (less than 0.05 cps). Therefore the peak of Cu-Kα line can be distinguished from the background. It can be said that a calibration curve can be drawn to the middle range of 10 9 atoms/cm 2 . The same samples were measured with another TXRF instrument having W-Lβ 1 line for excitation. It was difficult to draw a calibration curve in this case. We will present both results taken with Au-Lβ 1 line and with W-Lβ 1 line. (author)

Interband cascade (IC) photovoltaic (PV) architecture for PV devices

Science.gov (United States)

Yang, Rui Q.; Tian, Zhaobing; Mishima, Tetsuya D.; Santos, Michael B.; Johnson, Matthew B.; Klem, John F.

2015-10-20

A photovoltaic (PV) device, comprising a PV interband cascade (IC) stage, wherein the IC PV stage comprises an absorption region with a band gap, the absorption region configured to absorb photons, an intraband transport region configured to act as a hole barrier, and an interband tunneling region configured to act as an electron barrier. An IC PV architecture for a photovoltaic device, the IC PV architecture comprising an absorption region, an intraband transport region coupled to the absorption region, and an interband tunneling region coupled to the intraband transport region and to the adjacent absorption region, wherein the absorption region, the intraband transport region, and the interband tunneling region are positioned such that electrons will flow from the absorption region to the intraband transport region to the interband tunneling region.

Reducing the substrate dependent scanner leveling effect in low-k1 contact printing

Science.gov (United States)

Chang, C. S.; Tseng, C. F.; Huang, C. H.; Yang, Elvis; Yang, T. H.; Chen, K. C.

2015-03-01

As the scaling down of design rule for high-density memory device, the small depth of focus (DoF) budget may be deteriorated by focus leveling errors, which arises in unpredicted reflectivity from multilayer structures on the topographic wafer. The leveling sensors of ASML scanner use near infrared (NIR) range wavelength which can penetrate through most of films using in semiconductor fabrication such as photo-resist, bottom anti reflective coating (BARC) and dielectric materials. Consequently, the reflected light from underlying substructures would disturb leveling sensors from accurate leveling. The different pattern densities and layout characteristics between array and periphery of a memory chip are expected to result in different leveling signals. Furthermore, the process dependent variations between wafer central and edge areas are also considered to yield different leveling performances during wafer exposure. In this study, lower blind contact immunity was observed for peripheral contacts comparing to the array contacts especially around wafer edge region. In order to overcome this problem, a series of investigations have been carried out. The wafer edge leveling optimization through circuit dependent focus edge clearance (CDFEC) option doesn't get improvement. Air gauge improved process leveling (AGILE) function of ASML immersion scanner doesn't show improved result either. The ILD uniformity improvement and step height treatments around wafer edge such as edge exclusion of film deposition and bevel etching are also ineffective to mitigate the blind contact problem of peripheral patterns. Altering the etch hard-mask stack is finally found to be an effective approach to alleviate the issue. For instance, through either containing high temperature deposition advanced patterning film (APF) in the hard-mask or inserting higher opaque film such as amorphous Si in between the hard-mask stack.

Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

International Nuclear Information System (INIS)

Casse, G.; Glaser, M.; Lemeilleur, F.; Ruzin, A.; Wegrzecki, M.

1999-01-01

The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10 17 atoms cm -3 ) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO 2 layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 μm thick silicon wafer

Credibility test; Vertrauens-Test

Energy Technology Data Exchange (ETDEWEB)

Fuhs, Michael

2009-07-01

Solar wafer producers must prove their quality standards. Q-Cells has started a marketing office and opened their test center to journalists. They are aware that adherence to standards is going only half the way of quality assurance. The other half consists in gaining the customers' trust. (orig.)

High quality single atomic layer deposition of hexagonal boron nitride on single crystalline Rh(111) four-inch wafers

Energy Technology Data Exchange (ETDEWEB)

Hemmi, A.; Bernard, C.; Cun, H.; Roth, S.; Klöckner, M.; Kälin, T.; Osterwalder, J.; Greber, T., E-mail: greber@physik.uzh.ch [Physik-Institut, Universität Zürich, CH-8057 Zürich (Switzerland); Weinl, M.; Gsell, S.; Schreck, M. [Institut für Physik, Universität Augsburg, D-86135 Augsburg (Germany)

2014-03-15

The setup of an apparatus for chemical vapor deposition (CVD) of hexagonal boron nitride (h-BN) and its characterization on four-inch wafers in ultra high vacuum (UHV) environment is reported. It provides well-controlled preparation conditions, such as oxygen and argon plasma assisted cleaning and high temperature annealing. In situ characterization of a wafer is accomplished with target current spectroscopy. A piezo motor driven x-y stage allows measurements with a step size of 1 nm on the complete wafer. To benchmark the system performance, we investigated the growth of single layer h-BN on epitaxial Rh(111) thin films. A thorough analysis of the wafer was performed after cutting in atmosphere by low energy electron diffraction, scanning tunneling microscopy, and ultraviolet and X-ray photoelectron spectroscopies. The apparatus is located in a clean room environment and delivers high quality single layers of h-BN and thus grants access to large area UHV processed surfaces, which had been hitherto restricted to expensive, small area single crystal substrates. The facility is versatile enough for customization to other UHV-CVD processes, e.g., graphene on four-inch wafers.

Considerations in applying on-line IC techniques to BWR's

International Nuclear Information System (INIS)

Kaleda, R.J.

1992-01-01

Ion-Chromatography (IC) has moved from its traditional role as a laboratory analytical tool to a real time, dynamic, on-line measurement device to follow ppb and sub-ppb concentrations of deleterious impurities in nuclear power plants. Electric Power Research Institute (EPRI), individual utilities, and industry all have played significant roles in effecting the transition. This paper highlights considerations and the evolution in current on-line Ion Chromatography systems. The first applications of on-line techniques were demonstrated by General Electric (GE) under EPRI sponsorship at Rancho Seco (1980), Calvert Cliffs, and McGuire nuclear units. The primary use was for diagnostic purposes. Today the on-line IC applications have been expanded to include process control and routine plant monitoring. Current on-line IC's are innovative in design, promote operational simplicity, are modular for simplified maintenance and repair, and use field-proven components which enhance reliability. Conductivity detection with electronic or chemical suppression and spectrometric detection techniques are intermixed in applications. Remote multi-point sample systems have addressed memory effects. Early applications measured ionic species in the part per billion range. Today reliable part per trillion measurements are common for on-line systems. Current systems are meeting the challenge of EPRI guideline requirements. Today's on-line IC's, with programmed sampling systems, monitor fluid streams throughout a power plant, supplying data that can be trended, stored and retrieved easily. The on-line IC has come of age. Many technical challenges were overcome to achieve today's IC

In situ beam angle measurement in a multi-wafer high current ion implanter

International Nuclear Information System (INIS)

Freer, B.S.; Reece, R.N.; Graf, M.A.; Parrill, T.; Polner, D.

2005-01-01

Direct, in situ measurement of the average angle and angular content of an ion beam in a multi-wafer ion implanter is reported for the first time. A new type of structure and method are described. The structures are located on the spinning disk, allowing precise angular alignment to the wafers. Current that passes through the structures is known to be within a range of angles and is detected behind the disk. By varying the angle of the disk around two axes, beam current versus angle is mapped and the average angle and angular spread are calculated. The average angle measured in this way is found to be consistent with that obtained by other techniques, including beam centroid offset and wafer channeling methods. Average angle of low energy beams, for which it is difficult to use other direct methods, is explored. A 'pencil beam' system is shown to give average angle repeatability of 0.13 deg. (1σ) or less, for two low energy beams under normal tuning variations, even though no effort was made to control the angle

Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

Energy Technology Data Exchange (ETDEWEB)

Trushin, Maxim

2011-07-15

The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

The effect of EC-IC bypass surgery on resting cerebral blood flow and cerebrovascular reserve capacity studied with stable Xe-CT and acetazolamide test

Energy Technology Data Exchange (ETDEWEB)

Yamashita, T.; Kashiwagi, S.; Nakano, S.; Takasago, T.; Abiko, S.; Shiroyama, Y.; Hayashi, M.; Ito, H. (Yamaguchi Univ. School of Medicine (Japan). Dept. of Neurosurgery)

1991-06-01

Cerebral blood flow (CBF) and cerebrovascular reserve capacity (CRC) were measured by stable xenon computerized tomography (Xe-CT) and acetazolamide test in 15 patients with cerebrovascular disease before and after extracranial-intracranial (EC-IC) bypass surgery for minor stroke, reversible ischemic neurological deficit or transient ischemic attack. All had angiographically shown occlusive lesions of the major arterial trunk. In the present series, global analysis showed that the bypass did not increase the resting rCBF, but did increase the rCRC. We divided the patients into four groups according to the preoperative resting rCBF and rCRC. All 3 patients with normal resting rCBF and reduced rCRC showed postoperative improvement of rCRC. Of 6 patients with reduced CBF and reduced CRC, three had postoperative increase in resting CBF and four had increased CRC. One of two patients with reduced CBF and normal CRC showed only an increase in CRC. We propose that reduced CRC or reduced CBF with reduced CRC are criteria for selection of candidates for bypass surgery. We conclude that Xe-CT with the Diamox test is a useful and simple method for evaluating cerebral hemodynamics. Preoperative grouping with a combination of preoperative resting rCBF and preoperative rCRC is useful for predicting the effect of EC-IC bypass surgery. (orig.).

Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

Science.gov (United States)

Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL

2011-07-12

An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

Simplified nonplanar wafer bonding for heterogeneous device integration

Science.gov (United States)

Geske, Jon; Bowers, John E.; Riley, Anton

2004-07-01

We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

Application of a layout/material handling design method to a furnace area in a 300 mm wafer fab

NARCIS (Netherlands)

Hesen, P.M.C.; Renders, P.J.J.; Rooda, J.E.

2001-01-01

For many years, material handling within the semiconductor industry has become increasingly important. With the introduction of 300 mm wafer production, ergonomics and product safety become more critical. Therefore, the manufacturers of semiconductor wafer fabs are considering the automation of

Adopting De Novo Programming Approach on IC Design Service Firms Resources Integration

Directory of Open Access Journals (Sweden)

James K. C. Chen

2014-01-01

Full Text Available The semiconductor industry has very important position in computer industry, ICT field, and new electronic technology developing. The IC design service is one of key factor of semiconductor industry development. There are more than 365 IC design service firms have been established around Hsinchu Science Park in Taiwan. Building an efficient planning model for IC design service firm resources integrating is very interest issue. This study aims to construct a planning model for IC design service firm implementation resources integration. This study uses the De Novo programming as an approach of criteria alternative to achieve optimal resource allocation on IC design firm. Results show the IC design service firm should conduct open innovation concept and utilizes design outsourcing obtains cost down and enhance IC design service business performance. This plan model of De Novo programming is not only for IC design service firm and also can apply to the other industrial implementation strategic alliance/integrating resource. This plan model is a universal model for the others industries field.

Proficiency Testing in Nondestructive Testing (NDT)

International Nuclear Information System (INIS)

Amry Amin Abbas; Suhairy Sani; Mohamad Pauzi Ismail; Abd Nassir Ibrahim

2014-01-01

Department of Standard Malaysia (DSM) launched myPTP programme on 31 December 2013 in accordance to ISO/IC 17043. The standard states the requirements for Proficiency Testing. The provider of these services is called Proficiency Testing Provider (PTP). The role of PTP is to compare the proficiency level between inspection bodies or laboratories. With the assistance of expert panel, the PTP will determine the assigned value as reference to be compared to the values obtained from the inspection bodies or laboratories. Quality wise, this services is important as participation will improve wuality of the inspection quality continuously and increase confidence level of client and improve safety level. Requirement of PT in NDT is mentioned in SC1.5- Specific Criteria for Accreditation of Mechanical Testing and Non-Destructive Testing (NDT) for MS ISO/IEC17025 and MTR2- MIBAS Technical Requirements for Accreditation of NDT. This paper explains and discusses the result of this proficiency test done on a number of NDT companies that participated. (author)

Improved delivery of the anticancer agent citral using BSA nanoparticles and polymeric wafers

Directory of Open Access Journals (Sweden)

White B

2017-12-01

Full Text Available Benjamin White,1 Anna Evison,1 Eszter Dombi,1 Helen E Townley1,2 1Nuffield Department of Obstetrics and Gynaecology, Women’s Centre, John Radcliffe Hospital, 2Department of Engineering Science, Oxford University, Oxford, UK Abstract: Rhabdomyosarcoma (RMS is the most common soft tissue sarcoma in children, with a 5-year survival rate of between 30 and 65%. Standard treatment involves surgery, radiation treatment, and chemotherapy. However, there is a high recurrence rate, particularly from locoregional spread. We investigated the use of the natural compound citral (3,7-dimethyl-2,6-octadienal, which can be found in a number of plants, but is particularly abundant in lemon grass (Cymbopogon citratus oil, for activity against immortalized RMS cells. Significant cancer cell death was seen at concentrations above 150 μM citral, and mitochondrial morphological changes were seen after incubation with 10 μM citral. However, since citral is a highly volatile molecule, we prepared albumin particles by a desolvation method to encapsulate citral, as a means of stabilization. We then further incorporated the loaded nanoparticles into a biodegradable polyanhydride wafer to generate a slow release system. The wafers were shown to degrade by 50% over the course of 25 days and to release the active compound. We therefore propose the use of the citral-nanoparticle-polymer wafers for implantation into the tumor bed after surgical removal of a sarcoma as a means to control locoregional spread due to any remaining cancerous cells. Keywords: citral, nanoparticle, wafer, biodegradable, mitochondria, toroidal, cancer, rhabdomyosarcoma, Cymbopogon citratus

Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

Science.gov (United States)

Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

2018-05-01

Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

Science.gov (United States)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

Denuded zone in Czochralski silicon wafer with high carbon content

International Nuclear Information System (INIS)

Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

2006-01-01

The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

Denuded zone in Czochralski silicon wafer with high carbon content

Science.gov (United States)

Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

2006-12-01

The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

Wafer scale lead zirconate titanate film preparation by sol-gel method using stress balance layer

International Nuclear Information System (INIS)

Lu Jian; Kobayashi, Takeshi; Yi Zhang; Maeda, Ryutaro; Mihara, Takashi

2006-01-01

In this paper, platinum/titanium (Pt/Ti) film was introduced as a residual stress balance layer into wafer scale thick lead zirconate titanate (PZT) film fabrication by sol-gel method. The stress developing in PZT film's bottom electrode as well as in PZT film itself during deposition were analyzed; the wafer curvatures, PZT crystallizations and PZT electric properties before and after using Pt/Ti stress balance layer were studied and compared. It was found that this layer is effective to balance the residual stress in PZT film's bottom electrode induced by thermal expansion coefficient mismatch and Ti diffusion, thus can notably reduce the curvature of 4-in. wafer from - 40.5 μm to - 12.9 μm after PZT film deposition. This stress balance layer was also found effective to avoid the PZT film cracking even when annealed by rapid thermal annealing with heating-rate up to 10.5 deg. C/s. According to X-ray diffraction analysis and electric properties characterization, crack-free uniform 1-μm-thick PZT film with preferred pervoskite (001) orientation, excellent dielectric constant, as high as 1310, and excellent remanent polarization, as high as 39.8 μC/cm 2 , can be obtained on 4-in. wafer

Apparatus and method for defect testing of integrated circuits

Science.gov (United States)

Cole, Jr., Edward I.; Soden, Jerry M.

2000-01-01

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

Tunneling Current Probe for Noncontract Wafer-Level Photodiode Array Testing

National Research Council Canada - National Science Library

Verdun, Horacio

1999-01-01

The Tunneling Current Probe (TCP) is an automated picometer-sensitive proximity sensor and current measurement system which measures the current through a photodiode detector array element by establishing a tunneling current...

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

KAUST Repository

Pirro, Luca

2015-09-01

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

KAUST Repository

Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

2015-01-01

Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

Science.gov (United States)

Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

2016-08-01

Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

Mathematical model for predicting molecular-beam epitaxy growth rates for wafer production

International Nuclear Information System (INIS)

Shi, B.Q.

2003-01-01

An analytical mathematical model for predicting molecular-beam epitaxy (MBE) growth rates is reported. The mathematical model solves the mass-conservation equation for liquid sources in conical crucibles and predicts the growth rate by taking into account the effect of growth source depletion on the growth rate. Assumptions made for deducing the analytical model are discussed. The model derived contains only one unknown parameter, the value of which can be determined by using data readily available to MBE growers. Procedures are outlined for implementing the model in MBE production of III-V compound semiconductor device wafers. Results from use of the model to obtain targeted layer compositions and thickness of InP-based heterojunction bipolar transistor wafers are presented

Spatially resolved localized vibrational mode spectroscopy of carbon in liquid encapsulated Czochralski grown gallium arsenide wafers

International Nuclear Information System (INIS)

Yau, Waifan.

1988-04-01

Substitutional carbon on an arsenic lattice site is the shallowest and one of the most dominant acceptors in semi-insulating Liquid Encapsulated Czochralski (LEC) GaAs. However, the role of this acceptor in determining the well known ''W'' shape spatial variation of neutral EL2 concentration along the diameter of a LEC wafer is not known. In this thesis, we attempt to clarify the issue of the carbon acceptor's effect on this ''W'' shaped variation by measuring spatial profiles of this acceptor along the radius of three different as-grown LEC GaAs wafers. With localized vibrational mode absorption spectroscopy, we find that the profile of the carbon acceptor is relatively constant along the radius of each wafer. Average values of concentration are 8 x 10E15 cm -3 , 1.1 x 10E15 cm -3 , and 2.2 x 10E15 cm -3 , respectively. In addition, these carbon acceptor LVM measurements indicate that a residual donor with concentration comparable to carbon exists in these wafers and it is a good candidate for the observed neutral EL2 concentration variation. 22 refs., 39 figs

Utility of a rapid immunochromatographic strip test in detecting canine parvovirus infection compared with polymerase chain reaction

Directory of Open Access Journals (Sweden)

Sundaran S. Tinky

2015-04-01

Full Text Available Aim: The present study was undertaken to detect the presence of canine parvovirus (CPV in fecal samples of diarrheic dogs by conventional polymerase chain reaction (PCR and immunochromatographic (IC strip test and to compare the diagnostic potential of these tests. Materials and Methods: A total of 50 fecal samples collected from diarrheic dogs suspected for CPV infection were subjected to PCR using CPV-555 primer amplifying the gene coding for the VP1 protein. These samples were also tested by IC strip test using a commercial rapid Ag test kit. The results were statistically analyzed using McNemar test. Results: A total of 22 samples (44% were detected as positive by PCR, which yielded a specific amplicon of 583 bp. In IC strip test, 18 (36% samples were found to be positive. The sensitivity of the test as compared to PCR was found to be 72.22% and specificity was 92.86%. Positive predictive value and negative predictive value of IC strip test was found to be 88.89% and 81.25%, respectively. Statistical analysis of the results of PCR and IC assay using McNemar test revealed no significant difference (p>0.05. Conclusion: The IC strip test could be employed as a rapid field level diagnostic tool for the diagnosis of canine parvoviral diarrhea.

Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

Directory of Open Access Journals (Sweden)

Min-Kyoo Song

2013-01-01

Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

Task 4 - EMI/RFI Issues Potentially Impacting Electromagnetic Compatibility of I&C Systems (NRCHQ6014D0015)

Energy Technology Data Exchange (ETDEWEB)

Wood, Richard Thomas [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Ewing, Paul D. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)

2015-05-01

The U.S. Nuclear Regulatory Commission’s (NRC’s) regulations in Part 50, “Domestic Licensing of Production and Utilization Facilities,” of Title 10 of the Code of Federal Regulations (10 CFR Part 50) state that structures, systems, and components important to safety in a nuclear power plant are to be designed to accommodate the effects of environmental conditions (i.e., remain functional under all postulated service conditions) and that design control measures such as testing are to be used to check the adequacy of design. Regulatory Guide (RG) 1.180 was developed to provide guidance to licensees and applicants on methods acceptable to the NRC staff for complying with the NRC’s regulations on design, installation, and testing practices for addressing the effects of electromagnetic and radio-frequency interference (EMI/RFI) and power surges on safety-related instrumentation and control (I&C) systems. The first revision of RG 1.180 was issued in January 2000 and a second revision was issued in October 2003*. The second revision differed from the first revision in endorsing Military Standard (MIL-STD)-461E and the International Electrotechnical Commission (IEC) Standard (Std) 61000 series of EMI/RFI test methods, extending the guidance to cover signal line testing, incorporating frequency ranges where portable communications devices are experiencing increasing use, and relaxing the operating envelopes (test levels) when experience and confirmatory research warranted. It also offered exemptions from specific test criteria based on technical considerations such as plant conditions and the intended location of the safety-related I&C equipment. Since the last revision, new requirements have been identified, associated RGs have been created and updated, and additional industry guidance has been developed. Additionally, the operational environment has changed with the increase in wireless communication technology for both personal (smartphone) and industrial

Pengaruh Pengungkapan Intellectual Capital (IC dan Economic Value Added (EVA terhadap Harga Saham Perusahaan Manufaktur yang terdaftar di BEI

Directory of Open Access Journals (Sweden)

Achmad Fauzi

2015-07-01

Full Text Available This study aims at finding out if The Influence of Intellectual Capital (ICand Economic Value Added (EVA on Stock Price of Manufacturing Companies listed on the Indonesia Stock Exchange (BEI in 2012. The hypothesis of this study is : There is Influence of Intellectual Capital (IC and Economic Value Added (EVA on Stock Price of Manufacturing Company listed on the Indonesia Stock Exchange (BEI in 2012. The method used is the author of the survey method with a quantitative approach . This study population is the entire manufacturing companies listed on the Stock Exchange in 2012 his sampling technique is random sampling as many as 36 samples .. Correlation Coefficient significance test ( Test A of 0.512 , indicating that there is a middle relationship between IC and EVA on Stock Price. The results of the coefficient of determination ( R2 Test stated that R2 is 0.262 or 26.2% . This shows that the percentage contribution of the effect of independent variables ( IC and EVA on the dependent variable ( stock price of 26.2 % . Or variations of the independent variables used in the model ( IC and EVA are able to explain 26.2% of variation in the dependent variable ( stock price . While the remaining 73.8 % are influenced or explained by other variables not included in this research model .

Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers

International Nuclear Information System (INIS)

Hoechbauer, T.; Misra, A.; Nastasi, M.; Henttinen, K.; Suni, T.; Suni, I.; Lau, S.S.; Ensinger, W.

2004-01-01

Hydrogen ion-implantation into Si and subsequent heat treatment has been shown to be an effective means of cleaving thin layer of Si from its parent wafer. This process has been called Smart Cut TM or ion-cut. We investigated the cleavage process in H-implanted silicon samples, in which the ion-cut was provoked thermally and mechanically, respectively. A oriented p-type silicon wafer was irradiated at room temperature with 100 keV H 2 + -ions to a dose of 5 x 10 16 H 2 /cm 2 and subsequently joined to a handle wafer. Ion-cutting was achieved by two different methods: (1) thermally by annealing to 350 deg. C and (2) mechanically by insertion of a razor blade sidewise into the bonded wafers near the bond interface. The H-concentration and the crystal damage depth profiles before and after the ion-cut were investigated through the combined use of elastic recoil detection analysis and Rutherford backscattering spectroscopy (RBS). The location at which the ion-cut occurred was determined by RBS in channeling mode and cross-section transmission electron spectroscopy. The ion-cut depth was found to be independent on the cutting method. The gained knowledge was correlated to the depth distribution of the H-platelet density in the as-implanted sample, which contains two separate peaks in the implantation zone. The obtained results suggest that the ion-cut location coincides with the depth of the H-platelet density peak located at a larger depth

Fusion bonding of Si wafers investigated by x ray diffraction

DEFF Research Database (Denmark)

Weichel, Steen; Grey, Francois; Rasmussen, Kurt

2000-01-01

The interface structure of bonded Si(001) wafers with twist angle 6.5 degrees is studied as a function of annealing temperature. An ordered structure is observed in x-ray diffraction by monitoring a satellite reflection due to the periodic modulation near the interface, which results from...

Design Developing of IC- Model Using VHDL

International Nuclear Information System (INIS)

Inzar-Anas

2005-01-01

In present, the electronic design required to become simple, small and flexible. The physical dimension of IC and number of pin can be significantly reduced while the flexibility and compatibility of IC was not change. Implementation of VHDL(VHSIC Hardware Description Language) seem as a great progress in the design of digital circuit. By using this language designing of model can be more simple, flexible and efficient. This paper was purposed to introduce VHDL and its features. Sample in modeling to illustrate the advantage of VHDL will also be described. (author)

Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

Science.gov (United States)

Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

2016-11-01

The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

Sensitivity Study on Availability of I&C Components Using Bayesian Network

Directory of Open Access Journals (Sweden)

Rahman Khalil Ur

2013-01-01

Full Text Available The objective of this study is to find out the impact of instrumentation and control (I&C components on the availability of I&C systems in terms of sensitivity analysis using Bayesian network. The analysis has been performed on I&C architecture of reactor protection system. The analysis results would be applied to develop I&C architecture which will meet the desire reliability features and save cost. RPS architecture unavailability P(x=0 and availability P(x=1 were estimated to 6.1276E-05 and 9.9994E-01 for failure (0 and perfect (1 states, respectively. The impact of I&C components on overall system risk has been studied in terms of risk achievement worth (RAW and risk reduction worth (RRW. It is found that circuit breaker failure (TCB, bi-stable processor (BP, sensor transmitter (TR, and pressure transmitter (PT have high impact on risk. The study concludes and recommends that circuit breaker bi-stable processor should be given more consideration while designing I&C architecture.

Post-test analysis of PIPER-ONE PO-IC-2 experiment by RELAP5/MOD3 codes

International Nuclear Information System (INIS)

Bovalini, R.; D'Auria, F.; Galassi, G.M.; Mazzini, M.

1996-11-01

RELAP5/MOD3.1 was applied to the PO-IC-2 experiment performed in PIPER-ONE facility, which has been modified to reproduce typical isolation condenser thermal-hydraulic conditions. RELAP5 is a well known code widely used at the University of Pisa during the past seven years. RELAP5/MOD3.1 was the latest version of the code made available by the Idaho National Engineering Laboratory at the time of the reported study. PIPER-ONE is an experimental facility simulating a General Electric BWR-6 with volume and height scaling ratios of 1/2,200 and 1./1, respectively. In the frame of the present activity a once-through heat exchanger immersed in a pool of ambient temperature water, installed approximately 10 m above the core, was utilized to reproduce qualitatively the phenomenologies expected for the Isolation Condenser in the simplified BWR (SBWR). The PO-IC-2 experiment is the flood up of the PO-SD-8 and has been designed to solve some of the problems encountered in the analysis of the PO-SD-8 experiment. A very wide analysis is presented hereafter including the use of different code versions

Investigation of room-temperature wafer bonded GaInP/GaAs/InGaAsP triple-junction solar cells

Energy Technology Data Exchange (ETDEWEB)

Yang, Wen-xian; Dai, Pan; Ji, Lian; Tan, Ming; Wu, Yuan-yuan [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China); Uchida, Shiro [Department of Mechanical Science and Engineering Faculty of Engineering, Chiba Institute of Technology, 2-17-1, Tsudanuma, Narashino, Chiba 275-0016 (Japan); Lu, Shu-long, E-mail: sllu2008@sinano.ac.cn [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China); Yang, Hui [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China)

2016-12-15

Highlights: • High quality InGaAsP material with a bandgap of 1.0 eV was grown by MBE. • Room-temperature wafer-bonded GaInP/GaAs/InGaAsP SCs were fabricated. • An efficiency of 30.3% of wafer-bonded triple-junction SCs was obtained. - Abstract: We report on the fabrication of III–V compound semiconductor multi-junction solar cells using the room-temperature wafer bonding technique. GaInP/GaAs dual-junction solar cells on GaAs substrate and InGaAsP single junction solar cell on InP substrate were separately grown by all-solid state molecular beam epitaxy (MBE). The two cells were then bonded to a triple-junction solar cell at room-temperature. A conversion efficiency of 30.3% of GaInP/GaAs/InGaAsP wafer-bonded solar cell was obtained at 1-sun condition under the AM1.5G solar simulator. The result suggests that the room-temperature wafer bonding technique and MBE technique have a great potential to improve the performance of multi-junction solar cell.

Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

International Nuclear Information System (INIS)

Moslehi, M.M.; Davis, C.

1989-01-01

Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

Science.gov (United States)

Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

2018-06-01

Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

Science.gov (United States)

Nguyen, M. D.; Tiggelaar, R.; Aukes, T.; Rijnders, G.; Roelof, G.

2017-11-01

Piezoelectric lead-zirconate-titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films. The results indicated that the highly textured (001)-oriented PZT thin films with wafer-scale thickness homogeneity (990 nm ± 0.8%) were obtained. The films were fabricated into piezoelectric cantilevers through a MEMS microfabrication process. The measured longitudinal piezoelectric coefficient (d 33f = 210 pm/V ± 1.6%) and piezoelectric transverse coefficient (e 31f = -18.8 C/m2 ± 2.8%) were high and homogeneity across wafers. The high piezoelectric properties on Si wafers will extend industrial application of PZT thin films and further development of piezoMEMS.

The MusIC method: a fast and quasi-optimal solution to the muscle forces estimation problem.

Science.gov (United States)

Muller, A; Pontonnier, C; Dumont, G

2018-02-01

The present paper aims at presenting a fast and quasi-optimal method of muscle forces estimation: the MusIC method. It consists in interpolating a first estimation in a database generated offline thanks to a classical optimization problem, and then correcting it to respect the motion dynamics. Three different cost functions - two polynomial criteria and a min/max criterion - were tested on a planar musculoskeletal model. The MusIC method provides a computation frequency approximately 10 times higher compared to a classical optimization problem with a relative mean error of 4% on cost function evaluation.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

Directory of Open Access Journals (Sweden)

Kenji Okabe

2015-12-01

Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

Science.gov (United States)

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-12-16

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Differential diagnosis between aneurysm and infundibular dilatation in the IC-PC region with 3D-CTA

International Nuclear Information System (INIS)

Kubota, Tsukasa; Niwa, Jun; Tanigawara, Tetsuya; Chiba, Masahiko; Akiyama, Yukinori; Inamura Shigeru

2000-01-01

In cases of asymptomatic internal carotid-posterior communicating artery (IC-PC) protrusions, it is sometimes difficult to differentiate infundibular dilatation (ID) from aneurysm by digital subtraction angiography. We applied three-dimensional CT angiography (3D-CTA) in 32 cases of these IC-PC protrusions. SOMATOM PLUS 4 was used under such conditions as to provide images with high spatial resolution. The shaded surface display (SSD) method was adopted to reconstruct the 3D images because of its advantage in separating overlapped vasculature. We also made reference to source images and maximum intensity projection (MIP) to make sure of our diagnoses. In all cases including 4 aneurysms and 28 IDs, we were able to distinguish between ID and aneurysm. The accuracy of 3D-CTA was confirmed by 9 surgical cases. Our technique was as follows: To inject a high dose of diluted contrast medium rapidly to smaller arteries for opacification of contrast medium. To exclude neighboring useless structures except for the very close structures such as posterior clinoid process from the target image focusing on the IC-PC region. To observe the reconstructed image of MIP and SSD from various angles. The contralateral and craniocaudal view were valuable. To change the threshold level gradually and observe the configurational changes of the apex of protrusion. Poorly developed PcomA was mostly delineated at the optimum threshold level. Otherwise, the apex of protrusion remained spherical in an aneurysm and became pyramidal in shape in an ID when the threshold level was gradually decreased. In conclusion, 3D-CTA was a useful modality for IC-PC protrusions to distinguish between ID and aneurysm. (author)

System reduction for nanoscale IC design

CERN Document Server

2017-01-01

This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.

Method of manufacturing a capacitor on a nanowire and integrated circuit having such a capacitor

NARCIS (Netherlands)

2009-01-01

A method of manufacturing a capacitor on a wafer, and an IC comprising such a capacitor is disclosed. The method comprises forming a plurality of vertical structures (140) each having a sub-micron thickness on the wafer; and growing a metal-insulator-metal (MIM) stack (150) over the plurality of

Instrument Control (iC) - An Open-Source Software to Automate Test Equipment.

Science.gov (United States)

Pernstich, K P

2012-01-01

It has become common practice to automate data acquisition from programmable instrumentation, and a range of different software solutions fulfill this task. Many routine measurements require sequential processing of certain tasks, for instance to adjust the temperature of a sample stage, take a measurement, and repeat that cycle for other temperatures. This paper introduces an open-source Java program that processes a series of text-based commands that define the measurement sequence. These commands are in an intuitive format which provides great flexibility and allows quick and easy adaptation to various measurement needs. For each of these commands, the iC-framework calls a corresponding Java method that addresses the specified instrument to perform the desired task. The functionality of iC can be extended with minimal programming effort in Java or Python, and new measurement equipment can be addressed by defining new commands in a text file without any programming.

30 GHz monolithic balanced mixers using an ion-implanted FET-compatible 3-inch GaAs wafer process technology

Science.gov (United States)

Bauhahn, P.; Contolatis, A.; Sokolov, V.; Chao, C.

1986-01-01

An all ion-implanted Schottky barrier mixer diode which has a cutoff frequency greater than 1000 GHz has been developed. This new device is planar and FET-compatible and employs a projection lithography 3-inch wafer process. A Ka-band monolithic balanced mixer based on this device has been designed, fabricated and tested. A conversion loss of 8 dB has been measured with a LO drive of 10 dBm at 30 GHz.

Eutectic and solid-state wafer bonding of silicon with gold

International Nuclear Information System (INIS)

Abouie, Maryam; Liu, Qi; Ivey, Douglas G.

2012-01-01

Highlights: ► Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. ► Exchange of a-Si and Au layer was observed in both types of bonded samples. ► Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. ► Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 °C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 °C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

Catalog of Realizations for DXCCII using Commercially Available ICs and Applications

Directory of Open Access Journals (Sweden)

S. Maheshwari

2012-04-01

Full Text Available This paper presents fifteen distinct practical realizations for dual-X second generation current conveyor (DXCCII using commercially available integrated circuits. Detailed comparisons and results are presented to verify the utility of proposed realizations. The catalog of proposed realizations is a first attempt and is expected to be useful for testing newly developed circuits based on dual-X second generation current conveyor. Each of the first fourteen proposed realizations uses four ICs. One three IC based implementation is further given making the total count fifteen. Some additional features are also explored which further enhance the versatility of DXCCII. The paper further presents a novel and compact quadrature oscillator to verify the applicability of the proposed realizations. Single resistance control of the frequency of oscillation is also demonstrated by employing the new gain-variable DXCCII. Experimental results are also included along with simulation results to validate the proposed theory and its practical significance.

Machine learning and predictive data analytics enabling metrology and process control in IC fabrication

Science.gov (United States)

Rana, Narender; Zhang, Yunlin; Wall, Donald; Dirahoui, Bachir; Bailey, Todd C.

2015-03-01

Integrate circuit (IC) technology is going through multiple changes in terms of patterning techniques (multiple patterning, EUV and DSA), device architectures (FinFET, nanowire, graphene) and patterning scale (few nanometers). These changes require tight controls on processes and measurements to achieve the required device performance, and challenge the metrology and process control in terms of capability and quality. Multivariate data with complex nonlinear trends and correlations generally cannot be described well by mathematical or parametric models but can be relatively easily learned by computing machines and used to predict or extrapolate. This paper introduces the predictive metrology approach which has been applied to three different applications. Machine learning and predictive analytics have been leveraged to accurately predict dimensions of EUV resist patterns down to 18 nm half pitch leveraging resist shrinkage patterns. These patterns could not be directly and accurately measured due to metrology tool limitations. Machine learning has also been applied to predict the electrical performance early in the process pipeline for deep trench capacitance and metal line resistance. As the wafer goes through various processes its associated cost multiplies. It may take days to weeks to get the electrical performance readout. Predicting the electrical performance early on can be very valuable in enabling timely actionable decision such as rework, scrap, feedforward, feedback predicted information or information derived from prediction to improve or monitor processes. This paper provides a general overview of machine learning and advanced analytics application in the advanced semiconductor development and manufacturing.

Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

Science.gov (United States)

Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

2018-03-01

A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

Pulse plating of Pt on n-GaAs (1 0 0) wafer surfaces: Synchrotron induced photoelectron spectroscopy and XPS of wet fabrication processes

International Nuclear Information System (INIS)

Ensling, D.; Hunger, R.; Kraft, D.; Mayer, Th.; Jaegermann, W.; Rodriguez-Girones, M.; Ichizli, V.; Hartnagel, H.L.

2003-01-01

Preparation steps of Pt/n-GaAs Schottky contacts as applied in the fabrication process of varactor diode arrays for THz applications are analysed by photoelectron spectroscopy. Pulsed cathodic deposition of Pt onto GaAs (1 0 0) wafer surfaces from acidic solution has been studied by core level photoelectron spectroscopy using different excitation energies. A laboratory AlKα source as well as synchrotron radiation of hν=130 and 645 eV at BESSY was used. Chemical analyses and semiquantitative estimates of layer thickness are given for the natural oxide of an untreated wafer surface, a surface conditioning NH 3 etching step, and stepwise pulse plating of Pt. The structural arrangement of the detected species and interface potentials are considered

Large Out-of-Plane Displacement Bistable Electromagnetic Microswitch on a Single Wafer.

Science.gov (United States)

Miao, Xiaodan; Dai, Xuhan; Huang, Yi; Ding, Guifu; Zhao, Xiaolin

2016-05-05

This paper presents a bistable microswitch fully batch-fabricated on a single glass wafer, comprising of a microactuator, a signal transformer, a microspring and a permanent magnet. The bistable mechanism of the microswitch with large displacement of 160 μm depends on the balance of the magnetic force and elastic force. Both the magnetic force and elastic force were optimized by finite-element simulation to predict the reliable of the device. The prototype was fabricated and characterized. By utilizing thick laminated photoresist sacrificial layer, the large displacement was obtained to ensure the insulation of the microswitch. The testing results show that the microswitch realized the bistable mechanism at a 3-5 V input voltage and closed in 0.96 ms, which verified the simulation.

30 CFR 57.22209 - Auxiliary fans (I-C mines).

Science.gov (United States)

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Auxiliary fans (I-C mines). 57.22209 Section 57... Standards for Methane in Metal and Nonmetal Mines Ventilation § 57.22209 Auxiliary fans (I-C mines). Electric auxiliary fans shall be approved by MSHA under the applicable requirements of 30 CFR part 18...

Identification of signals that facilitate isoform specific nucleolar localization of myosin IC

Energy Technology Data Exchange (ETDEWEB)

Schwab, Ryan S.; Ihnatovych, Ivanna; Yunus, Sharifah Z.S.A.; Domaradzki, Tera [Department of Physiology and Biophysics, University at Buffalo—State University of New York, Buffalo, NY (United States); Hofmann, Wilma A., E-mail: whofmann@buffalo.edu [Department of Physiology and Biophysics, University at Buffalo—State University of New York, Buffalo, NY (United States)

2013-05-01

Myosin IC is a single headed member of the myosin superfamily that localizes to the cytoplasm and the nucleus, where it is involved in transcription by RNA polymerases I and II, intranuclear transport, and nuclear export. In mammalian cells, three isoforms of myosin IC are expressed that differ only in the addition of short isoform-specific N-terminal peptides. Despite the high sequence homology, the isoforms show differences in cellular distribution, in localization to nuclear substructures, and in their interaction with nuclear proteins through yet unknown mechanisms. In this study, we used EGFP-fusion constructs that express truncated or mutated versions of myosin IC isoforms to detect regions that are involved in isoform-specific localization. We identified two nucleolar localization signals (NoLS). One NoLS is located in the myosin IC isoform B specific N-terminal peptide, the second NoLS is located upstream of the neck region within the head domain. We demonstrate that both NoLS are functional and necessary for nucleolar localization of specifically myosin IC isoform B. Our data provide a first mechanistic explanation for the observed functional differences between the myosin IC isoforms and are an important step toward our understanding of the underlying mechanisms that regulate the various and distinct functions of myosin IC isoforms. - Highlights: ► Two NoLS have been identified in the myosin IC isoform B sequence. ► Both NoLS are necessary for myosin IC isoform B specific nucleolar localization. ► First mechanistic explanation of functional differences between the isoforms.

Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

Science.gov (United States)

Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

2018-06-01

Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

Voltage-assisted polymer wafer bonding

International Nuclear Information System (INIS)

Varsanik, J S; Bernstein, J J

2012-01-01

Polymer wafer bonding is a widely used process for fabrication of microfluidic devices. However, best practices for polymer bonds do not achieve sufficient bond strength for many applications. By applying a voltage to a polymer bond in a process called voltage-assisted bonding, bond strength is shown to improve dramatically for two polymers (Cytop™ and poly(methyl methacrylate)). Several experiments were performed to provide a starting point for further exploration of this technique. An optimal voltage range is experimentally observed with a reduction in bonding strength at higher voltages. Additionally, voltage-assisted bonding is shown to reduce void diameter due to bond defects. An electrostatic force model is proposed to explain the improved bond characteristics. This process can be used to improve bond strength for most polymers. (paper)

Study on Mine Emergency Mechanism based on TARP and ICS

Science.gov (United States)

Xi, Jian; Wu, Zongzhi

2018-01-01

By analyzing the experiences and practices of mine emergency in China and abroad, especially the United States and Australia, normative principle, risk management principle and adaptability principle of constructing mine emergency mechanism based on Trigger Action Response Plans (TARP) and Incident Command System (ICS) are summarized. Classification method, framework, flow and subject of TARP and ICS which are suitable for the actual situation of domestic mine emergency are proposed. The system dynamics model of TARP and ICS is established. The parameters such as evacuation ratio, response rate, per capita emergency capability and entry rate of rescuers are set up. By simulating the operation process of TARP and ICS, the impact of these parameters on the emergency process are analyzed, which could provide a reference and basis for building emergency capacity, formulating emergency plans and setting up action plans in the emergency process.

Testbed diversity as a fundamental principle for effective ICS security research

OpenAIRE

Green, Benjamin; Frey, Sylvain Andre Francis; Rashid, Awais; Hutchison, David

2016-01-01

The implementation of diversity in testbeds is essential to understanding and improving the security and resilience of Industrial Control Systems (ICS). Employing a wide spec- trum of equipment, diverse networks, and business processes, as deployed in real-life infrastructures, is particularly diffi- cult in experimental conditions. However, this level of di- versity is key from a security perspective, as attackers can exploit system particularities and process intricacies to their advantage....

Prometheus Reactor I&C Software Development Methodology, for Action

Energy Technology Data Exchange (ETDEWEB)

T. Hamilton

2005-07-30

The purpose of this letter is to submit the Reactor Instrumentation and Control (I&C) software life cycle, development methodology, and programming language selections and rationale for project Prometheus to NR for approval. This letter also provides the draft Reactor I&C Software Development Process Manual and Reactor Module Software Development Plan to NR for information.

Wafer-scale integration of piezoelectric actuation capabilities in nanoelectromechanical systems resonators

OpenAIRE

DEZEST, Denis; MATHIEU, Fabrice; MAZENQ, Laurent; SOYER, Caroline; COSTECALDE, Jean; REMIENS, Denis; THOMAS, Olivier; DEÜ, Jean-François; NICU, Liviu

2013-01-01

In this work, we demonstrate the integration of piezoelectric actuation means on arrays of nanocantilevers at the wafer scale. We use lead titanate zirconate (PZT) as piezoelectric material mainly because of its excellent actuation properties even when geometrically constrained at extreme scale

Comparison Study on I&C System Architecture of the Third Generation NPP Between EPR 1600 and US-APWR 1700

International Nuclear Information System (INIS)

Nafi Feridian; Arief Heru Kuncoro

2009-01-01

In order to support government's programs on research and development of nuclear energy, so a comparative study has been conducted on I&C system architecture of the third generation Nuclear Power Plant (NPP) of EPR 1600 and US-APWR 1700. I&C system is one of supporting systems in nuclear power plant in such away that the nuclear reactor operation can be safely and control. This study compares parameters on main structure of I&C system architecture related with safety system of nuclear power plant operation.The methodology of this study are literature study, data collection, review and analysis. It can be concluded although the two system have some have similarities, both of them have implemented a modern digital and computerized I&C system architecture with high ability of safety level and suitable with American code standard. But in general, they have difference parameters, such as classification of safety-related and non safety-related group, control and monitoring system, supporting systems of defence in depth and also supporting systems of I&C safety. (author)

An Improved Dispatching Method (a-HPDB for Automated Material Handling System with Active Rolling Belt for 450 mm Wafer Fabrication

Directory of Open Access Journals (Sweden)

Chia-Nan Wang

2017-07-01

Full Text Available The semiconductor industry is facing the transition from 300 mm to 450 mm wafer fabrication. Due to the increased size and weight, 450 mm wafers will pose unprecedented challenges on semiconductor wafer fabrication. To better handle and transport 450 mm wafers, an advanced Automated Material Handling System (AMHS is definitely required. Though conveyor-based AMHS is expected to be suitable for 450 mm wafer fabrication, still it faces two main problems, traffic-jam problem and lot-prioritization. To address the two problems, in this research we have proposed an improved dispatching method, termed Heuristic Preemptive Dispatching Method using Activated Roller Belt (a-HPDB. We have developed some effective rules for the a-HPDB based on Activated Roller Belt (ARB. In addition, we have conducted experiments to investigate its effectiveness. Compared with the HPDB and R-HPD, two dispatching rules proposed in previous studies, our experimental results showed the a-HPDB had a better performance in terms of average lot delivery time (ALDT. For hot lots and normal lots, the a-HPDB had advantages of 4.14% and 8.92% over the HPDB and advantages of 4.89% and 8.52% over R-HPD, respectively.

Comparison of slowness profiles of lamb wave with elastic moduli and crystal structure in single crystalline silicon wafers

Energy Technology Data Exchange (ETDEWEB)

Min, Young Jae; Yun, Gyeong Won; Kim, Kyung Min; Roh, Yuji; Kim, Young H. [Applied Acoustics Lab, Korea Science Academy of KAIST, Busan (Korea, Republic of)

2016-02-15

Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

Improved process control, lowered costs and reduced risks through the use of non-destructive mobility and sheet carrier density measurements on GaAs and GaN wafers

Science.gov (United States)

Nguyen, D.; Hogan, K.; Blew, A.; Cordes, M.

2004-12-01

Improved process control, lowered costs and reduced risks can be realized through the use of non-destructive mobility and sheet charge density measurements during the fabrication of GaAs and GaN wafers. The results from this microwave-based technique are shown to agree with destructive van der Pauw Hall testing results to within ±5%. In addition, it has the ability to map wafer uniformity and provide separated 2DEG data for thick cap or multi-layered structures. As a result, this technique provides an efficient and cost-effective alternative to current process control metrology methods, while providing the user with important process control data.

A full-wafer fabrication process for glass microfluidic chips with integrated electroplated electrodes by direct bonding of dry film resist

International Nuclear Information System (INIS)

Vulto, Paul; Urban, G A; Huesgen, Till; Albrecht, Björn

2009-01-01

A full-wafer process is presented for fast and simple fabrication of glass microfluidic chips with integrated electroplated electrodes. The process employs the permanent dry film resist (DFR) Ordyl SY300 to create microfluidic channels, followed by electroplating of silver and subsequent chlorination. The dry film resist is bonded directly to a second substrate, without intermediate gluing layers, only by applying pressure and moderate heating. The process of microfluidic channel fabrication, electroplating and wafer bonding can be completed within 1 day, thus making it one of the fastest and simplest full-wafer fabrication processes. (note)