WorldWideScience

Sample records for wafer bonded cmuts

  1. Void-Free Direct Bonding of CMUT Arrays with Single Crystalline Plates and Pull- In Insulation

    DEFF Research Database (Denmark)

    Christiansen, Thomas Lehrmann; Hansen, Ole; Dahl Johnsen, Mathias

    2013-01-01

    The implications on direct bonding quality, when using a double oxidation step to fabricate capacitive micromachined ultrasonic transducers (CMUTs), is analyzed. The protrusions along the CMUT cavity edges created during the second oxidation are investigated using simulations, AFM measurements, a...

  2. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  3. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  4. Fabrication and Characterization of Capacitive Micromachined Ultrasonic Transducers with Low-Temperature Wafer Direct Bonding

    Directory of Open Access Journals (Sweden)

    Xiaoqing Wang

    2016-12-01

    Full Text Available This paper presents a fabrication method of capacitive micromachined ultrasonic transducers (CMUTs by wafer direct bonding, which utilizes both the wet chemical and O2plasma activation processes to decrease the bonding temperature to 400 °C. Two key surface properties, the contact angle and surface roughness, are studied in relation to the activation processes, respectively. By optimizing the surface activation parameters, a surface roughness of 0.274 nm and a contact angle of 0° are achieved. The infrared images and static deflection of devices are assessed to prove the good bonding effect. CMUTs having silicon membranes with a radius of 60 μm and a thickness of 2 μm are fabricated. Device properties have been characterized by electrical and acoustic measurements to verify their functionality and thus to validate this low-temperature process. A resonant frequency of 2.06 MHz is obtained by the frequency response measurements. The electrical insertion loss and acoustic signal have been evaluated. This study demonstrates that the CMUT devices can be fabricated by low-temperature wafer direct bonding, which makes it possible to integrate them directly on top of integrated circuit (IC substrates.

  5. 2-D Row-Column CMUT Arrays with an Open-Grid Support Structure

    DEFF Research Database (Denmark)

    Christiansen, Thomas Lehrmann; Dahl-Petersen, Christian; Jensen, Jørgen Arendt

    2013-01-01

    Fabrication and characterization of 64 + 64 2-D row-column addressed CMUT arrays with 250 μm element pitch and 4.4 MHz center frequency in air incorporating a new design approach is presented. The arrays are comprised of two wafer bonded, structured silicon-on-insulator wafers featuring an opengr...

  6. Voltage-assisted polymer wafer bonding

    International Nuclear Information System (INIS)

    Varsanik, J S; Bernstein, J J

    2012-01-01

    Polymer wafer bonding is a widely used process for fabrication of microfluidic devices. However, best practices for polymer bonds do not achieve sufficient bond strength for many applications. By applying a voltage to a polymer bond in a process called voltage-assisted bonding, bond strength is shown to improve dramatically for two polymers (Cytop™ and poly(methyl methacrylate)). Several experiments were performed to provide a starting point for further exploration of this technique. An optimal voltage range is experimentally observed with a reduction in bonding strength at higher voltages. Additionally, voltage-assisted bonding is shown to reduce void diameter due to bond defects. An electrostatic force model is proposed to explain the improved bond characteristics. This process can be used to improve bond strength for most polymers. (paper)

  7. Mechanics of wafer bonding: Effect of clamping

    Science.gov (United States)

    Turner, K. T.; Thouless, M. D.; Spearing, S. M.

    2004-01-01

    A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

  8. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  9. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

  10. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

  11. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  12. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

    Science.gov (United States)

    Turner, K. T.; Spearing, S. M.

    2002-12-01

    Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

  13. Si-to-Si wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Reus, Roger De; Lindahl, M.

    1997-01-01

    Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

  14. BCB polymer based row-column addressed CMUT

    DEFF Research Database (Denmark)

    Havreland, Andreas Spandet; Ommen, Martin Lind; Silvestre, Chantal

    2017-01-01

    This paper presents an inexpensive, low temperature and rapid fabrication method for capacitive micromachined ultrasonic transducers (CMUT). The fabrication utilizes the bonding and dielectric properties of the photosensitive polymer Benzocyclobutene (BCB). A BCB based row-column addressed CMUT w...

  15. Cohesive zone model for direct silicon wafer bonding

    Science.gov (United States)

    Kubair, D. V.; Spearing, S. M.

    2007-05-01

    Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

  16. Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

    Science.gov (United States)

    Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

    2004-10-01

    The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

  17. Physical mechanisms of Cu-Cu wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.

    2014-01-01

    Modern manufacturing processes of complex integrated semiconductor devices are based on wafer-level manufacturing of components which are subsequently interconnected. When compared with classical monolithic bi-dimensional integrated circuits (2D ICs), the new approach of three-dimensional integrated circuits (3D ICs) exhibits significant benefits in terms of signal propagation delay and power consumption due to the reduced metal interconnection length and allows high integration levels with reduced form factor. Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level, which facilitates the electrical and mechanical connection of two wafers even processed in different technologies, such as complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS). Due to its high electrical conductivity, copper is a very attractive material for electrical interconnects. For Cu-Cu wafer bonding the process requires typically bonding for around 1 h at 400°C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve issues regarding (i) throughput in the wafer bonder, (ii) wafer-to-wafer misalignment after bonding and (iii) to minimise thermo-mechanical stresses or device degradation. The aim of this work was to study the physical mechanisms of Cu-Cu bonding and based on this study to further optimise the bonding process for low temperatures. The critical sample parameters (roughness, oxide, crystallinity) were identified using selected analytical techniques and correlated with the characteristics of the bonded Cu-Cu interfaces. Based on the results of this study the impact of several materials and process specifications on the bonding result were theoretically defined and experimentally proven. These fundamental findings subsequently facilitated low temperature (LT) metal thermo-compression Cu-Cu wafer bonding and even room temperature direct

  18. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    Science.gov (United States)

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  19. Bond strength tests between silicon wafers and duran tubes (fusion bonded fluidic interconnects)

    NARCIS (Netherlands)

    Fazal, I.; Berenschot, Johan W.; de Boer, J.H.; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2005-01-01

    The fusion bond strength of glass tubes with standard silicon wafers is presented. Experiments with plain silicon wafers and those coated with silicon oxide and silicon nitride are presented. Results obtained are discussed in terms of homogeneity and strength of fusion bond. High pressure testing

  20. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Directory of Open Access Journals (Sweden)

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  1. Science and technology of plasma activated direct wafer bonding

    Science.gov (United States)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  2. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

  3. Comparative TEM study of bonded silicon/silicon interfaces fabricated by hydrophilic, hydrophobic and UHV wafer bonding

    International Nuclear Information System (INIS)

    Reznicek, A.; Scholz, R.; Senz, S.; Goesele, U.

    2003-01-01

    Wafers of Czochralski-grown silicon were bonded hydrophilically, hydrophobically and in ultrahigh vacuum (UHV) at room temperature. Wafers bonded hydrophilically adhere together by hydrogen bonds, those bonded hydrophobically by van der Waals forces and UHV-bonded ones by covalent bonds. Annealing the pre-bonded hydrophilic and hydrophobic wafer pairs in argon for 2 h at different temperatures increases the initially low bonding energy. UHV-bonded wafer pairs were also annealed to compare the results. Transmission electron microscopy (TEM) investigations show nano-voids at the interface. The void density depends on the initial bonding strength. During annealing the shape, coverage and density of the voids change significantly

  4. Fusion bonding of Si wafers investigated by x ray diffraction

    DEFF Research Database (Denmark)

    Weichel, Steen; Grey, Francois; Rasmussen, Kurt

    2000-01-01

    The interface structure of bonded Si(001) wafers with twist angle 6.5 degrees is studied as a function of annealing temperature. An ordered structure is observed in x-ray diffraction by monitoring a satellite reflection due to the periodic modulation near the interface, which results from...

  5. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  6. Physical mechanisms of copper-copper wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.; Hingerl, K.

    2015-01-01

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing

  7. Low-temperature Au/a-Si wafer bonding

    International Nuclear Information System (INIS)

    Jing, Errong; Xiong, Bin; Wang, Yuelin

    2011-01-01

    The Si/SiO 2 /Ti/Au–Au/Ti/a-Si/SiO 2 /Si bonding structure, which can also be used for the bonding of non-silicon material, was investigated for the first time in this paper. The bond quality test showed that the bond yield, bond repeatability and average shear strength are higher for this bonding structure. The interfacial microstructure analysis indicated that the Au-induced crystallization of the amorphous silicon process leads to big Si grains extending across the bond interface and Au filling the other regions of the bond interface, which result into a strong and void-free bond interface. In addition, the Au-induced crystallization reaction leads to a change in the IR images of the bond interface. Therefore, the IR microscope can be used to evaluate and compare the different bond strengths qualitatively. Furthermore, in order to verify the superiority of the bonding structure, the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si (i.e. no Ti/Au layer on the a-Si surface) and Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structures (i.e. Au thermocompression bonding) were also investigated. For the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si bonding structure, the poor bond quality is due to the native oxide layer on the a-Si surface, and for the Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structure, the poor bond quality is caused by the wafer surface roughness which prevents intimate contact and limits the interdiffusion at the bond interface.

  8. Simplified nonplanar wafer bonding for heterogeneous device integration

    Science.gov (United States)

    Geske, Jon; Bowers, John E.; Riley, Anton

    2004-07-01

    We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

  9. Automotive SOI-BCD Technology Using Bonded Wafers

    International Nuclear Information System (INIS)

    Himi, H.; Fujino, S.

    2008-01-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  10. An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

    Science.gov (United States)

    Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

    2009-10-01

    State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

  11. Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

    Energy Technology Data Exchange (ETDEWEB)

    Trushin, Maxim

    2011-07-15

    The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

  12. Reliable four-point flexion test and model for die-to-wafer direct bonding

    Energy Technology Data Exchange (ETDEWEB)

    Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.; Moriceau, H. [Univ. Grenoble Alpes, F-38000 Grenoble, France and CEA, LETI, MINATEC Campus, F-38054 Grenoble (France)

    2015-07-07

    For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, both D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.

  13. Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

    International Nuclear Information System (INIS)

    Khan, M F; Ghavanini, F A; Enoksson, P; Haasl, S; Löfgren, L; Persson, K; Rusu, C; Schjølberg-Henriksen, K

    2010-01-01

    This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

  14. Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

    2012-01-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

  15. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  16. Impact of SiO2 on Al–Al thermocompression wafer bonding

    International Nuclear Information System (INIS)

    Malik, Nishant; Finstad, Terje G; Schjølberg-Henriksen, Kari; Poppe, Erik U; Taklo, Maaike M V

    2015-01-01

    Al–Al thermocompression bonding suitable for wafer level sealing of MEMS devices has been investigated. This paper presents a comparison of thermocompression bonding of Al films deposited on Si with and without a thermal oxide (SiO 2 film). Laminates of diameter 150 mm containing device sealing frames of width 200 µm were realized. The wafers were bonded by applying a bond force of 36 or 60 kN at bonding temperatures ranging from 300–550 °C for bonding times of 15, 30 or 60 min. The effects of these process variations on the quality of the bonded laminates have been studied. The bond quality was estimated by measurements of dicing yield, tensile strength, amount of cohesive fracture in Si and interfacial characterization. The mean bond strength of the tested structures ranged from 18–61 MPa. The laminates with an SiO 2 film had higher dicing yield and bond strength than the laminates without SiO 2 for a 400 °C bonding temperature. The bond strength increased with increasing bonding temperature and bond force. The laminates bonded for 30 and 60 min at 400 °C and 60 kN had similar bond strength and amount of cohesive fracture in the bulk silicon, while the laminates bonded for 15 min had significantly lower bond strength and amount of cohesive fracture in the bulk silicon. (paper)

  17. Bonding of Si wafers by surface activation method for the development of high efficiency high counting rate radiation detectors

    International Nuclear Information System (INIS)

    Kanno, Ikuo; Yamashita, Makoto; Onabe, Hideaki

    2006-01-01

    Si wafers with two different resistivities ranging over two orders of magnitude were bonded by the surface activation method. The resistivities of bonded Si wafers were measured as a function of annealing temperature. Using calculations based on a model, the interface resistivities of bonded Si wafers were estimated as a function of the measured resistivities of bonded Si wafers. With thermal treatment from 500degC to 900degC, all interfaces showed high resistivity, with behavior that was close to that of an insulator. Annealing at 1000degC decreased the interface resistivity and showed close to ideal bonding after thermal treatment at 1100degC. (author)

  18. Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

    Science.gov (United States)

    Kubair, D. V.; Spearing, S. M.

    2006-03-01

    Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

  19. Eutectic and solid-state wafer bonding of silicon with gold

    International Nuclear Information System (INIS)

    Abouie, Maryam; Liu, Qi; Ivey, Douglas G.

    2012-01-01

    Highlights: ► Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. ► Exchange of a-Si and Au layer was observed in both types of bonded samples. ► Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. ► Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 °C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 °C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

  20. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

  1. I-line stepper based overlay evaluation method for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2018-03-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

  2. GeSn-on-insulator substrate formed by direct wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  3. Direct Wafer Bonding and Its Application to Waveguide Optical Isolators.

    Science.gov (United States)

    Mizumoto, Tetsuya; Shoji, Yuya; Takei, Ryohei

    2012-05-24

    This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO₃. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI) waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

  4. Direct Wafer Bonding and Its Application to Waveguide Optical Isolators

    Directory of Open Access Journals (Sweden)

    Ryohei Takei

    2012-05-01

    Full Text Available This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO3. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

  5. Formation of III–V-on-insulator structures on Si by direct wafer bonding

    International Nuclear Information System (INIS)

    Yokoyama, Masafumi; Iida, Ryo; Ikku, Yuki; Kim, Sanghyeon; Takenaka, Mitsuru; Takagi, Shinichi; Takagi, Hideki; Yasuda, Tetsuji; Yamada, Hisashi; Ichikawa, Osamu; Fukuhara, Noboru; Hata, Masahiko

    2013-01-01

    We have studied the formation of III–V-compound-semiconductors-on-insulator (III–V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III–V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O 2 plasma-assisted DWB process with ECR sputtered SiO 2 BOX layers and a DWB process based on atomic-layer-deposition Al 2 O 3 (ALD-Al 2 O 3 ) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO 2 and ALD-Al 2 O 3 BOX layers are desorption of Ar and H 2 O gas, respectively. In order to suppress micro-void generation in the ECR-SiO 2 BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al 2 O 3 BOX layers to increase the deposition temperature of the ALD-Al 2 O 3 BOX layers. It is also another possible solution to deposit ALD-Al 2 O 3 BOX layers on thermally oxidized SiO 2 layers, which can absorb the desorption gas from ALD-Al 2 O 3 BOX layers. (invited paper)

  6. Nanodiamond resonators fabricated on 8″ Si substrates using adhesive wafer bonding

    Science.gov (United States)

    Lebedev, V.; Lisec, T.; Yoshikawa, T.; Reusch, M.; Iankov, D.; Giese, C.; Žukauskaitė, A.; Cimalla, V.; Ambacher, O.

    2017-06-01

    In this work, the adhesive wafer bonding of diamond thin films onto 8″ silicon substrates is reported. In order to characterize bonded nano-crystalline diamond layers, vibrometry and interferometry studies of micro-fabricated flexural beam and disk resonators were carried out. In particular, surface topology along with resonant frequencies, eigenmodes and mechanical quality factors were recorded and analyzed in order to obtain physical parameters of the transferred films. The vibration properties of the bonded resonators were compared to those fabricated directly on 3″ silicon substrates.

  7. Accurate characterization of wafer bond toughness with the double cantilever specimen

    Science.gov (United States)

    Turner, Kevin T.; Spearing, S. Mark

    2008-01-01

    The displacement loaded double cantilever test, also referred to as the "Maszara test" and the "crack opening method" by the wafer bonding community, is a common technique used to evaluate the interface toughness or surface energy of direct wafer bonds. While the specimen is widely used, there has been a persistent question as to the accuracy of the method since the actual specimen geometry differs from the ideal beam geometry assumed in the expression used for data reduction. The effect of conducting the test on whole wafer pairs, in which the arms of cantilevers are wide plates rather than slender beams, is examined in this work using finite element analysis. A model is developed to predict the equilibrium shape of the crack front and to develop a corrected expression for calculating interface toughness from crack length measurements obtained in tests conducted on whole wafer pairs. The finite element model, which is validated through comparison to experiments, demonstrates that using the traditional beam theory-based expressions for data reduction can lead to errors of up to 25%.

  8. The Evolution of Wafer Bonding Moving from the back-end further to the front-end

    Institute of Scientific and Technical Information of China (English)

    Thomas Glinsner; Peter Hangweier

    2009-01-01

    @@ 1 Introduction As the nanoscale era progresses, innovative new materials and processes continue to be developed and implemented as a means of keeping the industry on the path of Moore's Law. Wafer bonding - literally, the temporary or permanent joining of two wafers or substrates using a suitable combination of process technologies, chemicals and adhesives - is one such innovation.

  9. III-V/Si wafer bonding using transparent, conductive oxide interlayers

    Energy Technology Data Exchange (ETDEWEB)

    Tamboli, Adele C., E-mail: Adele.Tamboli@nrel.gov; Hest, Maikel F. A. M. van; Steiner, Myles A.; Essig, Stephanie; Norman, Andrew G.; Bosco, Nick; Stradins, Paul [National Center for Photovoltaics, National Renewable Energy Laboratory, 15013 Denver West Pkwy, Golden, Colorado 80401 (United States); Perl, Emmett E. [Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106-9560 (United States)

    2015-06-29

    We present a method for low temperature plasma-activated direct wafer bonding of III-V materials to Si using a transparent, conductive indium zinc oxide interlayer. The transparent, conductive oxide (TCO) layer provides excellent optical transmission as well as electrical conduction, suggesting suitability for Si/III-V hybrid devices including Si-based tandem solar cells. For bonding temperatures ranging from 100 °C to 350 °C, Ohmic behavior is observed in the sample stacks, with specific contact resistivity below 1 Ω cm{sup 2} for samples bonded at 200 °C. Optical absorption measurements show minimal parasitic light absorption, which is limited by the III-V interlayers necessary for Ohmic contact formation to TCOs. These results are promising for Ga{sub 0.5}In{sub 0.5}P/Si tandem solar cells operating at 1 sun or low concentration conditions.

  10. Fabrication of an integrated ΔE-E-silicon detector by wafer bonding using cobalt disilicide

    International Nuclear Information System (INIS)

    Thungstroem, G.; Veldhuizen, E.J. van; Westerberg, L.; Norlin, L.-O.; Petersson, C.S.

    1997-01-01

    The problem concerning mechanical stability of thin self-supporting ΔE detector in a ΔE-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The ΔE-detector has a thickness of 6.5 μm and the E detector 290 μm with an area of 24.8 mm 2 . The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.)

  11. Fabrication of an integrated {Delta}E-E-silicon detector by wafer bonding using cobalt disilicide

    Energy Technology Data Exchange (ETDEWEB)

    Thungstroem, G. [Mid-Sweden Univ., Sundsvall (Sweden). Dept. of Inf. Technol.]|[Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden); Veldhuizen, E.J. van [Uppsala University, Department of Radiation Science, Box 535, S-751 21 Uppsala (Sweden); Westerberg, L. [Uppsala University, The Svedberg Laboratory, Box 533, S-751 21 Uppsala (Sweden); Norlin, L.-O. [Royal Institute of Technology, Department of Physics, Frescativaegen 24, S-104 05 Stockholm (Sweden); Petersson, C.S. [Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden)

    1997-06-01

    The problem concerning mechanical stability of thin self-supporting {Delta}E detector in a {Delta}E-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The {Delta}E-detector has a thickness of 6.5 {mu}m and the E detector 290 {mu}m with an area of 24.8 mm{sup 2}. The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.).

  12. Integrated optical MEMS using through-wafer vias and bump-bonding.

    Energy Technology Data Exchange (ETDEWEB)

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  13. Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

    Science.gov (United States)

    Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

    2018-02-01

    We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

  14. Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies

    Science.gov (United States)

    Tanake, Katsuaki

    We fabricated a direct-bond interconnected multijunction solar cell, a two-terminal monolithic GaAs/InGaAs dual-junction cell, to demonstrate a proof-of-principle for the viability of direct wafer bonding for solar cell applications. The bonded interface is a metal-free n+GaAs/n +InP tunnel junction with highly conductive Ohmic contact suitable for solar cell applications overcoming the 4% lattice mismatch. The quantum efficiency spectrum for the bonded cell was quite similar to that for each of unbonded GaAs and InGaAs subcells. The bonded dual-junction cell open-circuit voltage was equal to the sum of the unbonded subcell open-circuit voltages, which indicates that the bonding process does not degrade the cell material quality since any generated crystal defects that act as recombination centers would reduce the open-circuit voltage. Also, the bonded interface has no significant carrier recombination rate to reduce the open circuit voltage. Engineered substrates consisting of thin films of InP on Si handle substrates (InP/Si substrates or epitaxial templates) have the potential to significantly reduce the cost and weight of compound semiconductor solar cells relative to those fabricated on bulk InP substrates. InGaAs solar cells on InP have superior performance to Ge cells at photon energies greater than 0.7 eV and the current record efficiency cell for 1 sun illumination was achieved using an InGaP/GaAs/InGaAs triple junction cell design with an InGaAs bottom cell. Thermophotovoltaic (TPV) cells from the InGaAsP-family of III-V materials grown epitaxially on InP substrates would also benefit from such an InP/Si substrate. Additionally, a proposed four-junction solar cell fabricated by joining subcells of InGaAs and InGaAsP grown on InP with subcells of GaAs and AlInGaP grown on GaAs through a wafer-bonded interconnect would enable the independent selection of the subcell band gaps from well developed materials grown on lattice matched substrates. Substitution of

  15. Investigation of Surface Pre-Treatment Methods for Wafer-Level Cu-Cu Thermo-Compression Bonding

    Directory of Open Access Journals (Sweden)

    Koki Tanaka

    2016-12-01

    Full Text Available To increase the yield of the wafer-level Cu-Cu thermo-compression bonding method, certain surface pre-treatment methods for Cu are studied which can be exposed to the atmosphere before bonding. To inhibit re-oxidation under atmospheric conditions, the reduced pure Cu surface is treated by H2/Ar plasma, NH3 plasma and thiol solution, respectively, and is covered by Cu hydride, Cu nitride and a self-assembled monolayer (SAM accordingly. A pair of the treated wafers is then bonded by the thermo-compression bonding method, and evaluated by the tensile test. Results show that the bond strengths of the wafers treated by NH3 plasma and SAM are not sufficient due to the remaining surface protection layers such as Cu nitride and SAMs resulting from the pre-treatment. In contrast, the H2/Ar plasma–treated wafer showed the same strength as the one with formic acid vapor treatment, even when exposed to the atmosphere for 30 min. In the thermal desorption spectroscopy (TDS measurement of the H2/Ar plasma–treated Cu sample, the total number of the detected H2 was 3.1 times more than the citric acid–treated one. Results of the TDS measurement indicate that the modified Cu surface is terminated by chemisorbed hydrogen atoms, which leads to high bonding strength.

  16. Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

    Science.gov (United States)

    Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

    2005-01-01

    Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

  17. Development of a classical force field for the oxidized Si surface: application to hydrophilic wafer bonding.

    Science.gov (United States)

    Cole, Daniel J; Payne, Mike C; Csányi, Gábor; Spearing, S Mark; Colombi Ciacchi, Lucio

    2007-11-28

    We have developed a classical two- and three-body interaction potential to simulate the hydroxylated, natively oxidized Si surface in contact with water solutions, based on the combination and extension of the Stillinger-Weber potential and of a potential originally developed to simulate SiO(2) polymorphs. The potential parameters are chosen to reproduce the structure, charge distribution, tensile surface stress, and interactions with single water molecules of a natively oxidized Si surface model previously obtained by means of accurate density functional theory simulations. We have applied the potential to the case of hydrophilic silicon wafer bonding at room temperature, revealing maximum room temperature work of adhesion values for natively oxidized and amorphous silica surfaces of 97 and 90 mJm(2), respectively, at a water adsorption coverage of approximately 1 ML. The difference arises from the stronger interaction of the natively oxidized surface with liquid water, resulting in a higher heat of immersion (203 vs 166 mJm(2)), and may be explained in terms of the more pronounced water structuring close to the surface in alternating layers of larger and smaller densities with respect to the liquid bulk. The computed force-displacement bonding curves may be a useful input for cohesive zone models where both the topographic details of the surfaces and the dependence of the attractive force on the initial surface separation and wetting can be taken into account.

  18. Wafer-level packaging with compression-controlled seal ring bonding

    Science.gov (United States)

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  19. Wafer-level hermetic thermo-compression bonding using electroplated gold sealing frame planarized by fly-cutting

    Science.gov (United States)

    Farisi, Muhammad Salman Al; Hirano, Hideki; Frömel, Jörg; Tanaka, Shuji

    2017-01-01

    In this paper, a novel wafer-level hermetic packaging technology for heterogeneous device integration is presented. Hermetic sealing is achieved by low-temperature thermo-compression bonding using electroplated Au micro-sealing frame planarized by single-point diamond fly-cutting. The proposed technology has significant advantages compared to other established processes in terms of integration of micro-structured wafer, vacuum encapsulation and electrical interconnection, which can be achieved at the same time. Furthermore, the technology is also achievable for a bonding frame width as narrow as 30 μm, giving it an advantage from a geometry perspective, and bonding temperatures as low as 300 °C, making it advantageous for temperature-sensitive devices. Outgassing in vacuum sealed cavities is studied and a cavity pressure below 500 Pa is achieved by introducing annealing steps prior to bonding. The pressure of the sealed cavity is measured by zero-balance method utilizing diaphragm-structured bonding test devices. The leak rate into the packages is determined by long-term sealed cavity pressure measurement for 1500 h to be less than 2.0× {{10}-14} Pa m3s-1. In addition, the bonding shear strength is also evaluated to be higher than 100 MPa.

  20. Determination of wafer bonding mechanisms for plasma activated SiN films with x-ray reflectivity

    Energy Technology Data Exchange (ETDEWEB)

    Hayashi, S [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States); Sandhu, R [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States); Wojtowicz, M [Northrop Grumman Space Technology, Redondo Beach, CA 90278 (United States); Sun, Y [Department of Chemical Engineering, University of California, Los Angeles, CA 90095 (United States); Hicks, R [Department of Chemical Engineering, University of California, Los Angeles, CA 90095 (United States); Goorsky, M S [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States)

    2005-05-21

    Specular and diffuse x-ray reflectivity measurements were employed for wafer bonding studies of surface and interfacial reactions in {approx}800 A thick SiN films deposited on III-V substrates. CuK{sub {alpha}}{sub 1} radiation was employed for these measurements. The as-deposited films show very low surface roughness and uniform, high density SiN. Reflectivity measurements show that an oxygen plasma treatment converts the nitride surface to a somewhat porous SiO{sub x} layer (67 A thick, at 80% of SiO{sub 2} density), with confirmation of the oxide formation from x-ray photoelectron spectroscopy. Reactions at the bonded interface of two oxygen plasma treated SiN layers were examined using a bonded structure from which one of the III-V wafers is removed. Reflectivity measurements of bonded structures annealed at 150 deg. C and 300 deg. C show an increase in the SiO{sub x} layer density and thickness and even a density gradient across this interface. The increase in density is correlated with an increase in bond strength, where after the 300 deg. C anneal, a high interfacial bond strength, exceeding the bulk strength, was achieved.

  1. Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

    Science.gov (United States)

    Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

    2018-03-01

    A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

  2. A hand-held row-column addressed CMUT probe with integrated electronics for volumetric imaging

    DEFF Research Database (Denmark)

    Engholm, Mathias; Christiansen, Thomas Lehrmann; Beers, Christopher

    2015-01-01

    A 3 MHz, λ / 2-pitch 62+62 channel row-column addressed 2-D CMUT array designed to be mounted in a probe handle and connected to a commercial BK Medical scanner for real-time volumetric imaging is presented. It is mounted and wire-bonded on a flexible PCB, which is connected to two rigid PCBs...

  3. A full-wafer fabrication process for glass microfluidic chips with integrated electroplated electrodes by direct bonding of dry film resist

    International Nuclear Information System (INIS)

    Vulto, Paul; Urban, G A; Huesgen, Till; Albrecht, Björn

    2009-01-01

    A full-wafer process is presented for fast and simple fabrication of glass microfluidic chips with integrated electroplated electrodes. The process employs the permanent dry film resist (DFR) Ordyl SY300 to create microfluidic channels, followed by electroplating of silver and subsequent chlorination. The dry film resist is bonded directly to a second substrate, without intermediate gluing layers, only by applying pressure and moderate heating. The process of microfluidic channel fabrication, electroplating and wafer bonding can be completed within 1 day, thus making it one of the fastest and simplest full-wafer fabrication processes. (note)

  4. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Directory of Open Access Journals (Sweden)

    N. Daix

    2014-08-01

    Full Text Available We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  5. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Energy Technology Data Exchange (ETDEWEB)

    Daix, N., E-mail: dai@zurich.ibm.com; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J. [IBM Research - Zürich, Säumerstrasse 4, CH-8803 Rüschlikon (Switzerland); Hartmann, J. M. [CEA, LETI 17, rue des Martyrs, F-38054 Grenoble (France); Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D. [IBM T. J. Watson Research Center, 1101 Kitchawan Rd., Route 134 Yorktown Heights, New York 10598 (United States)

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  6. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Science.gov (United States)

    Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  7. Wafer-level integration of NiTi shape memory alloy on silicon using Au–Si eutectic bonding

    International Nuclear Information System (INIS)

    Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; Van der Wijngaart, Wouter

    2013-01-01

    This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au–Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more than 1 μm thickness before bonding gives the most promising results. Through patterning of the SMA sheet and by limiting bonding to small areas, stresses created by the thermal mismatch between Si and NiTi are reduced. With a gold layer of 1 μm thickness and bond areas between 200 × 200 and 800 × 800 μm 2 a high bond strength and a yield above 90% is demonstrated. (paper)

  8. Fabrication process for CMUT arrays with polysilicon electrodes, nanometre precision cavity gaps and through-silicon vias

    International Nuclear Information System (INIS)

    Due-Hansen, J; Poppe, E; Summanwar, A; Jensen, G U; Breivik, L; Wang, D T; Schjølberg-Henriksen, K; Midtbø, K

    2012-01-01

    Capacitive micromachined ultrasound transducers (CMUTs) can be used to realize miniature ultrasound probes. Through-silicon vias (TSVs) allow for close integration of the CMUT and read-out electronics. A fabrication process enabling the realization of a CMUT array with TSVs is being developed. The integrated process requires the formation of highly doped polysilicon electrodes with low surface roughness. A process for polysilicon film deposition, doping, CMP, RIE and thermal annealing that resulted in a film with sheet resistance of 4.0 Ω/□ and a surface roughness of 1 nm rms has been developed. The surface roughness of the polysilicon film was found to increase with higher phosphorus concentrations. The surface roughness also increased when oxygen was present in the thermal annealing ambient. The RIE process for etching CMUT cavities in the doped polysilicon gave a mean etch depth of 59.2 ± 3.9 nm and a uniformity across the wafer ranging from 1.0 to 4.7%. The two presented processes are key processes that enable the fabrication of CMUT arrays suitable for applications in for instance intravascular cardiology and gastrointestinal imaging. (paper)

  9. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Xianshu eLuo

    2015-04-01

    Full Text Available Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP laser, lateral-coupled distributed feedback (LC-DFB laser with side wall grating, and mode-locked laser (MLL. From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC.

  10. New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2017-06-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

  11. Investigation of room-temperature wafer bonded GaInP/GaAs/InGaAsP triple-junction solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Yang, Wen-xian; Dai, Pan; Ji, Lian; Tan, Ming; Wu, Yuan-yuan [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China); Uchida, Shiro [Department of Mechanical Science and Engineering Faculty of Engineering, Chiba Institute of Technology, 2-17-1, Tsudanuma, Narashino, Chiba 275-0016 (Japan); Lu, Shu-long, E-mail: sllu2008@sinano.ac.cn [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China); Yang, Hui [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China)

    2016-12-15

    Highlights: • High quality InGaAsP material with a bandgap of 1.0 eV was grown by MBE. • Room-temperature wafer-bonded GaInP/GaAs/InGaAsP SCs were fabricated. • An efficiency of 30.3% of wafer-bonded triple-junction SCs was obtained. - Abstract: We report on the fabrication of III–V compound semiconductor multi-junction solar cells using the room-temperature wafer bonding technique. GaInP/GaAs dual-junction solar cells on GaAs substrate and InGaAsP single junction solar cell on InP substrate were separately grown by all-solid state molecular beam epitaxy (MBE). The two cells were then bonded to a triple-junction solar cell at room-temperature. A conversion efficiency of 30.3% of GaInP/GaAs/InGaAsP wafer-bonded solar cell was obtained at 1-sun condition under the AM1.5G solar simulator. The result suggests that the room-temperature wafer bonding technique and MBE technique have a great potential to improve the performance of multi-junction solar cell.

  12. Hysteresis-free high-temperature precise bimorph actuators produced by direct bonding of lithium niobate wafers

    Energy Technology Data Exchange (ETDEWEB)

    Shur, V. Ya.; Baturin, I. S.; Mingaliev, E. A.; Zorikhin, D. V.; Udalov, A. R.; Greshnyakov, E. D. [Ferroelectric Laboratory, Institute of Natural Sciences, Ural Federal University, 51 Lenin Ave., 620000 Ekaterinburg (Russian Federation)

    2015-02-02

    The current paper presents a piezoelectric bimorph actuator produced by direct bonding of lithium niobate wafers with the mirrored Y and Z axes. Direct bonding technology allowed to fabricate bidomain plate with precise positioning of ideally flat domain boundary. By optimizing the cutting angle (128° Y-cut), the piezoelectric constant became as large as 27.3 pC/N. Investigation of voltage dependence of bending displacement confirmed that bimorph actuator has excellent linearity and hysteresis-free. Decrease of the applied voltage down to mV range showed the perfect linearity up to the sub-nm deflection amplitude. The frequency and temperature dependences of electromechanical transmission coefficient in wide temperature range (from 300 to 900 K) were investigated.

  13. Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

    Science.gov (United States)

    Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

    2018-05-01

    Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

  14. Wafer-level hermetic vacuum packaging by bonding with a copper-tin thin film sealing ring

    Science.gov (United States)

    Akashi, Teruhisa; Funabashi, Hirofumi; Takagi, Hideki; Omura, Yoshiteru; Hata, Yoshiyuki

    2018-04-01

    A wafer-level hermetic vacuum packaging technology intended for use with MEMS devices was developed based on a copper-tin (CuSn) thin film sealing ring. To allow hermetic packaging, the shear strength of the CuSn thin film bond was improved by optimizing the pretreatment conditions. As a result, an average shear strength of 72.3 MPa was obtained and a cavity that had been hermetically sealed using wafer-level packaging (WLP) maintained its vacuum for 1.84 years. The total pressures in the cavities and the partial pressures of residual gases were directly determined with an ultra-low outgassing residual gas analyzer (RGA) system. Hermeticity was evaluated based on helium leak rates, which were calculated from helium pressures determined with the RGA system. The resulting data showed that a vacuum cavity following 1.84 years storage had a total pressure of 83.1 Pa, contained argon as the main residual gas and exhibited a helium leak rate as low as 1.67  ×  10-17 Pa · m3 s-1, corresponding to an air leak rate of 6.19  ×  10-18 Pa · m3 s-1. The RGA data demonstrate that WLP using a CuSn thin film sealing ring permits ultra-high hermeticity in conjunction with long-term vacuum packaging that is applicable to MEMS devices.

  15. A comparison of buried oxide characteristics of single and multiple implant SIMOX and bond and etch back wafers

    International Nuclear Information System (INIS)

    Annamalai, N.K.; Bockman, J.F.; McGruer, N.E.; Chapski, J.

    1990-01-01

    The current through the buried oxides of single and multiple implant SIMOX and bond and etch back silicon-on-insulator (BESOI) wafers were measured as a function of radiation dose. From these measurements, conductivity and static capacitances were derived. High frequency capacitances were also measured. Leakage current through the buried oxide of multiple implant SIMOX is considerably less than that of single implant SIMOX (more than an order of magnitude). High frequency and static capacitances, as a function of total dose, were used to study the buried oxide---top silicon interface and the buried oxide---bottom silicon interface. Multiple implant had fewer interface traps than single implant at pre-rad and after irradiation

  16. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    International Nuclear Information System (INIS)

    Bronuzzi, J.; Mapelli, A.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations.

  17. Nature of bonding forces between two hydrogen-passivated silicon wafers

    DEFF Research Database (Denmark)

    Stokbro, Kurt; Nielsen, E.; Hult, E.

    1998-01-01

    The nature and strength of the bonding forces between two II-passivated Si surfaces are studied with the density-functional theory, using an approach based on recent theoretical advances in understanding of van der Waals forces between two surfaces. Contrary to previous suggestions of van der Waals...

  18. Dimensional Scaling for Optimized CMUT Operations

    DEFF Research Database (Denmark)

    Lei, Anders; Diederichsen, Søren Elmin; la Cour, Mette Funding

    2014-01-01

    This work presents a dimensional scaling study using numerical simulations, where gap height and plate thickness of a CMUT cell is varied, while the lateral plate dimension is adjusted to maintain a constant transmit immersion center frequency of 5 MHz. Two cell configurations have been simulated...

  19. Material size effects on crack growth along patterned wafer-level Cu–Cu bonds

    DEFF Research Database (Denmark)

    Tvergaard, Viggo; Niordson, Christian Frithiof; Hutchinson, John W.

    2013-01-01

    together. Crack growth along the bond interface is here studied numerically using finite element analyses. The experiments have shown that plasticity in the Cu films makes a major contribution to the macroscopic interface toughness. To account for the size dependence of the plastic flow a strain gradient...... plasticity model is applied here for the metal. A cohesive zone model is applied to represent the crack growth along the bond between the two Cu films. This cohesive zone model incorporates the effect of higher order stresses in the continuum, such that the higher order tractions on the crack faces decay...... the toughness peak and the subsequent plateau level are highly sensitive to the value of the characteristic material length. A small material length, relative to the thickness of the Cu film, gives high toughness whereas a length comparable to the film thickness gives much reduced crack growth resistance...

  20. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    CERN Document Server

    Bronuzzi, J.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

  1. Eutectic-based wafer-level-packaging technique for piezoresistive MEMS accelerometers and bond characterization using molecular dynamics simulations

    Science.gov (United States)

    Aono, T.; Kazama, A.; Okada, R.; Iwasaki, T.; Isono, Y.

    2018-03-01

    We developed a eutectic-based wafer-level-packaging (WLP) technique for piezoresistive micro-electromechanical systems (MEMS) accelerometers on the basis of molecular dynamics analyses and shear tests of WLP accelerometers. The bonding conditions were experimentally and analytically determined to realize a high shear strength without solder material atoms diffusing to adhesion layers. Molecular dynamics (MD) simulations and energy dispersive x-ray (EDX) spectrometry done after the shear tests clarified the eutectic reaction of the solder materials used in this research. Energy relaxation calculations in MD showed that the diffusion of solder material atoms into the adhesive layer was promoted at a higher temperature. Tensile creep MD simulations also suggested that the local potential energy in a solder material model determined the fracture points of the model. These numerical results were supported by the shear tests and EDX analyses for WLP accelerometers. Consequently, a bonding load of 9.8 kN and temperature of 300 °C were found to be rational conditions because the shear strength was sufficient to endure the polishing process after the WLP process and there was little diffusion of solder material atoms to the adhesion layer. Also, eutectic-bonding-based WLP was effective for controlling the attenuation of the accelerometers by determining the thickness of electroplated solder materials that played the role of a cavity between the accelerometers and lids. If the gap distance between the two was less than 6.2 µm, the signal gains for x- and z-axis acceleration were less than 20 dB even at the resonance frequency due to air-damping.

  2. High-κ Al{sub 2}O{sub 3} material in low temperature wafer-level bonding for 3D integration application

    Energy Technology Data Exchange (ETDEWEB)

    Fan, J., E-mail: fanji@hust.edu.cn; Tu, L. C. [MOE Key Laboratory of Fundamental Physical Quantities Measurement, School of Physics, Huazhong University of Science and Technology, Wuhan 430074 (China); Tan, C. S. [School of Electrical and Electronics Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2014-03-15

    This work systematically investigated a high-κ Al{sub 2}O{sub 3} material for low temperature wafer-level bonding for potential applications in 3D microsystems. A clean Si wafer with an Al{sub 2}O{sub 3} layer thickness of 50 nm was applied as our experimental approach. Bonding was initiated in a clean room ambient after surface activation, followed by annealing under inert ambient conditions at 300 °C for 3 h. The investigation consisted of three parts: a mechanical support study using the four-point bending method, hermeticity measurements using the helium bomb test, and thermal conductivity analysis for potential heterogeneous bonding. Compared with samples bonded using a conventional oxide bonding material (SiO{sub 2}), a higher interfacial adhesion energy (∼11.93 J/m{sup 2}) and a lower helium leak rate (∼6.84 × 10{sup −10} atm.cm{sup 3}/sec) were detected for samples bonded using Al{sub 2}O{sub 3}. More importantly, due to the excellent thermal conductivity performance of Al{sub 2}O{sub 3}, this technology can be used in heterogeneous direct bonding, which has potential applications for enhancing the performance of Si photonic integrated devices.

  3. Barrier reduction via implementation of InGaN interlayer in wafer-bonded current aperture vertical electron transistors consisting of InGaAs channel and N-polar GaN drain

    International Nuclear Information System (INIS)

    Kim, Jeonghee; Laurent, Matthew A.; Li, Haoran; Lal, Shalini; Mishra, Umesh K.

    2015-01-01

    This letter reports the influence of the added InGaN interlayer on reducing the inherent interfacial barrier and hence improving the electrical characteristics of wafer-bonded current aperture vertical electron transistors consisting of an InGaAs channel and N-polar GaN drain. The current-voltage characteristics of the transistors show that the implementation of N-polar InGaN interlayer effectively reduces the barrier to electron transport across the wafer-bonded interface most likely due to its polarization induced downward band bending, which increases the electron tunneling probability. Fully functional wafer-bonded transistors with nearly 600 mA/mm of drain current at V GS  = 0 V and L go  = 2 μm have been achieved, and thus demonstrate the feasibility of using wafer-bonded heterostructures for applications that require active carrier transport through both materials

  4. Modelling of CMUTs with Anisotropic Plates

    DEFF Research Database (Denmark)

    la Cour, Mette Funding; Christiansen, Thomas Lehrmann; Jensen, Jørgen Arendt

    2012-01-01

    Traditionally, CMUTs are modelled using the isotropic plate equation and this leads to deviations between analytical calculations and FEM simulations. In this paper, the deflection profile and material parameters are calculated using the anisotropic plate equation. It is shown that the anisotropic...... calculations match perfectly with FEM while an isotropic approach causes up to 10% deviations in deflection profile. Furthermore, we show how commonly used analytic modelling methods such as static calculations of the pull-in voltage and dynamic modelling through an equivalent circuit representation can...

  5. 1.3 μm wavelength vertical cavity surface emitting laser fabricated by orientation-mismatched wafer bonding: A prospect for polarization control

    Science.gov (United States)

    Okuno, Yae L.; Geske, Jon; Gan, Kian-Giap; Chiu, Yi-Jen; DenBaars, Steven P.; Bowers, John E.

    2003-04-01

    We propose and demonstrate a long-wavelength vertical cavity surface emitting laser (VCSEL) which consists of a (311)B InP-based active region and (100) GaAs-based distributed Bragg reflectors (DBRs), with an aim to control the in-plane polarization of output power. Crystal growth on (311)B InP substrates was performed under low-migration conditions to achieve good crystalline quality. The VCSEL was fabricated by wafer bonding, which enables us to combine different materials regardless of their lattice and orientation mismatch without degrading their quality. The VCSEL was polarized with a power extinction ratio of 31 dB.

  6. Aberration-corrected transmission electron microscopy analyses of GaAs/Si interfaces in wafer-bonded multi-junction solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Häussler, Dietrich [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany); Houben, Lothar [Ernst Ruska-Centre for Microscopy and Spectroscopy with Electrons, Research Centre Juelich GmbH, 52425 Juelich (Germany); Essig, Stephanie [Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg (Germany); Kurttepeli, Mert [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany); Dimroth, Frank [Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg (Germany); Dunin-Borkowski, Rafal E. [Ernst Ruska-Centre for Microscopy and Spectroscopy with Electrons, Research Centre Juelich GmbH, 52425 Juelich (Germany); Jäger, Wolfgang, E-mail: wolfgang.jaeger@tf.uni-kiel.de [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany)

    2013-11-15

    Aberration-corrected scanning transmission electron microscopy (STEM) and electron energy loss spectroscopy (EELS) investigations have been applied to investigate the structure and composition fluctuations near interfaces in wafer-bonded multi-junction solar cells. Multi-junction solar cells are of particular interest since efficiencies well above 40% have been obtained for concentrator solar cells which are based on III-V compound semiconductors. In this methodologically oriented investigation, we explore the potential of combining aberration-corrected high-angle annular dark-field STEM imaging (HAADF-STEM) with spectroscopic techniques, such as EELS and energy-dispersive X-ray spectroscopy (EDXS), and with high-resolution transmission electron microscopy (HR-TEM), in order to analyze the effects of fast atom beam (FAB) and ion beam bombardment (IB) activation treatments on the structure and composition of bonding interfaces of wafer-bonded solar cells on Si substrates. Investigations using STEM/EELS are able to measure quantitatively and with high precision the widths and the fluctuations in element distributions within amorphous interface layers of nanometer extensions, including those of light elements. Such measurements allow the control of the activation treatments and thus support assessing electrical conductivity phenomena connected with impurity and dopant distributions near interfaces for optimized performance of the solar cells. - Highlights: • Aberration-corrected TEM and EELS reveal structural and elemental profiles across GaAs/Si bond interfaces in wafer-bonded GaInP/GaAs/Si - multi-junction solar cells. • Fluctuations in elemental concentration in nanometer-thick amorphous interface layers, including the disrubutions of light elements, are measured using EELS. • The projected widths of the interface layers are determined on the atomic scale from STEM-HAADF measurements. • The effects of atom and ion beam activation treatment on the bonding

  7. Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

    Science.gov (United States)

    Egelkrout, D. W.

    1981-01-01

    Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

  8. High-density plasma-induced etch damage of wafer-bonded AlGaInP/mirror/Si light-emitting diodes

    CERN Document Server

    Wuu, D S; Huang, S H; Chung, C R

    2002-01-01

    Dry etch of wafer-bonded AlGaInP/mirror/Si light-emitting diodes (LEDs) with planar electrodes was performed by high-density plasma using an inductively coupled plasma (ICP) etcher. The etching characteristics were investigated by varying process parameters such as Cl sub 2 /N sub 2 gas combination, chamber pressure, ICP power and substrate-bias power. The corresponding plasma properties (ion flux and dc bias), in situ measured by a Langmuir probe, show a strong relationship to the etch results. With a moderate etch rate of 1.3 mu m/min, a near vertical and smooth sidewall profile can be achieved under a Cl sub 2 /(Cl sub 2 +N sub 2) gas mixture of 0.5, ICP power of 800 W, substrate-bias power of 100 W, and chamber pressure of 0.67 Pa. Quantitative analysis of the plasma-induced damage was attempted to provide a means to study the mechanism of leakage current and brightness with various dc bias voltages (-110 to -328 V) and plasma duration (3-5 min) on the wafer-bonded LEDs. It is found that the reverse leaka...

  9. Temperature-dependent interface characteristic of silicon wafer bonding based on an amorphous germanium layer deposited by DC-magnetron sputtering

    Science.gov (United States)

    Ke, Shaoying; Lin, Shaoming; Ye, Yujie; Mao, Danfeng; Huang, Wei; Xu, Jianfang; Li, Cheng; Chen, Songyan

    2018-03-01

    We report a near-bubble-free low-temperature silicon (Si) wafer bonding with a thin amorphous Ge (a-Ge) intermediate layer. The DC-magnetron-sputtered a-Ge film on Si is demonstrated to be extremely flat (RMS = 0.28 nm) and hydrophilic (contact angle = 3°). The effect of the post-annealing temperature on the surface morphology and crystallinity of a-Ge film at the bonded interface is systematically identified. The relationship among the bubble density, annealing temperature, and crystallinity of a-Ge film is also clearly clarified. The crystallization of a-Ge film firstly appears at the bubble region. More interesting feature is that the crystallization starts from the center of the bubbles and sprawls to the bubble edge gradually. The H2 by-product is finally absorbed by intermediate Ge layer with crystalline phase after post annealing. Moreover, the whole a-Ge film out of the bubble totally crystallizes when the annealing time increases. This Ge integration at the bubble region leads to the decrease of the bubble density, which in turn increases the bonding strength.

  10. Integrated differential high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Farch, Kjartan

    2015-01-01

    In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order...... to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption...

  11. Combined Colorimetric and Gravimetric CMUT Sensor for Detection of Phenylacetone

    DEFF Research Database (Denmark)

    Mølgaard, Mathias Johannes Grøndahl; Laustsen, Milan; Thygesen, Ida Lysgaard

    2017-01-01

    The detection of phenylacetone is of interest as it is a common precursor for the synthesis of (meth)amphetamine. Resonant gravimetric sensors can be used to detect the mass and hereby the concentration of a gas while colorimetric arrays typically have an exceptional selectivity to the target...... analyte if the right colorimetric dyes are chosen. We present a sensor system consisting of a Capacitive Micromachined Ultrasonic Transducer (CMUT) and a colorimetric array for detection of phenylacetone. The CMUT is used as a resonant gravimetric gas sensor where the resonance frequency shift due to mass...

  12. Integrated Reconfigurable High-Voltage Transmitting Circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2014-01-01

    -out and measurements are performed on the integrated circuit. The transmitting circuit is reconfigurable externally making it able to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes, pulse voltages up to 100 V, maximum pulse range of 50 V and frequencies up to 5 MHz. The area...

  13. Investigation of PDMS as coating on CMUTs for Imaging

    DEFF Research Database (Denmark)

    la Cour, Mette Funding; Stuart, Matthias Bo; Laursen, Mads Bjerregaard

    2014-01-01

    A protective layer is necessary for Capacitive Mi- cromachined Ultrasonic Transducers (CMUTs) to be used for imaging purpose. The layer should both protect the device itself and the patient while maintaining the performance of the device. In this work Sylgard 170 PDMS is tested as coating material...... for CMUTs through comparison of transmit pressure and receive sensitivity in immersion of coated and uncoated elements. It is seen that the transmitted pressure decreases with 27% and the receive sensitivity decreases 35 % when applying the coating using a dam and fill principle. This matches well...... with the estimated value of 31 %. With the coating, the center frequency was found to be decreased from 4.5 MHz to 4.1 MHz and the fractional bandwidth was increased from 77 % to 84 % in transmit. In receive the center frequency was found to decrease from 4.4 MHz to 3.9 MHz and the fractional bandwidth was decreased...

  14. Integrated reconfigurable high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2015-01-01

    In this paper a high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in scanners for medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The transmitting circuit is reconfigurable externally making it able...... to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes with voltages up to 100 V, maximum pulse range of 50 V, frequencies up to 5 MHz and different driving slew rates. Measurements are performed on the circuit in order to assess its functionality and power consumption...... performance. The design occupies an on-chip area of 0.938 mm2 and the power consumption of a 128-element transmitting circuit array that would be used in an portable ultrasound scanner is found to be a maximum of 181 mW....

  15. Modeling of CMUTs with Multiple Anisotropic Layers and Residual Stress

    DEFF Research Database (Denmark)

    Engholm, Mathias; Thomsen, Erik Vilain

    2014-01-01

    Usually the analytical approach for modeling CMUTs uses the single layer plate equation to obtain the deflection and does not take anisotropy and residual stress into account. A highly accurate model is developed for analytical characterization of CMUTs taking an arbitrary number of layers...... and residual stress into account. Based on the stress-strain relation of each layer and balancing stress resultants and bending moments, a general multilayered anisotropic plate equation is developed for plates with an arbitrary number of layers. The exact deflection profile is calculated for a circular...... clamped plate of anisotropic materials with residual bi-axial stress. From the deflection shape the critical stress for buckling is calculated and by using the Rayleigh-Ritz method the natural frequency is estimated....

  16. Wafer level packaging of MEMS

    International Nuclear Information System (INIS)

    Esashi, Masayoshi

    2008-01-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

  17. Volumetric Real-Time Imaging Using a CMUT Ring Array

    OpenAIRE

    Choe, Jung Woo; Oralkan, Ömer; Nikoozadeh, Amin; Gencel, Mustafa; Stephens, Douglas N.; O’Donnell, Matthew; Sahn, David J.; Khuri-Yakub, Butrus T.

    2012-01-01

    A ring array provides a very suitable geometry for forward-looking volumetric intracardiac and intravascular ultrasound imaging. We fabricated an annular 64-element capacitive micromachined ultrasonic transducer (CMUT) array featuring a 10-MHz operating frequency and a 1.27-mm outer radius. A custom software suite was developed to run on a PC-based imaging system for real-time imaging using this device.

  18. Bondability of processed glass wafers

    NARCIS (Netherlands)

    Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

    1999-01-01

    The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

  19. Output pressure and harmonic characteristics of a CMUT as function of bias and excitation voltage

    DEFF Research Database (Denmark)

    Lei, Anders; Diederichsen, Søren Elmin; Hansen, Sebastian Molbech

    2015-01-01

    of the transmitted signal. The generation of intrinsic harmonics by the CMUT can be minimized by decreasing the excitation signal. This, however, leads to lower fundamental pressure which limits the desired generation of harmonics in the medium. This work examines the output pressure and harmonic characteristics...... of a CMUT as function of bias and excitation voltage. The harmonic to fundamental ratio of the surface pressures declines for decreasing excitation voltage and increasing bias voltage. The ratio, however, becomes unchanged for bias levels close to the pull-in voltage. The harmonic limitations of the CMUT...

  20. Miniaturized Ultrasound Imaging Probes Enabled by CMUT Arrays with Integrated Frontend Electronic Circuits

    Science.gov (United States)

    Khuri-Yakub, B. (Pierre) T.; Oralkan, Ömer; Nikoozadeh, Amin; Wygant, Ira O.; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N.; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O’Donnell, Matthew; Truong, Uyen; Sahn, David J.

    2010-01-01

    Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics. PMID:21097106

  1. Volumetric real-time imaging using a CMUT ring array.

    Science.gov (United States)

    Choe, Jung Woo; Oralkan, Ömer; Nikoozadeh, Amin; Gencel, Mustafa; Stephens, Douglas N; O'Donnell, Matthew; Sahn, David J; Khuri-Yakub, Butrus T

    2012-06-01

    A ring array provides a very suitable geometry for forward-looking volumetric intracardiac and intravascular ultrasound imaging. We fabricated an annular 64-element capacitive micromachined ultrasonic transducer (CMUT) array featuring a 10-MHz operating frequency and a 1.27-mm outer radius. A custom software suite was developed to run on a PC-based imaging system for real-time imaging using this device. This paper presents simulated and experimental imaging results for the described CMUT ring array. Three different imaging methods--flash, classic phased array (CPA), and synthetic phased array (SPA)--were used in the study. For SPA imaging, two techniques to improve the image quality--Hadamard coding and aperture weighting--were also applied. The results show that SPA with Hadamard coding and aperture weighting is a good option for ring-array imaging. Compared with CPA, it achieves better image resolution and comparable signal-to-noise ratio at a much faster image acquisition rate. Using this method, a fast frame rate of up to 463 volumes per second is achievable if limited only by the ultrasound time of flight; with the described system we reconstructed three cross-sectional images in real-time at 10 frames per second, which was limited by the computation time in synthetic beamforming.

  2. Quantitative comparison of PZT and CMUT probes for photoacoustic imaging: Experimental validation.

    Science.gov (United States)

    Vallet, Maëva; Varray, François; Boutet, Jérôme; Dinten, Jean-Marc; Caliano, Giosuè; Savoia, Alessandro Stuart; Vray, Didier

    2017-12-01

    Photoacoustic (PA) signals are short ultrasound (US) pulses typically characterized by a single-cycle shape, often referred to as N-shape. The spectral content of such wideband signals ranges from a few hundred kilohertz to several tens of megahertz. Typical reception frequency responses of classical piezoelectric US imaging transducers, based on PZT technology, are not sufficiently broadband to fully preserve the entire information contained in PA signals, which are then filtered, thus limiting PA imaging performance. Capacitive micromachined ultrasonic transducers (CMUT) are rapidly emerging as a valid alternative to conventional PZT transducers in several medical ultrasound imaging applications. As compared to PZT transducers, CMUTs exhibit both higher sensitivity and significantly broader frequency response in reception, making their use attractive in PA imaging applications. This paper explores the advantages of the CMUT larger bandwidth in PA imaging by carrying out an experimental comparative study using various CMUT and PZT probes from different research laboratories and manufacturers. PA acquisitions are performed on a suture wire and on several home-made bimodal phantoms with both PZT and CMUT probes. Three criteria, based on the evaluation of pure receive impulse response, signal-to-noise ratio (SNR) and contrast-to-noise ratio (CNR) respectively, have been used for a quantitative comparison of imaging results. The measured fractional bandwidths of the CMUT arrays are larger compared to PZT probes. Moreover, both SNR and CNR are enhanced by at least 6 dB with CMUT technology. This work highlights the potential of CMUT technology for PA imaging through qualitative and quantitative parameters.

  3. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    Science.gov (United States)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  4. A fluid-coupled transmitting CMUT operated in collapse mode : Semi-analytic modeling and experiments

    NARCIS (Netherlands)

    Pekař, Martin; van Nispen, Stephan H.M.; Fey, Rob H.B.; Shulepov, Sergei; Mihajlović, Nenad; Nijmeijer, Henk

    2017-01-01

    An electro-mechanical, semi-analytic, reduced-order (RO) model of a fluid-loaded transmitting capacitive-micromachined ultrasound transducer (CMUT) operated in collapse mode is developed. Simulation of static deflections, approximated by a linear combination of six mode shapes, are benchmarked

  5. Application of the O-lattice theory for the reconstruction of the high-angle near 90° tilt Si(1 1 0)/(0 0 1) boundary created by wafer bonding

    International Nuclear Information System (INIS)

    Cherkashin, N.; Kononchuk, O.; Reboh, S.; Hÿtch, M.

    2012-01-01

    This work presents an experimental and theoretical identification of defects and morphologies of a high-angle near-90° tilt Si (1 ¯ 10)//(001) boundary created by direct wafer bonding. Two samples with different twist misorientations, between the (1 ¯ 10) layer and the (0 0 1) substrate, were studied using conventional transmission electron microscopy (TEM) and geometric phase analysis of high-resolution TEM images. The O-lattice theory was used for atom reconstruction of the interface along the [11 ¯ 0] sub //[001] lay direction. It is demonstrated that to preserve covalent bonding across the interface, it should consist of {11 ¯ 1} sub,lay //{1 ¯ 12} lay,sub facets intersected by maximum of six {11 ¯ 1} lay,sub planes with three 90° Shockley dislocations per facet. It is shown that a particular atom reconstruction is needed at transition points from one facet to another. The presence or absence of deviation from exact 90° tilt of the layer with respect to the substrate is shown to be related directly to the undulations of the interface. It is demonstrated that the latter has an influence on the Burgers vector of the dislocations adjusting in-plane twist misorientation. A general model for cubic face-centered materials for an arbitrary 〈1 1 0〉 sub,lay tilt interface is proposed, which predicts the net Burgers vector and the spacing between dislocations necessary to realize transition from the lattice of the substrate (layer) to the layer (substrate).

  6. Output Pressure and Pulse-Echo Characteristics of CMUTs as Function of Plate Dimensions

    DEFF Research Database (Denmark)

    Diederichsen, Søren Elmin; Hansen, Jesper Mark Fly; Engholm, Mathias

    2017-01-01

    This paper presents an experimental study of the acoustic performance of Capacitive Micromachined Ultrasonic Transducers (CMUTs) as function of plate dimensions. The objective is to increase the output pressure without decreasingthe pulse-echo signal. The CMUTs are fabricated with a LOCOS process......-to-peak output pressure and pulse-echo signal is obtained for the 9.3μm plate, which still has a moderate pulseecho bandwidth of 60%. The 9.3μm plate results in a 1.9 times higher peak-to-peak output pressure and a 3.6 times higherpulse-echo signal compared to the 2μm plate. By adjusting the plate dimensions...

  7. 3-D Vector Flow Using a Row-Column Addressed CMUT Array

    DEFF Research Database (Denmark)

    Holbek, Simon; Christiansen, Thomas Lehrmann; Engholm, Mathias

    2016-01-01

    This paper presents an in-house developed 2-D capacitive micromachined ultrasonic transducer (CMUT) appliedfor 3-D blood flow estimation. The probe breaks with conventional transducers in two ways; first, the ultrasonicpressure field is generated from thousands of small vibrating micromachined...... cells, and second, elements areaccessed by row and/or column indices. The 62+62 2-D row-column addressed prototype CMUT probe was usedfor vector flow estimation by transmitting focused ultrasound into a flow-rig with a fully developed parabolicflow. The beam-to-flow angle was 90◦. The received data...... was beamformed and processed offline. A transverseoscillation (TO) velocity estimator was used to estimate the 3-D vector flow along a line originating from thecenter of the transducer. The estimated velocities in the lateral and axial direction were close to zero as expected.In the transverse direction...

  8. Wafer-Level Vacuum Packaging of Smart Sensors

    Directory of Open Access Journals (Sweden)

    Allan Hilton

    2016-10-01

    Full Text Available The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  9. Wafer-Level Vacuum Packaging of Smart Sensors.

    Science.gov (United States)

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  10. BCB Bonding Technology of Back-Side Illuminated COMS Device

    Science.gov (United States)

    Wu, Y.; Jiang, G. Q.; Jia, S. X.; Shi, Y. M.

    2018-03-01

    Back-side illuminated CMOS(BSI) sensor is a key device in spaceborne hyperspectral imaging technology. Compared with traditional devices, the path of incident light is simplified and the spectral response is planarized by BSI sensors, which meets the requirements of quantitative hyperspectral imaging applications. Wafer bonding is the basic technology and key process of the fabrication of BSI sensors. 6 inch bonding of CMOS wafer and glass wafer was fabricated based on the low bonding temperature and high stability of BCB. The influence of different thickness of BCB on bonding strength was studied. Wafer bonding with high strength, high stability and no bubbles was fabricated by changing bonding conditions.

  11. Wafer-level vacuum/hermetic packaging technologies for MEMS

    Science.gov (United States)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  12. Transceiver Design for CMUT-Based Super-Resolution Ultrasound Imaging.

    Science.gov (United States)

    Behnamfar, Parisa; Molavi, Reza; Mirabbasi, Shahriar

    2016-04-01

    A recently introduced structure for the capacitive micromachined ultrasonic transducers (CMUTs) has focused on the applications of the asymmetric mode of vibration and has shown promising results in construction of super-resolution ultrasound images. This paper presents the first implementation and experimental results of a transceiver circuit to interface such CMUT structures. The multiple input/multiple output receiver in this work supports both fundamental and asymmetric modes of operation and includes transimpedance amplifiers and low-power variable-gain stages. These circuit blocks are designed considering the trade-offs between gain, input impedance, noise, linearity and power consumption. The high-voltage transmitter can generate pulse voltages up to 60 V while occupying a considerably small area. The overall circuit is designed and laid out in a 0.35 μm CMOS process and a four-channel transceiver occupies 0.86 × 0.38 mm(2). The prototype chip is characterized in both electrical and mechanical domains. Measurement results show that each receiver channel has a nominal gain of 110 dBΩ with a 3 dB bandwidth of 9 MHz while consuming 1.02 mW from a 3.3 V supply. The receiver is also highly linear, with 1 dB compression point of minimum 1.05 V which is considerably higher than the previously reported designs. The transmitter consumes 98.1 mW from a 30 V supply while generating 1.38 MHz, 30 V pulses. The CMOS-CMUT system is tested in the transmit mode and shows full functionality in air medium.

  13. Transmitting Performance Evaluation of ASICs for CMUT-Based Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Diederichsen, Søren Elmin; Jørgensen, Ivan Harald Holger

    2017-01-01

    Portable ultrasound scanners (PUS) have, in recent years, raised a lot of attention, as they can potentially overcome some of the limitations of static scanners. However, PUS have a lot of design limitations including size and power consumption. These restrictions can compromise the image quality...... of the scanner. In order to overcome these restrictions, application specific integrated circuits (ASICs) are needed to implement the electronics. In this work, a comparative study of the transmitting performance of a capacitive micromachined ultrasonic transducer (CMUT) driven by a commercial generic ultrasound...

  14. Probe development of CMUT and PZT row-column-addressed 2-D arrays

    DEFF Research Database (Denmark)

    Engholm, Mathias; Bouzari, Hamed; Christiansen, Thomas Lehrmann

    2018-01-01

    for driving the 128-channel coaxial cable to the scanner. The electronics were designed to allow all elements, both rows and columns, to be used interchangeably as either transmitters or receivers. The transducer characterization i.e. bandwidth, phase delay, surface pressure, sensitivity, insertion loss......, and acoustical crosstalk, were based on several single element measurements, including pressure and pulse-echo, and were evaluated quantitatively and comparatively. The weighted center frequency was 3.0 MHz for both probes and the measured -6 dB fractional bandwidth was 109 ± 4% and 80 ± 3% for the CMUT...

  15. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  16. Characterization of silicon-on-insulator wafers

    Science.gov (United States)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  17. High-voltage integrated transmitting circuit with differential driving for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz

    2016-01-01

    In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... is designed and implemented in AMS 0.35 μ m high-voltage process. Measurements are performed on the fabricated integrated circuit in order to assess its performance. The transmitting circuit consists of a low-voltage control logic, pulse-triggered level shifters and a differential output stage that generates...... conditions is 0.936 mW including the load. The integrated circuits measured prove to be consistent and robust to local process variations by measurements....

  18. Laser wafering for silicon solar

    International Nuclear Information System (INIS)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-01-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  19. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  20. A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.

    Science.gov (United States)

    Huang, Xiwei; Cheong, Jia Hao; Cha, Hyouk-Kyu; Yu, Hongbin; Je, Minkyu; Yu, Hao

    2013-01-01

    One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

  1. Estimation of interface resistivity in bonded Si for the development of high performance radiation detectors

    International Nuclear Information System (INIS)

    Kanno, Ikuo; Yamashita, Makoto; Nomiya, Seiichiro; Onabe, Hideaki

    2007-01-01

    For the development of high performance radiation detectors, direct bonding of Si wafers would be an useful method. Previously, p-n bonded Si were fabricated and they showed diode characteristics. The interface resistivity was, however, not investigated in detail. For the study of interface resistivity, n-type Si wafers with different resistivities were bonded. The resistivity of bonded Si wafers were measured and the interface resistivity was estimated by comparing with the results of model calculations. (author)

  2. Fusion-bonded fluidic interconnects

    NARCIS (Netherlands)

    Fazal, I.; Elwenspoek, Michael Curt

    2008-01-01

    A new approach to realize fluidic interconnects based on the fusion bonding of glass tubes with silicon is presented. Fusion bond strength analyses have been carried out. Experiments with plain silicon wafers and coated with silicon oxide and silicon nitride are performed. The obtained results are

  3. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  4. Surface etching technologies for monocrystalline silicon wafer solar cells

    Science.gov (United States)

    Tang, Muzhi

    With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

  5. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

    Science.gov (United States)

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

    2014-02-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

  6. Temperature Dependent Electrical Properties of PZT Wafer

    Science.gov (United States)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  7. Industrial Silicon Wafer Solar Cells

    OpenAIRE

    Neuhaus, Dirk-Holger; Münzer, Adolf

    2007-01-01

    In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future e...

  8. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    OpenAIRE

    Zhuhao Gong; Yulong Zhang; Xin Guo; Zewen Liu

    2018-01-01

    A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to gener...

  9. Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

    Science.gov (United States)

    Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

    2017-10-01

    Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

  10. Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

    Science.gov (United States)

    Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

    2018-01-01

    Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

  11. Wafer scale oblique angle plasma etching

    Science.gov (United States)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  12. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  13. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  14. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  15. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  16. Wafer-level manufacturing technology of glass microlenses

    Science.gov (United States)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  17. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    CERN Document Server

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  18. Sealing of cavities with lateral feed-throughs by anodic bonding

    DEFF Research Database (Denmark)

    Fléron, René; Jensen, Flemming

    2003-01-01

    The SESiBon(1)) project under the EU Growth programme has focussed on the investigation and exploitation of various silicon bonding techniques. Both standard silicon to pyrex wafer bonding and the more advanced silicon-to-silicon thin film anodic bonding has been investigated. Here we present...... the results of the work done to enable bonding of structured wafer surfaces, allowing lateral feed-throughs into sealed cavities.Lateral feed throughs are formed by means of RIE in a high-doped poly-silicon film deposited on an oxidized 4" silicon wafer. Next a BPSG (Boron Phosphorus Silicate Glass) layer...... is deposited in a PECVD reaction chamber onto the structured surface. The BPSG is used as an intermediate planarization layer. Planarization is done by annealing the wafer in a N2-O2-H2O ambient for 4 - 8h @ 900 degreesC. After planarization the two wafers are bonded together, sealing the cavities.Our work...

  19. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  20. Single wafer rapid thermal multiprocessing

    International Nuclear Information System (INIS)

    Saraswat, K.C.; Moslehi, M.M.; Grossman, D.D.; Wood, S.; Wright, P.; Booth, L.

    1989-01-01

    Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. The authors propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. This paper describes the development of a novel single wafer rapid thermal multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals

  1. Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology

    International Nuclear Information System (INIS)

    Cao Yuhan; Luo Le

    2009-01-01

    A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu 6 Sn 5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 x 10 -9 atm cc/s are possible, meeting the demands of MIL-STD-883E. (semiconductor technology)

  2. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  3. Wafer Cakes of Improved Amino Acid Structure

    Directory of Open Access Journals (Sweden)

    Roksolana Boidunyk

    2017-11-01

    Full Text Available The article presents the results of the study of the amino acid composition of newly developed wafer cakes with adipose fillings combined with natural additives. The appropriateness of the using non-traditional raw materials (powder of willow herb, poppy oilcake, carob, as well as skimmed milk powder in order to increase the biological value of wafer cakes and improve their amino acid composition is proven.

  4. Silicon wafers for integrated circuit process

    OpenAIRE

    Leroy , B.

    1986-01-01

    Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

  5. Lamb wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Fromme, P.; Pizzolato, M.; Robyr, J-L; Masserey, B.

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness a...

  6. On the design and implementation of a wafer yield editor

    NARCIS (Netherlands)

    Pineda de Gyvez, J.; Jess, J.A.G.

    1989-01-01

    An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and

  7. Modeling the wafer temperature profile in a multiwafer LPCVD furnace

    Energy Technology Data Exchange (ETDEWEB)

    Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

    1994-01-01

    A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

  8. Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel; Frech, J.; Heschel, M.

    2003-01-01

    A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr...

  9. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  10. X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2014-09-15

    The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

  11. Fusion-bonded fluidic interconnects

    International Nuclear Information System (INIS)

    Fazal, I; Elwenspoek, M C

    2008-01-01

    A new approach to realize fluidic interconnects based on the fusion bonding of glass tubes with silicon is presented. Fusion bond strength analyses have been carried out. Experiments with plain silicon wafers and coated with silicon oxide and silicon nitride are performed. The obtained results are discussed in terms of the homogeneity and strength of fusion bond. High pressure testing shows that the bond strength is large enough for most applications of fluidic interconnects. The bond strength for 525 µm thick silicon, with glass tubes having an outer diameter of 6 mm and with a wall thickness of 2 mm, is more than 60 bars after annealing at a temperature of 800 °C

  12. Wafer level 3-D ICs process technology

    CERN Document Server

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  13. Making Porous Luminescent Regions In Silicon Wafers

    Science.gov (United States)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  14. Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

    Science.gov (United States)

    Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

    2017-10-01

    Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

  15. InGaAs-OI Substrate Fabrication on a 300 mm Wafer

    Directory of Open Access Journals (Sweden)

    Sebastien Sollier

    2016-09-01

    Full Text Available In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs wafer on insulator (InGaAs-OI substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM, scanning acoustic microscopy (SAM, and HR-XRD, to insure the crystalline quality of the post transferred layer.

  16. Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

    Science.gov (United States)

    Syed, Ahmed Rashid

    Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

  17. High throughput batch wafer handler for 100 to 200 mm wafers

    International Nuclear Information System (INIS)

    Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

    1989-01-01

    A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

  18. An electret-based energy harvesting device with a wafer-level fabrication process

    DEFF Research Database (Denmark)

    Crovetto, Andrea; Wang, Fei; Hansen, Ole

    2013-01-01

    This paper presents a MEMS energy harvesting device which is able to generate power from two perpendicular ambient vibration directions. A CYTOP polymer is used both as the electret material for electrostatic transduction and as a bonding interface for low-temperature wafer bonding. The device...... is also discussed. With a final chip size of about 1 cm2, a power output of 32.5 nW is successfully harvested with an external load of 17 MΩ, when a harmonic vibration source with an RMS acceleration amplitude of 0.03 g (∼0.3 m s−2) and a resonant frequency of 179 Hz is applied. These results can...

  19. Controllable laser thermal cleavage of sapphire wafers

    Science.gov (United States)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  20. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

  1. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  2. Wafer plane inspection for advanced reticle defects

    Science.gov (United States)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  3. Noncontact sheet resistance measurement technique for wafer inspection

    Science.gov (United States)

    Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

    1995-12-01

    A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

  4. Water saving in IC wafer washing process; IC wafer senjo deno sessui taisaku

    Energy Technology Data Exchange (ETDEWEB)

    Harada, H. [Mitsubishi Corp., Tokyo (Japan); Araki, M.; Nakazawa, T.

    1997-11-30

    This paper reports features of a wafer washing technology, a new IC wafer washing process, its pure water saving effect, and a `QC washing` which has pure water saving effect in the wafer washing. Wafer washing processes generally include the SC1 process (using ammonia + hydrogen peroxide aqueous solution) purposed for removing contamination due to ultrafine particles, the SC2 process (using hydrochloric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to heavy metals, the piranha washing process (using hot sulfuric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to organic matters, and the DHF (using dilute hydrofluoric acid) purposed for removing natural oxide films. Natural oxide films are now remained as surface protection films, by which surface contamination has been reduced remarkably. A high-temperature washing chemical circulating and filtering technology developed in Japan has brought about a reform in wafer washing processes having been used previously. Spin washing is used as a water saving measure, in which washing chemicals or pure water are sprayed onto one each of wafers which is spin-rotated, allowing washing and rinsing to be made with small amount of washing chemicals and pure water. The QC washing is a method to replace tank interior with pure was as quick as possible in order to increase the rinsing effect. 7 refs., 5 figs.

  5. A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    International Nuclear Information System (INIS)

    Gao Baohong; Liu Yuling; Wang Chenwei; Wang Shengli; Zhou Qiang; Tan Baimei; Zhu Yadong

    2010-01-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO 4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection. (semiconductor technology)

  6. InP-based photonic integrated circuit platform on SiC wafer.

    Science.gov (United States)

    Takenaka, Mitsuru; Takagi, Shinichi

    2017-11-27

    We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

  7. An Experimental Protocol for Assessing the Performance of New Ultrasound Probes Based on CMUT Technology in Application to Brain Imaging.

    Science.gov (United States)

    Matrone, Giulia; Ramalli, Alessandro; Savoia, Alessandro Stuart; Quaglia, Fabio; Castellazzi, Gloria; Morbini, Patrizia; Piastra, Marco

    2017-09-24

    The possibility to perform an early and repeatable assessment of imaging performance is fundamental in the design and development process of new ultrasound (US) probes. Particularly, a more realistic analysis with application-specific imaging targets can be extremely valuable to assess the expected performance of US probes in their potential clinical field of application. The experimental protocol presented in this work was purposely designed to provide an application-specific assessment procedure for newly-developed US probe prototypes based on Capacitive Micromachined Ultrasonic Transducer (CMUT) technology in relation to brain imaging. The protocol combines the use of a bovine brain fixed in formalin as the imaging target, which ensures both realism and repeatability of the described procedures, and of neuronavigation techniques borrowed from neurosurgery. The US probe is in fact connected to a motion tracking system which acquires position data and enables the superposition of US images to reference Magnetic Resonance (MR) images of the brain. This provides a means for human experts to perform a visual qualitative assessment of the US probe imaging performance and to compare acquisitions made with different probes. Moreover, the protocol relies on the use of a complete and open research and development system for US image acquisition, i.e. the Ultrasound Advanced Open Platform (ULA-OP) scanner. The manuscript describes in detail the instruments and procedures involved in the protocol, in particular for the calibration, image acquisition and registration of US and MR images. The obtained results prove the effectiveness of the overall protocol presented, which is entirely open (within the limits of the instrumentation involved), repeatable, and covers the entire set of acquisition and processing activities for US images.

  8. Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

  9. Optical cavity furnace for semiconductor wafer processing

    Science.gov (United States)

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  10. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  11. Carbon dioxide capture using resin-wafer electrodeionization

    Science.gov (United States)

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  12. Wafer plane inspection with soft resist thresholding

    Science.gov (United States)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  13. Wafer-shape metrics based foundry lithography

    Science.gov (United States)

    Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

    2017-03-01

    As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

  14. Wafer-scale micro-optics fabrication

    Science.gov (United States)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  15. Lamb wave propagation in monocrystalline silicon wafers.

    Science.gov (United States)

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  16. Boron impurity at the Si/SiO2 interface in SOI wafers and consequences for piezoresistive MEMS devices

    International Nuclear Information System (INIS)

    Nafari, A; Karlen, D; Enoksson, P; Rusu, C; Svensson, K

    2009-01-01

    In this work, the electrical performance of piezoresistive devices fabricated on thinned SOI wafers has been investigated. Specifically, SOI wafers manufactured with the standard bond-and-etch back method (BESOI), commonly used for MEMS fabrication, have been studied. Results from electrical measurements and SIMS characterization show the presence of a boron impurity close to the buried oxide, even on unprocessed wafers. If the boron impurity overlaps with the piezoresistors on the device, it can create non-defined pn-junctions and thus allow conduction through the substrate, leading to stray connections and excessive noise. The thickness of the boron impurity can extend up to several µm, thus setting a thickness limit for the thinnest parts of a MEMS device. This work shows how this impurity can fundamentally affect the functionality of piezoresistive devices. Design rules of how to avoid this are presented

  17. Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell

    Directory of Open Access Journals (Sweden)

    Michael J. Schöning

    2006-04-01

    Full Text Available A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor is realised by means of integration of a specifically designedcapillary electrochemical micro-droplet cell into a commercial wafer prober-station. Thedeveloped system allows the identification and selection of “good” ISFETs at the earlieststage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. Thedeveloped system is also feasible for wafer-level characterisation of ISFETs in terms ofsensitivity, hysteresis and response time. Additionally, the system might be also utilised forwafer-level testing of further electrochemical sensors.

  18. Room temperature Cu-Cu direct bonding using surface activated bonding method

    International Nuclear Information System (INIS)

    Kim, T.H.; Howlader, M.M.R.; Itoh, T.; Suga, T.

    2003-01-01

    Thin copper (Cu) films of 80 nm thickness deposited on a diffusion barrier layered 8 in. silicon wafers were directly bonded at room temperature using the surface activated bonding method. A low energy Ar ion beam of 40-100 eV was used to activate the Cu surface prior to bonding. Contacting two surface-activated wafers enables successful Cu-Cu direct bonding. The bonding process was carried out under an ultrahigh vacuum condition. No thermal annealing was required to increase the bonding strength since the bonded interface was strong enough at room temperature. The chemical constitution of the Cu surface was examined by Auger electron spectroscope. It was observed that carbon-based contaminations and native oxides on copper surface were effectively removed by Ar ion beam irradiation for 60 s without any wet cleaning processes. An atomic force microscope study shows that the Ar ion beam process causes no surface roughness degradation. Tensile test results show that high bonding strength equivalent to bulk material is achieved at room temperature. The cross-sectional transmission electron microscope observations reveal the presence of void-free bonding interface without intermediate layer at the bonded Cu surfaces

  19. Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers

    International Nuclear Information System (INIS)

    Hoechbauer, T.; Misra, A.; Nastasi, M.; Henttinen, K.; Suni, T.; Suni, I.; Lau, S.S.; Ensinger, W.

    2004-01-01

    Hydrogen ion-implantation into Si and subsequent heat treatment has been shown to be an effective means of cleaving thin layer of Si from its parent wafer. This process has been called Smart Cut TM or ion-cut. We investigated the cleavage process in H-implanted silicon samples, in which the ion-cut was provoked thermally and mechanically, respectively. A oriented p-type silicon wafer was irradiated at room temperature with 100 keV H 2 + -ions to a dose of 5 x 10 16 H 2 /cm 2 and subsequently joined to a handle wafer. Ion-cutting was achieved by two different methods: (1) thermally by annealing to 350 deg. C and (2) mechanically by insertion of a razor blade sidewise into the bonded wafers near the bond interface. The H-concentration and the crystal damage depth profiles before and after the ion-cut were investigated through the combined use of elastic recoil detection analysis and Rutherford backscattering spectroscopy (RBS). The location at which the ion-cut occurred was determined by RBS in channeling mode and cross-section transmission electron spectroscopy. The ion-cut depth was found to be independent on the cutting method. The gained knowledge was correlated to the depth distribution of the H-platelet density in the as-implanted sample, which contains two separate peaks in the implantation zone. The obtained results suggest that the ion-cut location coincides with the depth of the H-platelet density peak located at a larger depth

  20. Wafer-Scale Integration of Systolic Arrays,

    Science.gov (United States)

    1985-10-01

    hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

  1. Wafer-scale pixelated detector system

    Science.gov (United States)

    Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

    2017-10-17

    A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

  2. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'Brien, Deirdre

    2012-02-01

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  3. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'brien, Deirdre

    2010-12-15

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  4. High frequency guided wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Pizzolato, M.; Masserey, B.; Robyr, J. L.; Fromme, P.

    2017-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full...

  5. Low temperature bonding of heterogeneous materials using Al2O3 as an intermediate layer

    DEFF Research Database (Denmark)

    Sahoo, Hitesh Kumar; Ottaviano, Luisa; Zheng, Yi

    2018-01-01

    Integration of heterogeneous materials is crucial for many nanophotonic devices. The integration is often achieved by bonding using polymer adhesives or metals. A much better and cleaner option is direct wafer bonding, but the high annealing temperatures required make it a much less attractive...... atomic layer deposited Al2O3 an excellent choice for the intermediate layer. The authors have optimized the bonding process to achieve a high interface energy of 1.7 J/m2 for a low temperature annealing of 300 °C. The authors also demonstrate wafer bonding of InP to SiO2 on Si and GaAs to sapphire using...

  6. Development of bonded semiconductor device for high counting rate high efficiency photon detectors

    International Nuclear Information System (INIS)

    Kanno, Ikuo

    2008-01-01

    We are trying to decrease dose exposure in medical diagnosis by way of measuring the energy of X-rays. For this purpose, radiation detectors for X-ray energy measurement with high counting rate should be developed. Direct bonding of Si wafers was carried out to make a radiation detector, which had separated X-ray absorber and detector. The resistivity of bonding interface was estimated with the results of four-probe measurements and model calculations. Direct bonding of high resistivity p and n-Si wafers was also performed. The resistance of the pn bonded diode was 0.7 MΩ. The resistance should be increased in the future. (author)

  7. Wafer edge overlay control solution for N7 and beyond

    Science.gov (United States)

    van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

    2018-03-01

    Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

  8. Direct Electroplating on Highly Doped Patterned Silicon Wafers

    NARCIS (Netherlands)

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    Nickel thin films have been electrodeposited directly on highly doped silicon wafers after removal of the native oxide layer. These substrates conduct sufficiently well to allow deposition using a periferical electrical contact on the wafer. Films 2 μm thick were deposited using a nickel sulfamate

  9. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang; Carreno, Armando Arpys Arevalo; Li, Huawei; Foulds, Ian G.

    2014-01-01

    feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared

  10. Design and implementation of a novel conical electrode for fast anodic bonding

    International Nuclear Information System (INIS)

    Yang, Chii-Rong; Chang, Long-Yin; Wu, Jim-Wei

    2014-01-01

    Anodic bonding is a frequently used nonintermediate wafer-bonding technique for use in MEMS. However, it has a minimum bonding time for a 4 in silicon/glass wafer that is generally limited to the order of several minutes because of the gas-trapping problem that occurs in the bonded interface when a conventional bonding electrode is used. Therefore, the purpose of this study was to develop a novel conical bonding electrode, which shortens the bonding time and solves the gas-trapping problem of the bonded interface. The 4 in silicon/glass wafers fitted with the proposed electrode exhibited a bonding ratio of 99.89% and an average bonding strength of around 15 MPa, which was attained within 15 s, at a bonding voltage of 900 V and a bonding temperature of 400 °C. A comprehensive series of experiments was performed to validate the excellent bonding performance of the proposed conical electrode. (paper)

  11. Semiconductor industry wafer fab exhaust management

    CERN Document Server

    Sherer, Michael J

    2005-01-01

    Given the myriad exhaust compounds and the corresponding problems that they can pose in an exhaust management system, the proper choice of such systems is a complex task. Presenting the fundamentals, technical details, and general solutions to real-world problems, Semiconductor Industry: Wafer Fab Exhaust Management offers practical guidance on selecting an appropriate system for a given application. Using examples that provide a clear understanding of the concepts discussed, Sherer covers facility layout, support facilities operations, and semiconductor process equipment, followed by exhaust types and challenges. He reviews exhaust point-of-use devices and exhaust line requirements needed between process equipment and the centralized exhaust system. The book includes information on wet scrubbers for a centralized acid exhaust system and a centralized ammonia exhaust system and on centralized equipment to control volatile organic compounds. It concludes with a chapter devoted to emergency releases and a separ...

  12. Chemical polishing of epitoxial silicon wafer

    International Nuclear Information System (INIS)

    Osada, Shohei

    1978-01-01

    SSD telescopes are used for the determination of the kind and energy of charged particles produced by nuclear reactions, and are the equipments combining ΔE counters and E counters. The ΔE counter is a thin SSD which is required to be thin and homogeneous enough to get the high resolution of measurement. The SSDs for ΔE counters have so far been obtained by polishing silicon plates mechanically and chemically or by applying electrolytic polishing method on epitaxial silicon wafers, but it was very hard to obtain them. The creative etching equipment and technique developed this time make it possible to obtain thin SSDs for ΔE counters. The outline of the etching equipment and its technique are described in the report. The etching technique applied for the silicon films for ΔE counters with thickness of about 10 μm was able to be experimentally established in this study. (Kobatake, H.)

  13. Thermoelectric properties of boron and boron phosphide CVD wafers

    Energy Technology Data Exchange (ETDEWEB)

    Kumashiro, Y.; Yokoyama, T.; Sato, A.; Ando, Y. [Yokohama National Univ. (Japan)

    1997-10-01

    Electrical and thermal conductivities and thermoelectric power of p-type boron and n-type boron phosphide wafers with amorphous and polycrystalline structures were measured up to high temperatures. The electrical conductivity of amorphous boron wafers is compatible to that of polycrystals at high temperatures and obeys Mott`s T{sup -{1/4}} rule. The thermoelectric power of polycrystalline boron decreases with increasing temperature, while that of amorphous boron is almost constant in a wide temperature range. The weak temperature dependence of the thermal conductivity of BP polycrystalline wafers reflects phonon scattering by grain boundaries. Thermal conductivity of an amorphous boron wafer is almost constant in a wide temperature range, showing a characteristic of a glass. The figure of merit of polycrystalline BP wafers is 10{sup -7}/K at high temperatures while that of amorphous boron is 10{sup -5}/K.

  14. Reticle variation influence on manufacturing line and wafer device performance

    Science.gov (United States)

    Nistler, John L.; Spurlock, Kyle

    1994-01-01

    Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

  15. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    International Nuclear Information System (INIS)

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

    2014-01-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

  16. Bond Issues.

    Science.gov (United States)

    Pollack, Rachel H.

    2000-01-01

    Notes trends toward increased borrowing by colleges and universities and offers guidelines for institutions that are considering issuing bonds to raise money for capital projects. Discussion covers advantages of using bond financing, how use of bonds impacts on traditional fund raising, other cautions and concerns, and some troubling aspects of…

  17. Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

    Science.gov (United States)

    Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

    2012-05-01

    In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

  18. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    Directory of Open Access Journals (Sweden)

    Zhuhao Gong

    2018-02-01

    Full Text Available A radio-frequency micro-electro-mechanical system (RF MEMS wafer-level packaging (WLP method using pre-patterned benzo-cyclo-butene (BCB polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to generate the housing cavity, the BCB sealing ring was protected by a sputtered Cr/Au (chromium/gold layer. The average measured thickness of the BCB layer was 5.9 μm. In contrast to the conventional methods of spin-coating BCB after fabricating cavities, the pre-patterned BCB method presented BCB bonding layers with better quality on severe topography surfaces in terms of increased uniformity of thickness and better surface flatness. The observation of the bonded layer showed that no void or gap formed on the protruding coplanar waveguide (CPW lines. A shear strength test was experimentally implemented as a function of the BCB widths in the range of 100–400 μm. The average shear strength of the packaged device was higher than 21.58 MPa. A RF MEMS switch was successfully packaged using this process with a negligible impact on the microwave characteristics and a significant improvement in the lifetime from below 10 million to over 1 billion. The measured insertion loss of the packaged RF MEMS switch was 0.779 dB and the insertion loss deterioration caused by the package structure was less than 0.2 dB at 30 GHz.

  19. Dislocation behavior of surface-oxygen-concentration controlled Si wafers

    International Nuclear Information System (INIS)

    Asazu, Hirotada; Takeuchi, Shotaro; Sannai, Hiroya; Sudo, Haruo; Araki, Koji; Nakamura, Yoshiaki; Izunome, Koji; Sakai, Akira

    2014-01-01

    We have investigated dislocation behavior in the surface area of surface-oxygen-concentration controlled Si wafers treated by a high temperature rapid thermal oxidation (HT-RTO). The HT-RTO process allows us to precisely control the interstitial oxygen concentration ([O i ]) in the surface area of the Si wafers. Sizes of rosette patterns, generated by nano-indentation and subsequent thermal annealing at 900 °C for 1 h, were measured for the Si wafers with various [O i ]. It was found that the rosette size decreases in proportion to the − 0.25 power of [O i ] in the surface area of the Si wafers, which were higher than [O i ] of 1 × 10 17 atoms/cm 3 . On the other hand, [O i ] of lower than 1 × 10 17 atoms/cm 3 did not affect the rosette size very much. These experimental results demonstrate the ability of the HT-RTO process to suppress the dislocation movements in the surface area of the Si wafer. - Highlights: • Surface-oxygen-concentration controlled Si wafers have been made. • The oxygen concentration was controlled by high temperature rapid thermal oxidation. • Dislocation behavior in the surface area of the Si wafers has been investigated. • Rosette size decreased with increasing of interstitial oxygen atoms. • The interstitial oxygen atoms have a pinning effect of dislocations at the surface

  20. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    Science.gov (United States)

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

  1. The uses of Man-Made diamond in wafering applications

    Science.gov (United States)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  2. Influence of Si wafer thinning processes on (sub)surface defects

    Energy Technology Data Exchange (ETDEWEB)

    Inoue, Fumihiro, E-mail: fumihiro.inoue@imec.be [Imec, Kapeldreef 75, 3001 Leuven (Belgium); Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric [Imec, Kapeldreef 75, 3001 Leuven (Belgium); Uedono, Akira [Division of Applied Physics, Faculty of Pure and Applied Science, University of Tsukuba, Tsukuba, Ibaraki 305-8573 (Japan)

    2017-05-15

    Highlights: • Mono-vacancy free Si-thinning can be accomplished by combining several thinning techniques. • The grinding damage needs to be removed prior to dry etching, otherwise vacancies remain in the Si at a depth around 0.5 to 2 μm after Si wafer thickness below 5 μm. • The surface of grinding + CMP + dry etching is equivalent mono vacancy level as that of grinding + CMP. - Abstract: Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5–2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in

  3. Optoelectronic interconnects for 3D wafer stacks

    Science.gov (United States)

    Ludwig, David; Carson, John C.; Lome, Louis S.

    1996-01-01

    Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

  4. development and evaluation of lyophilized thiolated-chitosan wafers

    African Journals Online (AJOL)

    User

    THIOLATED-CHITOSAN WAFERS FOR BUCCAL DELIVERY. OF PROTEIN ... of the thiolated polymer incorporating per polymer weight, 10 % each of glycerol as plasticizer, D-mannitol as ..... delivery systems: in vitro stability, in vivo fate, and ...

  5. Parental Bonding

    Directory of Open Access Journals (Sweden)

    T. Paul de Cock

    2014-08-01

    Full Text Available Estimating the early parent–child bonding relationship can be valuable in research and practice. Retrospective dimensional measures of parental bonding provide a means for assessing the experience of the early parent–child relationship. However, combinations of dimensional scores may provide information that is not readily captured with a dimensional approach. This study was designed to assess the presence of homogeneous groups in the population with similar profiles on parental bonding dimensions. Using a short version of the Parental Bonding Instrument (PBI, three parental bonding dimensions (care, authoritarianism, and overprotection were used to assess the presence of unobserved groups in the population using latent profile analysis. The class solutions were regressed on 23 covariates (demographics, parental psychopathology, loss events, and childhood contextual factors to assess the validity of the class solution. The results indicated four distinct profiles of parental bonding for fathers as well as mothers. Parental bonding profiles were significantly associated with a broad range of covariates. This person-centered approach to parental bonding has broad utility in future research which takes into account the effect of parent–child bonding, especially with regard to “affectionless control” style parenting.

  6. Automated reticle inspection data analysis for wafer fabs

    Science.gov (United States)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  7. Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

    Directory of Open Access Journals (Sweden)

    Kwang Hong Lee

    2015-01-01

    Full Text Available A method to remove the misfit dislocations and reduce the threading dislocations density (TDD in the germanium (Ge epilayer growth on a silicon (Si substrate is presented. The Ge epitaxial film is grown directly on the Si (001 donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001 handle wafer to form a germanium-on-insulator (GOI substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to <5 × 106 cm−2.

  8. Guided ultrasonic wave beam skew in silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2018-04-01

    In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

  9. Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster

    OpenAIRE

    Zoschke, Kai; Güttler, Maurice; Böttcher, Lars; Grübl, Andreas; Husmann, Dan; Schemmel, Johannes; Meier, Karlheinz; Ehrmann, Oswin

    2018-01-01

    Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the KIP and the associated hardware requirements which drove the described technological developments. In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a ...

  10. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

    Science.gov (United States)

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-12-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

  11. Preparation and characterisation of immobilised humic acid on silicon wafer

    International Nuclear Information System (INIS)

    Szabo, Gy.; Guczi, J.; Telegdi, J.; Pashalidis, I.; Szymczak, W.; Buckau, G.

    2005-01-01

    Full text of publication follows: The chemistry of the interactions of radionuclides with humic acid needs to be understood in details so that humate-mediated migration of radionuclides through the environment can be predicted. To achieve such a data in microscopic scale, several detective techniques, such as atomic force microscopy (AFM), chemical force microscopy (CFM), nuclear microprobe analysis (NMA) and X-ray photoelectron spectroscopy (XPS) can be used to measure intermolecular forces and to visualize the surface morphology. The main aim of this work was to provide humic material with specific properties in order to study with different spectroscopic techniques, the complexation behaviour of surface bound humic acid in microscopic scale. Namely, humic acid has been immobilised on silicon wafers in order to mimic surface bound humic substances in natural aquatic systems. In this communication, we present a simple protocol to immobilize humic acid on silicon wafer surface. A tri-functional silane reagent 3-amino-propyl-tri-methoxy-silane (APTES) was used to modify the surface of silicon wafers and appeared to be able to strongly attached soluble humic acid through their carboxylic groups to solid support. Characterisation of the surfaces, after any preparation steps, was done by ATR-FTIR, AFM and TOF-SIMS. These methods have proved that the humic acid forms a relatively homogeneous layer on the wafers. Immobilisation of humic acid on silicon wafer was further proved by binding isotherm of Am/Nd. (authors)

  12. Characterizing SOI Wafers By Use Of AOTF-PHI

    Science.gov (United States)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  13. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    Science.gov (United States)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  14. Wafer-scale fabrication of polymer distributed feedback lasers

    DEFF Research Database (Denmark)

    Christiansen, Mads Brøkner; Schøler, Mikkel; Balslev, Søren

    2006-01-01

    The authors demonstrate wafer-scale, parallel process fabrication of distributed feedback (DFB) polymer dye lasers by two different nanoimprint techniques: By thermal nanoimprint lithography (TNIL) in polymethyl methacrylate and by combined nanoimprint and photolithography (CNP) in SU-8. In both...... techniques, a thin film of polymer, doped with rhodamine-6G laser dye, is spin coated onto a Borofloat glass buffer substrate and shaped into a planar waveguide slab with first order DFB surface corrugations forming the laser resonator. When optically pumped at 532 nm, lasing is obtained in the wavelength...... range between 576 and 607 nm, determined by the grating period. The results, where 13 laser devices are defined across a 10 cm diameter wafer substrate, demonstrate the feasibility of NIL and CNP for parallel wafer-scale fabrication of advanced nanostructured active optical polymer components...

  15. Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

    International Nuclear Information System (INIS)

    Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

    2005-01-01

    Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

  16. PMMA to SU-8 Bonding for Polymer Based Lab-on-a-chip Systems with Integrated Optics

    DEFF Research Database (Denmark)

    Olsen, Brian Bilenberg; Nielsen, Theodor; Nilsson, Daniel

    2003-01-01

    An adhesive bonding technique for wafer-level sealing of SU-8 based lab-on-a-chip microsystems with integrated optical components is presented. Microfluidic channels and optical components, e.g. waveguides, are fabricated in cross-linked SU-8 and sealed with a Pyrex glass substrate by means...... strength of 16 MPa is achieved at bonding temperatures between 110 oC and 120oC, at a bonding force of 2000 N on a 4-inch wafer. The optical propagation loss of multi-mode 10ym (thickness)x 30ym (width)SU-8 waveguides is measured. The propagation loss in PMMA bonded waveguide struc-tures is more than 5 d......B/cm lower, at wavelengths between 600nm and 900 nm, than in similar structures bonded by an intermediate layer of SU-8. Furthermore 950K PMMA shows no tendency to flow into the bonded structures during bonding because of its high viscosity....

  17. Protection of MOS capacitors during anodic bonding

    Science.gov (United States)

    Schjølberg-Henriksen, K.; Plaza, J. A.; Rafí, J. M.; Esteve, J.; Campabadal, F.; Santander, J.; Jensen, G. U.; Hanneborg, A.

    2002-07-01

    We have investigated the electrical damage by anodic bonding on CMOS-quality gate oxide and methods to prevent this damage. n-type and p-type MOS capacitors were characterized by quasi-static and high-frequency CV-curves before and after anodic bonding. Capacitors that were bonded to a Pyrex wafer with 10 μm deep cavities enclosing the capacitors exhibited increased leakage current and interface trap density after bonding. Two different methods were successful in protecting the capacitors from such damage. Our first approach was to increase the cavity depth from 10 μm to 50 μm, thus reducing the electric field across the gate oxide during bonding from approximately 2 × 105 V cm-1 to 4 × 104 V cm-1. The second protection method was to coat the inside of a 10 μm deep Pyrex glass cavity with aluminium, forming a Faraday cage that removed the electric field across the cavity during anodic bonding. Both methods resulted in capacitors with decreased interface trap density and unchanged leakage current after bonding. No change in effective oxide charge or mobile ion contamination was observed on any of the capacitors in the study.

  18. 450mm wafer patterning with jet and flash imprint lithography

    Science.gov (United States)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  19. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    Science.gov (United States)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  20. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    International Nuclear Information System (INIS)

    Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

    2006-01-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

  1. Wafer scale integration of catalyst dots into nonplanar microsystems

    DEFF Research Database (Denmark)

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

    2007-01-01

    In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  2. Computational Modeling in Plasma Processing for 300 mm Wafers

    Science.gov (United States)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  3. Wafer-Level Vacuum Packaging of Smart Sensors

    OpenAIRE

    Hilton, Allan; Temple, Dorota S.

    2016-01-01

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging...

  4. Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

    International Nuclear Information System (INIS)

    Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

    2006-01-01

    The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

  5. Scatterometry on pelliclized masks: an option for wafer fabs

    Science.gov (United States)

    Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

    2007-03-01

    Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

  6. Prediction of thermo-mechanical reliability of wafer backend processes

    NARCIS (Netherlands)

    Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; van Driel, W.D.; Hoofman, R.J.O.M.; Ernst, L.J.

    2004-01-01

    More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

  7. Prediction of thermo-mechanical integrity of wafer backend processes

    NARCIS (Netherlands)

    Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; Hoofman, R.J.O.M.; Ernst, L.J.; Ernst, L.J.

    2003-01-01

    More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

  8. High frequency guided wave propagation in monocrystalline silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  9. Bonds Boom.

    Science.gov (United States)

    Reynolds, Cathryn

    1989-01-01

    The combined effect of the "Serrano" decision and Proposition 13 left California school districts with aging, overcrowded facilities. Chico schools won a $18.5 million general obligation bond election for facilities construction. With $11 billion needed for new school construction, California will need to tap local sources. A sidebar…

  10. Trace analysis for 300 MM wafers and processes with TXRF

    International Nuclear Information System (INIS)

    Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

    2000-01-01

    Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

  11. Diffusion bonding

    International Nuclear Information System (INIS)

    Anderson, R.C.

    1976-01-01

    A method is described for joining beryllium to beryllium by diffusion bonding. At least one surface portion of at least two beryllium pieces is coated with nickel. A coated surface portion is positioned in a contiguous relationship with another surface portion and subjected to an environment having an atmosphere at a pressure lower than ambient pressure. A force is applied on the beryllium pieces for causing the contiguous surface portions to abut against each other. The contiguous surface portions are heated to a maximum temperature less than the melting temperature of the beryllium, and the applied force is decreased while increasing the temperature after attaining a temperature substantially above room temperature. A portion of the applied force is maintained at a temperature corresponding to about maximum temperature for a duration sufficient to effect the diffusion bond between the contiguous surface portions

  12. Denuded zone in Czochralski silicon wafer with high carbon content

    International Nuclear Information System (INIS)

    Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

    2006-01-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

  13. Denuded zone in Czochralski silicon wafer with high carbon content

    Science.gov (United States)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  14. Peptide and protein loading into porous silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

    2008-02-15

    The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  15. Contacting graphene in a 200 mm wafer silicon technology environment

    Science.gov (United States)

    Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

    2018-06-01

    Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

  16. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    International Nuclear Information System (INIS)

    Montoya, Angela C.; Maji, Arup K.

    2010-01-01

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  17. Cost of Czochralski wafers as a function of diameter

    Science.gov (United States)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-02-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  18. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    Science.gov (United States)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  19. Strength and leak testing of plasma activated bonded interfaces

    DEFF Research Database (Denmark)

    Visser, M.M.; Weichel, Steen; Reus, Roger De

    2002-01-01

    on detection of changes in membrane deflections. The detection limit for leak was 8E-13 mbar l/s. For comparison, strength and leak tests were also performed with regular fusion bonded wafers annealed at 1100 degreesC. The PAB was found to withstand post-processing steps such as RCA cleaning, 24 h in de......-ionised water (DIW), 24 h in 2.5% HF, 24 h in acetone and 60 s in a resist developer. By analysing the thin silicon oxide present on the surfaces to be bonded with optical methods, the influence of pre-cleaning and activation process parameters was investigated....

  20. Low temperature bonding of heterogeneous materials using Al2O3 as an intermediate layer

    DEFF Research Database (Denmark)

    Sahoo, Hitesh Kumar; Ottaviano, Luisa; Zheng, Yi

    2018-01-01

    Integration of heterogeneous materials is crucial for many nanophotonic devices. The integration is often achieved by bonding using polymer adhesives or metals. A much better and cleaner option is direct wafer bonding, but the high annealing temperatures required make it a much less attractive...

  1. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    Science.gov (United States)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

  2. Solid-liquid interdiffusion (SLID) bonding in the Au-In system: experimental study and 1D modelling

    Science.gov (United States)

    Deillon, Léa; Hessler-Wyser, Aïcha; Hessler, Thierry; Rappaz, Michel

    2015-12-01

    Au-In bonds with a nominal composition of about 60 at.% In were fabricated for use in wafer-level packaging of MEMS. The microstructure of the bonds was studied by scanning electron microscopy. The bond hermeticity was then assessed using oxidation of Cu thin discs predeposited within the sealed packages. The three intermetallic compounds AuIn2, AuIn and Au7In3 were observed. Their thickness evolution during bonding and after subsequent heat treatment was successfully modelled using a finite difference model of diffusion, thermodynamic data and diffusion coefficients calibrated from isothermal diffusion couples. 17% of the packages were hermetic and, although the origin of the leaks could not be clearly identified, it appeared that hermeticity was correlated with the unevenness of the metallisation and/or wafer and the fact that the bonds shrink due to density differences as the relative fractions of the various phases gradually evolve.

  3. Solid-liquid interdiffusion (SLID) bonding in the Au–In system: experimental study and 1D modelling

    International Nuclear Information System (INIS)

    Deillon, Léa; Hessler-Wyser, Aïcha; Hessler, Thierry; Rappaz, Michel

    2015-01-01

    Au–In bonds with a nominal composition of about 60 at.% In were fabricated for use in wafer-level packaging of MEMS. The microstructure of the bonds was studied by scanning electron microscopy. The bond hermeticity was then assessed using oxidation of Cu thin discs predeposited within the sealed packages. The three intermetallic compounds AuIn 2 , AuIn and Au 7 In 3 were observed. Their thickness evolution during bonding and after subsequent heat treatment was successfully modelled using a finite difference model of diffusion, thermodynamic data and diffusion coefficients calibrated from isothermal diffusion couples. 17% of the packages were hermetic and, although the origin of the leaks could not be clearly identified, it appeared that hermeticity was correlated with the unevenness of the metallisation and/or wafer and the fact that the bonds shrink due to density differences as the relative fractions of the various phases gradually evolve. (paper)

  4. Magnetron target designs to improve wafer edge trench filling in ionized metal physical vapor deposition

    International Nuclear Information System (INIS)

    Lu Junqing; Yoon, Jae-Hong; Shin, Keesam; Park, Bong-Gyu; Yang Lin

    2006-01-01

    Severe asymmetry of the metal deposits on the trench sidewalls occurs near the wafer edge during low pressure ionized metal physical vapor deposition of Cu seed layer for microprocessor interconnects. To investigate this process and mitigate the asymmetry, an analytical view factor model based on the analogy between metal sputtering and diffuse thermal radiation was constructed. The model was validated based on the agreement between the model predictions and the reported experimental values for the asymmetric metal deposition at trench sidewalls near the wafer edge for a 200 mm wafer. This model could predict the thickness of the metal deposits across the wafer, the symmetry of the deposits on the trench sidewalls at any wafer location, and the angular distributions of the metal fluxes arriving at any wafer location. The model predictions for the 300 mm wafer indicate that as the target-to-wafer distance is shortened, the deposit thickness increases and the asymmetry decreases, however the overall uniformity decreases. Up to reasonable limits, increasing the target size and the sputtering intensity for the outer target portion significantly improves the uniformity across the wafer and the symmetry on the trench sidewalls near the wafer edge

  5. PMMA to SU-8 bonding for polymer based lab-on-a-chip systems with integrated optics

    DEFF Research Database (Denmark)

    Olsen, Brian Bilenberg; Nielsen, Theodor; Clausen, Bjarne Hans

    2004-01-01

    We present an adhesive bonding technique developed for SU-8 based "lab-on-a-chip"- systems with integrated optical components. Microfluidic channels and optical components (e.g. wave-guides) are defined in SU-8 photoresist on a Pyrex glass substrate. The microfluidic channels are sealed by a second...... Pyrex substrate, bonded on top of the cross-linked SU-8 structure using an inter- mediate layer of 950K molecular weight poly-methylmethacrylate (PMMA). Due to a lower refractive index of PMMA, this bonding technique offers optical waveguiding in the SU-8 structures in combination with good sealing...... of the microfluidic channels. The bonding technique is investigated with respect to bonding temperature in the range of 50 - 150 degr. C and at bonding forces of 1000 N and 2000 N on a 4-inch wafer. A maximum bonding strength of 16 MPa is achieved for the PMMA to SU-8 bonding at a bonding temperature of 110 degr. C...

  6. Multiproject wafers: not just for million-dollar mask sets

    Science.gov (United States)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

  7. Study of Si wafer surfaces irradiated by gas cluster ion beams

    International Nuclear Information System (INIS)

    Isogai, H.; Toyoda, E.; Senda, T.; Izunome, K.; Kashima, K.; Toyoda, N.; Yamada, I.

    2007-01-01

    The surface structures of Si (1 0 0) wafers subjected to gas cluster ion beam (GCIB) irradiation have been analyzed by cross-sectional transmission electron microscopy (XTEM) and atomic force microscopy (AFM). GCIB irradiation is a promising technique for both precise surface etching and planarization of Si wafers. However, it is very important to understand the crystalline structure of Si wafers after GCIB irradiation. An Ar-GCIB used for the physically sputtering of Si atoms and a SF 6 -GCIB used for the chemical etching of the Si surface are also analyzed. The GCIB irradiation increases the surface roughness of the wafers, and amorphous Si layers are formed on the wafer surface. However, when the Si wafers are annealed in hydrogen at a high temperature after the GCIB irradiation, the surface roughness decreases to the same level as that before the irradiation. Moreover, the amorphous Si layers disappear completely

  8. Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging

    International Nuclear Information System (INIS)

    Lee, Ju-Yong; Lee, Sung-Woo; Lee, Seung-Ki; Park, Jae-Hyoung

    2013-01-01

    We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 mΩ. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test. (paper)

  9. Tests of a silicon wafer based neutron collimator

    International Nuclear Information System (INIS)

    Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

  10. Tests of a silicon wafer based neutron collimator

    CERN Document Server

    Cussen, L D; Anderson, I S; Hoeghoj, P

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

  11. Underling modification in ion beam induced Si wafers

    International Nuclear Information System (INIS)

    Hazra, S.; Chini, T.K.; Sanyal, M.K.; Grenzer, J.; Pietsch, U.

    2005-01-01

    Subsurface (amorphous-crystalline interface) structure of keV ion beam modified Si(001) wafers was studied for the first time using non-destructive technique and compared with that of the top one. Ion-beam modifications of the Si samples were done using state-of-art high-current ion implanter facility at Saha Institute of Nuclear Physics by changing energy, dose and angle of incidence of the Ar + ion beam. To bring out the underlying modification depth-resolved x-ray grazing incidence diffraction has been carried out using synchrotron radiation facility, while the structure of the top surface was studied through atomic force microscopy

  12. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Science.gov (United States)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  13. Bond strength of masonry

    NARCIS (Netherlands)

    Pluijm, van der R.; Vermeltfoort, A.Th.

    1992-01-01

    Bond strength is not a well defined property of masonry. Normally three types of bond strength can be distinguished: - tensile bond strength, - shear (and torsional) bond strength, - flexural bond strength. In this contribution the behaviour and strength of masonry in deformation controlled uniaxial

  14. Cu Pillar Low Temperature Bonding and Interconnection Technology of for 3D RF Microsystem

    Science.gov (United States)

    Shi, G. X.; Qian, K. Q.; Huang, M.; Yu, Y. W.; Zhu, J.

    2018-03-01

    In this paper 3D interconnects technologies used Cu pillars are discussed with respect to RF microsystem. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, RF microsystem used the heterogeneous chip such as GaAs integration with Si interposers should be at low temperature. The pillars were constituted by Cu (2 micron) -Ni (2 micron) -Cu (3 micron) -Sn (1 micron) multilayer metal and total height is 8 micron on the front-side of the wafer by using electroplating. The wafer backside Cu pillar is obtained by temporary bonding, thinning and silicon surface etching. The RF interposers are stacked by Cu-Sn eutectic bonding at 260 °C. Analyzed the reliability of different pillar bonding structure.

  15. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

    Directory of Open Access Journals (Sweden)

    Bo Xie

    2015-09-01

    Full Text Available This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months, a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

  16. Determination of wafer center position during the transfer process by using the beam-breaking method

    International Nuclear Information System (INIS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-01-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human–machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions. (paper)

  17. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  18. Comprehensive Die Shear Test of Silicon Packages Bonded by Thermocompression of Al Layers with Thin Sn Capping or Insertions

    Directory of Open Access Journals (Sweden)

    Shiro Satoh

    2018-04-01

    Full Text Available Thermocompression bonding for wafer-level hermetic packaging was demonstrated at the lowest temperature of 370 to 390 °C ever reported using Al films with thin Sn capping or insertions as bonding layer. For shrinking the chip size of MEMS (micro electro mechanical systems, a smaller size of wafer-level packaging and MEMS–ASIC (application specific integrated circuit integration are of great importance. Metal-based bonding under the temperature of CMOS (complementary metal-oxide-semiconductor backend process is a key technology, and Al is one of the best candidates for bonding metal in terms of CMOS compatibility. In this study, after the thermocompression bonding of two substrates, the shear fracture strength of dies was measured by a bonding tester, and the shear-fractured surfaces were observed by SEM (scanning electron microscope, EDX (energy dispersive X-ray spectrometry, and a surface profiler to clarify where the shear fracture took place. We confirmed two kinds of fracture mode. One mode is Si bulk fracture mode, where the die shear strength is 41.6 to 209 MPa, proportionally depending on the area of Si fracture. The other mode is bonding interface fracture mode, where the die shear strength is 32.8 to 97.4 MPa. Regardless of the fracture modes, the minimum die shear strength is practical for wafer-level MEMS packaging.

  19. Hydrogen Incorporation during Aluminium Anodisation on Silicon Wafer Surfaces

    International Nuclear Information System (INIS)

    Lu, Pei Hsuan Doris; Strutzberg, Hartmuth; Wenham, Stuart; Lennon, Alison

    2014-01-01

    Hydrogen can act to reduce recombination at silicon surfaces for solar cell devices and consequently the ability of dielectric layers to provide a source of hydrogen for this purpose is of interest. However, due to the ubiquitous nature of hydrogen and its mobility, direct measurements of hydrogen incorporation in dielectric layers are challenging. In this paper, we report the use of secondary ion mass spectrometry measurements to show that deuterium from an electrolyte can be incorporated in an anodic aluminium oxide (AAO) layer and be introduced into an underlying amorphous silicon layer during anodisation of aluminium on silicon wafers. After annealing at 400 °C, the concentration of deuterium in the AAO was reduced by a factor of two, as the deuterium was re-distributed to the interface between the amorphous silicon and AAO and to the amorphous silicon. The assumption that hydrogen, from an aqueous electrolyte, could be similarly incorporated in AAO, is supported by the observation that the hydrogen content in the underlying amorphous silicon was increased by a factor of ∼ 3 after anodisation. Evidence for hydrogen being introduced into crystalline silicon after aluminium anodisation was provided by electrochemical capacitance voltage measurements indicating boron electrical deactivation in the underlying crystalline silicon. If introduced hydrogen can electrically deactivate dopant atoms at the surface, then it is reasonable to assume that it could also deactivate recombination-active states at the crystalline silicon interface therefore enabling higher minority carrier lifetimes in the silicon wafer

  20. Residual stress in silicon wafer using IR polariscope

    Science.gov (United States)

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  1. Improving scanner wafer alignment performance by target optimization

    Science.gov (United States)

    Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

    2016-03-01

    In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

  2. Adsorption kinetics and dynamics of small organic molecules on a silica wafer: Butane, pentane, nonane, thiophene, and methanol adsorption on SiO2/Si(1 1 1)

    International Nuclear Information System (INIS)

    Funk, S.; Goering, J.; Burghaus, U.

    2008-01-01

    The adsorption kinetics (by thermal desorption spectroscopy) and adsorption dynamics (by molecular beam scattering) have been determined for a number of alkanes, methanol, thiophene, and water on a silica wafer-SiO 2 /Si(1 1 1). No indications for bond activation were present, i.e., all probe molecules adsorb molecularly obeying 1st order kinetics. The coverage-dependent heat of adsorption has been determined accordingly. The adsorption dynamics are precursor-mediated with Kisliuk-like shapes of the adsorption probabilities at low impact energies and adsorbate-assisted adsorption at large impact energies

  3. Understanding Bonds - Denmark

    DEFF Research Database (Denmark)

    Rimmer, Nina Røhr

    2016-01-01

    Undervisningsmateriale. A bond is a debt security, similar to an ”I Owe You document” (IOU). When you purchase a bond, you are lending money to a government, municipality, corporation, federal agency or other entity known as the issuer. In return for the loan, the issuer promises to pay you...... a specified rate of interest during the life of the bond and to repay the face value of the bond (the principal) when it “matures,” or comes due. Among the types of bonds you can choose from are: Government securities, municipal bonds, corporate bonds, mortgage and asset-backed securities, federal agency...... securities and foreign government bonds....

  4. Penggunaan Limbah Kopi Sebagai Bahan Penyusun Ransum Itik Peking dalam Bentuk Wafer Ransum Komplit

    Directory of Open Access Journals (Sweden)

    Muhammad Daud

    2013-04-01

    Full Text Available Effect of coffee waste as component of compiler ration peking duck in the form of wafer complete ration ABSTRACT. Coffee waste is a by-product of coffee processing that potential to be used as feed stuff for peking duck. The weakness of this coffee waste, among others, is perishable, voluminous (bulky and the availability was fluctuated so the processing technology is needed to make this vegetable waste to be durable, easy to stored and to be given to livestock. To solve this problem vegetable waste could be formed as wafer. This research was conducted to study effectiveness of coffee waste as component of compiler ration peking duck in the form of wafer complete ration This experiment was run in completely randomized design which consist of 4 feed treatment and 3 replications.  Ration used was consisted of  P0 = wafer complete ration 0% coffee waste (control, P1 = wafer complete ration 2,5% coffee waste, P2 = wafer complete ration 5% coffee waste, and P3 = Wafer complete ration 7,5% coffee waste. The Variables observed were: physical characteristic (aroma, color, and wafer density and palatability of wafer complete ration. Data collected was analyzed with ANOVA and Duncan Range Test would be used if the result was significantly different. The result showed that the density of wafer complete ration coffee waste was significantly (P< 0.05 differences between of treatment. Mean density wafer complete ration equal to: P0= 0,52±0,03, P1 =0,67±0,04, P2 =0,72±0,03, and P3 = 0,76±0.05 g/cm3. Wafer complete ration coffee waste palatability was significantly (P< 0.05 differences between of treatment. It is concluded that of wafer complete ration composition 5 and 7,5% coffee waste was significantly wafer palatability and gave a highest wafer density. The ration P0 was the most palatable compare to other treatments for the experimental peking duck.

  5. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    International Nuclear Information System (INIS)

    Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

    2013-01-01

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

  6. Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

    Science.gov (United States)

    Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

    2018-03-01

    It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

  7. Wire bonding in microelectronics

    CERN Document Server

    Harman, George G

    2010-01-01

    Wire Bonding in Microelectronics, Third Edition, has been thoroughly revised to help you meet the challenges of today's small-scale and fine-pitch microelectronics. This authoritative guide covers every aspect of designing, manufacturing, and evaluating wire bonds engineered with cutting-edge techniques. In addition to gaining a full grasp of bonding technology, you'll learn how to create reliable bonds at exceedingly high yields, test wire bonds, solve common bonding problems, implement molecular cleaning methods, and much more. Coverage includes: Ultrasonic bonding systems and technologies, including high-frequency systems Bonding wire metallurgy and characteristics, including copper wire Wire bond testing Gold-aluminum intermetallic compounds and other interface reactions Gold and nickel-based bond pad plating materials and problems Cleaning to improve bondability and reliability Mechanical problems in wire bonding High-yield, fine-pitch, specialized-looping, soft-substrate, and extreme-temperature wire bo...

  8. Propagation of resist heating mask error to wafer level

    Science.gov (United States)

    Babin, S. V.; Karklin, Linard

    2006-10-01

    As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the

  9. A Study of the Charge Trap Transistor (CTT) for Post-Fab Modification of Wafers

    Science.gov (United States)

    2018-04-01

    AFRL-RY-WP-TR-2018-0030 A STUDY OF THE CHARGE TRAP TRANSISTOR (CTT) FOR POST- FAB MODIFICATION OF WAFERS Subramanian S. Iyer University of California...Final 13 June 2016 – 13 December 2017 4. TITLE AND SUBTITLE A STUDY OF THE CHARGE TRAP TRANSISTOR (CTT) FOR POST- FAB MODIFICATION OF WAFERS 5a. CONTRACT

  10. Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

    NARCIS (Netherlands)

    Tilmans, H.A.C.; Ziad, H.; Jansen, Henricus V.; Di Monaco, O.; Jourdain, A.; De Raedt, W.; Rottenberg, X.; De Backer, E.; Decoussernaeker, A.; Baert, K.

    2001-01-01

    Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as

  11. Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

    International Nuclear Information System (INIS)

    Brehm, L.; Kregsamer, P.; Pianetta, P.

    2000-01-01

    It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

  12. Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

  13. Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

    DEFF Research Database (Denmark)

    Mackenzie, David; Buron, Jonas Christian Due; Whelan, Patrick Rebsdorf

    2015-01-01

    Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140......-effect mobility, doping level, on–off ratio, and conductance minimum before and after laser ablation fabrication....

  14. Locally-enhanced light scattering by a monocrystalline silicon wafer

    Directory of Open Access Journals (Sweden)

    Li Ma

    2018-03-01

    Full Text Available We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

  15. Joint Research on Scatterometry and AFM Wafer Metrology

    Science.gov (United States)

    Bodermann, Bernd; Buhr, Egbert; Danzebrink, Hans-Ulrich; Bär, Markus; Scholze, Frank; Krumrey, Michael; Wurm, Matthias; Klapetek, Petr; Hansen, Poul-Erik; Korpelainen, Virpi; van Veghel, Marijn; Yacoot, Andrew; Siitonen, Samuli; El Gawhary, Omar; Burger, Sven; Saastamoinen, Toni

    2011-11-01

    Supported by the European Commission and EURAMET, a consortium of 10 participants from national metrology institutes, universities and companies has started a joint research project with the aim of overcoming current challenges in optical scatterometry for traceable linewidth metrology. Both experimental and modelling methods will be enhanced and different methods will be compared with each other and with specially adapted atomic force microscopy (AFM) and scanning electron microscopy (SEM) measurement systems in measurement comparisons. Additionally novel methods for sophisticated data analysis will be developed and investigated to reach significant reductions of the measurement uncertainties in critical dimension (CD) metrology. One final goal will be the realisation of a wafer based reference standard material for calibration of scatterometers.

  16. Coherent spin transport through a 350 micron thick silicon wafer.

    Science.gov (United States)

    Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

    2007-10-26

    We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

  17. Ambient plasma treatment of silicon wafers for surface passivation recovery

    Science.gov (United States)

    Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

  18. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    Science.gov (United States)

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  19. Development of thin film measurement program of wafer for spin etcher

    International Nuclear Information System (INIS)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

    2001-01-01

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  20. Development of thin film measurement program of wafer for spin etcher

    Energy Technology Data Exchange (ETDEWEB)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

    2001-11-15

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  1. Temperature Uniformity of Wafer on a Large-Sized Susceptor for a Nitride Vertical MOCVD Reactor

    International Nuclear Information System (INIS)

    Li Zhi-Ming; Jiang Hai-Ying; Han Yan-Bin; Li Jin-Ping; Yin Jian-Qin; Zhang Jin-Cheng

    2012-01-01

    The effect of coil location on wafer temperature is analyzed in a vertical MOCVD reactor by induction heating. It is observed that the temperature distribution in the wafer with the coils under the graphite susceptor is more uniform than that with the coils around the outside wall of the reactor. For the case of coils under the susceptor, we find that the thickness of the susceptor, the distance from the coils to the susceptor bottom and the coil turns significantly affect the temperature uniformity of the wafer. An optimization process is executed for a 3-inch susceptor with this kind of structure, resulting in a large improvement in the temperature uniformity. A further optimization demonstrates that the new susceptor structure is also suitable for either multiple wafers or large-sized wafers approaching 6 and 8 inches

  2. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    International Nuclear Information System (INIS)

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-01-01

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

  3. Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

    2009-07-01

    Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  4. Wafer size effect on material removal rate in copper CMP process

    Energy Technology Data Exchange (ETDEWEB)

    Yuh, Minjong; Jang, Soocheon; Park, Inho; Jeong, Haedo [Pusan National University, Busan (Korea, Republic of)

    2017-06-15

    The semiconductor industry has employed the Chemical mechanical planarization (CMP) to enable surface topography control. Copper has been used to build interconnects because of its low-resistivity and high-electromigration. In this study, the effect of wafer size on the Material removal rate (MRR) in copper CMP process was investigated. CMP experiments were conducted using copper blanket wafers with diameter of 100, 150, 200 and 300 mm, while temperature and friction force were measured by infrared and piezoelectric sen-sors. The MRR increases with an increase in wafer size under the same process conditions. The wafer size increased the sliding distance of pad, resulting in an increase in the process temperature. This increased the process temperature, accelerating the chemical etching rate and the dynamic etch rate. The sliding distance of the pad was proportional to the square of the wafer radius; it may be used to predict CMP results and design a CMP machine.

  5. A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

    Science.gov (United States)

    Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

    2013-03-01

    The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

  6. Application of a layout/material handling design method to a furnace area in a 300 mm wafer fab

    NARCIS (Netherlands)

    Hesen, P.M.C.; Renders, P.J.J.; Rooda, J.E.

    2001-01-01

    For many years, material handling within the semiconductor industry has become increasingly important. With the introduction of 300 mm wafer production, ergonomics and product safety become more critical. Therefore, the manufacturers of semiconductor wafer fabs are considering the automation of

  7. Edge printability: techniques used to evaluate and improve extreme wafer edge printability

    Science.gov (United States)

    Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

    2004-05-01

    The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

  8. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

    Science.gov (United States)

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-13

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  9. Low-Temperature Cu-Cu Bonding Using Silver Nanoparticles Fabricated by Physical Vapor Deposition

    Science.gov (United States)

    Wu, Zijian; Cai, Jian; Wang, Junqiang; Geng, Zhiting; Wang, Qian

    2018-02-01

    Silver nanoparticles (Ag NPs) fabricated by physical vapor deposition (PVD) were introduced in Cu-Cu bonding as surface modification layer. The bonding structure consisted of a Ti adhesive/barrier layer and a Cu substrate layer was fabricated on the silicon wafer. Ag NPs were deposited on the Cu surface by magnetron sputtering in a high-pressure environment and a loose structure with NPs was obtained. Shear tests were performed after bonding, and the influences of PVD pressure, bonding pressure, bonding temperature and annealing time on shear strength were assessed. Cu-Cu bonding with Ag NPs was accomplished at 200°C for 3 min under the pressure of 30 MPa without a post-annealing process, and the average bonding strength of 13.99 MPa was reached. According to cross-sectional observations, a void-free bonding interface with an Ag film thickness of around 20 nm was achieved. These results demonstrated that a reliable low-temperature short-time Cu-Cu bonding was realized by the sintering process of Ag NPs between the bonding pairs, which indicated that this bonding method could be a potential candidate for future ultra-fine pitch 3D integration.

  10. Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

    Science.gov (United States)

    Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

    2018-04-01

    In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

  11. Improvement of silicon direct bonding using surfaces activated by hydrogen plasma treatment

    CERN Document Server

    Choi, W B; Lee Jae Sik; Sung, M Y

    2000-01-01

    The plasma surface treatment, using hydrogen gas, of silicon wafers was studied as a pretreatment for silicon direct bonding. Chemical reactions of the hydrogen plasma with the surfaces were used for both surface activation and removal of surface contaminants. Exposure of the silicon wafers to the plasma formed an active oxide layer on the surface. This layer was hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposure time and power. The surface became smoother with shorter plasma exposure time and lower power. In addition, the plasma surface treatment was very efficient in removing the carbon contaminants on the silicon surface. The value of the initial surface energy, as estimated by using the crack propagation method, was 506 mJ/M sup 2 , which was up to about three times higher than the value for the conventional direct bonding method using wet chemical treatments.

  12. Sequential plasma activation methods for hydrophilic direct bonding at sub-200 °C

    Science.gov (United States)

    He, Ran; Yamauchi, Akira; Suga, Tadatomo

    2018-02-01

    We present our newly developed sequential plasma activation methods for hydrophilic direct bonding of silica glasses and thermally grown SiO2 films. N2 plasma was employed to introduce a metastable oxynitride layer on wafer surfaces for the improvement of bond energy. By using either O2-plasma/N2-plasma/N-radical or N2-plasma/N-radical sequential activation, the quartz-quartz bond energy was increased from 2.7 J/m2 to close to the quartz bulk fracture energy that was estimated to be around 9.0 J/m2 after post-bonding annealing at 200 °C. The silicon bulklike bond energy between thermal SiO2 films was also obtained. We suggest that the improvement is attributable to surface modification such as N-related defect formation and asperity softening by the N2 plasma surface treatment.

  13. TXRF with synchrotron radiation. Analysis of Ni on Si-wafer surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Wobrauschek, P [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Kregsamer, P [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Ladisich, W [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Streli, C [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Pahlke, S [Wacker Chemitronic GmbH, D-84479 Burghausen (Germany); Fabry, L [Wacker Chemitronic GmbH, D-84479 Burghausen (Germany); Garbe, S [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Haller, M [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Knoechel, A [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Radtke, M [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany)

    1995-09-11

    SR-TXRF (Synchrotron Radiation excited Total Reflection X-ray Fluorescence Analysis) with monoenergetic radiation produced by a W/C multilayer monochromator has been applied to the analysis of Ni on a Si-wafer surface. An intentionally contaminated wafer with 100 pg has been used to determine the detection limits. 13 fg have been achieved for Ni at a beam current of 73 mA and extrapolated to 1000 s. This technique simulates the sample preparation technique of Vapour Phase Decomposition (VPD) on a wafer surface. (orig.).

  14. TXRF with synchrotron radiation. Analysis of Ni on Si-wafer surfaces

    International Nuclear Information System (INIS)

    Wobrauschek, P.; Kregsamer, P.; Ladisich, W.; Streli, C.; Pahlke, S.; Fabry, L.; Garbe, S.; Haller, M.; Knoechel, A.; Radtke, M.

    1995-01-01

    SR-TXRF (Synchrotron Radiation excited Total Reflection X-ray Fluorescence Analysis) with monoenergetic radiation produced by a W/C multilayer monochromator has been applied to the analysis of Ni on a Si-wafer surface. An intentionally contaminated wafer with 100 pg has been used to determine the detection limits. 13 fg have been achieved for Ni at a beam current of 73 mA and extrapolated to 1000 s. This technique simulates the sample preparation technique of Vapour Phase Decomposition (VPD) on a wafer surface. (orig.)

  15. A modified occlusal wafer for managing partially dentate orthognathic patients--a case series.

    Science.gov (United States)

    Soneji, Bhavin Kiritkumar; Esmail, Zaid; Sharma, Pratik

    2015-03-01

    A multidisciplinary approach is essential in orthognathic surgery to achieve stable and successful outcomes. The model surgery planning is an important aspect in achieving the desired aims. An occlusal wafer used at the time of surgery aids the surgeon during correct placement of the jaws. When dealing with partially dentate patients, the design of the occlusal wafer requires modification to appropriately position the jaw. Two cases with partially dentate jaws are presented in which the occlusal wafer has been modified to provide stability at the time of surgery.

  16. Direct, CMOS In-Line Process Flow Compatible, Sub 100 °C Cu-Cu Thermocompression Bonding Using Stress Engineering

    Science.gov (United States)

    Panigrahi, Asisa Kumar; Ghosh, Tamal; Kumar, C. Hemanth; Singh, Shiv Govind; Vanjari, Siva Rama Krishna

    2018-05-01

    Diffusion of atoms across the boundary between two bonding layers is the key for achieving excellent thermocompression Wafer on Wafer bonding. In this paper, we demonstrate a novel mechanism to increase the diffusion across the bonding interface and also shows the CMOS in-line process flow compatible Sub 100 °C Cu-Cu bonding which is devoid of Cu surface treatment prior to bonding. The stress in sputtered Cu thin films was engineered by adjusting the Argon in-let pressure in such a way that one film had a compressive stress while the other film had tensile stress. Due to this stress gradient, a nominal pressure (2 kN) and temperature (75 °C) was enough to achieve a good quality thermocompression bonding having a bond strength of 149 MPa and very low specific contact resistance of 1.5 × 10-8 Ω-cm2. These excellent mechanical and electrical properties are resultant of a high quality Cu-Cu bonding having grain growth between the Cu films across the boundary and extended throughout the bonded region as revealed by Cross-sectional Transmission Electron Microscopy. In addition, reliability assessment of Cu-Cu bonding with stress engineering was demonstrated using multiple current stressing and temperature cycling test, suggests excellent reliable bonding without electrical performance degradation.

  17. Direct, CMOS In-Line Process Flow Compatible, Sub 100 °C Cu-Cu Thermocompression Bonding Using Stress Engineering

    Science.gov (United States)

    Panigrahi, Asisa Kumar; Ghosh, Tamal; Kumar, C. Hemanth; Singh, Shiv Govind; Vanjari, Siva Rama Krishna

    2018-03-01

    Diffusion of atoms across the boundary between two bonding layers is the key for achieving excellent thermocompression Wafer on Wafer bonding. In this paper, we demonstrate a novel mechanism to increase the diffusion across the bonding interface and also shows the CMOS in-line process flow compatible Sub 100 °C Cu-Cu bonding which is devoid of Cu surface treatment prior to bonding. The stress in sputtered Cu thin films was engineered by adjusting the Argon in-let pressure in such a way that one film had a compressive stress while the other film had tensile stress. Due to this stress gradient, a nominal pressure (2 kN) and temperature (75 °C) was enough to achieve a good quality thermocompression bonding having a bond strength of 149 MPa and very low specific contact resistance of 1.5 × 10-8 Ω-cm2. These excellent mechanical and electrical properties are resultant of a high quality Cu-Cu bonding having grain growth between the Cu films across the boundary and extended throughout the bonded region as revealed by Cross-sectional Transmission Electron Microscopy. In addition, reliability assessment of Cu-Cu bonding with stress engineering was demonstrated using multiple current stressing and temperature cycling test, suggests excellent reliable bonding without electrical performance degradation.

  18. Bonding with Your Baby

    Science.gov (United States)

    ... the future bonding of the child and parent. Adoptive parents may be concerned about bonding with their ... general emotional support. And it's OK to ask family members and friends for help in the days — ...

  19. Fabrication of a microfluidic chip by UV bonding at room temperature for integration of temperature-sensitive layers

    Science.gov (United States)

    Schlautmann, S.; Besselink, G. A. J.; Radhakrishna Prabhu, G.; Schasfoort, R. B. M.

    2003-07-01

    A method for the bonding of a microfluidic device at room temperature is presented. The wafer with the fluidic structures was bonded to a sensor wafer with gold pads by means of adhesive bonding, utilizing an UV-curable glue layer. To avoid filling the fluidic channels with the glue, a stamping process was developed which allows the selective application of a thin glue layer. In this way a microfluidic glass chip was fabricated that could be used for performing surface plasmon resonance measurements without signs of leakage. The advantage of this method is the possibility of integration of organic layers as well as other temperature-sensitive layers into a microfluidic glass device.

  20. Australia's Bond Home Bias

    OpenAIRE

    Anil V. Mishra; Umaru B. Conteh

    2014-01-01

    This paper constructs the float adjusted measure of home bias and explores the determinants of bond home bias by employing the International Monetary Fund's high quality dataset (2001 to 2009) on cross-border bond investment. The paper finds that Australian investors' prefer investing in countries with higher economic development and more developed bond markets. Exchange rate volatility appears to be an impediment for cross-border bond investment. Investors prefer investing in countries with ...

  1. A metallic buried interconnect process for through-wafer interconnection

    International Nuclear Information System (INIS)

    Ji, Chang-Hyeon; Herrault, Florian; Allen, Mark G

    2008-01-01

    In this paper, we present the design, fabrication process and experimental results of electroplated metal interconnects buried at the bottom of deep silicon trenches with vertical sidewalls. A manual spray-coating process along with a unique trench-formation process has been developed for the electroplating of a metal interconnection structure at the bottom surface of the deep trenches. The silicon etch process combines the isotropic dry etch process and conventional Bosch process to fabricate a deep trench with angled top-side edges and vertical sidewalls. The resulting trench structure, in contrast to the trenches fabricated by wet anisotropic etching, enables spray-coated photoresist patterning with good sidewall and top-side edge coverage while maintaining the ability to form a high-density array of deep trenches without excessive widening of the trench opening. A photoresist spray-coating process was developed and optimized for the formation of electroplating mold at the bottom of 300 µm deep trenches having vertical sidewalls. A diluted positive tone photoresist with relatively high solid content and multiple coating with baking between coating steps has been experimentally proven to provide high quality sidewall and edge coverage. To validate the buried interconnect approach, a three-dimensional daisy chain structure having a buried interconnect as the bottom connector and traces on the wafer surface as the top conductor has been designed and fabricated

  2. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2017-05-10

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

  3. Phenylacetylene and H bond

    Indian Academy of Sciences (India)

    ... all resembling H bonds. Non-linear H bonds due to secondary interactions. C-H stretching frequency shows blue shift. Heavy atom distances are longer than the sum of van der Waals radii. Formed a task group through IUPAC to come up with a modern definition of H bond. 15 international experts including Desiraju.

  4. Chemical bond fundamental aspects of chemical bonding

    CERN Document Server

    Frenking, Gernot

    2014-01-01

    This is the perfect complement to ""Chemical Bonding - Across the Periodic Table"" by the same editors, who are two of the top scientists working on this topic, each with extensive experience and important connections within the community. The resulting book is a unique overview of the different approaches used for describing a chemical bond, including molecular-orbital based, valence-bond based, ELF, AIM and density-functional based methods. It takes into account the many developments that have taken place in the field over the past few decades due to the rapid advances in quantum chemica

  5. Characterization and control of wafer charging effects during high-current ion implantation

    International Nuclear Information System (INIS)

    Current, M.I.; Lukaszek, W.; Dixon, W.; Vella, M.C.; Messick, C.; Shideler, J.; Reno, S.

    1994-02-01

    EEPROM-based sense and memory devices provide direct measures of the charge flow and potentials occurring on the surface of wafers during ion beam processing. Sensor design and applications for high current ion implantation are discussed

  6. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    Science.gov (United States)

    Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL

    2011-07-12

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  7. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming; Zhong, Zhaowei; Diallo, Elhadj; Wang, Zhihong; Yue, Weisheng

    2014-01-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  8. Fabrication of high aspect ratio through-wafer copper interconnects by reverse pulse electroplating

    International Nuclear Information System (INIS)

    Gu, Changdong; Zhang, Tong-Yi; Xu, Hui

    2009-01-01

    This study aims to fabricate high aspect ratio through-wafer copper interconnects by a simple reverse pulse electroplating technique. High aspect-ratio (∼18) through-wafer holes obtained by a two-step deep reactive ion etching (DRIE) process exhibit a taper profile, which might automatically optimize the local current density distribution during the electroplating process, thereby achieving void-free high aspect-ratio copper vias

  9. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming

    2014-10-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  10. Nonuniformities of electrical resistivity in undoped 6H-SiC wafers

    International Nuclear Information System (INIS)

    Li, Q.; Polyakov, A.Y.; Skowronski, M.; Sanchez, E.K.; Loboda, M.J.; Fanton, M.A.; Bogart, T.; Gamble, R.D.

    2005-01-01

    Chemical elemental analysis, temperature-dependent Hall measurements, deep-level transient spectroscopy, and contactless resistivity mapping were performed on undoped semi-insulating (SI) and lightly nitrogen-doped conducting 6H-SiC crystals grown by physical vapor transport (PVT). Resistivity maps of commercial semi-insulating SiC wafers revealed resistivity variations across the wafers between one and two orders of magnitude. Two major types of variations were identified. First is the U-shape distribution with low resistivity in the center and high in the periphery of the wafer. The second type had an inverted U-shape distribution. Secondary-ion-mass spectrometry measurements of the distribution of nitrogen concentration along the growth axis and across the wafers sliced from different locations of lightly nitrogen-doped 6H-SiC boules were conducted. The measured nitrogen concentration gradually decreased along the growth direction and from the center to the periphery of the wafers. This change gives rise to the U-like distribution of resistivity in wafers of undoped SI-SiC. The concentrations of deep electron traps exhibited similar dependence. Compensation of nitrogen donors by these traps can result in the inverted U-like distribution of resistivity. Possible reasons for the observed nonuniformities include formation of a (0001) facet in PVT growth coupled with orientation-dependent nitrogen incorporation, systematic changes of the gas phase composition, and increase of the deposition temperature during boule growth

  11. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    Science.gov (United States)

    Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

    2013-01-01

    Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

  12. A wafer mapping technique for residual stress in surface micromachined films

    International Nuclear Information System (INIS)

    Schiavone, G; Murray, J; Smith, S; Walton, A J; Desmulliez, M P Y; Mount, A R

    2016-01-01

    The design of MEMS devices employing movable structures is crucially dependant on the mechanical behaviour of the deposited materials. It is therefore important to be able to fully characterize the micromachined films and predict with confidence the mechanical properties of patterned structures. This paper presents a characterization technique that enables the residual stress in MEMS films to be mapped at the wafer level by using microstructures released by surface micromachining. These dedicated MEMS test structures and the associated measurement techniques are used to extract localized information on the strain and Young’s modulus of the film under investigation. The residual stress is then determined by numerically coupling this data with a finite element analysis of the structure. This paper illustrates the measurement routine and demonstrates it with a case study using electrochemically deposited alloys of nickel and iron, particularly prone to develop high levels of residual stress. The results show that the technique enables wafer mapping of film non-uniformities and identifies wafer-to-wafer differences. A comparison between the results obtained from the mapping technique and conventional wafer bow measurements highlights the benefits of using a procedure tailored to films that are non-uniform, patterned and surface-micromachined, as opposed to simple standard stress extraction methods. The presented technique reveals detailed information that is generally unexplored when using conventional stress extraction methods such as wafer bow measurements. (paper)

  13. Evaluation of a cyanoacrylate dressing to manage peristomal skin alterations under ostomy skin barrier wafers.

    Science.gov (United States)

    Milne, Catherine T; Saucier, Darlene; Trevellini, Chenel; Smith, Juliet

    2011-01-01

    Peristomal skin alterations under ostomy barrier wafers are a commonly reported problem. While a number of interventions to manage this issue have been reported, the use of a topically applied cyanoacrylate has received little attention. This case series describes the use of a topical cyanoacrylate for the management of peristomal skin alterations in persons living with an ostomy. Using a convenience sample, the topical cyanoacrylate dressing was applied to 11 patients with peristomal skin disruption under ostomy wafers in acute care and outpatient settings. The causes of barrier function interruption were also addressed to enhance outcomes. Patients were assessed for wound discomfort using a Likert Scale, time to healing, and number of appliance changes. Patient satisfaction was also examined. Average reported discomfort levels were 9.5 out of 10 at the initial peristomal irritation assessment visit decreased to 3.5 at the first wafer change and were absent by the second wafer change. Wafers had increasing wear time between changes in both settings with acute care patients responding faster. Epidermal resurfacing occurred within 10.2 days in outpatients and within 7 days in acute care patients. Because of the skin sealant action of this dressing, immediate adherence of the wafer was reported at all pouch changes.

  14. DynAMITe: a wafer scale sensor for biomedical applications

    International Nuclear Information System (INIS)

    Esposito, M; Wells, K; Anaxagoras, T; Fant, A; Allinson, N M; Konstantinidis, A; Speller, R D; Osmond, J P F; Evans, P M

    2011-01-01

    In many biomedical imaging applications Flat Panel Imagers (FPIs) are currently the most common option. However, FPIs possess several key drawbacks such as large pixels, high noise, low frame rates, and excessive image artefacts. Recently Active Pixel Sensors (APS) have gained popularity overcoming such issues and are now scalable up to wafer size by appropriate reticule stitching. Detectors for biomedical imaging applications require high spatial resolution, low noise and high dynamic range. These figures of merit are related to pixel size and as the pixel size is fixed at the time of the design, spatial resolution, noise and dynamic range cannot be further optimized. The authors report on a new rad-hard monolithic APS, named DynAMITe (Dynamic range Adjustable for Medical Imaging Technology), developed by the UK MI-3 Plus consortium. This large area detector (12.8 cm × 12.8 cm) is based on the use of two different diode geometries within the same pixel array with different size pixels (50 μm and 100 μm). Hence the resulting device can possess two inherently different resolutions each with different noise and saturation performance. The small and the large pixel cameras can be reset at different voltages, resulting in different depletion widths. The larger depletion width for the small pixels allows the initial generated photo-charge to be promptly collected, which ensures an intrinsically lower noise and higher spatial resolution. After these pixels reach near saturation, the larger pixels start collecting so offering a higher dynamic range whereas the higher noise floor is not important as at higher signal levels performance is governed by the Poisson noise of the incident radiation beam. The overall architecture and detailed characterization of DynAMITe will be presented in this paper.

  15. The Au/Si eutectic bonding compatibility with KOH etching for 3D devices fabrication

    Science.gov (United States)

    Liang, Hengmao; Liu, Mifeng; Liu, Song; Xu, Dehui; Xiong, Bin

    2018-01-01

    KOH etching and Au/Si eutectic bonding are cost-efficient technologies for 3D device fabrication. Aimed at investigating the process compatibility of KOH etching and Au/Si bonding, KOH etching tests have been carried out for Au/bulk Si and Au/amorphous Si (a-Si) bonding wafers in this paper. For the Au/bulk Si bonding wafer, a serious underetch phenomenon occurring on the damage layer in KOH etching definitely results in packaging failure. In the microstructure analysis, it is found that the formation of the damage layer between the bonded layer and bulk Si is attributed to the destruction of crystal Si lattices in Au/bulk Si eutectic reaction. Considering the occurrence of underetch for Au/Si bonding must meet two requirements: the superfluous Si and the defective layer near the bonded layer, the Au/a-Si bonding by regulating the a-Si/Au thickness ratio is presented in this study. Only when the a-Si/Au thickness ratio is relatively low are there not underetch phenomena, of which the reason is the full reaction of the a-Si layer avoiding the formation of the damage layer for easy underetch. Obviously, the Au/a-Si bonding via choosing a moderate a-Si/Au thickness ratio (⩽1.5:1 is suggested) could be reliably compatible with KOH etching, which provides an available and low-cost approach for 3D device fabrication. More importantly, the theory of the damage layer proposed in this study can be naturally applied to relevant analyses on the eutectic reaction of other metals and single crystal materials.

  16. P/N InP solar cells on Ge wafers

    Science.gov (United States)

    Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

    1994-01-01

    Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

  17. BONDING ALUMINUM METALS

    Science.gov (United States)

    Noland, R.A.; Walker, D.E.

    1961-06-13

    A process is given for bonding aluminum to aluminum. Silicon powder is applied to at least one of the two surfaces of the two elements to be bonded, the two elements are assembled and rubbed against each other at room temperature whereby any oxide film is ruptured by the silicon crystals in the interface; thereafter heat and pressure are applied whereby an aluminum-silicon alloy is formed, squeezed out from the interface together with any oxide film, and the elements are bonded.

  18. Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

    Science.gov (United States)

    Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

    2018-03-01

    The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

  19. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    Directory of Open Access Journals (Sweden)

    Lim SCB

    2013-04-01

    Full Text Available Stephen CB Lim,1,3 Michael J Paech,2 Bruce Sunderland,3 Yandi Liu3 1Pharmacy Department, Armadale Health Service, Armadale, 2School of Medicine and Pharmacology, University of Western Australia, and Department of Anaesthesia and Pain Medicine, King Edward Memorial Hospital for Women, Subiaco, 3School of Pharmacy, Curtin Health Innovation Research Institute, Curtin University, Perth, WA, Australia Background: The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods: The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results: In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion: These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. Keywords: absolute bioavailability, fentanyl wafer, in vitro dissolution, in vivo study, pharmacokinetics, sublingual

  20. Copper wire bonding

    CERN Document Server

    Chauhan, Preeti S; Zhong, ZhaoWei; Pecht, Michael G

    2014-01-01

    This critical volume provides an in-depth presentation of copper wire bonding technologies, processes and equipment, along with the economic benefits and risks.  Due to the increasing cost of materials used to make electronic components, the electronics industry has been rapidly moving from high cost gold to significantly lower cost copper as a wire bonding material.  However, copper wire bonding has several process and reliability concerns due to its material properties.  Copper Wire Bonding book lays out the challenges involved in replacing gold with copper as a wire bond material, and includes the bonding process changes—bond force, electric flame off, current and ultrasonic energy optimization, and bonding tools and equipment changes for first and second bond formation.  In addition, the bond–pad metallurgies and the use of bare and palladium-coated copper wires on aluminum are presented, and gold, nickel and palladium surface finishes are discussed.  The book also discusses best practices and re...

  1. Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

    International Nuclear Information System (INIS)

    Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

    2000-01-01

    Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

  2. X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

    Science.gov (United States)

    Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); King, Glen C. (Inventor); Choi, Sang Hyouk (Inventor)

    2017-01-01

    An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

  3. A quality quantitative method of silicon direct bonding based on wavelet image analysis

    Science.gov (United States)

    Tan, Xiao; Tao, Zhi; Li, Haiwang; Xu, Tiantong; Yu, Mingxing

    2018-04-01

    The rapid development of MEMS (micro-electro-mechanical systems) has received significant attention from researchers in various fields and subjects. In particular, the MEMS fabrication process is elaborate and, as such, has been the focus of extensive research inquiries. However, in MEMS fabrication, component bonding is difficult to achieve and requires a complex approach. Thus, improvements in bonding quality are relatively important objectives. A higher quality bond can only be achieved with improved measurement and testing capabilities. In particular, the traditional testing methods mainly include infrared testing, tensile testing, and strength testing, despite the fact that using these methods to measure bond quality often results in low efficiency or destructive analysis. Therefore, this paper focuses on the development of a precise, nondestructive visual testing method based on wavelet image analysis that is shown to be highly effective in practice. The process of wavelet image analysis includes wavelet image denoising, wavelet image enhancement, and contrast enhancement, and as an end result, can display an image with low background noise. In addition, because the wavelet analysis software was developed with MATLAB, it can reveal the bonding boundaries and bonding rates to precisely indicate the bond quality at all locations on the wafer. This work also presents a set of orthogonal experiments that consist of three prebonding factors, the prebonding temperature, the positive pressure value and the prebonding time, which are used to analyze the prebonding quality. This method was used to quantify the quality of silicon-to-silicon wafer bonding, yielding standard treatment quantities that could be practical for large-scale use.

  4. Impedance-based structural health monitoring of additive manufactured structures with embedded piezoelectric wafers

    Science.gov (United States)

    Scheyer, Austin G.; Anton, Steven R.

    2017-04-01

    Embedding sensors within additive manufactured (AM) structures gives the ability to develop smart structures that are capable of monitoring the mechanical health of a system. AM provides an opportunity to embed sensors within a structure during the manufacturing process. One major limitation of AM technology is the ability to verify the geometric and material properties of fabricated structures. Over the past several years, the electromechanical impedance (EMI) method for structural health monitoring (SHM) has been proven to be an effective method for sensing damage in structurers. The EMI method utilizes the coupling between the electrical and mechanical properties of a piezoelectric transducer to detect a change in the dynamic response of a structure. A piezoelectric device, usually a lead zirconate titanate (PZT) ceramic wafer, is bonded to a structure and the electrical impedance is measured across as range of frequencies. A change in the electrical impedance is directly correlated to changes made to the mechanical condition of the structure. In this work, the EMI method is employed on piezoelectric transducers embedded inside AM parts to evaluate the feasibility of performing SHM on parts fabricated using additive manufacturing. The fused deposition modeling (FDM) method is used to print specimens for this feasibility study. The specimens are printed from polylactic acid (PLA) in the shape of a beam with an embedded monolithic piezoelectric ceramic disc. The specimen is mounted as a cantilever while impedance measurements are taken using an HP 4194A impedance analyzer. Both destructive and nondestructive damage is simulated in the specimens by adding an end mass and drilling a hole near the free end of the cantilever, respectively. The Root Mean Square Deviation (RMSD) method is utilized as a metric for quantifying damage to the system. In an effort to determine a threshold for RMSD, the values are calculated for the variation associated with taking multiple

  5. 120 mm Single-crystalline perovskite and wafers: towards viable applications

    Institute of Scientific and Technical Information of China (English)

    Yucheng Liu; Bo Wang; Qingbo Wei; Fengwei Xiao; Haibo Fan; Hao Deng; Liangping Deng; Shengzhong (Frank) Liu; Xiaodong Ren; Jing Zhang; Zhou Yang; Dong Yang; Fengyang Yu; Jiankun Sun; Changming Zhao; Zhun Yao

    2017-01-01

    As the large single-crystalline silicon wafers have revolutionized many industries including electronics and solar cells,it is envisioned that the availability of large single-crystalline perovskite crystals and wafers will revolutionize its broad applications in photovoltaics,optoelectronics,lasers,photodetectors,light emitting diodes (LEDs),etc.Here we report a method to grow large single-crystalline perovskites including single-halide crystals:CH3NH3PbX3 (X=Ⅰ,Br,Cl),and dual-halide ones:CH3NH3Pb(ClxBr1-x)3 and CH3NH3Pb(BrxI1-x)3,with the largest crystal being 120 mm in length.Meanwhile,we have advanced a process to slice the large perovskite crystals into thin wafers.It is found that the wafers exhibit remarkable features:(1) its trap-state density is a million times smaller than that in the microcrystalline perovskite thin films (MPTF);(2) its carrier mobility is 410 times higher than its most popular organic counterpart P3HT;(3) its optical absorption is expanded to as high as 910 nm comparing to 797 nm for the MPTF;(4) while MPTF decomposes at 150 ℃,the wafer is stable at high temperature up to 270 ℃;(5) when exposed to high humidity (75% RH),MPTF decomposes in 5 h while the wafer shows no change for overnight;(6) its photocurrent response is 250 times higher than its MPTF counterpart.A few electronic devices have been fabricated using the crystalline wafers.Among them,the Hall test gives low carrier concentration with high mobility.The trap-state density is measured much lower than common semiconductors.Moreover,the large SC-wafer is found particularly useful for mass production of integrated circuits.By adjusting the halide composition,both the optical absorption and the light emission can be fine-tuned across the entire visible spectrum from 400 nm to 800 nm.It is envisioned that a range of visible lasers and LEDs may be developed using the dual-halide perovskites.With fewer trap states,high mobility,broader absorption,and humidity resistance,it is

  6. Qualification of multi-crystalline silicon wafers by optical imaging for industrial use

    Energy Technology Data Exchange (ETDEWEB)

    Janssen, G.J.M.; Van der Borg, N.J.C.M.; Manshanden, P.; De Bruijne, M.; Bende, E.E. [ECN Solar Energy, Petten (Netherlands)

    2012-09-15

    We have developed a method to qualify multi-crystalline silicon (mc-Si) wafers that are being used in a production process. An optical image of an etched wafer is made. This etching can be a standard industrial acid etching for mc-Si wafers as is commonly used for saw damage removal and simultaneous iso-texturing. Digital image processing is then applied to identify the number of dislocations and their distribution over the wafer. This information is used as input for a cell performance prediction model, where the performance is characterized by the open circuit voltage (Voc) or the efficiency. The model can include various levels of sophistication, i.e. from using an average density of dislocations to the full spatial resolution of the dislocations in a 2D simulation that includes also the metallization pattern on the cell. The predicted performance is then evaluated against pre-selected criteria. The possibility to apply this optical qualification method in an initial stage in the production enables early rejection of the wafers, further tailoring of the cell production process or identification of instabilities in the production process.

  7. Palladium-based on-wafer electroluminescence studies of GaN-based LED structures

    Energy Technology Data Exchange (ETDEWEB)

    Salcianu, C.O.; Thrush, E.J.; Humphreys, C.J. [Department of Materials Science and Metallurgy, University of Cambridge, Pembroke Street, Cambridge CB2 3QZ (United Kingdom); Plumb, R.G. [Centre for Photonic Systems, Department of Engineering, University of Cambridge, Cambridge CB3 0FD (United Kingdom); Boyd, A.R.; Rockenfeller, O.; Schmitz, D.; Heuken, M. [AIXTRON AG, Kackertstr. 15-17, 52072 Aachen (Germany)

    2008-07-01

    Electroluminescence (EL) testing of Light Emitting Diode (LED) structures is usually done at the chip level. Assessing the optical and electrical properties of LED structures at the wafer scale prior to their processing would improve the cost effectiveness of producing LED-lamps. A non-destructive method for studying the luminescence properties of the structure at the wafer-scale is photoluminescence (PL). However, the relationship between the on-wafer PL data and the final device EL can be less than straightforward (Y. H Aliyu et al., Meas. Sci. Technol. 8, 437 (1997)) as the two techniques employ different carrier injection mechanisms. This paper provides an overview of some different techniques in which palladium is used as a contact in order to obtain on-wafer electroluminescence information which could be used to screen wafers prior to processing into final devices. Quick mapping of the electrical and optical characteristics was performed using either palladium needle electrodes directly, or using the latter in conjunction with evaporated palladium contacts to inject both electrons and holes into the active region via the p-type capping layer of the structure. For comparison, indium was also used to make contact to the n-layer so that electrons could be directly injected into that layer. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  8. Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

    International Nuclear Information System (INIS)

    Yoon, Sang Won; Lee, Sangwoo; Najafi, Khalil; Perkins, Noel C

    2011-01-01

    This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped–clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm 2 footprint. The contact resistance ranges from 4–11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

  9. Transversely Compressed Bonded Joints

    DEFF Research Database (Denmark)

    Hansen, Christian Skodborg; Schmidt, Jacob Wittrup; Stang, Henrik

    2012-01-01

    The load capacity of bonded joints can be increased if transverse pressure is applied at the interface. The transverse pressure is assumed to introduce a Coulomb-friction contribution to the cohesive law for the interface. Response and load capacity for a bonded single-lap joint was derived using...

  10. Corporate Bonds in Denmark

    DEFF Research Database (Denmark)

    Tell, Michael

    2015-01-01

    Corporate financing is the choice between capital generated by the corporation and capital from external investors. However, since the financial crisis shook the markets in 2007–2008, financing opportunities through the classical means of financing have decreased. As a result, corporations have...... to think in alternative ways such as issuing corporate bonds. A market for corporate bonds exists in countries such as Norway, Germany, France, the United Kingdom and the United States, while Denmark is still behind in this trend. Some large Danish corporations have instead used foreign corporate bonds...... markets. However, NASDAQ OMX has introduced the First North Bond Market in December 2012 and new regulatory framework came into place in 2014, which may contribute to a Danish based corporate bond market. The purpose of this article is to present the regulatory changes in Denmark in relation to corporate...

  11. Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

    Science.gov (United States)

    Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

    2013-11-22

    Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

  12. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    Science.gov (United States)

    Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

    2017-04-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

  13. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    International Nuclear Information System (INIS)

    Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

    2017-01-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

  14. Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

    International Nuclear Information System (INIS)

    Wang, D.; Ueda, A.; Takada, H.; Nakashima, H.

    2006-01-01

    A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τ g ) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron-hole droplet in the band-edge emission

  15. Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

    Science.gov (United States)

    Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

    2018-06-01

    Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

  16. Design and implementation of a S-parameter wafer defect scanner

    International Nuclear Information System (INIS)

    Naik, P.S.; Beling, C.D.; Fung, S.

    2004-01-01

    We describe the design and implementation of a real-time automated scanning system that gives an S-parameter image of a semiconductor wafer, thus allowing the density of vacancy type defects to be shown as a function of position on the wafer. A conventional 22 Na positron source of 0.5 mm diameter rasters across 5 x 5 cm 2 region of two times per hour in rectilinear motion. Gamma ray energies E γ are processed using a standard HP Ge spectroscopy system and a 14 bit nuclear ADC. Over a period of 1-2 days a high resolution 128 x 128 pixel image with 256 colours (scaled to the S-parameter range) can be formed as a wafer defect map. The system is reliable, interactive and user-friendly (patent pending 2003). (orig.)

  17. Wafer defect detection by a polarization-insensitive external differential interference contrast module.

    Science.gov (United States)

    Nativ, Amit; Feldman, Haim; Shaked, Natan T

    2018-05-01

    We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

  18. Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

    Science.gov (United States)

    Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

    2018-05-01

    A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

  19. Bonding temperature dependence of GaInAsP/InP laser diode grown on hydrophilically directly bonded InP/Si substrate

    Science.gov (United States)

    Aikawa, Masaki; Onuki, Yuya; Hayasaka, Natsuki; Nishiyama, Tetsuo; Kamada, Naoki; Han, Xu; Kallarasan Periyanayagam, Gandhi; Uchida, Kazuki; Sugiyama, Hirokazu; Shimomura, Kazuhiko

    2018-02-01

    The bonding-temperature-dependent lasing characteristics of 1.5 a µm GaInAsP laser diode (LD) grown on a directly bonded InP/Si substrate were successfully obtained. We have fabricated the InP/Si substrate using a direct hydrophilic wafer bonding technique at bonding temperatures of 350, 400, and 450 °C, and deposited GaInAsP/InP double heterostructure layers on this InP/Si substrate. The surface conditions, X-ray diffraction (XRD) analysis, photoluminescence (PL) spectra, and electrical characteristics after the growth were compared at these bonding temperatures. No significant differences were confirmed in X-ray diffraction analysis and PL spectra at these bonding temperatures. We realized the room-temperature lasing of the GaInAsP LD on the InP/Si substrate bonded at 350 and 400 °C. The threshold current densities were 4.65 kA/cm2 at 350 °C and 4.38 kA/cm2 at 400 °C. The electrical resistance was found to increase with annealing temperature.

  20. Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

    Science.gov (United States)

    Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

    2004-08-01

    The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

  1. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

    Science.gov (United States)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-12-10

    To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

  2. Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

    Science.gov (United States)

    Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

    2012-03-01

    Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

  3. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

    2015-01-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  4. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    International Nuclear Information System (INIS)

    Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

    2014-01-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  5. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  6. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

    International Nuclear Information System (INIS)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-01-01

    To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

  7. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  8. EM Simulation Accuracy Enhancement for Broadband Modeling of On-Wafer Passive Components

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Jiang, Chenhui; Hadziabdic, Dzenan

    2007-01-01

    This paper describes methods for accuracy enhancement in broadband modeling of on-wafer passive components using electromagnetic (EM) simulation. It is shown that standard excitation schemes for integrated component simulation leads to poor correlation with on-wafer measurements beyond the lower...... GHz frequency range. We show that this is due to parasitic effects and higher-order modes caused by the excitation schemes. We propose a simple equivalent circuit for the parasitic effects in the well-known ground ring excitation scheme. An extended L-2L calibration method is shown to improve...

  9. Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

    International Nuclear Information System (INIS)

    Casse, G.; Glaser, M.; Lemeilleur, F.; Ruzin, A.; Wegrzecki, M.

    1999-01-01

    The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10 17 atoms cm -3 ) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO 2 layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 μm thick silicon wafer

  10. Novel SU-8 based vacuum wafer-level packaging for MEMS devices

    DEFF Research Database (Denmark)

    Murillo, Gonzalo; Davis, Zachary James; Keller, Stephan Urs

    2010-01-01

    This work presents a simple and low-cost SU-8 based wafer-level vacuum packaging method which is CMOS and MEMS compatible. Different approaches have been investigated by taking advantage of the properties of SU-8, such as chemical resistance, optical transparence, mechanical reliability and versa......This work presents a simple and low-cost SU-8 based wafer-level vacuum packaging method which is CMOS and MEMS compatible. Different approaches have been investigated by taking advantage of the properties of SU-8, such as chemical resistance, optical transparence, mechanical reliability...

  11. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  12. Glass frit bonding with controlled width and height using a two-step wet silicon etching procedure

    Science.gov (United States)

    Yifang, Liu; Daner, Chen; Liwei, Lin; Gaofeng, Zheng; Jianyi, Zheng; Lingyun, Wang; Daoheng, Sun

    2016-03-01

    A simple and versatile two-step silicon wet etching technique for the control of the width and height of the glass frit bonding layer has been developed to improve bonding strength and reliability in wafer-level microelectromechanical systems (MEMS) packaging processes. The height of the glass frit bonding layer is set by the design of a vertical reference wall which regulates the distance between the silicon wafer and the encapsulation capping substrate. On the other hand, the width of the bonding layer is constrained between two micro grooves which are used to accommodate the spillages of extra glass frit during the bonding process. An optimized thermal bonding process, including the formation of glass liquid, removal of gas bubbles under vacuum and the filling of voids under normal atmospheric condition has been developed to suppress the formation of the bubbles/voids. The stencil printing and pre-sintering processes for the glass frit have been characterized before the thermal bonding process under different magnitudes of bonding pressure. The bonding gap thickness is found to be equal to the height of the reference wall of 10 μm in the prototype design. The bubbles/voids are found to be suppressed effectively and the bonding strength increases from 10.2 to 19.1 MPa as compared with a conventional thermal annealing process in air. Experimentally, prototype samples are measured to have passed the high hermetic sealing leakage tests of 5  ×  10-8 atm cc s-1.

  13. Thin film metal sensors in fusion bonded glass chips for high-pressure microfluidics

    International Nuclear Information System (INIS)

    Andersson, Martin; Ek, Johan; Hedman, Ludvig; Johansson, Fredrik; Sehlstedt, Viktor; Stocklassa, Jesper; Snögren, Pär; Pettersson, Victor; Larsson, Jonas; Vizuete, Olivier; Hjort, Klas; Klintberg, Lena

    2017-01-01

    High-pressure microfluidics offers fast analyses of thermodynamic parameters for compressed process solvents. However, microfluidic platforms handling highly compressible supercritical CO 2 are difficult to control, and on-chip sensing would offer added control of the devices. Therefore, there is a need to integrate sensors into highly pressure tolerant glass chips. In this paper, thin film Pt sensors were embedded in shallow etched trenches in a glass wafer that was bonded with another glass wafer having microfluidic channels. The devices having sensors integrated into the flow channels sustained pressures up to 220 bar, typical for the operation of supercritical CO 2 . No leakage from the devices could be found. Integrated temperature sensors were capable of measuring local decompression cooling effects and integrated calorimetric sensors measured flow velocities over the range 0.5–13.8 mm s −1 . By this, a better control of high-pressure microfluidic platforms has been achieved. (paper)

  14. Suppression of interfacial voids formation during silane (SiH4)-based silicon oxide bonding with a thin silicon nitride capping layer

    Science.gov (United States)

    Lee, Kwang Hong; Bao, Shuyu; Wang, Yue; Fitzgerald, Eugene A.; Seng Tan, Chuan

    2018-01-01

    The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (-OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of -OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of -OH groups from the ambient. This process results in defect-free bonded wafers.

  15. Bond markets in Africa

    Directory of Open Access Journals (Sweden)

    Yibin Mu

    2013-07-01

    Full Text Available African bond markets have been steadily growing in recent years, but nonetheless remain undeveloped. African countries would benefit from greater access to financing and deeper financial markets. This paper compiles a unique set of data on government securities and corporate bond markets in Africa. It then applies an econometric model to analyze the key determinants of African government securities market and corporate bond market capitalization. Government securities market capitalization is directly related to better institutions and interest rate volatility, and inversely related to smaller fiscal deficits, higher interest rate spreads, exchange rate volatility, and current and capital account openness. Corporate bond market capitalization is directly linked to economic size, the level of development of the economy and financial markets, better institutions, and interest rate volatility, and inversely related to higher interest rate spreads and current account openness. Policy implications follow.

  16. Diffusion bonding techniques

    International Nuclear Information System (INIS)

    Peters, R.D.

    1978-01-01

    The applications of diffusion bonding at the General Electric Neutron Devices Department are briefly discussed, with particular emphasis on the gold/gold or gold/indium joints made between metallized alumina ceramic parts in the vacuum switch tube and the crystal resonator programs. Fixtures which use the differential expansion of dissimilar metals are described and compared to one that uses hydraulic pressure to apply the necessary bonding force

  17. Improvement of the thickness distribution of a quartz crystal wafer by numerically controlled plasma chemical vaporization machining

    International Nuclear Information System (INIS)

    Shibahara, Masafumi; Yamamura, Kazuya; Sano, Yasuhisa; Sugiyama, Tsuyoshi; Endo, Katsuyoshi; Mori, Yuzo

    2005-01-01

    To improve the thickness uniformity of thin quartz crystal wafer, a new machining process that utilizes an atmospheric pressure plasma was developed. In an atmospheric pressure plasma process, since the kinetic energy of ions that impinge to the wafer surface is small and the density of the reactive species is large, high-efficiency machining without damage is realized, and the thickness distribution is corrected by numerically controlled scanning of the quartz wafer to the localized high-density plasma. By using our developed machining process, the thickness distribution of an AT cut wafer was improved from 174 nm [peak to valley (p-v)] to 67 nm (p-v) within 94 s. Since there are no unwanted spurious modes in the machined quartz wafer, it was proved that the developed machining method has a high machining efficiency without any damage

  18. Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

    Science.gov (United States)

    Sun, Q. M.; Melnikov, A.; Mandelis, A.

    2015-06-01

    Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

  19. Comparison of on-wafer calibrations using the concept of reference impedance

    OpenAIRE

    Purroy Martín, Francesc; Pradell i Cara, Lluís

    1993-01-01

    A novel method that allows to compare different calibration techniques has been developed. It is based on determining the reference impedance of a given Network Analyzer calibration from the reflection coefficient measurement of a physical open circuit. The method has been applied to several on-wafer calibrations. Peer Reviewed

  20. Spatially resolved localized vibrational mode spectroscopy of carbon in liquid encapsulated Czochralski grown gallium arsenide wafers

    International Nuclear Information System (INIS)

    Yau, Waifan.

    1988-04-01

    Substitutional carbon on an arsenic lattice site is the shallowest and one of the most dominant acceptors in semi-insulating Liquid Encapsulated Czochralski (LEC) GaAs. However, the role of this acceptor in determining the well known ''W'' shape spatial variation of neutral EL2 concentration along the diameter of a LEC wafer is not known. In this thesis, we attempt to clarify the issue of the carbon acceptor's effect on this ''W'' shaped variation by measuring spatial profiles of this acceptor along the radius of three different as-grown LEC GaAs wafers. With localized vibrational mode absorption spectroscopy, we find that the profile of the carbon acceptor is relatively constant along the radius of each wafer. Average values of concentration are 8 x 10E15 cm -3 , 1.1 x 10E15 cm -3 , and 2.2 x 10E15 cm -3 , respectively. In addition, these carbon acceptor LVM measurements indicate that a residual donor with concentration comparable to carbon exists in these wafers and it is a good candidate for the observed neutral EL2 concentration variation. 22 refs., 39 figs

  1. Wafer scale nano-membrane supported on a silicon microsieve using thin-film transfer technology

    NARCIS (Netherlands)

    Unnikrishnan, S.; Jansen, Henricus V.; Berenschot, Johan W.; Elwenspoek, Michael Curt

    A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independently of the thin-film, which is later transferred onto it by

  2. Radiation imaging detectors made by wafer post-processing of CMOS chips

    NARCIS (Netherlands)

    Blanco Carballo, V.M.

    2009-01-01

    In this thesis several wafer post-processing steps have been applied to CMOS chips. Amplification gas strucutures are built on top of the microchips. A complete radiation imaging detector is obtained this way. Integrated Micromegas-like and GEM-like structures were fabricated on top of Timepix CMOS

  3. Wafer-scale integration of piezoelectric actuation capabilities in nanoelectromechanical systems resonators

    OpenAIRE

    DEZEST, Denis; MATHIEU, Fabrice; MAZENQ, Laurent; SOYER, Caroline; COSTECALDE, Jean; REMIENS, Denis; THOMAS, Olivier; DEÜ, Jean-François; NICU, Liviu

    2013-01-01

    In this work, we demonstrate the integration of piezoelectric actuation means on arrays of nanocantilevers at the wafer scale. We use lead titanate zirconate (PZT) as piezoelectric material mainly because of its excellent actuation properties even when geometrically constrained at extreme scale

  4. MIMO feed-forward design in wafer scanners using a gradient approximation-based algorithm

    NARCIS (Netherlands)

    Heertjes, M.F.; Hennekens, D.W.T.; Steinbuch, M.

    2010-01-01

    An experimental demonstration is given of a data-based multi-input multi-output (MIMO) feed-forward control design applied to the motion systems of a wafer scanner. Atop a nominal single-input single-output (SISO) feed-forward controller, a MIMO controller is designed having a finite impulse

  5. Automatic Semiconductor Wafer Image Segmentation for Defect Detection Using Multilevel Thresholding

    Directory of Open Access Journals (Sweden)

    Saad N.H.

    2016-01-01

    Full Text Available Quality control is one of important process in semiconductor manufacturing. A lot of issues trying to be solved in semiconductor manufacturing industry regarding the rate of production with respect to time. In most semiconductor assemblies, a lot of wafers from various processes in semiconductor wafer manufacturing need to be inspected manually using human experts and this process required full concentration of the operators. This human inspection procedure, however, is time consuming and highly subjective. In order to overcome this problem, implementation of machine vision will be the best solution. This paper presents automatic defect segmentation of semiconductor wafer image based on multilevel thresholding algorithm which can be further adopted in machine vision system. In this work, the defect image which is in RGB image at first is converted to the gray scale image. Median filtering then is implemented to enhance the gray scale image. Then the modified multilevel thresholding algorithm is performed to the enhanced image. The algorithm worked in three main stages which are determination of the peak location of the histogram, segmentation the histogram between the peak and determination of first global minimum of histogram that correspond to the threshold value of the image. The proposed approach is being evaluated using defected wafer images. The experimental results shown that it can be used to segment the defect correctly and outperformed other thresholding technique such as Otsu and iterative thresholding.

  6. Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

    Directory of Open Access Journals (Sweden)

    Prithviraj Chakraborty

    2013-01-01

    Full Text Available Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR. Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A, and lactose monohydrate as ingredient, of hydrophilic matrix former (B on the bioadhesive force, disintegration time, percent (% swelling index, and time taken for 70% drug release (t70%. The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design.

  7. Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

    Directory of Open Access Journals (Sweden)

    Shisheng Cai

    2017-03-01

    Full Text Available In order to obtain excellent physical properties and ultrathin devices, thinning technique plays an important role in semiconductor industry with the rapid development of wearable electronic devices. This study presents a physical nano-diamond grinding technique without any chemistry to obtain ultrathin silicon substrate. The nano-diamond with spherical shape repeats nano-cutting and penetrating surface to physically etch silicon wafer during grinding process. Nano-diamond grinding induces an ultrathin “amorphous layer” on silicon wafer and thus the mismatch strain between the amorphous layer and substrate leads to stability transition from the spherical to non-spherical deformation of the wafer. Theoretical model is proposed to predict and analyze the deformation of amorphous layer/silicon substrate system. Furthermore, the deformation bifurcation behavior of amorphous layer/silicon substrate system is analyzed. As the mismatch strain increases or thickness decreases, the amorphous layer/silicon substrate system may transit to non-spherical deformation, which is consistent to the experimental results. The amorphous layer stresses are also obtained to predict the damage of silicon wafer.

  8. Synchronizing decentralized control loops for overall performance enhancement : a Youla framework applied to a wafer scanner

    NARCIS (Netherlands)

    Evers, E.; van de Wal, M.M.J.; Oomen, T.A.E.

    2017-01-01

    Manufacturing equipment often consists of multiple subsystems. For instance, in lithographic IC manufacturing, both a reticle stage and a wafer stage move synchronously. Traditionally, these subsystems are divided into manageable subproblems, at the expense of a suboptimal overall solution. The aim

  9. Sidewall patterning - A new wafer-scale method for accurate patterning of vertical silicon structures

    NARCIS (Netherlands)

    Westerik, P. J.; Vijselaar, W. J.C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G.E.

    2018-01-01

    For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that

  10. Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

    Science.gov (United States)

    Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

    2016-03-01

    With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

  11. Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate

    DEFF Research Database (Denmark)

    Buron, Jonas Due; Mackenzie, David M. A.; Petersen, Dirch Hjorth

    2015-01-01

    We demonstrate wafer-scale, non-contact mapping of essential carrier transport parameters, carrier mobility (mu(drift)), carrier density (N-S), DC sheet conductance (sigma(dc)), and carrier scattering time (tau(SC)) in CVD graphene, using spatially resolved terahertz time-domain conductance...

  12. The preparation and thermoelectric properties of molten salt electrodeposited boron wafers

    International Nuclear Information System (INIS)

    Kumashiro, Y.; Ozaki, S.; Sato, K.; Kataoka, Y.; Hirata, K.; Yokoyama, T.; Nagatani, S.; Kajiyama, K.

    2004-01-01

    We have prepared electrodeposited boron wafer by molten salts with KBF 4 -KF at 680 deg. C using graphite crucible for anode and silicon wafer and nickel plate for cathodes. Experiments were performed by various molar ratios KBF 4 /KF and current densities. Amorphous p-type boron wafers with purity 87% was deposited on nickel plate for 1 h. Thermal diffusivity by ring-flash method and heat capacity by DSC method produced thermal conductivity showing amorphous behavior in the entire temperature range. The systematical results on thermoelectric properties were obtained for the wafers prepared with KBF 4 -KF (66-34 mol%) under various current densities in the range 1-2 A/cm 2 . The temperature dependencies of electrical conductivity showed thermal activated type with activation energy of 0.5 eV. Thermoelectric power tended to increase with increasing temperature up to high temperatures with high values of (1-10) mV/K. Thermoelectric figure-of-merit was 10 -4 /K at high temperatures. Estimated efficiency of thermoelectric energy conversion would be calculated to be 4-5%

  13. A facility for plastic deformation of germanium single-crystal wafers

    DEFF Research Database (Denmark)

    Lebech, B.; Theodor, K.; Breiting, B.

    1998-01-01

    . All movements and temperature changes are done by a robot via a PLC-control system. Two nine-crystal focusing monochromators (54 x 116 and 70 x 116 mm(2)) made from 100 wafers with average mosaicity similar to 13' have been constructed. Summaries of the test results are presented. (C) 1998 Elsevier...

  14. Polymer-based 2D/3D wafer level heterogeneous integration for SSL module

    NARCIS (Netherlands)

    Yuan, C.; Wei, J.; Ye, H.; Koh, S.; Harianto, S.; Nieuwenhof, M.A. van den; Zhang, G.Q.

    2012-01-01

    This paper demonstrates a heterogeneous integration of solid state lighting (SSL) module, including light source (LED) and driver/control components. Such integration has been realized by the polymer-based reconfigured wafer level package technologies and such structure has been prototyped and

  15. Graphene-Decorated Nanocomposites for Printable Electrodes in Thin Wafer Devices

    Science.gov (United States)

    Bakhshizadeh, N.; Sivoththaman, S.

    2017-12-01

    Printable electrodes that induce less stress and require lower curing temperatures compared to traditional screen-printed metal pastes are needed in thin wafer devices such as future solar cells, and in flexible electronics. The synthesis of nanocomposites by incorporating graphene nanopowders as well as silver nanowires into epoxy-based electrically conductive adhesives (ECA) is examined to improve electrical conductivity and to develop alternate printable electrode materials that induce less stress on the wafer. For the synthesized graphene and Ag nanowire-decorated ECA nanocomposites, the curing kinetics were studied by dynamic and isothermal differential scanning calorimetry measurements. Thermogravimetric analysis on ECA, ECA-AG and ECA/graphene nanopowder nanocomposites showed that the temperatures for onset of decomposition are higher than their corresponding glass transition temperature ( T g) indicating an excellent thermal resistance. Printed ECA/Ag nanowire nanocomposites showed 90% higher electrical conductivity than ECA films, whereas the ECA/graphene nanocomposites increased the conductivity by over two orders of magnitude. Scanning electron microscopy results also revealed the effect of fillers morphology on the conductivity improvement and current transfer mechanisms in nanocomposites. Residual stress analysis performed on Si wafers showed that the ECA and nanocomposite printed wafers are subjected to much lower stress compared to those printed with metallic pastes. The observed parameters of low curing temperature, good thermal resistance, reasonably high conductivity, and low residual stress in the ECA/graphene nanocomposite makes this material a promising alternative in screen-printed electrode formation in thin substrates.

  16. Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments

    NARCIS (Netherlands)

    Bomer, Johan G.; Prokofyev, A.V.; van den Berg, Albert; le Gac, Severine

    2014-01-01

    We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the

  17. Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

    Science.gov (United States)

    Dey, Surajit; Parcha, Versha; Bhattacharya, Shiv Sankar; Ghosh, Amitava

    2013-01-01

    Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR). Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A), and lactose monohydrate as ingredient, of hydrophilic matrix former (B) on the bioadhesive force, disintegration time, percent (%) swelling index, and time taken for 70% drug release (t 70%). The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD) analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design. PMID:23781498

  18. Wafer scale lead zirconate titanate film preparation by sol-gel method using stress balance layer

    International Nuclear Information System (INIS)

    Lu Jian; Kobayashi, Takeshi; Yi Zhang; Maeda, Ryutaro; Mihara, Takashi

    2006-01-01

    In this paper, platinum/titanium (Pt/Ti) film was introduced as a residual stress balance layer into wafer scale thick lead zirconate titanate (PZT) film fabrication by sol-gel method. The stress developing in PZT film's bottom electrode as well as in PZT film itself during deposition were analyzed; the wafer curvatures, PZT crystallizations and PZT electric properties before and after using Pt/Ti stress balance layer were studied and compared. It was found that this layer is effective to balance the residual stress in PZT film's bottom electrode induced by thermal expansion coefficient mismatch and Ti diffusion, thus can notably reduce the curvature of 4-in. wafer from - 40.5 μm to - 12.9 μm after PZT film deposition. This stress balance layer was also found effective to avoid the PZT film cracking even when annealed by rapid thermal annealing with heating-rate up to 10.5 deg. C/s. According to X-ray diffraction analysis and electric properties characterization, crack-free uniform 1-μm-thick PZT film with preferred pervoskite (001) orientation, excellent dielectric constant, as high as 1310, and excellent remanent polarization, as high as 39.8 μC/cm 2 , can be obtained on 4-in. wafer

  19. SiC epitaxial layer growth in a novel multi-wafer VPE reactor

    Energy Technology Data Exchange (ETDEWEB)

    Burk, A.A. Jr.; O`Loughlin, M.J. [Northrop Grumman Advanced Technology Lab., Baltimore, MD (United States); Mani, S.S. [Northrop Grumman Science and Technology Center, Pittsburgh, PA (United States)

    1998-06-01

    Preliminary results are presented for SiC epitaxial layer growth employing a unique planetary SiC-VPE reactor. The high-throughput, multi-wafer (7 x 2-inch) reactor, was designed for atmospheric and reduced pressure operation at temperatures up to and exceeding 1600 C. Specular epitaxial layers have been grown in the reactor at growth rates from 3-5 {mu}m/hr. The thickest layer grown to data was 42 {mu}m. The layers exhibit minimum unintentional n-type doping of {proportional_to}1 x 10{sup 15} cm{sup -3}, room temperature mobilities of {proportional_to}1000 cm{sup 2}/Vs, and intentional n-type doping from {proportional_to}5 x 10{sup 15} cm{sup -3} to >1 x 10{sup 19} cm{sup -3}. Intrawafer thickness and doping uniformities of 4% and 7% (standard deviation/mean) have been obtained, respectively, on 35 mm diameter substrates. Recently, 3% thickness uniformity has been demonstrated on a 50 mm substrate. Within a run, wafer-to-wafer thickness deviation is {proportional_to}4-14%. Doping variation is currently larger, ranging as much as a factor of two from the highest to the lowest doped wafer. Continuing efforts to improve the susceptor temperature uniformity and reduce unintentional hydrocarbon generation to improve layer uniformity and reproducibility, are presented. (orig.) 18 refs.

  20. Controlled planar interface synthesis by ultrahigh vacuum diffusion bonding/deposition

    International Nuclear Information System (INIS)

    Kim, M. J.; Carpenter, R. W.; Cox, M. J.; Xu, J.

    2000-01-01

    An ultrahigh vacuum (UHV) diffusion bonding/deposition instrument was designed and constructed, which can produce homophase and heterophase planar interfaces from a wide array of materials. The interfaces are synthesized in situ by diffusion bonding of two substrates with or without various interfacial layers, at temperatures up to about 1500 degree sign C. Substrate surfaces can be heat treated, ion-beam sputter cleaned, and chemically characterized in situ by Auger electron spectroscopy prior to deposition and/or bonding. Bicrystals can be synthesized by bonding two single-crystal substrates at a specified orientation. Interfacial layers can be deposited by electron beam evaporation and/or sputter deposition in any layered or alloyed combination on the substrates before bonding. The instrument can accommodate cylindrical and/or wafer type specimens whose sizes are sufficient for fracture mechanical testing to measure interface bond strength. A variety of planar interfaces of metals, semiconductors, and ceramics were synthesized. Examples of bonded stainless steel/Ti/stainless steel, Si/Si, and sapphire/sapphire interfaces are presented. (c) 2000 Materials Research Society

  1. Characterization of bulk-micromachined direct-bonded silicon nanofilters

    Science.gov (United States)

    Tu, Jay K.; Huen, Tony; Szema, Robert; Ferrari, Mauro

    1998-03-01

    The ability to separate 30-100 nm particles - nanofiltration - is critical for many biomedical applications. Where this filtration needs to be absolute, such as for viral elimination in the blood fractionation process, the large variations in pore size found with conventional polymeric filters can lead to the unwanted presence of viruses in the filtrate. To overcome this problem, we have developed a filter with micromachined channels sandwiched between two bonded silicon wafers. These channels are formed through the selective deposition and then removal of a thermally-grown oxide, the thickness of which can be controlled to +/- 4 percent for 30 nm pores. In this paper, we will present both the gas and liquid characterization, and the filtration studies done on 44 and 100 nm beads.

  2. Romanian government bond market

    Directory of Open Access Journals (Sweden)

    Cornelia POP

    2012-12-01

    Full Text Available The present paper aims to present the level of development reached by Romanian government bond market segment, as part of the country financial market. The analysis will be descriptive (the data series available for Romania are short, based on the secondary data offered by the official bodies involved in the process of issuing and trading the Romanian government bonds (Romanian Ministry of Public Finance, Romanian National Bank and Bucharest Stock Exchange, and also on secondary data provided by the Federation of European Stock Exchanges.To enhance the market credibility as a benchmark, a various combination of measures is necessary; among these measures are mentioned: the extension of the yield curve; the issuance calendars in order to improve transparency; increasing the disclosure of information on public debt issuance and statistics; holding regular meetings with dealers, institutional investors and rating agencies; introducing a system of primary dealers; establishing a repurchase (repo market in the government bond market. These measures will be discussed based on the evolution presented inside the paper.The paper conclude with the fact that, until now, the Romanian government bond market did not provide a benchmark for the domestic financial market and that further efforts are needed in order to increase the government bond market transparency and liquidity.

  3. Interstellar hydrogen bonding

    Science.gov (United States)

    Etim, Emmanuel E.; Gorai, Prasanta; Das, Ankan; Chakrabarti, Sandip K.; Arunan, Elangannan

    2018-06-01

    This paper reports the first extensive study of the existence and effects of interstellar hydrogen bonding. The reactions that occur on the surface of the interstellar dust grains are the dominant processes by which interstellar molecules are formed. Water molecules constitute about 70% of the interstellar ice. These water molecules serve as the platform for hydrogen bonding. High level quantum chemical simulations for the hydrogen bond interaction between 20 interstellar molecules (known and possible) and water are carried out using different ab-intio methods. It is evident that if the formation of these species is mainly governed by the ice phase reactions, there is a direct correlation between the binding energies of these complexes and the gas phase abundances of these interstellar molecules. Interstellar hydrogen bonding may cause lower gas abundance of the complex organic molecules (COMs) at the low temperature. From these results, ketenes whose less stable isomers that are more strongly bonded to the surface of the interstellar dust grains have been observed are proposed as suitable candidates for astronomical observations.

  4. Safe and Liquid Mortgage Bonds

    DEFF Research Database (Denmark)

    Dick-Nielsen, Jens; Gyntelberg, Jacob; Lund, Jesper

    This paper shows that strict match pass-through funding of covered bonds provides safe and liquid mortgage bonds. Despite a 30% drop in house prices during the 2008 global crisis Danish mortgage bonds remained as liquid as most European government bonds. The Danish pass-through system effectively...... eliminates credit risk from the investor's perspective. Similar to other safe bonds, funding liquidity becomes the main driver of mortgage bond liquidity and this creates commonality in liquidity across markets and countries. These findings have implications for how to design a robust mortgage bond system...

  5. Hydrogen bonded supramolecular materials

    CERN Document Server

    Li, Zhan-Ting

    2015-01-01

    This book is an up-to-date text covering topics in utilizing hydrogen bonding for constructing functional architectures and supramolecular materials. The first chapter addresses the control of photo-induced electron and energy transfer. The second chapter summarizes the formation of nano-porous materials. The following two chapters introduce self-assembled gels, many of which exhibit unique functions. Other chapters cover the advances in supramolecular liquid crystals and the versatility of hydrogen bonding in tuning/improving the properties and performance of materials. This book is designed

  6. Continuing bonds and place.

    Science.gov (United States)

    Jonsson, Annika; Walter, Tony

    2017-08-01

    Where do people feel closest to those they have lost? This article explores how continuing bonds with a deceased person can be rooted in a particular place or places. Some conceptual resources are sketched, namely continuing bonds, place attachment, ancestral places, home, reminder theory, and loss of place. The authors use these concepts to analyze interview material with seven Swedes and five Britons who often thought warmly of the deceased as residing in a particular place and often performing characteristic actions. The destruction of such a place, by contrast, could create a troubling, haunting absence, complicating the deceased's absent-presence.

  7. Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

    Science.gov (United States)

    Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

    2018-05-01

    Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

  8. Chemical strategies for modifications of the solar cell process, from wafering to emitter diffusion; Chemische Ansaetze zur Neuordnung des Solarzellenprozesses ausgehend vom Wafering bis hin zur Emitterdiffusion

    Energy Technology Data Exchange (ETDEWEB)

    Mayer, Kuno

    2009-11-06

    The paper describes the classic standard industrial solar cell based on monocrystalline silicon and describes new methods of fabrication. The first is an alternative wafering concept using laser microjet cutting instead of multiwire cutting. This method originally uses pure, deionized water; it was modified so that the liquid jet will not only be a liquid light conductor but also a transport medium for etching fluids supporting thermal abrasion of silicon by the laser jet. Two etching fluids were tested experimentally; it was found that water-free fluids based on perfluorinated solvents with very slight additions of gaseous chlorine are superior to all other options. In the second section, the wet chemical process steps between wafering and emitter diffusion (i.e. the first high-temperature step) was to be modified. Alternatives to 2-propanol were to be found in the experimental part. Purification after texturing was to be rationalized in order to reduce the process cost, either by using less chemical substances or by achieving shorter process times. 1-pentanol and p-toluolsulfonic acid were identified as two potential alternatives to 2-propanol as texture additives. Finally, it could be shown that wire-cut substrates processed with the new texturing agents have higher mechanical stabilities than substrates used with the classic texturing agent 2-propanol. [German] Im ersten Kapitel wird die klassische Standard-Industrie-Solarzelle auf der Basis monokristallinen Siliziums vorgestellt. Der bisherige Herstellungsprozess der Standard-Industrie-Solarzelle, der in wesentlichen Teilen darauf abzielt, diese Verluste zu minimieren, dient als Referenz fuer die Entwicklung neuer Fertigungsverfahren, wie sie in dieser Arbeit vorgestellt werden. Den ersten thematischen Schwerpunkt bildet die Entwicklung eines alternativen Wafering-Konzeptes zum Multi-Drahtsaegen. Die Basis des neuen, hier vorgestellten Wafering-Prozesses bildet das Laser-Micro-Jet-Verfahren. Dieses System

  9. A new method for wafer quality monitoring using semiconductor process big data

    Science.gov (United States)

    Sohn, Younghoon; Lee, Hyun; Yang, Yusin; Jun, Chungsam

    2017-03-01

    In this paper we proposed a new semiconductor quality monitoring methodology - Process Sensor Log Analysis (PSLA) - using process sensor data for the detection of wafer defectivity and quality monitoring. We developed exclusive key parameter selection algorithm and user friendly system which is able to handle large amount of big data very effectively. Several production wafers were selected and analyzed based on the risk analysis of process driven defects, for example alignment quality of process layers. Thickness of spin-coated material can be measured using PSLA without conventional metrology process. In addition, chip yield impact was verified by matching key parameter changes with electrical die sort (EDS) fail maps at the end of the production step. From this work, we were able to determine that process robustness and product yields could be improved by monitoring the key factors in the process big data.

  10. ILT based defect simulation of inspection images accurately predicts mask defect printability on wafer

    Science.gov (United States)

    Deep, Prakash; Paninjath, Sankaranarayanan; Pereira, Mark; Buck, Peter

    2016-05-01

    At advanced technology nodes mask complexity has been increased because of large-scale use of resolution enhancement technologies (RET) which includes Optical Proximity Correction (OPC), Inverse Lithography Technology (ILT) and Source Mask Optimization (SMO). The number of defects detected during inspection of such mask increased drastically and differentiation of critical and non-critical defects are more challenging, complex and time consuming. Because of significant defectivity of EUVL masks and non-availability of actinic inspection, it is important and also challenging to predict the criticality of defects for printability on wafer. This is one of the significant barriers for the adoption of EUVL for semiconductor manufacturing. Techniques to decide criticality of defects from images captured using non actinic inspection images is desired till actinic inspection is not available. High resolution inspection of photomask images detects many defects which are used for process and mask qualification. Repairing all defects is not practical and probably not required, however it's imperative to know which defects are severe enough to impact wafer before repair. Additionally, wafer printability check is always desired after repairing a defect. AIMSTM review is the industry standard for this, however doing AIMSTM review for all defects is expensive and very time consuming. Fast, accurate and an economical mechanism is desired which can predict defect printability on wafer accurately and quickly from images captured using high resolution inspection machine. Predicting defect printability from such images is challenging due to the fact that the high resolution images do not correlate with actual mask contours. The challenge is increased due to use of different optical condition during inspection other than actual scanner condition, and defects found in such images do not have correlation with actual impact on wafer. Our automated defect simulation tool predicts

  11. Mathematical model for predicting molecular-beam epitaxy growth rates for wafer production

    International Nuclear Information System (INIS)

    Shi, B.Q.

    2003-01-01

    An analytical mathematical model for predicting molecular-beam epitaxy (MBE) growth rates is reported. The mathematical model solves the mass-conservation equation for liquid sources in conical crucibles and predicts the growth rate by taking into account the effect of growth source depletion on the growth rate. Assumptions made for deducing the analytical model are discussed. The model derived contains only one unknown parameter, the value of which can be determined by using data readily available to MBE growers. Procedures are outlined for implementing the model in MBE production of III-V compound semiconductor device wafers. Results from use of the model to obtain targeted layer compositions and thickness of InP-based heterojunction bipolar transistor wafers are presented

  12. Wafer-Level Patterned and Aligned Polymer Nanowire/Micro- and Nanotube Arrays on any Substrate

    KAUST Repository

    Morber, Jenny Ruth

    2009-05-25

    A study was conducted to fabricate wafer-level patterned and aligned polymer nanowire (PNW), micro- and nanotube arrays (PNT), which were created by exposing the polymer material to plasma etching. The approach for producing wafer-level aligned PNWs involved a one-step inductively coupled plasma (ICP) reactive ion etching process. The polymer nanowire array was fabricated in an ICP reactive ion milling chamber with a pressure of 10mTorr. Argon (Ar), O 2, and CF4 gases were released into the chamber as etchants at flow rates of 15 sccm, 10 sccm, and 40 sccm. Inert gasses, such as Ar-form positive ions were incorporated to serve as a physical component to assist in the material degradation process. One power source (400 W) was used to generate dense plasma from the input gases, while another power source applied a voltage of approximately 600V to accelerate the plasma toward the substrate.

  13. Wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible biomedical platform.

    Science.gov (United States)

    Maeng, Jimin; Meng, Chuizhou; Irazoqui, Pedro P

    2015-02-01

    We present wafer-scale integrated micro-supercapacitors on an ultrathin and highly flexible parylene platform, as progress toward sustainably powering biomedical microsystems suitable for implantable and wearable applications. All-solid-state, low-profile (supercapacitors are formed on an ultrathin (~20 μm) freestanding parylene film by a wafer-scale parylene packaging process in combination with a polyaniline (PANI) nanowire growth technique assisted by surface plasma treatment. These micro-supercapacitors are highly flexible and shown to be resilient toward flexural stress. Further, direct integration of micro-supercapacitors into a radio frequency (RF) rectifying circuit is achieved on a single parylene platform, yielding a complete RF energy harvesting microsystem. The system discharging rate is shown to improve by ~17 times in the presence of the integrated micro-supercapacitors. This result suggests that the integrated micro-supercapacitor technology described herein is a promising strategy for sustainably powering biomedical microsystems dedicated to implantable and wearable applications.

  14. Non-axisymmetric flexural vibrations of free-edge circular silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Dmitriev, A.V., E-mail: dmitriev@hbar.phys.msu.ru; Gritsenko, D.S.; Mitrofanov, V.P., E-mail: mitr@hbar.phys.msu.ru

    2014-02-07

    Non-axisymmetric flexural vibrations of circular silicon (111) wafers are investigated. The modes with azimuthal index 2⩽k⩽30 are electrostatically excited and monitored by a capacitive sensor. The splitting of the mode frequencies associated with imperfection of the wafer is observed. The measured loss factors for the modes with 6≲k≲26 are close to those calculated according to the thermoelastic damping theory, while clamping losses likely dominate for k≲6, and surface losses at the level of inverse Q-factor Q{sup −1}≈4×10{sup −6} prevail for the modes with large k. The modes demonstrate nonlinear behavior of mainly geometrical origin at large amplitudes.

  15. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    Science.gov (United States)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-08-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

  16. Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

    Science.gov (United States)

    Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

    Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

  17. External self-gettering of nickel in float zone silicon wafers

    Science.gov (United States)

    Gay, N.; Martinuzzi, S.

    1997-05-01

    During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

  18. Ion implanters contamination on wafer surface analyzed by ToF-SIMS and SPV analytical techniques

    International Nuclear Information System (INIS)

    Ricciari, R.; Bertini, M.; Ferlito, E.P.; Pizzo, G.; Anastasi, G.; Mello, D.; Franco, G.

    2007-01-01

    In ULSI processes, metallic contamination controls are very important issues. For the ion implantation process it is known that several sources of contaminations still need to be controlled: metals from sputtering of the apertures or wafer holders, Na + contaminations from filament impurities and messy maintenance procedure. ToF-SIMS is one of the most promising candidates to perform in-line surface analysis due to its high sensitivity. It is very common to use surface photo-voltage (SPV) techniques to control ion implanter equipments but this kind of analysis is an indirect measure for metallic contamination. The aim of this work is to study the possibility to use ToF-SIMS instead of SPV for in line equipment contamination monitoring. For this reason a comparison between SPV and ToF-SIMS data occurred. Good correlation between the data is shown; moreover ToF-SIMS spectra give detailed information about the other contaminations present on the wafer surface

  19. Self-adaptive phosphor coating technology for wafer-level scale chip packaging

    International Nuclear Information System (INIS)

    Zhou Linsong; Rao Haibo; Wang Wei; Wan Xianlong; Liao Junyuan; Wang Xuemei; Zhou Da; Lei Qiaolin

    2013-01-01

    A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP. (semiconductor devices)

  20. Integration of European Bond Markets

    DEFF Research Database (Denmark)

    Christiansen, Charlotte

    2014-01-01

    I investigate the time variation in the integration of EU government bond markets. The integration is measured by the explanatory power of European factor portfolios for the individual bond markets for each year. The integration of the government bond markets is stronger for EMU than non-EMU memb......I investigate the time variation in the integration of EU government bond markets. The integration is measured by the explanatory power of European factor portfolios for the individual bond markets for each year. The integration of the government bond markets is stronger for EMU than non...

  1. Amalgam shear bond strength to dentin using different bonding agents.

    Science.gov (United States)

    Vargas, M A; Denehy, G E; Ratananakin, T

    1994-01-01

    This study evaluated the shear bond strength of amalgam to dentin using five different bonding agents: Amalgambond Plus, Optibond, Imperva Dual, All-Bond 2, and Clearfil Liner Bond. Flat dentin surfaces obtained by grinding the occlusal portion of 50 human third molars were used for this study. To contain the amalgam on the tooth surface, cylindrical plastic molds were placed on the dentin and secured with sticky wax. The bonding agents were then applied according to the manufacturers' instructions or light activated and Tytin amalgam was condensed into the plastic molds. The samples were thermocycled and shear bond strengths were determined using an Instron Universal Testing Machine. Analysis by one-way ANOVA indicated significant difference between the five groups (P < 0.05). The bond strength of amalgam to dentin was significantly higher with Amalgambond Plus using the High-Performance Additive than with the other four bonding agents.

  2. Development of self-calibration techniques for on-wafer and fixtured measurements: a novel approach

    OpenAIRE

    Pradell i Cara, Lluís; Purroy Martín, Francesc; Cáceres, M.

    1992-01-01

    Network Analyzer self-calibration techniques - TRL, LMR, TAR- are developed, implemented and compared in several transmission media. A novel LMR (Line-Match-Reflect) technique based on known LINE and REFLECT Standards, is proposed and compared to conventional LMR (based on known LINE and MATCH Standards) and other techniques (TRL, TAR). They are applied to on-wafer S-parameter measurement as well as to coaxial, waveguide and microstrip media. Experimental results up to 40 GHz are presented. ...

  3. Quantitative Exposure Assessment of Various Chemical Substances in a Wafer Fabrication Industry Facility

    Directory of Open Access Journals (Sweden)

    Hyunhee Park

    2011-03-01

    Conclusion: Benzene, a known human carcinogen for leukemia, and arsine, a hematologic toxin, were not detected in wafer fabrication sites in this study. Among reproductive toxic substances, n-butyl acetate was not detected, but fluorides and PGMEA existed in small amounts in the air. This investigation was focused on the air-borne chemical concentrations only in regular working conditions. Unconditional exposures during spills and/or maintenance tasks and by-product chemicals were not included. Supplementary studies might be required.

  4. Improved delivery of the anticancer agent citral using BSA nanoparticles and polymeric wafers

    Directory of Open Access Journals (Sweden)

    White B

    2017-12-01

    Full Text Available Benjamin White,1 Anna Evison,1 Eszter Dombi,1 Helen E Townley1,2 1Nuffield Department of Obstetrics and Gynaecology, Women’s Centre, John Radcliffe Hospital, 2Department of Engineering Science, Oxford University, Oxford, UK Abstract: Rhabdomyosarcoma (RMS is the most common soft tissue sarcoma in children, with a 5-year survival rate of between 30 and 65%. Standard treatment involves surgery, radiation treatment, and chemotherapy. However, there is a high recurrence rate, particularly from locoregional spread. We investigated the use of the natural compound citral (3,7-dimethyl-2,6-octadienal, which can be found in a number of plants, but is particularly abundant in lemon grass (Cymbopogon citratus oil, for activity against immortalized RMS cells. Significant cancer cell death was seen at concentrations above 150 μM citral, and mitochondrial morphological changes were seen after incubation with 10 μM citral. However, since citral is a highly volatile molecule, we prepared albumin particles by a desolvation method to encapsulate citral, as a means of stabilization. We then further incorporated the loaded nanoparticles into a biodegradable polyanhydride wafer to generate a slow release system. The wafers were shown to degrade by 50% over the course of 25 days and to release the active compound. We therefore propose the use of the citral-nanoparticle-polymer wafers for implantation into the tumor bed after surgical removal of a sarcoma as a means to control locoregional spread due to any remaining cancerous cells. Keywords: citral, nanoparticle, wafer, biodegradable, mitochondria, toroidal, cancer, rhabdomyosarcoma, Cymbopogon citratus

  5. Increasing reticle inspection efficiency and reducing wafer print-checks using automated defect classification and simulation

    Science.gov (United States)

    Ryu, Sung Jae; Lim, Sung Taek; Vacca, Anthony; Fiekowsky, Peter; Fiekowsky, Dan

    2013-09-01

    IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the "requal" phase for extended, non-productive periods of time. The overall "requal" cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs. Fortunately, a software program has been developed which automates defect classification with simulated printability measurement greatly reducing requal cycle time and improving overall disposition accuracy. This product, called ADAS (Auto Defect Analysis System), has been tested in both engineering and high-volume production environments with very successful results. In this paper, data is presented supporting significant reduction for costly wafer print checks, improved inspection area productivity, and minimized risk of misclassified yield limiting defects.

  6. Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

    Science.gov (United States)

    Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

    2018-06-01

    Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

  7. DEPTH MEASUREMENT OF DISRUPTED LAYER ON SILICON WAFER SURFACE USING AUGER SPECTROSCOPY METHOD

    Directory of Open Access Journals (Sweden)

    V. A. Solodukha

    2016-01-01

    Full Text Available The paper proposes a method for depth measurement of a disrupted layer on silicon wafer surface which is based on application of Auger spectroscopy with the precision sputtering of surface silicon layers and registration of the Auger electron yield intensity. In order to measure the disrupted layer with the help of Auger spectroscopy it is necessary to determine dependence of the released Auger electron amount on sputtering time (profile and then the dependence is analyzed. Silicon amount in the disrupted layer is less than in the volume. While going deeper the disruptive layer is decreasing that corresponds to an increase of atom density in a single layer. The essence of the method lies in the fact the disruptive layer is removed by ion beam sputtering and detection of interface region is carried out with the help of registration of the Auger electron yield intensity from the sputtered surface up to the moment when it reaches the value which is equal to the Auger electron yield intensity for single-crystal silicon. While removing surface silicon layers the registration of the Auger electron yield intensity from silicon surface makes it possible to control efficiently a presence of the disrupted layer on the silicon wafer surface. In this case depth control locality is about 1.0 nm due to some peculiarities of Auger spectroscopy method. The Auger electron yield intensity is determined automatically while using Auger spectrometer and while removing the disrupted layer the intensity is gradually increasing. Depth of the disrupted layer is determined by measuring height of the step which has been formed as a result of removal of the disrupted layer from the silicon wafer surface. Auger spectroscopy methods ensures an efficient depth control surface disruptions at the manufacturing stages of silicon wafers and integrated circuits. The depth measurement range of disruptions constitutes 0.001–1.000 um.

  8. Application of genetic algorithm in modeling on-wafer inductors for up to 110 Ghz

    Science.gov (United States)

    Liu, Nianhong; Fu, Jun; Liu, Hui; Cui, Wenpu; Liu, Zhihong; Liu, Linlin; Zhou, Wei; Wang, Quan; Guo, Ao

    2018-05-01

    In this work, the genetic algorithm has been introducted into parameter extraction for on-wafer inductors for up to 110 GHz millimeter-wave operations, and nine independent parameters of the equivalent circuit model are optimized together. With the genetic algorithm, the model with the optimized parameters gives a better fitting accuracy than the preliminary parameters without optimization. Especially, the fitting accuracy of the Q value achieves a significant improvement after the optimization.

  9. Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

    Institute of Scientific and Technical Information of China (English)

    潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

    2011-01-01

    Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95% active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

  10. Benefits of on-wafer calibration standards fabricated in membrane technology

    Science.gov (United States)

    Rohland, M.; Arz, U.; Büttgenbach, S.

    2011-07-01

    In this work we compare on-wafer calibration standards fabricated in membrane technology with standards built in conventional thin-film technology. We perform this comparison by investigating the propagation of uncertainties in the geometry and material properties to the broadband electrical properties of the standards. For coplanar waveguides used as line standards the analysis based on Monte Carlo simulations demonstrates an up to tenfold reduction in uncertainty depending on the electromagnetic waveguide property we look at.

  11. Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments.

    Science.gov (United States)

    Bomer, Johan G; Prokofyev, Alexander V; van den Berg, Albert; Le Gac, Séverine

    2014-12-07

    We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the microchannels, and alignment precision. Experiments on lipid bilayers with electrophysiological recordings using a model pore-forming polypeptide are demonstrated.

  12. Photolithography diagnostic expert systems: a systematic approach to problem solving in a wafer fabrication facility

    Science.gov (United States)

    Weatherwax Scott, Caroline; Tsareff, Christopher R.

    1990-06-01

    One of the main goals of process engineering in the semiconductor industry is to improve wafer fabrication productivity and throughput. Engineers must work continuously toward this goal in addition to performing sustaining and development tasks. To accomplish these objectives, managers must make efficient use of engineering resources. One of the tools being used to improve efficiency is the diagnostic expert system. Expert systems are knowledge based computer programs designed to lead the user through the analysis and solution of a problem. Several photolithography diagnostic expert systems have been implemented at the Hughes Technology Center to provide a systematic approach to process problem solving. This systematic approach was achieved by documenting cause and effect analyses for a wide variety of processing problems. This knowledge was organized in the form of IF-THEN rules, a common structure for knowledge representation in expert system technology. These rules form the knowledge base of the expert system which is stored in the computer. The systems also include the problem solving methodology used by the expert when addressing a problem in his area of expertise. Operators now use the expert systems to solve many process problems without engineering assistance. The systems also facilitate the collection of appropriate data to assist engineering in solving unanticipated problems. Currently, several expert systems have been implemented to cover all aspects of the photolithography process. The systems, which have been in use for over a year, include wafer surface preparation (HMDS), photoresist coat and softbake, align and expose on a wafer stepper, and develop inspection. These systems are part of a plan to implement an expert system diagnostic environment throughout the wafer fabrication facility. In this paper, the systems' construction is described, including knowledge acquisition, rule construction, knowledge refinement, testing, and evaluation. The roles

  13. Convertible bond valuation focusing on Chinese convertible bond market

    OpenAIRE

    Yang, Ke

    2010-01-01

    This paper mainly discusses the methods of valuation of convertible bonds in Chinese market. Different from common convertible bonds in European market, considering the complicate features of Chinese convertible bond, this paper represents specific pricing approaches for pricing convertible bonds with different provisions along with the increment of complexity of these provisions. More specifically, this paper represents the decomposing method and binomial tree method for pricing both of Non-...

  14. In situ beam angle measurement in a multi-wafer high current ion implanter

    International Nuclear Information System (INIS)

    Freer, B.S.; Reece, R.N.; Graf, M.A.; Parrill, T.; Polner, D.

    2005-01-01

    Direct, in situ measurement of the average angle and angular content of an ion beam in a multi-wafer ion implanter is reported for the first time. A new type of structure and method are described. The structures are located on the spinning disk, allowing precise angular alignment to the wafers. Current that passes through the structures is known to be within a range of angles and is detected behind the disk. By varying the angle of the disk around two axes, beam current versus angle is mapped and the average angle and angular spread are calculated. The average angle measured in this way is found to be consistent with that obtained by other techniques, including beam centroid offset and wafer channeling methods. Average angle of low energy beams, for which it is difficult to use other direct methods, is explored. A 'pencil beam' system is shown to give average angle repeatability of 0.13 deg. (1σ) or less, for two low energy beams under normal tuning variations, even though no effort was made to control the angle

  15. Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

    Directory of Open Access Journals (Sweden)

    Min-Kyoo Song

    2013-01-01

    Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

  16. Development of parametric material, energy, and emission inventories for wafer fabrication in the semiconductor industry.

    Science.gov (United States)

    Murphy, Cynthia F; Kenig, George A; Allen, David T; Laurent, Jean-Philippe; Dyer, David E

    2003-12-01

    Currently available data suggest that most of the energy and material consumption related to the production of an integrated circuit is due to the wafer fabrication process. The complexity of wafer manufacturing, requiring hundreds of steps that vary from product to product and from facility to facility and which change every few years, has discouraged the development of material, energy, and emission inventory modules for the purpose of insertion into life cycle assessments. To address this difficulty, a flexible, process-based system for estimating material requirements, energy requirements, and emissions in wafer fabrication has been developed. The method accounts for mass and energy use atthe unit operation level. Parametric unit operation modules have been developed that can be used to predict changes in inventory as the result of changes in product design, equipment selection, or process flow. A case study of the application of the modules is given for energy consumption, but a similar methodology can be used for materials, individually or aggregated.

  17. Sample pretreatment for the determination of metal impurities in silicon wafer

    International Nuclear Information System (INIS)

    Chung, H. Y.; Kim, Y. H.; Yoo, H. D.; Lee, S. H.

    1999-01-01

    The analytical results obtained by microwave digestion and acid digestion methods for sample pretreatment to determine metal impurities in silicon wafer by inductively coupled plasma--mass spectrometry(ICP-MS) were compared. In order to decompose the silicon wafer, a mixed solution of HNO 3 and HF was added to the sample and the metal elements were determined after removing the silicon matrix by evaporating silicon in the form of Si-F. The recovery percentages of Ni, Cr and Fe were found to be 95∼106% for both microwave digestion and acid digestion methods. The recovery percentage of Cu obtained by the acid digestion method was higher than that obtained by the microwave digestion method. For Zn, however, the microwave digestion method gave better result than the acid digestion method. Fe was added to a silicon wafer using a spin coater. The concentration of Fe in this sample was determined by ICP-MS, and the same results were obtained in the two pretreatment methods

  18. Electron multibeam technology for mask and wafer writing at 0.1 nm address grid

    Science.gov (United States)

    Platzgummer, Elmar; Klein, Christof; Loeschner, Hans

    2013-07-01

    IMS Nanofabrication realized a 50 keV electron multibeam proof-of-concept (POC) tool confirming writing principles with 0.1 nm address grid and lithography performance capability. The POC system achieves the predicted 5 nm 1 sigma blur across the 82 μm×82 μm array of 512×512 (262,144) programmable 20 nm beams. 24-nm half pitch (HP) has been demonstrated and complex patterns have been written in scanning stripe exposure mode. The first production worthy system for the 11-nm HP mask node is scheduled for 2014 (Alpha), 2015 (Beta), and first-generation high-volume manufacturing multibeam mask writer (MBMW) tools in 2016. In these MBMW systems the max beam current through the column is 1 μA. The new architecture has also the potential for 1× mask (master template) writing. Substantial further developments are needed for maskless e-beam direct write (EBDW) applications as a beam current of >2 mA is needed to achieve 100 wafer per hour industrial targets for 300 mm wafer size. Necessary productivity enhancements of more than three orders of magnitude are only possible by shrinking the multibeam optics such that 50 to 100 subcolumns can be placed on the area of a 300 mm wafer and by clustering 10 to 20 multicolumn tools. An overview of current EBDW efforts is provided.

  19. An attempt to specify thermal history in CZ silicon wafers and possibilities for its modification

    International Nuclear Information System (INIS)

    Kissinger, G.; Sattler, A.; Mueller, T.; Ammon, W. von

    2007-01-01

    The term thermal history of silicon wafers represents the whole variety of process parameters of crystal growth. The aim of this contribution is an attempt to specify thermal history by one parameter that is directly correlated to the bulk microdefect density. The parameter that reflects thermal history and correlates it with nucleation of oxide precipitates is the concentration of VO 2 complexes. The VO 2 concentration in silicon wafers is too low to be measured by FTIR but it can be obtained from the loss of interstitial oxygen during a standardized thermal treatment. Based on this, the vacancy concentration frozen during crystal cooling in the ingot can be calculated. RTA treatments above 1150 deg. C create a well defined level of the VO 2 concentration in silicon wafers. This means that a well controlled modification of the thermal history is possible. We also investigated the kinetics of reduction of the as-grown excess VO 2 concentration during RTA treatments at 950 deg. C and 1050 deg. C and the effectiveness of this attempt to totally delete the thermal history

  20. Optimization of corn, rice and buckwheat formulations for gluten-free wafer production.

    Science.gov (United States)

    Dogan, Ismail Sait; Yildiz, Onder; Meral, Raciye

    2016-07-01

    Gluten-free baked products for celiac sufferers are essential for healthy living. Cereals having gluten such as wheat and rye must be removed from the diet for the clinical and histological improvement. The variety of gluten-free foods should be offered for the sufferers. In the study, gluten-free wafer formulas were optimized using corn, rice and buckwheat flours, xanthan and guar gum blend as an alternative product for celiac sufferers. Wafer sheet attributes and textural properties were investigated. Considering all wafer sheet properties in gluten-free formulas, better results were obtained by using 163.5% water, 0.5% guar and 0.1% xanthan in corn formula; 173.3% water, 0.45% guar and 0.15% xanthan gum in rice formula; 176% water, 0.1% guar and 0.5% xanthan gum in buckwheat formula. Average desirability values in gluten-free formulas were between 0.86 and 0.91 indicating they had similar visual and textural profiles to control sheet made with wheat flour. © The Author(s) 2015.

  1. Xe{sup +} ion beam induced rippled structures on Si miscut wafers

    Energy Technology Data Exchange (ETDEWEB)

    Hanisch, Antje; Grenzer, Joerg [Forschungszentrum Dresden-Rossendorf, Dresden (Germany); Biermanns, Andreas; Pietsch, Ullrich [Institute of Physics, University of Siegen (Germany)

    2009-07-01

    We report on the influence of the initial roughness and crystallography of the substrate on the formation of self-organized ripple structures on semiconductors surfaces by noble gas ion bombardment. The Bradley-Harper theory predicts that an initial roughness is most important for starting the sputtering process which in the ends leads to the evolution of regular patterns. We produced periodic structures with intermediate Xe{sup +} ion energies (5-70 keV) at different incidence and azimuthal angles which lead to the assumption that also crystallography plays a role at the beginning of ripple evolution. Most of the previous investigations started from the original roughness of a polished silicon wafer. We used (001) silicon wafers with a miscut angle of 1 , 5 and 10 towards[110]. We studied the ripple formation keeping the ion beam parallel to the[111],[-1-11] or[-111] direction, i.e. parallel, antiparallel or perpendicular to the miscut direction[110]. The parallel and antiparallel case implies a variation of the incidence angle with increased roughness over the surface step terraces. The perpendicular orientation means almost no roughness. The results were compared to normal Si(001) and Si(111) wafers.

  2. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    Science.gov (United States)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  3. Structural and electrical properties of the GexSi1-x/Si heterojunctions obtained by the method of direct bonding

    International Nuclear Information System (INIS)

    Argunova, T. S.; Belyakova, E. I.; Grekhov, I. V.; Zabrodskii, A. G.; Kostina, L. S.; Sorokin, L. M.; Shmidt, N. M.; Yi, J. M.; Jung, J. W.; Je, J. H.; Abrosimov, N. V.

    2007-01-01

    The results of studying the structural and electrical properties of structures produced by the method of direct bonding of Ge x Si 1-x and Si wafers are reported. The wafers were cut from the crystals grown by the Czochralski method. Continuity of the interface and the crystal-lattice defects were studied by X-ray methods using synchrotron radiation and by scanning electron microscopy. Measurements of the forward and reverse current-voltage characteristics of the p-Ge x Si 1-x /n-Si diodes made it possible to assess the effect of the crystallattice defects on the electrical properties of heterojunctions. Satisfactory electrical parameters suggest that the technology of direct bonding is promising for the fabrication of large-area Ge x Si 1-x /Si heterojunctions

  4. Growth of misfit dislocation-free p/p+ thick epitaxial silicon wafers on Ge-B-codoped substrates

    International Nuclear Information System (INIS)

    Jiang Huihua; Yang Deren; Ma Xiangyang; Tian Daxi; Li Liben; Que Duanlin

    2006-01-01

    The growth of p/p + silicon epitaxial silicon wafers (epi-wafers) without misfit dislocations has been successfully achieved by using heavily boron-doped Czochralski (CZ) silicon wafers codoped with desirable level of germanium as the substrates. The lattice compensation by codoping of germanium and boron into the silicon matrix to reduce the lattice mismatch between the substrate (heavily boron-doped) and epi-layer (lightly boron-doped) is the basic idea underlying in the present achievement. In principle, the codoping of germanium and boron in the CZ silicon can be tailored to achieve misfit dislocation-free epi-layer with required thickness. It is reasonably expected that the presented solution to elimination of misfit dislocations in the p/p + silicon wafers can be applied in the volume production

  5. Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

    Science.gov (United States)

    Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

    This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

  6. Comparison of shear bond strength of the stainless steel metallic brackets bonded by three bonding systems

    Directory of Open Access Journals (Sweden)

    Mehdi Ravadgar

    2013-09-01

    Full Text Available Introduction: In orthodontic treatment, it is essential to establish a satisfactory bond between enamel and bracket. After the self-etch primers (SEPs were introduced for the facilitation of bracket bonding in comparison to the conventional etch-and-bond system, multiple studies have been carried out on their shear bond strengths which have yielded different results. This study was aimed at comparing shear bond strengths of the stainless steel metallic brackets bonded by three bonding systems. Methods: In this experimental in vitro study, 60 extracted human maxillary premolar teeth were randomly divided into three equal groups: in the first group, Transbond XT (TBXT light cured composite was bonded with Transbond plus self-etching primer (TPSEP in the second group, TBXT composite was bonded with the conventional method of acid etching and in the third group, the self cured composite Unite TM bonding adhesive was bonded with the conventional method of acid etching. In all the groups, Standard edgewise-022 metallic brackets (American Orthodontics, Sheboygan, USA were used. Twenty-four hours after the completion of thermocycling, shear bond strength of brackets was measured by Universal Testing Machine (Zwick. In order to compare the shear bond strengths of the groups, the variance analysis test (ANOVA was adopted and p≤0.05 was considered as a significant level. Results: Based on megapascal, the average shear bond strength for the first, second, and third groups was 8.27±1.9, 9.78±2, and 8.92±2.5, respectively. There was no significant difference in the shear bond strength of the groups. Conclusions: Since TPSEP shear bond strength is approximately at the level of the conventional method of acid etching and within the desirable range for orthodontic brackets shear bond strength, applying TPSEP can serve as a substitute for the conventional method of etch and bond, particularly in orthodontic operations.

  7. Comparison of shear bond strength of the stainless steel metallic brackets bonded by three bonding systems

    Directory of Open Access Journals (Sweden)

    Mehdi Ravadgar

    2013-09-01

    Full Text Available Introduction: In orthodontic treatment, it is essential to establish a satisfactory bond between enamel and bracket. After the self-etch primers (SEPs were introduced for the facilitation of bracket bonding in comparison to the conventional etch-and-bond system, multiple studies have been carried out on their shear bond strengths which have yielded different results. This study was aimed at comparing shear bond strengths of the stainless steel metallic brackets bonded by three bonding systems. Methods: In this experimental in vitro study, 60 extracted human maxillary premolar teeth were randomly divided into three equal groups: in the first group, Transbond XT (TBXT light cured composite was bonded with Transbond plus self-etching primer (TPSEP; in the second group, TBXT composite was bonded with the conventional method of acid etching; and in the third group, the self cured composite Unite TM bonding adhesive was bonded with the conventional method of acid etching. In all the groups, Standard edgewise-022 metallic brackets (American Orthodontics, Sheboygan, USA were used. Twenty-four hours after the completion of thermocycling, shear bond strength of brackets was measured by Universal Testing Machine (Zwick. In order to compare the shear bond strengths of the groups, the variance analysis test (ANOVA was adopted and p≤0.05 was considered as a significant level. Results: Based on megapascal, the average shear bond strength for the first, second, and third groups was 8.27±1.9, 9.78±2, and 8.92±2.5, respectively. There was no significant difference in the shear bond strength of the groups. Conclusions: Since TPSEP shear bond strength is approximately at the level of the conventional method of acid etching and within the desirable range for orthodontic brackets shear bond strength, applying TPSEP can serve as a substitute for the conventional method of etch and bond, particularly in orthodontic operations.

  8. Study of the semiconductor properties by irradiation, 8. Study of trapping center by. gamma. -ray on Si wafer

    Energy Technology Data Exchange (ETDEWEB)

    Nakamura, Koji; Shioya, Hitoshi; Nagamatsu, Yasuhiko; Ogura, Shoji [Miyazaki Univ. (Japan). Faculty of Engineering

    1983-08-01

    In order to know the effects of ..gamma..-ray irradiation on n-type Si-wafers, the author did ..gamma..-ray irradiation experiments on n-type Si-wafers. They then observed the trapping center by using DLTS and ICTS equipments. The trapping center level, which is produced by ..gamma..-ray, is about 0.49 eV. In addition, the authors discuss the recombination rate.

  9. Plasma-assisted quartz-to-quartz direct bonding for the fabrication of a multilayered quartz template for nanoimprint lithography

    International Nuclear Information System (INIS)

    Lee, Jihye; Ali, Altun; Kim, Ki-don; Choi, Dae-guen; Choi, Jun-Hyuk; Jeong, Jun-ho; Kim, Jae-Hyun

    2010-01-01

    In this paper, a low-temperature plasma-assisted process is developed to realize a uniform, ultraviolet (UV) transparent and chemically inert quartz-to-quartz direct bonding. Two sets of pretests are performed in order to understand how the bond surface energy changes with the plasma exposure time and the wet etching of quartz, respectively. The developed technique is used to fabricate a multilayered quartz template for UV nanoimprint lithography (UV-NIL). The multilayered quartz template is fabricated by bonding a square piece of a standard quartz wafer, which is about 625 µm in thickness, to a wet-etched 6.35 mm thick quartz photomask plate. A fabricated multilayered template is loaded to the commercial UV-NIL tool Imprio(TM) 100, and NIL was performed successfully. The developed direct bonding technique makes it possible for standard quartz wafers, which are compatible with high-resolution semiconductor fabrication processes, to be utilized as the templates in commercial UV-NIL machines with enhanced mechanical stability.

  10. Why are Hydrogen Bonds Directional?

    Indian Academy of Sciences (India)

    century and most chemists appear to think of 'chemi- cal bond' as ..... These complexes, in their global min- ima, have ... taneously act as hydrogen bond donor and acceptor displaying ... also has a local minimum, which is linear and similar to.

  11. Bond yield curve construction

    Directory of Open Access Journals (Sweden)

    Kožul Nataša

    2014-01-01

    Full Text Available In the broadest sense, yield curve indicates the market's view of the evolution of interest rates over time. However, given that cost of borrowing it closely linked to creditworthiness (ability to repay, different yield curves will apply to different currencies, market sectors, or even individual issuers. As government borrowing is indicative of interest rate levels available to other market players in a particular country, and considering that bond issuance still remains the dominant form of sovereign debt, this paper describes yield curve construction using bonds. The relationship between zero-coupon yield, par yield and yield to maturity is given and their usage in determining curve discount factors is described. Their usage in deriving forward rates and pricing related derivative instruments is also discussed.

  12. Detection of trace contamination of copper on a silicon wafer with TXRF

    International Nuclear Information System (INIS)

    Yamada, T.; Matsuo, M.; Kohno, H.; Mori, Y.

    2000-01-01

    The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. When W-Lβ 1 (9.67 keV) line is used for the excitation in TXRF instrument and when Si(Li) is used as its detector, an escape peak appears at 7.93 keV which is close to the energy of Cu-Kα line(8.04 keV). When the concentration of copper is lower than 10 10 atoms/cm 2 , accurate quantitative analysis is difficult because of the overlapping of the peaks. When Au-Lβ 1 line(11.44 keV) is used for the excitation, the escape peak appears at 9.70 keV which is far enough from the energy of Cu-Ka line. We prepared silicon wafers intentionally contaminated with copper in a low concentration range of 10 8 to 10 10 atoms/cm 2 and measured them with a TXRF instrument having Au-Lβ 1 line for excitation. The contaminated samples were made with IAP method and their Cu concentrations were calibrated with VPD-AAS method (recovery solution: 2 % HF + 2 % H 2 O 2 ). A figure shows the correlation between the results with TXRF and those with AAS. The horizontal axis is the value of concentration decided by AAS and the vertical axis is the intensity of Cu-Kα line measured with the TXRF. Six wafers of different concentration were used and five points on each wafer including the center were measured with TXRF. Five points at each concentration in the figure correspond to the results measured on one wafer. Intensities of Cu-Kα line are weak in these low concentration ranges but the background of them are also very small (less than 0.05 cps). Therefore the peak of Cu-Kα line can be distinguished from the background. It can be said that a calibration curve can be drawn to the middle range of 10 9 atoms/cm 2 . The same samples were measured with another TXRF instrument having W-Lβ 1 line for excitation. It was difficult to draw a calibration curve in this case. We will present both results taken with Au-Lβ 1 line and with W-Lβ 1 line. (author)

  13. Prediction of UV spectra and UV-radiation damage in actual plasma etching processes using on-wafer monitoring technique

    International Nuclear Information System (INIS)

    Jinnai, Butsurin; Fukuda, Seiichi; Ohtake, Hiroto; Samukawa, Seiji

    2010-01-01

    UV radiation during plasma processing affects the surface of materials. Nevertheless, the interaction of UV photons with surface is not clearly understood because of the difficulty in monitoring photons during plasma processing. For this purpose, we have previously proposed an on-wafer monitoring technique for UV photons. For this study, using the combination of this on-wafer monitoring technique and a neural network, we established a relationship between the data obtained from the on-wafer monitoring technique and UV spectra. Also, we obtained absolute intensities of UV radiation by calibrating arbitrary units of UV intensity with a 126 nm excimer lamp. As a result, UV spectra and their absolute intensities could be predicted with the on-wafer monitoring. Furthermore, we developed a prediction system with the on-wafer monitoring technique to simulate UV-radiation damage in dielectric films during plasma etching. UV-induced damage in SiOC films was predicted in this study. Our prediction results of damage in SiOC films shows that UV spectra and their absolute intensities are the key cause of damage in SiOC films. In addition, UV-radiation damage in SiOC films strongly depends on the geometry of the etching structure. The on-wafer monitoring technique should be useful in understanding the interaction of UV radiation with surface and in optimizing plasma processing by controlling UV radiation.

  14. Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

    Science.gov (United States)

    Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

    2018-04-01

    Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

  15. Corporate Hybrid Bonds

    OpenAIRE

    Ahlberg, Johan; Jansson, Anton

    2016-01-01

    Hybrid securities do not constitute a new phenomenon in the Swedish capital markets. Most commonly, hybrids issued by Swedish real estate companies in recent years are preference shares. Corporate hybrid bonds on the other hand may be considered as somewhat of a new-born child in the family of hybrid instruments. These do, as all other hybrid securities, share some equity-like and some debt-like characteristics. Nevertheless, since 2013 the interest for the instrument has grown rapidly and ha...

  16. Hybrid Cat Bonds

    OpenAIRE

    Barrieu, Pauline; Louberge, Henri

    2009-01-01

    Natural catastrophes attract regularly the attention of media and have become a source of public concern. From a financial viewpoint, natural catastrophes represent idiosyncratic risks, diversifiable at the world level. But for reasons analyzed in this paper reinsurance markets are unable to cope with this risk completely. Insurance-linked securities, such as cat bonds, have been issued to complete the international risk transfer process, but their development is disappointing so far. This pa...

  17. Optimal Investment in Structured Bonds

    DEFF Research Database (Denmark)

    Jessen, Pernille; Jørgensen, Peter Løchte

    The paper examines the role of structured bonds in the optimal portfolio of a small retail investor. We consider the typical structured bond essentially repacking an exotic option and a zero coupon bond, i.e. an investment with portfolio insurance. The optimal portfolio is found when the investment...

  18. 46 CFR Sec. 10 - Bonds.

    Science.gov (United States)

    2010-10-01

    ... REPAIRS UNDER NATIONAL SHIPPING AUTHORITY MASTER LUMP SUM REPAIR CONTRACT-NSA-LUMPSUMREP Sec. 10 Bonds. (a... awarded work and the furnishing of the performance and payment bonds required by Article 14 of the NSA... of the NSA-LUMPSUMREP Contract, the standard form of individual performance bond (Standard Form 25...

  19. The chemical bond in inorganic chemistry the bond valence model

    CERN Document Server

    Brown, I David

    2016-01-01

    The bond valence model is a version of the ionic model in which the chemical constraints are expressed in terms of localized chemical bonds formed by the valence charge of the atoms. Theorems derived from the properties of the electrostatic flux predict the rules obeyed by both ionic and covalent bonds. They make quantitative predictions of coordination number, crystal structure, bond lengths and bond angles. Bond stability depends on the matching of the bonding strengths of the atoms, while the conflicting requirements of chemistry and space lead to the structural instabilities responsible for the unusual physical properties displayed by some materials. The model has applications in many fields ranging from mineralogy to molecular biology.

  20. Hydrogen bonding in ionic liquids.

    Science.gov (United States)

    Hunt, Patricia A; Ashworth, Claire R; Matthews, Richard P

    2015-03-07

    Ionic liquids (IL) and hydrogen bonding (H-bonding) are two diverse fields for which there is a developing recognition of significant overlap. Doubly ionic H-bonds occur when a H-bond forms between a cation and anion, and are a key feature of ILs. Doubly ionic H-bonds represent a wide area of H-bonding which has yet to be fully recognised, characterised or explored. H-bonds in ILs (both protic and aprotic) are bifurcated and chelating, and unlike many molecular liquids a significant variety of distinct H-bonds are formed between different types and numbers of donor and acceptor sites within a given IL. Traditional more neutral H-bonds can also be formed in functionalised ILs, adding a further level of complexity. Ab initio computed parameters; association energies, partial charges, density descriptors as encompassed by the QTAIM methodology (ρBCP), qualitative molecular orbital theory and NBO analysis provide established and robust mechanisms for understanding and interpreting traditional neutral and ionic H-bonds. In this review the applicability and extension of these parameters to describe and quantify the doubly ionic H-bond has been explored. Estimating the H-bonding energy is difficult because at a fundamental level the H-bond and ionic interaction are coupled. The NBO and QTAIM methodologies, unlike the total energy, are local descriptors and therefore can be used to directly compare neutral, ionic and doubly ionic H-bonds. The charged nature of the ions influences the ionic characteristics of the H-bond and vice versa, in addition the close association of the ions leads to enhanced orbital overlap and covalent contributions. The charge on the ions raises the energy of the Ylp and lowers the energy of the X-H σ* NBOs resulting in greater charge transfer, strengthening the H-bond. Using this range of parameters and comparing doubly ionic H-bonds to more traditional neutral and ionic H-bonds it is clear that doubly ionic H-bonds cover the full range of weak

  1. A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

    Science.gov (United States)

    Cekli, Hakki Ergun; Nije, Jelle; Ypma, Alexander; Bastani, Vahid; Sonntag, Dag; Niesing, Henk; Zhang, Linmiao; Ullah, Zakir; Subramony, Venky; Somasundaram, Ravin; Susanto, William; Matsunobu, Masazumi; Johnson, Jeff; Tabery, Cyrus; Lin, Chenxi; Zou, Yi

    2018-03-01

    In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a `fingerprint', on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel `computational process control strategy' which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each wafer and on every layer during the

  2. Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

    Science.gov (United States)

    Wang, Shing-Dar; Chen, Ting-Wei

    2018-06-01

    In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

  3. Bump Bonding Using Metal-Coated Carbon Nanotubes

    Science.gov (United States)

    Lamb, James L.; Dickie, Matthew R.; Kowalczyk, Robert S.; Liao, Anna; Bronikowski, Michael J.

    2012-01-01

    Bump bonding hybridization techniques use arrays of indium bumps to electrically and mechanically join two chips together. Surface-tension issues limit bump sizes to roughly as wide as they are high. Pitches are limited to 50 microns with bumps only 8-14 microns high on each wafer. A new process uses oriented carbon nanotubes (CNTs) with a metal (indium) in a wicking process using capillary actions to increase the aspect ratio and pitch density of the connections for bump bonding hybridizations. It merges the properties of the CNTs and the metal bumps, providing enhanced material performance parameters. By merging the bumps with narrow and long CNTs oriented in the vertical direction, higher aspect ratios can be obtained if the metal can be made to wick. Possible aspect ratios increase from 1:1 to 20:1 for most applications, and to 100:1 for some applications. Possible pitch density increases of a factor of 10 are possible. Standard capillary theory would not normally allow indium or most other metals to be drawn into the oriented CNTs, because they are non-wetting. However, capillary action can be induced through the ability to fabricate oriented CNT bundles to desired spacings, and the use of deposition techniques and temperature to control the size and mobility of the liquid metal streams and associated reservoirs. This hybridization of two technologies (indium bumps and CNTs) may also provide for some additional benefits such as improved thermal management and possible current density increases.

  4. Additional disulfide bonds in insulin

    DEFF Research Database (Denmark)

    Vinther, Tine N; Pettersson, Ingrid; Huus, Kasper

    2015-01-01

    The structure of insulin, a glucose homeostasis-controlling hormone, is highly conserved in all vertebrates and stabilized by three disulfide bonds. Recently, we designed a novel insulin analogue containing a fourth disulfide bond located between positions A10-B4. The N-terminus of insulin's B......-chain is flexible and can adapt multiple conformations. We examined how well disulfide bond predictions algorithms could identify disulfide bonds in this region of insulin. In order to identify stable insulin analogues with additional disulfide bonds, which could be expressed, the Cβ cut-off distance had...... in comparison to analogues with additional disulfide bonds that were more difficult to predict. In contrast, addition of the fourth disulfide bond rendered all analogues resistant to fibrillation under stress conditions and all stable analogues bound to the insulin receptor with picomolar affinities. Thus...

  5. Surface and subsurface cracks characteristics of single crystal SiC wafer in surface machining

    Energy Technology Data Exchange (ETDEWEB)

    Qiusheng, Y., E-mail: qsyan@gdut.edu.cn; Senkai, C., E-mail: senkite@sina.com; Jisheng, P., E-mail: panjisheng@gdut.edu.cn [School of Electromechanical Engineering, Guangdong University of Technology, Guangzhou, 510006 (China)

    2015-03-30

    Different machining processes were used in the single crystal SiC wafer machining. SEM was used to observe the surface morphology and a cross-sectional cleavages microscopy method was used for subsurface cracks detection. Surface and subsurface cracks characteristics of single crystal SiC wafer in abrasive machining were analysed. The results show that the surface and subsurface cracks system of single crystal SiC wafer in abrasive machining including radial crack, lateral crack and the median crack. In lapping process, material removal is dominated by brittle removal. Lots of chipping pits were found on the lapping surface. With the particle size becomes smaller, the surface roughness and subsurface crack depth decreases. When the particle size was changed to 1.5µm, the surface roughness Ra was reduced to 24.0nm and the maximum subsurface crack was 1.2µm. The efficiency of grinding is higher than lapping. Plastic removal can be achieved by changing the process parameters. Material removal was mostly in brittle fracture when grinding with 325# diamond wheel. Plow scratches and chipping pits were found on the ground surface. The surface roughness Ra was 17.7nm and maximum subsurface crack depth was 5.8 µm. When grinding with 8000# diamond wheel, the material removal was in plastic flow. Plastic scratches were found on the surface. A smooth surface of roughness Ra 2.5nm without any subsurface cracks was obtained. Atomic scale removal was possible in cluster magnetorheological finishing with diamond abrasive size of 0.5 µm. A super smooth surface eventually obtained with a roughness of Ra 0.4nm without any subsurface crack.

  6. Nanoimprint wafer and mask tool progress and status for high volume semiconductor manufacturing

    Science.gov (United States)

    Matsuoka, Yoichi; Seki, Junichi; Nakayama, Takahiro; Nakagawa, Kazuki; Azuma, Hisanobu; Yamamoto, Kiyohito; Sato, Chiaki; Sakai, Fumio; Takabayashi, Yukio; Aghili, Ali; Mizuno, Makoto; Choi, Jin; Jones, Chris E.

    2016-10-01

    Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for wafer manufacturing. Defectivity and mask life play a significant role relative to meeting the cost of ownership (CoO) requirements in the production of semiconductor devices. Hard particles on a wafer or mask create the possibility of inducing a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, the lifetime of both the master mask and the replica mask can be extended. In this work, we report results that demonstrate a path towards achieving mask lifetimes of better than 1000 wafers. On the mask side, a new replication tool, the FPA-1100 NR2 is introduced. Mask replication is required for nanoimprint lithography (NIL), and criteria that are crucial to the success of a replication platform include both particle control, resolution and image placement accuracy. In this paper we discuss the progress made in both feature resolution and in meeting the image placement specification for replica masks.

  7. Coaxial twin-shaft magnetic fluid seals applied in vacuum wafer-handling robot

    Science.gov (United States)

    Cong, Ming; Wen, Haiying; Du, Yu; Dai, Penglei

    2012-07-01

    Compared with traditional mechanical seals, magnetic fluid seals have unique characters of high airtightness, minimal friction torque requirements, pollution-free and long life-span, widely used in vacuum robots. With the rapid development of Integrate Circuit (IC), there is a stringent requirement for sealing wafer-handling robots when working in a vacuum environment. The parameters of magnetic fluid seals structure is very important in the vacuum robot design. This paper gives a magnetic fluid seal device for the robot. Firstly, the seal differential pressure formulas of magnetic fluid seal are deduced according to the theory of ferrohydrodynamics, which indicate that the magnetic field gradient in the sealing gap determines the seal capacity of magnetic fluid seal. Secondly, the magnetic analysis model of twin-shaft magnetic fluid seals structure is established. By analyzing the magnetic field distribution of dual magnetic fluid seal, the optimal value ranges of important parameters, including parameters of the permanent magnetic ring, the magnetic pole tooth, the outer shaft, the outer shaft sleeve and the axial relative position of two permanent magnetic rings, which affect the seal differential pressure, are obtained. A wafer-handling robot equipped with coaxial twin-shaft magnetic fluid rotary seals and bellows seal is devised and an optimized twin-shaft magnetic fluid seals experimental platform is built. Test result shows that when the speed of the two rotational shafts ranges from 0-500 r/min, the maximum burst pressure is about 0.24 MPa. Magnetic fluid rotary seals can provide satisfactory performance in the application of wafer-handling robot. The proposed coaxial twin-shaft magnetic fluid rotary seal provides the instruction to design high-speed vacuum robot.

  8. Comparative study on the predictability of statistical models (RSM and ANN) on the behavior of optimized buccoadhesive wafers containing Loratadine and their in vivo assessment.

    Science.gov (United States)

    Chakraborty, Prithviraj; Parcha, Versha; Chakraborty, Debarupa D; Ghosh, Amitava

    2016-01-01

    Buccoadhesive wafer dosage form containing Loratadine is formulated utilizing Formulation by Design (FbD) approach incorporating sodium alginate and lactose monohydrate as independent variable employing solvent casting method. The wafers were statistically optimized using Response Surface Methodology (RSM) and Artificial Neural Network algorithm (ANN) for predicting physicochemical and physico-mechanical properties of the wafers as responses. Morphologically wafers were tested using SEM. Quick disintegration of the samples was examined employing Optical Contact Angle (OCA). The comparison of the predictability of RSM and ANN showed a high prognostic capacity of RSM model over ANN model in forecasting mechanical and physicochemical properties of the wafers. The in vivo assessment of the optimized buccoadhesive wafer exhibits marked increase in bioavailability justifying the administration of Loratadine through buccal route, bypassing hepatic first pass metabolism.

  9. Features of the electric-field distribution in anisotropic semiconductor wafers in a transverse magnetic field

    Energy Technology Data Exchange (ETDEWEB)

    Filippov, V. V., E-mail: wwfilippow@mail.ru [Lipetsk State Pedagogical University (Russian Federation); Bormontov, E. N. [Voronezh State University (Russian Federation)

    2013-07-15

    A macroscopic model of the Hall effects and magnetoresistance in anisotropic semiconductor wafers is developed. The results obtained by solving the electrodynamic boundary problem allow the potential and eddy currents in anisotropic semiconductors to be calculated at different current-contact locations, depending on the parameters of the sample material's anisotropy. The results of this study are of great practical importance for investigating the physical properties of anisotropic semiconductors and simulating the electron-transport phenomena in devices based on anisotropic semiconductors.

  10. Magnetic structure of cross-shaped permalloy arrays embedded in silicon wafers

    International Nuclear Information System (INIS)

    Machida, Kenji; Tezuka, Tomoyuki; Yamamoto, Takahiro; Ishibashi, Takayuki; Morishita, Yoshitaka; Koukitu, Akinori; Sato, Katsuaki

    2005-01-01

    This paper describes the observed magnetic structure and the micromagnetic simulation of cross-shaped, permalloy (Ni 80 Fe 20 ) arrays embedded in silicon wafers. The nano-scale-width, cross-shaped patterns were fabricated using the damascene technique, electron beam lithography, and chemical mechanical polishing. The magnetic poles were observed as two pairs of bright and dark spots at the ends of the crossed-bars using a magnetic force microscope. The force gradient distributions were simulated based on micromagnetic calculations and tip's stray field calculations using the integral equation method. This process of calculation successfully explains the appearance of the poles and complicated spin structure at the crossing region

  11. Features of the electric-field distribution in anisotropic semiconductor wafers in a transverse magnetic field

    International Nuclear Information System (INIS)

    Filippov, V. V.; Bormontov, E. N.

    2013-01-01

    A macroscopic model of the Hall effects and magnetoresistance in anisotropic semiconductor wafers is developed. The results obtained by solving the electrodynamic boundary problem allow the potential and eddy currents in anisotropic semiconductors to be calculated at different current-contact locations, depending on the parameters of the sample material’s anisotropy. The results of this study are of great practical importance for investigating the physical properties of anisotropic semiconductors and simulating the electron-transport phenomena in devices based on anisotropic semiconductors

  12. Semi-infinite photocarrier radiometric model for the characterization of semiconductor wafer

    International Nuclear Information System (INIS)

    Liu Xianming; Li Bincheng; Huang Qiuping

    2010-01-01

    The analytical expression is derived to describe the photocarrier radiometric (PCR) signal for a semi-infinite semiconductor wafer excited by a square-wave modulated laser. For comparative study, the PCR signals are calculated by the semi-infinite model and the finite thickness model with several thicknesses. The fitted errors of the electronic transport properties by semi-infinite model are analyzed. From these results it is evident that for thick samples or at high modulation frequency, the semiconductor can be considered as semi-infinite.

  13. Production planning and control for semiconductor wafer fabrication facilities modeling, analysis, and systems

    CERN Document Server

    Mönch, Lars; Mason, Scott J

    2012-01-01

    Over the last fifty-plus years, the increased complexity and speed of integrated circuits have radically changed our world. Today, semiconductor manufacturing is perhaps the most important segment of the global manufacturing sector. As the semiconductor industry has become more competitive, improving planning and control has become a key factor for business success. This book is devoted to production planning and control problems in semiconductor wafer fabrication facilities. It is the first book that takes a comprehensive look at the role of modeling, analysis, and related information systems

  14. Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications

    International Nuclear Information System (INIS)

    Ngo, H-D; Hiess, Andre; Seidemann, Volker; Studzinski, Daniel; Lange, Martin; Leib, Juergen; Shariff, Dzafir; Ashraf, Huma; Steel, Mike; Atabo, Lilian; Reast, Jon

    2006-01-01

    This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained and plasma configurations are described elsewhere. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters

  15. Worker exposure to methanol vapors during cleaning of semiconductor wafers in a manufacturing setting.

    Science.gov (United States)

    Gaffney, Shannon; Moody, Emily; McKinley, Meg; Knutsen, Jeffrey; Madl, Amy; Paustenbach, Dennis

    2008-05-01

    An exposure simulation was conducted to characterize methanol exposure of workers who cleaned wafers in quality control departments within the semiconductor industry. Short-term (15 min) and long-term (2-4 hr) personal and area samples (at distances of 1 m and 3-6 m from the source) were collected during the 2-day simulation. On the first day, 45 mL of methanol were used per hour by a single worker washing wafers in a 102 m(3) room with a ventilation rate of about 10 air changes per hour (ACH). Virtually all methanol volatilized. To assess exposures under conditions associated with higher productivity, on the second day, two workers cleaned wafers simultaneously, together using methanol at over twice the rate of the first day (95 mL/hr). On this day, the ventilation rate was halved (5 ACH). Personal concentrations on the first day averaged 60 ppm (SD = 46 ppm) and ranged from 10-140 ppm. On the second day, personal concentrations for both workers averaged 118 ppm (SD = 50 ppm; range: 64-270 ppm). Area concentrations measured on the first day at 1 m from the source and throughout the balance of the room averaged 29 ppm (SD = 19 ppm; range: 4-83 ppm) and 18 ppm (SD = 12 ppm; range: 3-42 ppm), respectively. As expected, area concentrations measured on the second day were higher than the first and averaged 73 ppm (SD = 25 ppm; range: 27-140 ppm) at 1 meter and 48 ppm (SD = 13 ppm; range: 21-67 ppm) throughout the balance of the room. The results of this simulation suggest that the use of methanol to clean semiconductor wafers without the use of local exhaust ventilation and with relatively low room ventilation rates is unlikely to result in worker exposures exceeding the current ACGIH(R) threshold limit value of 200 ppm. This study also confirmed prior studies suggesting that when a relatively volatile chemical is located within arm's length (near field), breathing zone concentrations will be about two- to threefold greater than the room concentration when the air

  16. Microsized structures assisted nanostructure formation on ZnSe wafer by femtosecond laser irradiation

    International Nuclear Information System (INIS)

    Wang, Shutong; Feng, Guoying; Zhou, Shouhuan

    2014-01-01

    Micro/nano patterning of ZnSe wafer is demonstrated by femtosecond laser irradiation through a diffracting pinhole. The irradiation results obtained at fluences above the ablation threshold are characterized by scanning electron microscopy. The microsized structure with low spatial frequency has a good agreement with Fresnel diffraction theory. Laser induced periodic surface structures and laser-induced periodic curvelet surface structures with high spatial frequency have been found on the surfaces of microsized structures, such as spikes and valleys. We interpret its formation in terms of the interference between the reflected laser field on the surface of the valley and the incident laser pulse

  17. Wafer bowing control of free-standing heteroepitaxial diamond (100) films grown on Ir(100) substrates via patterned nucleation growth

    International Nuclear Information System (INIS)

    Yoshikawa, Taro; Kodama, Hideyuki; Kono, Shozo; Suzuki, Kazuhiro; Sawabe, Atsuhito

    2015-01-01

    The potential of patterned nucleation growth (PNG) technique to control the wafer bowing of free-standing heteroepitaxial diamond films was investigated. The heteroepitaxial diamond (100) films were grown on an Ir(100) substrate via PNG technique with different patterns of nucleation regions (NRs), which were dot-arrays with 8 or 13 μm pitch aligned to < 100 > or < 110 > direction of the Ir(100) substrate. The wafer bows and the local stress distributions of the free-standing films were measured using a confocal micro-Raman spectrometer. For each NR pattern, the stress evolutions within the early stage of diamond growth were also studied together with a scanning electron microscopic observation of the coalescing diamond particles. These investigations revealed that the NR pattern, in terms of pitch and direction of dot-array, strongly affects the compressive stress on the nucleation side of the diamond film and dominantly contributes to the elastic deformation of the free-standing film. This indicates that the PNG technique with an appropriate NR pattern is a promising solution to fabricate free-standing heteroepitaxial diamond films with extremely small bows. - Highlights: • Wafer bowing control of free-standing heteroepitaxial diamond (100) films • Effect of patterned nucleation and growth (PNG) technique on wafer bowing reduction • Influence of nucleation region patterns of PNG on wafer bowing • Internal stress analysis of PNG films via confocal micro-Raman spectroscopy

  18. High quality single atomic layer deposition of hexagonal boron nitride on single crystalline Rh(111) four-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Hemmi, A.; Bernard, C.; Cun, H.; Roth, S.; Klöckner, M.; Kälin, T.; Osterwalder, J.; Greber, T., E-mail: greber@physik.uzh.ch [Physik-Institut, Universität Zürich, CH-8057 Zürich (Switzerland); Weinl, M.; Gsell, S.; Schreck, M. [Institut für Physik, Universität Augsburg, D-86135 Augsburg (Germany)

    2014-03-15

    The setup of an apparatus for chemical vapor deposition (CVD) of hexagonal boron nitride (h-BN) and its characterization on four-inch wafers in ultra high vacuum (UHV) environment is reported. It provides well-controlled preparation conditions, such as oxygen and argon plasma assisted cleaning and high temperature annealing. In situ characterization of a wafer is accomplished with target current spectroscopy. A piezo motor driven x-y stage allows measurements with a step size of 1 nm on the complete wafer. To benchmark the system performance, we investigated the growth of single layer h-BN on epitaxial Rh(111) thin films. A thorough analysis of the wafer was performed after cutting in atmosphere by low energy electron diffraction, scanning tunneling microscopy, and ultraviolet and X-ray photoelectron spectroscopies. The apparatus is located in a clean room environment and delivers high quality single layers of h-BN and thus grants access to large area UHV processed surfaces, which had been hitherto restricted to expensive, small area single crystal substrates. The facility is versatile enough for customization to other UHV-CVD processes, e.g., graphene on four-inch wafers.

  19. Improvements to the solar cell efficiency and production yields of low-lifetime wafers with effective phosphorus gettering

    International Nuclear Information System (INIS)

    Lu, Jiunn-Chenn; Chen, Ping-Nan; Chen, Chih-Min; Wu, Chung-Han

    2013-01-01

    Highlights: • Variable-temperature gettering improves efficiencies when the wafer quality is poor. • High-quality wafers need not be used for variable-temperature gettering. • The proposed gettering method is based on an existing diffusion process. • It has a potential interest for hot-spot prevention. -- Abstract: This research focuses on the improvement of solar cell efficiencies in low-lifetime wafers by implementing an appropriate gettering method of the diffusion process. The study also considers a reduction in the value of the reverse current at −12 V, an important electrical parameter related to the hot-spot heating of solar cells and modules, to improve the product's quality during commercial mass production. A practical solar cell production case study is examined to illustrate the use of the proposed method. The results of this case study indicate that variable-temperature gettering significantly improves solar cell efficiencies by 0.14% compared to constant-temperature methods when the wafer quality is poor. Moreover, this study finds that variable-temperature gettering raises production yields of low quality wafers by more than 30% by restraining the measurement value of the reverse current at −12 V during solar cell manufacturing

  20. Fatigue aging of adhesive bonds

    International Nuclear Information System (INIS)

    DeLollis, N.J.

    1979-01-01

    A year long study has been made of the effect of fatigue on the bond between two epoxy encapsulant formulations and a fused alumina disc. The variables studied included isothermal aging at temperatures up to and including the cure temperature and cyclic thermal aging from +74 to -54 0 C. The encapsulants were glass microballoon filled epoxies differing only in curing agents. One was cured with an aromatic amine eutectic (Shell Curing Agent Z). The other was cured with diethanolamine. The Z cured encapsulant bond failed completely at the bond interface with little or no aging; infrared evidence indicated a soluble interlayer as a possible cause of failure. The diethanolamine cured encapsulant survived a year of isothermal aging with little or no evidence of bond degradation. Cyclic thermal aging resulted in gradual bond failure with time. An extrapolation of the cyclic aging data indicates that the stresses induced by thermal cycling would result in complete bond failure in about 1200 days

  1. Determination of the thickness distribution of a graphene layer grown on a 2″ SiC wafer by means of Auger electron spectroscopy depth profiling

    International Nuclear Information System (INIS)

    Kotis, L.; Gurban, S.; Pecz, B.; Menyhard, M.; Yakimova, R.

    2014-01-01

    Highlights: • The thickness of graphene grown on SiC was determined by AES depth profiling. • The AES depth profiling verified the presence of buffer layer on SiC. • The presence of unsaturated Si bonds in the buffer layer has been shown. • Using multipoint analysis thickness distribution of the graphene on the wafer was determined. - Abstract: Auger electron spectroscopy (AES) depth profiling was applied for determination of the thickness of a macroscopic size graphene sheet grown on 2 in. 6H-SiC (0 0 0 1) by sublimation epitaxy. The measured depth profile deviated from the expected exponential form showing the presence of an additional, buffer layer. The measured depth profile was compared to the simulated one which allowed the derivation of the thicknesses of the graphene and buffer layers and the Si concentration of buffer layer. It has been shown that the graphene-like buffer layer contains about 30% unsaturated Si. The depth profiling was carried out in several points (diameter 50 μm), which permitted the constructing of a thickness distribution characterizing the uniformity of the graphene sheet

  2. What is a hydrogen bond?

    Indian Academy of Sciences (India)

    First page Back Continue Last page Overview Graphics. What is a hydrogen bond? Precise definition of a hydrogen bond is still elusive!1. Several criteria are listed usually for X-H•••Y, X and Y initially thought to be F, O and N only1. Structural: The X-Y bond length is less than the sum of their van der Waals radii. X-H•••Y is ...

  3. Composite interlayer for diffusion bonding

    International Nuclear Information System (INIS)

    1976-01-01

    A ductile interlayer is described, which is useful for transient liquid phase diffusion bonding of metallic articles; the interlayer consisting of a melting point depressant and a plurality of ductile lamellae which are free from carbides, aluminides and borides. The composition and fabrication of the lamellae, and the process for bonding the metallic articles, depend on the composition of the metals to be bonded, and are exemplified in the specification. (U.K.)

  4. A simplified indirect bonding technique

    Directory of Open Access Journals (Sweden)

    Radha Katiyar

    2014-01-01

    Full Text Available With the advent of lingual orthodontics, indirect bonding technique has become an integral part of practice. It involves placement of brackets initially on the models and then their transfer to teeth with the help of transfer trays. Problems encountered with current indirect bonding techniques used are (1 the possibility of adhesive flash remaining around the base of the brackets which requires removal (2 longer time required for the adhesive to gain enough bond strength for secure tray removal. The new simplified indirect bonding technique presented here overcomes both these problems.

  5. Human Bond Communication

    DEFF Research Database (Denmark)

    Prasad, Ramjee

    2016-01-01

    Modern dexterous communication technology is progressively enabling humans to communicate their information through them with speech (aural) and media (optical) as underpinning essence. Humans realize this kind of aural and optical information by their optical and auditory senses. However, due...... to certain constraints, the ability to incorporate the other three sensory features namely, olfactory, gustatory, and tactile are still far from reality. Human bond communication is a novel concept that incorporates olfactory, gustatory, and tactile that will allow more expressive and holistic sensory...... information exchange through communication techniques for more human sentiment centric communication. This concept endorses the need of inclusion of other three senses and proposes an innovative approach of holistic communication for future communication network....

  6. Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

    Science.gov (United States)

    Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

    2017-09-01

    Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

  7. CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

    Directory of Open Access Journals (Sweden)

    Pei-Zen Chang

    2012-12-01

    Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

  8. Preparation of immobilized glucose oxidase wafer enzyme on calcium-bentonite modified by surfactant

    Science.gov (United States)

    Widi, R. K.; Trisulo, D. C.; Budhyantoro, A.; Chrisnasari, R.

    2017-07-01

    Wafer glucose oxidase (GOx) enzymes was produced by addition of PAH (Poly-Allyamine Hydrochloride) polymer into immobilized GOx enzyme on modified-Tetramethylammonium Hydroxide (TMAH) 5%-calsium-bentonite. The use of surfactant molecul (TMAH) is to modify the surface properties and pore size distribution of the Ca-bentonite. These properties are very important to ensure GOx molecules can be bound on the Ca-bentonit surface to be immobilized. The addition of the polymer (PAH) is expected to lead the substrates to be adsorbed onto the enzyme. In this study, wafer enzymes were made in various concentration ratio (Ca-bentonite : PAH) which are 1:0, 1:1, 1:2 and 1:3. The effect of PAH (Poly-Allyamine Hydrochloride) polymer added with various ratios of concentrations can be shown from the capacitance value on LCR meter and enzyme activity using DNS method. The addition of the polymer (PAH) showed effect on the activity of GOx, it can be shown from the decreasing of capacitance value by increasing of PAH concentration.

  9. Wafer-level chip-scale packaging analog and power semiconductor applications

    CERN Document Server

    Qu, Shichun

    2015-01-01

    This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

  10. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    International Nuclear Information System (INIS)

    Vega, M; Lasorsa, C; Lerner, B; Perez, M; Granell, P

    2016-01-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production. (paper)

  11. Preliminary reduction of chromium ore using Si sludge generated in silicon wafer manufacturing process

    Directory of Open Access Journals (Sweden)

    Jung W.-G.

    2018-01-01

    Full Text Available In order to promote the recycling of by-product from Si wafer manufacturing process and to develop environment-friend and low cost process for ferrochrome alloy production, a basic study was performed on the preliminary reduction reaction between chromium ore and the Si sludge, comprised of SiC and Si particles, which is recovered from the Si wafer manufacturing process for the semiconductor and solar cell industries. Pellets were first made by mixing chromium ore, Si sludge, and some binders in the designed mixing ratios and were then treated at different temperatures in the 1116°C–1388°C range in an ambient atmosphere. Cordierite and SiO2 were confirmed to be formed in the products after the reduction. Additionally, metal particles were observed in the product with Fe, Cr, and Si components. It is found that temperatures above 1300°C are necessary for the reduction of the chromium ore by the Si sludge. The reduction ratio for Fe was evaluated quantitatively for our experimental conditions, and the proper mixing ratio was suggested for the pre-reduction of the chromium ore by the Si sludge. This study provides basic information for the production of ferrochrome alloys on the pre-reduction of chromium ore using Si sludge.

  12. Sliding-mode control combined with improved adaptive feedforward for wafer scanner

    Science.gov (United States)

    Li, Xiaojie; Wang, Yiguang

    2018-03-01

    In this paper, a sliding-mode control method combined with improved adaptive feedforward is proposed for wafer scanner to improve the tracking performance of the closed-loop system. Particularly, In addition to the inverse model, the nonlinear force ripple effect which may degrade the tracking accuracy of permanent magnet linear motor (PMLM) is considered in the proposed method. The dominant position periodicity of force ripple is determined by using the Fast Fourier Transform (FFT) analysis for experimental data and the improved feedforward control is achieved by the online recursive least-squares (RLS) estimation of the inverse model and the force ripple. The improved adaptive feedforward is given in a general form of nth-order model with force ripple effect. This proposed method is motivated by the motion controller design of the long-stroke PMLM and short-stroke voice coil motor for wafer scanner. The stability of the closed-loop control system and the convergence of the motion tracking are guaranteed by the proposed sliding-mode feedback and adaptive feedforward methods theoretically. Comparative experiments on a precision linear motion platform can verify the correctness and effectiveness of the proposed method. The experimental results show that comparing to traditional method the proposed one has better performance of rapidity and robustness, especially for high speed motion trajectory. And, the improvements on both tracking accuracy and settling time can be achieved.

  13. Shear horizontal wave excitation and reception with shear horizontal piezoelectric wafer active sensor (SH-PWAS)

    International Nuclear Information System (INIS)

    Kamal, A; Giurgiutiu, V

    2014-01-01

    This article discusses shear horizontal (SH) guided-waves that can be excited with shear type piezoelectric wafer active sensor (SH-PWAS). The paper starts with a review of state of the art SH waves modelling and their importance in non-destructive evaluation (NDE) and structural health monitoring (SHM). The basic piezoelectric sensing and actuation equations for the case of shear horizontal piezoelectric wafer active sensor (SH-PWAS) with electro-mechanical coupling coefficient d 35 are reviewed. Multiphysics finite element modelling (MP-FEM) was performed on a free SH-PWAS to show its resonance modeshapes. The actuation mechanism of the SH-PWAS is predicted by MP-FEM, and modeshapes of excited structure are presented. The structural resonances are compared with experimental measurements and showed good agreement. Analytical prediction of SH waves was performed. SH wave propagation experimental study was conducted between different combinations of SH-PWAS and regular in-plane PWAS transducers. Experimental results were compared with analytical predictions for aluminium plates and showed good agreement. 2D wave propagation effects were studied by MP-FEM. An analytical model was developed for SH wave power and energy. The normal mode expansion (NME) method was used to account for superpositioning multimodal SH waves. Modal participation factors were presented to show the contribution of every mode. Power and energy transfer between SH-PWAS and the structure was analyzed. Finally, we present simulations of our developed wave power and energy analytical models. (paper)

  14. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    Science.gov (United States)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  15. Self-consistent simulation study on magnetized inductively coupled plasma for 450 mm semiconductor wafer processing

    International Nuclear Information System (INIS)

    Lee, Ho-Jun; Kim, Yun-Gi

    2012-01-01

    The characteristics of weakly magnetized inductively coupled plasma (MICP) are investigated using a self-consistent simulation based on the drift–diffusion approximation with anisotropic transport coefficients. MICP is a plasma source utilizing the cavity mode of the low-frequency branch of the right-hand circularly polarized wave. The model system is 700 mm in diameter and has a 250 mm gap between the radio-frequency window and wafer holder. The model chamber size is chosen to verify the applicability of this type of plasma source to the 450 mm wafer process. The effects of electron density distribution and external axial magnetic field on the propagation properties of the plasma wave, including the wavelength modulation and refraction toward the high-density region, are demonstrated. The restricted electron transport and thermal conductivity in the radial direction due to the magnetic field result in small temperature gradient along the field lines and off-axis peak density profile. The calculated impedance seen from the antenna terminal shows that MICP has a resistance component that is two to threefold higher than that of ICP. This property is practically important for large-size, low-pressure plasma sources because high resistance corresponds to high power-transfer efficiency and stable impedance matching characteristics. For the 0.665 Pa argon plasma, MICP shows a radial density uniformity of 6% within 450 mm diameter, which is much better than that of nonmagnetized ICP.

  16. Control of cavitation using dissolved carbon dioxide for damage-free megasonic cleaning of wafers

    Science.gov (United States)

    Kumari, Sangita

    This dissertation describes the finding that dissolved carbon dioxide is a potent inhibitor of sonoluminescence and describes the implications of the finding in the development of improved megasonic cleaning formulations. Megasonic cleaning, or the removal of contaminants particles from wafer surfaces using sound-irradiated cleaning fluids, has been traditionally used in the semiconductor industry for cleaning of wafers. A critical challenge in the field is to achieve removal of small particles (22 nm to 200 nm) without causing damage to fine wafer features. The work described here addresses this challenge by identifying sonoluminescence and solution pH as two key factors affecting damage and cleaning efficiency, respectively and establishing novel means to control them using CO2(aq) release compounds in the presence of acids and bases. Sonoluminescence (SL) behavior of the major dissolved gases such as Ar, Air, N2, O2 and CO2 was determined using a newly designed Cavitation Threshold Cell (CT Cell). SL, which is the phenomenon of release of light in sound-irradiated liquids, is a sensitive indicator of cavitation, primarily transient cavitation. It was found that all the tested dissolved gases such as Ar, Air, N2 and O2, generated SL signal efficiently. However, dissolved CO2 was found to be completely incapable of generating SL signal. Based on this interesting result, gradual suppression of SL signal was demonstrated using CO2(aq). It was further demonstrated that CO2(aq) is not only incapable but is also a potent inhibitor of SL. The inhibitory role of CO2(aq) was established using a novel method of controlled in-situ release of CO 2 from NH4HCO3. ~130 ppm CO2(aq) was shown to be necessary and sufficient for complete suppression of SL generation in air saturated DI water. The method however required acidification of solution for significant release of CO2, making it unsuitable for the design of cleaning solutions at high pH. Analysis of the underlying ionic

  17. Process induced sub-surface damage in mechanically ground silicon wafers

    International Nuclear Information System (INIS)

    Yang Yu; De Munck, Koen; Teixeira, Ricardo Cotrin; Swinnen, Bart; De Wolf, Ingrid; Verlinden, Bert

    2008-01-01

    Micro-Raman spectroscopy, scanning electron microcopy, atomic force microscopy and preferential etching were used to characterize the sub-surface damage induced by the rough and fine grinding steps used to make ultra-thin silicon wafers. The roughly and ultra-finely ground silicon wafers were examined on both the machined (1 0 0) planes and the cross-sectional (1 1 0) planes. They reveal similar multi-layer damage structures, consisting of amorphous, plastically deformed and elastically stressed layers. However, the thickness of each layer in the roughly ground sample is much higher than its counterpart layers in the ultra-finely ground sample. The residual stress after rough and ultra-fine grinding is in the range of several hundreds MPa and 30 MPa, respectively. In each case, the top amorphous layer is believed to be the result of sequential phase transformations (Si-I to Si-II to amorphous Si). These phase transformations correspond to a ductile grinding mechanism, which is dominating in ultra-fine grinding. On the other hand, in rough grinding, a mixed mechanism of ductile and brittle grinding causes multi-layer damage and sub-surface cracks

  18. Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

    Directory of Open Access Journals (Sweden)

    Nuno Brito

    2016-09-01

    Full Text Available The uniqueness of microelectromechanical system (MEMS devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr, quality factor (Q, and pull-in voltage (Vpi within 1.5 s with repeatability better than 5 ppt (parts per thousand. A full-wafer with 420 devices under test (DUTs has been evaluated detecting the faulty devices and providing important design specification feedback to the designers.

  19. Aerosol-assisted extraction of silicon nanoparticles from wafer slicing waste for lithium ion batteries.

    Science.gov (United States)

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-03-30

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

  20. Relation between film character and wafer alignment: critical alignment issues on HV device for VLSI manufacturing

    Science.gov (United States)

    Lo, Yi-Chuan; Lee, Chih-Hsiung; Lin, Hsun-Peng; Peng, Chiou-Shian

    1998-06-01

    Several continuous splits for wafer alignment target topography conditions to improve epitaxy film alignment were applied. The alignment evaluation among former layer pad oxide thickness (250 angstrom - 500 angstrom), drive oxide thickness (6000 angstrom - 10000 angstrom), nitride film thickness (600 angstrom - 1500 angstrom), initial oxide etch (fully wet etch, fully dry etch and dry plus wet etch) will be split to this experiment. Also various epitaxy deposition recipe such as: epitaxy source (SiHCl2 or SiCHCl3) and growth rate (1.3 micrometer/min approximately 2.0 micrometer/min) will be used to optimize the process window for alignment issue. All the reflectance signal and cross section photography of alignment target during NIKON stepper alignment process will be examined. Experimental results show epitaxy recipe plays an important role to wafer alignment. Low growth rate with good performance conformity epitaxy lead to alignment target avoid washout, pattern shift and distortion. All the results (signal monitor and film character) combined with NIKON's stepper standard laser scanning alignment system will be discussed in this paper.

  1. Big data driven cycle time parallel prediction for production planning in wafer manufacturing

    Science.gov (United States)

    Wang, Junliang; Yang, Jungang; Zhang, Jie; Wang, Xiaoxi; Zhang, Wenjun Chris

    2018-07-01

    Cycle time forecasting (CTF) is one of the most crucial issues for production planning to keep high delivery reliability in semiconductor wafer fabrication systems (SWFS). This paper proposes a novel data-intensive cycle time (CT) prediction system with parallel computing to rapidly forecast the CT of wafer lots with large datasets. First, a density peak based radial basis function network (DP-RBFN) is designed to forecast the CT with the diverse and agglomerative CT data. Second, the network learning method based on a clustering technique is proposed to determine the density peak. Third, a parallel computing approach for network training is proposed in order to speed up the training process with large scaled CT data. Finally, an experiment with respect to SWFS is presented, which demonstrates that the proposed CTF system can not only speed up the training process of the model but also outperform the radial basis function network, the back-propagation-network and multivariate regression methodology based CTF methods in terms of the mean absolute deviation and standard deviation.

  2. A study of UO2 wafer fuel for very high-power research reactors

    International Nuclear Information System (INIS)

    Hsieh, T.C.; Jankus, V.Z.; Rest, J.; Billone, M.C.

    1983-01-01

    The Reduced Enrichment Research and Test Reactor Program is aimed at reducing fuel enrichment to 2 caramel fuel is one of the most promising new types of reduced-enrichment fuel for use in research reactors with very high power density. Parametric studies have been carried out to determine the maximum specific power attainable without significant fission-gas release for UO 2 wafers ranging from 0.75 to 1.50 mm in thickness. The results indicate that (1) all the fuel designs considered in this study are predicted not to fail under full power operation up to a burnup, of 1.9x10 21 fis/cm 3 ; (2) for all fuel designs, failure is predicted at approximately the same fuel centerline temperature for a given burnup; (3) the thinner the wafer, the wider the margin for fuel specific power between normal operation and increased-power operation leading to fuel failure; (4) increasing the coolant pressure in the reactor core could improve fuel performance by maintaining the fuel at a higher power level without failure for a given burnup; and (5) for a given power level, fuel failure will occur earlier at a higher cladding surface temperature and/or under power-cycling conditions. (author)

  3. Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

    International Nuclear Information System (INIS)

    Moslehi, M.M.; Davis, C.

    1989-01-01

    Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

  4. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  5. Homogeneous transparent conductive ZnO:Ga by ALD for large LED wafers

    Energy Technology Data Exchange (ETDEWEB)

    Szabó, Zoltán; Baji, Zsófia [MTA EK Institute of Technical Physics and Materials Science, Konkoly Thege M. út 29-33, 1121 Budapest (Hungary); Basa, Péter [Semilab Semiconductor Physics Laboratory Co. Ltd., Prielle K. u. 2, H-1117 Budapest (Hungary); Czigány, Zsolt; Bársony, István [MTA EK Institute of Technical Physics and Materials Science, Konkoly Thege M. út 29-33, 1121 Budapest (Hungary); Wang, Hsin-Ying [Epistar corporation No 5, Li-hsin 5th Rd., Hsinchu Science Park, Hsinchu 300, Taiwan (China); Volk, János, E-mail: volk@mfa.kfki.hu [MTA EK Institute of Technical Physics and Materials Science, Konkoly Thege M. út 29-33, 1121 Budapest (Hungary)

    2016-08-30

    Highlights: • Highly conductive, transparent GZO layers were deposited by ALD. • The ALD layers show superior thickness and sheet resistance homogeneity for 4” wafers. • A two-step ALD deposition technique was proposed and demonstrated to improve the quality of GZO/p-GaN interface. - Abstract: Highly conductive and uniform Ga doped ZnO (GZO) films were prepared by atomic layer deposition (ALD) as transparent conductive layers for InGaN/GaN LEDs. The optimal Ga doping concentration was found to be 3 at%. Even for 4” wafers, the TCO layer shows excellent homogeneity of film resistivity (0.8 %) according to Eddy current and spectroscopic ellipsometry mapping. This makes ALD a favourable technique over concurrent methods like MBE and PLD where the up-scaling is problematic. In agreement with previous studies, it was found that by an annealing treatment the quality of the GZO/p-GaN interface can be improved, although it causes the degradation of TCO conductivity. Therefore, a two-step ALD deposition technique was proposed and demonstrated: a “buffer layer” deposited and annealed first was followed by a second deposition step to maintain the high conductivity of the top layer.

  6. 30 CFR 281.33 - Bonds and bonding requirements.

    Science.gov (United States)

    2010-07-01

    ... 30 Mineral Resources 2 2010-07-01 2010-07-01 false Bonds and bonding requirements. 281.33 Section 281.33 Mineral Resources MINERALS MANAGEMENT SERVICE, DEPARTMENT OF THE INTERIOR OFFSHORE LEASING OF MINERALS OTHER THAN OIL, GAS, AND SULPHUR IN THE OUTER CONTINENTAL SHELF Financial Considerations § 281.33...

  7. 29 CFR 2580.412-19 - Term of the bond, discovery period, other bond clauses.

    Science.gov (United States)

    2010-07-01

    ... SECURITY ACT OF 1974 TEMPORARY BONDING RULES General Bond Rules § 2580.412-19 Term of the bond, discovery... 29 Labor 9 2010-07-01 2010-07-01 false Term of the bond, discovery period, other bond clauses... new bond must be obtained each year. There is nothing in the Act that prohibits a bond for a term...

  8. Use of acoustic waves and x-ray radiation for determination of small deformations in monocrystalline Si wafers

    International Nuclear Information System (INIS)

    Gavrilov, V.N.; Myasishchev, D.E.; Raitman, E.A.

    2006-01-01

    The paper describes a new method for determination of inhomogeneous deformations in monocrystalline semiconductor wafers. The physical basis of the method is dynamical scattering of X-rays by ultra-sound waves in the presence of static stresses in the crystal. By solving approximately a modified Takagi-Taupin equation the expressions have been obtained that describe relative variations of the diffraction intensity depending on the deformation gradient, the amplitude of ultra-sound wave and its frequency. The paper exemplifies the use of the method for analyzing the deformations and their distribution near the wafer surface in almost 'perfect' crystals and in oxidized wafers with etched windows. It is shown that the new method of nondestructive control, along with its relative simplicity, possesses high sensitivity allowing relative deformations of crystalline lattice of the order of 10-4-10-5 to be determined. (Authors)

  9. Comparison of slowness profiles of lamb wave with elastic moduli and crystal structure in single crystalline silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Min, Young Jae; Yun, Gyeong Won; Kim, Kyung Min; Roh, Yuji; Kim, Young H. [Applied Acoustics Lab, Korea Science Academy of KAIST, Busan (Korea, Republic of)

    2016-02-15

    Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

  10. Wafer Surface Charge Reversal as a Method of Simplifying Nanosphere Lithography for Reactive Ion Etch Texturing of Solar Cells

    Directory of Open Access Journals (Sweden)

    Daniel Inns

    2007-01-01

    Full Text Available A simplified nanosphere lithography process has been developed which allows fast and low-waste maskings of Si surfaces for subsequent reactive ion etching (RIE texturing. Initially, a positive surface charge is applied to a wafer surface by dipping in a solution of aluminum nitrate. Dipping the positive-coated wafer into a solution of negatively charged silica beads (nanospheres results in the spheres becoming electrostatically attracted to the wafer surface. These nanospheres form an etch mask for RIE. After RIE texturing, the reflection of the surface is reduced as effectively as any other nanosphere lithography method, while this batch process used for masking is much faster, making it more industrially relevant.

  11. Stabilisation of a thin crystalline Si wafer solar cell using glass substrate; Duenne kristalline Silizium Wafer-Solarzelle mit Glastraeger stabilisiert

    Energy Technology Data Exchange (ETDEWEB)

    Muehlbauer, Maria

    2009-07-01

    An attempt was made to stabilise ultrathin crystalline silicon wafers (< 100 {mu}m) by a support material (BOROFLOAT33 by Schott Glas). It was found that the total serial resistance results mainly from the specific resistance of the back contact, and that especially the ultrathin solar cells have high recombination in the back. The ultrathin Si wafers also are slightly corrugated, which results in uneven joining of the Si wafer with the glass support. For optimisation, the solar cells of this specific types, with different thicknesses, were modelled in the one-dimensional simulation code PC1D, including all material-specific and electric properties. It was found that a slight reduction of the serial resistance will be enough for a significant improvement of the efficiency of the stabilized solar cell. With this knowledge, selective optimisation of the stabilised solar cells was possible, with the following results: 1. The improved temperature-time profile of the RTP step will improve the solar cell parameters for all Si thicknesses, which is assumed to be the result of better quality of the Al/Si back contact. 2. Thicker aluminium layers improved passivation on the back of solar cells with a thickness of 300 {mu}m and 120 {mu}m. In thinner stabilised solar cells, this measure resulted in enhanced formation of shunts and did not reduce the recombination rate on the back of the solar cell. 3. An additional optimisation step was the introduction of the so-called 'combined method' in which part of the aluminium layer is replaced by silkscreen paste. This combination, with adequate preparation, ensures uniform joining of the ultrathin silicon to the glass carrier. The resulting intermediate layers are highly homogeneous and have good fill factors and current densities for thin solar cells with a si thickness of 60 {mu}m. A decisive argument for the combined method is its near-100% reproducibility. [German] Ziel dieser Arbeit ist es sehr duenne kristalline

  12. The role of Gliadel wafers in the treatment of newly diagnosed GBM: a meta-analysis

    Directory of Open Access Journals (Sweden)

    Xing WK

    2015-06-01

    Full Text Available Wei-kang Xing,1 Chuan Shao,2 Zhen-yu Qi,1 Chao Yang,1 Zhong Wang1 1Department of Neurosurgery, The First Affiliated Hospital of Soochow University, Suzhou, Jiangsu, 2Department of Neurosurgery, The Second Clinical Medical College of North Sichuan Medical College, Nanchong, Sichuan, People’s Republic of China Background: Standard treatment for high-grade glioma (HGG includes surgery followed by radiotherapy and/or chemotherapy. Insertion of carmustine wafers into the resection cavity as a treatment for malignant glioma is currently a controversial topic among neurosurgeons. Our meta-analysis focused on whether carmustine wafer treatment could significantly benefit the survival of patients with newly diagnosed glioblastoma multiforme (GBM.Method: We searched the PubMed and Web of Science databases without any restrictions on language using the keywords “Gliadel wafers”, “carmustine wafers”, “BCNU wafers”, or “interstitial chemotherapy” in newly diagnosed GBM for the period from January 1990 to March 2015. Randomized controlled trials (RCTs and cohort studies/clinical trials that compared treatments designed with and without carmustine wafers and which reported overall survival or hazard ratio (HR or survival curves were included in this study. Moreover, the statistical analysis was conducted by the STATA 12.0 software.Results: Six studies including two RCTs and four cohort studies, enrolling a total of 513 patients (223 with and 290 without carmustine wafers, matched the selection criteria. Carmustine wafers showed a strong advantage when pooling all the included studies (HR =0.63, 95% confidence interval (CI =0.49–0.81; P=0.019. However, the two RCTs did not show a statistical increase in survival in the group with carmustine wafer compared to the group without it (HR =0.51, 95% CI =0.18–1.41; P=0.426, while the cohort studies demonstrated a significant survival increase (HR =0.59, 95% CI =0.44–0.79; P<0.0001.Conclusion

  13. O hydrogen bonds in alkaloids

    Indian Academy of Sciences (India)

    An overview of general classification scheme, medicinal importance and crystal structure analysis with emphasis on the role of hydrogen bonding in some alkaloids is presented in this paper. The article is based on a general kind of survey while crystallographic analysis and role of hydrogen bonding are limited to only ...

  14. Distance criterion for hydrogen bond

    Indian Academy of Sciences (India)

    First page Back Continue Last page Overview Graphics. Distance criterion for hydrogen bond. In a D-H ...A contact, the D...A distance must be less than the sum of van der Waals Radii of the D and A atoms, for it to be a hydrogen bond.

  15. Optimal Investment in Structured Bonds

    DEFF Research Database (Denmark)

    Jessen, Pernille; Jørgensen, Peter Løchte

    2012-01-01

    of the article is to provide possible explanations for the puzzle of why small retail investors hold structured bonds. The investment universe consists of a stock index, a risk-free bank account, and a structured bond containing an option written on another index. We apply expected utility maximization...

  16. SOCIAL BONDING: REGULATION BY NEUROPEPTIDES

    Directory of Open Access Journals (Sweden)

    Claudia eLieberwirth

    2014-06-01

    Full Text Available Affiliative social relationships (e.g., among spouses, family members, and friends play an essential role in human society. These relationships affect psychological, physiological, and behavioral functions. As positive and enduring bonds are critical for the overall well-being of humans, it is not surprising that considerable effort has been made to study the neurobiological mechanisms that underlie social bonding behaviors. The present review details the involvement of the nonapeptides, oxytocin (OT and arginine vasopressin (AVP, in the regulation of social bonding in mammals including humans. In particular, we will discuss the role of OT and AVP in the formation of social bonds between partners of a mating pair as well as between parents and their offspring. Furthermore, the role of OT and AVP in the formation of interpersonal bonding involving trust is also discussed.

  17. Sibling bereavement and continuing bonds.

    Science.gov (United States)

    Packman, Wendy; Horsley, Heidi; Davies, Betty; Kramer, Robin

    2006-11-01

    Historically, from a Freudian and medical model perspective, emotional disengagement from the deceased was seen as essential to the successful adaptation of bereavement. A major shift in the bereavement literature has occurred and it is now generally accepted that despite the permanence of physical separation, the bereaved remains involved and connected to the deceased and can be emotionally sustained through continuing bonds. The majority of literature has focused on adults and on the nature of continuing bonds following the death of a spouse. In this article, the authors demonstrate how the continuing bonds concept applies to the sibling relationship. We describe the unique continued relationship formed by bereaved children and adolescents following a sibling loss, highlight the factors that influence the siblings continuing bonds expressions, and offer clinical interventions. In our view, mental health professionals can play an important role in helping parents encourage activities that may facilitate the creation and maintenance of continuing bonds in their children.

  18. Structure phenomena in the bond zone of explosively bonded plates

    International Nuclear Information System (INIS)

    Livne, Z.

    1979-12-01

    In the bond areas of couples of explosively bonded plates, there are often zones, generally designated as ''molten pockets'', which have undergone melting and solidification. The object of the present study was to investigate molten pockets, which have a decisive effect on bond quality. The experimental samples for the study were chosen in consideration of the mutual behaviour of the plates constituting the couples, according to their equilibrium phase diagrams. To facilitate the investigation, large plates were bonded under conditions that enabled to to obtain wavy bond zones that included relatively large molten pockets. To clarify the complex nature of molten pockets and their surroundings, a wide variety of methods were employed. It was found that the shape and composition of molten pockets largely depend upon the mechanism of formation of both the bond wave and the molten pockets. It was also found that the composition of molten pockets is not homogeneous, which is manifest in the modification of the composition of the pockets, the solidification morphology, the phases, which have been identified by X-ray diffraction, and the bond strenght and hardness. Moreover, the different solidification morphologies revealed by metallography were found to depend upon the types of plates bonded, the bonding conditions and the location of pockets in the wavy interface. For molten pockets, cooling rates of 10 4 to 10 5 (degC/sec) have been deduced from interdendritic spacing, and found to be in good agreement with calculations after a mathematical model. It seems that the fast cooling rates and the steep temperature gradients are at the origin of the particular solidification phenomena observed in molten pockets

  19. Possibility of whole-surface analysis of a silicon wafer with ordinary straight TXRF

    International Nuclear Information System (INIS)

    Mori, Y.; Uemura, K.; Iizuka, Y.

    2000-01-01

    For the analysis of average metal concentration on a semiconductor surface, we customarily use the wet techniques (AAS, typically), that require skilled operators or expensive automated machines for sample pretreatment. The straight TXRF require no pretreatment, on the other hand. However, its detection area is too small (1-2 cm 2 ) to conduct a whole-surface analysis. In fact, it takes more than one day per one wafer (500 s/point x 100-300 points) for a complete mapping. Therefore it has been believed that the whole-surface analysis with straight TXRF is impracticable. It should be noted that the absolute lower limit of detection (LLD) of the straight TXRF is superior to AAS. As an example, the absolute LLD of TXRF for Fe is 0.2 pg (500 s integration), while that of AAS is l0 pg. The required integration time for TXRF to obtain the same LLD of AAS is calculated to be only 0.2 s. This means, in principle, that the whole-surface contamination can be measured in some ten seconds by accumulating 0.2 s mapping. But actually, the adjustment of glancing angle requires several ten seconds per one point, so the above mapping still takes several hours. That is why such a measurement has not been applied to daily analysis so far. However, the influence of glancing angle errors is expected to be reduced through the multi-point measurement. Figure 1 shows an accumulated spectrum of 20 s x 25 points mapping for an IAP wafer doped with Ni. In this measurement, glancing angles were not precisely controlled (the error of glancing angle is ±15 %). A spectrum of 500 s x 1 point measurement for the same wafer is shown in Figure 2. Figures 1 and 2 are almost identical. This suggests that the reduction of glancing angle errors actually works well through multi-points measurement. This method is expected to give better results by increasing the number of measuring points. The overall variation for the final measurement value obtained by multi-point measurement can be assessed by the

  20. Synchrotron Radiation Total Reflection X-ray Fluorescence Spectroscopy for Microcontamination Analysis on Silicon Wafer Surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Takaura, Norikatsu

    1997-10-01

    As dimensions in state-of-the-art CMOS devices shrink to less than 0.1 pm, even low levels of impurities on wafer surfaces can cause device degradation. Conventionally, metal contamination on wafer surfaces is measured using Total Reflection X-Ray Fluorescence Spectroscopy (TXRF). However, commercially available TXRF systems do not have the necessary sensitivity for measuring the lower levels of contamination required to develop new CMOS technologies. In an attempt to improve the sensitivity of TXRF, this research investigates Synchrotron Radiation TXRF (SR TXRF). The advantages of SR TXRF over conventional TXRF are higher incident photon flux, energy tunability, and linear polarization. We made use of these advantages to develop an optimized SR TXRF system at the Stanford Synchrotron Radiation Laboratory (SSRL). The results of measurements show that the Minimum Detection Limits (MDLs) of SR TXRF for 3-d transition metals are typically at a level-of 3x10{sup 8} atoms/cm{sup 2}, which is better than conventional TXRF by about a factor of 20. However, to use our SR TXRF system for practical applications, it was necessary to modify a commercially available Si (Li) detector which generates parasitic fluorescence signals. With the modified detector, we could achieve true MDLs of 3x10{sup 8} atoms/cm{sup 2} for 3-d transition metals. In addition, the analysis of Al on Si wafers is described. Al analysis is difficult because strong Si signals overlap the Al signals. In this work, the Si signals are greatly reduced by tuning the incident beam energy below the Si K edge. The results of our measurements show that the sensitivity for Al is limited by x-ray Raman scattering. Furthermore, we show the results of theoretical modeling of SR TXRF backgrounds consisting of the bremsstrahlung generated by photoelectrons, Compton scattering, and Raman scattering. To model these backgrounds, we extended conventional theoretical models by taking into account several aspects particular