WorldWideScience

Sample records for wafer bonded cmuts

  1. Evaluation of wafer bonded CMUTs with rectangular membranes featuring high fill factor.

    Science.gov (United States)

    Wong, Serena H; Kupnik, Mario; Zhuang, Xuefeng; Lin, Der-Song; Butts-Pauly, Kim; Khuri-Yakub, Butrus T

    2008-09-01

    Increasing fill factor is one design approach used to increase average output displacement, output pressure, and sensitivity of capacitive micromachined ultrasonic transducers (CMUTs). For rectangular cells, the cell-to-cell spacing and the aspect ratio determine the fill factor. In this paper, we explore the effects of these parameters on performance, in particular the nonuniformity of collapse voltage between neighboring cells and presence of higher order modes in air or immersed operation. We used a white light interferometer to measure nonuniformity in deflection between neighboring cells. We found that reducing the cell-to-cell spacing could cause bending of the center support post, which amplifies nonuniformities in collapse voltage to 18.4% between neighboring cells. Using a 2-D finite element model (FEM), we found that for our designs, increasing the support post width to 1.67 times the membrane thickness alleviated the post bending problem. Using impedance and interferometer measurements to observe the effects of aspect ratio on higher order modes, we found that the (1,3) modal frequency approached the (1,1) modal frequency as the aspect ratio of the rectangles increased. In air operation, under continuous wave (CW) excitation at the center frequency, the rectangular cells behaved in the (1,1) mode. In immersion, because of dispersive guided modes, these cells operated in a higher order mode when excited with a CW signal at the center frequency. This contributed to a loss of output pressure; for this reason our rectangular design was unsuitable for CW operation in immersion.

  2. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  3. Fabrication of capacitive micromachined ultrasonic transducers based on adhesive wafer bonding technique

    Science.gov (United States)

    Li, Zhenhao; Wong, Lawrence L. P.; Chen, Albert I. H.; Na, Shuai; Sun, Jame; Yeow, John T. W.

    2016-11-01

    This paper reports the fabrication process of wafer bonded capacitive micromachined ultrasonic transducers (CMUTs) using photosensitive benzocyclobutene as a polymer adhesive. Compared with direct bonding and anodic bonding, polymer adhesive bonding provides good tolerance to wafer surface defects and contamination. In addition, the low process temperature of 250 °C is compatible with standard CMOS processes. Single-element CMUTs consisting of cells with a diameter of 46 µm and a cavity depth of 323 nm were fabricated. In-air and immersion acoustic characterizations were performed on the fabricated CMUTs, demonstrating their capability for transmitting and receiving ultrasound signals. An in-air resonance frequency of 5.47 MHz was measured by a vibrometer under a bias voltage of 300 V.

  4. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  5. Monolithic CMUT-on-CMOS integration for intravascular ultrasound applications.

    Science.gov (United States)

    Zahorian, Jaime; Hochman, Michael; Xu, Toby; Satir, Sarp; Gurun, Gokce; Karaman, Mustafa; Degertekin, F Levent

    2011-12-01

    One of the most important promises of capacitive micromachined ultrasonic transducer (CMUT) technology is integration with electronics. This approach is required to minimize the parasitic capacitances in the receive mode, especially in catheter-based volumetric imaging arrays, for which the elements must be small. Furthermore, optimization of the available silicon area and minimized number of connections occurs when the CMUTs are fabricated directly above the associated electronics. Here, we describe successful fabrication and performance evaluation of CMUT arrays for intravascular imaging on custom-designed CMOS receiver electronics from a commercial IC foundry. The CMUT-on-CMOS process starts with surface isolation and mechanical planarization of the CMOS electronics to reduce topography. The rest of the CMUT fabrication is achieved by modifying a low-temperature micromachining process through the addition of a single mask and developing a dry etching step to produce sloped sidewalls for simple and reliable CMUT-to-CMOS interconnection. This CMUT-to-CMOS interconnect method reduced the parasitic capacitance by a factor of 200 when compared with a standard wire-bonding method. Characterization experiments indicate that the CMUT-on-CMOS elements are uniform in frequency response and are similar to CMUTs simultaneously fabricated on standard silicon wafers without electronics integration. Ex- periments on a 1.6-mm-diameter dual-ring CMUT array with a center frequency of 15 MHz show that both the CMUTs and the integrated CMOS electronics are fully functional. The SNR measurements indicate that the performance is adequate for imaging chronic total occlusions located 1 cm from the CMUT array.

  6. Fabrication and Characterization of Capacitive Micromachined Ultrasonic Transducers with Low-Temperature Wafer Direct Bonding

    Directory of Open Access Journals (Sweden)

    Xiaoqing Wang

    2016-12-01

    Full Text Available This paper presents a fabrication method of capacitive micromachined ultrasonic transducers (CMUTs by wafer direct bonding, which utilizes both the wet chemical and O2plasma activation processes to decrease the bonding temperature to 400 °C. Two key surface properties, the contact angle and surface roughness, are studied in relation to the activation processes, respectively. By optimizing the surface activation parameters, a surface roughness of 0.274 nm and a contact angle of 0° are achieved. The infrared images and static deflection of devices are assessed to prove the good bonding effect. CMUTs having silicon membranes with a radius of 60 μm and a thickness of 2 μm are fabricated. Device properties have been characterized by electrical and acoustic measurements to verify their functionality and thus to validate this low-temperature process. A resonant frequency of 2.06 MHz is obtained by the frequency response measurements. The electrical insertion loss and acoustic signal have been evaluated. This study demonstrates that the CMUT devices can be fabricated by low-temperature wafer direct bonding, which makes it possible to integrate them directly on top of integrated circuit (IC substrates.

  7. Anodic bonding using SOI wafer for fabrication of capacitive micromachined ultrasonic transducers

    Science.gov (United States)

    Bellaredj, M.; Bourbon, G.; Walter, V.; Le Moal, P.; Berthillier, M.

    2014-02-01

    In medical ultrasound imaging, mostly piezoelectric crystals are used as ultrasonic transducers. Capacitive micromachined ultrasonic transducers (CMUTs) introduced around 1994 have been shown to be a good alternative to conventional piezoelectric transducers in various aspects, such as sensitivity, transduction efficiency or bandwidth. This paper focuses on a fabrication process for CMUTs using anodic bonding of a silicon on insulator wafer on a glass wafer. The processing steps are described leading to a good control of the mechanical response of the membrane. This technology makes possible the fabrication of large membranes and can extend the frequency range of CMUTs to lower frequencies of operation. Silicon membranes having radii of 50, 70, 100 and 150 µm and a 1.5 µm thickness are fabricated and electromechanically characterized using an auto-balanced bridge impedance analyzer. Resonant frequencies from 0.6 to 2.3 MHz and an electromechanical coupling coefficient around 55% are reported. The effects of residual stress in the membranes and uncontrolled clamping conditions are clearly responsible for the discrepancies between experimental and theoretical values of the first resonance frequency. The residual stress in the membranes is determined to be between 90 and 110 MPa. The actual boundary conditions are between the clamped condition and the simply supported condition and can be modeled with a torsional stiffness of 2.10-7 Nm rad-1 in the numerical model.

  8. Wafer bonding using Cu-Sn intermetallic bonding layers

    NARCIS (Netherlands)

    Flötgen, C.; Pawlak, M.; Pabo, E.; Wiel, H.J. van de; Hayes, G.R.; Dragoi, V.

    2014-01-01

    Wafer-level Cu-Sn intermetallic bonding is an interesting process for advanced applications in the area of MEMS and 3D interconnects. The existence of two intermetallic phases for Cu-Sn system makes the wafer bonding process challenging. The impact of process parameters on final bonding layer

  9. Biocompatible "click" wafer bonding for microfluidic devices.

    Science.gov (United States)

    Saharil, Farizah; Carlborg, Carl Fredrik; Haraldsson, Tommy; van der Wijngaart, Wouter

    2012-09-07

    We introduce a novel dry wafer bonding concept designed for permanent attachment of micromolded polymer structures to surface functionalized silicon substrates. The method, designed for simultaneous fabrication of many lab-on-chip devices, utilizes a chemically reactive polymer microfluidic structure, which rapidly bonds to a functionalized substrate via"click" chemistry reactions. The microfluidic structure consists of an off-stoichiometry thiol-ene (OSTE) polymer with a very high density of surface bound thiol groups and the substrate is a silicon wafer that has been functionalized with common bio-linker molecules. We demonstrate here void free, and low temperature (silane functionalized silicon wafer.

  10. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  11. Biocompatible "click" wafer bonding for microfluidic devices

    OpenAIRE

    Saharil, Farizah; Carlborg, Carl Fredrik; Haraldsson, Tommy; van der Wijngaart, Wouter

    2012-01-01

    We introduce a novel dry wafer bonding concept designed for permanent attachment of micromolded polymer structures to surface functionalized silicon substrates. The method, designed for simultaneous fabrication of many lab-on-chip devices, utilizes a chemically reactive polymer microfluidic structure, which rapidly bonds to a functionalized substrate via "click" chemistry reactions. The microfluidic structure consists of an off-stoichiometry thiol-ene (OSTE) polymer with a very high density o...

  12. High-power CMUTs: design and experimental verification.

    Science.gov (United States)

    Yamaner, F Yalçin; Olçum, Selim; Oğuz, H Kağan; Bozkurt, Ayhan; Köymen, Hayrettin; Atalar, Abdullah

    2012-06-01

    Capacitive micromachined ultrasonic transducers (CMUTs) have great potential to compete with piezoelectric transducers in high-power applications. As the output pressures increase, nonlinearity of CMUT must be reconsidered and optimization is required to reduce harmonic distortions. In this paper, we describe a design approach in which uncollapsed CMUT array elements are sized so as to operate at the maximum radiation impedance and have gap heights such that the generated electrostatic force can sustain a plate displacement with full swing at the given drive amplitude. The proposed design enables high output pressures and low harmonic distortions at the output. An equivalent circuit model of the array is used that accurately simulates the uncollapsed mode of operation. The model facilities the design of CMUT parameters for high-pressure output, without the intensive need for computationally involved FEM tools. The optimized design requires a relatively thick plate compared with a conventional CMUT plate. Thus, we used a silicon wafer as the CMUT plate. The fabrication process involves an anodic bonding process for bonding the silicon plate with the glass substrate. To eliminate the bias voltage, which may cause charging problems, the CMUT array is driven with large continuous wave signals at half of the resonant frequency. The fabricated arrays are tested in an oil tank by applying a 125-V peak 5-cycle burst sinusoidal signal at 1.44 MHz. The applied voltage is increased until the plate is about to touch the bottom electrode to get the maximum peak displacement. The observed pressure is about 1.8 MPa with -28 dBc second harmonic at the surface of the array.

  13. The influence of wafer dimensions on the contact wave velocity in silicon wafer bonding

    DEFF Research Database (Denmark)

    Bengtsson, S.; Ljungberg, Karin; Vedde, Jan

    1996-01-01

    The contact wave velocity in silicon wafer bonding is experimentally found to decrease with wafer thickness and to be only weakly dependent on wafer diameter. Wafers of different thicknesses ranging from 270 to 5000 mu m, were dipped in HF:H2O before bonding to give the surfaces hydrophobic...... stored in the material is increased, and the contact wave velocity is decreased. (C) 1996 American Institute of Physics....

  14. Void-Free Direct Bonding of CMUT Arrays with Single Crystalline Plates and Pull- In Insulation

    DEFF Research Database (Denmark)

    Christiansen, Thomas Lehrmann; Hansen, Ole; Dahl Johnsen, Mathias

    2013-01-01

    anisotropically plasma etched cavities after the second oxidation. It is demonstrated that the protrusions will prevent good wafer bonding without subsequent polishing or etching steps. A new fabrication process is therefore proposed, allowing protrusionfree bonding surfaces with no alteration of the final......, and a proposed analytical model, which is in good agreement with the simulated results. The results demonstrate protrusion heights in the order of 10 nm to 40 nm, with higher oxidation temperatures giving the highest protrusions. Isotropically wet etched cavities exhibit significantly smaller protrusions than...

  15. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  16. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Energy Technology Data Exchange (ETDEWEB)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  17. Si-to-Si wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Reus, Roger De; Lindahl, M.

    1997-01-01

    Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

  18. Fabricating Capacitive Micromachined Ultrasonic Transducers with Wafer Bonding Technique

    Directory of Open Access Journals (Sweden)

    Anil ARORA

    2008-06-01

    Full Text Available We report the fabrication of capacitive micromachined ultrasonic transducer by wafer bonding technique. Membrane is transferred from SOI wafer to the prime wafer having silicon dioxide cavity. The thickness of cavity height depends on silicon dioxide grown on prime wafer by dry/wet oxidation. Thinning of device wafer of SOI by oxidation, controls membrane thickness. Two wafers are bonded in vacuum under optimized controlled parameters. Using this method, we can get single crystal silicon as membrane, whose mechanical and electrical parameters are well known. Silicon membrane is free from stress and density variation. Focused Ion Beam etching and laser Doppler Vibrometer were used to do structural and electrical characterization respectively. The measured resonance frequency of fabricated device i.e. 2.24 MHz is much closer to the designed value i.e. 2.35 MHz.

  19. Row-Column Addressed 2-D CMUT Arrays with Integrated Apodization

    DEFF Research Database (Denmark)

    Christiansen, Thomas Lehrmann; Rasmussen, Morten Fischer; Jensen, Jørgen Arendt

    2014-01-01

    Experimental results from row-column addressed capacitive micromachined ultrasonic transducers (CMUTs) with integrated apodization are presented. The apodization is applied by varying the density of CMUT cells in the array with the objective of damping the edge waves originating from the element...... ends. Two row-column addressed 32+32 CMUT arrays are produced using a wafer-bonding technique, one with and one without integrated apodization. Hydrophone measurements of the emitted pressure field from the array with integrated apodization show a reduction in edge wave energy of 8.4 dB (85 %) compared...... to the array without integrated apodization. Field II simulations yield a corresponding reduction of 13.0 dB (95 %). The simulations are able to replicate the measured pressure field, proving the predictability of the technique....

  20. Wafer level bonding using localized radio-frequency induction heating

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    A wafer level bonding technique by localized induction heating has been developed and demonstrated in this paper.A suitable fabrication process scheme has also been established for the localized induction heating and bonding.It takes only about 20 seconds to complete the bonding process.The temperatures of solder loops and the central area of solder loops are above 300°C and below 70°C,respectively.Due to the solder reflow,robust and hermetic glass wafer bonding is accomplished,and the average tensile strength is 6.42 MPa.Under-heated or over-heated bonding has been found to result in cracks at bonding interfaces and sputtering layer,which degrades the bonding qualities.

  1. Si-gold-glass hybrid wafer bond for 3D-MEMS and wafer level packaging

    Science.gov (United States)

    Reddy, Jayaprakash; Pratap, Rudra

    2017-01-01

    We report a relatively low temperature (MEMS device integration and wafer level packaging. We demonstrate the process by realizing a simple MEMS cantilever beam and a complex MEMS gyroscope structure. These structures are characterized for ohmic contact and electromechanical response to verify the electrical interconnect and the mechanical strength of the structure at the bond interface.

  2. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Directory of Open Access Journals (Sweden)

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  3. Acoustic backing in 3-D integration of CMUT with front-end electronics.

    Science.gov (United States)

    Berg, Sigrid; Rønnekleiv, Arne

    2012-07-01

    Capacitive micromachined ultrasonic transducers (CMUTs) have shown promising qualities for medical imaging. However, there are still some problems to be investigated, and some challenges to overcome. Acoustic backing is necessary to prevent SAWs excited in the surface of the silicon substrate from affecting the transmit pattern from the array. In addition, echoes resulting from bulk waves in the substrate must be removed. There is growing interest in integrating electronic circuits to do some of the beamforming directly below the transducer array. This may be easier to achieve for CMUTs than for traditional piezoelectric transducers. We will present simulations showing that the thickness of the silicon substrate and thicknesses and acoustic properties of the bonding material must be considered, especially when designing highfrequency transducers. Through simulations, we compare the acoustic properties of 3-D stacks bonded with three different bonding techniques; solid-liquid interdiffusion (SLID) bonding, direct fusion bonding, and anisotropic conductive adhesives (ACA). We look at a CMUT array with a center frequency of 30 MHz and three silicon wafers underneath, having a total silicon thickness of 100 μm. We find that fusion bonding is most beneficial if we want to prevent surface waves from damaging the array response, but SLID and ACA are also promising if bonding layer thicknesses can be reduced.

  4. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

  5. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, Vincent L.; Berenschot, J.W.; Elwenspoek, Miko; Fluitman, Jan H.J

    1995-01-01

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a w

  6. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  7. Biocompatible silicon wafer bonding for biomedical microdevices

    Science.gov (United States)

    Hansford, Derek; Desai, Tejal A.; Tu, Jay K.; Ferrari, Mauro

    1998-03-01

    In this paper,several candidate bonding materials are reviewed for use in biomedical microdevices. These include poly propylmethacrylate (PPMA), poly methylmethacrylate (PMMA), a copolymer of poly methacrylate and two types of silicone gels. They were evaluated based on their cytotoxicity and bond strength, as well as several other qualitative assessments. The cytotoxicity was determined through a cell growth assay protocol in which cells were grown on the various substrate and their growth was compared to cells grown on control substrate. The adhesive strength was assessed by using a pressurized plate test in which the adhesive interface was pressurized to failure. All of the substrate were found to be non-cytotoxic in an inert manner except for the industrial silicone adhesive gel. The adhesive strengths of the various materials are compared to each other and to previously published adhesive strengths. All of the materials were found to have a sufficient bonding strength for biomedical applications, but several other factors were determined that limit the use of each material.

  8. Materials integration for high-performance photovoltaics by wafer bonding

    Science.gov (United States)

    Zahler, James Michael

    The fundamental efficiency limit for state of the art triple-junction photovoltaic devices is being approached. By allowing integration of non-lattice-matched materials in monolithic structures, wafer bonding enables novel photovoltaic devices that have a greater number of subcells to improve the discretization of the solar spectrum, thus extending the efficiency limit of the devices. Additionally, wafer bonding enables the integration of non-lattice-matched materials with foreign substrates to confer desirable properties associated with the handle substrate on the solar cell structure, such as reduced mass, increased thermal conductivity, and improved mechanical toughness. This thesis outlines process development and characterization of wafer bonding integration technologies essential for transferring conventional triple-junction solar cell designs to potentially lower cost Ge/Si epitaxial templates. These epitaxial templates consist of a thin film of single-crystal Ge on a Si handle substrate. Additionally, a novel four-junction solar cell design consisting of non-lattice matched subcells of GaInP, GaAs, InGaAsP, and InGaAs based on InP/Si wafer-bonded epitaxial templates is proposed and InP/Si template fabrication and characterization is pursued. In this thesis the detailed-balance theory of the thermodynamic limiting performance of solar cell efficiency is applied to several device designs enabled by wafer bonding and layer exfoliation. The application of the detailed-balance theory to the novel four-junction cell described above shows that operating under 100 suns at 300 K a maximum efficiency of 54.9% is achievable with subcell bandgaps of 1.90, 1.42, 1.02, and 0.60 eV, a material combination achievable by integrating two wide-bandgap subcells lattice matched to GaAs and two narrow-bandgap subcells lattice matched to InP. Wafer bonding and layer transfer processes with sufficient quality to enable subsequent material characterization are demonstrated for both

  9. Sulfur passivation techniques for III-V wafer bonding

    Science.gov (United States)

    Jackson, Michael James

    The use of direct wafer bonding in a multijunction III-V solar cell structure requires the formation of a low resistance bonded interface with minimal thermal treatment. A wafer bonded interface behaves as two independent surfaces in close proximity, hence a major source of resistance is Fermi level pinning common in III-V surfaces. This study demonstrates the use of sulfur passivation in III-V wafer bonding to reduce the energy barrier at the interface. Two different sulfur passivation processes are addressed. A dry sulfur passivation method that utilizes elemental sulfur vapor activated by ultraviolet light in vacuum is compared with aqueous sulfide and native oxide etch treatments. Through the addition of a sulfur desorption step in vacuum, the UV-S treatment achieves bondable surfaces free of particles contamination or surface roughening. X-ray photoelectron spectroscopy measurements of the sulfur treated GaAs surfaces find lower levels of oxide and the appearance of sulfide species. After 4 hrs of air exposure, the UV-S treated GaAs actually showed an increase in the amount of sulfide bonded to the semiconductor, resulting in less oxidation compared to the aqueous sulfide treatment. Large area bonding is achieved for sulfur treated GaAs / GaAs and InP / InP with bulk fracture strength achieved after annealing at 400 °C and 300 °C respectively, without large compressive forces. The electrical conductivity across a sulfur treated 400 °C bonded n-GaAs/n-GaAs interface significantly increased with a short anneal (1-2 minutes) at elevated temperatures (50--600 °C). Interfaces treated with the NH4OH oxide etch, on the other hand, exhibited only mild improvement in accordance with previously published studies in this area. TEM and STEM images revealed similar interfacial microstructure changes with annealing for both sulfur treated and NH4OH interfaces, whereby some areas have direct semiconductor-semiconductor contact without any interfacial layer. Fitting the

  10. Chemical strategies for die/wafer submicron alignment and bonding.

    Energy Technology Data Exchange (ETDEWEB)

    Martin, James Ellis; Baca, Alicia I.; Chu, Dahwey; Rohwer, Lauren Elizabeth Shea

    2010-09-01

    This late-start LDRD explores chemical strategies that will enable sub-micron alignment accuracy of dies and wafers by exploiting the interfacial energies of chemical ligands. We have micropatterned commensurate features, such as 2-d arrays of micron-sized gold lines on the die to be bonded. Each gold line is functionalized with alkanethiol ligands before the die are brought into contact. The ligand interfacial energy is minimized when the lines on the die are brought into registration, due to favorable interactions between the complementary ligand tails. After registration is achieved, standard bonding techniques are used to create precision permanent bonds. We have computed the alignment forces and torque between two surfaces patterned with arrays of lines or square pads to illustrate how best to maximize the tendency to align. We also discuss complex, aperiodic patterns such as rectilinear pad assemblies, concentric circles, and spirals that point the way towards extremely precise alignment.

  11. Fusion bonding of Si wafers investigated by x ray diffraction

    DEFF Research Database (Denmark)

    Weichel, Steen; Grey, Francois; Rasmussen, Kurt

    2000-01-01

    The interface structure of bonded Si(001) wafers with twist angle 6.5 degrees is studied as a function of annealing temperature. An ordered structure is observed in x-ray diffraction by monitoring a satellite reflection due to the periodic modulation near the interface, which results from...... the formation of a regular array of screw dislocations. This satellite reflection first appears at an annealing temperature of 800 degrees C, and increases abruptly up to temperatures of 1000 degrees C. We propose that this transition occurs when there is sufficient mobility for the reorganization of atomic...

  12. 2-D Row-Column CMUT Arrays with an Open-Grid Support Structure

    DEFF Research Database (Denmark)

    Christiansen, Thomas Lehrmann; Dahl-Petersen, Christian; Jensen, Jørgen Arendt

    2013-01-01

    support structure on top of the CMUT plates, omitting the need for through wafer vias. A 5 mask process is used to produce 2-D row-column addressed CMUT arrays with 74 nm vacuum gaps, single crystalline silicon plates with optional lithographically defined mass loads, 120 V pull-in voltage, and high...

  13. Characterization of wafer-level bonded hermetic packages using optical leak detection

    Science.gov (United States)

    Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

    2009-07-01

    For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

  14. Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

    Energy Technology Data Exchange (ETDEWEB)

    Trushin, Maxim

    2011-07-15

    The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

  15. Cu-Sn transient liquid phase wafer bonding for MEMS applications

    NARCIS (Netherlands)

    Flötgen, C.; Pawlak, M.; Pabo, E.; Wiel, H.J. van de; Hayes, G.R.; Dragoi, V.

    2013-01-01

    The impact of process parameters on final bonding layer quality was investigated for Transient Liquid Phase (TLP) wafer-level bonding based on the Cu-Sn system. Subjects of this investigation were bonding temperature profile, bonding time and contact pressure as well as the choice of metal

  16. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  17. Wafer bonding technology for new generation vacuum MEMS: challenges and promises

    Science.gov (United States)

    Dragoi, V.; Pabo, E.

    2015-05-01

    Various MEMS devices are incorporated into consumer electronic devices. A particular category of MEMS require vacuum packaging by wafer bonding with the need to encapsulate vacuum levels of 10-2 mbar or higher with long time stability. The vacuum requirement is limiting the choice of the wafer bonding process and raises significant challenges to the existing investigation methods (metrology) used for results qualification. From the broad range of wafer bonding processes only few are compatible with vacuum applications: fusion bonding, anodic bonding, glass frit bonding and metal-based bonding. The outgassing from the enclosed surfaces after bonding will affect the vacuum level in the cavity: in some cases, a getter material is used inside the device cavity to compensate for this outgassing. Additionally the selected bonding process must be compatible with the devices on the wafers being bonded. This work reviews the principles of vacuum encapsulation using wafer bonding. Examples showing the suitability of each process for specific applications types will be presented. A significant challenge in vacuum MEMS fabrication is the lack of analytical methods needed for process characterization or reliability testing. A short overview of the most used methods and their limitations will be presented. Specific needs to be addressed will be introduced with examples.

  18. Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon

    OpenAIRE

    Bushra, Sobia

    2011-01-01

    The objective of this research work was to investigate the low temperature gold silicon eutectic bonding of SMA with silicon wafers. The research work was carried out to optimize a bond process with better yield and higher bond strength. The gold layer thickness, processing temperature, diffusion barrier, adhesive layer, and the removal of silicon oxide are the important parameters in determining a reliable and uniform bond. Based on the previous work on Au-Si eutectic bonding, 7 different Si...

  19. Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

    Science.gov (United States)

    Khan, M. F.; Ghavanini, F. A.; Haasl, S.; Löfgren, L.; Persson, K.; Rusu, C.; Schjølberg-Henriksen, K.; Enoksson, P.

    2010-06-01

    This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

  20. Experimental Analysis of Bisbenzocyclobutene Bonded Capacitive Micromachined Ultrasonic Transducers

    OpenAIRE

    2016-01-01

    Experimental measurement results of a 1.75 mm × 1.75 mm footprint area Capacitive Micromachined Ultrasonic Transducer (CMUT) planar array fabricated using a bisbenzocyclobutene (BCB)-based adhesive wafer bonding technique has been presented. The array consists of 40 × 40 square diaphragm CMUT cells with a cavity thickness of 900 nm and supported by 10 µm wide dielectric spacers patterned on a thin layer of BCB. A 150 µm wide one µm thick gold strip has been used as the contact pad for gold wi...

  1. Analyses of crack growth along interface of patterned wafer-level Cu-Cu bonds

    DEFF Research Database (Denmark)

    Tvergaard, Viggo; Hutchinson, John W.

    2009-01-01

    A preliminary theoretical study is carried out of the role of micron-scale patterning on the interface toughness of bonded Cu-to-Cu nanometer-scale films. The work is motivated by the experimental studies of [Tadepalli, R., Turner. K.T., Thompson, C.V., 2008b. Effects of patterning on the interface...... toughness of wafer-level Cu-Cu bonds. Acta Materialia 56, 438-447; Tadepalli, R., Turner, K.T., Thompson, C.V., 2008c. Mixed-mode interface toughness of wafer-level Cu-Cu bonds using asymmetric chevron test. J. Mech. Phys. Solids 56, 707-718.] wherein 400 nm Cu films were deposited in a variety of patterns...... on Si wafer substrates. Specimens were then produced by bringing the Cu surfaces into contact creating thermo-compression bonds. Interface toughness of these specimens was experimentally measured. The present study focuses on interface patterns comprised of bonded strips, called lines, alternating...

  2. Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

    Science.gov (United States)

    Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

    2016-04-01

    In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

  3. Eutectic and solid-state wafer bonding of silicon with gold

    Energy Technology Data Exchange (ETDEWEB)

    Abouie, Maryam; Liu, Qi [Department of Chemical and Materials Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4 (Canada); Ivey, Douglas G., E-mail: doug.ivey@ualberta.ca [Department of Chemical and Materials Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4 (Canada)

    2012-12-01

    Highlights: Black-Right-Pointing-Pointer Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. Black-Right-Pointing-Pointer Exchange of a-Si and Au layer was observed in both types of bonded samples. Black-Right-Pointing-Pointer Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. Black-Right-Pointing-Pointer Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 Degree-Sign C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 Degree-Sign C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

  4. Experimental Analysis of Bisbenzocyclobutene Bonded Capacitive Micromachined Ultrasonic Transducers

    Science.gov (United States)

    Manwar, Rayyan; Chowdhury, Sazzadur

    2016-01-01

    Experimental measurement results of a 1.75 mm × 1.75 mm footprint area Capacitive Micromachined Ultrasonic Transducer (CMUT) planar array fabricated using a bisbenzocyclobutene (BCB)-based adhesive wafer bonding technique has been presented. The array consists of 40 × 40 square diaphragm CMUT cells with a cavity thickness of 900 nm and supported by 10 µm wide dielectric spacers patterned on a thin layer of BCB. A 150 µm wide one µm thick gold strip has been used as the contact pad for gold wire bonding. The measured resonant frequency of 19.3 MHz using a Polytec™ laser Doppler vibrometer (Polytec™ MSA-500) is in excellent agreement with the 3-D FEA simulation result using IntelliSuite™. An Agilent ENA5061B vector network analyzer (VNA) has been used for impedance measurement and the resonance and anti-resonance values from the imaginary impedance curve were used to determine the electromechanical coupling co-efficient. The measured coupling coefficient of 0.294 at 20 V DC bias exhibits 40% higher transduction efficiency as compared to a measured value published elsewhere for a silicon nitride based CMUT. A white light interferometry method was used to measure the diaphragm deflection profiles at different DC bias. The diaphragm center velocity was measured for different sub-resonant frequencies using a Polytec™ laser Doppler vibrometer that confirms vibration of the diaphragm at different excitation frequencies and bias voltages. Transmit and receive operations of CMUT cells were characterized using a pitch-catch method and a −6 dB fractional bandwidth of 23% was extracted from the received signal in frequency domain. From the measurement, it appears that BCB-based CMUTs offer superior transduction efficiency as compared to silicon nitride or silicon dioxide insulator-based CMUTs, and provide a very uniform deflection profile thus making them a suitable candidate to fabricate highly energy efficient CMUTs. PMID:27347955

  5. 3D micro-optical lens scanner made by multi-wafer bonding technology

    Science.gov (United States)

    Bargiel, S.; Gorecki, C.; Barański, M.; Passilly, N.; Wiemer, M.; Jia, C.; Frömel, J.

    2013-03-01

    We present the preliminary design, construction and technology of a microoptical, millimeter-size 3-D microlens scanner, which is a key-component for a number of optical on-chip microscopes with emphasis on the architecture of confocal microscope. The construction of the device relies on the vertical integration of micromachined building blocks: top glass lid, silicon electrostatic comb-drive X-Y and Z microactuators with integrated scanning microlenses, ceramic LTCC spacer, and bottom lid with focusing microlens. All components are connected on the wafer level only by sequential anodic bonding. The technology of through wafer vias is applied to create electrical connections through a stack of wafers. More generally, the presented bonding/connection technologies are also of a great importance for the development of various silicon-based devices based on vertical integration scheme. This approach offers a space-effective integration of complex MOEMS devices and an effective integration of various heterogeneous technologies.

  6. Semiconductor thin film transfer by wafer bonding and advanced ion implantation layer splitting technologies

    Science.gov (United States)

    Lee, Tien-Hsi

    Wafer bonding is an attractive technology for modern semiconductor and microelectronic industry due to its variability in allowing combination of materials. Initially, the bonding of wafers of the same material, such as silicon-silicon wafer bonding has been major interest. In the meantime, research interest has shifted to the bonding of dissimilar materials such as silicon to quartz or to sapphire. Thermal stress coming from the different expansion coefficients usually is a barrier to the success of dissimilar material bonding. Thermal stress may cause debonding, sliding, cracking, thermal misfit dislocations, or film wrinkle to impair the quality of the transferred layer. This dissertation presents several effective approaches to solve the thermal stress problem. These approaches concern bonding processes (low vacuum bonding and storage), thinning (advanced ion implantation layer splitting), and annealing processes (accumulative effect of blister generation) and are combined to design the best heat-treatment cycle. For this propose the concept of hot bonding is used in order to effectively minimize the thermal mismatch of dissimilar material bonding during the bonding and thinning procedures. During the initial bonding and bond strengthening phase, the difference in the temperature between bonding and annealing processes should be decreased as much as possible to avoid excessive thermal stresses. This concept can be realized either by increasing the bonding temperature or by decreasing the annealing temperature. A thinning technique has to employed that can thin the device wafer before debonding occurs due to the thermal stress generated either from the cooling-down process in the first case or by the annealing process itself in the late case. The ion implantation layer splitting method, also known as the Smart-cutsp°ler process, developed by Bruel at LEIT in France is a practical thinning technique which satisfies the above requirement. In the study, an

  7. Oxide layer dissolution in Si/SiO{sub x}/Si wafer bonded structures

    Energy Technology Data Exchange (ETDEWEB)

    Pippel, E.; Werner, P.; Goesele, U. [Max-Planck-Institut fuer Mikrostrukturphysik, Halle (Germany); Vdovin, V. [Institute for Chemical Problems of Microelectronics, Moscow (Russian Federation); Institute of Rare Metals Giredmet, Moscow (Russian Federation); Zakharov, N.

    2009-10-15

    The evolution of the interfaces of hydrophilic-bonded Si wafers and the corresponding low-angle twist boundary have been analysed in relation to thermal annealing and their relative crystallographic orientation. Two orientation relationships were investigated: Si<001>/Si<001> and Si<001>/Si<110>, where the interfaces are separated by thin native SiO2 layers. The interfaces were analysed by TEM and STEM/EELS. It is found that the decomposition rate of the intermediate oxide layer and the formation of a Si-Si bonded interface depend very much on the lattice mismatch and on the twist angle. The velocity of the dissolution of the thin oxide layers and the formation of Si-Si bonds at the bonding interface depend on the orientation relations of the corresponding wafers. The processes of interface fusion and the dissolution of oxide layer are discussed. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  8. Low temperature fusion wafer bonding quality investigation for failure mode analysis

    NARCIS (Netherlands)

    Dragoi, V.; Czurratis, P.; Brand, S.; Beyersdorfer, J.; Patzig, C.; Krugers, J.P.; Schrank, F.; Siegert, J.; Petzold, M.

    2012-01-01

    In this paper, a brief summary of potential defect formation and failure characteristics for low temperature plasma-assisted Si wafer bonding in correlation to different influencing factors is given. In terms of a failure catalogue classification, these defects are related to incoming material quali

  9. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Berenschot, J.W.; Elwenspoek, M.; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique co

  10. Low temperature fusion wafer bonding quality investigation for failure mode analysis

    NARCIS (Netherlands)

    Dragoi, V.; Czurratis, P.; Brand, S.; Beyersdorfer, J.; Patzig, C.; Krugers, J.P.; Schrank, F.; Siegert, J.; Petzold, M.

    2012-01-01

    In this paper, a brief summary of potential defect formation and failure characteristics for low temperature plasma-assisted Si wafer bonding in correlation to different influencing factors is given. In terms of a failure catalogue classification, these defects are related to incoming material

  11. Low temperature fusion wafer bonding quality investigation for failure mode analysis

    NARCIS (Netherlands)

    Dragoi, V.; Czurratis, P.; Brand, S.; Beyersdorfer, J.; Patzig, C.; Krugers, J.P.; Schrank, F.; Siegert, J.; Petzold, M.

    2012-01-01

    In this paper, a brief summary of potential defect formation and failure characteristics for low temperature plasma-assisted Si wafer bonding in correlation to different influencing factors is given. In terms of a failure catalogue classification, these defects are related to incoming material quali

  12. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

  13. Anodic Bonding of Transparent Conductive Oxide Coated Silicon Wafer to Glass Substrate for Solar Cell Applications

    Science.gov (United States)

    Yuda, Yohei; Koida, Takashi; Kaneko, Tetsuya; Kondo, Michio

    2013-01-01

    We report on the anodic bonding of Si wafer coated by thin transparent conductive oxide (TCO) with a glass substrate, for the first time. We obtained sufficient bonding strength of as high as 9.5 MPa using a 30-nm-thick indium tin oxide (ITO) layer. We have also found that the ITO sample shows much stronger bonding strength does a sample that with a zinc oxide layer. The bonding mechanism is discussed in terms of the permeation of indium elements into the glass side driven by electric field. Finally we demonstrated a solar cell using this substrate.

  14. GeSn-on-insulator substrate formed by direct wafer bonding

    Science.gov (United States)

    Lei, Dian; Lee, Kwang Hong; Bao, Shuyu; Wang, Wei; Wang, Bing; Gong, Xiao; Tan, Chuan Seng; Yeo, Yee-Chia

    2016-07-01

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge1-xSnx layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO2 on Ge1-xSnx, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge1-xSnx layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge1-xSnx epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge1-xSnx film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  15. GeSn-on-insulator substrate formed by direct wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  16. Wafer bonding solution to epitaxial graphene-silicon integration

    Science.gov (United States)

    Dong, Rui; Guo, Zelei; Palmer, James; Hu, Yike; Ruan, Ming; Hankinson, John; Kunc, Jan; Bhattacharya, Swapan K.; Berger, Claire; de Heer, Walt A.

    2014-03-01

    A new strategy for the integration of graphene electronics with silicon complementary metal-oxide-semiconductor (Si-CMOS) technology is demonstrated that requires neither graphene transfer nor patterning. Inspired by silicon-on-insulator and three-dimensional device hyper-integration techniques, a thin monocrystalline silicon layer ready for CMOS processing is bonded to epitaxial graphene (EG) on SiC. The parallel Si and graphene electronic platforms are interconnected by metal vias. In this method, EG is grown prior to bonding so that the process is compatible with EG high temperature growth and preserves graphene integrity and nano-structuring.

  17. Investigation of Au/Si Eutectic Wafer Bonding for MEMS Accelerometers

    Directory of Open Access Journals (Sweden)

    Dongling Li

    2017-05-01

    Full Text Available Au/Si eutectic bonding is considered to BE a promising technology for creating 3D structures and hermetic packaging in micro-electro-mechanical system (MEMS devices. However, it suffers from the problems of a non-uniform bonding interface and complex processes for the interconnection of metal wires. This paper presents a novel Au/Si eutectic wafer bonding structure and an implementation method for MEMS accelerometer packaging. The related processing parameters influencing the Au/Si eutectic bonding quality were widely investigated. It was found that a high temperature of 400 °C with a low heating/cooling rate of 5 °C/min is crucial for successful Au/Si eutectic bonding. High contact force is beneficial for bonding uniformity, but the bonding strength and bonding yield decrease when the contact force increases from 3000 to 5000 N due to the metal squeezing out of the interface. The application of TiW as an adhesion layer on a glass substrate, compared with a commonly used Cr or Ti layer, significantly improves the bonding quality. The bonding strength is higher than 50 MPa, and the bonding yield is above 90% for the presented Au/Si eutectic bonding. Furthermore, the wafer-level vacuum packaging of the MEMS accelerometer was achieved based on Au/Si eutectic bonding and anodic bonding with one process. Testing results show a nonlinearity of 0.91% and a sensitivity of 1.06 V/g for the MEMS accelerometer. This Au/Si eutectic bonding process can be applied to the development of reliable, low-temperature, low-cost fabrication and hermetic packaging for MEMS devices.

  18. Oxides formation on hydrophilic bonding interface in plasma-assisted InP/Al2O3/SOI direct wafer bonding

    Directory of Open Access Journals (Sweden)

    Kewei Gong

    2017-01-01

    Full Text Available Successful direct wafer bonding between InP and silicon-on-insulator (SOI wafers has been demonstrated by adopting a 20-nm-thick Al2O3 as the intermediate layer. A detailed investigation on the property of the bonding interface is carried out. Water contact angle test reveals an improved hydrophilicity for both the InP and the Al2O3/SOI wafers after oxygen plasma surface activation. X-ray photoelectron spectroscopy is employed to characterize the bonding interface before and after the wafer bonding process. It is found that oxides are formed on the bonding interface during bonding, which helps ensure high quality hydrophilic bonding.

  19. Damascene patterned metal/adhesive wafer bonding for three-dimensional integration

    Science.gov (United States)

    McMahon, J. Jay

    Wafer bonding of damascene patterned metal/adhesive surfaces is explored for a new three-dimensional (3D) integration technology platform. By bonding a pair of damascene patterned metal/adhesive layers, high density micron-sized vias can be formed for interconnection of fully fabricated integrated circuit (IC) dies at the wafer-level. Such via dimensions increase the areal interconnect density by at least two orders of magnitude over current package and die-stacking approaches to 3D integration. The adhesive field-dielectric produces a high critical adhesion energy bond and has the potential to produce void-free bonded interfaces. This new technology platform has been demonstrated by fabricating and characterizing inter-wafer via-chains on 200 mm diameter Si wafers. Copper and partially cured divinylsiloxane bis-benzocyclobutene (BCB) are selected as the metal and adhesive, respectively, and unit processes for this demonstration are described. Typical alignment tolerance is ˜2 mum, and baseline bonding conditions include vacuum of 5x10-4 mbar, bonding force of 10 kN, and two step bonding temperature of 250°C for 60 min followed by 350°C for 60 min. Integration issues associated with the damascene patterning and the wafer bonding processes are discussed, particularly the resulting topography of damascene patterned Cu/BCB. Cross-sectional investigation of bonded and annealed inter-wafer interconnections provides insight into the Cu-Cu and BCB-BCB bonding interfaces. Inter-wafer specific contact resistance is measured to be on the order of 10-7 O-cm 2 for these via-chains. Several material characterization techniques have been explored to evaluate partially cured BCB as an adhesive field-dielectric. To investigate the critical adhesion energy, Gc, four-point bending is utilized to compare surfaces bonded after chemical-mechanical planarization (CMP) and various post-CMP treatments. The Gc of bonded 50% partially cured BCB is measured to be in the range of 32--44 J

  20. Regularities in the formation of dislocation networks on the boundary of bonded Si(001) wafers

    Energy Technology Data Exchange (ETDEWEB)

    Vdovin, V. I., E-mail: vivdov@gmail.com; Ubyivovk, E. V.; Vyvenko, O. F. [St.-Petersburg State University (Russian Federation)

    2013-02-15

    The dislocation networks in structures with hydrophilically bonded Si (001) wafers are investigated by transmission electron microscopy. Networks with differing geometry and type of dominant dislocations are observed. One type of networks, which is typical of bonded structures, is formed on the basis of a square network of screw dislocations and contains a system of unidirectional 60 Degree-Sign zigzag-shaped dislocations. It is established that such dislocation networks are flat in structures with an azimuthal misorientation of wafers exceeding 2 Degree-Sign , whereas they are three-dimensional at smaller misorientation angles. A unique network of another type is formed only by 60 Degree-Sign dislocations, the majority of which are extended along one direction, which does not coincide with the Left-Pointing-Angle-Bracket 110 Right-Pointing-Angle-Bracket directions in the boundary plane and has a number of specific features, the explanation of which is impossible within the framework of conventional representations.

  1. The Evolution of Wafer Bonding Moving from the back-end further to the front-end

    Institute of Scientific and Technical Information of China (English)

    Thomas Glinsner; Peter Hangweier

    2009-01-01

    @@ 1 Introduction As the nanoscale era progresses, innovative new materials and processes continue to be developed and implemented as a means of keeping the industry on the path of Moore's Law. Wafer bonding - literally, the temporary or permanent joining of two wafers or substrates using a suitable combination of process technologies, chemicals and adhesives - is one such innovation.

  2. Material size effects on crack growth along patterned wafer-level Cu–Cu bonds

    DEFF Research Database (Denmark)

    Tvergaard, Viggo; Niordson, Christian Frithiof; Hutchinson, John W.

    2013-01-01

    The role of micron-scale patterning on the interface toughness of bonded Cu-to-Cu nanometer-scale films is analyzed, motivated by experimental studies of Tadepalli, Turner and Thompson. In the experiments 400nm Cu films were deposited in various patterns on Si wafer substrates and then bonded...... together. Crack growth along the bond interface is here studied numerically using finite element analyses. The experiments have shown that plasticity in the Cu films makes a major contribution to the macroscopic interface toughness. To account for the size dependence of the plastic flow a strain gradient...... plasticity model is applied here for the metal. A cohesive zone model is applied to represent the crack growth along the bond between the two Cu films. This cohesive zone model incorporates the effect of higher order stresses in the continuum, such that the higher order tractions on the crack faces decay...

  3. Reducing thermal mismatch stress in anodically bonded silicon-glass wafers: theoretical estimation

    Science.gov (United States)

    Sinev, Leonid S.; Ryabov, Vladimir T.

    2017-01-01

    This paper reports the theoretical study and estimations of thermal mismatch stress reduction in anodically bonded silicon-glass stacks by justifiable selection of bonding temperature and glass thickness. This can be done only after prior thorough study of temperature dependence of the linear thermal expansion coefficient of the glass and silicon to be used. We show by analyzing such a dependence of several glass brands that the usual idea of decreasing the bonding process temperature as a solution to the thermal mismatch stress problem can be a failure. Interchanging glass brands during device design is shown to produce very contrasting changes in residual stresses. These results are in good agreement with finite-element modeling. This paper reports there is proportion between glass and silicon wafer thicknesses minimizing thermal mismatch stress at unbonded side of the silicon independently of the bonding or working temperatures chosen.

  4. Evolution of the interface structure of bonded Si wafers after high temperature annealing

    Energy Technology Data Exchange (ETDEWEB)

    Zakharov, N D; Pippel, E; Werner, P; Goesele, U [Max Planck Institute of Microstructure Physics, 06120 Halle (Saale) (Germany); Vdovin, V [Institute for Chemical Problems of Microelectronics, 119017 Moscow (Russian Federation); Milvidskii, M [Institute of Rare Metals ' Giredmet' , 119017 Moscow (Russian Federation); Ries, M; Seacrist, M [MEMC Inc, 501 Pearl Drive, St Peters, MO, 63376 (United States); Falster, R [MEMC Electronic Materials SpA, Viale Gherzi 31, I-28100 Novara (Italy)

    2010-02-01

    The evolution of the interfaces of bonded Si wafers and the corresponding low-angle twist boundary have been analysed in dependence on thermal annealing. Two orientation relations were investigated: i) Si(001)/SiO{sub 2}/Si(001) and ii) Si(110)/SiO{sub 2}/Si(001). The interfaces were analysed by TEM and STEM/EDX and EELS. It is found that the decomposition rate of the intermediate oxide layer and the formation of a Si-Si bonded interface depend very much on the lattice mismatch and on the twist angle. A dissolution of the oxide and the formation of Si-Si boundaries occur much faster in the case of Si(110)/Si(001) bonding than in Si(001)/Si(001). The process of interface fusion and the dissolution of the oxide layer are discussed.

  5. Transparent and electrically conductive GaSb/Si direct wafer bonding at low temperatures by argon-beam surface activation

    Science.gov (United States)

    Predan, F.; Reinwand, D.; Klinger, V.; Dimroth, F.

    2015-10-01

    Direct wafer bonds of the material system n-GaSb/n-Si have been achieved by means of a low-temperature direct wafer bonding process, enabling an optical transparency of the bonds along with a high electrical conductivity of the boundary layer. In the used technique, the surfaces are activated by sputter-etching with an argon fast-atom-beam (FAB) and bonded in ultra-high vacuum. The bonds were annealed at temperatures between 300 and 400 °C, followed by an optical, mechanical and electrical characterization of the interface. Additionally, the influence of the sputtering on the surface topography of the GaSb was explicitly investigated. Fully bonded wafer pairs with high bonding strengths were found, as no blade could be inserted into the bonds without destroying the samples. The interfacial resistivities of the bonded wafers were significantly reduced by optimizing the process parameters, by which Ohmic interfacial resistivities of less than 5 mΩ cm2 were reached reproducibly. These promising results make the monolithic integration of GaSb on Si attractive for various applications.

  6. Integrated optical MEMS using through-wafer vias and bump-bonding.

    Energy Technology Data Exchange (ETDEWEB)

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  7. Comprehensive investigation of sequential plasma activated Si/Si bonded interfaces for nano-integration on the wafer scale.

    Science.gov (United States)

    Kibria, M G; Zhang, F; Lee, T H; Kim, M J; Howlader, M M R

    2010-04-02

    The sequentially plasma activated bonding of silicon wafers has been investigated to facilitate the development of chemical free, room temperature and spontaneous bonding required for nanostructure integration on the wafer scale. The contact angle of the surface and the electrical and nanostructural behavior of the interface have been studied. The contact angle measurements show that the sequentially plasma (reactive ion etching plasma followed by microwave radicals) treated surfaces offer highly reactive and hydrophilic surfaces. These highly reactive surfaces allow spontaneous integration at the nanometer scale without any chemicals, external pressure or heating. Electrical characteristics show that the current transportation across the nanobonded interface is dependent on the plasma parameters. High resolution transmission electron microscopy results confirm nanometer scale bonding which is needed for the integration of nanostructures. The findings can be applied in spontaneous integration of nanostructures such as nanowires/nanotubes/quantum dots on the wafer scale.

  8. Investigation of Surface Pre-Treatment Methods for Wafer-Level Cu-Cu Thermo-Compression Bonding

    Directory of Open Access Journals (Sweden)

    Koki Tanaka

    2016-12-01

    Full Text Available To increase the yield of the wafer-level Cu-Cu thermo-compression bonding method, certain surface pre-treatment methods for Cu are studied which can be exposed to the atmosphere before bonding. To inhibit re-oxidation under atmospheric conditions, the reduced pure Cu surface is treated by H2/Ar plasma, NH3 plasma and thiol solution, respectively, and is covered by Cu hydride, Cu nitride and a self-assembled monolayer (SAM accordingly. A pair of the treated wafers is then bonded by the thermo-compression bonding method, and evaluated by the tensile test. Results show that the bond strengths of the wafers treated by NH3 plasma and SAM are not sufficient due to the remaining surface protection layers such as Cu nitride and SAMs resulting from the pre-treatment. In contrast, the H2/Ar plasma–treated wafer showed the same strength as the one with formic acid vapor treatment, even when exposed to the atmosphere for 30 min. In the thermal desorption spectroscopy (TDS measurement of the H2/Ar plasma–treated Cu sample, the total number of the detected H2 was 3.1 times more than the citric acid–treated one. Results of the TDS measurement indicate that the modified Cu surface is terminated by chemisorbed hydrogen atoms, which leads to high bonding strength.

  9. Geometrical Deviation and Residual Strain in Novel Silicon-on-Aluminium-Nitride Bonded Wafers

    Institute of Scientific and Technical Information of China (English)

    门传玲; 徐政; 吴雁军; 安正华; 谢欣云; 林成鲁

    2002-01-01

    Aluminium nitride (AlN), with much higher thermal conductivity, is considered to be an excellent alternative to the SiO2 layer in traditional silicon-on-insulator (SOI) materials. The silicon-on-aluminium-nitride (SOAN) structure was fabricated by the smart-cut process to alleviate the self-heating effects for traditional SOI. The convergent beam Kikuchi line diffraction pattern results show that some rotational misalignment exists when two wafers are bonded, which is about 3°. The high-resolution x-ray diffraction result indicates that, before annealing at high temperature, the residual lattice strain in the top silicon layer is tensile. After annealing at 1100° C for an hour, the strain in the top Si decreases greatly and reverses from tensile to slightly compressive as a result of viscous flow of AlN.

  10. A three-mask process for fabricating vacuum-sealed capacitive micromachined ultrasonic transducers using anodic bonding.

    Science.gov (United States)

    Yamaner, F Yalçın; Zhang, Xiao; Oralkan, Ömer

    2015-05-01

    This paper introduces a simplified fabrication method for vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT) arrays using anodic bonding. Anodic bonding provides the established advantages of wafer-bondingbased CMUT fabrication processes, including process simplicity, control over plate thickness and properties, high fill factor, and ability to implement large vibrating cells. In addition to these, compared with fusion bonding, anodic bonding can be performed at lower processing temperatures, i.e., 350°C as opposed to 1100°C; surface roughness requirement for anodic bonding is more than 10 times more relaxed, i.e., 5-nm rootmean- square (RMS) roughness as opposed to 0.5 nm for fusion bonding; anodic bonding can be performed on smaller contact area and hence improves the fill factor for CMUTs. Although anodic bonding has been previously used for CMUT fabrication, a CMUT with a vacuum cavity could not have been achieved, mainly because gas is trapped inside the cavities during anodic bonding. In the approach we present in this paper, the vacuum cavity is achieved by opening a channel in the plate structure to evacuate the trapped gas and subsequently sealing this channel by conformal silicon nitride deposition in the vacuum environment. The plate structure of the fabricated CMUT consists of the single-crystal silicon device layer of a silicon-on-insulator wafer and a thin silicon nitride insulation layer. The presented fabrication approach employs only three photolithographic steps and combines the advantages of anodic bonding with the advantages of a patterned metal bottom electrode on an insulating substrate, specifically low parasitic series resistance and low parasitic shunt capacitance. In this paper, the developed fabrication scheme is described in detail, including process recipes. The fabricated transducers are characterized using electrical input impedance measurements in air and hydrophone measurements in immersion. A representative

  11. Low-Cost, Manufacturable, 6-Inch Wafer Bonding Process for Next-Generation 5-Junction IMM+Ge Photovoltaic Devices Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose the development of a 6-inch wafer bonding process to allow bonding of a multi-junction inverted metamorphic (IMM) tandem solar cell structure to an...

  12. Wafer-level integration of NiTi shape memory alloy on silicon using Au-Si eutectic bonding

    OpenAIRE

    Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; van der Wijngaart, Wouter

    2012-01-01

    This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au-Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more ...

  13. Plate-like structure health monitoring based on ultrasonic guided wave technology by using bonded piezoelectric ceramic wafers

    Science.gov (United States)

    Liu, Zenghua; Zhao, Jichen; He, Cunfu; Wu, Bin

    2008-11-01

    Piezoelectric ceramic wafers are applied for the excitation and detection of ultrasonic guided waves to determine the health state of plate-like structures. Two PZT wafers, whose diameter is 11mm and thickness is 0.4mm respectively, are bonded permanently on the surface of a 1mm thick aluminum plate. One of these wafers is actuated by sinusoidal tone burst at various frequencies ranging from 100kHz to 500kHz, the other one is used as a receiver for acquiring ultrasonic guided wave signals. According to the amplitudes and shapes of these received signals, guided wave modes and their proper frequency range by using these wafers are determined. For the improvement of the signal-to-noise ratio, the Daubechies wavelet of order 40 is used for signal denoising as the mother wavelet. Furthermore, the detection of an artificial cylindrical through-hole defect is achieved by using S0 at 300kHz. Experimental results show that it is feasible and effective to detect defects in plate-like structures based on ultrasonic guided wave technology by using bonded piezoelectric ceramic wafers.

  14. Wafer-level packaging with compression-controlled seal ring bonding

    Science.gov (United States)

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  15. New Three-Dimensional Integration Technology Using Chip-to-Wafer Bonding to Achieve Ultimate Super-Chip Integration

    Science.gov (United States)

    Fukushima, Takafumi; Yamada, Yusuke; Kikuchi, Hirokazu; Koyanagi, Mitsumasa

    2006-04-01

    A new three-dimensional (3D) integration technology using the chip-to-wafer bonding technique provides the ultimate super-chip integration in which various kinds of chip of different sizes can be vertically stacked and electrically connected through a number of vertical interconnections. We have investigated several key technologies of vertical interconnection formation, chip alignment, chip-to-wafer bonding, adhesive injection, and chip thinning to vertically stack known good dies (KGDs) into 3D LSI chips. By using these key technologies, successful fabrication of 3D LSI test chips with vertical interconnections consisting of In-Au microbumps and buried interconnections filled with polycrystalline silicon (poly-Si) was demonstrated. The test chips was composed of three kinds of very thin chip of 5, 6, and 7 mm2 and ranging in thickness from 30 to 90 μm. Each chip is tightly bonded using a low-viscosity epoxy adhesive as a dielectric material.

  16. The fabrication of microfluidic structures by means of full-wafer adhesive bonding using a poly(dimethylsiloxane) catalyst

    Science.gov (United States)

    Samel, Björn; Kamruzzaman Chowdhury, M.; Stemme, Göran

    2007-08-01

    In this work, we present the use of a PDMS (poly(dimethylsiloxane)) curing-agent as the intermediate layer for adhesive full-wafer bonding suitable for fabrication of microfluidic structures. The curing-agent of the two-component silicone rubber (Sylgard 184) is spin coated on a substrate, brought into contact with another PDMS layer and heat cured to create an irreversible seal which is as strong as or even stronger than plasma-assisted PDMS bonding. The maximum bond strength is measured to 800 kPa when bonding together PDMS and silicon. The applicability of the new PDMS adhesive bonding method is verified by means of fabricating microfluidic structures. Using this method allows for wafer-level bonding of PDMS to various materials such as PDMS, glass or silicon and more importantly to selectively bond different layers by using a patterned adhesive bonding technique. Moreover, precise alignment of the structural layers is facilitated since curing is initiated upon heat which is an advantage when fabricating multilayer microfluidic devices.

  17. A hand-held row-column addressed CMUT probe with integrated electronics for volumetric imaging

    DEFF Research Database (Denmark)

    Engholm, Mathias; Christiansen, Thomas Lehrmann; Beers, Christopher;

    2015-01-01

    A 3 MHz, λ / 2-pitch 62+62 channel row-column addressed 2-D CMUT array designed to be mounted in a probe handle and connected to a commercial BK Medical scanner for real-time volumetric imaging is presented. It is mounted and wire-bonded on a flexible PCB, which is connected to two rigid PCBs wit...

  18. 300 mm InGaAs-on-insulator substrates fabricated using direct wafer bonding and the Smart Cut™ technology

    Science.gov (United States)

    Widiez, Julie; Sollier, Sébastien; Baron, Thierry; Martin, Mickaël; Gaudin, Gweltaz; Mazen, Frédéric; Madeira, Florence; Favier, Sylvie; Salaun, Amélie; Alcotte, Reynald; Beche, Elodie; Grampeix, Helen; Veytizou, Christelle; Moulet, Jean-Sébastien

    2016-04-01

    This paper reports the first demonstration of 300 mm In0.53Ga0.47As-on-insulator (InGaAs-OI) substrates. The use of direct wafer bonding and the Smart Cut™ technology lead to the transfer of high quality InGaAs layer on large Si wafer size (300 mm) at low effective cost, taking into account the reclaim of the III-V on Si donor substrate. The optimization of the three key building blocks of this technology is detailed. (1) The III-V epitaxial growth on 300 mm Si wafers has been optimized to decrease the defect density. (2) For the first time, hydrogen-induced thermal splitting is made inside the indium phosphide (InP) epitaxial layer and a wide implantation condition ranges is observed on the contrary to bulk InP. (3) Finally a specific direct wafer bonding with alumina oxide has been chosen to avoid outgas diffusion at the alumina oxide/III-V compound interface.

  19. Wafer-level hermetic thermo-compression bonding using electroplated gold sealing frame planarized by fly-cutting

    Science.gov (United States)

    Farisi, Muhammad Salman Al; Hirano, Hideki; Frömel, Jörg; Tanaka, Shuji

    2017-01-01

    In this paper, a novel wafer-level hermetic packaging technology for heterogeneous device integration is presented. Hermetic sealing is achieved by low-temperature thermo-compression bonding using electroplated Au micro-sealing frame planarized by single-point diamond fly-cutting. The proposed technology has significant advantages compared to other established processes in terms of integration of micro-structured wafer, vacuum encapsulation and electrical interconnection, which can be achieved at the same time. Furthermore, the technology is also achievable for a bonding frame width as narrow as 30 μm, giving it an advantage from a geometry perspective, and bonding temperatures as low as 300 °C, making it advantageous for temperature-sensitive devices. Outgassing in vacuum sealed cavities is studied and a cavity pressure below 500 Pa is achieved by introducing annealing steps prior to bonding. The pressure of the sealed cavity is measured by zero-balance method utilizing diaphragm-structured bonding test devices. The leak rate into the packages is determined by long-term sealed cavity pressure measurement for 1500 h to be less than 2.0× {{10}-14} Pa m3s-1. In addition, the bonding shear strength is also evaluated to be higher than 100 MPa.

  20. Geiger mode theoretical study of a wafer-bonded Ge on Si single-photon avalanche photodiode

    Science.gov (United States)

    Ke, Shaoying; Lin, Shaoming; Wei, Huang; Wang, Jianyuan; cheng, Buwen; Liang, Kun; Li, Cheng; Chen, Songyan

    2017-02-01

    The investigation of the single-photon properties of a wafer-bonded Ge/Si single-photon avalanche photodiode (SPAD) is theoretically conducted. We focus on the effect of the natural GeO2 layer (hydrophilic reaction) at the Ge/Si wafer-bonded interface on dark count characteristics and single-photon response. It is found that the wafer-bonded Ge/Si SPAD exhibits very low dark current at 250 K due to the absence of threading dislocation (TD) in the Ge layer. Owing to the increase of the unit-gain bias applied on the SPAD, the primary dark current (I DM) increases with the increase in GeO2 thickness. Furthermore, the dependence of the linear-mode gain and 3 dB bandwidth (BW) for the dark count on GeO2 thickness is also presented. It is observed that the dark count probability of the Ge/Si SPAD significantly increases with the increase in GeO2 thickness due to the increase of the I DM and the reduction of the 3 dB BW. It is also found that with the increase in GeO2 thickness, the external quantum efficiency, which affects the single-photon detection efficiency (SPDE), drastically decreases because of the blocking effect of the GeO2 layer and the serious recombination at the wafer-bonded Ge/Si interface. The afterpulsing probability (AP) shows an abnormal behavior with GeO2 thickness. This results from the decrease in avalanche charge and increase in effective transit time.

  1. Wafer level vacuum packaging of scanning micro-mirrors using glass-frit and anodic bonding methods

    Science.gov (United States)

    Langa, S.; Drabe, C.; Kunath, C.; Dreyhaupt, A.; Schenk, H.

    2013-03-01

    In this paper the authors report about the six inch wafer level vacuum packaging of electro-statically driven two dimensional micro-mirrors. The packaging was done by means of two types of wafer bonding methods: anodic and glass frit. The resulting chips after dicing are 4 mm wide, 6 mm long and 1.6 mm high and the residual pressure inside the package after dicing was estimated to be between 2 and 20 mbar. This allowed us to reduce the driving voltage of the micro-mirrors by more than 40% compared to the driving voltage without vacuum packaging. The vacuum stability after 5 months was verified by measurement using the so called "membrane method". Persistence of the vacuum was proven. No getter materials were used for packaging.

  2. Wafer-level packaging and laser bonding as an approach for silicon-into-lab-on-chip integration

    Science.gov (United States)

    Brettschneider, T.; Dorrer, C.; Bründel, M.; Zengerle, R.; Daub, M.

    2013-05-01

    A novel approach for the integration of silicon biosensors into microfluidics is presented. Our approach is based on wafer-level packaging of the silicon die and a laser-bonding process of the resulting mold package into a polymer-multilayer stack. The introduction of a flexible and 40 μm thin hot melt foil as an intermediate layer enables laser bonding between materials with different melting temperatures, where standard laser welding processes cannot be employed. All process steps are suitable for mass production, e.g. the approach does not involve any dispensing steps for glue or underfiller. The integration approach was demonstrated and evaluated regarding process technology by wafer-level redistribution of daisy chain silicon dies representing a generic biosensor. Electrical connection was successfully established and laser-bonding tensile strength of 5.7 N mm-2 and burst pressure of 587 kPa at a temperature of 100 °C were achieved for the new material combination. The feasibility of the complete packaging approach was shown by the fabrication of a microfluidic flow cell with embedded mold package.

  3. Investigation of room-temperature wafer bonded GaInP/GaAs/InGaAsP triple-junction solar cells

    Science.gov (United States)

    Yang, Wen-xian; Dai, Pan; Ji, Lian; Tan, Ming; Wu, Yuan-yuan; Uchida, Shiro; Lu, Shu-long; Yang, Hui

    2016-12-01

    We report on the fabrication of III-V compound semiconductor multi-junction solar cells using the room-temperature wafer bonding technique. GaInP/GaAs dual-junction solar cells on GaAs substrate and InGaAsP single junction solar cell on InP substrate were separately grown by all-solid state molecular beam epitaxy (MBE). The two cells were then bonded to a triple-junction solar cell at room-temperature. A conversion efficiency of 30.3% of GaInP/GaAs/InGaAsP wafer-bonded solar cell was obtained at 1-sun condition under the AM1.5G solar simulator. The result suggests that the room-temperature wafer bonding technique and MBE technique have a great potential to improve the performance of multi-junction solar cell.

  4. Effects of adhesive thickness on the Lamb wave pitch-catch signal using bonded piezoelectric wafer transducers

    Science.gov (United States)

    Islam, M. M.; Huang, H.

    2016-08-01

    This paper investigates the effects of adhesive layer on Lamb wave ultrasound pitch-catch signals that are excited and sensed by piezoelectric wafer transducers bonded on a slender structure. Analytical models were established to simulate the longitudinal and flexural vibrations of the structures separately and parametric studies of the bonding layer properties, i.e. the shear transfer parameter, adhesive thickness, and shear modulus, were performed. The parametric studies indicate that there exists an optimal adhesive layer thickness that generates maximum ultrasound pitch-catch signal for both wave modes. This prediction was subsequently validated by measurements. In addition, an improved match between the measured and simulated pitch-catch signals was achieved by adjusting the adhesive layer parameters.

  5. A Flip-Chip AlGaInP LED with GaN/Sapphire Transparent Substrate Fabricated by Direct Wafer Bonding

    Institute of Scientific and Technical Information of China (English)

    LIANG Ting; GUO Xia; GUAN Bao-Lu; GUO Jing; GU Xiao-Ling; LIN Qiao-Ming; SHEN Guang-Di

    2007-01-01

    A red-light AlGaInP light emitting diode(LED)is fabricated by,using direct wafer bonding technology.Taking N-GaN wafer as the transparent substrate,the red-light LED is flip-chiped onto a structured silicon submount.Electronic luminance(EL)test reveals that the luminance flux is 130% higher than that of the conventional LED made from the same LED wafer.Current-voltage(Ⅰ-Ⅴ)measurement indicates that the bonding processes do not impact the electrical property of AlGaInP LED in the small voltage region (V<1.5V).In the large voltage region (V>1.5 V),the Ⅰ-Ⅴ characteristic exhibits space-charge-limited currents characteristic due to the p-GaAs/n-GaN bonding interface.

  6. GaN-Si direct wafer bonding at room temperature for thin GaN device transfer after epitaxial lift off

    Science.gov (United States)

    Mu, Fengwen; Morino, Yuki; Jerchel, Kathleen; Fujino, Masahisa; Suga, Tadatomo

    2017-09-01

    Room temperature GaN-Si direct wafer bonding was done by surface activated bonding (SAB). At first, a feasibility study using GaN template has been done. Then, crystal-face dependence of the bonding results for freestanding GaN substrate has been investigated between Ga-face and N-face. The results of Ga-face to Si bonding are better than that of N-face to Si bonding such as higher bonding energy and larger bonded area. This difference should be caused by their different surface roughnesses after chemical-mechanical polishing (CMP). Besides, both of the structure and composition of the two kinds of interfaces were investigated to understand the bonding mechanisms. The phenomenon of Ga-enrichment during surface activation and Ga-diffusion into Si at room temperature for both Ga-face bonding and N-face bonding has been confirmed.

  7. Modelling of CMUTs with Anisotropic Plates

    DEFF Research Database (Denmark)

    la Cour, Mette Funding; Christiansen, Thomas Lehrmann; Jensen, Jørgen Arendt

    2012-01-01

    Traditionally, CMUTs are modelled using the isotropic plate equation and this leads to deviations between analytical calculations and FEM simulations. In this paper, the deflection profile and material parameters are calculated using the anisotropic plate equation. It is shown that the anisotropic...

  8. Dimensional Scaling for Optimized CMUT Operations

    DEFF Research Database (Denmark)

    Lei, Anders; Diederichsen, Søren Elmin; la Cour, Mette Funding;

    2014-01-01

    This work presents a dimensional scaling study using numerical simulations, where gap height and plate thickness of a CMUT cell is varied, while the lateral plate dimension is adjusted to maintain a constant transmit immersion center frequency of 5 MHz. Two cell configurations have been simulated...

  9. Study on the pyroelectric properties of lithium niobate wafer prepared by wafer bonding and thinning%铌酸锂晶片的键合减薄及热释电性能研究

    Institute of Scientific and Technical Information of China (English)

    杨绪军; 陈箫; 刘岗; 牛坤旺; 张文栋

    2011-01-01

    铌酸锂(LN)作为一种热释电材料,可以被用于制作光电探测器敏感单元的敏感层,但通常LN晶片厚度为0.5 mm,远大于光电敏感单元厚度的要求,所以需要用键合减薄及抛光技术对LN晶片进行加工处理.本研究所用键合减薄技术主要包含:RZJ-304光刻胶键合、铣磨、抛光、剥离液剥离和丙酮清洗RZJ-304胶.利用该技术加工得到了面积为10 mm×10 mm,厚度为50 μm,表面比较光滑,表面粗糙度为1.63 nm的LN晶片.LN晶片的热释电信号峰峰值在减薄抛光后为176 mV,是未经处理时的4倍,满足了热释电探测器敏感层的要求.%Pyroelectric material lithium niobate (LN) can be used for the preparation of sensitive layer in the sensitive element of photoelectric detector. However, as the thickness of normal LN wafer, which is 0.5 mm, is much larger than the thickness of sensitive element, LN wafer need to be processed using the thinning and polishing techniques. A novel wafer bonding and thinning technique was introduced in this study, and it mainly included: wafer bonding with RZJ-304 photoresist, grinding, polishing, separating wafers with stripper and removing photoresist with acetone. LN wafer (10mm in square) with a thickness of 50 um is prepared using this technique, and the surface of prepared LN wafer is very smooth with the surface roughness being 1.63 nm. The peak value of the pyroelectric signal of the processed LN wafer is 176 mV, which is four times that of the unprocessed wafer, fulfilling the requirements of the sensitive layer of pyroelectric detector.

  10. Second-harmonic generation in periodically-poled thin film lithium niobate wafer-bonded on silicon

    Science.gov (United States)

    Rao, Ashutosh; Malinowski, Marcin; Honardoost, Amirmahdi; Talukder, Javed Rouf; Rabiei, Payam; Delfyett, Peter; Fathpour, Sasan

    2016-12-01

    Second-order optical nonlinear effects (second-harmonic and sum-frequency generation) are demonstrated in the telecommunication band by periodic poling of thin films of lithium niobate wafer-bonded on silicon substrates and rib-loaded with silicon nitride channels to attain ridge waveguide with cross-sections of ~ 2 {\\mu}m2. The compactness of the waveguides results in efficient second-order nonlinear devices. A nonlinear conversion of 8% is obtained with a pulsed input in 4 mm long waveguides. The choice of silicon substrate makes the platform potentially compatible with silicon photonics, and therefore may pave the path towards on-chip nonlinear and quantum-optic applications.

  11. Second-harmonic generation in periodically-poled thin film lithium niobate wafer-bonded on silicon

    CERN Document Server

    Rao, Ashutosh; Honardoost, Amirmahdi; Talukder, Javed Rouf; Rabiei, Rayam; Delfyett, Peter; Fathpour, Sasan

    2016-01-01

    Second-order optical nonlinear effects (second-harmonic and sum-frequency generation) are demonstrated in the telecommunication band by periodic poling of thin films of lithium niobate wafer-bonded on silicon substrates and rib-loaded with silicon nitride channels to attain ridge waveguide with cross-sections of ~ 2 {\\mu}m2. The compactness of the waveguides results in efficient second-order nonlinear devices. A nonlinear conversion of 8% is obtained with a pulsed input in 4 mm long waveguides. The choice of silicon substrate makes the platform potentially compatible with silicon photonics, and therefore may pave the path towards on-chip nonlinear and quantum-optic applications.

  12. Design and fabrication of high performance wafer-level vacuum packaging based on glass-silicon-glass bonding techniques

    Science.gov (United States)

    Zhang, Jinwen; Jiang, Wei; Wang, Xin; Zhou, Jilong; Yang, Huabing

    2012-12-01

    In this paper, a high performance wafer-level vacuum packaging technology based on GSG triple-layer sealing structure for encapsulating large mass inertial MEMS devices fabricated by silicon-on-glass bulk micromachining technology is presented. Roughness controlling strategy of bonding surfaces was proposed and described in detail. Silicon substrate was thinned and polished by CMP after the first bonding with the glass substrate and was then bonded with the glass micro-cap. Zr thin film was embedded into the concave of the micro-cap by a shadow-mask technique. The glass substrate was thinned to about 100 µm, wet etched through and metalized for realizing vertical feedthrough. During the fabrication, all patterning processes were operated carefully so as to reduce extrusive fragments to as little as possible. In addition, a high-performance micro-Pirani vacuum gauge was integrated into the package for monitoring the pressure and the leak rate further. The result shows that the pressure in the package is about 120 Pa and has no obvious change for more than one year indicating 10-13 stdcc s-1 leak rate.

  13. 热释电红外探测器PZT晶片粘接质量控制%Quality Control of the PZT Wafer Bonding in Pyroelectric Infrared Detector

    Institute of Scientific and Technical Information of China (English)

    黄江平; 冯江敏; 王羽; 苏玉辉; 信思树; 李玉英

    2013-01-01

    热释电红外探测器芯片研制中,晶片粘接是芯片研制中的关键工艺之一。本文详细论述了粘接胶的选择依据及晶片粘接质量控制。确定了适合器件研制的粘接胶和粘胶工艺流程。对粘接中出现的问题及解决办法进行了讨论。研制出了完全能满足器件工艺要求的热释电探测器PZT晶片。%The wafer bonding is one of the key technologies in pyroelectric infrared detector chip development. This paper discusses the selection basis of bonding glue and quality control of wafer bonding in details, also determines the adhesive glue and the technology suitable for detector development, and analyzes the problems and the resolution method in the course of wafer bonding. The PZT wafer that can fully meet the technology requirements of pyroelectric detector is provided.

  14. High-Q Wafer Level Package Based on Modified Tri-Layer Anodic Bonding and High Performance Getter and Its Evaluation for Micro Resonant Pressure Sensor

    National Research Council Canada - National Science Library

    Liying Wang; Xiaohui Du; Lingyun Wang; Zhanhao Xu; Chenying Zhang; Dandan Gu

    2017-01-01

    In order to achieve and maintain a high quality factor (high-Q) for the micro resonant pressure sensor, this paper presents a new wafer level package by adopting cross-layer anodic bonding technique of the glass/silicon/silica (GSS...

  15. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    Science.gov (United States)

    Bronuzzi, J.; Mapelli, A.; Moll, M.; Sallese, J. M.

    2016-08-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations.

  16. High performance InAs quantum dot lasers on silicon substrates by low temperature Pd-GaAs wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Zihao; Preble, Stefan F. [Microsystems Engineering, Rochester Institute of Technology, Rochester, New York 14623 (United States); Yao, Ruizhe; Lee, Chi-Sen; Guo, Wei, E-mail: wei-guo@uml.edu [Physics and Applied Physics Department, University of Massachusetts Lowell, Lowell, Massachusetts 01854 (United States); Lester, Luke F. [Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia 24061 (United States)

    2015-12-28

    InAs quantum dot (QD) laser heterostructures have been grown by molecular beam epitaxy system on GaAs substrates, and then transferred to silicon substrates by a low temperature (250 °C) Pd-mediated wafer bonding process. A low interfacial resistivity of only 0.2 Ω cm{sup 2} formed during the bonding process is characterized by the current-voltage measurements. The InAs QD lasers on Si exhibit comparable characteristics to state-of-the-art QD lasers on silicon substrates, where the threshold current density J{sub th} and differential quantum efficiency η{sub d} of 240 A/cm{sup 2} and 23.9%, respectively, at room temperature are obtained with laser bars of cavity length and waveguide ridge of 1.5 mm and 5 μm, respectively. The InAs QD lasers also show operation up to 100 °C with a threshold current density J{sub th} and differential quantum efficiency η{sub d} of 950 A/cm{sup 2} and 9.3%, respectively. The temperature coefficient T{sub 0} of 69 K from 60 to 100 °C is characterized from the temperature dependent J{sub th} measurements.

  17. Nature of bonding forces between two hydrogen-passivated silicon wafers

    DEFF Research Database (Denmark)

    Stokbro, Kurt; Nielsen, E.; Hult, E.;

    1998-01-01

    attraction between H overlayers, we find that the attraction is mainly due to long-range van der Waals interactions between the Si substrates, while the equilibrium separation is determined by short-range repulsion between occupied Si-H orbitals. Estimated bonding energies and Si-H frequency shifts...

  18. Mutual Radiation Impedance of Uncollapsed CMUT Cells with Different Radii

    CERN Document Server

    Ozgurluk, Alper; Atalar, Abdullah; Koymen, Hayrettin

    2015-01-01

    A polynomial approximation is proposed for the mutual acoustic impedance between uncollapsed capacitive micromachined ultrasonic transducer (CMUT) cells with different radii in an infinite rigid baffle. The resulting approximation is employed in simulating CMUTs with a circuit model. A very good agreement is obtained with the corresponding finite element simulation (FEM) result.

  19. An electrical test method for quality detecting of wafer level eutectic bonding

    Science.gov (United States)

    Zhang, Lemin; Jiao, Binbin; Ku, Will; Tseng, Li-Tien; Kong, Yanmei; Chien, Yu-Hao; Yun, Shichang; Chen, Dapeng

    2017-01-01

    As the costs of packaging and testing account for a substantial portion of microelectromechanical system (MEMS) devices, an effective and convenient characterization method is urgent to be investigated to lower the cost. In this paper, an electrical test method was utilized, and the test key used for a four-probe current-voltage test was designed to monitor the quality of the AuSn eutectic bonding. The electrical test can directly detect whether or not voids existed in the bonding layer. The difference in alloy state, for example, the existence of the (Au, Ni) 3Sn2 phase confirmed by the scanning electron microscope and energy dispersive x-ray spectroscopy test, can also be reflected by resistivity variation. The electrical test can be implemented automatically and conveniently unlike other characterization methods. Therefore, it is suitable to be applied in quality inspection in industrial production.

  20. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    CERN Document Server

    Bronuzzi, J.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

  1. High-Q Wafer Level Package Based on Modified Tri-Layer Anodic Bonding and High Performance Getter and Its Evaluation for Micro Resonant Pressure Sensor.

    Science.gov (United States)

    Wang, Liying; Du, Xiaohui; Wang, Lingyun; Xu, Zhanhao; Zhang, Chenying; Gu, Dandan

    2017-03-16

    In order to achieve and maintain a high quality factor (high-Q) for the micro resonant pressure sensor, this paper presents a new wafer level package by adopting cross-layer anodic bonding technique of the glass/silicon/silica (GSS) stackable structure and integrated Ti getter. A double-layer structure similar to a silicon-on-insulator (SOI) wafer is formed after the resonant layer and the pressure-sensitive layer are bonded by silicon direct bonding (SDB). In order to form good bonding quality between the pressure-sensitive layer and the glass cap layer, the cross-layer anodic bonding technique is proposed for vacuum package by sputtering Aluminum (Al) on the combination wafer of the pressure-sensitive layer and the resonant layer to achieve electrical interconnection. The model and the bonding effect of this technique are discussed. In addition, in order to enhance the performance of titanium (Ti) getter, the prepared and activation parameters of Ti getter under different sputtering conditions are optimized and discussed. Based on the optimized results, the Ti getter (thickness of 300 nm to 500 nm) is also deposited on the inside of the glass groove by magnetron sputtering to maintain stable quality factor (Q). The Q test of the built testing system shows that the number of resonators with a Q value of more than 10,000 accounts for more than 73% of the total. With an interval of 1.5 years, the Q value of the samples remains almost constant. It proves the proposed cross-layer anodic bonding and getter technique can realize high-Q resonant structure for long-term stable operation.

  2. High-Q Wafer Level Package Based on Modified Tri-Layer Anodic Bonding and High Performance Getter and Its Evaluation for Micro Resonant Pressure Sensor

    Directory of Open Access Journals (Sweden)

    Liying Wang

    2017-03-01

    Full Text Available In order to achieve and maintain a high quality factor (high-Q for the micro resonant pressure sensor, this paper presents a new wafer level package by adopting cross-layer anodic bonding technique of the glass/silicon/silica (GSS stackable structure and integrated Ti getter. A double-layer structure similar to a silicon-on-insulator (SOI wafer is formed after the resonant layer and the pressure-sensitive layer are bonded by silicon direct bonding (SDB. In order to form good bonding quality between the pressure-sensitive layer and the glass cap layer, the cross-layer anodic bonding technique is proposed for vacuum package by sputtering Aluminum (Al on the combination wafer of the pressure-sensitive layer and the resonant layer to achieve electrical interconnection. The model and the bonding effect of this technique are discussed. In addition, in order to enhance the performance of titanium (Ti getter, the prepared and activation parameters of Ti getter under different sputtering conditions are optimized and discussed. Based on the optimized results, the Ti getter (thickness of 300 nm to 500 nm is also deposited on the inside of the glass groove by magnetron sputtering to maintain stable quality factor (Q. The Q test of the built testing system shows that the number of resonators with a Q value of more than 10,000 accounts for more than 73% of the total. With an interval of 1.5 years, the Q value of the samples remains almost constant. It proves the proposed cross-layer anodic bonding and getter technique can realize high-Q resonant structure for long-term stable operation.

  3. Atomic scale fabrication of dangling bond structures on hydrogen passivated Si(0 0 1) wafers processed and nanopackaged in a clean room environment

    Science.gov (United States)

    Kolmer, Marek; Godlewski, Szymon; Zuzak, Rafal; Wojtaszek, Mateusz; Rauer, Caroline; Thuaire, Aurélie; Hartmann, Jean-Michel; Moriceau, Hubert; Joachim, Christian; Szymonski, Marek

    2014-01-01

    Specific surfaces allowing the ultra-high vacuum (UHV) creation of electronic interconnects and atomic nanostructures are required for the successful development of novel nanoscale electronic devices. Atomically flat and reconstructed Si(0 0 1):H surfaces are serious candidates for that role. In this work such Si:H surfaces were prepared in a cleanroom environment on 200 mm silicon wafers with a hydrogen bake and were subsequently bonded together to ensure the surface protection, and allow their transportation and storage for several months in air. Given the nature of the bonding, which was hydrophobic with weak van der Waals forces, we were then able to de-bond them in UHV. We show that the quality of the de-bonded Si:H surface enables the "at will" construction of sophisticated and complex dangling bond (DB) nanostructures by atomically precise scanning tunneling microscope (STM) tip induced desorption of hydrogen atoms. The DB structures created on slightly doped Si:H samples were characterized by scanning tunneling microscopy and spectroscopy (STM/STS) performed at 4 K. Our results demonstrate that DB nanostructures fabricated on UHV de-bonded Si(0 0 1):H wafers could be directly incorporated in future electronics as interconnects and parts of nanoscale logic circuits.

  4. Atomic scale fabrication of dangling bond structures on hydrogen passivated Si(0 0 1) wafers processed and nanopackaged in a clean room environment

    Energy Technology Data Exchange (ETDEWEB)

    Kolmer, Marek; Godlewski, Szymon; Zuzak, Rafal; Wojtaszek, Mateusz [Centre for Nanometer-Scale Science and Advanced Materials, NANOSAM, Faculty of Physics, Astronomy and Applied Computer Science, Jagiellonian University, Reymonta Str. 4, PL 30-059 Krakow (Poland); Rauer, Caroline; Thuaire, Aurélie; Hartmann, Jean-Michel; Moriceau, Hubert [CEA, LETI, Minatec Campus, 17, Avenue des Martyrs, 38 054 Grenoble Cedex 9 (France); Joachim, Christian [Nanosciences Group and MANA Satellite, CEMES-CNRS, 29 rue Jeanne Marvig, F-31055 Toulouse (France); Szymonski, Marek, E-mail: marek.szymonski@uj.edu.pl [Centre for Nanometer-Scale Science and Advanced Materials, NANOSAM, Faculty of Physics, Astronomy and Applied Computer Science, Jagiellonian University, Reymonta Str. 4, PL 30-059 Krakow (Poland)

    2014-01-01

    Specific surfaces allowing the ultra-high vacuum (UHV) creation of electronic interconnects and atomic nanostructures are required for the successful development of novel nanoscale electronic devices. Atomically flat and reconstructed Si(0 0 1):H surfaces are serious candidates for that role. In this work such Si:H surfaces were prepared in a cleanroom environment on 200 mm silicon wafers with a hydrogen bake and were subsequently bonded together to ensure the surface protection, and allow their transportation and storage for several months in air. Given the nature of the bonding, which was hydrophobic with weak van der Waals forces, we were then able to de-bond them in UHV. We show that the quality of the de-bonded Si:H surface enables the “at will” construction of sophisticated and complex dangling bond (DB) nanostructures by atomically precise scanning tunneling microscope (STM) tip induced desorption of hydrogen atoms. The DB structures created on slightly doped Si:H samples were characterized by scanning tunneling microscopy and spectroscopy (STM/STS) performed at 4 K. Our results demonstrate that DB nanostructures fabricated on UHV de-bonded Si(0 0 1):H wafers could be directly incorporated in future electronics as interconnects and parts of nanoscale logic circuits.

  5. Bubble evolution mechanism and stress-induced crystallization in low-temperature silicon wafer bonding based on a thin intermediate amorphous Ge layer

    Science.gov (United States)

    Ke, Shaoying; Lin, Shaoming; Ye, Yujie; Mao, Danfeng; Huang, Wei; Xu, Jianfang; Li, Cheng; Chen, Songyan

    2017-10-01

    The dependence of the morphology and crystallinity of an amorphous Ge (a-Ge) interlayer between two Si wafers on the annealing temperature is identified to understand the bubble evolution mechanism. The effect of a-Ge layer thickness on the bubble density and size at different annealing temperatures is also clearly clarified. It suggests that the bubble density is significantly affected by the crystallinity and thickness of the a-Ge layer. With the increase of the crystallinity and thickness of the a-Ge layer, the bubble density decreases. It is important that a near-bubble-free Ge interface, which is also an oxide-free interface, is achieved when the bonded Si wafers (a-Ge layer thickness  ⩾  20 nm) are annealed at 400 °C. Furthermore, the crystallization temperature of the a-Ge between the bonded Si wafers is lower than that on a Si substrate alone and the Ge grains firstly form at the Ge/Ge bonded interface, rather than the Ge/Si interface. We believe that the stress-induced crystallization of a-Ge film and the intermixing of Ge atoms at the Ge/Ge interface can be responsible for this feature.

  6. Dichromatic InGaN-based white light emitting diodes by using laser lift-off and wafer-bonding schemes

    Science.gov (United States)

    Lee, Y. J.; Lin, P. C.; Lu, T. C.; Kuo, H. C.; Wang, S. C.

    2007-04-01

    An InGaN-based dual-wavelength blue/green (470nm/550nm) light emitting diode (LED) with three terminal operations has been designed and fabricated by using sapphire laser lift-off and wafer-bonding schemes. The device is equivalent to a parallel connection of blue and green LEDs; thus the effective electrical resistance of the device could be reduced. The luminous efficiency is 40lm/W at 20mA, accompanied by a broad electroluminescence emission with a combination of blue and green colors. This monolithically integrated dichromatic lighting structure has great potential in the application of the solid-state lighting.

  7. Aberration-corrected transmission electron microscopy analyses of GaAs/Si interfaces in wafer-bonded multi-junction solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Häussler, Dietrich [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany); Houben, Lothar [Ernst Ruska-Centre for Microscopy and Spectroscopy with Electrons, Research Centre Juelich GmbH, 52425 Juelich (Germany); Essig, Stephanie [Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg (Germany); Kurttepeli, Mert [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany); Dimroth, Frank [Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg (Germany); Dunin-Borkowski, Rafal E. [Ernst Ruska-Centre for Microscopy and Spectroscopy with Electrons, Research Centre Juelich GmbH, 52425 Juelich (Germany); Jäger, Wolfgang, E-mail: wolfgang.jaeger@tf.uni-kiel.de [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany)

    2013-11-15

    Aberration-corrected scanning transmission electron microscopy (STEM) and electron energy loss spectroscopy (EELS) investigations have been applied to investigate the structure and composition fluctuations near interfaces in wafer-bonded multi-junction solar cells. Multi-junction solar cells are of particular interest since efficiencies well above 40% have been obtained for concentrator solar cells which are based on III-V compound semiconductors. In this methodologically oriented investigation, we explore the potential of combining aberration-corrected high-angle annular dark-field STEM imaging (HAADF-STEM) with spectroscopic techniques, such as EELS and energy-dispersive X-ray spectroscopy (EDXS), and with high-resolution transmission electron microscopy (HR-TEM), in order to analyze the effects of fast atom beam (FAB) and ion beam bombardment (IB) activation treatments on the structure and composition of bonding interfaces of wafer-bonded solar cells on Si substrates. Investigations using STEM/EELS are able to measure quantitatively and with high precision the widths and the fluctuations in element distributions within amorphous interface layers of nanometer extensions, including those of light elements. Such measurements allow the control of the activation treatments and thus support assessing electrical conductivity phenomena connected with impurity and dopant distributions near interfaces for optimized performance of the solar cells. - Highlights: • Aberration-corrected TEM and EELS reveal structural and elemental profiles across GaAs/Si bond interfaces in wafer-bonded GaInP/GaAs/Si - multi-junction solar cells. • Fluctuations in elemental concentration in nanometer-thick amorphous interface layers, including the disrubutions of light elements, are measured using EELS. • The projected widths of the interface layers are determined on the atomic scale from STEM-HAADF measurements. • The effects of atom and ion beam activation treatment on the bonding

  8. Preliminary reliability test of lateral-current-injection GaInAsP/InP membrane distributed feedback laser on Si substrate fabricated by adhesive wafer bonding

    Science.gov (United States)

    Fukuda, Kai; Inoue, Daisuke; Hiratani, Takuo; Amemiya, Tomohiro; Nishiyama, Nobuhiko; Arai, Shigehisa

    2017-02-01

    A preliminary reliability test was performed for lateral-current-injection GaInAsP/InP membrane Distributed Feedback (DFB) lasers fabricated by multi-regrowth and adhesive wafer bonding. The measurement was conducted for lasers with two different types of p-side electrode: Ti/Au and Au/Zn/Au. The device with the Au/Zn/Au electrode, which had better current-voltage (I-V) characteristics, showed no degradation of differential quantum efficiency and threshold current after continuous aging for 310 h at a bias current density of 5 kA/cm2. This result indicates that the multi-regrowth and bonding process for the GaInAsP/InP membrane DFB laser will not impact the initial reliability.

  9. High-density plasma-induced etch damage of wafer-bonded AlGaInP/mirror/Si light-emitting diodes

    CERN Document Server

    Wuu, D S; Huang, S H; Chung, C R

    2002-01-01

    Dry etch of wafer-bonded AlGaInP/mirror/Si light-emitting diodes (LEDs) with planar electrodes was performed by high-density plasma using an inductively coupled plasma (ICP) etcher. The etching characteristics were investigated by varying process parameters such as Cl sub 2 /N sub 2 gas combination, chamber pressure, ICP power and substrate-bias power. The corresponding plasma properties (ion flux and dc bias), in situ measured by a Langmuir probe, show a strong relationship to the etch results. With a moderate etch rate of 1.3 mu m/min, a near vertical and smooth sidewall profile can be achieved under a Cl sub 2 /(Cl sub 2 +N sub 2) gas mixture of 0.5, ICP power of 800 W, substrate-bias power of 100 W, and chamber pressure of 0.67 Pa. Quantitative analysis of the plasma-induced damage was attempted to provide a means to study the mechanism of leakage current and brightness with various dc bias voltages (-110 to -328 V) and plasma duration (3-5 min) on the wafer-bonded LEDs. It is found that the reverse leaka...

  10. Novel 1.3-micron high-speed directly modulated semiconductor laser device designs and the development of wafer bonding technology for compliant-substrate fabrication

    Science.gov (United States)

    Greenberg, Joseph

    2000-10-01

    substrate production requires the wafer fusion of two substrates. A wafer bonding system has been designed, built and tested to improve wafer bonding techniques for this application. This machine's scalable design is capable of improved reproducibility, uniformity and yield over comparable techniques.

  11. Integrated differential high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Farch, Kjartan

    2015-01-01

    In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order...... to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption...

  12. Simulating Capacitive Micromachined Ultrasonic Transducers (CMUTs) using Field II

    DEFF Research Database (Denmark)

    Bæk, David; Oralkan, Omer; Kupnik, Mario;

    2010-01-01

    Field II has been a recognized simulation tool for piezoceramic medical transducer arrays for more than a decade. The program has its strength in doing fast computations of the spatial impulse response (SIR) from array elements by dividing the elements into smaller mathematical elements (ME)s from...... which it calculates the SIR responses. The program features predefined models for classical transducer geometries, but currently none for the fast advancing CMUTs. This work addresses the assumptions required for modeling CMUTs with Field II. It is shown that rectangular array elements, populated...

  13. Investigation of PDMS as coating on CMUTs for Imaging

    DEFF Research Database (Denmark)

    la Cour, Mette Funding; Stuart, Matthias Bo; Laursen, Mads Bjerregaard;

    2014-01-01

    A protective layer is necessary for Capacitive Mi- cromachined Ultrasonic Transducers (CMUTs) to be used for imaging purpose. The layer should both protect the device itself and the patient while maintaining the performance of the device. In this work Sylgard 170 PDMS is tested as coating material...

  14. Integrated Reconfigurable High-Voltage Transmitting Circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2014-01-01

    -out and measurements are performed on the integrated circuit. The transmitting circuit is reconfigurable externally making it able to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes, pulse voltages up to 100 V, maximum pulse range of 50 V and frequencies up to 5 MHz. The area...

  15. Study of hybrid orientation structure wafer*

    Institute of Scientific and Technical Information of China (English)

    Tan Kaizhou; Zhang Jing; Xu Shiliu; Zhang Zhengfan; Yang Yonghui; Chen Jun; Liang Tao

    2011-01-01

    Two types of 5 μm thick hybrid orientation structure wafers, which were integrated by (110) or (100) orientation silicon wafers as the substrate, have been investigated for 15-40 V voltage ICs and MEMS sensor applications. They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique, and have been presented in China for the first time. The thickness of BOX SiO2 buried in wafer is 220 nm. It has been found that the quality of hybrid orientation structure with (100) wafer substrate is better than that with (110) wafer substrate by “Sirtl defect etching of HOSW”.

  16. Barrier reduction via implementation of InGaN interlayer in wafer-bonded current aperture vertical electron transistors consisting of InGaAs channel and N-polar GaN drain

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Jeonghee, E-mail: jhkim@ece.ucsb.edu; Laurent, Matthew A.; Li, Haoran; Lal, Shalini; Mishra, Umesh K. [Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106 (United States)

    2015-01-12

    This letter reports the influence of the added InGaN interlayer on reducing the inherent interfacial barrier and hence improving the electrical characteristics of wafer-bonded current aperture vertical electron transistors consisting of an InGaAs channel and N-polar GaN drain. The current-voltage characteristics of the transistors show that the implementation of N-polar InGaN interlayer effectively reduces the barrier to electron transport across the wafer-bonded interface most likely due to its polarization induced downward band bending, which increases the electron tunneling probability. Fully functional wafer-bonded transistors with nearly 600 mA/mm of drain current at V{sub GS} = 0 V and L{sub go} = 2 μm have been achieved, and thus demonstrate the feasibility of using wafer-bonded heterostructures for applications that require active carrier transport through both materials.

  17. Modeling of CMUTs with Multiple Anisotropic Layers and Residual Stress

    DEFF Research Database (Denmark)

    Engholm, Mathias; Thomsen, Erik Vilain

    2014-01-01

    Usually the analytical approach for modeling CMUTs uses the single layer plate equation to obtain the deflection and does not take anisotropy and residual stress into account. A highly accurate model is developed for analytical characterization of CMUTs taking an arbitrary number of layers...... and residual stress into account. Based on the stress-strain relation of each layer and balancing stress resultants and bending moments, a general multilayered anisotropic plate equation is developed for plates with an arbitrary number of layers. The exact deflection profile is calculated for a circular...... clamped plate of anisotropic materials with residual bi-axial stress. From the deflection shape the critical stress for buckling is calculated and by using the Rayleigh-Ritz method the natural frequency is estimated....

  18. Modeling and Measurements of CMUTs with Square Anisotropic Plates

    DEFF Research Database (Denmark)

    la Cour, Mette Funding; Christiansen, Thomas Lehrmann; Dahl-Petersen, Christian;

    2013-01-01

    The conventional method of modeling CMUTs use the isotropic plate equation to calculate the deflection, leading to deviations from FEM simulations including anisotropic effects of around 10% in center deflection. In this paper, the deflection is found for square plates using the full anisotropic...... plate equation and the Galerkin method. Utilizing the symmetry of the silicon crystal, a compact and accurate expression for the deflection can be obtained. The deviation from FEM in center deflection is

  19. Development of Blocked-Impurity-Band-Type Ge Detectors Fabricated with the Surface-Activated Wafer Bonding Method for Far-Infrared Astronomy

    Science.gov (United States)

    Hanaoka, M.; Kaneda, H.; Oyabu, S.; Yamagishi, M.; Hattori, Y.; Ukai, S.; Shichi, K.; Wada, T.; Suzuki, T.; Watanabe, K.; Nagase, K.; Baba, S.; Kochi, C.

    2016-07-01

    We report the current status of the development of our new detectors for far-infrared (FIR) astronomy. We develop Blocked-Impurity-Band (BIB)-type Ge detectors to realize large-format compact arrays covering a wide FIR wavelength range up to 200 \\upmu m. We fabricated Ge junction devices of different physical parameters with a BIB-type structure, using the room temperature, surface-activated wafer bonding (SAB) method. We measured the absolute responsivity and the spectral response curve of each device at low temperatures, using an internal blackbody source in a cryostat and a Fourier transform spectrometer, respectively. The results show that the SAB Ge junction devices have significantly higher absolute responsivities and longer cut-off wavelengths of the spectral response than the conventional bulk Ge:Ga device. Based upon the results, we discuss the optimum parameters of SAB Ge junction devices for FIR detectors. We conclude that SAB Ge junction devices possess a promising applicability to next-generation FIR detectors covering wavelengths up to ˜ 200 \\upmu m with high responsivity. As a next step, we plan to fabricate a BIB-type Ge array device in combination with a low-power cryogenic readout integrated circuit.

  20. Output pressure and harmonic characteristics of a CMUT as function of bias and excitation voltage

    DEFF Research Database (Denmark)

    Lei, Anders; Diederichsen, Søren Elmin; Hansen, Sebastian Molbech

    2015-01-01

    The large bandwidth makes CMUT based transducers interesting for both conventional and harmonic imaging. The inherent nonlinear behavior of the CMUT, however, poses an issue for harmonic imaging as it is difficult to dissociate the harmonics generated in the tissue from the harmonic content...... of the transmitted signal. The generation of intrinsic harmonics by the CMUT can be minimized by decreasing the excitation signal. This, however, leads to lower fundamental pressure which limits the desired generation of harmonics in the medium. This work examines the output pressure and harmonic characteristics...... of a CMUT as function of bias and excitation voltage. The harmonic to fundamental ratio of the surface pressures declines for decreasing excitation voltage and increasing bias voltage. The ratio, however, becomes unchanged for bias levels close to the pull-in voltage. The harmonic limitations of the CMUT...

  1. Modal analysis based equivalent circuit model and its verification for a single cMUT cell

    Science.gov (United States)

    Mao, S. P.; Rottenberg, X.; Rochus, V.; Czarnecki, P.; Helin, P.; Severi, S.; Nauwelaers, B.; Tilmans, H. A. C.

    2017-03-01

    This paper presents the lumped equivalent circuit model and its verification of both transmission and reception properties of a single cell capacitive micromachined ultrasonic transducer (cMUT), which is operating in a non-collapse small signal region. The derivation of this equivalent circuit model is based on the modal analysis techniques, harmonic modes are included by using the mode superposition method; and thus a wide frequency range response of the cMUT cell can be simulated by our equivalent circuit model. The importance of the cross modal coupling between different eigenmodes of a cMUT cell is discussed by us for the first time. In this paper the development of this model is only illustrated by a single circular cMUT cell under a uniform excitation. Extension of this model and corresponding results under a more generalized excitation will be presented in our upcoming publication (Mao et al 2016 Proc. IEEE Int. Ultrasonics Symp.). This model is verified by both finite element method (FEM) simulation and experimental characterizations. Results predicted by our model are in a good agreement with the FEM simulation results, and this works for a single cMUT cell operated in either transmission or reception. Results obtained from the model also rather match the experimental results of the cMUT cell. This equivalent circuit model provides an easy and precise way to rapidly predict the behaviors of cMUT cells.

  2. Integrated reconfigurable high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2015-01-01

    In this paper a high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in scanners for medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The transmitting circuit is reconfigurable externally making it able...... performance. The design occupies an on-chip area of 0.938 mm2 and the power consumption of a 128-element transmitting circuit array that would be used in an portable ultrasound scanner is found to be a maximum of 181 mW....

  3. Integrated reconfigurable high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger;

    2015-01-01

    In this paper a high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in scanners for medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The transmitting circuit is reconfigurable externally making it able...... performance. The design occupies an on-chip area of 0.938 mm2 and the power consumption of a 128-element transmitting circuit array that would be used in an portable ultrasound scanner is found to be a maximum of 181 mW....

  4. Parametric nonlinear lumped element model for circular CMUTs in collapsed mode.

    Science.gov (United States)

    Aydoğdu, Elif; Ozgurluk, Alper; Atalar, Abdullah; Köymen, Hayrettin

    2014-01-01

    We present a parametric equivalent circuit model for a circular CMUT in collapsed mode. First, we calculate the collapsed membrane deflection, utilizing the exact electrical force distribution in the analytical formulation of membrane deflection. Then we develop a lumped element model of collapsed membrane operation. The radiation impedance for collapsed mode is also included in the model. The model is merged with the uncollapsed mode model to obtain a simulation tool that handles all CMUT behavior, in transmit or receive. Large- and small-signal operation of a single CMUT can be fully simulated for any excitation regime. The results are in good agreement with FEM simulations.

  5. Electrically pumped 1.3 microm room-temperature InAs/GaAs quantum dot lasers on Si substrates by metal-mediated wafer bonding and layer transfer.

    Science.gov (United States)

    Tanabe, Katsuaki; Guimard, Denis; Bordel, Damien; Iwamoto, Satoshi; Arakawa, Yasuhiko

    2010-05-10

    An electrically pumped InAs/GaAs quantum dot laser on a Si substrate has been demonstrated. The double-hetero laser structure was grown on a GaAs substrate by metal-organic chemical vapor deposition and layer-transferred onto a Si substrate by GaAs/Si wafer bonding mediated by a 380-nm-thick Au-Ge-Ni alloy layer. This broad-area Fabry-Perot laser exhibits InAs quantum dot ground state lasing at 1.31 microm at room temperature with a threshold current density of 600 A/cm(2).

  6. Three wafer stacking for 3D integration.

    Energy Technology Data Exchange (ETDEWEB)

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  7. Three wafer stacking for 3D integration.

    Energy Technology Data Exchange (ETDEWEB)

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  8. A low power, area efficient fpga based beamforming technique for 1-D CMUT arrays.

    Science.gov (United States)

    Joseph, Bastin; Joseph, Jose; Vanjari, Siva Rama Krishna

    2015-08-01

    A low power area efficient digital beamformer targeting low frequency (2MHz) 1-D linear Capacitive Micromachined Ultrasonic Transducer (CMUT) array is developed. While designing the beamforming logic, the symmetry of the CMUT array is well exploited to reduce the area and power consumption. The proposed method is verified in Matlab by clocking an Arbitrary Waveform Generator(AWG). The architecture is successfully implemented in Xilinx Spartan 3E FPGA kit to check its functionality. The beamforming logic is implemented for 8, 16, 32, and 64 element CMUTs targeting Application Specific Integrated Circuit (ASIC) platform at Vdd 1.62V for UMC 90nm technology. It is observed that the proposed architecture consumes significantly lesser power and area (1.2895 mW power and 47134.4 μm(2) area for a 64 element digital beamforming circuit) compared to the conventional square root based algorithm.

  9. Electrostatic and Small-Signal Analysis of CMUTs With Circular and Square Anisotropic Plates

    DEFF Research Database (Denmark)

    la Cour, Mette Funding; Christiansen, Thomas Lehrmann; Jensen, Jørgen Arendt

    2015-01-01

    Traditionally, Capacitive Micromachined Ultrasonic Transducers (CMUTs) are modeled using the isotropic plate equation and this leads to deviations between analytical calcu- lations and Finite Element Modeling (FEM). In this paper, the deflection is calculated for both circular and square plates...... using the full anisotropic plate equation. It is shown that the anisotropic calculations match perfectly with FEM while an isotropic ap- proach causes up to 10% deviations in deflection. For circular plates an exact solution can be found and for square plates using the Galerkin method and utilizing...... the symmetry of the silicon crystal, a compact and accurate expression for the deflection can be obtained. The deviation from FEM in center deflection is plates is also applied to the CMUT. The deflection of a square plate was measured on fabricated CMUTs using a white light...

  10. Four-Junction Solar Cell with 40% Target Efficiency Fabricated by Wafer Bonding and Layer Transfer: Final Technical Report, 1 January 2005 - 31 December 2007

    Energy Technology Data Exchange (ETDEWEB)

    Atwater, H. A.

    2008-11-01

    We realized high-quality InGaP/GaAs 2-junction top cells on Ge/Si, InGaAs/InP bottom cells, direct-bond series interconnection of tandem cells, and modeling of bonded 3- and 4-junction device performance.

  11. 1D multi-element CMUT arrays for ultrasound thermal therapy

    Science.gov (United States)

    N'Djin, William Apoutou; Canney, Michael; Meynier, Cyril; Chavrier, Françoise; Lafon, Cyril; Nguyen-Dinh, An; Chapelon, Jean-Yves; Carpentier, Alexandre

    2017-03-01

    Interstitial therapeutic ultrasound devices are a promising technology for performing thermal ablation in a wide variety of organs. In this study, the use of Capacitive Micromachined Ultrasound Transducers (CMUTs) for interstitial heating applications was investigated. CMUTs exhibit potential advantages for use in therapeutic ultrasound applications in comparison to standard piezo ultrasound transducer technologies as they have good characteristics in terms of miniaturization (cell size: few dozens of microns), bandwidth (several MHz) and high electro-acoustic efficiency. Two designs of CMUT arrays were studied: (1) a 1D 128-element planar-CMUT array originally dedicated to abdominal ultrasound imaging purposes (5 MHz, element size: 0.3 × 8.0 mm2); (2) a 12-element linear-array, 32.4-mm long and 0.8-mm wide, developed specifically for minimally-invasive interstitial therapeutic applications (6 MHz, element size: 2.7 × 0.8 mm2). Simulations were performed to evaluate the ability to generate thermal lesions in soft tissues with: (1) 1 single linear array, (2) a combination of multiple linear arrays positioned on a cylindrical catheter. Experimental investigations performed with the CMUT imaging array showed the ability to generate surface acoustic intensities (Iac) up to 20 W.cm-2 and to generate intense centimetric thermal lesions in in-vitro turkey breast tissues. At 6 MHz, a single element was able to generate in water a maximum peak pressure of >0.5 MPa. In simulations, the ability to use various power levels and frequencies on independent elements, as well as combinations of multiple linear-arrays offered sufficient flexibility to achieve a wide variety of thermal ablation patterns in 3D. Simulated ablation volumes could be controlled to cover accurately non-symmetrical volumes of brain metastases. In conclusion, CMUT arrays show interesting characteristics, which may open new perspectives of spatial control for conformal interstitial thermal therapy with

  12. PECVD low stress silicon nitride analysis and optimization for the fabrication of CMUT devices

    Science.gov (United States)

    Bagolini, Alvise; Savoia, Alessandro Stuart; Picciotto, Antonino; Boscardin, Maurizio; Bellutti, Pierluigi; Lamberti, Nicola; Caliano, Giosuè

    2015-01-01

    Two technological options to achieve a high deposition rate, low stress plasma-enhanced chemical vapor deposition (PECVD) silicon nitride to be used in capacitive micromachined ultrasonic transducers (CMUT) fabrication are investigated and presented. Both options are developed and implemented on standard production line PECVD equipment in the framework of a CMUT technology transfer from R & D to production. A tradeoff between deposition rate, residual stress and electrical properties is showed. The first option consists in a double layer of silicon nitride with a relatively high deposition rate of ~100 nm min-1 and low compressive residual stress, which is suitable for the fabrication of the thick nitride layer used as a mechanical support of the CMUTs. The second option involves the use of a mixed frequency low-stress silicon nitride with outstanding electrical insulation capability, providing improved mechanical and electrical integrity of the CMUT active layers. The behavior of the nitride is analyzed as a function of deposition parameters and subsequent annealing. The nitride layer characterization is reported in terms of interfaces density influence on residual stress, refractive index, deposition rate, and thickness variation both as deposited and after thermal treatment. A sweet spot for stress stability is identified at an interfaces density of 0.1 nm-1, yielding 87 MPa residual stress after annealing. A complete CMUT device fabrication is reported using the optimized nitrides. The CMUT performance is tested, demonstrating full functionality in ultrasound imaging applications and an overall performance improvement with respect to previous devices fabricated with non-optimized silicon nitride.

  13. Volumetric elasticity imaging with a 2-D CMUT array.

    Science.gov (United States)

    Fisher, Ted G; Hall, Timothy J; Panda, Satchi; Richards, Michael S; Barbone, Paul E; Jiang, Jingfeng; Resnick, Jeff; Barnes, Steve

    2010-06-01

    This article reports the use of a two-dimensional (2-D) capacitive micro-machined ultrasound transducer (CMUT) to acquire radio-frequency (RF) echo data from relatively large volumes of a simple ultrasound phantom to compare three-dimensional (3-D) elasticity imaging methods. Typical 2-D motion tracking for elasticity image formation was compared with three different methods of 3-D motion tracking, with sum-squared difference (SSD) used as the similarity measure. Differences among the algorithms were the degree to which they tracked elevational motion: not at all (2-D search), planar search, combination of multiple planes and plane independent guided search. The cross-correlation between the predeformation and motion-compensated postdeformation RF echo fields was used to quantify motion tracking accuracy. The lesion contrast-to-noise ratio was used to quantify image quality. Tracking accuracy and strain image quality generally improved with increased tracking sophistication. When used as input for a 3-D modulus reconstruction, high quality 3-D displacement estimates yielded accurate and low noise modulus reconstruction.

  14. Equivalent circuit-based analysis of CMUT cell dynamics in arrays.

    Science.gov (United States)

    Oguz, H K; Atalar, Abdullah; Köymen, Hayrettin

    2013-05-01

    Capacitive micromachined ultrasonic transducers (CMUTs) are usually composed of large arrays of closely packed cells. In this work, we use an equivalent circuit model to analyze CMUT arrays with multiple cells. We study the effects of mutual acoustic interactions through the immersion medium caused by the pressure field generated by each cell acting upon the others. To do this, all the cells in the array are coupled through a radiation impedance matrix at their acoustic terminals. An accurate approximation for the mutual radiation impedance is defined between two circular cells, which can be used in large arrays to reduce computational complexity. Hence, a performance analysis of CMUT arrays can be accurately done with a circuit simulator. By using the proposed model, one can very rapidly obtain the linear frequency and nonlinear transient responses of arrays with an arbitrary number of CMUT cells. We performed several finite element method (FEM) simulations for arrays with small numbers of cells and showed that the results are very similar to those obtained by the equivalent circuit model.

  15. Elimination of Second-Harmonics in CMUTs using Square Pulse Excitation

    DEFF Research Database (Denmark)

    Lei, Anders; Diederichsen, Søren Elmin; Hansen, Sebastian Molbech;

    2016-01-01

    of the transmitted signal. This work presents how proper pulse coding of a bipolar pulser, which is present in most commercial ultrasound scanners, can reduce the intrinsic generated harmonic to fundamental pressure amplitude ratio to below −35 dB, making CMUT probes usable for clinical applications....

  16. Integrated Differential Three-Level High-Voltage Pulser Output Stage for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger;

    2015-01-01

    A new integrated differential three-level highvoltage pulser output stage to drive capacitive micromachined ultrasonic transducers (CMUTs) is proposed in this paper. A topology comparison between the new differential output stage and the most commonly used single-ended topology is performed...

  17. Capacitive Substrate Coupling of Row–Column-Addressed 2-D CMUT Arrays

    DEFF Research Database (Denmark)

    Engholm, Mathias; Bouzari, Hamed; Jensen, Jørgen Arendt;

    2016-01-01

    of the semiconductor substrate can be sustained for at least 10 minutes making it applicable for row–column-addressed CMUT arrays for ultrasonic imaging. Theoretically the reduced parasitic capacitance indicates that the receive sensitivity of the bottom elements can be increased by a factor of 2:1....

  18. 3-D Vector Flow Using a Row-Column Addressed CMUT Array

    DEFF Research Database (Denmark)

    Holbek, Simon; Christiansen, Thomas Lehrmann; Engholm, Mathias;

    2016-01-01

    This paper presents an in-house developed 2-D capacitive micromachined ultrasonic transducer (CMUT) appliedfor 3-D blood flow estimation. The probe breaks with conventional transducers in two ways; first, the ultrasonicpressure field is generated from thousands of small vibrating micromachined...

  19. CMUT With Substrate-Embedded Springs For Non-Flexural Plate Movement.

    Science.gov (United States)

    Nikoozadeh, Amin; Khuri-Yakub, Pierre T

    2010-01-01

    A conventional capacitive micromachined ultrasonic transducer (CMUT) is composed of many cells connected in parallel. Since the plate in each CMUT cell is anchored at its perimeter, the average displacement is several times smaller than the displacement of an equivalent ideal piston transducer. In addition, the post areas, where the plates are anchored to, are non-active and, thus, do not contribute to the transduction. We propose a CMUT structure that resembles an ideal capacitive piston transducer, where the movable top plate only undergoes translation rather than deflection. Our proposed CMUT structure is composed of a rigid plate connected to a substrate using relatively long and narrow posts, providing the spring constant for the movement of the plate. Rather than the flexure of the plate as in a conventional CMUT, this device operates based on the compression of the compliant posts. For a capacitive transducer, a thin electrostatic gap is provided under the top plate. We used finite element analysis (FEA) to design and verify the structure's functionality. The simulation results show a fractional bandwidth of over 100% in immersion for all the designs. They also confirm that the average displacement of the top plate is above 90% of its peak displacement. We fabricated the first prototype based on this idea, which only requires a simple 3-mask fabrication process. In addition to 128-element 1-D arrays, we fabricated a variety of 240 μm × 240 μm, single-element transducers with different post configurations. We successfully measured the electrical input impedance of the fabricated devices and confirmed their resonant behavior in air. Further, we measured the acoustic pressure using a calibrated hydrophone at a known distance. Using this measurement, we calculated a peak-to-peak pressure of 1.5 MPa at the face of the transducer. Our results show that it is possible to fabricate CMUTs that exhibit ideal piston-like plate movement. Because of the substrate

  20. High-voltage integrated transmitting circuit with differential driving for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz

    2016-01-01

    In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... is designed and implemented in AMS 0.35 μ m high-voltage process. Measurements are performed on the fabricated integrated circuit in order to assess its performance. The transmitting circuit consists of a low-voltage control logic, pulse-triggered level shifters and a differential output stage that generates...... pulses at differential voltage levels of 60, 80 and 100 V, a frequency up to 5 MHz and a measured driving strength of 2.03 V/ns with the CMUT electrical model connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption at the ultrasound scanner operation...

  1. Transmitting Performance Evaluation of ASICs for CMUT-Based Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Diederichsen, Søren Elmin; Jørgensen, Ivan Harald Holger

    2017-01-01

    Portable ultrasound scanners (PUS) have, in recent years, raised a lot of attention, as they can potentially overcome some of the limitations of static scanners. However, PUS have a lot of design limitations including size and power consumption. These restrictions can compromise the image quality...... of the scanner. In order to overcome these restrictions, application specific integrated circuits (ASICs) are needed to implement the electronics. In this work, a comparative study of the transmitting performance of a capacitive micromachined ultrasonic transducer (CMUT) driven by a commercial generic ultrasound...... in the time and frequency domains. The difference in normalized signal amplitude evaluated at the center frequency of the CMUT is −1.9 dB and the measured bandwidth is equivalent. The ASIC consumes only 1.3% of the total power consumption used by the commercial transmitter....

  2. Wafer characteristics via reflectometry

    Science.gov (United States)

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  3. Design and simulation of a tactile display based on a CMUT array

    Science.gov (United States)

    Chouvardas, Vasilios G.; Hatalis, Miltiadis K.; Miliou, Amalia N.

    2012-10-01

    In this article, we present the design of a tactile display based on a CMUT-phased array. The array implements a 'pixel' of the display and is used to focus airborne ultrasound energy on the skin surface. The pressure field, generated by the focused ultrasound waves, is used to excite the mechanoreceptors under the skin and transmit tactile information. The results of Finite Element Analysis (FEA) of the Capacitive Micromachined Ultrasonic Transducer (CMUT) and the CMUT-phased array for ultrasound emission are presented. The 3D models of the device and the array were developed using a commercial FEA package. Modelling and simulations were performed using the parameters from the POLYMUMPS surface micromachining technology from MEMSCAP. During the analysis of the phased array, several parameters were studied in order to determine their importance in the design of the tactile display. The output of the array is compared with the acoustic intensity thresholds in order to prove the feasibility of the design. Taking into account the density of the mechanoreceptors in the skin, we conclude that there should be at least one receptor under the excitation area formed on the skin.

  4. InGaN/GaN multi-quantum well and LED growth on wafer-bonded sapphire-on-polycrystalline AlN substrates by metalorganic chemical vapor deposition.

    Energy Technology Data Exchange (ETDEWEB)

    Crawford, Mary Hagerott; Olson, S. M. (Aonex Technologies Inc., Pasadena, CA); Banas, M.; Park, Y. -B. (Aonex Technologies Inc., Pasadena, CA); Ladous, C. (Aonex Technologies Inc., Pasadena, CA); Russell, Michael J.; Thaler, Gerald; Zahler, J. M. (Aonex Technologies Inc., Pasadena, CA); Pinnington, T. (Aonex Technologies Inc., Pasadena, CA); Koleske, Daniel David; Atwater, Harry A. (Aonex Technologies Inc., Pasadena, CA)

    2008-06-01

    We report growth of InGaN/GaN multi-quantum well (MQW) and LED structures on a novel composite substrate designed to eliminate the coefficient of thermal expansion (CTE) mismatch problems which impact GaN growth on bulk sapphire. To form the composite substrate, a thin sapphire layer is wafer-bonded to a polycrystalline aluminum nitride (P-AlN) support substrate. The sapphire layer provides the epitaxial template for the growth; however, the thermo-mechanical properties of the composite substrate are determined by the P-AlN. Using these substrates, thermal stresses associated with temperature changes during growth should be reduced an order of magnitude compared to films grown on bulk sapphire, based on published CTE data. In order to test the suitability of the substrates for GaN LED growth, test structures were grown by metalorganic chemical vapor deposition (MOCVD) using standard process conditions for GaN growth on sapphire. Bulk sapphire substrates were included as control samples in all growth runs. In situ reflectance monitoring was used to compare the growth dynamics for the different substrates. The material quality of the films as judged by X-ray diffraction (XRD), photoluminescence and transmission electron microscopy (TEM) was similar for the composite substrate and the sapphire control samples. Electroluminescence was obtained from the LED structure grown on a P-AlN composite substrate, with a similar peak wavelength and peak width to the control samples. XRD and Raman spectroscopy results confirm that the residual strain in GaN films grown on the composite substrates is dramatically reduced compared to growth on bulk sapphire substrates.

  5. Selective low temperature microcap packaging technique through flip chip and wafer level alignment

    Science.gov (United States)

    Pan, C. T.

    2004-04-01

    In this study, a new technique of selective microcap bonding for packaging 3-D MEMS (Micro Electro Mechanical Systems) devices is presented. Microcap bonding on a selected area of the host wafer was successfully demonstrated through flip chip and wafer level alignment. A passivation treatment was developed to separate the microcap from the carrier wafer. A thick metal nickel (Ni) microcap was fabricated by an electroplating process. Its stiffness is superior to that of thin film poly-silicon made by the surface micromachining technique. For the selective microcap packaging process, photo definable materials served as the intermediate adhesive layer between the host wafer and the metal microcap on the carrier wafer. Several types of photo definable material used as the adhesive layer were tested and characterized for bonding strength. The experimental result shows that excellent bonding strength at low bonding temperature can be achieved.

  6. Within-wafer CD variation induced by wafer shape

    Science.gov (United States)

    Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

    2016-03-01

    In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

  7. Wafer bonding process for building MEMS devices

    Science.gov (United States)

    Pabo, Eric F.; Meiler, Josef; Matthias, Thorsten

    2014-06-01

    The technology for the measurement of colour rendering and colour quality is not new, but many parameters related to this issue are currently changing. A number of standard methods were developed and are used by different specialty areas of the lighting industry. CIE 13.3 has been the accepted standard implemented by many users and used for many years. Light-emitting Diode (LED) technology moves at a rapid pace and, as this lighting source finds wider acceptance, it appears that traditional colour-rendering measurement methods produce inconsistent results. Practical application of various types of LEDs yielded results that challenged conventional thinking regarding colour measurement of light sources. Recent studies have shown that the anatomy and physiology of the human eye is more complex than formerly accepted. Therefore, the development of updated measurement methodology also forces a fresh look at functioning and colour perception of the human eye, especially with regard to LEDs. This paper includes a short description of the history and need for the measurement of colour rendering. Some of the traditional measurement methods are presented and inadequacies are discussed. The latest discoveries regarding the functioning of the human eye and the perception of colour, especially when LEDs are used as light sources, are discussed. The unique properties of LEDs when used in practical applications such as luminaires are highlighted.

  8. Wafer-Level Vacuum Packaging of Smart Sensors.

    Science.gov (United States)

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  9. Wafer-Level Vacuum Packaging of Smart Sensors

    Directory of Open Access Journals (Sweden)

    Allan Hilton

    2016-10-01

    Full Text Available The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  10. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    Science.gov (United States)

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

  11. Transceiver Design for CMUT-Based Super-Resolution Ultrasound Imaging.

    Science.gov (United States)

    Behnamfar, Parisa; Molavi, Reza; Mirabbasi, Shahriar

    2016-04-01

    A recently introduced structure for the capacitive micromachined ultrasonic transducers (CMUTs) has focused on the applications of the asymmetric mode of vibration and has shown promising results in construction of super-resolution ultrasound images. This paper presents the first implementation and experimental results of a transceiver circuit to interface such CMUT structures. The multiple input/multiple output receiver in this work supports both fundamental and asymmetric modes of operation and includes transimpedance amplifiers and low-power variable-gain stages. These circuit blocks are designed considering the trade-offs between gain, input impedance, noise, linearity and power consumption. The high-voltage transmitter can generate pulse voltages up to 60 V while occupying a considerably small area. The overall circuit is designed and laid out in a 0.35 μm CMOS process and a four-channel transceiver occupies 0.86 × 0.38 mm(2). The prototype chip is characterized in both electrical and mechanical domains. Measurement results show that each receiver channel has a nominal gain of 110 dBΩ with a 3 dB bandwidth of 9 MHz while consuming 1.02 mW from a 3.3 V supply. The receiver is also highly linear, with 1 dB compression point of minimum 1.05 V which is considerably higher than the previously reported designs. The transmitter consumes 98.1 mW from a 30 V supply while generating 1.38 MHz, 30 V pulses. The CMOS-CMUT system is tested in the transmit mode and shows full functionality in air medium.

  12. Towards a Reduced-Wire Interface for CMUT-Based Intravascular Ultrasound Imaging Systems.

    Science.gov (United States)

    Lim, Jaemyung; Tekes, Coskun; Degertekin, F Levent; Ghovanloo, Maysam

    2017-04-01

    Having intravascular ultrasound (IVUS) imaging capability on guide wires used in cardiovascular interventions may eliminate the need for separate IVUS catheters and expand the use of IVUS in a larger portion of the vasculature. High frequency capacitive micro machined ultrasonic transducer (CMUT) arrays should be integrated with interface electronics and placed on the guide wire for this purpose. Besides small size, this system-on-a-chip (SoC) front-end should connect to the back-end imaging system with a minimum number of wires to preserve the critical mechanical properties of the guide wire. We present a 40 MHz CMUT array interface SoC, which will eventually use only two wires for power delivery and transmits image data using a combination of analog-to-time conversion (ATC) and an impulse radio ultra-wideband (IR-UWB) wireless link. The proof-of-concept prototype ASIC consumes only 52.8 mW and occupies 4.07 [Formula: see text] in a 0.35- [Formula: see text] standard CMOS process. A rectifier and regulator power the rest of the SoC at 3.3 V from a 10 MHz power carrier that is supplied through a 2.4 m micro-coax cable with an overall efficiency of 49.1%. Echo signals from an 8-element CMUT array are amplified by a transimpedance amplifier (TIA) array and down-converted to baseband by quadrature sampling using a 40 MHz clock, derived from the power carrier. The ATC generates pulse-width-modulated (PWM) samples at 2 × 10 MS/s with 6 bit resolution, while the entire system achieved 5.1 ENOB. Preliminary images from the prototype system are presented, and alternative data transmission and possible future directions towards practical implementation are discussed.

  13. 3D互连中光刻与晶圆级键合技术面临的挑战,趋势及解决方案%Challenges, Trends and Solutions for 3D Interconnects in Lithography and Wafer Level Bonding Techniques

    Institute of Scientific and Technical Information of China (English)

    Margarete Zoberbier; Erwin Hell; Kathy Cook; Marc Hennemayer; Dr.-Ing.Barbara Neubert

    2010-01-01

    Technology advances such as 3D Integration are expanding the potential applications of products into mass markets such as consumer electronics. These new technologies are also pushing the envelope of what's currently possible for many production processes, including lithography processes and wafer bonding.There is still the need to coat, pattern and etch structures. This paper will explore some of the lithographic challenges associated with 3D interconnection technology. Wafer bonding techniques as used in the 3D Packaging will be described with all the challenges and available solutions and trends.Furthermore a new Maskalinger technology will be introduced which allows extreme alignment accuracy assisted by pattern recognition down to 0.25 μm.An overall introduction on the challenges, trends and solutions for 3D interconnects in lithography and Wafer Level bonding techniques and the SUSS's equipment platform will be described accordingly to the needed processes. The processing issues encountered in those techniques will be discussed with a focus on wafer bonding and lithography steps.%目前,3D集成技术的优势正在扩展消费类电子产品的潜在应用进入批量市场.这些新技术也在推进着当前许多生产工艺中的一些封装技术包括光刻和晶圆键合成为可能.其中还需要涂胶,作图和蚀刻结构.探讨一些与三维互连相关的光刻技术的挑战.用于三维封装的晶圆键合技术将结合这些挑战和可用的解决方案及发展趋势一并介绍.此外还介绍了一种新的光刻设备,它可通过图形识别技术的辅助实现低于0.25μm的最终对准精度.对于采用光刻和晶圆级键合技术在三维互连中的挑战,趋势和解决方案及SUSS公司设备平台的整体介绍将根据工艺要求来描述.在这些技术中遇到的工艺问题将集中在晶圆键合和光刻工序方面重点讨论.

  14. Electrostatic and Small-Signal Analysis of CMUTs With Circular and Square Anisotropic Plates.

    Science.gov (United States)

    Funding la Cour, Mette; Christiansen, Thomas Lehrmann; Jensen, Jørgen Arendt; Thomsen, Erik Vilain

    2015-08-01

    Traditionally, capacitive micromachined ultrasonic transducers (CMUTs) are modeled using the isotropic plate equation, and this leads to deviations between analytical calculations and finite element modeling (FEM). In this paper, the deflection is calculated for both circular and square plates using the full anisotropic plate equation. It is shown that the anisotropic calculations match excellently with FEM, whereas an isotropic approach causes up to 10% deviations in deflection. For circular plates, an exact solution can be found. For square plates using the Galerkin method, and utilizing the symmetry of the silicon crystal, a compact and accurate expression for the deflection can be obtained. The deviation from FEM in center deflection is white light interferometer. Fitting the plate parameter for the anisotropic calculated deflection to the measurement, a deviation of 0.07% is seen. Electrostatic and small-signal dynamic analysis are performed using energy considerations including anisotropy. The stable position, effective spring constant, pullin distance, and pull-in voltage are found for both circular and square anisotropic plates, and the pressure dependence is included by comparison with the corresponding analysis for a parallel plate. Measurements on fabricated devices with both circular and square plates subjected to increasing bias voltage are performed, and it is observed that the models including anisotropic effects are within the uncertainty interval of the measurements. Finally, a lumped element small-signal model for both circular and square anisotropic plates is derived to describe the dynamics of the CMUT.

  15. Wafer-level vacuum/hermetic packaging technologies for MEMS

    Science.gov (United States)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  16. High-voltage integrated transmitting circuit with differential driving for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz;

    2016-01-01

    In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... is designed and implemented in AMS 0.35 μ m high-voltage process. Measurements are performed on the fabricated integrated circuit in order to assess its performance. The transmitting circuit consists of a low-voltage control logic, pulse-triggered level shifters and a differential output stage that generates...... conditions is 0.936 mW including the load. The integrated circuits measured prove to be consistent and robust to local process variations by measurements....

  17. Integrated circuits for volumetric ultrasound imaging with 2-D CMUT arrays.

    Science.gov (United States)

    Bhuyan, Anshuman; Choe, Jung Woo; Lee, Byung Chul; Wygant, Ira O; Nikoozadeh, Amin; Oralkan, Ömer; Khuri-Yakub, Butrus T

    2013-12-01

    Real-time volumetric ultrasound imaging systems require transmit and receive circuitry to generate ultrasound beams and process received echo signals. The complexity of building such a system is high due to requirement of the front-end electronics needing to be very close to the transducer. A large number of elements also need to be interfaced to the back-end system and image processing of a large dataset could affect the imaging volume rate. In this work, we present a 3-D imaging system using capacitive micromachined ultrasonic transducer (CMUT) technology that addresses many of the challenges in building such a system. We demonstrate two approaches in integrating the transducer and the front-end electronics. The transducer is a 5-MHz CMUT array with an 8 mm × 8 mm aperture size. The aperture consists of 1024 elements (32 × 32) with an element pitch of 250 μm. An integrated circuit (IC) consists of a transmit beamformer and receive circuitry to improve the noise performance of the overall system. The assembly was interfaced with an FPGA and a back-end system (comprising of a data acquisition system and PC). The FPGA provided the digital I/O signals for the IC and the back-end system was used to process the received RF echo data (from the IC) and reconstruct the volume image using a phased array imaging approach. Imaging experiments were performed using wire and spring targets, a ventricle model and a human prostrate. Real-time volumetric images were captured at 5 volumes per second and are presented in this paper.

  18. Fabrication of Vacuum-Sealed Capacitive Micromachined Ultrasonic Transducer Arrays Using Glass Reflow Process

    Directory of Open Access Journals (Sweden)

    Nguyen Van Toan

    2016-04-01

    Full Text Available This paper presents a process for the fabrication of vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT arrays using glass reflow and anodic bonding techniques. Silicon through-wafer interconnects have been investigated by the glass reflow process. Then, the patterned silicon-glass reflow wafer is anodically bonded to an SOI (silicon-on-insulator wafer for the fabrication of CMUT devices. The CMUT 5 × 5 array has been successfully fabricated. The resonant frequency of the CMUT array with a one-cell radius of 100 µm and sensing gap of 3.2 µm (distance between top and bottom electrodes is observed at 2.84 MHz. The Q factor is approximately 1300 at pressure of 0.01 Pa.

  19. A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.

    Science.gov (United States)

    Huang, Xiwei; Cheong, Jia Hao; Cha, Hyouk-Kyu; Yu, Hongbin; Je, Minkyu; Yu, Hao

    2013-01-01

    One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

  20. MEMS Wafer-level Packaging Technology Using LTCC Wafer

    Science.gov (United States)

    Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

    This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40°C×30min/+125°C×30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

  1. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  2. Wafer Fusion for Integration of Semiconductor Materials and Devices

    Energy Technology Data Exchange (ETDEWEB)

    Choquette, K.D.; Geib, K.M.; Hou, H.Q.; Allerman, A.A.; Kravitz, S.; Follstaedt, D.M.; Hindi, J.J.

    1999-05-01

    We have developed a wafer fusion technology to achieve integration of semiconductor materials and heterostructures with widely disparate lattice parameters, electronic properties, and/or optical properties for novel devices not now possible on any one substrate. Using our simple fusion process which uses low temperature (400-600 C) anneals in inert N{sub 2} gas, we have extended the scope of this technology to examine hybrid integration of dissimilar device technologies. As a specific example, we demonstrate wafer bonding vertical cavity surface emitting lasers (VCSELs) to transparent AlGaAs and GaP substrates to fabricate bottom-emitting short wavelength VCSELs. As a baseline fabrication technology applicable to many semiconductor systems, wafer fusion will revolutionize the way we think about possible semiconductor devices, and enable novel device configurations not possible by epitaxial growth.

  3. Note: Near infrared interferometric silicon wafer metrology.

    Science.gov (United States)

    Choi, M S; Park, H M; Joo, K N

    2016-04-01

    In this investigation, two near infrared (NIR) interferometric techniques for silicon wafer metrology are described and verified with experimental results. Based on the transparent characteristic of NIR light to a silicon wafer, the fiber based spectrally resolved interferometry can measure the optical thickness of the wafer and stitching low coherence scanning interferometry can reconstruct entire surfaces of the wafer.

  4. Critical Cleaning Requirements for Back End Wafer Bumping Processes

    Energy Technology Data Exchange (ETDEWEB)

    Bixenman, M. [Kyzen Corporation (United States)

    2000-04-24

    As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packages in a huge device with hundreds of leads. The solution is bumps; hold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud bumping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research gas focused on enhanced cleaning solutions that meet this critical cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein. (author). 9 refs.

  5. The electrostatic-alloy bonding technique used in MEMS

    Institute of Scientific and Technical Information of China (English)

    WANG Wei; CHEN Wei-ping

    2006-01-01

    Electrostatic-alloy bonding of silicon wafer with glass deposited by Au to form Si/Au-glass water,and bonding of Si/Au-glass with silicon wafer were researched during fabrication of pressure sensors.The silicon wafer and glass wafer with an Au film resistor were bonded by electrostatic bonding,and then Si-Au alloy bonding was formed by annealing at 400℃ for 2 h.The air sealability of the cavity after bonding was finally tested using the N2 filling method.The results indicate that large bond strength was obtained at the bonding interface.This process was used in fabricating a pressure sensor with a sandwich structure.The results indicate that the sensor presented better performances and that the bonding techniques can be used in MEMS packaging.

  6. Wafer Replacement Cluster Tool (Presentation);

    Energy Technology Data Exchange (ETDEWEB)

    Branz, H. M.

    2008-04-01

    This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

  7. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

    Science.gov (United States)

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

    2014-02-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

  8. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  9. 三维互连中光刻及晶圆级键合技术的挑战、趋势和解决方案%Challenges, Trends and Solutions for 3D Interconnects in Lithography and Wafer Level Bonding Techniques

    Institute of Scientific and Technical Information of China (English)

    Margarete Zoberbier; Erwin Hell; Kathy Cook; Marc Hennemayer; Dr.-Ing. Barbara Neubert

    2009-01-01

    基于它的技术优势三雏集成技术正在不断地被应用到新的产品中,也包括被应用到消费电子产品里.同时也对许多工艺提出了新的要求,其中也包括光刻和晶圆级键合.三维集成技术还是需要光刻工艺来完成图形的转换,为此,讨论了三维集成工艺对工艺设备和技术提出的挑战.介绍了SUSS公司与三维技术相关的产品.着重讨论与三维集成工艺相关的光刻和键合工艺.描述了三维集成对它们提出的挑战以及目前已有的解决方案和前景.并介绍一款新的具有0.25μm对准精度的接近接触式光刻机.%Technology advances such as 3D Integration are expanding the potential applications of products into mass markets such as consumer electronics. These new technologies are also pushing the envelope of what's currently possible for many production processes, including lithography processes and wafer bonding.There is the need to coat, pattern and etch structures which may have tens or even hundreds of microns in height. This paper will explore some of the lithographic challenges associated with 3D interconnection technology, where use of the vertical dimension has necessitated new methods of conformally coating high topography, new imaging techniques to align various masking levels to the underlying patterns, and new exposure techniques to accomplish high fidelity patterning over such high structures. Wafer bonding techniques as used in the 3D Packaging will be described with all the challenges and available solutions and trends. Furthermore a new Maskalinger technology will be introduced which allows extreme alignment accuracy assisted by pattern recognition down to 0.25 μm.

  10. Fabrication of Capacitive Micromachined Ultrasonic Transducers Using a Boron Etch-Stop Method

    DEFF Research Database (Denmark)

    Diederichsen, Søren Elmin; Sandborg-Olsen, Filip; Engholm, Mathias

    2016-01-01

    Capacitive Micromachined Ultrasonic Transducers (CMUTs) fabricated using Silicon-On-Insulator (SOI) wafers often have large thickness variation of the flexible plate, which causes variation in both pull-in voltage and resonant frequency across the CMUT array. This work presents a bond and boron...... wt% potassium hydroxide solution with isopropyl alcohol added to increase the etch selectivity to the highly doped boron layer. The resulting plate thickness uniformity is estimated from scanning electron micrographs to a mean value of 2.00μm±2.5%. The resonant frequency in air for a 1-D linear CMUT...

  11. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    Science.gov (United States)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  12. Temperature Dependent Electrical Properties of PZT Wafer

    Science.gov (United States)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  13. Deposition uniformity inspection in IC wafer surface

    Science.gov (United States)

    Li, W. C.; Lin, Y. T.; Jeng, J. J.; Chang, C. L.

    2014-03-01

    This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

  14. Effect of In vitro Passage with Selection Pressure on Fitness of Plasmid-free Chlamydia Muridarum Strain CMUT3%体外传代选择对鼠衣原体质粒缺失株培养特性的影响

    Institute of Scientific and Technical Information of China (English)

    陈超群; 任林; 陆春雪; 李忠玉; 钟光明; 吴移谋

    2016-01-01

    Objective To unravel the effect of passage selection pressure on fitness of plasmid ̄free Chlamydia muri ̄darum strain CMUT3 and uncover the correlation between genetic and phenotypic signatures. Methods CMUT3 organisms were in vitro passaged for 40 generations under the alternating unassisted/assisted ̄infection cycle conditions and the infectivity of initial and final generation organisms in cell culture was measured by comparing their attachment efficiency phenotype in the presence or absence of centrifugation.Next ̄generation sequencing technology was then used to sequence the genomes of passaged CMUT3G40 and the parental CMUT3G0. Results Passaged CMUT3G40 organisms became less de ̄pendent on centrifugation and more efficient for infecting HeLa cells in the absence of centrifugation compared to the paren ̄tal CMUT3G0.Comparative genomes analysis of CMUT3G40 and CMUT3G0 revealed that a G to C substitution at position 277313,resulting in a glutamine to glutamic acid amino acid change in the protein product of TC0237 ( 99. 7% in CMUT3G40 versus 0% in CMUT3G0 genomes) . Conclusion The TC0237Q117E missense mutation under in vitro pas ̄sage selection pressure can be attributed to an in vitro attachment enhancement phenotype of plasmid ̄free C. muridarum CMUT3 organisms.%目的:探讨传代选择对鼠衣原体质粒缺失株CMUT3菌株培养特性的影响及其相应机制。方法采用“无辅助感染”和“辅助感染”交替方式体外传代培养CMUT3菌株,而后观察传代菌株和亲代感染细胞时的吸附效率以及对离心因素的依赖性,并利用下一代测序技术对传代菌株CMUT3G40和亲代CMUT3G0进行全基因组测序分析。结果传代菌株CMUT3G40在感染HeLa细胞时对离心因素依赖性降低,吸附试验表明CMUT3G40菌株对细胞的吸附能力增强;比较基因组学分析结果表明 CMUT3G40菌株与亲代 CMUT3G0在 tc0237基因存在差异, TC0237Q117E错义突变出现于CMUT3G40

  15. Wafer scale oblique angle plasma etching

    Energy Technology Data Exchange (ETDEWEB)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  16. Phase shift reflectometry for wafer inspection

    Science.gov (United States)

    Peng, Kuang; Cao, Yiping; Li, Hongru; Sun, Jianfei; Bourgade, Thomas; Asundi, Anand Krishna

    2015-07-01

    In 3D measurement, specular surfaces can be reconstructed by phase shift reflectometry and the system configuration is simple. In this paper, a wafer is measured for industrial inspection to make sure the quality of the wafer by calibrating, phase unwrapping, slope calculation and integration. The profile result of the whole wafer can be reconstructed and it is a curve. As the height of the structures on the wafer is the target we are interested in, by fitting and subtracting the curve surface, the structures on the wafer can be observed on the flat surface. To confirm the quality farther, a part of the wafer is captured and zoomed in to be detected so that the difference between two structures can be observed better.

  17. A large-signal model for CMUT arrays with arbitrary membrane geometry operating in non-collapsed mode.

    Science.gov (United States)

    Satir, Sarp; Zahorian, Jaime; Degertekin, F Levent

    2013-11-01

    A large-signal, transient model has been developed to predict the output characteristics of a CMUT array operated in the non-collapse mode. The model is based on separation of the nonlinear electrostatic voltage-to-force relation and the linear acoustic array response. For modeling of linear acoustic radiation and crosstalk effects, the boundary element method is used. The stiffness matrix in the vibroacoustics calculations is obtained using static finite element analysis of a single membrane which can have arbitrary geometry and boundary conditions. A lumped modeling approach is used to reduce the order of the system for modeling the transient nonlinear electrostatic actuation. To accurately capture the dynamics of the non-uniform electrostatic force distribution over the CMUT electrode during large deflections, the membrane electrode is divided into patches shaped to match higher order membrane modes, each introducing a variable to the system model. This reduced order nonlinear lumped model is solved in the time domain using commercial software. The model has two linear blocks to calculate the displacement profile of the electrode patches and the output pressure for a given force distribution over the array. The force-to-array-displacement block uses the linear acoustic model, and the Rayleigh integral is evaluated to calculate the pressure at any field point. Using the model, the time-domain transmitted pressure can be simulated for different large drive signal configurations. The acoustic model is verified by comparison to harmonic FEA in vacuum and fluid for high- and low-aspect-ratio membranes as well as mass-loaded membranes. The overall software model is verified by comparison to transient 3-D finite element analysis and experimental results for different large drive signals, and an example for a phased array simulation is given.

  18. Anodic bonding using a hybrid electrode with a two-step bonding process

    Science.gov (United States)

    Wei, Luo; Jing, Xie; Yang, Zhang; Chaobo, Li; Yang, Xia

    2012-06-01

    A two-step bonding process using a novel hybrid electrode is presented. The effects of different electrodes on bonding time, bond strength and the bonded interface are analyzed. The anodic bonding is studied using a domestic bonding system, which carries out a detailed analysis of the integrity of the bonded interface and the bond strength measurement. With the aid of the hybrid electrode, a bubble-free anodic bonding process could be accomplished within 15-20 min, with a shear strength in excess of 10 MPa. These results show that the proposed method has a high degree of application value, including in most wafer-level MEMS packaging.

  19. Study of wafer pre-aligning approaches

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    Wafer pre-aligning system is an important component in IC manufacturing industry. A wafer prealigning platform with a CCD sensor is presented in this paper. The centering and notch detecting approaches are extended based on this platform. Least square circle fitting approach is adopted to calculate the center and radius of the wafer, and a formula for calculating the fitting error is derived. An approach called edge variation rate is also proposed to detect the range of wafer notch, and the fiducial is calculated by curve fitting approach. These approaches can improve the accuracy effectively as indicated by experiments.

  20. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  1. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  2. Small footprint wafer-level vacuum packaging using compressible gold sealing rings

    Science.gov (United States)

    Antelius, Mikael; Stemme, Göran; Niklaus, Frank

    2011-08-01

    A novel low-temperature wafer-level vacuum packaging process is presented. The process uses plastically deformed gold rings as sealing structures in combination with flux-free soldering to provide the bond force for a sealing wafer. This process enables the separation of the sealing and the bonding functions both spatially on the wafer and temporally in different process steps, which results in reduced areas for the sealing rings and prevents outgassing from the solder process in the cavity. This enables space savings and yields improvements. We show the experimental result of the hermetic sealing. The leak rate into the packages is determined, by measuring the package lid deformation over 10 months, to be lower than 3.5 × 10-13 mbar l s-1, which is suitable for most MEMS packages. The pressure inside the produced packages is measured to be lower than 10 mbar.

  3. Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

    1999-09-07

    We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

  4. Wettability investigating on the wet etching textured multicrystalline silicon wafer

    Science.gov (United States)

    Liu, Xiangju; Niu, Yuchao; Zhai, Tongguang; Ma, Yuying; Zhen, Yongtai; Ma, Xiaoyu; Gao, Ying

    2016-02-01

    In order to investigate the wettability properties of multicrystalline silicon (mc-Si), the different surface structures were fabricated on the as-cut p-type multi-wire slurry sawn mc-Si wafers, such as as-cut, polished and etched in various acid solutions. The contact angles and the XRD spectra of these samples were measured. It was noted that both the surface structures and the use of surfactant, such as Tween 80, made a stronger effect on wettability of the Si wafer. Due to the lipophilic groups of Tween 80 combined with the Si atoms while the hydrophilic groups of it were outward, a lipophilic surface of Si changed into a hydrophilic one and the rougher the surface, the stronger the hydrophily. Thus, it is feasible to add an appropriate surfactant into the etching solution during black-Si wafer fabrication for solar cells. In addition, different crystal plains of Si had different dangling bond density, so that their surface energies were different. A surface with higher surface energy could attract more water atoms and its wettability was better. However, the effect of crystal plain on the surface wettability was much weaker than surface morphology.

  5. Wafer-level assembly and sealing of a MEMS nanoreactor for in situ microscopy

    NARCIS (Netherlands)

    Mele, L.; Santagata, F.; Panraud, G.; Morana, B.; Tichelaar, F.D.; Creemer, J.F.; Sarro, P.M.

    2010-01-01

    This paper presents a new process for the fabrication of MEMS-based nanoreactors for in situ atomic-scale imaging of nanoparticles under relevant industrial conditions. The fabrication of the device is completed fully at wafer level in an ISO 5 clean room and it is based on silicon fusion bonding

  6. Preparation and Characterization of PZT Wafers

    Science.gov (United States)

    Seal, A.; Rao, B. S. S. Chandra; Kamath, S. V.; Sen, A.; Maiti, H. S.

    2008-07-01

    Piezoelectric materials have recently attracted a lot of attention for ultrasonic structural health monitoring (shm) in aerospace, defence and civilian sectors, where they can act as both actuators and sensors. Incidentally, piezoelectric materials in the form of wafers (pwas-piezoelectric wafer active sensor, approx. 5-10 mm square and 0.2-0.3 mm thickness) are inexpensive, non intrusive and non-resonant wide band devices that can be surface-mounted on existing structures, inserted between the layers of lap joints or embedded inside composite materials. The material of choice for piezoelectric wafers is lead zirconate titanate (PZT) of composition close to morphotropic phase boundary [pb(zr0.52 ti0.48)o3]. However, an excess pbo is normally added to pzt as a densification aid and also to make up for the lead loss during high temperature sintering. Hence, it is of paramount importance to know how the shift of the lead content from the morphotropic composition affects the piezoelectric and mechanical properties of the sintered wafers, keeping in view the importance of mechanical properties of wafers in shm. In the present study, we observed that with the increase in the lead content of the sintered wafers, the dielectric and piezoelectric constants decreased. However, the elastic modulus, hardness and fracture toughness of the wafers increased with increasing lead content in the composition. Hence, the lead content in the sintered wafers should be optimized to get acceptable piezoelectric and mechanical

  7. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  8. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... these issues and presents the development leading to applicable technological solutions. The via technology developed in this work enable effective utilization of the available surface area on both sides of the amplifier chip for redistribution as well as placement of passive components and external...... connections. A process for wafer level packaging and assembly of chips with vias is presented in this thesis. Discrete components, capacitors and resistors, are assembled on the backside of the amplifier chips by screen printing of solder paste, pick and place of components, and reflow soldering. Since...

  9. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  10. Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

    Science.gov (United States)

    Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

    2011-04-21

    A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

  11. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1995-01-01

    A technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for not only resist spinning and layer patterning but also for realization of bridges and cantilevers across deep grooves or holes. The technique contains a standard dry film

  12. Wafer-level manufacturing technology of glass microlenses

    Science.gov (United States)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  13. Nanofluidic chip for liquid TEM cell fabricated by parylene and silicon nitride direct bonding

    Science.gov (United States)

    Jang, Heejun; Kang, Il-Suk; Kim, Jihye; Kim, Jonghyun; Cha, Yun Jeong; Yoon, Dong Ki; Lee, Wonhee

    2017-09-01

    Despite the importance of nanofluidic transmission electron microscope (TEM) chips, a simple fabrication method has yet to be developed due to the difficulty of wafer bonding techniques using a nanoscale thick bonding layer. We present a simple and robust wafer scale bonding technique using parylene as a bonding layer. A nanoscale thick parylene layer was deposited on a silicon nitride (SiN) wafer and patterned to construct nanofluidic channels. The patterned parylene layer was directly bonded to another SiN wafer by thermal surface activation and bonding, with a bonding strength of ˜3 MPa. Fourier transform infrared spectroscopy showed that carbon-oxygen bonds were generated by thermal activation. We demonstrated TEM imaging of gold nanoparticles suspended in liquid using the fabricated nanofluidic chip.

  14. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    CERN Document Server

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  15. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  16. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  17. Silicon Wafer X-ray Mirror Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this one year research project, we propose to do the following four tasks;(1) Design the silicon wafer X-ray mirror demo unit and develop a ray-tracing code to...

  18. ISOTROPIC TEXTURING OF POLYCRYSTALLINE SILICON WAFERS

    Institute of Scientific and Technical Information of China (English)

    L. Wang; H. Shen; Y.F. Hu

    2005-01-01

    An isotropic etching technique of texturing silicon solar cells has been applied to polycrystalline silicon wafers with different acid concentrations. Optimal etching conditions have been determined by etching rate calculation, scanning electron microscope (SEM) image and reflectance measurement. The surface morphology of the textured wafers varies in accordance with the different etchant concentration which in turn leads to the dissimilarity of etching speed. Textured polycrystalline silicon wafer surfaces display randomly located etched pits which can reduce the surface reflection and enhance the light absorption. The special relationship between reflectivity and etching rate was studied. Reflectance measurements show that isotropic texturing is one of the suitable techniques for texturing polycrystalline silicon wafers and benefits solar cells performances.

  19. Silicon Wafer X-ray Mirror Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this one year research project, we propose to do the following four tasks; (1) Design the silicon wafer X-ray mirror demo unit and develop a ray-tracing code to...

  20. Modelling deformation and fracture in confectionery wafers

    Science.gov (United States)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  1. Development of ultra-low impedance Through-wafer Micro-vias

    Energy Technology Data Exchange (ETDEWEB)

    Finkbeiner, F.M. E-mail: fmf@lheapop.gsfc.nasa.gov; Adams, C.; Apodaca, E.; Chervenak, J.A.; Fischer, J.; Doan, N.; Li, M.J.; Stahle, C.K.; Brekosky, R.P.; Bandler, S.R.; Figueroa-Feliciano, E.; Lindeman, M.A.; Kelley, R.L.; Saab, T.; Talley, D.J

    2004-03-11

    Concurrent with our microcalorimeter array fabrication for Constellation-X technology development, we are developing ultra-low impedance Through-Wafer Micro-Vias (TWMV) as electrical interconnects for superconducting circuits. The TWMV will enable the electrical contacts of each detector to be routed to contacts on the backside of the array. There, they can be bump-bonded to a wiring fan-out board which interfaces with the front-end Superconducting Quantum Interference Device readout. We are concentrating our developmental efforts on ultra-low impedance copper and superconducting aluminum TWMV in 300-400 micron thick silicon wafers. For both schemes, a periodic pulse-reverse electroplating process is used to fill or coat micron-scale through-wafer holes of aspect ratios up to 20. Here we discuss the design, fabrication process, and recent electro-mechanical test results of Al and Cu TWMV at room and cryogenic temperatures.

  2. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    Science.gov (United States)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  3. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  4. Influence of Immersion Lithography on Wafer Edge Defectivity

    OpenAIRE

    Jami, K.; Pollentier, I.; Vedula, S; Blumenstock, G

    2010-01-01

    In this paper, we investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to inspection of the flat top part of the wafer edge due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. Our study used a new automated edge inspection system that provides full wafer edge imaging and automatic defect classification. The work revealed several key challenges to controlling wafer edge-...

  5. Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

    Directory of Open Access Journals (Sweden)

    Pooja Batra

    2014-05-01

    Full Text Available For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs, wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS embedded DRAM (EDRAM having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation.

  6. Development of wafers with lowered glycemic index

    Directory of Open Access Journals (Sweden)

    N. N. Popova

    2016-01-01

    Full Text Available The negative impact on an organism is made by lack of culture of food of the population and low physical activity. It leads to violations of carbohydrate and lipidic exchange, development of obesity, diabetes, cardiovascular and other diseases. Relevance of development of foodstuff, in particular – the confectionery promoting decrease in risk of developing of such pathologies is proved. A research objective – development of a compounding of wafers with the lowered glycemic index. As an object of a research the wafers baked in house conditions are chosen. In work various characteristics are analysed (hygroscopicity, a cariogenicity sweet degree, power value, a glicemic index and a glycemic response the sweetening substances, the choice of fructose as sugar substitute for production of wafers with the lowered glycemic index is reasonable. By optimization of a compounding of wafers the amount of sugar was replaced with amount of sweetener, equivalent on sweet. As a result of predesigns the interval of a variation of amount of the fructose entered into a compounding of wafers is established. Further assessment of the indicators of quality forming consumer demand of products – appearance, taste, a smell, existence of a crunch is carried out. Humidity of the received wafers after their production and in the course of storage is also investigated. Decrease in a glycemic index was fixed by amount of glucose in blood. Its measurements saw by means of the glucose meter "on an empty stomach" and after the use of wafers to a complete recovery of level of sugar in blood. The confectionery made on the optimized compounding practically doesn't differ on caloric content from a control sample, and glucose level in blood after their use on about 20% below.

  7. Intra-lot wafer by wafer overlay control using integrated and standalone metrology combined sampling

    Science.gov (United States)

    Choi, Young Sin; Nam, Young Sun; Lee, Dong Han; Lee, Jae Il; Kang, Young Seog; Jang, Se Yeon; Kong, Jeong Heung

    2016-03-01

    As overlay margin is getting tighter, traditional overlay correction method is not enough to secure more overlay margin without extended correction potential on lithography tool. Timely, the lithography tool has a capability of wafer to wafer correction. From these well-timed industry's preparations, the uncorrected overlay error from current sampling in a lot could be corrected for yield enhancement. In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer's behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.

  8. Full-field wafer warpage measurement technique

    Science.gov (United States)

    Hsieh, H. L.; Lee, J. Y.; Huang, Y. G.; Liang, A. J.; Sun, B. Y.

    2017-06-01

    An innovative moiré technique for full-field wafer warpage measurement is proposed in this study. The wafer warpage measurement technique is developed based on moiré method, Talbot effect, scanning profiling method, stroboscopic, instantaneous phase-shift method, as well as four-step phase shift method, high resolution, high stability and full-field measurement capabilities can be easily achieved. According to the proposed full-field optical configuration, a laser beam is expanded into a collimated beam with a 2-inch diameter and projected onto the wafer surface. The beam is reflected by the wafer surface and forms a moiré fringe image after passing two circular gratings, which is then focused and captured on a CCD camera for computation. The corresponding moiré fringes reflected from the wafer surface are obtained by overlapping the images of the measuring grating and the reference grating. The moiré fringes will shift when wafer warpage occurs. The phase of the moiré fringes will change proportionally to the degree of warpage in the wafer, which can be measured by detecting variations in the phase shift of the moiré fringes in each detection points on the surface of the entire wafer. The phase shift variations of each detection points can be calculated via the instantaneous phase-shift method and the four-step phase-shift method. By adding up the phase shift variations of each detection points along the radii of the circular gratings, the warpage value and surface topography of the wafer can be obtained. Experiments show that the proposed method is capable of obtaining test results similar to that of a commercial sensor, as well as performing accurate measurements under high speed rotation of 1500rpm. As compared to current warpage measurement methods such as the beam optical method, confocal microscopy, laser interferometry, shadow moiré method, and structured light method, this proposed technique has the advantage of full-field measurement, high

  9. Wafer-fused semiconductor radiation detector

    Science.gov (United States)

    Lee, Edwin Y.; James, Ralph B.

    2002-01-01

    Wafer-fused semiconductor radiation detector useful for gamma-ray and x-ray spectrometers and imaging systems. The detector is fabricated using wafer fusion to insert an electrically conductive grid, typically comprising a metal, between two solid semiconductor pieces, one having a cathode (negative electrode) and the other having an anode (positive electrode). The wafer fused semiconductor radiation detector functions like the commonly used Frisch grid radiation detector, in which an electrically conductive grid is inserted in high vacuum between the cathode and the anode. The wafer-fused semiconductor radiation detector can be fabricated using the same or two different semiconductor materials of different sizes and of the same or different thicknesses; and it may utilize a wide range of metals, or other electrically conducting materials, to form the grid, to optimize the detector performance, without being constrained by structural dissimilarity of the individual parts. The wafer-fused detector is basically formed, for example, by etching spaced grooves across one end of one of two pieces of semiconductor materials, partially filling the grooves with a selected electrical conductor which forms a grid electrode, and then fusing the grooved end of the one semiconductor piece to an end of the other semiconductor piece with a cathode and an anode being formed on opposite ends of the semiconductor pieces.

  10. Wafer-level vacuum packaging for an optical readout bi-material cantilever infrared FPA

    Science.gov (United States)

    Li, Shuyu; Zhou, Xiaoxiong; Yu, Xiaomei

    2013-12-01

    In this paper, we report the design and fabrication of an uncooled infrared (IR) focal plane array (FPA) on quartz substrate and the wafer-level vacuum packaging for the IR FPA in view of an optical readout method. This FPA is composed of bi-material cantilever array which fabricated by the Micro-Electro Mechanical System (MEMS) technology, and the wafer-level packaging of the IR FPA is realized based on AuSn solder bonding technique. The interface of soldering is observed by scan electron microscope (SEM), which indicates that bonding interface is smooth and with no bubbles. The air leakage rate of packaged FPA is measured to be 1.3×10-9 atm·cc/s.

  11. On-wafer high temperature characterization system

    Science.gov (United States)

    Teodorescu, L.; ǎghici, F., Dr; Rusu, I.; Brezeanu, G.

    2016-12-01

    In this work a on-wafer high temperature characterization system for wide bandgap semiconductor devices and circuits has been designed, implemented and tested. The proposed system can perform the wafer temperature adjustment in a large domain, from the room temperature up to 3000C with a resolution better than +/-0.50C. In order to obtain both low-noise measurements and low EMI, the heating element of the wafer chuck is supplied in two ways: one is from a DC linear power supply connected to the mains electricity, another one is from a second DC unit powered by batteries. An original temperature control algorithm, different from classical PID, is used to modify the power applied to the chuck.

  12. Adhesive disbond detection using piezoelectric wafer active sensors

    Science.gov (United States)

    Roth, William; Giurgiutiu, Victor

    2015-04-01

    The aerospace industry continues to increase the use of adhesives for structural bonding due to the increased joint efficiency (reduced weight), even distribution of the load path and decreases in stress concentrations. However, the limited techniques for verifying the strength of adhesive bonds has reduced its use on primary structures and requires an intensive inspection schedule. This paper discusses a potential structural health monitoring (SHM) technique for the detection of disbonds through the in situ inspection of adhesive joints. This is achieved through the use of piezoelectric wafer active sensors (PWAS), thin unobtrusive sensors which are permanently bonded to the aircraft structure. The detection method discussed in this study is electromechanical impedance spectroscopy (EMIS), a local vibration method. This method detects disbonds from the change in the mechanical impedance of the structure surrounding the disbond. This paper will discuss how predictive modeling can provide valuable insight into the inspection method, and provide better results than empirical methods alone. The inspection scheme was evaluated using the finite element method, and the results were verified experimentally using a large aluminum test article, and included both pristine and disbond coupons.

  13. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

    OpenAIRE

    Bo Xie; Yonghao Xing; Yanshuang Wang; Jian Chen; Deyong Chen; Junbo Wang

    2015-01-01

    This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free ...

  14. Wafer level 3-D ICs process technology

    CERN Document Server

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  15. Wafer-scale graphene integrated circuit.

    Science.gov (United States)

    Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

    2011-06-10

    A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

  16. Removal of surface oxide from electrical test (E-test) pads using an argon sputter etch procedure to recover TAB wafers

    Science.gov (United States)

    Petersen-Buchheit, Tina A.; Johannes, William R.; Patel, Divyesh N.; Coleman, Jeffrey F.

    1997-09-01

    In Intel's manufacturing flow, discrete devices in the scribeline of wafers are tested (E-Test structures) to determine if they meet specifications for reliability and functionality. The wafers are then sorted to determine die functionality. Probing equipment is used to measure E-test structures by way of aluminum pads (E-Test pads) which make contact with devices in the scribeline. Tape automated bonding packaging requires additional processing (compared to Wire Bonded devices) to plate gold bumps on to the die bond pads. The gold bumps are not plated on the E-Test pads but they receive additional processing which may create an insulating surface layer, such as aluminum oxide, preventing the acquisition of reliability information from the wafer tested. If reliability data is not available, wafers are discarded even though the die present on the wafer may be functional. An argon sputter etch procedure is suggested to remove the problematic insulating oxide and recover wafers. The major concerns associated with using a sputter etch recovery procedure include: redistribution of gold across the surface of the wafer; gate charging due to the sputter process; polyimide (PI) surface roughness and thickness issues; encapsulation adhesion issues; and elevated burn-in fallout. This paper will discuss the procedure used to remove surface oxide and experiments to determine if recovery was successful. Process characterization which encompassed etch time and RF power were used to optimize the recovery procedure for reliability purposes. The experimental parameters evaluated include: E-Test parametric data to compare recovered wafers to baseline wafers; threshold voltage data; pad to pad surface leakage due to gold redistribution; SEM cross sections and profilometry to ensure PI integrity; and C-mode Scanning Acoustic Microscopy to address encapsulation adhesion concerns.

  17. InGaAs-OI Substrate Fabrication on a 300 mm Wafer

    Directory of Open Access Journals (Sweden)

    Sebastien Sollier

    2016-09-01

    Full Text Available In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs wafer on insulator (InGaAs-OI substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM, scanning acoustic microscopy (SAM, and HR-XRD, to insure the crystalline quality of the post transferred layer.

  18. Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel; Frech, J.; Heschel, M.

    2003-01-01

    A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr....../Au, and electroless deposition of Cu. A novel characteristic of the process is the use of a metal etch stop layer providing perfect control of the etch profile of the wafer through-holes in combination with a remarkably improved etch uniformity across the wafer. Excellent through-hole insulation is provided through...

  19. Modeling radiative properties of nanoscale patterned wafers

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    Temperature nonuniformity in rapid thermal processing of wafers is a critical problem facing the semiconductor industry. One cause of the problem is the nonuniform absorption of thermal radiation in patterned wafers where the optical properties vary across the wafer surface. This paper presents a parametric study of the radiative properties of patterned wafers, considering the effect of temperature, wavelength, and polarization. The finite-difference time-domain (FDTD) method is employed to examine the effect of various trench sizes on the radiative properties via numerically solving the Maxwell equations. The effective medium theory (EMT) is also used to help explain the absorptance prediction. The results show that in the cases with trench size variation, the resonance cavity effect may increase the absorptance as the trench width increases. And in the cases with trench size increasing at several different filling ratios, the absorptance does not change much at small filling ratio. The effects of the resonant cavity, diffraction, wave interferences on the spectral-directional absorptance were also discussed. This work is of great importance for optimization of advanced annealing techniques in semiconductor manufacturing.

  20. Solar wafer market in a crisis; Ausgeduennt

    Energy Technology Data Exchange (ETDEWEB)

    Heup, Juergen

    2010-07-15

    After a boom period in which producers of silicon wafers were hailed for reducing the cost of solar modules, the market is now undergoing a period of stress, and some producers were unable to continue. The contribution presents an example to show how the industry can be saved. (orig.)

  1. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    A major cost in semiconductor manufacturing is the generation of photo masks which are used to produce the dies. When producing smaller series of chips it can be advantageous to build a shuttle mask (or multi-project wafer) to share the startup costs by placing different dies on the same mask...

  2. Wafer-Scale Integration of Systolic Arrays,

    Science.gov (United States)

    1985-10-01

    wafer-scale system, however, all the nearest neighbors of a processor may be dead, and thus the prime advantage of adopting a systolic array...work, however. To the best of our knowledge, the only result of a similar nature is due to Erdos and Renyi 15] who showed that most graphs with N

  3. 100% foundry compatible packaging and full wafer release and die separation technique for surface micromachined devices

    Energy Technology Data Exchange (ETDEWEB)

    OLIVER,ANDREW D.; MATZKE,CAROLYN M.

    2000-04-06

    A completely foundry compatible chip-scale package for surface micromachines has been successfully demonstrated. A pyrex (Corning 7740) glass cover is placed over the released surface micromachined die and anodically bonded to a planarized polysilicon bonding ring. Electrical feedthroughs for the surface micromachine pass underneath the polysilicon sealing ring. The package has been found to be hermetic with a leak rate of less than 5 x 10{sup {minus}8} atm cm{sup {minus}3}/s. This technology has applications in the areas of hermetic encapsulation and wafer level release and die separation.

  4. An electret-based energy harvesting device with a wafer-level fabrication process

    DEFF Research Database (Denmark)

    Crovetto, Andrea; Wang, Fei; Hansen, Ole

    2013-01-01

    This paper presents a MEMS energy harvesting device which is able to generate power from two perpendicular ambient vibration directions. A CYTOP polymer is used both as the electret material for electrostatic transduction and as a bonding interface for low-temperature wafer bonding. The device...... is also discussed. With a final chip size of about 1 cm2, a power output of 32.5 nW is successfully harvested with an external load of 17 MΩ, when a harmonic vibration source with an RMS acceleration amplitude of 0.03 g (∼0.3 m s−2) and a resonant frequency of 179 Hz is applied. These results can...

  5. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  6. Laser-induced subsurface modification of silicon wafers

    NARCIS (Netherlands)

    Verburg, P.C.

    2015-01-01

    Wafer dicing is the technology to separate wafers into divided components known as dies. New developments in the semiconductor industry, such as die stacking and the development of microelectromechanical systems, present significant challenges to the dicing process. A promising wafer dicing method

  7. Anodically bonded submicron microfluidic chambers.

    Science.gov (United States)

    Dimov, S; Bennett, R G; Córcoles, A; Levitin, L V; Ilic, B; Verbridge, S S; Saunders, J; Casey, A; Parpia, J M

    2010-01-01

    We demonstrate the use of anodic bonding to fabricate cells with characteristic size as large as 7 x 10 mm(2), with height of approximately 640 nm, and without any internal support structure. The cells were fabricated from Hoya SD-2 glass and silicon wafers, each with 3 mm thickness to maintain dimensional stability under internal pressure. Bonding was carried out at 350 degrees C and 450 V with an electrode structure that excluded the electric field from the open region. We detail fabrication and characterization steps and also discuss the design of the fill line for access to the cavity.

  8. Anodically bonded submicron microfluidic chambers

    Science.gov (United States)

    Dimov, S.; Bennett, R. G.; Córcoles, A.; Levitin, L. V.; Ilic, B.; Verbridge, S. S.; Saunders, J.; Casey, A.; Parpia, J. M.

    2010-01-01

    We demonstrate the use of anodic bonding to fabricate cells with characteristic size as large as 7×10 mm2, with height of ≈640 nm, and without any internal support structure. The cells were fabricated from Hoya SD-2 glass and silicon wafers, each with 3 mm thickness to maintain dimensional stability under internal pressure. Bonding was carried out at 350 °C and 450 V with an electrode structure that excluded the electric field from the open region. We detail fabrication and characterization steps and also discuss the design of the fill line for access to the cavity.

  9. Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

  10. Strength and leak testing of plasma activated bonded interfaces

    DEFF Research Database (Denmark)

    Visser, M.M.; Weichel, Steen; Reus, Roger De

    2002-01-01

    Bond strength and hermeticity of plasma activated bonded (PAB) Si-Si interfaces are reported. Bonding of 100 mm Si(1 0 0) wafers was performed. An average bond strength of 9.0+/-3.9 MPa was achieved without performing any annealing steps. Cavities bonded in vacuum were found to be hermetic based...... on detection of changes in membrane deflections. The detection limit for leak was 8E-13 mbar l/s. For comparison, strength and leak tests were also performed with regular fusion bonded wafers annealed at 1100 degreesC. The PAB was found to withstand post-processing steps such as RCA cleaning, 24 h in de......-ionised water (DIW), 24 h in 2.5% HF, 24 h in acetone and 60 s in a resist developer. By analysing the thin silicon oxide present on the surfaces to be bonded with optical methods, the influence of pre-cleaning and activation process parameters was investigated....

  11. An X-ray diffraction study of direct-bonded silicon interfaces

    DEFF Research Database (Denmark)

    Howes, P.B.; Benamara, M.; Grey, F.

    1998-01-01

    Semiconductor wafer bonding techniques have been used to create a giant twist grain boundary from two Si(001) wafers. We show, using X-ray diffraction measurements that after annealing the interface forms a highly ordered superstructure with relaxations extending to many layers into the crystals...

  12. Thermal modeling of wafer-based precision glass molding process

    Science.gov (United States)

    Hu, Yang; Shen, Lianguan; Zhou, Jian; Li, Mujun

    2016-10-01

    Wafer based precision glass optics manufacturing has been an innovative approach for combining high accuracy with mass production. However, due to the small ratio of thickness and diameter of the glass wafer, deformation and residual stress would be induced for the nonuniform temperature distribution in the glass wafer after molding. Therefore, thermal modelling of the heating system in the wafer based precision glass molding (PGM) process is of great importance in optimizing the heating system and the technique of the process. The current paper deals with a transient thermal modelling of a self-developed heating system for wafer based PGM process. First, in order to investigate the effect of radiation from the surface and interior of the glass wafer, the thermal modeling is simulated with a discrete ordinates radiation model in the CFD software FLUENT. Temperature distribution of the glass wafer obtained from the simulations is then used to evaluate the performance of heating system and investigate some importance parameters in the model, such as interior and surface radiation in glass wafer, thermal contact conductance between glass wafer and molds, thickness to diameter ratio of glass wafer. Finally, structure modification in the molding chamber is raised to decrease the temperature gradient in the glass wafer and the effect is significant.

  13. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  14. Wafer level test solutions for IR sensors

    Science.gov (United States)

    Giessmann, Sebastian; Werner, Frank-Michael

    2014-05-01

    Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

  15. Wafer weak point detection based on aerial images or WLCD

    Science.gov (United States)

    Ning, Guoxiang; Philipp, Peter; Litt, Lloyd C.; Ackmann, Paul; Crell, Christian; Chen, Norman

    2015-10-01

    Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

  16. Fusion bonding of silicon nitride surfaces

    DEFF Research Database (Denmark)

    Reck, Kasper; Østergaard, Christian; Thomsen, Erik Vilain

    2011-01-01

    While silicon nitride surfaces are widely used in many micro electrical mechanical system devices, e.g. for chemical passivation, electrical isolation or environmental protection, studies on fusion bonding of two silicon nitride surfaces (Si3N4–Si3N4 bonding) are very few and highly application...... specific. Often fusion bonding of silicon nitride surfaces to silicon or silicon dioxide to silicon surfaces is preferred, though Si3N4–Si3N4 bonding is indeed possible and practical for many devices as will be shown in this paper. We present an overview of existing knowledge on Si3N4–Si3N4 bonding and new...... results on bonding of thin and thick Si3N4 layers. The new results include high temperature bonding without any pretreatment, along with improved bonding ability achieved by thermal oxidation and chemical pretreatment. The bonded wafers include both unprocessed and processed wafers with a total silicon...

  17. Super-flat wafer chucks: from simulation and testing to a complete 300mm wafer chuck with low wafer deformation between pins

    Science.gov (United States)

    Müller, Renate; Afanasiev, Kanstantin; Ziemann, Marcel; Schmidt, Volker

    2014-04-01

    Berliner Glas is a privately owned, mid-sized manufacturer of precision opto-mechanics in Germany. One specialty of Berliner Glas is the design and production of high performance vacuum and electrostatic wafer chucks. Driven by the need of lithography and inspection for smaller overlay values, we pursue the production of an ideally flat wafer chuck. An ideally flat wafer chuck holds a wafer with a completely flat backside and without lateral distortion within the wafer surface. Key parameters in influencing the wafer chucks effective flatness are thermal performance and thermal management, roughness of the surface, choice of materials and the contact area between wafer and wafer chuck. In this presentation we would like to focus on the contact area. Usually this is decreased as much as possible to avoid sticking effects and the chance of trapped particles between the chuck surface and the backside of the wafer. This can be realized with a pin structure on the chuck surface. Making the pins smaller and moving pins further apart from each other makes the contact area ever smaller but also adds new challenges to achieve a flat and undistorted wafer on the chuck. We would like to address methods of designing and evaluating such a pin structure. This involves not only the capability to simulate the ideal pattern of pins on the chuck's surface, for which we will present 2D and 3D simulation results. As well, we would like to share first results of our functional models. Finally, measurement capability has to be ensured, which means improving and further development of Fizeau flatness test interferometers.

  18. Intermetallic Compound Formation Mechanisms for Cu-Sn Solid-Liquid Interdiffusion Bonding

    Science.gov (United States)

    Liu, H.; Wang, K.; Aasmundtveit, K. E.; Hoivik, N.

    2012-09-01

    Cu-Sn solid-liquid interdiffusion (SLID) bonding is an evolving technique for wafer-level packaging which features robust, fine pitch and high temperature tolerance. The mechanisms of Cu-Sn SLID bonding for wafer-level bonding and three-dimensional (3-D) packaging applications have been studied by analyzing the microstructure evolution of Cu-Sn intermetallic compounds (IMCs) at elevated temperature up to 400°C. The bonding time required to achieve a single IMC phase (Cu3Sn) in the final interconnects was estimated according to the parabolic growth law with consideration of defect-induced deviation. The effect of predominantly Cu metal grain size on the Cu-Sn interdiffusion rate is discussed. The temperature versus time profile (ramp rate) is critical to control the morphology of scallops in the IMC. A low temperature ramp rate before reaching the bonding temperature is believed to be favorable in a SLID wafer-level bonding process.

  19. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'Brien, Deirdre

    2012-02-01

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  20. SHAPE BIFURCATION OF AN ELASTIC WAFER DUE TO SURFACE STRESS

    Institute of Scientific and Technical Information of China (English)

    闫琨; 何陵辉; 刘人怀

    2003-01-01

    A geometrically nonlinear analysis was proposed for the deformation of a freestanding elastically isotropic wafer caused by the surface stress change on one surface. Thelink between the curvature and the change in surface stress was obtained analytically fromenergetic consideration. In contrast to the existing linear analysis, a remarkableconsequence is that, when the wafer is very thin or the surface stress difference between thetwo major surfaces is large enough, the shape of the wafer will bifurcate.

  1. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'brien, Deirdre

    2010-12-15

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  2. Electrochemical behaviors of silicon wafers in silica slurry

    Institute of Scientific and Technical Information of China (English)

    Xiaolan Song; Haiping Yang; Xunda Shi; Xi He; Guanzhou Qiu

    2008-01-01

    The electrochemical behaviors of n-type silicon wafers in silica-based slurry were investigated, and the influences of the pH value and solid content of the slurry on the corrosion of silicon wafers were studied by using electrochemical DC polarization and AC impedance techniques. The results revealed that these factors affected the corrosion behaviors of silicon wafers to different degrees and had their suitable parameters that made the maximum corrosion rate of the wafers. The corrosion potential of (100) surface was lower than that of (111), whereas the current density of (100) was much higher than that of (111).

  3. Review. Industrial silicon wafer solar cells. Status and trends

    Energy Technology Data Exchange (ETDEWEB)

    Aberle, Armin G.; Boreland, Matthew B.; Hoex, Bram; Mueller, Thomas [National Univ. of Singapore (Singapore). Solar Energy Research Institute of Singapore (SERIS)

    2012-11-01

    Crystalline silicon solar cells dominate today's global photovoltaic (PV) market. This paper presents the status and trends of the most important industrial silicon wafer solar cells, ranging from standard p-type homojunction cells to heterojunction cells on n-type wafers. Owing to ongoing technological innovations such as improved surface passivation and the use of increasingly thinner wafers, the trend towards higher cell efficiencies and lower dollar/watt costs is expected to continue during the next 10 years, making silicon wafer based PV modules a moving target for any competing PV technology. (orig.)

  4. Mask qualification strategies in a wafer fab

    Science.gov (United States)

    Jaehnert, Carmen; Kunowski, Angela

    2007-02-01

    Having consistent high quality photo masks is one of the key factors in lithography in the wafer fab. Combined with stable exposure- and resist processes, it ensures yield increases in production and fast learning cycles for technology development and design evaluation. Preventive controlling of incoming masks and quality monitoring while using the mask in production is essential for the fab to avoid yield loss or technical problems caused by mask issues, which eventually result in delivery problems to the customer. In this paper an overview of the procedures used for mask qualification and production release, for both logic and DRAM, at Infineon Dresden is presented. Incoming qualification procedures, such as specification checks, incoming inspection, and inline litho process window evaluation, are described here. Pinching and electrical tests, including compatibility tests for mask copies for high volume products on optimized litho processes, are also explained. To avoid mask degradation over lifetime, re-inspection checks are done for re-qualification while using the mask in production. The necessity of mask incoming inspection and re-qualification, due to the repeater printing from either the processing defects of the original mask or degrading defects of being used in the fab (i.e. haze, ESD, and moving particles, etc.), is demonstrated. The need and impact of tight mask specifications, such as CD uniformity signatures and corresponding electrical results, are shown with examples of mask-wafer CD correlation.

  5. Characterization of MEMS-on-tube assembly: reflow bonding of borosilicate glass (Duran ®) tubes to silicon substrates

    NARCIS (Netherlands)

    Mogulkoc, B.; Jansen, H.V.; Berenschot, J.W.; Brake, ter H.J.M.; Knowles, K.M.; Elwenspoek, M.C.

    2009-01-01

    Reflow bonding of borosilicate glass tubes to silicon wafers is a technology which has significant potential for microfluidic applications. The borosilicate glass tubes are designed to be used as an interface and package for wafer-level microfluidic devices. The strength of the resulting package has

  6. Use of nanoporous columnar thin film in the wafer-level packaging of MEMS devices

    Science.gov (United States)

    Lee, Byung-Kee; Choi, Dong-Hoon; Yoon, Jun-Bo

    2010-04-01

    This paper presents a new packaging technology that uses a nanoporous columnar thin film to seal microelectromechanical system (MEMS) devices at the wafer level. In the proposed packaging process, the processing temperature is 350 °C. The process is relatively inexpensive compared to wafer level packaging processes, because the wafer-bonding step is eliminated and the die size is shrunk. In the suggested approach, a sputtered columnar thin film at room temperature forms vertical nanopores as etch holes, and an air cavity is formed by the removal of a sacrificial layer through the nanopores in the columnar membrane. Subsequent hermetic vacuum packaging of the cavity is achieved by depositing thin films over the membrane under low pressure. The hermeticity of the packaging was verified by using an optical surface morphology microscope to measure the deflection change of the sealing membrane before and after breaking of the vacuum through an interconnected membrane. The long-term hermeticity was monitored by measuring the maximum central deflection of the PECVD sealing layer over a period of 170 days. The precise pressure (0.7 Torr) and short-term (30 days) pressure change inside the cavity were measured by encapsulated Ni Pirani gauges, representing packaged freestanding MEMS devices.

  7. FY1995 study of perfect-closed ULSI manufacturing system for future large-diameter wafer processing; 1995 nendo jisedai daikokei wafer taio kanzen closed ULSI seizo sochi system no kenkyu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-05-01

    The purpose of this study is to develop advanced processing technologies to fabricate ultra-large-scale-integrated circuit on large-diameter wafers with high-precision and no-fluctuations at low temperatures. We develop the plasma process technologies to generate high-density uniform plasma with high-controllability to realize very precise manufacturing and low-temperature processing, and technologies for the high-performance process apparatus in which wafer surface is never exposed to atmosphere and therefore ultraclean wafer surface in atomic level are always maintained and molecules and ions react on the wafer surface in perfect accordance with reaction theories. We have developed a plasma process equipment using RLSA (Radial Line Slot Antenna) for formations of high-quality thin films. As a result, high-density uniform plasma has been successfully produced. The kinetic energy of bombarding ions onto the semiconductor substrate surface can be reduced to 7eV in this microwave plasma. Therefore high-quality thin films without any damages can be successfully formed. Next, we have developed magnetron plasma equipment with dipole-ring magnet for deep sub-micron etching. It was revealed that deviation of the plasma due to E x B drifts of electrons was perfectly improved by applying RF to an upper ring electrode. It was also revealed that to realize a closed manufacturing system, in which the wafers are transported in an ultra clean N{sub 2} environment and the wafer surface are never exposed to atmosphere, is essential for the deep sub-micron semiconductor manufacturing with high-reliability. Additionally, very fine-structure and bonding state of Si (100) surface which are terminated by hydrogen or fluorine, chorine was made clear by calculations using quantum chemistry under the three-dimensional periodic boundary condition. (NEDO)

  8. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  9. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  10. Analysis of wafer heating in 14nm DUV layers

    Science.gov (United States)

    Subramany, Lokesh; Chung, Woong Jae; Samudrala, Pavan; Gao, Haiyong; Aung, Nyan; Gomez, Juan Manuel; Minghetti, Blandine; Lee, Shawn

    2016-03-01

    To further shrink the contact and trench dimensions, Negative Tone Development (NTD) has become the de facto process at these layers. The NTD process uses a positive tone resist and an organic solvent-based negative tone developer which leads to improved image contrast, larger process window and smaller Mask Error Enhancement Factor (MEEF)[1]. The NTD masks have high transmission values leading to lens heating and as observed here wafer heating as well. Both lens and wafer heating will contribute to overlay error, however the effects of lens heating can be mitigated by applying lens heating corrections while no such corrections exist for wafer heating yet. Although the magnitude of overlay error due to wafer heating is low relative to lens heating; ever tightening overlay requirements imply that the distortions due to wafer heating will quickly become a significant part of the overlay budget. In this work the effects, analysis and observations of wafer heating on contact and metal layers of the 14nm node are presented. On product wafers it manifests as a difference in the scan up and scan down signatures between layers. An experiment to further understand wafer heating is performed with a test reticle that is used to monitor scanner performance.

  11. Wafer hot spot identification through advanced photomask characterization techniques

    Science.gov (United States)

    Choi, Yohan; Green, Michael; McMurran, Jeff; Ham, Young; Lin, Howard; Lan, Andy; Yang, Richer; Lung, Mike

    2016-10-01

    As device manufacturers progress through advanced technology nodes, limitations in standard 1-dimensional (1D) mask Critical Dimension (CD) metrics are becoming apparent. Historically, 1D metrics such as Mean to Target (MTT) and CD Uniformity (CDU) have been adequate for end users to evaluate and predict the mask impact on the wafer process. However, the wafer lithographer's process margin is shrinking at advanced nodes to a point that the classical mask CD metrics are no longer adequate to gauge the mask contribution to wafer process error. For example, wafer CDU error at advanced nodes is impacted by mask factors such as 3-dimensional (3D) effects and mask pattern fidelity on subresolution assist features (SRAFs) used in Optical Proximity Correction (OPC) models of ever-increasing complexity. These items are not quantifiable with the 1D metrology techniques of today. Likewise, the mask maker needs advanced characterization methods in order to optimize the mask process to meet the wafer lithographer's needs. These advanced characterization metrics are what is needed to harmonize mask and wafer processes for enhanced wafer hot spot analysis. In this paper, we study advanced mask pattern characterization techniques and their correlation with modeled wafer performance.

  12. Development of a novel plasma scanning technique for high-quality anodic bonding

    Science.gov (United States)

    Wu, Jim-Wei; Yang, Chii-Rong; Huang, Che-Yi

    2016-04-01

    Anodic bonding is a type of nonintermediate wafer bonding technique that has been widely used in microelectromechanical systems for sealing devices or assembling microstructures. However, the conventional anodic bonding method has a limitation. The specimens being bonded must typically be in contact with the anode and cathode electrodes during the bonding process. In general, the initial bonding position corresponds to the contact area of the two electrodes; subsequently, the bonded region gradually extends to cover the entire target region. Nevertheless, the traditional diffuse bonding method provides limited bonding efficiency in industrial applications. Therefore, this paper proposes a novel plasma bonding technique for 2D scanning anodic bonding. In this technique, the plasma is positioned to simultaneously heat and bond specimens. We conducted an experiment that entailed bonding 4-inch silicon/glass wafers by using N2 plasma. The results revealed that an almost bubble-free bonded interface and an average bonding strength exceeding 37 MPa were achieved for a bonding time of 15 min 53 s, bonding voltage of 2 kV, noncontact distance (between the cathode electrode and the bonding specimens) of 3 mm, variable raster scan path, scan speed of 3 mm s-1, and continuous scan steps of 2.5 mm in the x- and y-axes. A comprehensive series of experiments were performed to validate the bonding performance of the proposed technique.

  13. Infrared spectroscopy of wafer-scale graphene.

    Science.gov (United States)

    Yan, Hugen; Xia, Fengnian; Zhu, Wenjuan; Freitag, Marcus; Dimitrakopoulos, Christos; Bol, Ageeth A; Tulevski, George; Avouris, Phaedon

    2011-12-27

    We report spectroscopy results from the mid- to far-infrared on wafer-scale graphene, grown either epitaxially on silicon carbide or by chemical vapor deposition. The free carrier absorption (Drude peak) is simultaneously obtained with the universal optical conductivity (due to interband transitions) and the wavelength at which Pauli blocking occurs due to band filling. From these, the graphene layer number, doping level, sheet resistivity, carrier mobility, and scattering rate can be inferred. The mid-IR absorption of epitaxial two-layer graphene shows a less pronounced peak at 0.37 ± 0.02 eV compared to that in exfoliated bilayer graphene. In heavily chemically doped single-layer graphene, a record high transmission reduction due to free carriers approaching 40% at 250 μm (40 cm(-1)) is measured in this atomically thin material, supporting the great potential of graphene in far-infrared and terahertz optoelectronics.

  14. Semiconductor industry wafer fab exhaust management

    CERN Document Server

    Sherer, Michael J

    2005-01-01

    Given the myriad exhaust compounds and the corresponding problems that they can pose in an exhaust management system, the proper choice of such systems is a complex task. Presenting the fundamentals, technical details, and general solutions to real-world problems, Semiconductor Industry: Wafer Fab Exhaust Management offers practical guidance on selecting an appropriate system for a given application. Using examples that provide a clear understanding of the concepts discussed, Sherer covers facility layout, support facilities operations, and semiconductor process equipment, followed by exhaust types and challenges. He reviews exhaust point-of-use devices and exhaust line requirements needed between process equipment and the centralized exhaust system. The book includes information on wet scrubbers for a centralized acid exhaust system and a centralized ammonia exhaust system and on centralized equipment to control volatile organic compounds. It concludes with a chapter devoted to emergency releases and a separ...

  15. Laser Enhanced Hydrogen Passivation of Silicon Wafers

    Directory of Open Access Journals (Sweden)

    Lihui Song

    2015-01-01

    Full Text Available The application of lasers to enable advanced hydrogenation processes with charge state control is explored. Localised hydrogenation is realised through the use of lasers to achieve localised illumination and heating of the silicon material and hence spatially control the hydrogenation process. Improvements in minority carrier lifetime are confirmed in the laser hydrogenated regions using photoluminescence (PL imaging. However with inappropriate laser settings a localised reduction in minority carrier lifetime can result. It is observed that high illumination intensities and rapid cooling are beneficial for achieving improvements in minority carrier lifetimes through laser hydrogenation. The laser hydrogenation process is then applied to finished screen-printed solar cells fabricated on seeded-cast quasi monocrystalline silicon wafers. The passivation of dislocation clusters is observed with clear improvements in quantum efficiency, open circuit voltage, and short circuit current density, leading to an improvement in efficiency of 0.6% absolute.

  16. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    Science.gov (United States)

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  17. Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

    Science.gov (United States)

    Lee, Ho Ki; Baek, Kye Hyun; Shin, Kyoungsub

    2017-06-01

    As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R 2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3-2.9 nm) to the range (0.79-1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

  18. Design and implementation of a novel conical electrode for fast anodic bonding

    Science.gov (United States)

    Yang, Chii-Rong; Wu, Jim-Wei; Chang, Long-Yin

    2014-10-01

    Anodic bonding is a frequently used nonintermediate wafer-bonding technique for use in MEMS. However, it has a minimum bonding time for a 4 in silicon/glass wafer that is generally limited to the order of several minutes because of the gas-trapping problem that occurs in the bonded interface when a conventional bonding electrode is used. Therefore, the purpose of this study was to develop a novel conical bonding electrode, which shortens the bonding time and solves the gas-trapping problem of the bonded interface. The 4 in silicon/glass wafers fitted with the proposed electrode exhibited a bonding ratio of 99.89% and an average bonding strength of around 15 MPa, which was attained within 15 s, at a bonding voltage of 900 V and a bonding temperature of 400 °C. A comprehensive series of experiments was performed to validate the excellent bonding performance of the proposed conical electrode.

  19. Dislocation structure in interfaces between Si wafers with hybrid crystal orientation

    Energy Technology Data Exchange (ETDEWEB)

    Vdovin, Vladimir [Institute for Chemical Problems of Microelectronics, Moscow (Russian Federation); Zakharov, Nikolai; Pippel, Eckhard; Werner, Peter [Max-Planck-Institut fuer Mikrostrukturphysik, Halle (Saale) (Germany); Milvidskii, Mikhail [Institute of Rare Metals ' Giredmet' , Moscow (Russian Federation); Ries, Mike; Seacrist, Mike [MEMC Inc., 501 Pearl Drive, St. Peters, MO (United States); Falster, Robert [MEMC Electronic Materials SpA, Novara (Italy)

    2009-08-15

    Dislocation structure in Si(110)/Si(001) wafer bonding (WB) structures have been studied by transmission electron microscopy (TEM). The behavior of intermediate native oxide layers during high temperature annealing, the nature of interfacial dislocations and dislocation generation mechanisms are the main issues of this work. Samples were fabricated by direct hydrophilic WB of 200 mm wafers with native oxide. The as-bonded structures containing 140-nm thick layers were thermally annealed in the temperature range 1150 to 1200 C. The dislocation structure composed of a pattern of unidirectional parallel but broken dislocation arrays is formed in the structures with partial or entire dissolution of the oxide layer. The contrast of broken dark lines usually observed in TEM bright field micrographs is supposed to be caused by integral effect of steps compensating twist misorientation and arrays of 60-degree dislocations. We suggest that nucleation of dislocation loops at the interface due to the agglomeration of intrinsic point defects is a plausible mechanism of dislocation generation. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  20. Novel Ge waveguide platform on Ge-on-insulator wafer for mid-infrared photonic integrated circuits.

    Science.gov (United States)

    Kang, Jian; Takenaka, Mitsuru; Takagi, Shinichi

    2016-05-30

    We present Ge rib waveguide devices fabricated on a Ge-on-insulator (GeOI) wafer as a proof-of-concept Ge mid-infrared photonics platform. Numerical analysis revealed that the driving current for a given optical attenuation in a carrier-injection Ge waveguide device at a 1.95 μm wavelength can be approximately five times smaller than that in a Si device, enabling in-line carrier-injection Ge optical modulators based on free-carrier absorption. We prepared a GeOI wafer with a 2-μm-thick buried oxide layer (BOX) by wafer bonding. By using the GeOI wafer, we fabricated Ge rib waveguides. The Ge rib waveguides were transparent to 2 μm wavelengths and the propagation loss was found to be 1.4 dB/mm, which may have been caused by sidewall scattering. We achieved a negligible bend loss in the Ge rib waveguide, even with a 5 μm bend radius, owing to the strong optical confinement in the GeOI structure. We also formed a lateral p-i-n junction along the Ge rib waveguide to explore the capability of absorption modulation by carrier injection. By injecting current through the lateral p-i-n junction, we achieved optical intensity modulation in the 2 μm band based on the free-carrier absorption in Ge.

  1. SEMICONDUCTOR TECHNOLOGY A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    Science.gov (United States)

    Baohong, Gao; Yuling, Liu; Chenwei, Wang; Yadong, Zhu; Shengli, Wang; Qiang, Zhou; Baimei, Tan

    2010-10-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.

  2. Doping Silicon Wafers with Boron by Use of Silicon Paste

    Institute of Scientific and Technical Information of China (English)

    Yu Gao; Shu Zhou; Yunfan Zhang; Chen Dong; Xiaodong Pi; Deren Yang

    2013-01-01

    In this work we introduce recently developed silicon-paste-enabled p-type doping for silicon.Boron-doped silicon nanoparticles are synthesized by a plasma approach.They are then dispersed in solvents to form silicon paste.Silicon paste is screen-printed at the surface of silicon wafers.By annealing,boron atoms in silicon paste diffuse into silicon wafers.Chemical analysis is employed to obtain the concentrations of boron in silicon nanoparticles.The successful doping of silicon wafers with boron is evidenced by secondary ion mass spectroscopy (SIMS) and sheet resistance measurements.

  3. Bond Issues.

    Science.gov (United States)

    Pollack, Rachel H.

    2000-01-01

    Notes trends toward increased borrowing by colleges and universities and offers guidelines for institutions that are considering issuing bonds to raise money for capital projects. Discussion covers advantages of using bond financing, how use of bonds impacts on traditional fund raising, other cautions and concerns, and some troubling aspects of…

  4. Stress-warping relation in thin film coated wafers

    Science.gov (United States)

    Schicker, J.; Khan, W. A.; Arnold, T.; Hirschl, C.

    2017-02-01

    A misfit strain or stress in a thin layer on the surface of a wafer lets the composite disk warp. When the wafer is thin and large, the Stoney estimation of the film stress as function of the curvature yields large errors. We present a nonlinear analytical model that describes the relationship between warpage and film stress on an anisotropic wafer, and give evidence for its suitability for large thin wafers by a comparison to finite element results. Finally, we show the confidence limit of the Stoney estimation and the benefit by the nonlinear model. For thin coatings, it can be succesfully used even without knowledge of the film properties, which was the main advantage of the Stoney estimation.

  5. On-wafer magnetic resonance of magnetite nanoparticles

    Energy Technology Data Exchange (ETDEWEB)

    Little, Charles A.E., E-mail: caelittle@gmail.com; Russek, Stephen E., E-mail: stephen.russek@nist.gov; Booth, James C., E-mail: james.booth@nist.gov; Kabos, Pavel, E-mail: pavel.kabos@nist.gov; Usselman, Robert J., E-mail: robertusselman@gmail.com

    2015-11-01

    Magnetic resonance measurements of ferumoxytol and TEMPO were made using an on-wafer transmission line technique with a vector network analyzer, allowing for broadband measurements of small sample volumes (4 nL) and small numbers of spins (1 nmol). On-wafer resonance measurements were compared with standard single-frequency cavity-based electron paramagnetic resonance (EPR) measurements using a new power conservation approach and the results show similar line shape. On-wafer magnetic resonance measurements using integrated microfluidics and microwave technology can significantly reduce the cost and sample volumes required for EPR spectral analysis and allow for integration of EPR with existing lab-on-a-chip processing and characterization techniques for point-of-care medical diagnostic applications. - Highlights: • On-wafer measurements showed similar line shape to traditional cavity-based EPR. • New power conservation approach alleviates de-embedding ambiguities. • Allows for measurements of small sample volumes and small number of spins.

  6. High Performance Wafer-Based Capillary Electrochromatography Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Los Gatos Research proposes to develop wafer-based capillary electrochromatography for lab-on-a-chip (LOC) applications. These microfluidic devices will be...

  7. 9nm node wafer defect inspection using visible light

    Science.gov (United States)

    Zhou, Renjie; Edwards, Chris; Popescu, Gabriel; Goddard, Lynford L.

    2014-04-01

    Over the past 2 years, we have developed a common optical-path, 532 nm laser epi-illumination diffraction phase microscope (epi-DPM) and successfully applied it to detect different types of defects down to 20 by 100 nm in a 22nm node intentional defect array (IDA) wafer. An image post-processing method called 2DISC, using image frame 2nd order differential, image stitching, and convolution, was used to significantly improve sensitivity of the measured images. To address 9nm node IDA wafer inspection, we updated our system with a highly stable 405 nm diode laser. By using the 2DISC method, we detected parallel bridge defects in the 9nm node wafer. To further enhance detectability, we are exploring 3D wafer scanning, white-light illumination, and dark-field inspection.

  8. Investigation on Adsorption State of Surface Adsorbate on Silicon Wafer

    Institute of Scientific and Technical Information of China (English)

    1999-01-01

    An adsorption kinetics model for adsorbate on the specularly polished silicon wafer was suggested. The mathematical model of preferential adsorption and the mechanism controlling the adsorption state of adsorbate were discussed.

  9. Use of Selective Anodic Bonding to Create Micropump Chambers with Virtually No Dead Volume

    NARCIS (Netherlands)

    Veenstra, T.T.; Berenschot, Johan W.; Gardeniers, Johannes G.E.; Sanders, Remco G.P.; Elwenspoek, Michael Curt; van den Berg, Albert

    2001-01-01

    Membrane micropump chambers of 11 mm diam with virtually zero) dead volume were realized using selective anodic bonding. The selective bonding was achieved with less than 1 mm thick metallic antibonding layers on the glass wafer. Experiments were carried out to come to a better understanding of the

  10. Use of selective anodic bonding to create micropump chambers with virtually no dead volume

    NARCIS (Netherlands)

    Veenstra, T.T.; Berenschot, Johan W.; Gardeniers, Johannes G.E.; Sanders, Remco G.P.; Elwenspoek, Michael Curt; van den Berg, Albert

    2001-01-01

    Membrane micropump chambers of 11 mm diam with virtually zero dead volume were realized using selective anodic bonding. The selective bonding was achieved with less than 1 nm thick metallic antibonding layers on the glass wafer. Experiments were carried out to come to a better understanding of the

  11. IGBT Scaling Principle Toward CMOS Compatible Wafer Processes

    OpenAIRE

    2012-01-01

    A scaling principle for trench gate IGBT is proposed. CMOS technology on large diameter wafer enables to produce various digital circuits with higher performance and lower cost. The transistor cell structure becomes laterally smaller and smaller and vertically shallower and shallower. In contrast, latest IGBTs have rather deeper trench structure to obtain lower on-state voltage drop and turn-off loss. In the aspect of the process uniformity and wafer warpage, manufacturing such structure in t...

  12. Development of Megasonic cleaning for silicon wafers. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  13. One step automated unpatterned wafer defect detection and classification

    Science.gov (United States)

    Dou, Lie; Kesler, Daniel; Bruno, William; Monjak, Charles; Hunt, Jim

    1998-11-01

    Automated detection and classification of crystalline defects on micro-grade silicon wafers is extremely important for integrated circuit (IC) device yield. High training cost, limited capability of classifying defects, increasing possibility of contamination, and unexpected human mistakes necessitate the need to replace the human visual inspection with automated defect inspection. The Laser Scanning Surface Inspection Systems (SSISs) equipped with the Reconvergent Specular Detection (RSD) apparatus are widely used for final wafer inspection. RSD, more commonly known as light channel detection (LC), is capable of detecting and classifying material defects by analyzing information from two independent phenomena, light scattering and reflecting. This paper presents a new technique including a new type of light channel detector to detect and classify wafer surface defects such as slipline dislocation, Epi spikes, Pits, and dimples. The optical system to study this technique consists of a particle scanner to detect and quantify light scattering events from contaminants on the wafer surface and a RSD apparatus (silicon photo detector). Compared with the light channel detector presently used in the wafer fabs, this new light channel technique provides higher sensitivity for small defect detection and more defect scattering signatures for defect classification. Epi protrusions (mounds and spikes), slip dislocations, voids, dimples, and some other common defect features and contamination on silicon wafers are studied using this equipment. The results are compared quantitatively with that of human visual inspection and confirmed by microscope or AFM. This new light channel technology could provide the real future solution to the wafer manufacturing industry for fully automated wafer inspection and defect characterization.

  14. Further investigation of EUV process sensitivities for wafer track processing

    Science.gov (United States)

    Bradon, Neil; Nafus, K.; Shite, H.; Kitano, J.; Kosugi, H.; Goethals, M.; Cheng, S.; Hermans, J.; Hendrickx, E.; Baudemprez, B.; Van Den Heuvel, D.

    2010-04-01

    As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.

  15. Strategy optimization for mask rule check in wafer fab

    Science.gov (United States)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  16. Using Multiple Implant Regions To Reduce Development Wafer Usage

    Science.gov (United States)

    Walther, S. R.; Falk, S.; Mehta, S.; Erokhin, Y.; Nunan, P.

    2006-11-01

    The cost of new process development has risen significantly with larger wafer sizes and the increased number of fabrication steps needed to create advanced devices. The high value of each 300 mm development wafer has spurred efforts to find a way to explore more than a single process setting with each wafer. Traditional methods of defining multiple spatially distinct implant regions on a single wafer achieve poor utilization of device die. The need for efficient utilization of the die and wide process latitude for defining multiple implant regions per wafer has led to the development of an implant proximity mask (vMask™), which permits sharply defined borders between implant regions that may have different species, energy, angle, or dose. The capability of this system to achieve multiple spatially resolved implant conditions per wafer with high die utilization and using the same process parameters as production implants will be described. Specifically, results for measurement of the uniform process area, process repeatability, and cleanliness will illustrate the potential of this technique to dramatically reduce implant process development costs.

  17. Dry texturing of mc-Si wafers

    Energy Technology Data Exchange (ETDEWEB)

    Agarwal, Garima [ENEA-Casaccia, Rome (Italy); CNER, 14-Vigyan Bhawan, University of Rajasthan, Jaipur (India); De Iuliis, Simona; Serenelli, Luca; Salza, Enrico; Tucci, Mario [ENEA-Casaccia, Rome (Italy)

    2011-03-15

    Texturing of mc-Si is a prevailing research topic to improve solar cell efficiency in production. Surface texturing for enhanced absorption in Si has been historically obtained by creating randomly distributed pyramids using anisotropic etchants; but this preferential etching works only on single crystalline silicon because of its crystallographic orientations. A low-cost, large area, random, mask-less texturing scheme is expected to significantly impact terrestrial PV technology and reduce the amount of wet-chemical waste. We propose an approach based on randomly etched mc-Si by RIE system using NF{sub 3} instead of SF{sub 6} or CF{sub 4} to reduce the detrimental formation of carbonaceous or sulfurous contamination at the silicon surface, which results in a surface recombination. To obtain a fast process we have investigated the effect of the chemical etching due to the NF{sub 3} radicals and the ion bombardment induced by Ar. We have found that Arions promote a helpful surface pre-conditioning, while fluorine radicals, produced by NF{sub 3} dissociation, are needed to increase the Si etching rate. Different combinations of flux ratios, gas pressures and RF power have been explored. Efforts have been devoted in obtaining a homogeneous texture on large area wafers, which is inescapable for industrialization. After 10 minutes process effective reflectance values have been measured within the range of 12-14%, and with a-Si/SiN{sub x} the value reduced to 7%. Post-processing minority carrier lifetime values in the range of 10 microseconds have been measured without applying any further chemical cleaning. Additionally, microscopic analysis has been performed to evaluate the surface microstructure morphology (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  18. Stability of laser-propelled wafer satellites

    Science.gov (United States)

    Srinivasan, Prashant; Hughes, Gary B.; Lubin, Philip; Zhang, Qicheng; Madajian, Jonathan; Brashears, Travis; Kulkarni, Neeraj; Cohen, Alexander; Griswold, Janelle

    2016-09-01

    For interstellar missions, directed energy is envisioned to drive wafer-scale spacecraft to relativistic speeds. Spacecraft propulsion is provided by a large array of phase-locked lasers, either in Earth orbit or stationed on the ground. The directed-energy beam is focused on the spacecraft, which includes a reflective sail that propels the craft by reflecting the beam. Fluctuations and asymmetry in the beam will create rotational forces on the sail, so the sail geometry must possess an inherent, passive stabilizing effect. A hyperboloid shape is proposed, since changes in the incident beam angle due to yaw will passively counteract rotational forces. This paper explores passive stability properties of a hyperboloid reflector being bombarded by directed-energy beam. A 2D cross-section is analyzed for stability under simulated asymmetric loads. Passive stabilization is confirmed over a range of asymmetries. Realistic values of radiation pressure magnitude are drawn from the physics of light-mirror interaction. Estimates of beam asymmetry are drawn from optical modeling of a laser array far-field intensity using fixed and stochastic phase perturbations. A 3D multi-physics model is presented, using boundary conditions and forcing terms derived from beam simulations and lightmirror interaction models. The question of optimal sail geometry can be pursued, using concepts developed for the baseline hyperboloid. For example, higher curvature of the hyperboloid increases stability, but reduces effective thrust. A hyperboloid sail could be optimized by seeking the minimum curvature that is stable over the expected range of beam asymmetries.

  19. Reliable aluminum contact formation by electrostatic bonding

    Science.gov (United States)

    Kárpáti, T.; Pap, A. E.; Radnóczi, Gy; Beke, B.; Bársony, I.; Fürjes, P.

    2015-07-01

    The paper presents a detailed study of a reliable method developed for aluminum fusion wafer bonding assisted by the electrostatic force evolving during the anodic bonding process. The IC-compatible procedure described allows the parallel formation of electrical and mechanical contacts, facilitating a reliable packaging of electromechanical systems with backside electrical contacts. This fusion bonding method supports the fabrication of complex microelectromechanical systems (MEMS) and micro-opto-electromechanical systems (MOEMS) structures with enhanced temperature stability, which is crucial in mechanical sensor applications such as pressure or force sensors. Due to the applied electrical potential of  -1000 V the Al metal layers are compressed by electrostatic force, and at the bonding temperature of 450 °C intermetallic diffusion causes aluminum ions to migrate between metal layers.

  20. Electric current characteristic of anodic bonding

    Science.gov (United States)

    He, Jun; Yang, Fang; Wang, Wei; Zhang, Li; Huang, Xian; Zhang, Dacheng

    2015-06-01

    In this paper, a novel current-time model of anodic bonding is proposed and verified experimentally in order to investigate underlying mechanisms of anodic bonding and to achieve real-time monitoring of bonding procedure. The proposed model provides a thorough explanation for the electric current characteristic of anodic bonding. More significantly, it explains two issues which other models cannot explain. One is the sharp rise in current when a voltage is initially applied during anodic bonding. The other is the unexpected large width of depletion layers. In addition, enlargement of the intimately contacted area during anodic bonding can be obtained from the proposed model, which can be utilized to monitor the bonding process. To verify the proposed model, Borofloat33 glass and silicon wafers were adopted in bonding experiments in SUSS SB6 with five different bonding conditions (350 °C 1200 V 370 °C 1200 V 380 °C 1200 V 380 °C 1000 V and 380 °C 1400 V). The results indicate that the observed current data highly coincide with the proposed current-time model. For widths of depletion layers, depth profiling using secondary ion mass spectrometry demonstrates that the calculated values by the model are basically consistent with the experimental values as well.

  1. Parental Bonding

    Directory of Open Access Journals (Sweden)

    T. Paul de Cock

    2014-08-01

    Full Text Available Estimating the early parent–child bonding relationship can be valuable in research and practice. Retrospective dimensional measures of parental bonding provide a means for assessing the experience of the early parent–child relationship. However, combinations of dimensional scores may provide information that is not readily captured with a dimensional approach. This study was designed to assess the presence of homogeneous groups in the population with similar profiles on parental bonding dimensions. Using a short version of the Parental Bonding Instrument (PBI, three parental bonding dimensions (care, authoritarianism, and overprotection were used to assess the presence of unobserved groups in the population using latent profile analysis. The class solutions were regressed on 23 covariates (demographics, parental psychopathology, loss events, and childhood contextual factors to assess the validity of the class solution. The results indicated four distinct profiles of parental bonding for fathers as well as mothers. Parental bonding profiles were significantly associated with a broad range of covariates. This person-centered approach to parental bonding has broad utility in future research which takes into account the effect of parent–child bonding, especially with regard to “affectionless control” style parenting.

  2. Process for Patterning Indium for Bump Bonding

    Science.gov (United States)

    Denis, Kevin

    2012-01-01

    An innovation was created for the Cosmology Large Angular Scale Surveyor for integration of low-temperature detector chips with a silicon backshort and a silicon photonic choke through flipchip bonding. Indium bumps are typically patterned using liftoff processes, which require thick resist. In some applications, it is necessary to locate the bumps close to high-aspect-ratio structures such as wafer through-holes. In those cases, liftoff processes are challenging, and require complicated and time-consuming spray coating technology if the high-aspect-ratio structures are delineated prior to the indium bump process. Alternatively, processing the indium bumps first is limited by compatibility of the indium with subsequent processing. The present invention allows for locating bumps arbitrarily close to multiple-level high-aspect-ratio structures, and for indium bumps to be formed without liftoff resist. The process uses the poor step coverage of indium deposited on a silicon wafer that has been previously etched to delineate the location of the indium bumps. The silicon pattern can be processed through standard lithography prior to adding the high-aspect-ratio structures. Typically, high-aspectratio structures require a thick resist layer so this layer can easily cover the silicon topography. For multiple levels of topography, the silicon can be easily conformally coated through standard processes. A blanket layer of indium is then deposited onto the full wafer; bump bonding only occurs at the high points of the topography.

  3. Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

    Science.gov (United States)

    Chen, Po-Ying; Tsai, Ming-Hsing; Yeh, Wen-Kuan; Jing, Ming-Haw; Chang, Yukon

    2009-12-01

    Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size (B1), edge widths (A1,A2), and bevel angle (θ) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.

  4. Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications.

    Science.gov (United States)

    Geum, Dae-Myeong; Park, Min-Su; Lim, Ju Young; Yang, Hyun-Duk; Song, Jin Dong; Kim, Chang Zoo; Yoon, Euijoon; Kim, SangHyeon; Choi, Won Jun

    2016-02-11

    Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called "Si photonics"). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

  5. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    Science.gov (United States)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  6. Fuzzy TOPSIS for Multiresponse Quality Problems in Wafer Fabrication Processes

    Directory of Open Access Journals (Sweden)

    Chiun-Ming Liu

    2013-01-01

    Full Text Available The quality characteristics in the wafer fabrication process are diverse, variable, and fuzzy in nature. How to effectively deal with multiresponse quality problems in the wafer fabrication process is a challenging task. In this study, the fuzzy technique for order preference by similarity to an ideal solution (TOPSIS, one of the fuzzy multiattribute decision-analysis (MADA methods, is proposed to investigate the fuzzy multiresponse quality problem in integrated-circuit (IC wafer fabrication process. The fuzzy TOPSIS is one of the effective fuzzy MADA methods for dealing with decision-making problems under uncertain environments. First, a fuzzy TOPSIS methodology is developed by considering the ambiguity between quality characteristics. Then, a detailed procedure for the developed fuzzy TOPSIS approach is presented to show how the fuzzy wafer fabrication quality problems can be solved. Real-world data is collected from an IC semiconductor company and the developed fuzzy TOPSIS approach is applied to find an optimal combination of parameters. Results of this study show that the developed approach provides a satisfactory solution to the wafer fabrication multiresponse problem. This developed approach can be also applied to other industries for investigating multiple quality characteristics problems.

  7. Simple and accurate optical height sensor for wafer inspection systems

    Science.gov (United States)

    Shimura, Kei; Nakai, Naoya; Taniguchi, Koichi; Itoh, Masahide

    2016-02-01

    An accurate method for measuring the wafer surface height is required for wafer inspection systems to adjust the focus of inspection optics quickly and precisely. A method for projecting a laser spot onto the wafer surface obliquely and for detecting its image displacement using a one-dimensional position-sensitive detector is known, and a variety of methods have been proposed for improving the accuracy by compensating the measurement error due to the surface patterns. We have developed a simple and accurate method in which an image of a reticle with eight slits is projected on the wafer surface and its reflected image is detected using an image sensor. The surface height is calculated by averaging the coordinates of the images of the slits in both the two directions in the captured image. Pattern-related measurement error was reduced by applying the coordinates averaging to the multiple-slit-projection method. Accuracy of better than 0.35 μm was achieved for a patterned wafer at the reference height and ±0.1 mm from the reference height in a simple configuration.

  8. Microstructure studies of the grinding damage in monocrystalline silicon wafers

    Institute of Scientific and Technical Information of China (English)

    ZHANG Yinxia; KANG Renke; GUO Dongming; JIN Zhuji

    2007-01-01

    The depth and nature of the subsurface damage in a silicon wafer will limit the performance of IC components.Damage microstructures of the silicon wafers ground by the #325,#600, and #2000 grinding wheels was analyzed.The results show that many microcracks,fractures, and dislocation rosettes appear in the surface and subsurface of the wafer ground by the #325 grinding wheel.No obvious microstructure change exists.The amorphous layer with a thickness of about 100 nm,microcracks, high density dislocations,and polycrystalline silicon are observed in the subsurface of the wafer ground by the #600 grinding wheel.For the wafer ground by the #2000 grinding wheel,an amorphous layer of about 30 nm thickness,a polycrystalline silicon layer,a few dislocations,and an elastic deformation layer exist.In general,with the decrease in grit size,the material removal mode changes from micro-fracture mode to ductile mode gradually.

  9. Wafer-level fabrication of arrays of glass lens doublets

    Science.gov (United States)

    Passilly, Nicolas; Perrin, Stéphane; Albero, Jorge; Krauter, Johann; Gaiffe, Olivier; Gauthier-Manuel, Ludovic; Froehly, Luc; Lullin, Justine; Bargiel, Sylwester; Osten, Wolfgang; Gorecki, Christophe

    2016-04-01

    Systems for imaging require to employ high quality optical components in order to dispose of optical aberrations and thus reach sufficient resolution. However, well-known methods to get rid of optical aberrations, such as aspherical profiles or diffractive corrections are not easy to apply to micro-optics. In particular, some of these methods rely on polymers which cannot be associated when such lenses are to be used in integrated devices requiring high temperature process for their further assembly and separation. Among the different approaches, the most common is the lens splitting that consists in dividing the focusing power between two or more optical components. In here, we propose to take advantage of a wafer-level technique, devoted to the generation of glass lenses, which involves thermal reflow in silicon cavities to generate lens doublets. After the convex lens sides are generated, grinding and polishing of both stack sides allow, on the first hand, to form the planar lens backside and, on the other hand, to open the silicon cavity. Nevertheless, silicon frames are then kept and thinned down to form well-controlled and auto-aligned spacers between the lenses. Subsequent accurate vertical assembly of the glass lens arrays is performed by anodic bonding. The latter ensures a high level of alignment both laterally and axially since no additional material is required. Thanks to polishing, the generated lens doublets are then as thin as several hundreds of microns and compatible with micro-opto-electro-systems (MOEMS) technologies since they are only made of glass and silicon. The generated optical module is then robust and provide improved optical performances. Indeed, theoretically, two stacked lenses with similar features and spherical profiles can be almost diffraction limited whereas a single lens characterized by the same numerical aperture than the doublet presents five times higher wavefront error. To demonstrate such assumption, we fabricated glass

  10. Behavior of piezoelectric wafer active sensor in various media

    Science.gov (United States)

    Kamas, Tuncay

    The dissertation addresses structural health monitoring (SHM) techniques using ultrasonic waves generated by piezoelectric wafer active sensors (PWAS) with an emphasis on the development of theoretical models of standing harmonic waves and guided waves. The focal objective of the research is to extend the theoretical study of electro-mechanical coupled PWAS as a resonator/transducer that interacts with standing and traveling waves in various media through electro-mechanical impedance spectroscopy (EMIS) method and guided wave propagation. The analytical models are developed and the coupled field finite element analysis (CF-FEA) models are simulated and verified with experiments. The dissertation is divided into two parts with respect to the developments in EMIS methods and GWP methods. In the first part, analytical and finite element models have been developed for the simulation of PWAS-EMIS in in-plane (longitudinal) and out-of-plane (thickness) mode. Temperature effects on free PWAS-EMIS are also discussed with respect to the in-plane mode. Piezoelectric material degradation on certain electrical and mechanical properties as the temperature increases is simulated by our analytical model for in-plane circular PWAS-EMIS that agrees well with the sets of experiments. Then the thickness mode PWAS-EMIS model was further developed for a PWAS resonator bonded on a plate-like structure. The latter analytical model was to determine the resonance frequencies for the normal mode expansion method through the global matrix method by considering PWAS-substrate and proof mass-PWAS-substrate models. The proof mass concept was adapted to shift the systems resonance frequencies in thickness mode. PWAS in contact with liquid medium on one of its surface has been analytically modeled and simulated the electro-mechanical response of PWAS with various liquids with different material properties such as the density and the viscosity. The second part discusses the guided wave propagation

  11. Development of wafer-level-packaging technology for simultaneous sealing of accelerometer and gyroscope under different pressures

    Science.gov (United States)

    Aono, T.; Suzuki, K.; Kanamaru, M.; Okada, R.; Maeda, D.; Hayashi, M.; Isono, Y.

    2016-10-01

    This research demonstrates a newly developed anodic bonding-based wafer-level-packaging technique to simultaneously seal an accelerometer in the atmosphere and a gyroscope in a vacuum with a glass cap for micro-electromechanical systems sensors. It is necessary for the accelerometer, with a damping oscillator, to be sealed in the atmosphere to achieve a high-speed response. As the gyroscope can achieve high sensitivity with a large displacement at the resonant frequency without air-damping, the gyroscope must be sealed in a vacuum. The technique consists of three processing steps: the first bonding step in the atmosphere for the accelerometer, the pressure control step and the second bonding step in a vacuum for the gyroscope. The process conditions were experimentally determined to achieve higher shear strength at the interface of the packaging. The packaging performance of the accelerometer and gyroscope after wafer-level packaging was also investigated using a laser Doppler velocimeter at room temperature. The amplitude at the resonant frequency of the accelerometer was reduced by air damping, and the quality factor of the gyroscope showed a value higher than 1000. The reliability of the gyroscope was also confirmed by a thermal cyclic test and an endurance test at high humidity and high temperature.

  12. A method for wafer level hermetic packaging of SOI-MEMS devices with embedded vertical feedthroughs using advanced MEMS process

    Science.gov (United States)

    Mert Torunbalci, Mustafa; Emre Alper, Said; Akin, Tayfun

    2015-12-01

    This paper presents a novel, inherently simple, and low-cost fabrication and hermetic packaging method developed for SOI-MEMS devices, where a single SOI wafer is used for the fabrication of MEMS structures as well as vertical feedthroughs, while a single glass cap wafer is used for hermetic encapsulation and routing metallization. Hermetic encapsulation can be achieved either with the silicon-glass anodic or Au-Si eutectic bonding techniques. The dies sealed with anodic and Au-Si eutectic bonding provide a low vertical feedthrough resistance around 50 Ω. Glass-to-silicon anodically and Au-Si eutectic bonded seals yield a very stable cavity pressure below 10 mTorr with thin-film getters, which are measured to be stable even after 311 d. The package pressure can be adjusted from 5 mTorr to 20 Torr by using different outgassing, cavity depth, and gettering options. The packaging yield is observed to be around 64% and 84% for the anodic and Au-Si eutectic packages, respectively. The average shear strength of the anodic and eutectic packages is measured to be higher than 17 MPa and 42 MPa, respectively. Temperature cycling, high temperature storage, and ultra-high temperature shock tests result in no degradation in the hermeticity of the packaged chips, proving perfect thermal reliability.

  13. Selective Au-Si eutectic bonding for Si-based MEMS applications

    Energy Technology Data Exchange (ETDEWEB)

    Lee, A.; Lehew, S.; Yu, C. [and others

    1995-05-22

    A novel method of fabricating three-dimensional silicon micro electromechanical systems (MEMS) is presented, using selectivity thin film deposited Au-Si eutectic bond pads. Utilizing this process, complicated structures such as microgrippers and microchannels are fabricated. Bond strengths are higher than the silicon fracture strength and the bond areas can be localized and aligned to the processed wafer. The process and the applications are described in this paper.

  14. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging.

    Science.gov (United States)

    Xie, Bo; Xing, Yonghao; Wang, Yanshuang; Chen, Jian; Chen, Deyong; Wang, Junbo

    2015-09-21

    This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection) on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months), a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

  15. Wafer-scale fabrication of polymer distributed feedback lasers

    DEFF Research Database (Denmark)

    Christiansen, Mads Brøkner; Schøler, Mikkel; Balslev, Søren

    2006-01-01

    The authors demonstrate wafer-scale, parallel process fabrication of distributed feedback (DFB) polymer dye lasers by two different nanoimprint techniques: By thermal nanoimprint lithography (TNIL) in polymethyl methacrylate and by combined nanoimprint and photolithography (CNP) in SU-8. In both...... techniques, a thin film of polymer, doped with rhodamine-6G laser dye, is spin coated onto a Borofloat glass buffer substrate and shaped into a planar waveguide slab with first order DFB surface corrugations forming the laser resonator. When optically pumped at 532 nm, lasing is obtained in the wavelength...... range between 576 and 607 nm, determined by the grating period. The results, where 13 laser devices are defined across a 10 cm diameter wafer substrate, demonstrate the feasibility of NIL and CNP for parallel wafer-scale fabrication of advanced nanostructured active optical polymer components...

  16. White-light interferometric microscopy for wafer defect inspection

    Science.gov (United States)

    Zhou, Renjie; Edwards, Christopher; Bryniarski, Casey; Dallmann, Marjorie F.; Popescu, Gabriel; Goddard, Lynford L.

    2015-03-01

    White-light imaging systems are free of laser-speckle. Thus, they offer high sensitivity for optical defect metrology, especially when used with interferometry based quantitative phase imaging. This can be a potential solution for wafer inspection beyond the 9 nm node. Recently, we built a white-light epi-illumination diffraction phase microscopy (epi-wDPM) for wafer defect inspection. The system is also equipped with an XYZ scanning stage and real-time processing. Preliminary results have demonstrated detection of 15 nm by 90 nm in a 9 nm node densely patterned wafer with bright-field imaging. Currently, we are implementing phase imaging with epi-wDPM for additional sensitivity.

  17. Laser assisted micro-welding of ultra-thin glass wafers

    Science.gov (United States)

    Hevonkorpi, V.; Lundén, H.; Määttänen, A.

    2016-03-01

    The use of glass in semiconductor industry has been growing during the past years and the grow is estimated to continue and accelerate considerably during the coming years. For efficient manufacturing, especially when using ultra-thin wafers, novel bonding technologies are needed. In this paper, a laser assisted additive free glass-glass welding technology is presented. Furthermore, the use of laser assisted welding to manufacture hermetic packages for optical components is investigated. The reliability and robustness of the weld and the process is verified by damp heat (85 °C at 85% RH) testing. A large quantity, one hundred samples, was tested to define the repeatability of the welding process. D263T, a glass type commonly used in manufacturing consumer products, was selected. Glass-glass welding proved to be a reliable bonding method offering a non-outgassing, room temperature bonding. In addition, it was verified that the weld is hermetic having a good resistance to high temperature and moisture conditions. No changes in the welding seams were observed during or after damp heat testing.

  18. 450mm wafer patterning with jet and flash imprint lithography

    Science.gov (United States)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  19. Disc resonator gyroscope fabrication process requiring no bonding alignment

    Science.gov (United States)

    Shcheglov, Kirill V. (Inventor)

    2010-01-01

    A method of fabricating a resonant vibratory sensor, such as a disc resonator gyro. A silicon baseplate wafer for a disc resonator gyro is provided with one or more locating marks. The disc resonator gyro is fabricated by bonding a blank resonator wafer, such as an SOI wafer, to the fabricated baseplate, and fabricating the resonator structure according to a pattern based at least in part upon the location of the at least one locating mark of the fabricated baseplate. MEMS-based processing is used for the fabrication processing. In some embodiments, the locating mark is visualized using optical and/or infrared viewing methods. A disc resonator gyroscope manufactured according to these methods is described.

  20. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    Energy Technology Data Exchange (ETDEWEB)

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  1. Simulations and Silicon Wafer Compatibility of a Voltage-Controlled Optical Switch Using ITO/NbOx

    Science.gov (United States)

    Burghardt, Kevin

    The story of optics and processing has always been on of silicon devices making strides faster and cheaper than optics. The idea of creating optical switches has been generally relegated to academic exercises or niche markets. This research takes a view of optical processing that is complimentary to silicon. Silicon wafers produce extremely dense, high quality devices but producing truly 3D integrated circuits has been a challenge. It would be advantageous to not need to bond wafers to create a 3D active structure. An argument for an optical switch that has a simple structure and uses industry established fabrication methods is given. The proposed switch uses the material indium tin oxide nanoparticles in niobum oxide glass (ITO/NbOx) as the active layer. The transmittance through this material is proportional to the electric field applied to it meaning the structure of a capacitor could be used to control it. It uses a metal for one plate of the capacitor and the ITO/NbOx as the other plate with the light running through ITO/NbO x plate. Each of the plates are separated from one another and surrounded by a dielectric material. Simulations show that silicon dioxide (SiO 2) can be used effectively to turn the ITO/NbOx into a light guide with a transmittance controllable using an applied voltage and that the proposed structure can be created using industry established wafer fabrication processes.

  2. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    Science.gov (United States)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  3. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    Energy Technology Data Exchange (ETDEWEB)

    Ko, Hyoungho [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Park, Sangjun [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Paik, Seung-Joon [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Choi, Byoung-doo [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Park, Yonghwa [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Lee, Sangmin [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of); Kim, Sungwook [SML Electronics, Inc. (Korea, Republic of); Lee, Sang Chul [SML Electronics, Inc. (Korea, Republic of); Lee, Ahra [SML Electronics, Inc. (Korea, Republic of); Yoo, Kwangho [SML Electronics, Inc. (Korea, Republic of); Lim, Jaesang [SML Electronics, Inc. (Korea, Republic of); Cho, Dong-il [School of Electrical Engineering and Computer Science, Seoul National University (Korea, Republic of)

    2006-04-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 {mu}m BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 {mu}g/{radical}Hz, the bias instability of 490 {mu}g, the input range of {+-}10 g, and the output nonlinearity of {+-}0.5 %FSO.

  4. Low-cost bump bonding activities at CERN

    Energy Technology Data Exchange (ETDEWEB)

    Vaehaenen, S; Tick, T; Campbell, M, E-mail: Sami.vaehaenen@cern.c [CERN, PH-ESE 1211 Geneva 23 (Switzerland)

    2010-11-15

    Conventional bumping processes used in the fabrication of hybrid pixel detectors for High Energy Physics (HEP) experiments use electroplating for Under Bump Metallization (UBM) and solder bump deposition. This process is laborious, involves time consuming photolithography and can only be performed using whole wafers. Electroplating has been found to be expensive when used for the low volumes which are typical of HEP experiments. In the low-cost bump bonding development work, electroless deposition technology of UBM is studied as an alternative to the electroplating process in the bump size / pitch window beginning from 20 {mu}m / 50 {mu}m. Electroless UBM deposition used in combination with solder transfer techniques has the potential to significantly lower the cost of wafer bumping without requiring increased wafer volumes. A test vehicle design of sensor and readout chip, having daisy chains and Kelvin bump structures, was created to characterize the flip chip process with electroless UBM. Two batches of test vehicle wafers were manufactured with different bump pad metallization. Batch no. 1 had AlSi(1%) metallization, which is similar to the one used on sensor wafers, and Batch no. 2 had AlSi(2%)Cu(1%) metallization, which is very similar to the one used on readout wafers. Electroless UBMs were deposited on both wafer batches. In addition, electroplated Ni UBM and SnPb solder bumps were grown on the test sensor wafers. Test assemblies were made by flip chip bonding the solder-bumped test sensors against the test readout chips with electroless UBMs. Electrical yields and individual joint resistances were measured from assemblies, and the results were compared to a well known reference technique based on electroplated solder bumps structures on both chips. The electroless UBMs deposited on AlSi(2%)Cu(1%) metallization showed excellent electrical yields and small tolerances in individual joint resistance. The results from the UBMs deposited on AlSi(1

  5. Optical coating uniformity of 200mm (8") diameter precut wafers

    Science.gov (United States)

    Burt, Travis C.; Fisher, Mark; Brown, Dean; Troiani, David

    2017-02-01

    Automated spectroscopic profiling (mapping) of a 200 mm diameter near infrared high reflector (centered at 1064 nm) are presented. Spatial resolution at 5 mm or less was achieved using a 5 mm × 1.5 mm monochromatic beam. Reflection changes of 1.0% across the wafer diameter were observed under s-polarized and p- polarized conditions. Redundancy was established for each chord by re-measuring the center of the wafer and reproducibility of approximately platform for angles of incidence in the range 5°stream processing.

  6. Wafer scale integration of catalyst dots into nonplanar microsystems

    DEFF Research Database (Denmark)

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge;

    2007-01-01

    In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  7. Bond Boom

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    The Ministry of Finance recently kick-started a pilot program allowing local governments of Shanghai and Shenzhen,and Zhejiang and Guangdong provinces to issue bonds for the first time.How will the new policy affect fiscal capacities of local governments and the broader economy? What else should the country do to build a healthy bond market? Economists and experts discussed these issues in an interview with the Shanghai Securities Journal.Edited excerpts follow.

  8. Bond Boom

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    The Ministry of Finance recently kick-started a pilot program allowing local governments of Shanghai and Shenzhen, and Zhejiang and Guangdong provinces to issue bonds for the first time. How will the new policy affect fiscal capacities of local governments and the broader economy? What else should the country do to build a healthy bond market? Economists and experts discussed these issues in an interview with the ShanghaiSecuritiesJournal. Edited excerpts follow:

  9. Measurement of bonding energy in an anhydrous nitrogen atmosphere and its application to silicon direct bonding technology

    Science.gov (United States)

    Fournel, F.; Continni, L.; Morales, C.; Da Fonseca, J.; Moriceau, H.; Rieutord, F.; Barthelemy, A.; Radu, I.

    2012-05-01

    Bonding energy represents an important parameter for direct bonding applications as well as for the elaboration of physical mechanisms at bonding interfaces. Measurement of bonding energy using double cantilever beam (DCB) under prescribed displacement is the most used technique thanks to its simplicity. The measurements are typically done in standard atmosphere with relative humidity above 30%. Therefore, the obtained bonding energies are strongly impacted by the water stress corrosion at the bonding interfaces. This paper presents measurements of bonding energies of directly bonded silicon wafers under anhydrous nitrogen conditions in order to prevent the water stress corrosion effect. It is shown that the measurements under anhydrous nitrogen conditions (less than 0.2 ppm of water in nitrogen) lead to high stable debonding lengths under static load and to higher bonding energies compared to the values measured under standard ambient conditions. Moreover, the bonding energies of Si/SiO2 or SiO2/SiO2 bonding interfaces are measured overall the classical post bond annealing temperature range. These new results allow to revisit the reported bonding mechanisms and to highlight physical and chemical phenomena in the absence of stress corrosion effect.

  10. The influence of wafer elasticity on acoustic waves during LIGA development.

    Energy Technology Data Exchange (ETDEWEB)

    Ting, Aili

    2003-12-01

    During acoustically stimulated LIGA development, a wafer receives sound waves from both sides at a wide variety of incidence angles that vary in time depending on the orientation of the wafer relative to the multiple transducers that are typically actuated in a periodic sequence. It is important to understand the influence of these variables on the transmission of energy through the wafer as well as the induced motion of the wafer itself because these processes impact the induced acoustic streaming of the fluid within features, the mechanism presently thought responsible for enhanced development of LIGA features. In the present work, the impact of wafer elasticity on LIGA development is investigated. Transmission waves, wafer bending waves, and the related concepts such as critical bending frequency, mechanical impedance, coincidence, and resonance, are discussed. Supercritical-frequency incident waves induce supersonic bending waves in the wafer. Incident wave energy is channeled into three components, transmitted, reflected and energy deposited to the wafer, depending on the wafer material, thickness and wave incidence angle. Results show at normal incidence for a 1-mm PMMA wafer, about 47% of the wave energy is deposited in the wafer. The wafer gains almost half of the incident energy, a result that agrees well with the Bankert et a1 measurements. In LIGA development, transmitted waves may sometimes produce strong acoustic motion of the developer on the wafer backside, especially for the so-called coincidence case in which almost all incident wave energy transfers to the backside. Wafer bending waves cause wafer oscillation at high frequency, promoting the development process, but features shaking may weaken their attachments to the substrate. Resonance is not likely for the entire wafer, but may occur in short and wide wafer feature columns, which are least likely to break away from the substrate, perhaps resulting in good agitation of the fluid in adjacent

  11. A high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging.

    Science.gov (United States)

    Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

    2014-12-16

    This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in "H" type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than -0.01% F.S/°C in the range of -40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S.

  12. A High-Q Resonant Pressure Microsensor with Through-Glass Electrical Interconnections Based on Wafer-Level MEMS Vacuum Packaging

    Directory of Open Access Journals (Sweden)

    Zhenyu Luo

    2014-12-01

    Full Text Available This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than −0.01% F.S/°C in the range of −40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S.

  13. A High-Q Resonant Pressure Microsensor with Through-Glass Electrical Interconnections Based on Wafer-Level MEMS Vacuum Packaging

    Science.gov (United States)

    Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

    2014-01-01

    This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than −0.01% F.S/°C in the range of −40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S. PMID:25521385

  14. Protection of MOS capacitors during anodic bonding

    Science.gov (United States)

    Schjølberg-Henriksen, K.; Plaza, J. A.; Rafí, J. M.; Esteve, J.; Campabadal, F.; Santander, J.; Jensen, G. U.; Hanneborg, A.

    2002-07-01

    We have investigated the electrical damage by anodic bonding on CMOS-quality gate oxide and methods to prevent this damage. n-type and p-type MOS capacitors were characterized by quasi-static and high-frequency CV-curves before and after anodic bonding. Capacitors that were bonded to a Pyrex wafer with 10 μm deep cavities enclosing the capacitors exhibited increased leakage current and interface trap density after bonding. Two different methods were successful in protecting the capacitors from such damage. Our first approach was to increase the cavity depth from 10 μm to 50 μm, thus reducing the electric field across the gate oxide during bonding from approximately 2 × 105 V cm-1 to 4 × 104 V cm-1. The second protection method was to coat the inside of a 10 μm deep Pyrex glass cavity with aluminium, forming a Faraday cage that removed the electric field across the cavity during anodic bonding. Both methods resulted in capacitors with decreased interface trap density and unchanged leakage current after bonding. No change in effective oxide charge or mobile ion contamination was observed on any of the capacitors in the study.

  15. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    Science.gov (United States)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  16. 3D Align overlay verification using glass wafers

    NARCIS (Netherlands)

    Smeets, E.M.J.; Bijnen, F.C.G.; Slabbekoorn, J.; Van Zeijl, H.W.

    2004-01-01

    In the MEMS world, increasing attention is being given to 3D devices requiring dual-sided processing. This requires lithography tools that are able to align a wafer to both its back side as front side. Overlay describes how well front and back side layers are positioned with respect to each other. C

  17. 3D Align overlay verification using glass wafers

    NARCIS (Netherlands)

    Smeets, E.M.J.; Bijnen, F.C.G.; Slabbekoorn, J.; Van Zeijl, H.W.

    2004-01-01

    In the MEMS world, increasing attention is being given to 3D devices requiring dual-sided processing. This requires lithography tools that are able to align a wafer to both its back side as front side. Overlay describes how well front and back side layers are positioned with respect to each other.

  18. Fatigue Life Analysis of Cantilever Probe on Wafer Test

    Directory of Open Access Journals (Sweden)

    Hsiao Te-Ching

    2016-01-01

    Full Text Available This research utilizes the finite element analysis software (ANSYS to stimulate the different probe material quality (tungsten, SUS304 stainless steel, SUS316L stainless steel and SKD11 tool steel, respectively during wafer tests. Under a room temperature of (25°C, the stress and fatigue life (cycles of probing test of the cantilever probe were measured with an OverDriver (OD of 20µm, 40µm, 50µm, 60µm and 80µm, respectively. First, to obtain the magnitude of pinpoint shift of the probe under wafer test and the OverDriver is 50µm. And, calculate the fatigue life of the probe. Then, a probe model with the same characteristics as the experiment is created and the probe fatigue life analyzed with the ANSYS. After the reliability of the model is ascertained, the wafer tests of different probe materials are stimulated under different OverDriver circumstances to calculate its stress and fatigue life. The results indicate that the greatest stress measured during the wafer test of the tungsten, SUS304 stainless steel, SUS316L stainless steel and SKD11 tool steel cantilever probe are all smaller than the yield strength, and the fatigue life could reach over one hundred K cycles. When catalogued by the cantilever probe fatigue life during one hundred K cycles, the life span, in order, is tungsten < SUS316L stainless steel < SUS304 stainless steel < SKD11 tool steel.

  19. High frequency guided wave propagation in monocrystalline silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  20. Wafer-scale nanostructure formation inside vertical nano-pores

    NARCIS (Netherlands)

    Berenschot, Johan W.; Sun, Xingwu; Le The, Hai; Tiggelaar, Roald M.; de Boer, Meint J.; Eijkel, Jan C.T.; Gardeniers, Johannes G.E.; Tas, Niels Roelof; Sarajlic, Edin

    We propose a wafer-scale technique for nanostructure formation inside vertically oriented, through-membrane nano-pores. It uses 50 nm monocrystalline silicon pillars as a mold, embedded in a silicon nitride membrane formed in an innovative step. The proposed technique paves the way towards advanced

  1. Wafer scale coating of polymer cantilever fabricated by nanoimprint lithography

    DEFF Research Database (Denmark)

    Greve, Anders; Dohn, Søren; Keller, Stephan Urs

    2010-01-01

    Microcantilevers can be fabricated in TOPAS by nanoimprint lithography, with the dimensions of 500 ¿m length 4.5 ¿m thickness and 100 ¿m width. By using a plasma polymerization technique it is possible to selectively functionalize individually cantilevers with a polymer coating, on wafer scale...

  2. 3D Align overlay verification using glass wafers

    NARCIS (Netherlands)

    Smeets, E.M.J.; Bijnen, F.C.G.; Slabbekoorn, J.; Van Zeijl, H.W.

    2004-01-01

    In the MEMS world, increasing attention is being given to 3D devices requiring dual-sided processing. This requires lithography tools that are able to align a wafer to both its back side as front side. Overlay describes how well front and back side layers are positioned with respect to each other. C

  3. Wafer-scale nanostructure formation inside vertical nano-pores

    NARCIS (Netherlands)

    Berenschot, Johan W.; Sun, Xingwu; Le The, Hai; Tiggelaar, Roald M.; de Boer, Meint J.; Eijkel, Jan C.T.; Gardeniers, Johannes G.E.; Tas, Niels Roelof; Sarajlic, Edin

    2017-01-01

    We propose a wafer-scale technique for nanostructure formation inside vertically oriented, through-membrane nano-pores. It uses 50 nm monocrystalline silicon pillars as a mold, embedded in a silicon nitride membrane formed in an innovative step. The proposed technique paves the way towards advanced

  4. Method for reuse of wafers for growth of vertically-aligned wire arrays

    Science.gov (United States)

    Spurgeon, Joshua M; Plass, Katherine E; Lewis, Nathan S; Atwater, Harry A

    2013-06-04

    Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide.

  5. Novel Bonding technologies for wafer-level transparent packaging of MOEMS

    CERN Document Server

    Kirchberger, H; Wimpliger, M

    2008-01-01

    Depending on the type of Micro-Electro-Mechanical System (MEMS), packaging costs are contributing up to 80% of the total device cost. Each MEMS device category, its function and operational environment will individually dictate the packaging requirement. Due to the lack of standardized testing procedures, the reliability of those MEMS packages sometimes can only be proven by taking into consideration its functionality over lifetime. Innovation with regards to cost reduction and standardization in the field of packaging is therefore of utmost importance to the speed of commercialisation of MEMS devices. Nowadays heavily driven by consumer applications the MEMS device market is forecasted to enjoy a compound annual growth rate (CAGR) above 13%, which is when compared to the IC device market, an outstanding growth rate. Nevertheless this forecasted value can drift upwards or downwards depending on the rate of innovation in the field of packaging. MEMS devices typically require a specific fabrication process wher...

  6. Predictive modeling of composite material degradation using piezoelectric wafer sensors electromechanical impedance spectroscopy

    Science.gov (United States)

    Gresil, Matthieu; Yu, Lingyu; Sutton, Mike; Guo, Siming; Pollock, Patrick

    2012-04-01

    The advancement of composite materials in aircraft structures has led to on increased need for effective structural health monitoring (SHM) technologies that are able to detect and assess damage present in composites structures. The work presented in this paper is interested in understanding using self-sensing piezoelectric wafer active sensors (PWAS) to conduct electromechanical impedance spectroscopy (EMIS) in glass fiber reinforced plastic (GFRP) to perform structures health monitoring. PWAS are bonded to the composite material and the EMIS method is used to analyze the changes in the structural resonance and anti-resonance. As the damage progresses in the specimen, the impedance spectrum will change. In addition, multi-physics based finite element method (MP-FEM) is used to model the electromechanical behavior of a free PWAS and its interaction with the host structure on which it is bonded. The MPFEM permits the input and the output variables to be expressed directly in electric terms while the two way electromechanical conversion is done internally in the MP_FEM formulation. To reach the goal of using the EMIS approach to detect damage, several damages models are generated on laminated GFRP structures. The effects of the modeling are carefully studied through experimental validation. A good match has been observed for low and very high frequencies.

  7. Characterization of Boron Diffusion Phenomena According to the Specific Resistivity of N-Type Si Wafer.

    Science.gov (United States)

    Lee, Woo-Jin; Choi, Chel-Jong; Park, Gye-Choon; Yang, O-Bong

    2016-02-01

    This paper is directed to characterize the boron diffusion process according to the specific resistivity of the Si wafer. N-type Si wafers were used with the specific resistivity of 0.5-3.2 omega-cm, 1.0-6.5 omega-cm and 2.0-8.0 omega-cm. The boron tribromide (BBr3) was used as boron source to create the PN junction on N-type Si wafer. The boron diffusion in N-type Si wafer was characterized by sheet resistance of wafer surface, secondary ion mass spectroscopy measurements (SIMS) and surface life time analysis. The degree of boron diffusion was depended on the variation in specific resistivity and sheet resistance of the bare N-type Si wafer. The boron diffused N-Si wafer exhibited the average junction depth of 750 nm and boron concentration of 1 x 10(19). N-type Si wafer with the different specific resistance considerably affected the boron diffusion length and life time of Si wafer. It was found that the lifetime of boron diffused wafer was proportional to the sheet resistance and resistivity. However, optimization process may necessary to achieve the high efficiency through the high sheet resistance wafer, because the metallization process control is very sensitive.

  8. Realization of ultrafast and high-quality anodic bonding using a non-contact scanning electrode

    Science.gov (United States)

    Wu, Jim-Wei; Yang, Chii-Rong; Huang, Mao-Jung; Yang, Cheng-Hao; Huang, Che-Yi

    2013-07-01

    The anodic bonding technique, which is primarily used in glass to silicon wafer bonding, has been extensively used in microelectromechanical systems (MEMS) for the packaging of microsensors and microactuators. When the bonding voltage is applied, the bonded region instantly occurs at the contact point of the cathode with the glass. The geometric shape or arranged pattern of the cathode electrode significantly affects the bonding quality, particularly the gas-trapping at the bonded interface and the bonding time. This paper presents a novel anodic bonding process, in which the non-contacting and rotating electrode with radial lines is used as the cathode for scan bonding with arc-discharge assistance. The experimental results show that a bonding ratio of 99.98% and an average bonding strength of 15.45 MPa for a 4-inch silicon/glass bonded pair can be achieved in a 17 s bonding time by using a cathode electrode with eight 45 included-angle radial lines at a rotation speed of 0.45 rpm, a non-contact gap of 120 µm, a bonding voltage of 900 V and a bonding temperature of 400 °C. This ultrafast and high-quality anodic bonding has been synchronously realized under this scan bonding technique.

  9. Multicrystalline silicon wafers prepared from upgraded metallurgical feedstock

    Energy Technology Data Exchange (ETDEWEB)

    Degoulange, J.; Trassy, C. [SIMAP UMR CNRS, INP Grenoble (France); Perichaud, I.; Martinuzzi, S. [TECSEN UMR CNRS-University Paul Cezanne-Aix, Marseille III (France)

    2008-10-15

    A solution to the problem of the shortage of silicon feedstock used to grow multicrystalline ingots can be the production of a feedstock obtained by the direct purification of upgraded metallurgical silicon by means of a plasma torch. It is found that the dopant concentrations in the material manufactured following this metallurgical route are in the 10{sup 17} cm{sup -3} range. Minority carrier diffusion lengths L{sub n} are close to 35 {mu}m in the raw wafers and increases up to 120 {mu}m after the wafers go through the standard processing steps needed to make solar cells: phosphorus diffusion, aluminium-silicon alloying and hydrogenation by deposition of a hydrogen-rich silicon nitride layer followed by an annealing. L{sub n} values are limited by the presence of residual metallic impurities, mainly slow diffusers like aluminium, and also by the high doping level. (author)

  10. Peptide and protein loading into porous silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

    2008-02-15

    The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  11. Switchable static friction of piezoelectric composite—silicon wafer contacts

    Science.gov (United States)

    van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

    2013-04-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from μ* = 1.65 to μ* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

  12. Surface shape control of the workpiece in a double-spindle triple-workstation wafer grinder

    Science.gov (United States)

    Xianglong, Zhu; Renke, Kang; Zhigang, Dong; Guang, Feng

    2011-10-01

    Double-spindle triple-workstation (DSTW) ultra precision grinders are mainly used in production lines for manufacturing and back thinning large diameter (>= 300 mm) silicon wafers for integrated circuits. It is important, but insufficiently studied, to control the wafer shape ground on a DSTW grinder by adjusting the inclination angles of the spindles and work tables. In this paper, the requirements of the inclination angle adjustment of the grinding spindles and work tables in DSTW wafer grinders are analyzed. A reasonable configuration of the grinding spindles and work tables in DSTW wafer grinders are proposed. Based on the proposed configuration, an adjustment method of the inclination angle of grinding spindles and work tables for DSTW wafer grinders is put forward. The mathematical models of wafer shape with the adjustment amount of inclination angles for both fine and rough grinding spindles are derived. The proposed grinder configuration and adjustment method will provide helpful instruction for DSTW wafer grinder design.

  13. Towards reduced impact of EUV mask defectivity on wafer

    Science.gov (United States)

    Jonckheere, R.; Van den Heuvel, D.; Pacco, A.; Pollentier, I.; Baudemprez, B.; Jehoul, C.; Hermans, J.; Hendrickx, E.

    2014-07-01

    The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles "hopping" between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present "black-border" solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

  14. Wafer-shape based in-plane distortion predictions using superfast 4G metrology

    Science.gov (United States)

    van Dijk, Leon; Mileham, Jeffrey; Malakhovsky, Ilja; Laidler, David; Dekkers, Harold; Van Elshocht, Sven; Anberg, Doug; Owen, David M.; van Haren, Richard

    2017-03-01

    With the latest immersion scanners performing at the sub-2 nm overlay level, the non-lithography contributors to the OnProduct-Overlay budget become more and more dominant. Examples of these contributors are etching, thin film deposition, Chemical-Mechanical Planarization and thermal anneal. These processes can introduce stress or stress changes in the thin films on top of the silicon wafers, resulting in significant wafer grid distortions. High-order wafer alignment (HOWA) is the current ASML solution for correcting wafers with a high order grid distortion introduced by non-lithographic processes, especially when these distortions vary from wafer-to-wafer. These models are currently successfully applied in high volume production at several semiconductor device manufacturers. An important precondition is that the wafer distortions remain global as the polynomial-based HOWA models become less effective for very local distortions. Wafer-shape based feed forward overlay corrections can be a possible solution to overcome this challenge. Thin film stress typically has an impact on the unclamped, free-form shape of the wafers. When an accurate relationship between the wafer shape and in-plane distortion (IPD) after clamping is established then feedforward overlay control can be enabled. In this work we assess the capability of wafer-shape based IPD predictions via a controlled experiment. The processinduced IPDs are accurately measured on the ASML TWINSCANTM system using its SMASH alignment system and the wafer shapes are measured on the Superfast 4G inspection system. In order to relate the wafer shape to the IPD we have developed a prediction model beyond the standard Stoney approximation. The match between the predicted and measured IPD is excellent ( 1-nm), indicating the feasibility of using wafer shape for feed-forward overlay control.

  15. Integration of robust fluidic interconnects using metal to glass anodic bonding

    Science.gov (United States)

    Briand, Danick; Weber, Patrick; de Rooij, Nicolaas F.

    2005-09-01

    This paper reports on the encapsulation of a piezoresistive silicon/Pyrex liquid flow sensor using metal to glass anodic bonding. The bonding technique allowed integrating robust metallic microfluidic interconnects and eliminating the use of glue and O-rings. The bonding parameters of a silicon/Pyrex/metal triple stack were chosen to minimize the residual stress and to obtain a strong and liquid tight bonding interface. The silicon/Pyrex liquid flow sensor was successfully bonded to metallic plates of Kovar and Alloy 42, on which tubes were fixed and a printed circuit board (PCB) was integrated. A post-bonding annealing procedure was developed to reduce the residual bonding stress. The characteristics of the encapsulated liquid flow sensor, such as the temperature coefficient of sensitivity, fulfilled the specifications. Wafer level packaging using metal to glass anodic bonding was considered to reduce the packaging size and cost.

  16. Nanoneedles based on porous silicon for chip bonding with self assembly capability

    Energy Technology Data Exchange (ETDEWEB)

    Jonnalagadda, Prasad; Mescheder, Ulrich; Kovacs, Andras; Nimoe, Antwi [Institute for Applied Research and Faculty Computer and Electrical Engineering, Hochschule Furtwangen University, Robert-Gerwig-Platz 1, 78120 Furtwangen (Germany)

    2011-06-15

    Needle-like surface structures have been fabricated using a self-organized nanostructuring process based on porous silicon. Optimized surfaces have been used for a novel bonding process in Si-MEMS. The realized needle-like surfaces enable Van-der-Waals based bonding at low temperature with self-assembly capability. The bonding forces depend on the surface topology and can be tailored by the nanostructuring process between permanent and detachable bonding. Bond strength for permanent bonding in the range of 1-10 MPa has been achieved. Multiple bonding of the same surface is possible (Velcro {sup registered} -principle). The capability of needle like surfaces for self aligned bonding of Si-chips or small silicon based systems (''smart dust'') on locally nanostructured areas of silicon wafers (Si-motherboard) has been shown. (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  17. DRIE and Bonding Assisted Low Cost MEMS Processing of In-plane HAR Inertial Sensors

    NARCIS (Netherlands)

    Rajaraman, V.; Makinwa, K.A.A.; French, P.J.

    2008-01-01

    We present a simple, flexible and low cost MEMS fabrication process, developed using deep reactive ion etching (DRIE) and wafer bonding technologies, for manufacturing in-plane high aspect ratio (HAR) inertial sensors. Among examples, the design and fabrication results of a two axis inertial device

  18. DRIE and Bonding Assisted Low Cost MEMS Processing of In-plane HAR Inertial Sensors

    NARCIS (Netherlands)

    Rajaraman, V.; Makinwa, K.A.A.; French, P.J.

    2008-01-01

    We present a simple, flexible and low cost MEMS fabrication process, developed using deep reactive ion etching (DRIE) and wafer bonding technologies, for manufacturing in-plane high aspect ratio (HAR) inertial sensors. Among examples, the design and fabrication results of a two axis inertial device

  19. Thick orientation-patterned growth of GaP on wafer-fused GaAs templates by hydride vapor phase epitaxy for frequency conversion

    Science.gov (United States)

    Vangala, Shivashankar; Kimani, Martin; Peterson, Rita; Stites, Ron; Snure, Michael; Tassev, Vladimir

    2016-10-01

    Quasi-phase-matched (QPM) GaP layers up to 300 μm thick have been produced by low-pressure hydride vapor phase epitaxy (LP-HVPE) overgrowth on orientation-patterned GaAs (OPGaAs) templates fabricated using a wafer-fusion bonding technique. The growth on the OPGaAs templates resulted in up to 200 μm thick vertically propagating domains, with a total GaP thickness of 300 μm. The successful thick growth on OPGaAs templates is the first step towards solving the material problems associated with unreliable material quality of commercially available GaP wafers and making the whole process of designing QPM frequency conversion devices molecular beam epitaxy free and more cost-effective.

  20. Legume Wafer Supplementation to Increase the Performance of Post-Weaning Ettawa Grade Goats

    Directory of Open Access Journals (Sweden)

    Brilian Desca Dianingtyas

    2017-04-01

    Full Text Available This research was conducted to analyze the effect of legume wafer supplementation on the performance of post weaning Ettawa Grade goats. A total of 16 post weaning Ettawa Grade goats (average body weight 13.10±0.91 kg were grouped into 4 group treatments and 4 blocks as replicate in a completely randomized block design. The treatments were T0 (basal diet/control, T1 (supplementation of 12.12% wafer supplement of Indigofera zollingeriana, T2 (supplementation of 13.54% wafer supplement of Leucaena leucocephala and T3 (supplementation of 12.37% wafer supplement of Calliandra calothyrsus. The feed intake, nutrient digestibility, average daily gain (ADG, feed efficiency (FE, and income over feed cost (IOFC were observed. The results showed that supplementation of legume wafer increased (P<0.05 the feed intake, organic matter digestibility, ADG, FE, and IOFC. Supplementation of I. zollingeriana wafer increased ADG by 55.08%, FE by 34.91%, and IOFC by 14.53%; L. leucocephala wafer increased ADG by 66.18%, FE by 41.63%, and IOFC by 19.09%; and C. calothyrsus wafer increased ADG by 32.62%, FE by 11.30%, and IOFC by 14.34%. In conclusion, the addition of legume wafer supplements into the rations could increase the feed utility value of legumes and L. leucocephala wafer at 13.54% showed the best performance in post-weaning Ettawa Grade goats.

  1. Persentase Karkas Itik Peking yang Diberi Pakan dalam Bentuk Wafer Ransum Komplit Mengandung Limbah Kopi

    Directory of Open Access Journals (Sweden)

    Muhammad Daud

    2016-04-01

    Full Text Available ABSTRAK. Penggunaan wafer ransum komplit mengandung limbah kopi pada itik peking dilakukan dengan tujuan untuk mengetahui berat akhir dan persentase karkas. Materi penelitian yang digunakan adalah itik peking umur 1 hari (DOD sebanyak 96 ekor dibagi dalam 4 perlakuan dan 3 ulangan. Ransum yang digunakan satu bulan pertama adalah ransum komersil, dan satu bulan terakhir wafer ransum komplit mengandung limbah kopi. Ransum perlakuan yang diberikan adalah: P0 = Wafer ransum komplit 0% limbah kopi (kontrol, P1 = Wafer ransum komplit 2,5% limbah kopi, P2 = Wafer ransum komplit 5% limbah kopi, dan P3 = Wafer ransum komplit 7,5% limbah kopi. Parameter yang diamati: bobot hidup, bobot karkas, bobot potongan karkas, persentase karkas, dan persentase potongan karkas. Penelitian ini menggunakan Rancangan Acak Lengkap. Data dianalisis dengan analysis of variance dan dilanjutkan dengan Uji Duncan. Hasil penelitian menunjukkan penggunaan limbah kulit kopi sebagai bahan penyusun ransum itik peking dalam bentuk wafer ransum komplit berpengaruh nyata terhadap bobot akhir. Penggunaan limbah kulit kopi 2,5% dalam ransum secara signifikan (P<0.05 meningkatkan bobot karkas dan potongan karkas. Dapat disimpulkan penggunaan limbah kulit kopi sebanyak 2,5% sebagai bahan penyusun wafer ransum komplit tidak memberi pengaruh negatif terhadap bobot badan akhir, persentase karkas dan potongan karkas itik peking.    (Carcass percentage of peking duck feed wafer complete ration containing of coffee waste  ABSTRACT. This research was conducted to study the effectiveness of wafer complete ration containing coffee waste on the final body weight and carcass percentage. The study used 96 DOD Peking duck. Completely Randomized Design (CRD consisting of 4 treatments and 3 replications. Rations used during the first month was a commercial ration, and then subsequently wafer complete ration of coffee waste given as treatments; P0 = wafer complete ration contained 0% of coffee waste

  2. Interfacial characterization of Al-Al thermocompression bonds

    Energy Technology Data Exchange (ETDEWEB)

    Malik, N., E-mail: nishantmalik1987@gmail.com [Centre for Materials Science and Nanotechnology, University of Oslo, P.O. Box 1032, Blindern, N-0315 Oslo (Norway); SINTEF ICT, Department of Microsystems and Nanotechnology, P.O. Box 124 Blindern, N-0314 Oslo (Norway); Carvalho, P. A. [SINTEF Materials and Chemistry, Department of Materials and Nanotechnology, P.O. Box 124 Blindern, N-0314 Oslo (Norway); Poppe, E. [SINTEF ICT, Department of Microsystems and Nanotechnology, P.O. Box 124 Blindern, N-0314 Oslo (Norway); Finstad, T. G. [Centre for Materials Science and Nanotechnology, University of Oslo, P.O. Box 1032, Blindern, N-0315 Oslo (Norway)

    2016-05-28

    Interfaces formed by Al-Al thermocompression bonding were studied by the transmission electron microscopy. Si wafer pairs having patterned bonding frames were bonded using Al films deposited on Si or SiO{sub 2} as intermediate bonding media. A bond force of 36 or 60 kN at bonding temperatures ranging from 400–550 °C was applied for a duration of 60 min. Differences in the bonded interfaces of 200 μm wide sealing frames were investigated. It was observed that the interface had voids for bonding with 36 kN at 400 °C for Al deposited both on Si and on SiO{sub 2}. However, the dicing yield was 33% for Al on Si and 98% for Al on SiO{sub 2}, attesting for the higher quality of the latter bonds. Both a bond force of 60 kN applied at 400 °C and a bond force of 36 kN applied at 550 °C resulted in completely bonded frames with dicing yields of, respectively, 100% and 96%. A high density of long dislocations in the Al grains was observed for the 60 kN case, while the higher temperature resulted in grain boundary rotation away from the original Al-Al interface towards more stable configurations. Possible bonding mechanisms and reasons for the large difference in bonding quality of the Al films deposited on Si or SiO{sub 2} are discussed.

  3. GaAs wafer overlay performance affected by annealing heat treatment: II

    Science.gov (United States)

    Liu, Ying; Black, Iain

    2002-07-01

    Further analysis on how wafer distortion affecting the overlay performance during annealing treatment in GaAs wafer fabrication was conducted quantitatively using MONO-LITH software. The experimental results were decomposed as wafer translation, scaling at X and Y direction, rotation and orthogonality. The grid residual was used to describe non- correctable distortion of the wafers, which fits the equations given below: Residual equals Measured - Modeled, which is not a modeled component. The Vector Map displays distribution of error vectors over the wafer or field for various components or overall effect. Based on the component analysis that the misalignment caused by translation and scaling can be compensated by heat treatment if the wafer is placed at a favorable orientation. This can help mitigate the effects of substrate quality in manufactory.

  4. Effect of surfactant on removal of particle contamination on Si wafers in ULSI

    Institute of Scientific and Technical Information of China (English)

    TAN Bai-mei; LI Wei-wei; NIU Xin-huan; WANG Sheng-li; LIU Yu-ling

    2006-01-01

    The adsorption mechanism of particle on the surface of silicon wafer after polishing or grinding whose surface force field is very strong was discussed,and the removal method of particle was studied. Particle is deposited on the wafer surface by interactions,mainly including the Van der Waals forces and static forces. In order to suppress particles depositing on the wafer surface,it is essential that the wafer surface and the particles should have the same polarity of the zeta potential. According to colloid chemistry and lots of experiments,this can be achieved by adding surfactants. Nonionic complex surfactant was used as megasonic cleaning solution,and the adsorptive state of particle on Si wafers was effectively controlled. The efficiency and effect of megasonic particle removal is greatly improved. A perfect result is also obtained in wafer cleaning.

  5. Network analyzer calibration for cryogenic on-wafer measurements

    Energy Technology Data Exchange (ETDEWEB)

    Hietala, V.M.; Housel, M.S.; Caldwell, R.B.

    1994-04-01

    A cryogenic probe station for on-wafer microwave measurements has been developed at Sandia National Laboratories to explore the basic device physics and characterize advanced components for low-temperature applications. The station was designed to operate over a temperature range of 20 to 300 K with a frequency range of DC to 50 GHz. Due to the vacuum and the low temperature environment, the use of microwave probes and the calibration of network analyzer measurements are somewhat elaborate. This paper presents guidelines for probe use and calibration in this environment.

  6. PEMANFAATAN KLOBOT JAGUNG SEBAGAI WAFER RANSUM KOMPLIT UNTUK DOMBA

    Directory of Open Access Journals (Sweden)

    YULI RETNANI

    2012-09-01

    Full Text Available ABSTRAK Limbah pertanian pada umumnya memiliki kandungan protein, kecernaan, dan palatabilitas yang rendah disamping itu sifatnya yang voluminous menyulitkan dalam penanganan, baik pada saat transportasi maupun penyimpanannya, sehingga memerlukan suatu cara untuk meningkatkan nilai guna limbah pertanian. Klobot jagung merupakan salah satu limbah yang dapat dimanfaatkan sebagai sumber serat, karena kandungan seratnya tinggi yaitu sebesar 32%. Kendala yang dihadapi dalam penggunaan klobot jagung sebagai pakan ternak yaitu sifatnya yang voluminous, sehingga masih belum banyak dimanfaatkan sebagai pakan ternak. Untuk memudahkan penyimpanan dan menjaga ketersediaannya maka klobot jagung dimanfaatkan dengan pengolahan fisik dalam bentuk wafer. Tujuan penelitian ini untuk mengetahui taraf terbaik dari klobot jagung yang dapat digunakan sebagai substitusi sumber serat pengganti rumput lapang di dalam wafer ransum komplit untuk domba ditinjau dari kualitas sifat fisik yaitu kadar air, kerapatan wafer, daya serap air, dan palatabilitas. Rancangan percobaan yang digunakan adalah rancangan acak lengkap (RAL dengan 4 perlakuan dan 3 ulangan. Perlakuan yang dicobakan adalah: ransum yang mengandung 30% rumput lapang + 70% konsentrat (R1; ransum yang mengandung 20% rumput lapang + 10% klobot jagung + 70% konsentrat (R2; ransum yang mengandung 10% rumput lapang + 20% klobot jagung + 70% konsentrat (R3; dan ransum yang mengandung 30% klobot jagung + 70% konsentrat (R4. Variabel yang diukur adalah kandungan air, densitas, penyerapan air, dan palatabitas dari wafer klobot jagung. Hasil penelitian menunjukkan bahwa perlakuan R2 dan R3 berpengaruh terhadap kandungan air (p<0,05. Perlakuan R2, R3, dan R4 berpengaruh sangat nyata terhadap daya serap air (p<0,01, tetapi tidak berpengaruh terhadap densitas. Nilai kandungan air berkisar antara 9,39%-12,61%, dan nilai densitas berkisar antara 0,70 g/cm3-0,75 g/cm3, sedangkan nilai palatabilitas wafer berkisar 550-885 g

  7. Characteristics of Si+/B+ dual implanted silicon wafers

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    Thin p+ layers with good electrical properties were fabricated by RTA (rapid thermal annealing) with post-FA (furance annealing) of Si+/B+ dual implanted silicon wafers. The electrical and structural characteristics of thin p+ layers have been measured by FPP (four-point probe), SRP (spreading resistance probe), RBS/channelling. Optimizing the implantation and annealing processes, especially using the thermal cycle of RTA followed by FA, shallow p+n junctions can be fabricated, which shows excellent I-V characteristics with revers-bias leakage current densities of 1.8?nA/cm2 at -1.4?V.

  8. Exploration of surface hydrophilic properties on AISI 304 stainless steel and silicon wafer against aging after atmospheric pressure plasma treatment

    Science.gov (United States)

    Chuang, Shang-I.; Duh, Jenq-Gong

    2014-11-01

    The aim of this work is to seek the enhanced surface hydrophilic properties on AISI 304 stainless steel and silicon wafer after atmospheric pressure plasma treatment using a specifically designed atmospheric pressure plasma jet. The aging tendency of surface hydrophilic property under air is highlighted. It is concluded that both of the silicon wafer and stainless steel treated with plasma generated from supply gas of argon 15 slm mixed with oxygen 40 sccm shows a better tendency on remaining high water contact angle as compared to that with pure argon and nitrogen addition. Additional peaks of O I (777, 844 nm), O II (408 nm) are detected by optical emission spectroscope indicating the presence of the oxygen radicals and ionic species, which interact with surfaces and thus contribute to low water contact angle (WCA) surfaces. Moreover, the result acquired from X-ray photoelectron spectroscopy (XPS) indicates that the increase in the oxygen-related bonding exhibits a better contribution on remaining high surface energy over a period of time.

  9. DRIE fabrication of notch-free silicon structures using a novel silicon-on-patterned metal and glass wafer

    Science.gov (United States)

    Kim, Ki Hoon; Kim, Sang Cheol; Park, Kyu Yeon; Yang, Sang Sik

    2011-04-01

    This paper presents a method of fabricating a silicon structure without notches using a new kind of substrate consisting of silicon-on-patterned metal and glass (SOMG). It has a metal interlayer with a thickness of 0.1 µm between a silicon wafer and glass wafer as an insulation layer to eliminate the micro-charging effect on the insulation surface for the silicon dry etching process. This substrate is fabricated by anodic bonding and polishing. To ascertain the effect of the SOMG substrate, 100 µm deep silicon structures with 5 and 20 µm wide trenches have been etched on SOG (silicon-on-glass) and SOMG substrates under similar conditions. In order to perform the deep silicon etching process, a thick photoresist of AZ9260 is used as a dry etch mask. In the results, no notches are on SOMG, while notches occur on SOG. Also, regardless of the over-etching time as the dimensions of the area to be etched, no notches are formed at the bottom of the silicon structure. This results in a notchless silicon structure. This research shows the feasibility of applying this technique to many applications using silicon devices.

  10. Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging

    Science.gov (United States)

    Lee, Ju-Yong; Lee, Sung-Woo; Lee, Seung-Ki; Park, Jae-Hyoung

    2013-08-01

    We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 mΩ. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test.

  11. Selected applications of photothermal and photoluminescence heterodyne techniques for process control in silicon wafer manufacturing

    Science.gov (United States)

    Ehlert, Andreas; Kerstan, Michael; Lundt, Holger; Huber, Anton; Helmreich, Dieter; Geiler, Hans-Dieter; Karge, Harald; Wagner, Matthias

    1997-02-01

    Two noncontact laser-based heterodyne techniques, photothermal heterodyne (PTH) and photoluminescence heterodyne (PLH), are introduced and applied to processing and quality control in silicon wafer manufacturing. The crystallographic characteristics of process-induced defects in silicon wafers are suitable for the application of PTH and PLH techniques, which are demonstrated on selected examples from different steps of silicon wafer production. Both PLH and PTH techniques meet the demand for nondestructive and on-line-suitable measurement in the semiconductor industry.

  12. Optical characterization of double-side-textured silicon wafer based on photonic nanostructures for thin-wafer crystalline silicon solar cells

    Science.gov (United States)

    Tayagaki, Takeshi; Furuta, Daichi; Aonuma, Osamu; Takahashi, Isao; Hoshi, Yusuke; Kurokawa, Yasuyoshi; Usami, Noritaka

    2017-04-01

    Crystalline silicon (c-Si) wafers have found extensive use in photovoltaic applications. In this regard, to enable advanced light manipulation in thin-wafer c-Si solar cells, we demonstrate the fabrication of double-side-textured Si wafers composed of a front-surface photonic nanotexture fabricated with quantum dot arrays and a rear-surface microtexture. The addition of the rear-surface microtexture to a Si wafer with the front-surface photonic nanotexture increases the wafer’s optical absorption in the near-infrared region, thus enabling enhanced light trapping. Excitation spectroscopy reveals that the photoluminescence intensity in the Si wafer with the double-sided texture is higher than that in the Si wafer without the rear-surface microtexture, thus indicating an increase in true optical absorption in the Si wafer with the double-sided texture. Our results indicate that the double-sided textures, i.e., the front-surface photonic nanotexture and rear-surface microtexture, can effectively reduce the surface reflection loss and provide enhanced light trapping, respectively.

  13. Improved quality control of silicon wafers using novel off-line air pocket image analysis

    Science.gov (United States)

    Valley, John F.; Sanna, M. Cristina

    2014-08-01

    Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented, APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during wafer manufacturing.

  14. Growth of Catalyst-Free Epitaxial InAs Nanowires on Si Wafers Using Metallic Masks.

    Science.gov (United States)

    Soo, M Teng; Zheng, Kun; Gao, Qiang; Tan, H Hoe; Jagadish, Chennupati; Zou, Jin

    2016-07-13

    Development of heteroepitaxy growth of catalyst-free vertical III-V nanowires on Si wafers is highly desirable for future nanoscale Si-based electronic and optoelectronic devices. In this study, a proof-of-concept approach is developed for catalyst-free heteroepitaxy growth of InAs nanowires on Si wafers. Before the growth of InAs nanowires, a Si-compatible metallic film with a thickness of several tens of nanometers was predeposited on a Si wafer and then annealed to form nanosize openings so as to obtain a metallic mask. These nano-openings exposed the surface of the Si wafer, which allowed subsequent nucleation and growth of epitaxial InAs nanowires directly on the surface of the Si wafer. The small size of the nano-openings limits the lateral growth of the nanostructures but promotes their axial growth. Through this approach, catalyst-free InAs nanowires were grown on both Si (111) and (001) wafers successfully at different growth temperatures. In particular, ultralong defect-free InAs nanowires with the wurtzite structure were grown the Si (111) wafers at 550 °C using the Ni mask. This study offers a simple, cost-effective, and scalable method to grow catalyst-free III-V nanowires on Si wafers. The simplicity of the approach opens a new avenue for the growth and integration of catalyst-free high-quality heteroepitaxial III-V nanowires on Si wafers.

  15. Effect of internal stresses on the mechanical parameters of silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Oksanich, A.P.; Cherner, V.M.; Tuzovskii, K.A.

    1988-12-01

    The authors examined how the mechanical parameters of silicon wafers vary with the stress area. The polished (100) wafers were cut from a billet grown by Czochralski's method. The internal stresses were produced by moving the wafers in and out of an oven having a working zone at 1420 K. Then the oxide film was removed. The area of the stressed parts was determined by photoelasticity. The mechanical parameters were measured with contactless pneumatic loading and continuous central deflection measurement. The internal stresses affect the properties; at a given load the central deflection in an unstressed wafer is larger than in a stressed one.

  16. Determination of wafer center position during the transfer process by using the beam-breaking method

    Science.gov (United States)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-09-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human-machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions.

  17. Fabrication of micro-nano composite textured surface for slurry sawn mc-Si wafers cell

    Science.gov (United States)

    Niu, Y. C.; liu, Z.; Ren, X. K.; Liu, X. J.; Liu, H. T.; Jiang, Y. S.

    2017-01-01

    In order to enhance the PV efficiency of the cell made from slurry sawn (SS) mc-Si wafers, using a Ag-assisted electroless etching (AgNO3+HF+H2O2) combined with an auxiliary etching (HF+HNO3) the RENA textured SS mc-Si wafers (called as RENA wafers) were further textured (nano pores were formed on the original micro pits) to change into micro-nano composite textured wafers (called as MN-RENA wafers). The solar cells made from the MN-RENA wafers had a better PV efficiency than that of RENA wafers. This is mainly attributed to the higher light-trapping of the micro-nano composite texture. The nano size texture enhanced the light-trap of wafer surface and, at the same time, the micro size texture maintained the light-trap uniformity of different gains of RENA wafer. However, there still exist a potential for optimization, such as, the SiNx passviation coating should be improved to be deposited more uniformly in order to passivate the bottom of pits better and to reduce the reflectance of the obtuse tips of pits.

  18. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  19. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

    Directory of Open Access Journals (Sweden)

    Bo Xie

    2015-09-01

    Full Text Available This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months, a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

  20. Residual stress in silicon wafer using IR polariscope

    Science.gov (United States)

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  1. Implementation of high-resolution reticle inspection in wafer fabs

    Science.gov (United States)

    Dayal, Aditya; Bergmann, Nathan M.; Sanchez, Peter

    2003-05-01

    Many advanced wafer fabs are currently fabricating devices with 130nm or smaller design rules. To meet the challenges at these sub-wavelength technology nodes, fabs are using a variety of resolution enhancement techniques (RETs) in lithography and exploring new methods of processing, inspecting and requalifying photomasks. The acceleration of the lithography roadmap imposes more stringent requirements on mask qualification and requalification to ensure that device yields are not compromised: mask inspection tools of today need to find smaller defects on reticles against considerably more complicated patterns or tighter critical dimensions (CDs). In this paper we describe the early stages of implementation and proliferation of advanced reticle inspection tools at high volume manufacturing wafer fabs. The fabs run incoming multi-surface contamination inspections on masks sent from the mask shop (Intel Mask Operations, IMO), and follow them up with periodic inspections/review to make sure any new contaminant or damage does not go undetected. When necessary, images of defects are electronically presented to engineers at IMO for review. Reticle requalification with these inspection tools reduces or eliminates the need for print test verification. We describe the tools and procedure used to streamline reticle requalification at the fabs and improve the feedback loop between the fabs and the mask shop.

  2. Understanding Bonds - Denmark

    DEFF Research Database (Denmark)

    Rimmer, Nina Røhr

    2016-01-01

    a specified rate of interest during the life of the bond and to repay the face value of the bond (the principal) when it “matures,” or comes due. Among the types of bonds you can choose from are: Government securities, municipal bonds, corporate bonds, mortgage and asset-backed securities, federal agency...

  3. Penggunaan Limbah Kopi Sebagai Bahan Penyusun Ransum Itik Peking dalam Bentuk Wafer Ransum Komplit

    Directory of Open Access Journals (Sweden)

    Muhammad Daud

    2013-04-01

    Full Text Available Effect of coffee waste as component of compiler ration peking duck in the form of wafer complete ration ABSTRACT. Coffee waste is a by-product of coffee processing that potential to be used as feed stuff for peking duck. The weakness of this coffee waste, among others, is perishable, voluminous (bulky and the availability was fluctuated so the processing technology is needed to make this vegetable waste to be durable, easy to stored and to be given to livestock. To solve this problem vegetable waste could be formed as wafer. This research was conducted to study effectiveness of coffee waste as component of compiler ration peking duck in the form of wafer complete ration This experiment was run in completely randomized design which consist of 4 feed treatment and 3 replications.  Ration used was consisted of  P0 = wafer complete ration 0% coffee waste (control, P1 = wafer complete ration 2,5% coffee waste, P2 = wafer complete ration 5% coffee waste, and P3 = Wafer complete ration 7,5% coffee waste. The Variables observed were: physical characteristic (aroma, color, and wafer density and palatability of wafer complete ration. Data collected was analyzed with ANOVA and Duncan Range Test would be used if the result was significantly different. The result showed that the density of wafer complete ration coffee waste was significantly (P< 0.05 differences between of treatment. Mean density wafer complete ration equal to: P0= 0,52±0,03, P1 =0,67±0,04, P2 =0,72±0,03, and P3 = 0,76±0.05 g/cm3. Wafer complete ration coffee waste palatability was significantly (P< 0.05 differences between of treatment. It is concluded that of wafer complete ration composition 5 and 7,5% coffee waste was significantly wafer palatability and gave a highest wafer density. The ration P0 was the most palatable compare to other treatments for the experimental peking duck.

  4. Penggunaan Limbah Kopi Sebagai Bahan Penyusun Ransum Itik Peking dalam Bentuk Wafer Ransum Komplit

    Directory of Open Access Journals (Sweden)

    Muhammad Daud

    2013-04-01

    Full Text Available Effect of coffee waste as component of compiler ration peking duck in the form of wafer complete ration ABSTRACT. Coffee waste is a by-product of coffee processing that potential to be used as feed stuff for peking duck. The weakness of this coffee waste, among others, is perishable, voluminous (bulky and the availability was fluctuated so the processing technology is needed to make this vegetable waste to be durable, easy to stored and to be given to livestock. To solve this problem vegetable waste could be formed as wafer. This research was conducted to study effectiveness of coffee waste as component of compiler ration peking duck in the form of wafer complete ration This experiment was run in completely randomized design which consist of 4 feed treatment and 3 replications.  Ration used was consisted of  P0 = wafer complete ration 0% coffee waste (control, P1 = wafer complete ration 2,5% coffee waste, P2 = wafer complete ration 5% coffee waste, and P3 = Wafer complete ration 7,5% coffee waste. The Variables observed were: physical characteristic (aroma, color, and wafer density and palatability of wafer complete ration. Data collected was analyzed with ANOVA and Duncan Range Test would be used if the result was significantly different. The result showed that the density of wafer complete ration coffee waste was significantly (P< 0.05 differences between of treatment. Mean density wafer complete ration equal to: P0= 0,52±0,03, P1 =0,67±0,04, P2 =0,72±0,03, and P3 = 0,76±0.05 g/cm3. Wafer complete ration coffee waste palatability was significantly (P< 0.05 differences between of treatment. It is concluded that of wafer complete ration composition 5 and 7,5% coffee waste was significantly wafer palatability and gave a highest wafer density. The ration P0 was the most palatable compare to other treatments for the experimental peking duck.

  5. LiTaO3/Silicon Composite Wafers for the Fabrication of Low Loss Low TCF High Coupling Resonators for Filter Applications

    Science.gov (United States)

    Ballandras, S.; Courjon, E.; Baron, T.; Moulet, J.-B.; Signamarcheix, T.; Daniau, W.

    SAW devices are widely used for radio-frequency (RF) telecommunication filtering and the number of SAW filters, resonators or duplexers is still increasing in RF stage of cellular phones. Therefore, a strong effort is still dedicated to reduce as much as possible their sensitivity to environmental parameter and more specifically to temperature. Bounding processes have been developed at FEMTO-ST and CEA-LETI using either Au/Au or direct bonding techniques for the fabrication of composite wafers combining materials with very different thermoelastic properties, yielding innovative solutions for about-zero temperature coefficient of frequency (TCF) bulk acoustic wave devices. In the present work, this approach has been applied to (YXl)/42∘ lithium tantalate plates, bounded onto (100) silicon wafers and thinned down to 25 μm. The leading idea already explored by other groups as mentioned in introduction consists in impeding the thermal expansion of the piezoelectric material using silicon limited expansion. 2 GHz resonators have been built on such plates and tested electrically and thermally, first by tip probing. A dramatic reduction of the TCF is observed for all the tested devices, allowing to reduce the thermal drift of the resonators down to a few ppm.K-1 within the standard temperature range. We then propose an analysis of the frequency-temperature behavior of the device to improve the resonator design to use these wafers for industrial applications.

  6. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    Energy Technology Data Exchange (ETDEWEB)

    Bai, Fan; Li, Meicheng, E-mail: mcli@ncepu.edu.cn [Harbin Institute of Technology, School of Materials Science and Engineering (China); Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing [North China Electric Power University, State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources, School of Renewable Energy (China)

    2013-09-15

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO{sub 2} produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO{sub 2} located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications.

  7. Charge carrier Density Imaging / IR lifetime mapping of Si wafers by Lock-In Thermography

    NARCIS (Netherlands)

    Van der Tempel, L.

    2012-01-01

    ABSTRACT Minority carrier lifetime imaging by lock-in thermography of passivated silicon wafers for photovoltaic cells has been developed for the public Pieken in de Delta project geZONd. CONCLUSIONS Minority carrier lifetime imaging by lock-in thermography of passivatedsilicon wafers is released

  8. Charge carrier Density Imaging / IR lifetime mapping of Si wafers by Lock-In Thermography

    NARCIS (Netherlands)

    Van der Tempel, L.

    2012-01-01

    ABSTRACT Minority carrier lifetime imaging by lock-in thermography of passivated silicon wafers for photovoltaic cells has been developed for the public Pieken in de Delta project geZONd. CONCLUSIONS Minority carrier lifetime imaging by lock-in thermography of passivatedsilicon wafers is released t

  9. Tunable Vertical-Cavity Surface-Emitting Lasers Integrated with Two Wafers

    Institute of Scientific and Technical Information of China (English)

    REN Xiu-Juan; GUAN Bao-Lu; GUO Shuai; LI Shuo; LI Chuan-Chuan; HAO Cong-Xia; ZHOU Hong-Yi; GUO Xiao

    2011-01-01

    A novel two-wafer concept for micro-electro-mechanically tunable vertical cavity surface emitting lasers (VCSELs)is presented. The VCSEL is composed by two wafers: one micro-electromechanical-system membrane wafer with four arms to adjust the cavity length through electrostatic actuation and a "half-VCSEL" wafer consisting of a fixed bottom mirror and an amplifying active region. The measurement results of the electricity pumped tunable VCSEL with more than 9mW output power at room temperature over the tuning range prove the feasibility of the proposition.%@@ A novel two-wafer concept for micro-electro-mechanically tunable vertical cavity surface emitting lasers (VCSELs) is presented.The VCSEL is composed by two wafers: one micro-electromechanical-system membrane wafer with four arms to adjust the cavity length through electrostatic actuation and a "half-VCSEL" wafer consisting of a fixed bottom mirror and an amplifying active region.The measurement results of the electricity pumped tunable VCSEL with more than 9mW output power at room temperature over the tuning range prove the feasibility of the proposition.

  10. Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

    DEFF Research Database (Denmark)

    Mackenzie, David; Buron, Jonas Christian Due; Whelan, Patrick Rebsdorf;

    2015-01-01

    Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140......-effect mobility, doping level, on–off ratio, and conductance minimum before and after laser ablation fabrication....

  11. In-plane shear piezoelectric wafer active sensor phased arrays for structural health monitoring

    Science.gov (United States)

    Wang, Wentao; Zhou, Wensong; Wang, Peng; Wang, Chonghe; Li, Hui

    2016-04-01

    This paper proposes a new way for guided wave structural health monitoring using in-plane shear (d36 type) piezoelectric wafer active sensors phased arrays. Conventional piezoelectric wafer active sensors phased arrays based on inducing into specific Lamb wave modes (d31 type) has already widely used for health monitoring of the thin-wall structures. Rather than Lamb wave modes, the in-plane shear piezoelectric wafer active sensors phased arrays induces in-plane shear horizontal (SH) guided waves. The SH guided waves are distinct with the Lamb waves with simple waveform and less additional converted wave modes and the zero symmetric mode (SH0) is non-dispersive. In this paper, the advantage of the shear horizontal wave and the in-plane shear piezoelectric wafers capability to generate SH waves is first reviewed. Then finite element analysis of a 4-in-plane shear wafer active sensors phased array embedded on a rectangular aluminium plate is performed. In addition, numerical simulations with respect to creaks with different sizes as well as locations are implemented by the in-plane shear wafer active sensors phased array. For comparison purposes, the same numerical simulations using the conventional piezoelectric wafer active sensors phased arrays are also employed at the same time. Results indicate that the in-plane shear (d36 type) piezoelectric wafer active sensors phased arrays has the potential to identify damage location and assess damage severity in structural health monitoring.

  12. Heat transport in cold-wall single-wafer low pressure chemical-vapor-deposition reactors

    NARCIS (Netherlands)

    Hasper, A.; Schmitz, J.E.J.; Holleman, J.; Verweij, J.F.

    1992-01-01

    A model is formulated to understand and predict wafer temperatures in a tungsten low pressure chemical‐vapor‐deposition (LPCVD) single‐wafer cold‐wall reactor equipped with hot plate heating. The temperature control is usually carried out on the hot plate temperature. Large differences can occur

  13. Improved wafer-scale fabrication of aligned pdms-glass microchips with integrated electrodes

    NARCIS (Netherlands)

    Li, J.; Le Gac, S.; Berg, van den A.; Viovy, J.L.; Tabeling, P.; Descroix, S.; Malaquin, L.

    2007-01-01

    We report an improved fabrication process of PDMS-based hybrid chips at the scale of a whole wafer and including an alignment step. This implies a control of the dimension variations of this elastomer upon temperature changes and the production of a PDMS wafer compatible with the use of standard ali

  14. PMMA to SU-8 Bonding for Polymer Based Lab-on -a-chip Systems with Integrated Optics

    DEFF Research Database (Denmark)

    Clausen, Bjarne

    2003-01-01

    An adhesive bonding technique for wafer-level sealing of SU-8 based lab-on-a-chip microsystems with integrated optical components is presented. Microfluidic channels and optical components, e.g. waveguides, are fabricated in cross-linked SU-8 and sealed with a Pyrex glass substrate by means...

  15. Temperature Uniformity of Wafer on a Large-Sized Susceptor for a Nitride Vertical MOCVD Reactor

    Institute of Scientific and Technical Information of China (English)

    LI Zhi-Ming; JIANG Hai-Ying; HAN Yan-Bin; LI Jin-Ping; YIN Jian-Qin; ZHANG Jin-Cheng

    2012-01-01

    The effect of coil location on wafer temperature is analyzed in a vertical MOCVD reactor by induction heating.It is observed that the temperature distribution in the wafer with the coils under the graphite susceptor is more uniform than that with the coils around the outside wall of the reactor.For the case of coils under the susceptor,we find that the thickness of the susceptor,the distance from the coils to the susceptor bottom and the coil turns significantly affect the temperature uniformity of the wafer. An optimization process is executed for a 3-inch susceptor with this kind of structure,resulting in a large improvement in the temperature uniformity.A further optimization demonstrates that the new susceptor structure is also suitable for either multiple wafers or large-sized wafers approaching 6 and 8 inches.

  16. Stickers versus wafers: The value of resource in a public goods game with children

    Directory of Open Access Journals (Sweden)

    Phiética Raíssa Rodrigues da Silva

    Full Text Available Abstract We investigated how the type of resource, food (wafer or non-food (sticker, age and sex influence cooperation in children. 251 children were tested in a public goods game during eight rounds in two experimental conditions: wafer or sticker condition. Wafers were all of the same kind but stickers were varied. The results indicated that 1 older children donated more stickers than younger children, but they did not differ in relation to wafer donations; and 2 sticker donations remained high along the rounds, while wafer donations decreased. We propose that different strategies may be adopted according to the quality, particularly to the diversity of the resource used, and the cost of cooperation may be overcome when it is more advantageous to wait for a future reward.

  17. Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

    2009-07-01

    Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  18. Cross Shear Roll Bonding

    DEFF Research Database (Denmark)

    Bay, Niels; Bjerregaard, Henrik; Petersen, Søren. B;

    1994-01-01

    The present paper describes an investigation of roll bonding an AlZn alloy to mild steel. Application of cross shear roll bonding, where the two equal sized rolls run with different peripheral speed, is shown to give better bond strength than conventional roll bonding. Improvements of up to 20......-23% in bond strength are found and full bond strength is obtained at a reduction of 50% whereas 65% is required in case of conventional roll bonding. Pseudo cross shear roll bonding, where the cross shear effect is obtained by running two equal sized rolls with different speed, gives the same results....

  19. Study on localized induction heating for wafer level packaging

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    Micro-electro-mechanical systems(MEMS)are being developed as a new multi-disciplinary technology,which will undoubtedly have a revolutionary impact on the future of human life.However,with the development of MEMS technology,the packaging has become the main technical obstacle to the commercialization of MEMS.An approach to MEMS packaging by high-frequency electromagnetic induction heating at wafer level is presented in terms of numerical simulation and experimental study.The structure of inductor is firstly designed and optimized.Then the heating situation of PCB board is verified.The results indicate that the heat impact on the chip during the packaging process can be effectively reduced by local induction heating packaging,therefore the thermal stress on the chip is considerably lowered.This method can effectively improve the reliability of the MEMS devices.

  20. Ambient plasma treatment of silicon wafers for surface passivation recovery

    Science.gov (United States)

    Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

  1. Delineation of Crystalline Extended Defects on Multicrystalline Silicon Wafers

    Directory of Open Access Journals (Sweden)

    Mohamed Fathi

    2007-01-01

    Full Text Available We have selected Secco and Yang etch solutions for the crystalline defect delineation on multicrystalline silicon (mc-Si wafers. Following experimentations and optimization of Yang and Secco etching process parameters, we have successfully revealed crystalline extended defects on mc-Si surfaces. A specific delineation process with successive application of Yang and Secco agent on the same sample has proved the increased sensitivity of Secco etch to crystalline extended defects in mc-Si materials. The exploration of delineated mc-Si surfaces indicated that strong dislocation densities are localized mainly close to the grain boundaries and on the level of small grains in size (below 1 mm. Locally, we have observed the formation of several parallel dislocation lines, perpendicular to the grain boundaries. The overlapping of several dislocations lines has revealed particular forms for etched pits of dislocations.

  2. Patterned wafer inspection using spatial filtering for the cluster environment.

    Science.gov (United States)

    Taubenblatt, M A; Batchelder, J S

    1992-06-10

    Automated-process tool clusters are becoming increasingly prevalent in advanced semiconductor manufacturing plants, necessitating integrated inspection of patterned semiconductor wafers for defects and particulates. Integrated inspection tools must be small, sensitive, inexpensive, and fast in order to be compatible with the cluster environment. We show that intensity spatial filtering, with some refinements, can provide the required sensitivity and speed in a small, inexpensive package. By using dark-field illumination and a nonrectangular azimuthal orientation (e.g., 45 degrees ) to the primarily rectangular pattern, we show that the strongest diffraction from the pattern can be made to bypass the optical system entirely. This technique alleviates stringent scatter and antireflection requirements on the optics, and it permits the use of off-the-shelf components.

  3. Fabrication of PIN diode detectors on thinned silicon wafers

    CERN Document Server

    Ronchin, Sabina; Dalla Betta, Gian Franco; Gregori, Paolo; Guarnieri, Vittorio; Piemonte, Claudio; Zorzi, Nicola

    2004-01-01

    Thin substrates are one of the possible choices to provide radiation hard detectors for future high-energy physics experiments. Among the advantages of thin detectors are the low full depletion voltage, even after high particle fluences, the improvement of the tracking precision and momentum resolution and the reduced material budget. In the framework of the CERN RD50 Collaboration, we have developed p-n diode detectors on membranes obtained by locally thinning the silicon substrate by means of tetra-methyl ammonium hydroxide etching from the wafer backside. Diodes of different shapes and sizes have been fabricated on 57 and 99mum thick membranes. They have been tested, showing a very low leakage current ( less than 0.4nA/cm**2) and, as expected, a very low depletion voltage ( less than 1V for the 57mum membrane). The paper describes the technological approach used for devices fabrication and reports selected results from the electrical characterization.

  4. Time-varying wetting behavior on copper wafer treated by wet-etching

    Energy Technology Data Exchange (ETDEWEB)

    Tu, Sheng-Hung; Wu, Chuan-Chang [Department of Chemical and Materials Engineering, National Central University, Jhongli 320, Taiwan, ROC (China); Wu, Hsing-Chen [Advanced Technology Materials Inc, Hsinchu 310, Taiwan, ROC (China); Cheng, Shao-Liang [Department of Chemical and Materials Engineering, National Central University, Jhongli 320, Taiwan, ROC (China); Sheng, Yu-Jane, E-mail: yjsheng@ntu.edu.tw [Department of Chemical Engineering, National Taiwan University, Taipei 106, Taiwan, ROC (China); Tsao, Heng-Kwong, E-mail: hktsao@cc.ncu.edu.tw [Department of Chemical and Materials Engineering, National Central University, Jhongli 320, Taiwan, ROC (China)

    2015-06-30

    Graphical abstract: - Highlights: • A thin oxide layer always remains on surfaces of Cu wafers after aqueous etching. • A pure Cu wafer is obtained by the HAc treatment and the water CA is about 45°. • The oxide layer and CA grow with time after the Cu wafer is exposed to air. • Surface roughness and hydrophobicity of pure Cu wafers grow rapidly in vacuum. - Abstract: The wet cleaning process in semiconductor fabrication often involves the immersion of the copper wafer into etching solutions and thereby its surface properties are significantly altered. The wetting behavior of a copper film deposited on silicon wafer is investigated after a short dip in various etching solutions. The etchants include glacial acetic acid and dilute solutions of nitric acid, hydrofluoric acid, and tetramethylammonium hydroxide. It was found that in most cases a thin oxide layer still remains on the surface of as-received Cu wafers when they are subject to etching treatments. However, a pure Cu wafer can be obtained by the glacial acetic acid treatment and its water contact angle (CA) is about 45°. As the pure Cu wafer is placed in the ambient condition, the oxide thickness grows rapidly to the range of 10–20 Å within 3 h and the CA on the hydrophilic surface also rises. In the vacuum, it is surprising to find that the CA and surface roughness of the pure Cu wafer can grow significantly. These interesting results may be attributed to the rearrangement of surface Cu atoms to reduce the surface free energy.

  5. Wire bonding in microelectronics

    CERN Document Server

    Harman, George G

    2010-01-01

    Wire Bonding in Microelectronics, Third Edition, has been thoroughly revised to help you meet the challenges of today's small-scale and fine-pitch microelectronics. This authoritative guide covers every aspect of designing, manufacturing, and evaluating wire bonds engineered with cutting-edge techniques. In addition to gaining a full grasp of bonding technology, you'll learn how to create reliable bonds at exceedingly high yields, test wire bonds, solve common bonding problems, implement molecular cleaning methods, and much more. Coverage includes: Ultrasonic bonding systems and technologies, including high-frequency systems Bonding wire metallurgy and characteristics, including copper wire Wire bond testing Gold-aluminum intermetallic compounds and other interface reactions Gold and nickel-based bond pad plating materials and problems Cleaning to improve bondability and reliability Mechanical problems in wire bonding High-yield, fine-pitch, specialized-looping, soft-substrate, and extreme-temperature wire bo...

  6. Validation of thermodesorption method for analysis of semi-volatile organic compounds adsorbed on wafer surface.

    Science.gov (United States)

    Hayeck, Nathalie; Gligorovski, Sasho; Poulet, Irène; Wortham, Henri

    2014-05-01

    To prevent the degradation of the device characteristics it is important to detect the organic contaminants adsorbed on the wafers. In this respect, a reliable qualitative and quantitative analytical method for analysis of semi-volatile organic compounds which can adsorb on wafer surfaces is of paramount importance. Here, we present a new analytical method based on Wafer Outgassing System (WOS) coupled to Automated Thermal Desorber-Gas chromatography-Mass spectrometry (ATD-GC-MS) to identify and quantify volatile and semi-volatile organic compounds from 6", 8" and 12" wafers. WOS technique allows the desorption of organic compounds from one side of the wafers. This method was tested on three important airborne contaminants in cleanroom i.e. tris-(2-chloroethyl) phosphate (TCEP), tris-(2-chloroisopropyl) phosphate (TCPP) and diethyl phthalate (DEP). In addition, we validated this method for the analysis and quantification of DEP, TCEP and TCPP and we estimated the backside organic contamination which may contribute to the front side of the contaminated wafers. We are demonstrating that WOS/ATD-GC-MS is a suitable and highly efficient technique for desorption and quantitative analysis of organophosphorous compounds and phthalate ester which could be found on the wafer surface.

  7. Surface shape control of the workpiece in a double-spindle triple-workstation wafer grinder

    Institute of Scientific and Technical Information of China (English)

    Zhu Xianglong; Kang Renke; Dong Zhigang; Feng Guang

    2011-01-01

    Double-spindle triple-workstation (DSTW) ultra precision grinders are mainly used in production lines for manufacturing and back thinning large diameter (≥ 300 mm) silicon wafers for integrated circuits.It is important,but insufficiently studied,to control the wafer shape ground on a DSTW grinder by adjusting the inclination angles of the spindles and work tables.In this paper,the requirements of the inclination angle adjustment of the grinding spindles and work tables in DSTW wafer grinders are analyzed.A reasonable configuration of the grinding spindles and work tables in DSTW wafer grinders are proposed.Based on the proposed configuration,an adjustment method of the inclination angle of grinding spindles and work tables for DSTW wafer grinders is put forward.The mathematical models of wafer shape with the adjustment amount of inclination angles for both fine and rough grinding spindles are derived.The proposed grinder configuration and adjustment method will provide helpful instruction for DSTW wafer grinder design.

  8. Kajian Level Kadar Air dan Ukuran Partikel Bahan Pakan Terhadap Penampilan Fisik Wafer

    Directory of Open Access Journals (Sweden)

    Retno Iswarin Pujaningsih

    2013-04-01

    Full Text Available Study on the level of water content and particle size of feed ingredients to the physical appearance of wafer  ABSTRACT. This study attempted wafer manufacturing technology development of conventional feed ingredients. The benefit of wafer increase feed consumption and feed efficiency, increase the metabolizable energy content of the feed, kill pathogenic bacteria, reduce the amount of feed scattered, extending the storage time, ensure the balance of feed nutrients and vitamins to prevent oxidation. Research was continuing several research activities on wafer manufacturing technology that has been done and continues to be developed by the researchers. The long term goal of a series of research is to obtain basic information to the wafer manufacturing optimum quality and measurable. Specific target is to obtain basic information about the quality of the wafer on the level of water content and the use of a certain particle size. The research method used was experimental and analytical methods in the laboratory. The results showed that based on the test of physical qualities (moisture content, density, water absorption showed that the use of the level of moisture content up to 8% with a particle size of 10-20 mm feed material provides the best physical appearance of wafer.

  9. Sheet resistance uniformity in drive-in step for different multi-crystalline silicon wafer dispositions

    Energy Technology Data Exchange (ETDEWEB)

    Moussi, A.; Bouhafs, D.; Mahiou, L. [Laboratoire des Cellules Photovoltaiques, Unite de Developpement de la Technologie du Silicium, 2 Bd, Frantz Fanon, B.P. 140, 7 Merveilles Alger (Algeria); Belkaid, M.S. [Dep. Electronique, Faculte de Genie Electrique et Informatique, UMMTO (Algeria)

    2009-09-15

    In this work, we present a study of emitters realized using different configurations of the silicon wafers in the quartz boat. The phosphorous liquid source is sprayed onto p-type multi-crystalline silicon substrates and the drive-in is made at high temperature in a muffle furnace. Three different configurations of the wafers in the boat are tested: separated, back to back and compact block of wafers. A fourth configuration is also used in source-receptor mode. The emitter phosphorous concentration profile is obtained by SIMS analysis. The resulting emitters are characterized by sheet resistance measurements and a comparison is made between the wafers within the same batch and from one batch to another. The uniformity and the standard deviation of the sheet resistance are calculated in each case. The emitter sheet resistance mapping of the wafer set in the middle of the boat for a given process gives a mean R{sub sq} 14.66 {omega}/sq with a standard deviation of 1.76% and uniformity of 18.7%. Standard deviations of 2.116% and 1.559% are obtained for wafers in the batch when using the spaced and compact configurations, respectively. The standard deviation is reduced to 0.68% when the wafers are used in source/receptor mode. A comparison is also made between wafers with different dilution of phosphorous source in ethanol. From these results we can conclude that the compact configuration offers better uniformity and lower standard deviation. Furthermore, when combined with the source-receptor configuration these parameters are significantly improved. This study allows the experimenter to identify the technological parameters of the solar cell emitter manufacturing and target precisely the desired values of the sheet resistance while limiting the number of rejected wafers. (author)

  10. Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

    Science.gov (United States)

    Kasinski, Krzysztof; Zubrzycka, Weronika

    2016-09-01

    The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

  11. Characterization of perovskite layer on various nanostructured silicon wafer

    Science.gov (United States)

    Rostan, Nur Fairuz Mohd; Sepeai, Suhaila; Ramli, Noor Fadhilah; Azhari, Ayu Wazira; Ludin, Norasikin Ahmad; Teridi, Mohd Asri Mat; Ibrahim, Mohd Adib; Zaidi, Saleem H.

    2017-05-01

    Crystalline silicon (c-Si) solar cell dominates 90% of photovoltaic (PV) market. The c-Si is the most mature of all PV technologies and expected to remain leading the PV technology by 2050. The attractive characters of Si solar cell are stability, long lasting and higher lifetime. Presently, the efficiency of c-Si solar cell is still stuck at 25% for one and half decades. Tandem approach is one of the attempts to improve the Si solar cell efficiency with higher bandgap layer is stacked on top of Si bottom cell. Perovskite offers a big potential to be inserted into a tandem solar cell. Perovskite with bandgap of 1.6 to 1.9 eV will be able to absorb high energy photons, meanwhile c-Si with bandgap of 1.124 eV will absorb low energy photons. The high carrier mobility, high carrier lifetime, highly compatible with both solution and evaporation techniques makes perovskite an eligible candidate for perovskite-Si tandem configuration. The solution of methyl ammonium lead iodide (MAPbI3) was prepared by single step precursor process. The perovskite layer was deposited on different c-Si surface structure, namely planar, textured and Si nanowires (SiNWs) by using spin-coating technique at different rotation speeds. The nanostructure of Si surface was textured using alkaline based wet chemical etching process and SiNW was grown using metal assisted etching technique. The detailed surface morphology and absorbance of perovskite were studied in this paper. The results show that the thicknesses of MAPbI3 were reduced with the increasing of rotation speed. In addition, the perovskite layer deposited on the nanostructured Si wafer became rougher as the etching time and rotation speed increased. The average surface roughness increased from ˜24 nm to ˜38 nm for etching time range between 5-60 min at constant low rotation speed (2000 rpm) for SiNWs Si wafer.

  12. Development of a fixed abrasive slicing technique (FAST) for reducing the cost of photovoltaic wafers

    Energy Technology Data Exchange (ETDEWEB)

    Schmid, F. (Crystal Systems, Inc., Salem, MA (United States))

    1991-12-01

    This report examines a wafer slicing technique developed by Crystal Systems, Inc. that reduces the cost of photovoltaic wafers. This fixed, abrasive slicing technique (FAST) uses a multiwire bladepack and a diamond-plated wirepack; water is the coolant. FAST is in the prototype production stage and reduces expendable material costs while retaining the advantages of a multiwire slurry technique. The cost analysis revealed that costs can be decreased by making more cuts per bladepack and slicing more wafers per linear inch. Researchers studied the degradation of bladepacks and increased wirepack life. 21 refs.

  13. Enhanced photoluminescence from photonic crystal-coated GaN LED wafers

    Science.gov (United States)

    Rahman, F.; Khokhar, A. Z.

    2011-06-01

    This paper describes results of studies on photoluminescence from blue-emitting GaN LED wafers coated with a layer of synthetic opal photonic crystals. Commercial LED wafer material was used and samples were coated with thin films consisting of several layers of stacked spherical polystyrene balls. Various optical measurements were performed on these samples while they were excited with a 405 nm laser beam. Diffraction pattern due to the photonic crystal structure, showing the underlying six-fold symmetry, was recorded. The spectrum and angle-resolved intensity of photoluminescence were measured to understand the coupling of LED light with the grown photonic crystal structure on top of the wafer.

  14. Low-Temperature Silicon-to-Silicon Anodic Bonding Using Sodium-Rich Glass for MEMS Applications

    Science.gov (United States)

    Tiwari, Ruchi; Chandra, Sudhir

    2014-02-01

    In the present work, silicon-to-silicon anodic bonding has been accomplished using an intermediate sodium-rich glass layer deposited by a radiofrequency magnetron sputtering process. The bonding was carried out at low direct-current voltage of about 80 V at 365°C. The alkali ion (sodium) concentration in the deposited film, the surface roughness of the film, and the flatness of the silicon wafers were studied in detail and closely monitored to improve the bond strength of the bonded silicon wafers. The effect of chemical mechanical polishing (CMP) on the surface roughness of the deposited film was also investigated. The average roughness of the deposited film was found to be ~6 Å, being reduced to 2 Å after CMP. It was observed that the concentration of sodium ions in the deposited film varied significantly with the sputtering parameters. Scanning electron microscopy was used to obtain cross-sectional images of the bonded pair. The bonding energy of the bonded wafer pair was measured using the crack-opening method. The bonding energy was found to vary from 0.3 J/m2 to 2.1 J/m2 for different bonding conditions. To demonstrate the application of the process developed, a sealed cavity was created using the silicon-to-silicon anodic bonding technique, which can be used for fabrication of devices such as capacitive pressure sensors and Fabry- Perot-based pressure sensors. Also, a matrix of microwells was fabricated using this technique, which can be used in various biomicroelectromechanical system applications.

  15. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2017-05-10

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

  16. Fast wafer-level detection and control of interconnect reliability

    Science.gov (United States)

    Foley, Sean; Molyneaux, James; Mathewson, Alan

    2000-08-01

    Many of the technological advances in the semiconductor industry have led to dramatic increases in device density and performance in conjunction with enhanced circuit reliability. As reliability is improved, the time taken to characterize particular failure modes with traditional test methods is getting substantially longer. Furthermore, semiconductor customers expect low product cost and fast time-to-market. The limits of traditional reliability testing philosophies are being reached and new approaches need to be investigated to enable the next generation of highly reliable products to be tested. This is especially true in the area of IC interconnect, where significant challenges are predicted for the next decade. A number of fast, wafer level test methods exist for interconnect reliability evaluation. The relative abilities of four such methods to detect the quality and reliability of IC interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are bench-marked against conventional package level Median Time to Failure results. The Isothermal test method combine with SWEAT-type test structures is shown to be the most suitable combination for defect detection and interconnect reliability control over very short test times.

  17. Designing defect spins for wafer-scale quantum technologies

    Energy Technology Data Exchange (ETDEWEB)

    Koehl, William F. [Argonne National Lab. (ANL), Argonne, IL (United States); Univ. of Chicago, IL (United States); Seo, Hosung [Univ. of Chicago, IL (United States); Galli, Giulia [Argonne National Lab. (ANL), Argonne, IL (United States); Univ. of Chicago, IL (United States); Awschalom, David D. [Argonne National Lab. (ANL), Argonne, IL (United States); Univ. of Chicago, IL (United States)

    2015-11-27

    The past decade has seen remarkable progress in the development of the nitrogen-vacancy (NV) defect center in diamond, which is one of the leading candidates for quantum information technologies. The success of the NV center as a solid-state qubit has stimulated an active search for similar defect spins in other technologically important and mature semiconductors, such as silicon carbide. If successfully combined with the advanced microfabrication techniques available to such materials, coherent quantum control of defect spins could potentially lead to semiconductor-based, wafer-scale quantum technologies that make use of exotic quantum mechanical phenomena like entanglement. In this article, we describe the robust spin property of the NV center and the current status of NV center research for quantum information technologies. We then outline first-principles computational modeling techniques based on density functional theory to efficiently search for potential spin defects in nondiamond hosts suitable for quantum information applications. The combination of computational modeling and experimentation has proven invaluable in this area, and we describe the successful interplay between theory and experiment achieved with the divacancy spin qubit in silicon carbide.

  18. Evolution of grain structures during directional solidification of silicon wafers

    Science.gov (United States)

    Lin, H. K.; Wu, M. C.; Chen, C. C.; Lan, C. W.

    2016-04-01

    The evolution of grain structures, especially the types of grain boundaries (GBs), during directional solidification is crucial to the electrical properties of multicrystalline silicon used for solar cells. To study this, the electric molten zone crystallization (EMZC) of silicon wafers at different drift speeds from 2 to 6 mm/min was considered. It was found that orientation was dominant at the lower drift velocity, while orientation at the higher drift velocity. Most of the non-∑GBs tended to align with the thermal gradient, but some tilted toward the unfavorable grains having higher interfacial energies. On the other hand, the tilted ∑3GBs tended to decrease during grain competition, except at the higher speed, where the twin nucleation became frequent. The competition of grains separated by ∑GBs could be viewed as the interactions of GBs that two coherent ∑3n GBs turned into one ∑3nGB following certain relations as reported before. On the other hand, when ∑ GBs met non-∑ GBs, the non-∑ GBs remained which explained the decrease of ∑ GBs at the lower speed.

  19. Wafer back pressure control and optimization in the CMP process

    Institute of Scientific and Technical Information of China (English)

    Men Yanwu; Zhang Hui; Zhou Kai; Ye Peiqing

    2011-01-01

    Chemical mechanical polishing(CMP)is the most effective wafer global planarization technology.The CMP polishing head is one of the most important components,and zone back pressure control technology is used to design a new generation of polishing head.The quality of polishing not only depends on slurry,but also depends on the precise control of polishing pressures.During the CMP polishing process,the set pressure of each chamber is usually not the same and the presence of a flexible elastic diaphragm causes coupling effects.Because of the coupling effects,the identification of multi-chambers and pressure controls becomes complicated.To solve the coupling problem,this paper presents a new method of multi-chamber decoupled control,and then system identification and control parameter tuning are carried out based on the method.Finally,experiments of multichambers inflated at the same time are performed.The experimental results show that the presented decoupling control method is feasible and correct.

  20. Modified robust sliding-mode control method for wafer scanner

    Directory of Open Access Journals (Sweden)

    Yiguang Wang

    2015-03-01

    Full Text Available This article studies the precision motion control of a long-stroke reticle stage driven by the permanent magnet linear motor in wafer scanner. A robust sliding-mode control method is proposed for tracking the reference trajectory in the presence of un-modeled dynamics, parametric uncertainty and external disturbances including force ripple, cogging and friction in the controlled system. A modified sliding-mode term based on the variable structure technique for eliminating the tracking error is employed in the proposed control law. The system stability and tracking convergence of the closed-loop control system are guaranteed by Lyapunov theory theoretically. The feasibility and effectiveness of the proposed method are demonstrated by comparative experiments on a linear motion testbed. The experimental results show that better tracking performance can be achieved by the proposed method compared with the conventional proportional–integral–derivative method and it can be considered as a possible alternative in the precision motion control system.

  1. Wafer-Scale Microwire Transistor Array Fabricated via Evaporative Assembly.

    Science.gov (United States)

    Park, Jae Hoon; Sun, Qijun; Choi, Yongsuk; Lee, Seungwoo; Lee, Dong Yun; Kim, Yong Hoon; Cho, Jeong Ho

    2016-06-22

    One-dimensional (1D) nano/microwires have attracted significant attention as promising building blocks for various electronic and optical device applications. The integration of these elements into functional device networks with controlled alignment and density presents a significant challenge for practical device applications. Here, we demonstrated the fabrication of wafer-scale microwire field-effect transistor (FET) arrays based on well-aligned inorganic semiconductor microwires (indium-gallium-zinc-oxide (IGZO)) and organic polymeric insulator microwires fabricated via a simple and large-area evaporative assembly technique. This microwire fabrication method offers a facile approach to precisely manipulating the channel dimensions of the FETs. The resulting solution-processed monolithic IGZO microwire FETs exhibited a maximum electron mobility of 1.02 cm(2) V(-1) s(-1) and an on/off current ratio of 1 × 10(6). The appropriate choice of the polymeric microwires used to define the channel lengths enabled fine control over the threshold voltages of the devices, which were employed to fabricate high-performance depletion-load inverters. Low-voltage-operated microwire FETs were successfully fabricated on a plastic substrate using a high-capacitance ion gel gate dielectric. The microwire fabrication technique involving evaporative assembly provided a facile, effective, and reliable method for preparing flexible large-area electronics.

  2. Improvement of silicon direct bonding using surfaces activated by hydrogen plasma treatment

    CERN Document Server

    Choi, W B; Lee Jae Sik; Sung, M Y

    2000-01-01

    The plasma surface treatment, using hydrogen gas, of silicon wafers was studied as a pretreatment for silicon direct bonding. Chemical reactions of the hydrogen plasma with the surfaces were used for both surface activation and removal of surface contaminants. Exposure of the silicon wafers to the plasma formed an active oxide layer on the surface. This layer was hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposure time and power. The surface became smoother with shorter plasma exposure time and lower power. In addition, the plasma surface treatment was very efficient in removing the carbon contaminants on the silicon surface. The value of the initial surface energy, as estimated by using the crack propagation method, was 506 mJ/M sup 2 , which was up to about three times higher than the value for the conventional direct bonding method using wet chemical treatments.

  3. Diffusion length and resistivity distribution characteristics of silicon wafer by photoluminescence

    Energy Technology Data Exchange (ETDEWEB)

    Baek, Dohyun; Lee, Jaehyeong; Choi, Byoungdeog, E-mail: bdchoi@skku.edu

    2014-10-15

    Highlights: • Analytical photoluminescence efficiency calculation and PL intensity ratio method are developed. • Wafer resistivity and diffusion length characteristics are investigated by PL intensity ratio. • PL intensity is well correlated with resistivity, diffusion length or defect density on wafer measurement. - Abstract: Photoluminescence is a convenient, contactless method to characterize semiconductors. Its use for room-temperature silicon characterization has only recently been implemented. We have developed the PL efficiency theory as a function of substrate doping densities, bulk trap density, photon flux density, and reflectance and compared it with experimental data initially for bulk Si wafers. New developed PL intensity ratio method is able to predict the silicon wafer properties, such as doping densities, minority carrier diffusion length and bulk trap density.

  4. A study of defects on EUV mask using blank inspection, patterned mask inspection, and wafer inspection

    Energy Technology Data Exchange (ETDEWEB)

    Huh, S.; Ren, L.; Chan, D.; Wurm, S.; Goldberg, K. A.; Mochi, I.; Nakajima, T.; Kishimoto, M.; Ahn, B.; Kang, I.; Park, J.-O.; Cho, K.; Han, S.-I.; Laursen, T.

    2010-03-12

    The availability of defect-free masks remains one of the key challenges for inserting extreme ultraviolet lithography (EUVL) into high volume manufacturing. yet link data is available for understanding native defects on real masks. In this paper, a full-field EUV mask is fabricated to investigate the printability of various defects on the mask. The printability of defects and identification of their source from mask fabrication to handling were studied using wafer inspection. The printable blank defect density excluding particles and patterns is 0.63 cm{sup 2}. Mask inspection is shown to have better sensitivity than wafer inspection. The sensitivity of wafer inspection must be improved using through-focus analysis and a different wafer stack.

  5. Electron Optic Design of Arrayed E-Beam Microcolumns Based Systems for Wafer Defects Inspection

    CERN Document Server

    Kazmiruk, V V

    2008-01-01

    In this paper is considered a matter of the system for wafer defect inspection (WDIS) practical realization. Such systems are on the agenda as the next generation and substitution for light optics and single $e$-beam based WDISs.

  6. Electromagnetic field modeling for defect detection in 7 nm node patterned wafers

    Science.gov (United States)

    Zhu, Jinlong; Zhang, Kedi; Davoudzadeh, Nima; Wang, Xiaozhen; Goddard, Lynford L.

    2016-03-01

    By 2017, the critical dimension in patterned wafers will shrink down to 7 nm, which brings great challenges to optics-based defect inspection techniques, due to the ever-decreasing signal to noise ratio with respect to defect size. To continue pushing forward the optics-based metrology technique, it is of great importance to analyze the full characteristics of the scattering field of a wafer with a defect and then to find the most sensitive signal type. In this article, the vector boundary element method is firstly introduced to calculate the scattering field of a patterned wafer at a specific objective plane, after which a vector imaging theory is introduced to calculate the field at an image plane for an imaging system with a high numerical aperture objective lens. The above methods enable the effective modeling of the image for an arbitrary vectorial scattering electromagnetic field coming from the defect pattern of the wafer.

  7. Towards wafer scale inductive determination of magnetostatic and dynamic parameters of magnetic thin films and multilayers

    CERN Document Server

    Sievers, Sibylle; Nass, Paul; Serrano-Guisan, Santiago; Pasquale, Massimo; Schumacher, Hans Werner

    2013-01-01

    We investigate an inductive probe head suitable for non-invasive characterization of the magnetostatic and dynamic parameters of magnetic thin films and multilayers on the wafer scale. The probe is based on a planar waveguide with rearward high frequency connectors that can be brought in close contact to the wafer surface. Inductive characterization of the magnetic material is carried out by vector network analyzer ferromagnetic resonance. Analysis of the field dispersion of the resonance allows the determination of key material parameters such as the saturation magnetization MS or the effective damping parameter Meff. Three waveguide designs are tested. The broadband frequency response is characterized and the suitability for inductive determination of MS and Meff is compared. Integration of such probes in a wafer prober could in the future allow wafer scale in-line testing of magnetostatic and dynamic key material parameters of magnetic thin films and multilayers.

  8. Analysis of organic contaminants from silicon wafer and disk surfaces by thermal desorption-GC-MS

    Science.gov (United States)

    Camenzind, Mark J.; Ahmed, Latif; Kumar, Anurag

    1999-03-01

    Organic contaminants can affect semiconductor wafer processing including gate oxide integrity, polysilicon growth, deep ultraviolet photoresist line-width, and cleaning & etching steps. Organophosphates are known to counter dope silicon wafers. Organic contaminants in disk drives can cause failures due to stiction or buildup on the heads. Therefore, it is important to identify organic contaminants adsorbed on wafer or disk surfaces and find their sources so they can be either completely eliminated or at least controlled. Dynamic headspace TD-GC-MS (Thermal Desorption-Gas Chromatography-Mass Spectrometry) methods are very sensitive and can be used to identify organic contaminants on disks and wafers, in air, or outgassing from running drives or their individual components.

  9. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming

    2014-10-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  10. Large volume production of large size GaAs substrates and epitaxial wafers for microwave devices

    OpenAIRE

    Otoki, Y.; Kamogawa, H.; Ohnishi, M.; Inada, T.; Kashiwa, M.; Sakaguchi, H.

    1999-01-01

    Recent mass production techniques for LEC substrates and MOVPE wafers for microwave devices are described. Huge GaAs semi-insulating ingots (150mm diam., 310mm long) was obtained by Multi-hot-zone very large size pullar. Three step boule annealing and fully-automated process enabled mass production of the large size substrates. Epitaxiial wafers with abrupt hetero interface, excellent uniformity and reproducibility are producing largely by face down horizontal flow type MOVPE system, which ca...

  11. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    Science.gov (United States)

    Lin, YuPo J.; Henry, Michael P.; Snyder, Seth W.

    2008-11-18

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  12. A wafer mapping technique for residual stress in surface micromachined films

    Science.gov (United States)

    Schiavone, G.; Murray, J.; Smith, S.; Desmulliez, M. P. Y.; Mount, A. R.; Walton, A. J.

    2016-09-01

    The design of MEMS devices employing movable structures is crucially dependant on the mechanical behaviour of the deposited materials. It is therefore important to be able to fully characterize the micromachined films and predict with confidence the mechanical properties of patterned structures. This paper presents a characterization technique that enables the residual stress in MEMS films to be mapped at the wafer level by using microstructures released by surface micromachining. These dedicated MEMS test structures and the associated measurement techniques are used to extract localized information on the strain and Young’s modulus of the film under investigation. The residual stress is then determined by numerically coupling this data with a finite element analysis of the structure. This paper illustrates the measurement routine and demonstrates it with a case study using electrochemically deposited alloys of nickel and iron, particularly prone to develop high levels of residual stress. The results show that the technique enables wafer mapping of film non-uniformities and identifies wafer-to-wafer differences. A comparison between the results obtained from the mapping technique and conventional wafer bow measurements highlights the benefits of using a procedure tailored to films that are non-uniform, patterned and surface-micromachined, as opposed to simple standard stress extraction methods. The presented technique reveals detailed information that is generally unexplored when using conventional stress extraction methods such as wafer bow measurements.

  13. Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage

    Science.gov (United States)

    Zhu, Chunsheng; Ning, Wenguo; Xu, Gaowei; Luo, Le

    2014-09-01

    Polyimide is widely used as the dielectric material in wafer level packaging. One potential problem with its application is the warpage and stress generated in the curing process. This paper investigated the material properties of polyimide and its influence on the wafer warpage. The viscoelastic properties of polyimide film were measured and a mathematical model of the properties was developed. Finite element analysis of the wafer warpage was performed and this indicates that the viscoelastic material model gave the best prediction. To better understand the causation of the warpage, curvature evolution of the polyimide-coated silicon wafer during its curing process was measured by a multi-beam optical sensor system. It was found that the warpage was mainly induced by the coefficient of thermal expansion mismatch and that the cure shrinkage of polyimide had little effect. Additionally, the effect of the cooling rate on the wafer warpage was also studied. Both simulation and experiment results showed that a slower cooling rate in the temperature range around the glass transition temperature ( T g) of polyimide will help to reduce the final wafer warpage.

  14. Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Johnston, S.; Yan, F.; Dorn, D.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Ounadjela, K.

    2012-06-01

    Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect band images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.

  15. Reduction of batwing effect in white light interferometry for measurement of patterned sapphire substrates (PSS) wafer

    Science.gov (United States)

    Tapilouw, Abraham Mario; Chang, Yi-Wei; Yu, Long-Yo; Wang, Hau-Wei

    2016-08-01

    Patterned sapphire substrates (PSS) wafers are used in LED manufacturing to enhance the luminous conversion of LED chips. The most critical characteristics in PSS wafers are height, width, pitch and shape of the pattern. The common way to measure these characteristics is by using surface electron microscope (SEM). White light interferometry is capable to measure dimension with nanometer accuracy and it is suitable for measuring the characteristics of PSS wafers. One of the difficulties in measuring PSS wafers is the aspect ratio and density of the features. The high aspect ratio combined with dense pattern spacing diffracts incoming lights and reduces the accuracy of the white light interferometry measurement. In this paper, a method to improve the capability of white light interferometry for measuring PSS wafers by choosing the appropriate wavelength and microscope objective with high numerical aperture. The technique is proven to be effective for reducing the batwing effect in edges of the feature and improves measurement accuracy for PSS wafers with circular features of 1.95 um in height and diameters, and 700 nm spacing between the features. Repeatability of the measurement is up to 5 nm for height measurement and 20 nm for pitch measurement.

  16. Bonding with Your Baby

    Science.gov (United States)

    ... in infant massage in your area. Breastfeeding and bottle-feeding are both natural times for bonding. Infants respond ... activities include: participating together in labor and delivery feeding ( breast or bottle ); sometimes dad forms a special bond with baby ...

  17. NXE:3100 full wafer imaging performance and budget verification

    Science.gov (United States)

    van Setten, Eelco; van Ingen Schenau, Koen; O'Mahony, Mark; Hollink, Thijs; Wittebrood, Friso; Davydova, Natalia; Eurlings, Mark; Feenstra, Kees; Finders, Jo; Dusa, Mircea; Young, Stuart

    2012-02-01

    With the introduction of the NXE:3100 NA=0.25 exposure system a big step has been made to get EUV lithography ready for High Volume Manufacturing. Over the last year, 6 exposure systems have been shipped to various customers around the world, active in Logic, DRAM, MPU and Flash memory, covering all major segments in the semi-conductor industry. The integration and qualification of these systems have provided a great learning, identifying the benefits of EUV over ArF immersion and the critical parameters of the exposure tool and how to operate it. In this paper we will focus specifically on the imaging performance of the NXE:3100 EUV scanner. Having been operational for more than a year a wide range of features were evaluated for lithographic performance across the field and across wafer. CD results of 32nm contact holes, 27nm isolated and dense lines, 27nm two-bar, 22nm dense L/S with Dipole, as well as several device features will be discussed and benchmarked against the current ArF immersion performance. A budget verification will be presented showing CD and contrast budgets for a selection of lithographic features. The contribution of the resist process and the mask will be discussed as well. The litho performance optimization will be highlighted with the 27nm twobar and isolated lines features that are sensitive to the illuminator pupil shape and projection lens aberrations. We will estimate the amount of resist induced contrast loss for 27 and 22nm L/S based on measurements of Exposure Latitude and the contributors from the exposure system. We will further present on the impact of variations in the mask blank and patterned mask on imaging, with several new contributors to take into account compared to traditional transmission masks. Finally, the combined results will be projected to the NXE:3300 NA=0.33 exposure system to give an outlook for its imaging performance capabilities.

  18. Bond percolation in films

    Science.gov (United States)

    Korneta, W.; Pytel, Z.

    1988-04-01

    Bond percolation in films with simple cubic structure is considered. It is assumed that the probability of a bond being present between nearest-neighbor sites depends on the distances to surfaces. Based on the relation between the Potts model and the bond percolation model, and using the mean-field approximation, the phase diagram and profiles of the percolation probability have been obtained.

  19. Acrylic mechanical bond tests

    Energy Technology Data Exchange (ETDEWEB)

    Wouters, J.M.; Doe, P.J.

    1991-02-01

    The tensile strength of bonded acrylic is tested as a function of bond joint thickness. 0.125 in. thick bond joints were found to posses the maximum strength while the acceptable range of joints varied from 0.063 in. to almost 0.25 in. Such joints are used in the Sudbury Neutrino Observatory.

  20. Chemical bond fundamental aspects of chemical bonding

    CERN Document Server

    Frenking, Gernot

    2014-01-01

    This is the perfect complement to ""Chemical Bonding - Across the Periodic Table"" by the same editors, who are two of the top scientists working on this topic, each with extensive experience and important connections within the community. The resulting book is a unique overview of the different approaches used for describing a chemical bond, including molecular-orbital based, valence-bond based, ELF, AIM and density-functional based methods. It takes into account the many developments that have taken place in the field over the past few decades due to the rapid advances in quantum chemica

  1. Effective operation of pattern defect/particle inspection systems for VLSI wafers; Handotai wafer gaikan furyo kensa no kokateki un`yo

    Energy Technology Data Exchange (ETDEWEB)

    Shiba, M.; Kubota, H.; Kenbo, Y.; Hiratsuka, S.; Maeda, S. [Hitachi, Ltd., Tokyo (Japan)

    1997-10-01

    Responsible for 60-80% of causes for defects in highly integrated semiconductor wafers are the anomalous crystal growth and foreign objects occurring in the manufacturing facilities or processes and the outward discrepancies including defects in the pattern such as disconnected or shortcircuited lines. Accordingly, it is required to incessantly keep a watch for the occurrence of outward discrepancies and, if any detected, to promptly take necessary steps for the manufacturing facilities or processes. Hitachi Group has developed an AS-5000 which deals with foreign objects and outward discrepancies comprehensively for the construction of a semiconductor manufacturing line that is economically efficient. Inspection may be conducted economically and with high efficiency when the `overall loss minimization method` is incorporated into the AS-5000 for selecting an optimal inspection device and determining the wafer extraction rate in response to the constantly shifting conditions, and when the WI-890 for wafer appearance inspection, the IS-2500 provided with patterns for inspecting foreign objects in wafers, and the IS-1510 for monitoring tiny foreign objects, are connected to the AS-5000. 5 refs., 5 figs., 1 tab.

  2. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    Energy Technology Data Exchange (ETDEWEB)

    Emanuel Sachs

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the

  3. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    Directory of Open Access Journals (Sweden)

    Lim SCB

    2013-04-01

    Full Text Available Stephen CB Lim,1,3 Michael J Paech,2 Bruce Sunderland,3 Yandi Liu3 1Pharmacy Department, Armadale Health Service, Armadale, 2School of Medicine and Pharmacology, University of Western Australia, and Department of Anaesthesia and Pain Medicine, King Edward Memorial Hospital for Women, Subiaco, 3School of Pharmacy, Curtin Health Innovation Research Institute, Curtin University, Perth, WA, Australia Background: The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods: The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results: In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion: These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. Keywords: absolute bioavailability, fentanyl wafer, in vitro dissolution, in vivo study, pharmacokinetics, sublingual

  4. Radiation, temperature, and vacuum effects on piezoelectric wafer active sensors

    Science.gov (United States)

    Giurgiutiu, Victor; Postolache, Cristian; Tudose, Mihai

    2016-03-01

    The effect of radiation, temperature, and vacuum (RTV) on piezoelectric wafer active sensors (PWASs) is discussed. This study is relevant for extending structural health monitoring (SHM) methods to space vehicle applications that are likely to be subjected to harsh environmental conditions such as extreme temperatures (hot and cold), cosmic radiation, and interplanetary vacuums. This study contains both theoretical and experimental investigations with the use of electromechanical impedance spectroscopy (EMIS). In the theoretical part, analytical models of circular PWAS resonators were used to derive analytical expressions for the temperature sensitivities of EMIS resonance and antiresonance behavior. Closed-form expressions for frequency and peak values at resonance and antiresonance were derived as functions of the coefficients of thermal expansion, {α }1, {α }2, {α }3; the Poisson ratio, ν and its sensitivity, \\partial ν /\\partial T; the relative compliance gradient (\\partial {s}11E/\\partial T)/{s}11E; and the Bessel function root, z and its sensitivity, \\partial z/\\partial T. In the experimental part, tests were conducted to subject the PWAS transducers to RTV conditions. In one set of experiments, several RTV exposure, cycles were applied with EMIS signatures recorded at the beginning and after each of the repeated cycles. In another set of experiments, PWAS transducers were subjected to various temperatures and the EMIS signatures were recorded at each temperature after stabilization. The processing of measured EMIS data from the first set of experiments revealed that the resonance and antiresonance frequencies changed by less than 1% due to RTV exposure, whereas the resonance and antiresonance amplitudes changed by around 15%. After processing an individual set of EMIS data from the second set of experiments, it was determined that the relative temperature sensitivity of the antiresonance frequency ({f}{{AR}}/{f}{{AR}}) is approximately 63.1× {10

  5. Structural Damage Detection with Piezoelectric Wafer Active Sensors

    Energy Technology Data Exchange (ETDEWEB)

    Giurgiutiu, Victor, E-mail: victorg@sc.edu [University of South Carolina, SC 29205 (United States)

    2011-07-19

    Piezoelectric wafer active sensors (PWAS) are lightweight and inexpensive enablers for a large class of damage detection and structural health monitoring (SHM) applications. This paper starts with a brief review of PWAS physical principles and basic modelling and continues by considering the various ways in which PWAS can be used for damage detection: (a) embedded guided-wave ultrasonics, i.e., pitch-catch, pulse-echo, phased arrays, thickness mode; (b) high-frequency modal sensing, i.e., the electro-mechanical (E/M) impedance method; (c) passive detection, i.e., acoustic emission and impact detection. An example of crack-like damage detection and localization with PWAS phased arrays on a small metallic plate is given. The modelling of PWAS detection of disbond damage in adhesive joints is achieved with the analytical transfer matrix method (TMM). The analytical methods offer the advantage of fast computation which enables parameter studies and carpet plots. A parametric study of the effect of crack size and PWAS location on disbond detection is presented. The power and energy transduction between PWAS and structure is studied analytically with a wave propagation method. Special attention is given to the mechatronics modeling of the complete transduction cycle from electrical excitation into ultrasonic acoustic waves by the piezoelectric effect, the transfer through the structure, and finally reverse piezoelectric transduction to generate the received electric signal. It is found that the combination of PWAS size and wave frequency/wavelength play an important role in identifying transduction maxima and minima that could be exploited to achieve an optimum power-efficient design. The multi-physics finite element method (MP-FEM), which permits fine discretization of damaged regions and complicated structural geometries, is used to study the generation of guided waves in a plate from an electrically excited transmitter PWAS and the capture of these waves as electric

  6. Structural Damage Detection with Piezoelectric Wafer Active Sensors

    Science.gov (United States)

    Giurgiutiu, Victor

    2011-07-01

    Piezoelectric wafer active sensors (PWAS) are lightweight and inexpensive enablers for a large class of damage detection and structural health monitoring (SHM) applications. This paper starts with a brief review of PWAS physical principles and basic modelling and continues by considering the various ways in which PWAS can be used for damage detection: (a) embedded guided-wave ultrasonics, i.e., pitch-catch, pulse-echo, phased arrays, thickness mode; (b) high-frequency modal sensing, i.e., the electro-mechanical (E/M) impedance method; (c) passive detection, i.e., acoustic emission and impact detection. An example of crack-like damage detection and localization with PWAS phased arrays on a small metallic plate is given. The modelling of PWAS detection of disbond damage in adhesive joints is achieved with the analytical transfer matrix method (TMM). The analytical methods offer the advantage of fast computation which enables parameter studies and carpet plots. A parametric study of the effect of crack size and PWAS location on disbond detection is presented. The power and energy transduction between PWAS and structure is studied analytically with a wave propagation method. Special attention is given to the mechatronics modeling of the complete transduction cycle from electrical excitation into ultrasonic acoustic waves by the piezoelectric effect, the transfer through the structure, and finally reverse piezoelectric transduction to generate the received electric signal. It is found that the combination of PWAS size and wave frequency/wavelength play an important role in identifying transduction maxima and minima that could be exploited to achieve an optimum power-efficient design. The multi-physics finite element method (MP-FEM), which permits fine discretization of damaged regions and complicated structural geometries, is used to study the generation of guided waves in a plate from an electrically excited transmitter PWAS and the capture of these waves as electric

  7. Rinsing of wafers after wet processing: Simulation and experiments

    Science.gov (United States)

    Chiang, Chieh-Chun

    In semiconductor manufacturing, a large amount (50 billion gallons for US semiconductor fabrication plants in 2006) of ultrapure water (UPW) is used to rinse wafers after wet chemical processing to remove ionic contaminants on surfaces. Of great concern are the contaminants left in narrow (tens of nm), high-aspect-ratio (5:1 to 20:1) features (trenches, vias, and contact holes). The International Technology Roadmap for Semiconductors (ITRS) stipulates that ionic contaminant levels be reduced to below ˜ 10 10 atoms/cm2. Understanding the bottlenecks in the rinsing process would enable conservation of rinse water usage. A comprehensive process model has been developed on the COMSOL platform to predict the dynamics of rinsing of narrow structures on patterned SiO 2 substrates initially cleaned with NH4OH. The model considers the effect of various mass-transport mechanisms, including convection and diffusion/dispersion, which occur simultaneously with various surface phenomena, such as adsorption and desorption of impurities. The influences of charged species in the bulk and on the surface, and their induced electric field that affect both transport and surface interactions, have been addressed. Modeling results show that the efficacy of rinsing is strongly influenced by the rate of desorption of adsorbed contaminants, mass transfer of contaminants from the mouth of the feature to the bulk liquid, and the trench aspect ratio. Detection of the end point of rinsing is another way to conserve water used for rinsing after wet processing. The applicability of electrochemical impedance spectroscopy (EIS) to monitor rinsing of Si processed in HF with and without copper contaminant was explored. In the first study, the effect of the nature of surface state (flat band, depletion, or accumulation) of silicon on rinsing rate was investigated. The experimental results show that the state of silicon could affect rinsing kinetics through modulation of ion adsorption. In the second

  8. Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

    Energy Technology Data Exchange (ETDEWEB)

    Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas; Tan, Teh; Upadhyaya, Ajay; Tate, Keith; Rohatgi, Ajeet; Xu, Han

    2017-01-01

    We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygen analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.

  9. Interfacial Characterizations of a Nickel-Phosphorus Layer Electrolessly Deposited on a Silane Compound-Modified Silicon Wafer Under Thermal Annealing

    Science.gov (United States)

    Lai, Kuei-Chang; Wu, Pei-Yu; Chen, Chih-Ming; Wei, Tzu-Chien; Wu, Chung-Han; Feng, Shien-Ping

    2016-10-01

    Front-side metallization of a Si wafer was carried out using electroless deposition of nickel-phosphorus (Ni-P) catalyzed by polyvinylpyrrolidone-capped palladium nanoclusters (PVP-nPd). A 3-[2-(2-Aminoethylamino)ethylamino] propyl-trimethoxysilane (ETAS) layer was covalently bonded on the Si surface as bridge linker to the Pd cores of PVP-nPd clusters for improving adhesion between the Ni-P layer and the Si surface. To investigate the effects of an interfacial ETAS layer on the Ni silicide formation at the Ni-P/Si contact, the Ni-P-coated Si samples were thermally annealed via rapid thermal annealing (RTA) from 500°C to 900°C for 2 min. To compare with the ETAS sample, the sputtered Ni layer on Si and electroless Ni-P layer on ion-Pd-catalyzed Si (both are standard processes) were also investigated. The microstructural characterizations for the Ni-P or Ni layer deposited on the Si wafer were performed using x-ray diffractometer, scanning electron microscopy, and transmission electron microscopy. Our results showed that the ETAS layer acted as a barrier to slow the atomic diffusion of Ni toward the Si side. Although the formation of Ni silicides required a higher annealing temperature, the adhesion strength and contact resistivity measurements of annealed Ni-P/Si contacts showed satisfactory results, which were essential to the device performance and reliability during thermal annealing.

  10. Correlation between reticle- and wafer-CD difference of multiple 28nm reticle-sites

    Science.gov (United States)

    Ning, Guoxiang; Richter, Frank; Thamm, Thomas; Ackmann, Paul; Staples, Marc; Weisbuch, Francois; Kurth, Karin; Schenker, Joerg; Leschok, Andre; GN, Fang Hong

    2012-11-01

    Reticle critical dimension uniformity (CDU) is an important criterion for the qualification of mask layer processes. Normally, the smaller the three sigma value of reticle CDU is, the better is the reticle CDU performance. For qualification of mask processes, the mask layers to be qualified should have a comparable reticle CDU compared to the process of record (POR) mask layers. Because the reticle critical dimension (CD) measurement is based on algorithms like "middle side lobe measurement", evaluation of the reticle CD-values can not reflect aspects like the sidewall angle of the reticle and variation in corner rounding which may be critical for 45nm technology nodes (and below). All involved tools and processes contribute to the wafer intra-field CDU (scanner, track, reticle, metrology). Normally, the reticle contribution to the wafer CDU should be as small as possible. In order to reduce the process contributions to the wafer intra-field CDU during the mask qualification process, the same toolset (exposure tool, metrology tool) should be applied as for the POR. Out of the results of these investigations the correlation between wafer measurement to target (MTT) and reticle MTT can be obtained in order to accurately qualify the CDU performance of the mask processes. We will demonstrate the correlation between reticle MTT and wafer MTT by use of multiple mask processes and alternative mask blank materials. We will investigate the results of four process-layers looking at advanced binary maskblank material from two different suppliers (moreover the results of a 2X-via layer as an example for a phase-shift maskblank is discussed). Objective of this article is to demonstrate the distribution between reticle MTT and wafer MTT as a qualification criterion for mask processes. The correlation between wafer CD-difference and reticle CD-difference of these mask processes are demonstrated by having performed investigations of dense features of different 28nmtechnology

  11. Structural Characterization of Self-Assembled Monolayers of Organosilanes Chemically Bonded on Silica Wafers by Dynamical Force Microscopy

    CERN Document Server

    Navarre, S; Bousbaa, J; Bennetau, B; Nony, L; Aimé, J P; Choplin, Franck; Bennetau, Bernard; Nony, Laurent; Aim\\'{e}, Jean-Pierre

    2001-01-01

    In this article, a dynamical force microscopy study of self-assembled monolayers of organosilanes, grafted on a silica support, is reported. Organosilanes, terminated either with a functional group (ethylene glycol) or with a methyl group, were used. The influence of the reaction time and the solvent composition on the grafting was investigated to improve the homogeneity of the self-assembled monolayers. Numerical simulations of approach-retract curves, obtained in the tapping mode, were performed and compared to experimental ones. Informations, such as mechanical response and height of the grafted organic layers, have been obtained.

  12. Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

    Science.gov (United States)

    Pa, Pai-Shan

    2010-01-01

    A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

  13. Force Modeling for Ultrasonic-assisted Wire Saw Cutting SiC Monocryatal Wafers

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jie; LI Shujuan; Liu Yong

    2011-01-01

    The advantages, such as a small cutting force, narrow kerf and little material waste make wire saw cut- ting suitable for machining precious materials like SiC, Si monocrystal and a variety of gem. As regards wire saw cutting fo wafer, however, in traditional wire saw cutting process, the cutting efficiency is low, the wear of wire saw is badly, the surface roughness of wafer is poor etc, which have a seriously impact on the cutting process stability and the use of wafers. Ultrasonic-assisted machining method is very suitable for processing a variety of non-conduc- tive hard and brittle materials, glass, ceramics, quartz, silicon, precious stones and diamonds, etc. In this paper, the force model of ultrusonic-assisted wire saw cutting of SiC monocrystal wafer, based on the kinematic and experi- mental analysis were established. The single factor and orthogonal experimental scheme for different processing pa- rameters such as wire saw speed, part rotation speed of and part feed rate, were carried out in traditional wire saw and ultrasonic-assisted wire saw cutting process. The multiple linear regression method is used to establish the static model among the cutting force, processing parameters and ultrasonic vibration parameters, and the model signifi- cance is verified. The results show, as regards ultrasonic-assisted wire saw cutting of SiC monicrystal wafer, both the tangential and normal cutting forces can reduce about 24. 5%-36% and 36. 6%-40%.

  14. Gated Silicon Drift Detector Fabricated from a Low-Cost Silicon Wafer

    Directory of Open Access Journals (Sweden)

    Hideharu Matsuura

    2015-05-01

    Full Text Available Inexpensive high-resolution silicon (Si X-ray detectors are required for on-site surveys of traces of hazardous elements in food and soil by measuring the energies and counts of X-ray fluorescence photons radially emitted from these elements. Gated silicon drift detectors (GSDDs are much cheaper to fabricate than commercial silicon drift detectors (SDDs. However, previous GSDDs were fabricated from \\(10\\-k\\(\\Omega \\cdot\\cm Si wafers, which are more expensive than \\(2\\-k\\(\\Omega \\cdot\\cm Si wafers used in commercial SDDs. To fabricate cheaper portable X-ray fluorescence instruments, we investigate GSDDs formed from \\(2\\-k\\(\\Omega \\cdot\\cm Si wafers. The thicknesses of commercial SDDs are up to \\(0.5\\ mm, which can detect photons with energies up to \\(27\\ keV, whereas we describe GSDDs that can detect photons with energies of up to \\(35\\ keV. We simulate the electric potential distributions in GSDDs with Si thicknesses of \\(0.5\\ and \\(1\\ mm at a single high reverse bias. GSDDs with one gate pattern using any resistivity Si wafer can work well for changing the reverse bias that is inversely proportional to the resistivity of the Si wafer.

  15. The Process of Plasma Chemical Photoresist Film Ashing from the Surface of Silicon Wafers

    Directory of Open Access Journals (Sweden)

    Siarhei Bordusau

    2013-01-01

    Full Text Available At present, the research for finding new technical methods of treating materials with plasma, including the development of energy and resource saving technologies for microelectronic manufacturing, is particularly actual.In order to improve the efficiency of microwave plasma chemical ashing of photoresist films from the surface of silicon wafers a two-stage process of treating was developed. The idea of the developed process is that wafers coated with photoresist are pre-heated by microwave energy. This occurs because the microwave energy initially is not spent on the excitation and maintenance of a microwave discharge but it is absorbed by silicon wafers which have a high tangent of dielectric losses. During the next step after the excitation of the microwave discharge the interaction of oxygen plasma with a pre-heated photoresist films proceeds more intensively. The delay of the start of plasma forming process in the vacuum chamber of a plasmatron with respect to the beginning of microwave energy generation by a magnetron leads to the increase of the total rate of photoresist ashing from the surface of silicon wafers approximately 1.7 times. The advantage of this method of microwave plasma chemical processing of semi-conductor wafers is the possibility of intensifying the process without changing the design of microwave discharge module and without increasing the input microwave power supplied into the discharge.

  16. Lateral Scanning Linnik Interferometry for Large Field of View and Fast Scanning: Wafer Bump Inspection

    Science.gov (United States)

    Kim, Min Y.; Veluvolu, Kalyana C.; Lee, Soon-Geul

    2011-07-01

    Wafer-level packaging is currently the major trend in semiconductor packaging for miniaturization and high-density integration. To ensure the package reliability, the wafer and substrate bumps utilized as connection junctions need to be in-line inspected as regards their top-height distribution, coplanarity, and volume uniformity. This article proposes a lateral scanning interferometric system for wafer bump shape inspection in three dimensions with a large field of view and fast inspection speed based on an optomechatronic system design. For multiple-peak interferogram from wafer bumps around a transparent film layer, two-step information extraction algorithms are suggested, including top surface profile and under-layer surface profile detection algorithms. The multiple-peak interferogram is acquired with variations of lateral position of the reference mirror by a piezoelectric transducer (PZT). A series of experiments is performed for representative wafer samples with solder and gold bumps, and the effectiveness of the proposed inspection system is verified from the test results.

  17. Automated 3D IR defect mapping system for CZT wafer and tile inspection and characterization

    Science.gov (United States)

    Liao, Yi; Heidari, Esmaeil; Abramovich, Gil; Nafis, Christopher; Butt, Amer; Czechowski, Joseph; Harding, Kevin; Tkaczyk, J. Eric

    2011-08-01

    In this paper, the design and evaluation of a 3D stereo, near infrared (IR), defect mapping system for CZT inspection is described. This system provides rapid acquisition and data analysis that result in detailed mapping of CZT crystal defects across the area of wafers up to 100 millimeter diameter and through thicknesses of up to 20 millimeter. In this paper, system characterization has been performed including a close evaluation of the bright field and dark field illumination configurations for both wafer-scale and tile-scale inspection. A comparison of microscope image and IR image for the same sample is performed. As a result, the IR inspection system has successfully demonstrated the capability of detecting and localizing inclusions within minutes for a whole CZT wafer. Important information is provided for selecting defect free areas out of a wafer and thereby ensuring the quality of the tile. This system would support the CZT wafer dicing and assembly techniques that enable the economical production of CZT detectors. This capability can improve the yield and reduce the cost of the thick detector devices that are rarely produced today.

  18. Minimizing wafer defectivity during high-temperature baking of organic films in 193nm lithography

    Science.gov (United States)

    Randall, Mai; Longstaff, Christopher; Ueda, Kenichi; Nicholson, Jim; Winter, Thomas

    2006-03-01

    Demands for continued defect reduction in 300mm IC manufacturing is driving process engineers to examine all aspects of the apply process for improvement. Process engineers, and their respective tool sets, are required to process films at temperatures above the boiling point of the casting solvents. This can potentially lead to the sublimation of the film chemical components. The current methods used to minimize wafer defectivity due to bake residues include frequent cleaning of bake plate modules and surrounding equipment, process optimization, and hardware improvements until more robust chemistries are available. IBM has evaluated the Tokyo Electron CLEAN TRACK TM ACT TM 12 high exhaust high temperature hotplate (HHP) lid to minimize wafer level contamination due to the outgasing of a bottom anti-reflective coating (BARC) films during the high temperature bake process. Goal was to minimize airborne contamination (particles in free space), reduce hotplate contamination build up, and ultimately reduce defects on the wafer. This evaluation was performed on a 193nm BARC material. Evaluation data included visual hardware inspections, airborne particle counting, relative thickness build up measurements on hotplate lids, wafer level defect measurements, and electrical open fail rate. Film coat thickness mean and uniformity were also checked to compare the high exhaust HHP with the standard HHP lid. Chemical analysis of the HHP module residue was performed to identify the source material. The work will quantify potential cost savings achieved by reducing added wafer defects during processing and extending PM frequency for equipment cleaning.

  19. Automated defect review of the wafer bevel with a defect review scanning electron microscope

    Science.gov (United States)

    McGarvey, Steve; Kanezawa, Masakazu

    2009-03-01

    One of the few remaining bastions of non-regulated Integrated Circuit defectivity is the wafer bevel. Recent internal Integrated Circuit Manufacturing studies have suggested that the edge bevel may be responsible for as much as a two to three percent yield loss during a defect excursion on the manufacturing line and a one to two percent yield loss during ongoing wafer manufacturing. A new generation of defect inspection equipment has been introduced to the Research and Development, Integrated Circuit, MEM's and Si wafer manufacturing markets that has imparted the ability for the end equipment user to detect defects located on the bevel of the wafer. The inherent weakness of the current batch of wafer bevel inspection equipment is the lack of automatic discrete defect classification data into multiple, significant classification bins and the lack of discrete elemental analysis data. Root cause analysis is based on minimal discrete defect analysis as a surrogate for a statistically valid sampling of defects from the bevel. This paper provides a study of the methods employed with a Hitachi RS-5500EQEQ Defect Review Scanning Electron Microscope (DRSEM) to automatically capture high resolution/high magnification images and collect elemental analysis on a statistically valid sample of the discrete defects that were located by a bevel inspection system.

  20. Rapid, Non-Contact Method for Measurement of Si-Wafer Thickness: Principles and Preliminary Results; Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Sopori, B.; Auriemma, C.; Li, C.; Madjdpour, J.

    2003-08-01

    The thickness of a semiconductor wafer can critically influence mechanical and/or electronic yield of the device(s) fabricated on it. For most microelectronic (surface) devices, the thickness of a wafer is important primarily for mechanical reasons--to provide control and stability of devices by minimizing stresses resulting from various device-fabrication processes. However, for minority-carrier devices, such as solar cells, the entire thickness of the wafer participates in the optical and electronic performance of the device. In either case, control of wafer thickness through careful measurement is a fundamental requirement in the commercial fabrication of electronic devices.

  1. Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

    Science.gov (United States)

    Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

    2015-11-01

    Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group.

  2. Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

    Science.gov (United States)

    Yoon, Sang Won; Lee, Sangwoo; Perkins, Noel C.; Najafi, Khalil

    2011-01-01

    This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped-clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm2 footprint. The contact resistance ranges from 4-11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

  3. Equilibrium CO bond lengths

    Science.gov (United States)

    Demaison, Jean; Császár, Attila G.

    2012-09-01

    Based on a sample of 38 molecules, 47 accurate equilibrium CO bond lengths have been collected and analyzed. These ultimate experimental (reEX), semiexperimental (reSE), and Born-Oppenheimer (reBO) equilibrium structures are compared to reBO estimates from two lower-level techniques of electronic structure theory, MP2(FC)/cc-pVQZ and B3LYP/6-311+G(3df,2pd). A linear relationship is found between the best equilibrium bond lengths and their MP2 or B3LYP estimates. These (and similar) linear relationships permit to estimate the CO bond length with an accuracy of 0.002 Å within the full range of 1.10-1.43 Å, corresponding to single, double, and triple CO bonds, for a large number of molecules. The variation of the CO bond length is qualitatively explained using the Atoms in Molecules method. In particular, a nice correlation is found between the CO bond length and the bond critical point density and it appears that the CO bond is at the same time covalent and ionic. Conditions which permit the computation of an accurate ab initio Born-Oppenheimer equilibrium structure are discussed. In particular, the core-core and core-valence correlation is investigated and it is shown to roughly increase with the bond length.

  4. Copper wire bonding

    CERN Document Server

    Chauhan, Preeti S; Zhong, ZhaoWei; Pecht, Michael G

    2014-01-01

    This critical volume provides an in-depth presentation of copper wire bonding technologies, processes and equipment, along with the economic benefits and risks.  Due to the increasing cost of materials used to make electronic components, the electronics industry has been rapidly moving from high cost gold to significantly lower cost copper as a wire bonding material.  However, copper wire bonding has several process and reliability concerns due to its material properties.  Copper Wire Bonding book lays out the challenges involved in replacing gold with copper as a wire bond material, and includes the bonding process changes—bond force, electric flame off, current and ultrasonic energy optimization, and bonding tools and equipment changes for first and second bond formation.  In addition, the bond–pad metallurgies and the use of bare and palladium-coated copper wires on aluminum are presented, and gold, nickel and palladium surface finishes are discussed.  The book also discusses best practices and re...

  5. Preparation of a catalytic reactor composed of a microchannel etched on a silicon wafer; Shirikon ueha jo ni sakuseishita mikuro channeru wo mochiiru shokubai hanno sochi no shisaku

    Energy Technology Data Exchange (ETDEWEB)

    Tsubota, T.; Miyagawa, D.; Kusakabe, K.; Morooka, S. [Kyushu Univ., Fukuoka (Japan). Dept. of Applied Chemistry

    2000-11-10

    A Microchannel (upper width = 280 {mu}m, lower width = 138 {mu}m, depth 100 {mu}m, length = 27 mm) was formed on a (100) silicon wafer by means of wet chemical etching, and a platinum layer was then coated on the microchannel walls by sputtering. The resulting channel was sealed with a glass cover by an anodic bonding technique. Cyclohexane vapor, carried by a stream of nitrogen, was then introduced into the microreactor at 400 degree C, and the concentrations of both the reactant, and the products of the ensuing dehydrogenation reaction over the platinum catalyst, were determined by means of a micro gas chromatograph. Thus, a series of procedures for manufacturing and testing a microreactor such as lithography of a microchannel, the formation of a catalytic Pt film, the introduction of a reactant into the covered microchannel, or an analysis of reactants and products was established and verified. (author)

  6. EM Simulation Accuracy Enhancement for Broadband Modeling of On-Wafer Passive Components

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Jiang, Chenhui; Hadziabdic, Dzenan;

    2007-01-01

    This paper describes methods for accuracy enhancement in broadband modeling of on-wafer passive components using electromagnetic (EM) simulation. It is shown that standard excitation schemes for integrated component simulation leads to poor correlation with on-wafer measurements beyond the lower...... GHz frequency range. We show that this is due to parasitic effects and higher-order modes caused by the excitation schemes. We propose a simple equivalent circuit for the parasitic effects in the well-known ground ring excitation scheme. An extended L-2L calibration method is shown to improve...... significantly the accuracy of the on-wafer component modeling, when applied to parasitic effect removal associated with the excitation schemes....

  7. Three-Stage Tracking Control for the LED Wafer Transporting Robot

    Directory of Open Access Journals (Sweden)

    Zuoxun Wang

    2015-01-01

    Full Text Available In order to ensure the steady ability of the LED wafer transporting robot, a high order polynomial interpolation method is proposed to plan the motion process of the LED wafer transporting robot. According to the LED wafer transporting robot which is fast and has no vibration, fifth-order polynomial is applied to complete the robot’s motion planning. A new subsection search method is proposed to optimize the transporting robot’s acceleration. Optimal planning curve is achieved by the subsection searching. Extended Kalman filter algorithm and PID algorithm are employed to follow the tracks of planned path. MATLAB simulation and experiment confirm the validity and efficiency of the proposed method.

  8. Feature profile evolution in plasma processing using on-wafer monitoring system

    CERN Document Server

    Samukawa, Seiji

    2014-01-01

    This book provides for the first time a good understanding of the etching profile technologies that do not disturb the plasma. Three types of sensors are introduced: on-wafer UV sensors, on-wafer charge-up sensors and on-wafer sheath-shape sensors in the plasma processing and prediction system of real etching profiles based on monitoring data. Readers are made familiar with these sensors, which can measure real plasma process surface conditions such as defect generations due to UV-irradiation, ion flight direction due to charge-up voltage in high-aspect ratio structures and ion sheath conditions at the plasma/surface interface. The plasma etching profile realistically predicted by a computer simulation based on output data from these sensors is described.

  9. Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers

    Directory of Open Access Journals (Sweden)

    Chun-You Wei

    2013-11-01

    Full Text Available Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

  10. Effects of cleaning procedures of silica wafers on their friction characteristics.

    Science.gov (United States)

    Donose, Bogdan C; Taran, Elena; Vakarelski, Ivan U; Shinto, Hiroyuki; Higashitani, Ko

    2006-07-01

    Silicon wafers with thermal silicon oxide layers were cleaned and hydrophilized by three different methods: (1) the remote chemical analysis (RCA) wet cleaning by use of ammonia and hydrogen peroxide mixture solutions, (2) water-vapor plasma cleaning, and (3) UV/ozone combined cleaning. All procedures were found to remove effectively organic contaminations on wafers and gave identical characteristics of the contact angle, the surface roughness and the normal force interactions, measured by atomic force microscopy (AFM). However, it is found that wafers cleaned by the RCA method have several times larger friction coefficients than those cleaned by the plasma and UV/ozone methods. The difference was explained by the atomic-scale topological difference induced during the RCA cleaning. This study reveals the lateral force microscopy as a very sensitive method to detect the microstructure of surfaces.

  11. First On-Wafer Power Characterization of MMIC Amplifiers at Sub-Millimeter Wave Frequencies

    Science.gov (United States)

    Fung, A. K.; Gaier, T.; Samoska, L.; Deal, W. R.; Radisic, V.; Mei, X. B.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Lai, R.

    2008-01-01

    Recent developments in semiconductor technology have enabled advanced submillimeter wave (300 GHz) transistors and circuits. These new high speed components have required new test methods to be developed for characterizing performance, and to provide data for device modeling to improve designs. Current efforts in progressing high frequency testing have resulted in on-wafer-parameter measurements up to approximately 340 GHz and swept frequency vector network analyzer waveguide measurements to 508 GHz. On-wafer noise figure measurements in the 270-340 GHz band have been demonstrated. In this letter we report on on-wafer power measurements at 330 GHz of a three stage amplifier that resulted in a maximum measured output power of 1.78mW and maximum gain of 7.1 dB. The method utilized demonstrates the extension of traditional power measurement techniques to submillimeter wave frequencies, and is suitable for automated testing without packaging for production screening of submillimeter wave circuits.

  12. Radiation thermometry of silicon wafers based on emissivity-invariant condition.

    Science.gov (United States)

    Iuchi, Tohru; Seo, Tomohiro

    2011-01-20

    An emissivity-invariant condition for a silicon wafer was determined by simulation modeling and it was confirmed experimentally. The p-polarized spectral emissivity at a wavelength of 900 nm and at temperatures over 900 K was constant at 0.83 at an angle of about 55.4° irrespective of large variations in the oxide layer thickness and the resistivity due to the different impurity doping concentrations of the silicon wafer. The expanded uncertainty, U(c) = ku(c) (k = 2), of the temperature measurement is estimated to be 4.9 K. This result is expected to significantly enhance the accuracy of radiometric temperature measurements of silicon wafers in actual manufacturing processes.

  13. High extinction ratio bandgap of photonic crystals in LNOI wafer

    Science.gov (United States)

    Zhang, Shao-Mei; Cai, Lu-Tong; Jiang, Yun-Peng; Jiao, Yang

    2017-02-01

    A high-extinction-ratio bandgap of air-bridge photonic crystal slab, in the near infrared, is reported. These structures were patterned in single-crystalline LiNbO3 film bonded to SiO2/LiNbO3 substrate by focused ion beam. To improve the vertical confinement of light, the SiO2 layer was removed by 3.6% HF acid. Compared with photonic crystals sandwiched between SiO2 and air, the structures suspending in air own a robust photonic bandgap and high transmission efficiency at valence band region. The measured results are in good agreement with numerically computed transmission spectra by finite-difference time-domain method. The air-bridge photonic crystal waveguides were formed by removing one line holes. We reveal experimentally the guiding characteristics and calculate the theoretical results for photonic crystal waveguides in LiNbO3 film.

  14. Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

    Science.gov (United States)

    Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

    2004-08-01

    The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

  15. Improving wafer level CD uniformity for logic applications utilizing mask level metrology and process

    Science.gov (United States)

    Cohen, Avi; Trautzsch, Thomas; Buttgereit, Ute; Graitzer, Erez; Hanuka, Ori

    2013-09-01

    Critical Dimension Uniformity (CDU) is one of the key parameters necessary to assure good performance and reliable functionality of any integrated circuit (IC). The extension of 193nm based lithography usage combined with design rule shrinkage makes process control, in particular the wafer level CDU control, an extremely important and challenging task in IC manufacturing. In this study the WLCD-CDC closed loop solution offered by Carl Zeiss SMS was examined. This solution aims to improve the wafer level intra-field CDU without the need to run wafer prints and extensive wafer CD metrology. It combines two stand-alone tools: The WLCD tool which measures CD based on aerial imaging technology while applying the exact scanner-used illumination conditions to the photomask and the CDC tool which utilizes an ultra-short femto-second laser to write intra-volume shading elements (Shade-In Elements™) inside the photomask bulk material. The CDC process changes the dose going through the photomask down to the wafer, hence the wafer level intra-field CDU improves. The objective of this study was to evaluate how CDC process is affecting the CD for different type of features and pattern density which are typical for logic and system on chip (SOC) devices. The main findings show that the linearity and proximity behavior is maintained by the CDC process and CDU and CDC Ratio (CDCR) show a linear behavior for the different feature types. Finally, it was demonstrated that the CDU errors of the targeted (critical) feature have been effectively eliminated. In addition, the CDU of all other features have been significantly improved as well.

  16. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  17. Artificial solid electrolyte interphase with in-situ formed porosity for enhancing lithiation of silicon wafer

    Science.gov (United States)

    Lin, Jie; Guo, Jianlai; Liu, Chang; Guo, Hang

    2016-12-01

    In order to utilize silicon wafer as electrode and substrate for integrated lithium-ion batteries, a composite film with in-situ formed porosity (lithium phosphorous oxynitride/tin oxide, LiPON/SnO2) is fabricated and directly exploited as the artificial solid electrolyte interphase film. Without the compromise of Coulombic efficiency, the capacity and cycle performance of silicon wafer are both developed, resulting from the reduced resistance and the dynamically stable coating. This work provides guidance to enhance the lithiation of bulk silicon, and the strategy of surface modification can be applied to other advanced materials or fields.

  18. DISPERSION OF NANODIAMOND AND ULTRA-FINE POLISHING OF QUARTZ WAFER

    Institute of Scientific and Technical Information of China (English)

    Yongwei Zhu; Zhijing Feng; Baichun Wang; Xianyang Xu

    2004-01-01

    Mechanochemical Modification (MCM) of nanodiamond surface with DN-10 was studied in relation to the performance of nanodiamond in polishing quartz wafers. Results show that the modified nanodiamond is more stable in the pH range 8~11. A super smooth surface with an average roughness of 0.214 nm was achieved using a nanodiamond-based slurry regulated by N-(2-hydroxyethyl)ethylenediamine. It is suggested that the principal ultra-fine polishing mechanism of quartz wafer involves atom-level removal under the synergism of chemical and mechanical actions.

  19. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  20. Apparatus for use in examining the lattice of a semiconductor wafer by X-ray diffraction

    Science.gov (United States)

    Parker, D. L.; Porter, W. A. (Inventor)

    1978-01-01

    An improved apparatus for examining the crystal lattice of a semiconductor wafer utilizing X-ray diffraction techniques was presented. The apparatus is employed in a method which includes the step of recording the image of a wafer supported in a bent configuration conforming to a compound curve, produced through the use of a vacuum chuck provided for an X-ray camera. The entire surface thereof is illuminated simultaneously by a beam of incident X-rays which are projected from a distant point-source and satisfy conditions of the Bragg Law for all points on the surface of the water.

  1. Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

    Science.gov (United States)

    Calaway, Michael J.; Rodriquez, M. C.; Allton, J. H.; Stansbery, E. K.

    2009-01-01

    The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

  2. 22 nm node wafer inspection using diffraction phase microscopy and image post-processing

    Science.gov (United States)

    Zhou, Renjie; Popescu, Gabriel; Goddard, Lynford L.

    2013-04-01

    We applied epi-illumination diffraction phase microscopy to measure the amplitude and phase of the scattered field from a SEMATECH 22 nm node intentional defect array (IDA) wafer. We used several imaging processing techniques to remove the wafer's underlying structure and reduce both the spatial and temporal noise and eliminate the system calibration error to produce stretched panoramic amplitude and phase images. From the stretched images, we detected defects down to 20 nm × 160 nm for a parallel bridge, 20 nm × 100 nm for perpendicular bridge, and 35 nm × 70 nm for an isolated dot.

  3. Thermal and structural assessments of a ceramic wafer seal in hypersonic engines

    Science.gov (United States)

    Tong, Mike T.; Steinetz, Bruce M.

    1991-01-01

    The thermal and structural performances of a ceramic wafer seal in a simulated hypersonic engine environment are numerically assessed. The effects of aerodynamic heating, surface contact conductance between the seal and its adjacent surfaces, flow of purge coolant gases, and leakage of hot engine flow path gases on the seal temperature were investigated from the engine inlet back to the entrance region of the combustion chamber. Finite element structural analyses, coupled with Weibull failure analyses, were performed to determine the structural reliability of the wafer seal.

  4. Thermal and structural assessments of a ceramic wafer seal in hypersonic engine

    Science.gov (United States)

    Tong, Mike; Steinetz, Bruce

    1991-01-01

    The thermal and structural performances of a ceramic wafer seal in a simulated hypersonic engine environment are numerically assessed. The effects of aerodynamic heating, surface contact conductance between the seal and its adjacent surfaces, flow of purge coolant gases, and leakage of hot engine flow path gases on the seal temperature were investigated from the engine inlet back to the entrance region of the combustion chamber. Finite element structural analyses, coupled with Weibull failure analyses, were performed to determine the structural reliability of the wafer seal.

  5. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Science.gov (United States)

    Bergauer, T.; Dragicevic, M.; König, A.; Hacker, J.; Bartl, U.

    2016-09-01

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  6. Wafer-scale fabrication of high-aspect ratio nanochannels based on edge-lithography technique.

    Science.gov (United States)

    Xie, Quan; Zhou, Qing; Xie, Fei; Sang, Jianming; Wang, Wei; Zhang, Haixia Alice; Wu, Wengang; Li, Zhihong

    2012-03-01

    This paper introduced a wafer-scale fabrication approach for the preparation of nanochannels with high-aspect ratio (the ratio of the channel depth to its width). Edge lithography was used to pattern nanogaps in an aluminum film, which was functioned as deep reactive ion etching mask thereafter to form the nanochannel. Nanochannels with aspect ratio up to 172 and width down to 44 nm were successfully fabricated on a 4-inch Si wafer with width nonuniformity less than 13.6%. A microfluidic chip integrated with nanometer-sized filters was successfully fabricated by utilizing the present method for geometric-controllable nanoparticle packing.

  7. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  8. A comparison of batch and single wafer high dose arsenic ion implantation techniques

    Energy Technology Data Exchange (ETDEWEB)

    Irwin, R.B.; Filo, A.J.; Kannan, V.C.; Feygenson, A.; Prematta, R.J.

    1989-04-01

    High dose, low energy (4x10/sup 15/ cm/sup -2/ at 15 keV) arsenic ion implantation into silicon was performed in batch and single wafer mode using medium and high current ion implanters. An investigation of implanted and annealed samples by Rutherford backscattering (RBS), transmission electron microscopy (TEM), thermal wave technique, and sheet resistance mapping showed little to no difference of arsenic profiles and residual damage between batch and single wafer implantation conditions when the sample temperature during implantation was kept below 120/sup 0/C. (orig.).

  9. A comparison of batch and single wafer high dose arsenic ion implantation techniques

    Science.gov (United States)

    Irwin, R. B.; Filo, A. J.; Kannan, V. C.; Feygenson, A.; Prematta, R. J.

    1989-04-01

    High dose, low energy (4×10 15 cm -2 at 15 keV) arsenic ion implantation into silicon was performed in batch and single wafer mode using medium and high current ion implanters. An investigation of implanted and annealed samples by Rutherford backscattering (RBS), transmission electron microscopy (TEM), thermal wave technique, and sheet resistance mapping showed little to no difference of arsenic profiles and residual damage between batch and single wafer implantation conditions when the sample temperature during implantation was kept below 120° C.

  10. Comparison of Gold Bonding with Mercury Bonding

    NARCIS (Netherlands)

    Kraka, Elfi; Filatov, Michael; Cremer, Dieter

    2009-01-01

    Nine AuX molecules (X = H, O, S, Se, Te, F, Cl, Br, I), their isoelectronic HgX(+) analogues, and the corresponding neutral HgX diatomics have been investigated using NESC (Normalized Elimination of the Small Component) and B3LYP theory to determine relativistic effects for bond dissociation energie

  11. Comparison of Gold Bonding with Mercury Bonding

    NARCIS (Netherlands)

    Kraka, Elfi; Filatov, Michael; Cremer, Dieter

    2009-01-01

    Nine AuX molecules (X = H, O, S, Se, Te, F, Cl, Br, I), their isoelectronic HgX(+) analogues, and the corresponding neutral HgX diatomics have been investigated using NESC (Normalized Elimination of the Small Component) and B3LYP theory to determine relativistic effects for bond dissociation

  12. The dissociative bond.

    Science.gov (United States)

    Gordon, Nirit

    2013-01-01

    Dissociation leaves a psychic void and a lingering sense of psychic absence. How do 2 people bond while they are both suffering from dissociation? The author explores the notion of a dissociative bond that occurs in the aftermath of trauma--a bond that holds at its core an understanding and shared detachment from the self. Such a bond is confined to unspoken terms that are established in the relational unconscious. The author proposes understanding the dissociative bond as a transitional space that may not lead to full integration of dissociated knowledge yet offers some healing. This is exemplified by R. Prince's (2009) clinical case study. A relational perspective is adopted, focusing on the intersubjective aspects of a dyadic relationship. In the dissociative bond, recognition of the need to experience mutual dissociation can accommodate a psychic state that yearns for relationship when the psyche cannot fully confront past wounds. Such a bond speaks to the need to reestablish a sense of human relatedness and connection when both parties in the relationship suffer from disconnection. This bond is bound to a silence that becomes both a means of protection against the horror of traumatic memory and a way to convey unspoken gestures toward the other.

  13. The samurai bond market

    OpenAIRE

    1997-01-01

    Issuance in the samurai bond market has more than tripled over the past several years. Some observers have attributed this growth to a systematic underestimation of credit risk in the market. A detailed review of credit quality, ratings differences, and initial issue pricing in the samurai bond market, however, turns up little evidence to support this concern.

  14. Dry adhesive bonding of nanoporous inorganic membranes to microfluidic devices using the OSTE(+) dual-cure polymer

    Science.gov (United States)

    Saharil, Farizah; Forsberg, Fredrik; Liu, Yitong; Bettotti, Paolo; Kumar, Neeraj; Niklaus, Frank; Haraldsson, Tommy; van der Wijngaart, Wouter; Gylfason, Kristinn B.

    2013-02-01

    We present two transfer bonding schemes for incorporating fragile nanoporous inorganic membranes into microdevices. Such membranes are finding increasing use in microfluidics, due to their precisely controllable nanostructure. Both schemes rely on a novel dual-cure dry adhesive bonding method, enabled by a new polymer formulation: OSTE(+), which can form bonds at room temperature. OSTE(+) is a novel dual-cure ternary monomer system containing epoxy. After the first cure, the OSTE(+) is soft and suitable for bonding, while during the second cure it stiffens and obtains a Young’s modulus of 1.2 GPa. The ability of the epoxy to react with almost any dry surface provides a very versatile fabrication method. We demonstrate the transfer bonding of porous silicon and porous alumina membranes to polymeric microfluidic chips molded into OSTE(+), and of porous alumina membranes to microstructured silicon wafers, by using the OSTE(+) as a thin bonding layer. We discuss the OSTE(+) dual-cure mechanism, describe the device fabrication and evaluate the bond strength and membrane flow properties after bonding. The membranes bonded to OSTE(+) chips delaminate at 520 kPa, and the membranes bonded to silicon delaminate at 750 kPa, well above typical maximum pressures applied to microfluidic circuits. Furthermore, no change in the membrane flow resistance was observed after bonding.

  15. Corporate Bonds in Denmark

    DEFF Research Database (Denmark)

    Tell, Michael

    2015-01-01

    Corporate financing is the choice between capital generated by the corporation and capital from external investors. However, since the financial crisis shook the markets in 2007–2008, financing opportunities through the classical means of financing have decreased. As a result, corporations have...... to think in alternative ways such as issuing corporate bonds. A market for corporate bonds exists in countries such as Norway, Germany, France, the United Kingdom and the United States, while Denmark is still behind in this trend. Some large Danish corporations have instead used foreign corporate bonds...... markets. However, NASDAQ OMX has introduced the First North Bond Market in December 2012 and new regulatory framework came into place in 2014, which may contribute to a Danish based corporate bond market. The purpose of this article is to present the regulatory changes in Denmark in relation to corporate...

  16. Sodium contamination of SiO2 caused by anodic bonding

    Science.gov (United States)

    Schjølberg-Henriksen, K.; Jensen, G. U.; Hanneborg, A.; Jakobsen, H.

    2003-11-01

    In this paper we present an investigation of sodium contamination of SiO2 (oxide) during anodic bonding. Sodium contamination can be deleterious to the electrical properties of silicon structures. Silicon wafers with metal-oxide semiconductor (MOS) capacitors were bonded to Corning 7740 (Pyrex) glass wafers. The concentration of mobile ions was measured on capacitors outside and within glass cavities using the triangular voltage sweep method. Using secondary ion mass spectrometry analysis, it was confirmed that the ions were sodium. We found an increase in sodium concentration Nm between 1010 and 1013 cm-2, depending on the oxide location and the geometry of the glass cavity. The gate aluminium of the MOS capacitor was found to partly shield the oxide from contamination, causing a two to five times smaller increase in Nm. Reducing the bonding voltage from 800 to 500 V did not affect the increase in Nm significantly. In contrast, changing the ambient in the bonding chamber from vacuum to 1020 mbar air, reduced the contamination of capacitors situated outside the glass. A plasma-enhanced chemical vapour deposited Si3N4 film was found to be very beneficial in protecting the capacitors. The Si3N4 prevented sodium contamination of the capacitors situated within the glass cavities, and radically reduced the contamination of the capacitors situated outside the glass. The results suggest that the contaminating sodium originated from the bulk glass.

  17. A New Activation Method for Electroless Metal Plating: Palladium Laden via Bonding with Self-Assembly Monolayers

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    A new activation method has been developed for electroless copper plating on silicon wafer based on palladium chemisorption on SAMs of APTS without SnCl2 sensitization and roughening condition. A closely packed electroless copper film with strong adhesion is successfully fonned by AFM observation. XPS study indicates that palladium chemisorption occurred via palladium chloride bonding to the pendant amino group of the SAMs.

  18. 圆片级真空封装技术在MEMS陀螺中的应用%Application of Wafer-Level Vacuum Packaging Technology for MEMS Gyroscopes

    Institute of Scientific and Technical Information of China (English)

    杨静; 张富强

    2012-01-01

    In order to maintain the vacuum required for MEMS silicon micro gyroscopes, the wafer-level vacuum hermetic packaging of MEMS silicon micro gyroscopes was realized using the silicon-glass anodic bonding for two times and long-term vacuum maintenance technology. The manufactu-ring process consists of bonding the silicon and glass, etching the silicon vibration structure on the silicon-glass base by DRIE, packaging in a vacuum environment of 10-5 mbar (1 mbar= 100 Pa) by MEMS wafer-level anodic bonding and achieving long-term vacuum by using getters. The test results show that the fabricated silicon micro gyroscope has the smooth anodic bonding interface without any bubble, and the leakage rate is lower than 5. 0× 10-8 atm·cm3/s. After the ceramic packaging for chips, the measured quality factor is higher than 12 000 under the static condition. And the performance is stable without change after the continuous monitoring for one year.%为维持MEMS硅微陀螺的真空度,利用两次硅-玻璃阳极键合和真空长期维持技术,实现了MEMS硅微陀螺的圆片级真空气密性封装.制作过程包括:先将硅和玻璃键合,在硅-玻璃衬底上采用DRIE工艺刻蚀出硅振动结构;再利用MEMS圆片级阳极键合工艺在10-5 mbar(1 mbar=100 Pa)真空环境中进行封装;最后利用吸气剂实现圆片的长期真空气密性.经测试,采用这种方式制作出的硅微陀螺键合界面均匀平整无气泡,漏率低于5.0×10-8atm·cm3/s.对芯片进行陶瓷封装,静态下测试得出品质因数超过12 000,并对样品进行连续一年监测,性能稳定无变化.

  19. Thin film metal sensors in fusion bonded glass chips for high-pressure microfluidics

    Science.gov (United States)

    Andersson, Martin; Ek, Johan; Hedman, Ludvig; Johansson, Fredrik; Sehlstedt, Viktor; Stocklassa, Jesper; Snögren, Pär; Pettersson, Victor; Larsson, Jonas; Vizuete, Olivier; Hjort, Klas; Klintberg, Lena

    2017-01-01

    High-pressure microfluidics offers fast analyses of thermodynamic parameters for compressed process solvents. However, microfluidic platforms handling highly compressible supercritical CO2 are difficult to control, and on-chip sensing would offer added control of the devices. Therefore, there is a need to integrate sensors into highly pressure tolerant glass chips. In this paper, thin film Pt sensors were embedded in shallow etched trenches in a glass wafer that was bonded with another glass wafer having microfluidic channels. The devices having sensors integrated into the flow channels sustained pressures up to 220 bar, typical for the operation of supercritical CO2. No leakage from the devices could be found. Integrated temperature sensors were capable of measuring local decompression cooling effects and integrated calorimetric sensors measured flow velocities over the range 0.5-13.8 mm s-1. By this, a better control of high-pressure microfluidic platforms has been achieved.

  20. Shaped silicon wafers obtained by hot plastic deformation: performance evaluation for future astronomical x-ray telescopes.

    Science.gov (United States)

    Ezoe, Yuichiro; Shirata, Takayuki; Mitsuishi, Ikuyuki; Ishida, Manabu; Mitsuda, Kazuhisa; Morishita, Kohei; Nakajima, Kazuo

    2009-07-01

    In order to develop lightweight and high angular resolution x-ray mirrors, we have investigated hot plastic deformation of 4 in. silicon (111) wafers. A sample wafer was deformed using hemispherical dies with a curvature radius of 1000 mm. The measured radius of the deformed wafer was 1030 mm, suggesting that further conditioning is indispensable for better shaping. For the first time to our knowledge, x-ray reflection on a deformed wafer was detected at Al K(alpha) 1.49 keV. An estimated surface roughness of <1 nm from the x-ray reflection profile was comparable to that of a bare silicon wafer without deformation. Hence, no significant degradation of the microroughness was seen.

  1. Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

    Directory of Open Access Journals (Sweden)

    Prithviraj Chakraborty

    2013-01-01

    Full Text Available Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR. Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A, and lactose monohydrate as ingredient, of hydrophilic matrix former (B on the bioadhesive force, disintegration time, percent (% swelling index, and time taken for 70% drug release (t70%. The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design.

  2. TwinGrid: A wafer post-processed multistage Micro Patterned Gaseous Detector

    NARCIS (Netherlands)

    Bilevych, Y.; Blanco Carballo, V.M.; Chefdeville, M.; Fransen, M.; van der Graaf, H.; Salm, C.; Schmitz, J.; Timmermans, J.

    2009-01-01

    This paper presents a new multistage Micro Patterned Gaseous Detector (MPGD) made by wafer post-processing. The device consists of a double metal grid supported by SU-8 structures on top of a Timepix chip. The detector has been operated with He/iC(4)H(10) and Ar/iC(4)H(10) gas mixtures. Cosmic rays

  3. Twingrid: a wafer post-processed multistage micro patterned gaseous detector

    NARCIS (Netherlands)

    Bilevych, Y.; Blanco Carballo, V.M.; Chefdeville, M.A.; Fransen, M.; Graaf, van der H.; Salm, C.; Schmitz, J.; Timmermans, J.

    2009-01-01

    This paper presents a new multistage Micro Patterned Gaseous Detector (MPGD) made by wafer post-processing. The device consists of a double metal grid supported by SU-8 structures on top of a Timepix chip. The detector has been operated with He/iC4H10 and Ar/iC4H10 gas mixtures. Cosmic rays as well

  4. Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

    Science.gov (United States)

    Sun, Q. M.; Melnikov, A.; Mandelis, A.

    2015-06-01

    Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

  5. Wafer-level heterogeneous 3D integration for MEMS and NEMS

    OpenAIRE

    Niklaus, Frank; Lapisa, Martin; Bleiker, Simon J.; Dubois, Valentin; Roxhed, Niclas; Fischer, Andreas C.; Forsberg, Fredrik; Stemme, Goran; Grogg, Daniel; Despont, Michel

    2012-01-01

    In this paper the state-of-the-art in wafer-level heterogeneous 3D integration technologies for micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) is reviewed. Various examples of commercial and experimental heterogeneous 3D integration processes for MEMS and NEMS devices are presented and discussed. QC 20120907

  6. Wafer level reliability monitoring strategy of an advanced multi-process CMOS foundry

    NARCIS (Netherlands)

    Scarpa, Andrea; Tao, Guoqiao; Kuper, F.G.

    2000-01-01

    In an advanced multi-process CMOS foundry it is strategically important to make use of an optimum reliability monitoring strategy, in order to be able to run well controlled processes. Philips Semiconductors Business Unit Foundries wafer fab MOS4YOU has developed an end-of-line ultra-fast

  7. Building the future of WaferSat spacecraft for relativistic spacecraft

    Science.gov (United States)

    Brashears, Travis; Lubin, Philip; Rupert, Nic; Stanton, Eric; Mehta, Amal; Knowles, Patrick; Hughes, Gary B.

    2016-09-01

    Recently, there has been a dramatic change in the way space missions are viewed. Large spacecraft with massive propellant-filled launch stages have dominated the space industry since the 1960's, but low-mass CubeSats and low-cost rockets have enabled a new approach to space exploration. In recent work, we have built upon the idea of extremely low mass (sub 1 kg), propellant-less spacecraft that are accelerated by photon propulsion from dedicated directed-energy facilities. Advanced photonics on a chip with hybridized electronics can be used to implement a laser-based communication system on board a sub 1U spacecraft that we call a WaferSat. WaferSat spacecraft are equipped with reflective sails suitable for propulsion by directed-energy beams. This low-mass spacecraft design does not require onboard propellant, creating significant new opportunities for deep space exploration at a very low cost. In this paper, we describe the design of a prototype WaferSat spacecraft, constructed on a printed circuit board. The prototype is envisioned as a step toward a design that could be launched on an early mission into Low Earth Orbit (LEO), as a key milestone in the roadmap to interstellar flight. In addition to laser communication, the WaferSat prototype includes subsystems for power source, attitude control, digital image acquisition, and inter-system communications.

  8. The multi-motion-overlap algorithms for minimizing the time between successive scans of wafer stage

    Institute of Scientific and Technical Information of China (English)

    Pan Haihong; Chen Lin; Li Xiaoqing; Zhou Yunfei

    2008-01-01

    In order to optimize the transitional time during the successive exposure seam for a step-and-scan lithography and improve the productivity in a wafer production process, an investigation of the motion trajectory planning along the scanning direction for wafer stage was carried out.The motions of wafer stage were divided into two respective logical moves ( i.e.step-move and scan-move) and the multi-motionoverlap algorithms (MMOA) were presented for optimizing the transitional time between the successive exposure scans.The conventional motion planning method, the Hazehon method and the MMOA were analyzed theoretically and simulated using MATLAB under four different exposure field sizes.The results show that the total time between two successive scans consumed by MMOA is reduced by 4.82%,2.62%, 3.06% and 3.96%, compared with those of the conventional motion planning method; and reduced by 2.58%, 0.76%, 1.63% and 2.92%, compared with those of the Hazehon method respectively.The theoretical analyses and simulation results illuminate that the MMOA can effectively minimize the transitional step time between successive exposure scans and therefore increase the wafer fabricating productivity.

  9. Productivity improvement through automated operation of reticle defect inspection tools in a wafer fab environment

    Science.gov (United States)

    Holfeld, Christian; Wagner, Heiko; Tchikoulaeva, Anna; Loebeth, Steffen; Melzig, Stephan; Zhang, Yulin; Tanabe, Shinichi; Katoh, Takenori; Moriizumi, Koichi

    2013-04-01

    Traditionally, product development for reticle defect inspection mostly addressed operational requirements of the mask shops with highly individualized manufacturing. As a result, limited automation capability was available as compared to the standards in wafer production. Wafer fabs are guided by completely different conditions. Thousands of active reticles exist in a single fab requiring frequent re-inspections without interruption of wafer exposures. This requires high throughput of inspection tools, smart management of tool fleet, sophisticated scheduling and in-time execution of reticle inspections linked to the wafer manufacturing. The paper reports about the successful implementation of fully automated reticle defect inspection in a high-volume advanced logic fab. Automation scenarios - created based on existing SEMI standards - included inspection scheduling, reticle transport and inspection tool operation. A considerable productivity gain for the operation of Lasertec MATRICS X700 series inspection tools was obtained. Based on the learning throughout implementation, the requirements to the automation capability and tool operation as well as adjustments to working procedures are discussed.

  10. Development of a wafer warpage measurement technique using Moiré-based method.

    Science.gov (United States)

    Hsieh, Hung-Lin; Huang, Yung-Guang; Tsai, Yu-Hsuan; Huang, Yao-Hui

    2016-06-01

    This paper reports on a novel technique for measuring wafer warpage, using the design concepts of moiré shift, digital moiré, autocollimator, and the scanning profiling method. The measurement system is divided into two parts: an optical moiré system and a phase analysis system. The optical arrangement can be adjusted to control the projection of a linear grating image onto the surface of a wafer to be reflected back into a CCD camera. The grating image acquired by the CCD camera is used for measurement whereas a reference grating image is obtained using the digital moiré method. By overlapping the two images of the measurement and the reference gratings, the corresponding moiré fringes are formed. The phase of the moiré fringes will change proportionally to the degree of warpage in the wafer, which can be measured by detecting variations in the phase shift of the moiré fringes in the scanning profile across the surface of the entire wafer. Measurement resolution can be controlled by adjusting the pitch size of the grating or the focal length of the focusing lens, or by adjusting the angle between the images of the measurement and reference gratings. Experiment results demonstrate that the proposed method is able to achieve an angular resolution of 0.2 μrad. As compared to the current warpage measurement techniques, the proposed method has the ability of high measurement resolution, high stability, and high flexibility.

  11. Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

    Science.gov (United States)

    Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

    2016-03-01

    With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

  12. Physical chemistry of water droplets in wafer cleaning with low water use

    NARCIS (Netherlands)

    Donck, J.C.J. van der; Bakker, J.; Smeltink, J.A.; Kolderweij, R.B.J.; Zon, B.C.M.B. van der; Kleef, M.H. van

    2015-01-01

    Reduction of water and energy consumption is of importance for keeping viable industry in Europe. In 2012 the Eniac project Silver was started in order to reduce water and energy consumption in the semiconductor industry by 10% [1]. Cleaning of wafers is one of the key process steps that require a h

  13. Automatic Semiconductor Wafer Image Segmentation for Defect Detection Using Multilevel Thresholding

    Directory of Open Access Journals (Sweden)

    Saad N.H.

    2016-01-01

    Full Text Available Quality control is one of important process in semiconductor manufacturing. A lot of issues trying to be solved in semiconductor manufacturing industry regarding the rate of production with respect to time. In most semiconductor assemblies, a lot of wafers from various processes in semiconductor wafer manufacturing need to be inspected manually using human experts and this process required full concentration of the operators. This human inspection procedure, however, is time consuming and highly subjective. In order to overcome this problem, implementation of machine vision will be the best solution. This paper presents automatic defect segmentation of semiconductor wafer image based on multilevel thresholding algorithm which can be further adopted in machine vision system. In this work, the defect image which is in RGB image at first is converted to the gray scale image. Median filtering then is implemented to enhance the gray scale image. Then the modified multilevel thresholding algorithm is performed to the enhanced image. The algorithm worked in three main stages which are determination of the peak location of the histogram, segmentation the histogram between the peak and determination of first global minimum of histogram that correspond to the threshold value of the image. The proposed approach is being evaluated using defected wafer images. The experimental results shown that it can be used to segment the defect correctly and outperformed other thresholding technique such as Otsu and iterative thresholding.

  14. Laser cutting silicon-glass double layer wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Yang, Lijun; Zhang, Hongzhi; Wang, Yang

    2016-07-01

    This study was aimed at introducing the laser induced thermal-crack propagation (LITP) technology to solve the silicon-glass double layer wafer dicing problems in the packaging procedure of silicon-glass device packaged by WLCSP technology, investigating the feasibility of this idea, and studying the crack propagation process of LITP cutting double layer wafer. In this paper, the physical process of the 1064 nm laser beam interact with the double layer wafer during the cutting process was studied theoretically. A mathematical model consists the volumetric heating source and the surface heating source has been established. The temperature and stress distribution was simulated by using finite element method (FEM) analysis software ABAQUS. The extended finite element method (XFEM) was added to the simulation as the supplementary features to simulate the crack propagation process and the crack propagation profile. The silicon-glass double layer wafer cutting verification experiment under typical parameters was conducted by using the 1064 nm semiconductor laser. The crack propagation profile on the fracture surface was examined by optical microscope and explained from the stress distribution and XFEM status. It was concluded that the quality of the finished fracture surface has been greatly improved, and the experiment results were well supported by the numerical simulation results.

  15. Modeling of etch profile evolution including wafer charging effects using self consistent ion fluxes

    Energy Technology Data Exchange (ETDEWEB)

    Hoekstra, R.J.; Kushner, M.J. [Univ. of Illinois, Urbana, IL (United States). Dept. of Electrical and Computer Engineering

    1996-12-31

    As high density plasma reactors become more predominate in industry, the need has intensified for computer aided design tools which address both equipment issues such as ion flux uniformity onto the water and process issues such etch feature profile evolution. A hierarchy of models has been developed to address these issues with the goal of producing a comprehensive plasma processing design capability. The Hybrid Plasma Equipment Model (HPEM) produces ion and neutral densities, and electric fields in the reactor. The Plasma Chemistry Monte Carlo Model (PCMC) determines the angular and energy distributions of ion and neutral fluxes to the wafer using species source functions, time dependent bulk electric fields, and sheath potentials from the HPEM. These fluxes are then used by the Monte Carlo Feature Profile Model (MCFP) to determine the time evolution of etch feature profiles. Using this hierarchy, the effects of physical modifications of the reactor, such as changing wafer clamps or electrode structures, on etch profiles can be evaluated. The effects of wafer charging on feature evolution are examined by calculating the fields produced by the charge deposited by ions and electrons within the features. The effect of radial variations and nonuniformity in angular and energy distribution of the reactive fluxes on feature profiles and feature charging will be discussed for p-Si etching in inductively-coupled plasma (ICP) sustained in chlorine gas mixtures. The effects of over- and under-wafer topography on etch profiles will also be discussed.

  16. Wafer level reliability monitoring strategy of an advanced multi-process CMOS foundry

    NARCIS (Netherlands)

    Scarpa, Andrea; Tao, Guoqiao; Kuper, Fred G.

    2000-01-01

    In an advanced multi-process CMOS foundry it is strategically important to make use of an optimum reliability monitoring strategy, in order to be able to run well controlled processes. Philips Semiconductors Business Unit Foundries wafer fab MOS4YOU has developed an end-of-line ultra-fast reliabilit

  17. Fully-vectorial simulation and tolerancing of optical systems for wafer inspection by field tracing

    Science.gov (United States)

    Asoubar, Daniel; Schweitzer, Hagen; Hellmann, Christian; Kuhn, Michael; Wyrowski, Frank

    2015-06-01

    The simulation, design and tolerancing of optical systems for wafer inspection is a challenging task due to the different feature sizes, which are involved in these systems. On the one hand light is propagated through macroscopic lens systems and on the other hand light is diffracted at microscopic structures with features in the range of the wavelength of light. Due to this variety of scale plenty of different physical effects like refraction, diffraction, interference and polarization have to be taken into account for a realistic analysis of such inspection systems. We show that all of these effects can be included in a system simulation by field tracing, which combines physical and geometrical optics. The main idea is the decomposition of the complex optical setup in a sequence of subdomains. Per subdomain a different approximative or rigorous solution of Maxwell's equations is applied to propagate the light. In this work the different modeling techniques for the analysis of an exemplary wafer inspection system are discussed in detail. These techniques are mainly geometrical optics for the light propagation through macroscopic lenses, a rigorous Fourier Modal Method (FMM) for the modeling of light diffraction at the wafer microstructure and different free-space diffraction integrals. In combination with a numerically efficient algorithm for the coordinate transformation of electromagnetic fields, field tracing enables position and fabrication tolerancing. As an example different tilt tolerance effects on the polarization state and image contrast of a simple wafer inspection system are shown.

  18. Fast movement strategies for a step-and-scan wafer stepper

    NARCIS (Netherlands)

    Kuipers, C.M.H.; Hurkens, C.A.J.; Melissen, J.B.M.

    We describe algorithms for the determination of fast movement strategies for a step-and-scan wafer stepper, a device that is used for the photolithographic processing of integrated circuits. The proposed solution strategy consists of two parts. First, we determine the maximum number of congruent

  19. Wafer-Scale Leaning Silver Nanopillars for Molecular Detection at Ultra-Low Concentrations

    DEFF Research Database (Denmark)

    Wu, Kaiyu; Rindzevicius, Tomas; Schmidt, Michael Stenbæk;

    2015-01-01

    Wafer-scale surface-enhanced Raman scattering (SERS) substrates fabricated using maskless lithography are important for scalable production targets. Large-area, leaning silver-capped silicon nanopillar (Ag NP) structures suitable for SERS molecular detection at extremely low analyte concentration...

  20. Dimensional Control in Corner Lithography for Wafer-Scale Fabrication of Nano-Apertures

    NARCIS (Netherlands)

    Burouni, N.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Tas, Niels Roelof

    2011-01-01

    In this paper we investigate a new method to fabricate 3D-oriented nanostructures in wafer scale, and apply it to fabricate a nano-apertures at the apex of a pyramid. A number of new technologies require the use of apertures to serve as electrical, nano fluidic or optical probes. Controlling the