WorldWideScience

Sample records for volume iii hardware

  1. On Issues of Precision for Hardware-based Volume Visualization

    Energy Technology Data Exchange (ETDEWEB)

    LaMar, E C

    2003-04-11

    This paper discusses issues with the limited precision of hardware-based volume visualization. We will describe the compositing OVER operator and how fixed-point arithmetic affects it. We propose two techniques to improve the precision of fixed-point compositing and the accuracy of hardware-based volume visualization. The first technique is to perform dithering of color and alpha values. The second technique we call exponent-factoring, and captures significantly more numeric resolution than dithering, but can only produce monochromatic images.

  2. S-1 project. Volume II. Hardware. 1979 annual report

    Energy Technology Data Exchange (ETDEWEB)

    1979-01-01

    This volume includes highlights of the design of the Mark IIA uniprocessor (SMI-2), and the SCALD II user's manual. SCALD (structured computer-aided logic design system) cuts the cost and time required to design logic by letting the logic designer express ideas as naturally as possible, and by eliminating as many errors as possible - through consistency checking, simulation, and timing verification - before the hardware is built. (GHT)

  3. [A hybrid volume rendering method using general hardware].

    Science.gov (United States)

    Li, Bin; Tian, Lianfang; Chen, Ping; Mao, Zongyuan

    2008-06-01

    In order to improve the effect and efficiency of the reconstructed image after hybrid volume rendering of different kinds of volume data from medical sequential slices or polygonal models, we propose a hybrid volume rendering method based on Shear-Warp with economical hardware. First, the hybrid volume data are pre-processed by Z-Buffer method and RLE (Run-Length Encoded) data structure. Then, during the process of compositing intermediate image, a resampling method based on the dual-interpolation and the intermediate slice interpolation methods is used to improve the efficiency and the effect. Finally, the reconstructed image is rendered by the texture-mapping technology of OpenGL. Experiments demonstrate the good performance of the proposed method.

  4. The SIFT hardware/software systems. Volume 2: Software listings

    Science.gov (United States)

    Palumbo, Daniel L.

    1985-01-01

    This document contains software listings of the SIFT operating system and application software. The software is coded for the most part in a variant of the Pascal language, Pascal*. Pascal* is a cross-compiler running on the VAX and Eclipse computers. The output of Pascal* is BDX-390 assembler code. When necessary, modules are written directly in BDX-390 assembler code. The listings in this document supplement the description of the SIFT system found in Volume 1 of this report, A Detailed Description.

  5. Software/hardware optimization for attenuation-based microtomography using SR at PETRA III (Conference Presentation)

    Science.gov (United States)

    Beckmann, Felix

    2016-10-01

    The Helmholtz-Zentrum Geesthacht, Germany, is operating the user experiments for microtomography at the beamlines P05 and P07 using synchrotron radiation produced in the storage ring PETRA III at DESY, Hamburg, Germany. In recent years the software pipeline, sample changing hardware for performing high throughput experiments were developed. In this talk the current status of the beamlines will be given. Furthermore, optimisation and automatisation of scanning techniques, will be presented. These are required to scan samples which are larger than the field of view defined by the X-ray beam. The integration into an optimized reconstruction pipeline will be shown.

  6. 76 FR 60511 - Amendment of Marine Safety Manual, Volume III

    Science.gov (United States)

    2011-09-29

    ... SECURITY Coast Guard Amendment of Marine Safety Manual, Volume III AGENCY: Coast Guard, DHS. ACTION: Notice... Offshore Units. The policy is currently found in Chapter 16 of the Marine Safety Manual, Volume III. The... Federal Register (73 FR 3316). Background and Purpose Chapter 16 of Volume III of the Marine Safety...

  7. Spent fuel assembly hardware: Characterization and 10 CFR 61 classification for waste disposal: Volume 3, Calculated activity profiles of spent nuclear fuel assembly hardware for boiling water reactors

    Energy Technology Data Exchange (ETDEWEB)

    Short, S.M.; Luksic, A.T.; Schutz, M.E.

    1989-06-01

    Consolidation of spent fuel is under active consideration as the US Department of Energy plans to dispose of spent fuel as required by the Nuclear Waste Policy Act of 1982. During consolidation, the fuel pins are removed from an intact fuel assembly and repackaged into a more compact configuration. After repackaging, approximately 30 kg of residual spent fuel assembly hardware per assembly that is also radioactive and required disposal. Understanding the nature of this secondary waste stream is critical to designing a system that will properly handle, package, store, and dispose of the waste. This report presents a methodology for estimating the radionuclide inventory in irradiated spent fuel hardware. Ratios are developed that allow the use of ORIGEN2 computer code calculations to be applied to regions that are outside the fueled region. The ratios are based on the analysis of samples of irradiated hardware from spent fuel assemblies. The results of this research are presented in three volumes. In Volume 1, the development of scaling factors that can be used with ORIGEN2 calculations to estimate activation of spent fuel assembly hardware is documented. The results from laboratory analysis of irradiated spent-fuel hardware samples are also presented in Volume 1. In Volume 2 and 3, the calculated flux profiles of spent nuclear fuel assemblies are presented for pressurized water reactors and boiling water reactors, respectively. The results presented in Volumes 2 and 3 were used to develop the scaling factors documented in Volume 1.

  8. Spent fuel assembly hardware: Characterization and 10 CFR 61 classification for waste disposal: Volume 1, Activation measurements and comparison with calculations for spent fuel assembly hardware

    Energy Technology Data Exchange (ETDEWEB)

    Luksic, A.

    1989-06-01

    Consolidation of spent fuel is under active consideration as the US Department of Energy plans to dispose of spent fuel. During consolidation, the fuel pins are removed from an intact fuel assembly and repackaged into a more compact configuration. After repackaging, approximately 30 kg of residual spent fuel assembly hardware per assembly remains that is also radioactive and requires disposal. Understanding the nature of this secondary waste stream is critical to designing a system that will properly handle, package, store, and dispose of the waste. This report presents a methodology for estimating the radionuclide inventory in irradiated spent fuel hardware. Ratios are developed that allow the use of ORIGEN2 computer code calculations to be applied to regions that are outside the fueled region. The ratios are based on the analysis of samples of irradiated hardware from spent fuel assemblies. The results of this research are presented in three volumes. In Volume 1, the development of scaling factors that can be used with ORIGEN2 calculations to estimate activation of spent fuel assembly hardware is documented. The results from laboratory analysis of irradiated spent-fuel hardware samples are also presented in Volume 1. In Volumes 2 and 3, the calculated flux profiles of spent nuclear fuel assemblies are presented for pressurized water reactors and boiling water reactors, respectively. The results presented in Volumes 2 and 3 were used to develop the scaling factors documented in Volume 1. 5 refs., 4 figs., 21 tabs.

  9. Spent fuel assembly hardware: Characterization and 10 CFR 61 classification for waste disposal: Volume 2, Calculated activity profiles of spent nuclear fuel assembly hardware for pressurized water reactors

    Energy Technology Data Exchange (ETDEWEB)

    Short, S.M.; Luksic, A.T.; Lotz, T.L.; Schutz, M.E.

    1989-06-01

    Consolidation of spent fuel is under active consideration as the US Department of Energy plans to dispose of spent fuel as required by the Nuclear Waste Policy Act of 1982. During consolidation, the fuel pins are removed from an intact fuel assembly and repackaged into a more compact configuration. After repackaging, approximately 30 kg of residual spent fuel assembly hardware per assembly remains that is also radioactive and requires disposal. Understanding the nature of this secondary waste stream is critical to designing a system that will properly handle, package, store, and dispose of the waste. This report present a methodology for estimating the radionuclide inventory in irradiated spent fuel hardware. Ratios are developed that allow the use of ORIGEN2 computer code calculations to be applied to regions that are outside the fueled region. The ratios are based on the analysis of samples of irradiated hardware from spent fuel assemblies. The results of this research are presented in three volumes. In Volume 1, the development of scaling factors that can be used with ORIGEN2 calculations to estimate activation of spent fuel assembly hardware is documented. The results from Laboratory analysis of irradiated spent-fuel hardware samples are also presented in Volume 1. In Volumes 2 and 3, the calculated flux profiles of spent nuclear fuel assemblies are presented for pressurized water reactors and boiling water reactors, respectively. The results presented in Volumes 2 and 3 were used to develop the scaling factors documented in Volume 1.

  10. Accelerating Time-Varying Hardware Volume Rendering Using TSP Trees and Color-Based Error Metrics

    Science.gov (United States)

    Ellsworth, David; Chiang, Ling-Jen; Shen, Han-Wei; Kwak, Dochan (Technical Monitor)

    2000-01-01

    This paper describes a new hardware volume rendering algorithm for time-varying data. The algorithm uses the Time-Space Partitioning (TSP) tree data structure to identify regions within the data that have spatial or temporal coherence. By using this coherence, the rendering algorithm can improve performance when the volume data is larger than the texture memory capacity by decreasing the amount of textures required. This coherence can also allow improved speed by appropriately rendering flat-shaded polygons instead of textured polygons, and by not rendering transparent regions. To reduce the polygonization overhead caused by the use of the hierarchical data structure, we introduce an optimization method using polygon templates. The paper also introduces new color-based error metrics, which more accurately identify coherent regions compared to the earlier scalar-based metrics. By showing experimental results from runs using different data sets and error metrics, we demonstrate that the new methods give substantial improvements in volume rendering performance.

  11. Culture of Schools. Final Report. Volume III.

    Science.gov (United States)

    American Anthropological Association, Washington, DC.

    The third volume of this 4-volume report contains the last two speeches, on educational philosophy and the role of reason in society, from the Colloquium on the Culture of Schools held at the New School for Social Research (preceding speeches are in Vol. II, SP 003 901), reports on conferences on the culture of schools held in Pittsburgh and…

  12. Ways to Environmental Education, Volume III.

    Science.gov (United States)

    Allen, Rodney F., Ed.; And Others

    Ten environmental education booklets presented in this document are the third volume of the environmental series developed by community groups around the Tallahassee Junior Museum and its Pioneer Farm. The first three booklets present an overview of the museum and of the various education programs and activities offered for students at the museum…

  13. DART II documentation. Volume III. Appendices

    Energy Technology Data Exchange (ETDEWEB)

    1979-10-01

    The DART II is a remote, interactive, microprocessor-based data acquistion system suitable for use with air monitors. This volume of DART II documentation contains the following appendixes: adjustment and calibration procedures; mother board signature list; schematic diagrams; device specification sheets; ROM program listing; 6800 microprocessor instruction list, octal listing; and cable lists. (RWR)

  14. DART II documentation. Volume III. Appendices

    Energy Technology Data Exchange (ETDEWEB)

    1979-05-23

    The DART II is a data acquisition system that can be used with air pollution monitoring equipment. This volume contains appendices that deal with the following topics: adjustment and calibration procedures (power supply adjustment procedure, ADC calibration procedure, analog multiplexer calibration procedure); mother board signature list; schematic diagrams; device specification sheets (microprocessor, asynchronous receiver/transmitter, analog-to-digital converter, arithmetic processing unit, 5-volt power supply, +- 15-volt power supply, 24-volt power supply, floppy disk formater/controller, random access static memory); ROM program listing; 6800 microprocessor instruction set, octal listing; and cable lists. (RR)

  15. Free radicals in biology. Volume III

    Energy Technology Data Exchange (ETDEWEB)

    Pryor, W.A. (ed.)

    1977-01-01

    This volume covers topics ranging from radiation chemistry to biochemistry, biology, and medicine. This volume attempts to bridge the gap between chemical investigations and the medical applications and implications of free radical reactions. Chapter 1 provides a general introduction to the technique of radiation chemistry, the thermodynamics and kinetic factors that need be considered, the use of pulse radiolysis and flow techniques, and the application of these methods to free radicals of biological interest. Chapter 3 discusses the mechanisms of carbon tetrachloride toxicity. Chapter 4 reviews the morphological, histochemical, biochemical, and chemical nature of lipofuscin pigments. This chapter brings together the evidence that lipofuscin pigments arise from free radical pathology and that the formation of these pigments proves the presence of lipid peroxidation in vivo. Chapter 5 reviews the evidence for production of free (i.e., scavengeable) radicals from the reactions of selected enzymes with their substrates. Chapter 6 discusses one of the systems in which free radical damage is clearly important in vivo, both for man and animal, the damage caused to skin by sunlight. The evidence that free radical reactions can contribute to carcinogenesis dates from the earliest observations that ionizing radiation often produces higher incidences of tumors. A current working hypothesis is that chemical toxins cause damage to DNA and that the repair of this damge may incorporate viral genetic information into the host cell's chromosomes, producing cell transformation and cancer. The mechanism whereby chemical carcinogens become bound to DNA to produce point defects is discussed in Chapter 7.

  16. Technology transfer package on seismic base isolation - Volume III

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1995-02-14

    This Technology Transfer Package provides some detailed information for the U.S. Department of Energy (DOE) and its contractors about seismic base isolation. Intended users of this three-volume package are DOE Design and Safety Engineers as well as DOE Facility Managers who are responsible for reducing the effects of natural phenomena hazards (NPH), specifically earthquakes, on their facilities. The package was developed as part of DOE's efforts to study and implement techniques for protecting lives and property from the effects of natural phenomena and to support the International Decade for Natural Disaster Reduction. Volume III contains supporting materials not included in Volumes I and II.

  17. Orbiter subsystem hardware/software interaction analysis. Volume 8: Forward reaction control system

    Science.gov (United States)

    Becker, D. D.

    1980-01-01

    The results of the orbiter hardware/software interaction analysis for the AFT reaction control system are presented. The interaction between hardware failure modes and software are examined in order to identify associated issues and risks. All orbiter subsystems and interfacing program elements which interact with the orbiter computer flight software are analyzed. The failure modes identified in the subsystem/element failure mode and effects analysis are discussed.

  18. Breckinridge Project, initial effort. Report III, Volume 2. Specifications

    Energy Technology Data Exchange (ETDEWEB)

    None

    1982-01-01

    Report III, Volume 2 contains those specifications numbered K through Y, as follows: Specifications for Compressors (K); Specifications for Piping (L); Specifications for Structures (M); Specifications for Insulation (N); Specifications for Electrical (P); Specifications for Concrete (Q); Specifications for Civil (S); Specifications for Welding (W); Specifications for Painting (X); and Specifications for Special (Y). The standard specifications of Bechtel Petroleum Incorporated have been amended as necessary to reflect the specific requirements of the Breckinridge Project and the more stringent specifications of Ashland Synthetic Fuels, Inc. These standard specifications are available for the Initial Effort (Phase Zero) work performed by all contractors and subcontractors.

  19. Impact of the column hardware volume on resolution in very high pressure liquid chromatography non-invasive investigations.

    Science.gov (United States)

    Gritti, Fabrice; McDonald, Thomas; Gilar, Martin

    2015-11-13

    The impact of the column hardware volume (≃ 1.7 μL) on the optimum reduced plate heights of a series of short 2.1 mm × 50 mm columns (hold-up volume ≃ 80-90 μL) packed with 1.8 μm HSS-T3, 1.7 μm BEH-C18, 1.7 μm CSH-C18, 1.6 μm CORTECS-C18+, and 1.7 μm BEH-C4 particles was investigated. A rapid and non-invasive method based on the reduction of the system dispersion (to only 0.15 μL(2)) of an I-class Acquity system and on the corrected plate heights (for system dispersion) of five weakly retained n-alkanophenones in RPLC was proposed. Evidence for sample dispersion through the column hardware volume was also revealed from the experimental plot of the peak capacities for smooth linear gradients versus the corrected efficiency of a weakly retained alkanophenone (isocratic runs). The plot is built for a constant gradient steepness irrespective of the applied flow rates (0.01-0.30 mL/min) and column lengths (2, 3, 5, and 10 cm). The volume variance caused by column endfittings and frits was estimated in between 0.1 and 0.7 μL(2) depending on the applied flow rate. After correction for system and hardware dispersion, the minimum reduced plate heights of short (5 cm) and narrow-bore (2.1mm i.d.) beds packed with sub-2 μm fully and superficially porous particles were found close to 1.5 and 0.7, respectively, instead of the classical h values of 2.0 and 1.4 for the whole column assembly.

  20. The SIFT hardware/software systems. Volume 1: A detailed description

    Science.gov (United States)

    Palumbo, Daniel L.

    1985-01-01

    This report contains a detailed description of the software implemented fault-tolerant computer's operating system and hardware subsystems. The Software Implemented Fault-Tolerant (SIFT) computer system was developed as an experimental vehicle for fault-tolerant systems research. The SIFT effort began with broad, in-depth studies stating the reliability and processing requirements for digital computers which would, in the aircraft of the 1990's, control flight-critical functions.

  1. Orbiter subsystem hardware/software interaction analysis. Volume 8: AFT reaction control system, part 2

    Science.gov (United States)

    Becker, D. D.

    1980-01-01

    The orbiter subsystems and interfacing program elements which interact with the orbiter computer flight software are analyzed. The failure modes identified in the subsystem/element failure mode and effects analysis are examined. Potential interaction with the software is examined through an evaluation of the software requirements. The analysis is restricted to flight software requirements and excludes utility/checkout software. The results of the hardware/software interaction analysis for the forward reaction control system are presented.

  2. Minerals Yearbook, volume III, Area Reports—International

    Science.gov (United States)

    ,

    2017-01-01

    The U.S. Geological Survey (USGS) Minerals Yearbook discusses the performance of the worldwide minerals and materials industries and provides background information to assist in interpreting that performance. Content of the individual Minerals Yearbook volumes follows:Volume I, Metals and Minerals, contains chapters about virtually all metallic and industrial mineral commodities important to the U.S. economy. Chapters on survey methods, summary statistics for domestic nonfuel minerals, and trends in mining and quarrying in the metals and industrial mineral industries in the United States are also included.Volume II, Area Reports: Domestic, contains a chapter on the mineral industry of each of the 50 States and Puerto Rico and the Administered Islands. This volume also has chapters on survey methods and summary statistics of domestic nonfuel minerals.Volume III, Area Reports: International, is published as four separate reports. These regional reports contain the latest available minerals data on more than 180 foreign countries and discuss the importance of minerals to the economies of these nations and the United States. Each report begins with an overview of the region’s mineral industries during the year. It continues with individual country chapters that examine the mining, refining, processing, and use of minerals in each country of the region and how each country’s mineral industry relates to U.S. industry. Most chapters include production tables and industry structure tables, information about Government policies and programs that affect the country’s mineral industry, and an outlook section.The USGS continually strives to improve the value of its publications to users. Constructive comments and suggestions by readers of the Minerals Yearbook are welcomed.

  3. Simple and inexpensive hardware and software method to measure volume changes in Xenopus oocytes expressing aquaporins.

    Science.gov (United States)

    Dorr, Ricardo; Ozu, Marcelo; Parisi, Mario

    2007-04-15

    Water channels (aquaporins) family members have been identified in central nervous system cells. A classic method to measure membrane water permeability and its regulation is to capture and analyse images of Xenopus laevis oocytes expressing them. Laboratories dedicated to the analysis of motion images usually have powerful equipment valued in thousands of dollars. However, some scientists consider that new approaches are needed to reduce costs in scientific labs, especially in developing countries. The objective of this work is to share a very low-cost hardware and software setup based on a well-selected webcam, a hand-made adapter to a microscope and the use of free software to measure membrane water permeability in Xenopus oocytes. One of the main purposes of this setup is to maintain a high level of quality in images obtained at brief intervals (shorter than 70 ms). The presented setup helps to economize without sacrificing image analysis requirements.

  4. Feasibility study for a numerical aerodynamic simulation facility. Volume 2: Hardware specifications/descriptions

    Science.gov (United States)

    Green, F. M.; Resnick, D. R.

    1979-01-01

    An FMP (Flow Model Processor) was designed for use in the Numerical Aerodynamic Simulation Facility (NASF). The NASF was developed to simulate fluid flow over three-dimensional bodies in wind tunnel environments and in free space. The facility is applicable to studying aerodynamic and aircraft body designs. The following general topics are discussed in this volume: (1) FMP functional computer specifications; (2) FMP instruction specification; (3) standard product system components; (4) loosely coupled network (LCN) specifications/description; and (5) three appendices: performance of trunk allocation contention elimination (trace) method, LCN channel protocol and proposed LCN unified second level protocol.

  5. Industrial Fuel Gas Demonstration Plant Program. Volume III. Demonstration plant environmental analysis (Deliverable No. 27)

    Energy Technology Data Exchange (ETDEWEB)

    1979-08-01

    An Environmental Report on the Memphis Light, Gas and Water Division Industrial Fuel Demonstration Plant was prepared for submission to the US Department of Energy under Contract ET-77-C-01-2582. This document is Volume III of a three-volume Environmental Report. Volume I consists of the Summary, Introduction and the Description of the Proposed Action. Volume II consists of the Description of the Existing Environment. Volume III contains the Environmental Impacts of the Proposed Action, Mitigating Measures and Alternatives to the Proposed Action.

  6. Industrial Maintenance, Volume III. Post Secondary Curriculum Guide.

    Science.gov (United States)

    Butler, Raymond H.; And Others

    This volume is the fourth of four volumes that comprise a curriculum guide for a postsecondary industrial maintenance program. It contains three sections and appendixes. Section 4 provides suggested methods of structuring the curriculum. Suggested ways of recording and documenting student progress are presented in section 5. Section 6 contains…

  7. National Utility Financial Statement model (NUFS). Volume III of III: software description. Final report

    Energy Technology Data Exchange (ETDEWEB)

    1981-10-29

    This volume contains a description of the software comprising the National Utility Financial Statement Model (NUFS). This is the third of three volumes describing NUFS provided by ICF Incorporated under contract DEAC-01-79EI-10579. The three volumes are entitled: model overview and description, user's guide, and software guide.

  8. Higher Education: Handbook of Theory and Research. Volumes III [and] IV.

    Science.gov (United States)

    Smart, John C., Ed.

    Two volumes of a handbook on theory and research in higher education are presented. The 11 papers included in Volume III are as follows: "Qualitative Research Methods in Higher Education" (R. Crowson); "Bricks and Mortar: Architecture and the Study of Higher Education" (J. Thelin and J. Yankovich); "Enrollment Demand Models and Their Policy Uses…

  9. An Evaluation of the Nutrition Services for the Elderly. Volume III. Descriptive Report.

    Science.gov (United States)

    Kirschner Associates, Inc., Albuquerque, NM.

    This document is part of a five-volume nationwide study of Nutrition Services operations and elderly citizens participating in congregate dining and home delivery services authorized by Title III-C of the Older Americans' Act. A descriptive report is contained in this volume, which presents non-selective and preliminary analysis of the data base…

  10. Workpapers in English as a Second Language, [Volume III].

    Science.gov (United States)

    Bracy, Maryruth, Ed.

    This volume contains the 1969 working papers on subjects related to teaching English as a second language (TESL) and abstracts of Masters Theses completed by students studying TESL. Several articles discuss teaching and learning a second language and practical considerations in second language learning such as reading and writing skills, the use…

  11. Council on Anthropology and Education Newsletter. Volume III, Number 1.

    Science.gov (United States)

    Singleton, John Ed.

    General information on format, included, materials, broad concerns, objectives, and availability of the newsletter are described in Volume I, ED 048 049. This issue focuses on ethnology, offering two papers presented at the American Anthropological Association symposiums. The lead paper presents a psycho-cultural developmental approach to the…

  12. Albanian: Basic Course. Volume III, Lessons 27-36.

    Science.gov (United States)

    Defense Language Inst., Monterey, CA.

    This third of ten volumes of audiolingual classroom instruction in Albanian for adult students treats Albanian grammar, syntax, and usage in a series of exercises consisting of grammar perception drills, grammar analysis, translation exercises, readings, question-and-answer exercises, and dialogues illustrating specific grammatical features. A…

  13. An Independent Scientific Assessment of Well Stimulation in California Volume III

    Energy Technology Data Exchange (ETDEWEB)

    Long, Jane C.S. [California Council on Science and Technology, Sacramento, CA (United States); Feinstein, Laura C. [California Council on Science and Technology, Sacramento, CA (United States); Birkholzer, Jens [California Council on Science and Technology, Sacramento, CA (United States); Foxall, William [California Council on Science and Technology, Sacramento, CA (United States); Houseworth, James [California Council on Science and Technology, Sacramento, CA (United States); Jordan, Preston [California Council on Science and Technology, Sacramento, CA (United States); Lindsey, Nathaniel [California Council on Science and Technology, Sacramento, CA (United States); Maddalena, Randy [California Council on Science and Technology, Sacramento, CA (United States); McKone, Thomas [California Council on Science and Technology, Sacramento, CA (United States); Stringfellow, William [California Council on Science and Technology, Sacramento, CA (United States); Ulrich, Craig [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Heberger, Matthew [Pacific Inst., Oakland, CA (United States); Shonkoff, Seth [PSE Healthy Energy, Berkeley, CA (United States); Brandt, Adam [Stanford Univ., CA (United States); Ferrar, Kyle [The FracTracker Alliance, Oakland, CA (United States); Gautier, Donald [DonGautier LLC., Palo Alto, CA (United States); Phillips, Scott [California State Univ. Stanislaus, Turlock, CA (United States); Greenfield, Ben [Univ. of California, Berkeley, CA (United States); Jerrett, Michael L.B. [Univ. of California, Los Angeles, CA (United States)

    2015-07-01

    This study is issued in three volumes. Volume I, issued in January 2015, describes how well stimulation technologies work, how and where operators deploy these technologies for oil and gas production in California, and where they might enable production in the future. Volume II, issued in July 2015, discusses how well stimulation could affect water, atmosphere, seismic activity, wildlife and vegetation, and human health. Volume II reviews available data, and identifies knowledge gaps and alternative practices that could avoid or mitigate these possible impacts. Volume III, this volume, presents case studies that assess environmental issues and qualitative risks for specific geographic regions. The Summary Report summarizes key findings, conclusions and recommendations of all three volumes.

  14. Field Operations and Enforcement Manual for Air Pollution Control. Volume III: Inspection Procedures for Specific Industries.

    Science.gov (United States)

    Weisburd, Melvin I.

    The Field Operations and Enforcement Manual for Air Pollution Control, Volume III, explains in detail the following: inspection procedures for specific sources, kraft pulp mills, animal rendering, steel mill furnaces, coking operations, petroleum refineries, chemical plants, non-ferrous smelting and refining, foundries, cement plants, aluminum…

  15. Field Operations and Enforcement Manual for Air Pollution Control. Volume III: Inspection Procedures for Specific Industries.

    Science.gov (United States)

    Weisburd, Melvin I.

    The Field Operations and Enforcement Manual for Air Pollution Control, Volume III, explains in detail the following: inspection procedures for specific sources, kraft pulp mills, animal rendering, steel mill furnaces, coking operations, petroleum refineries, chemical plants, non-ferrous smelting and refining, foundries, cement plants, aluminum…

  16. Technical Reports (Part I). End of Project Report, 1968-1971, Volume III.

    Science.gov (United States)

    Western Nevada Regional Education Center, Lovelock.

    The pamphlets included in this volume are technical reports prepared as outgrowths of the Student Information Systems of the Western Nevada Regional Education Center (WN-REC) funded by a Title III (Elementary and Secondary Education Act) grant. These reports describe methods of interpreting the printouts from the Student Information System;…

  17. Condylar volume and condylar area in class I, class II and class III young adult subjects

    Directory of Open Access Journals (Sweden)

    Saccucci Matteo

    2012-12-01

    Full Text Available Abstract Aim Aim of this study was to compare the volume and the shape of mandibular condyles in a Caucasian young adult population, with different skeletal pattern. Material and methods 200 Caucasian patients (15–30 years old, 95 male and 105 females were classified in three groups on the base of ANB angle: skeletal class I (65 patients, skeletal class II (70 patients and skeletal class III (65 patients. Left and right TMJs of each subject were evaluated independently with CBCT (Iluma. TMJ evaluation included: condylar volume; condylar area; morphological index (MI. Condylar volumes were calculated by using the Mimics software. The condylar volume, the area and the morphological index (MI were compared among the three groups, by using non-parametric tests. Results The Kruskal-Wallis test and the Mann Whitney test revealed that: no significant difference was observed in the whole sample between the right and the left condylar volume; subjects in skeletal class III showed a significantly higher condylar volume, respect to class I and class II subjects (p 3 in males and 663.5 ± 81.3 mm3 in females; p 2 in males and 389.76 ± 61.15 mm2 in females; p  Conclusion Skeletal class appeared to be associated to the mandibular condylar volume and to the mandibular condylar area in the Caucasian orthodontic population.

  18. Occupational Survey Report. Volume III. Programming Specialty, AFS 511X1.

    Science.gov (United States)

    1980-05-01

    ROGRAMMING 1SPECIALTY _ ".T\\ I , , ~AFPT 90-511-413 q ’VOLUME III OF III ON -Y 1980’ ’ q -ppT edfor public releaw; is: OCCUPATIONAL ANALYSIS PROGRAM ,"’ USAF...i I..... i l HI I . .. I Ij. ASSISTANT PROGRAMMING NCOICs (GRP308) PERCENT MEMBERS RF,-.N i:\\I’IVF ’ASKS PERFORMING L BEl k k ,,it’FR PROGRkM.S 96...EAVE OR LIBERfY 79 SilON,,, K NCOM ING PERSONNEl. 79 ODIF + UPDATE FXISI’ING COMPUTER PROGRAMS 75 REVIEW ,RA. SPECIFICATIONS 75 PREPARE PFIAl IEi) FLOW

  19. Hanford spent nuclear fuel project recommended path forward, volume III: Alternatives and path forward evaluation supporting documentation

    Energy Technology Data Exchange (ETDEWEB)

    Fulton, J.C.

    1994-10-01

    Volume I of the Hanford Spent Nuclear Fuel Project - Recommended Path Forward constitutes an aggressive series of projects to construct and operate systems and facilities to safely retrieve, package, transport, process, and store K Basins fuel and sludge. Volume II provided a comparative evaluation of four Alternatives for the Path Forward and an evaluation for the Recommended Path Forward. Although Volume II contained extensive appendices, six supporting documents have been compiled in Volume III to provide additional background for Volume II.

  20. Condylar volume and condylar area in class I, class II and class III young adult subjects

    OpenAIRE

    Saccucci Matteo; D’Attilio Michele; Rodolfino Daria; Festa Felice; Polimeni Antonella; Tecco Simona

    2012-01-01

    Abstract Aim Aim of this study was to compare the volume and the shape of mandibular condyles in a Caucasian young adult population, with different skeletal pattern. Material and methods 200 Caucasian patients (15–30 years old, 95 male and 105 females) were classified in three groups on the base of ANB angle: skeletal class I (65 patients), skeletal class II (70 patients) and skeletal class III (65 patients). Left and right TMJs of each subject were evaluated independently with CBCT (Iluma). ...

  1. Energy extension service pilot program evaluation report: the first year. Volume III: supplementary reports

    Energy Technology Data Exchange (ETDEWEB)

    None

    1979-09-01

    The appendices presented in this volume support and supplement Volume I of the Energy Extension Service Pilot Program Evaluation Report: The First Year. The appendices contain back-up data and detailed information on energy savings estimation and other analytic procedures. This volume also describes the data sources used for the evaluation. Appendix I presents the Btu estimation procedures used to calculate state-by-state energy savings. Appendix II contains details of the data sources used for the evaluation. Appendix III presents program activity data, budget, and cost per client analyses. Appendix IV, the Multivariate Analysis of EES Survey Data, provides the basis for the Integrating Statistical Analyses. Appendix V describes the rationale and exclusion rules for outlying data points. The final appendix presents program-by-program fuel costs and self-reported savings and investment.

  2. Instrumentation Hardware Abstraction Language (IHAL) Handbook

    Science.gov (United States)

    2017-01-01

    Telemetry Group DOCUMENT 128-17 INSTRUMENTATION HARDWARE ABSTRACTION LANGUAGE (IHAL) HANDBOOK DISTRIBUTION A...intentionally left blank DOCUMENT 128-17 INSTRUMENTATION HARDWARE ABSTRACTION LANGUAGE (IHAL) HANDBOOK January 2017...5100 This page intentionally left blank. Instrumentation Hardware Abstract Language (IHAL) Handbook, RCC Document 128-17, January 2017 iii

  3. World Energy Data System (WENDS). Volume III. Country data, LY-PO

    Energy Technology Data Exchange (ETDEWEB)

    None

    1979-06-01

    The World Energy Data System contains organized data on those countries and international organizations that may have critical impact on the world energy scene. Included in this volume, Vol. III, are Libya, Luxembourg, Malaysia, Mexico, Netherlands, New Zealand, Niger, Nigeria, Norway, Pakistan, Peru, Philippines, Poland, and Portugal. The following topics are covered for most of the countries: economic, demographic, and educational profiles; energy policy; indigenous energy resources and uses; forecasts, demand, exports, imports of energy supplies; environmental considerations of energy supplies; power production facilities; energy industries; commercial applications of energy; research and development activities of energy; and international activities.

  4. Robust Multiscale Modelling Of Two-Phase Steels On Heterogeneous Hardware Infrastructures By Using Statistically Similar Representative Volume Element

    Directory of Open Access Journals (Sweden)

    Rauch Ł.

    2015-09-01

    Full Text Available The coupled finite element multiscale simulations (FE2 require costly numerical procedures in both macro and micro scales. Attempts to improve numerical efficiency are focused mainly on two areas of development, i.e. parallelization/distribution of numerical procedures and simplification of virtual material representation. One of the representatives of both mentioned areas is the idea of Statistically Similar Representative Volume Element (SSRVE. It aims at the reduction of the number of finite elements in micro scale as well as at parallelization of the calculations in micro scale which can be performed without barriers. The simplification of computational domain is realized by transformation of sophisticated images of material microstructure into artificially created simple objects being characterized by similar features as their original equivalents. In existing solutions for two-phase steels SSRVE is created on the basis of the analysis of shape coefficients of hard phase in real microstructure and searching for a representative simple structure with similar shape coefficients. Optimization techniques were used to solve this task. In the present paper local strains and stresses are added to the cost function in optimization. Various forms of the objective function composed of different elements were investigated and used in the optimization procedure for the creation of the final SSRVE. The results are compared as far as the efficiency of the procedure and uniqueness of the solution are considered. The best objective function composed of shape coefficients, as well as of strains and stresses, was proposed. Examples of SSRVEs determined for the investigated two-phase steel using that objective function are demonstrated in the paper. Each step of SSRVE creation is investigated from computational efficiency point of view. The proposition of implementation of the whole computational procedure on modern High Performance Computing (HPC

  5. Hardware malware

    CERN Document Server

    Krieg, Christian

    2013-01-01

    In our digital world, integrated circuits are present in nearly every moment of our daily life. Even when using the coffee machine in the morning, or driving our car to work, we interact with integrated circuits. The increasing spread of information technology in virtually all areas of life in the industrialized world offers a broad range of attack vectors. So far, mainly software-based attacks have been considered and investigated, while hardware-based attacks have attracted comparatively little interest. The design and production process of integrated circuits is mostly decentralized due to

  6. Minerals Yearbook, volume III, Area Reports—International—Latin America and Canada

    Science.gov (United States)

    ,

    2017-01-01

    The U.S. Geological Survey (USGS) Minerals Yearbook discusses the performance of the worldwide minerals and materials industries and provides background information to assist in interpreting that performance. Content of the individual Minerals Yearbook volumes follows:Volume I, Metals and Minerals, contains chapters about virtually all metallic and industrial mineral commodities important to the U.S. economy. Chapters on survey methods, summary statistics for domestic nonfuel minerals, and trends in mining and quarrying in the metals and industrial mineral industries in the United States are also included.Volume II, Area Reports: Domestic, contains a chapter on the mineral industry of each of the 50 States and Puerto Rico and the Administered Islands. This volume also has chapters on survey methods and summary statistics of domestic nonfuel minerals.Volume III, Area Reports: International, is published as four separate reports. These regional reports contain the latest available minerals data on more than 180 foreign countries and discuss the importance of minerals to the economies of these nations and the United States. Each report begins with an overview of the region’s mineral industries during the year. It continues with individual country chapters that examine the mining, refining, processing, and use of minerals in each country of the region and how each country’s mineral industry relates to U.S. industry. Most chapters include production tables and industry structure tables, information about Government policies and programs that affect the country’s mineral industry, and an outlook section.The USGS continually strives to improve the value of its publications to users. Constructive comments and suggestions by readers of the Minerals Yearbook are welcomed.

  7. Minerals Yearbook, volume III, Area Reports—International—Europe and Central Eurasia

    Science.gov (United States)

    Geological Survey, U.S.

    2017-01-01

    The U.S. Geological Survey (USGS) Minerals Yearbook discusses the performance of the worldwide minerals and materials industries and provides background information to assist in interpreting that performance. Content of the individual Minerals Yearbook volumes follows:Volume I, Metals and Minerals, contains chapters about virtually all metallic and industrial mineral commodities important to the U.S. economy. Chapters on survey methods, summary statistics for domestic nonfuel minerals, and trends in mining and quarrying in the metals and industrial mineral industries in the United States are also included.Volume II, Area Reports: Domestic, contains a chapter on the mineral industry of each of the 50 States and Puerto Rico and the Administered Islands. This volume also has chapters on survey methods and summary statistics of domestic nonfuel minerals.Volume III, Area Reports: International, is published as four separate reports. These regional reports contain the latest available minerals data on more than 180 foreign countries and discuss the importance of minerals to the economies of these nations and the United States. Each report begins with an overview of the region’s mineral industries during the year. It continues with individual country chapters that examine the mining, refining, processing, and use of minerals in each country of the region and how each country’s mineral industry relates to U.S. industry. Most chapters include production tables and industry structure tables, information about Government policies and programs that affect the country’s mineral industry, and an outlook section.The USGS continually strives to improve the value of its publications to users. Constructive comments and suggestions by readers of the Minerals Yearbook are welcomed.

  8. Minerals Yearbook, volume III, Area Reports—International—Africa and the Middle East

    Science.gov (United States)

    ,

    2017-01-01

    The U.S. Geological Survey (USGS) Minerals Yearbook discusses the performance of the worldwide minerals and materials industries and provides background information to assist in interpreting that performance. Content of the individual Minerals Yearbook volumes follows:Volume I, Metals and Minerals, contains chapters about virtually all metallic and industrial mineral commodities important to the U.S. economy. Chapters on survey methods, summary statistics for domestic nonfuel minerals, and trends in mining and quarrying in the metals and industrial mineral industries in the United States are also included.Volume II, Area Reports: Domestic, contains a chapter on the mineral industry of each of the 50 States and Puerto Rico and the Administered Islands. This volume also has chapters on survey methods and summary statistics of domestic nonfuel minerals.Volume III, Area Reports: International, is published as four separate reports. These regional reports contain the latest available minerals data on more than 180 foreign countries and discuss the importance of minerals to the economies of these nations and the United States. Each report begins with an overview of the region’s mineral industries during the year. It continues with individual country chapters that examine the mining, refining, processing, and use of minerals in each country of the region and how each country’s mineral industry relates to U.S. industry. Most chapters include production tables and industry structure tables, information about Government policies and programs that affect the country’s mineral industry, and an outlook section.The USGS continually strives to improve the value of its publications to users. Constructive comments and suggestions by readers of the Minerals Yearbook are welcomed.

  9. Proceedings of the symposium to review Volume III of the Annual Report to Congress

    Energy Technology Data Exchange (ETDEWEB)

    Alt, F.; Norland, D.

    1979-01-01

    This report is a transcript of the proceedings of a two-day Symposium, held in the Fall of 1979 at the University of Maryland in order to independently review the 1978 Energy Information Administration (EIA) Annual Report to Congress (ARC), Volume III. Participants included energy forecasting experts from the academic community and the private sector; other Federal, State, and local government energy experts; and Office of Applied Analysis, EIA, staff members. The Symposium and its transcript are a critique of the underlying 1978 ARC assumptions, methodologies, and energy system projections. Discussions cover the short-, mid-, and long-term periods, national and international forecasts, source and consuming sectors and projected economic impacts. 27 figures, 22 tables.

  10. Planning manual for energy resource development on Indian lands. Volume III. Manpower and training

    Energy Technology Data Exchange (ETDEWEB)

    1978-03-01

    This volume addresses ways to bridge the gap between existing tribal skill levels and the skill levels required for higher-paying jobs in energy resource development projects. It addresses opportunities for technical, skilled, and semiskilled employment as well as professional positions, because it is important to have tribal participation at all levels of an operation. Section II, ''Energy-Related Employment Opportunities,'' covers three areas: (1) identification of energy-resource occupations; (2) description of these occupations; and (3) identification of skill requirements by type of occupation. Section III, ''Description of Training Programs,'' also covers three areas: (a) concept of a training-program model; (b) description of various training methods; and (c) an assessment of the cost of training, utilizing different programs. Section IV concentrates on development of a training program for target occupations, skills, and populations. Again this section covers three areas: (i) overview of the development of a skills training program; (ii) identification of target occupations, skills, and populations; and (iii) energy careers for younger tribal members.

  11. Hardware Accelerated Simulated Radiography

    Energy Technology Data Exchange (ETDEWEB)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-04-12

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists.

  12. Advanced Platform for Development and Evaluation of Grid Interconnection Systems Using Hardware-in-the-Loop: Part III -- Grid Interconnection System Evaluator: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Lundstrom, B.; Shirazi, M.; Coddington, M.; Kroposki, B.

    2013-01-01

    This paper, presented at the IEEE Green Technologies Conference 2013, describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1 (TM). The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through the use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of ICS grid interconnection conformance.

  13. Advanced Platform for Development and Evaluation of Grid Interconnection Systems Using Hardware-in-the-Loop: Part III - Grid Interconnection System Evaluator

    Energy Technology Data Exchange (ETDEWEB)

    Lundstrom, B.; Shirazi, M.; Coddington, M.; Kroposki, B.

    2013-01-01

    This paper describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1. The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through the use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of ICS grid interconnection conformance.

  14. State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 2: Hardware design verification

    Science.gov (United States)

    Carlan, A. J.; Breuer, M. A.

    1982-10-01

    The complexity of digital circuits requires that more emphasis be placed on design specifications and verification. Specification of design requirements currently advocated is done with formal hardware descriptive languages (HDLs) to describe hardware function. Industry's current use of HDLs is primarily for simulation. Verifying a design is a less mature discipline. Three approaches are considered: simulation, symbolic simulation amd formal proofs. While symbolic simulation shows promise, much research and development is required.

  15. Study for Teaching Behavioral Sciences in Schools of Medicine, Volume III: Behavioral Science Perspectives in Medical Education.

    Science.gov (United States)

    American Sociological Association, Washington, DC. Medical Sociology Council.

    Volume III of a study of teaching behavioral sciences in medical school presents perspectives on medical behavioral science from the viewpoints of the several behavioral disciplines (anthropology, psychology, sociology, political science, economics, behavioral biology and medical education). In addition, there is a discussion of translating…

  16. Financial constraints in capacity planning: a national utility regulatory model (NUREG). Volume I of III: methodology. Final report

    Energy Technology Data Exchange (ETDEWEB)

    1981-10-29

    This report develops and demonstrates the methodology for the National Utility Regulatory (NUREG) Model developed under contract number DEAC-01-79EI-10579. It is accompanied by two supporting volumes. Volume II is a user's guide for operation of the NUREG software. This includes description of the flow of software and data, as well as the formats of all user data files. Finally, Volume III is a software description guide. It briefly describes, and gives a listing of, each program used in NUREG.

  17. Underground Test Area Subproject Phase I Data Analysis Task. Volume III - Groundwater Recharge and Discharge Data Documentation Package

    Energy Technology Data Exchange (ETDEWEB)

    None

    1996-10-01

    Volume III of the documentation for the Phase I Data Analysis Task performed in support of the current Regional Flow Model, Transport Model, and Risk Assessment for the Nevada Test Site Underground Test Area Subproject contains the data covering groundwater recharge and discharge. Because of the size and complexity of the model area, a considerable quantity of data was collected and analyzed in support of the modeling efforts. The data analysis task was consequently broken into eight subtasks, and descriptions of each subtask's activities are contained in one of the eight volumes that comprise the Phase I Data Analysis Documentation.

  18. Technical and economic assessment of fluidized bed augmented compressed air energy storage system. Volume III. Preconceptual design

    Energy Technology Data Exchange (ETDEWEB)

    Giramonti, A.J.; Lessard, R.D.; Merrick, D.; Hobson, M.J.

    1981-09-01

    A technical and economic assessment of fluidized bed combustion augmented compressed air energy storage systems is presented. The results of this assessment effort are presented in three volumes. Volume III - Preconceptual Design contains the system analysis which led to the identification of a preferred component configuration for a fluidized bed combustion augmented compressed air energy storage system, the results of the effort which transformed the preferred configuration into preconceptual power plant design, and an introductory evaluation of the performance of the power plant system during part-load operation and while load following.

  19. Inside Out. Writings from the Prison Literacy Project. Volumes I-II.

    Science.gov (United States)

    Prison Literacy Project, Philadelphia, PA.

    These two volumes contain writings designed for the new reader who is in prison. Written by both inmates and external volunteers, the material in these volumes includes poems, stories, and short essays that deal with subjects of interest to prison inmates. To help the new reader, easier-to-read pieces are presented first. Titles in volume I are as…

  20. Hardware Implementation of AES

    Directory of Open Access Journals (Sweden)

    Aakrati Chaturvedi

    2014-01-01

    Full Text Available The Advanced Encryption Standard algorithm can be efficiently programmed in software and implemented in hardware. Field Programmable Gate Array (FPGA devices are considered as efficient and cost effective solution for hardware. This research is in context to efficient hardware implementation of AES algorithm with language platform as VHDL (Very High Speed Integrated Circuit Hardware Description language. This research is in context to efficient hardware implementation of AES algorithm with 128-192-256 key all in one module with language platform as VHDL (Very High Speed Integrated Circuit Hardware Description language. The software part has been created, processed and simulated through Xilinx ISE 9.2. A compact design approach has been chosen to implement the algorithm with minimal hardware. As for hardware, Spartan 3AN family device (XC3S700A device is used

  1. Introduction to Hardware Security

    Directory of Open Access Journals (Sweden)

    Yier Jin

    2015-10-01

    Full Text Available Hardware security has become a hot topic recently with more and more researchers from related research domains joining this area. However, the understanding of hardware security is often mixed with cybersecurity and cryptography, especially cryptographic hardware. For the same reason, the research scope of hardware security has never been clearly defined. To help researchers who have recently joined in this area better understand the challenges and tasks within the hardware security domain and to help both academia and industry investigate countermeasures and solutions to solve hardware security problems, we will introduce the key concepts of hardware security as well as its relations to related research topics in this survey paper. Emerging hardware security topics will also be clearly depicted through which the future trend will be elaborated, making this survey paper a good reference for the continuing research efforts in this area.

  2. How To Set Up Your Own Small Business. Volumes I-II and Overhead Transparencies.

    Science.gov (United States)

    Fallek, Max

    This two-volume textbook and collection of overhead transparency masters is intended for use in a course in setting up a small business. The following topics are covered in the first volume: getting off to a good start, doing market research, forecasting sales, financing a small business, understanding the different legal needs of different types…

  3. AIR QUALITY CRITERIA FOR PARTICULATE MATTER, VOLUMES I-III, (EXTERNAL REVIEW DRAFT, 1995)

    Science.gov (United States)

    There is no abstract available for these documents. If further information is requested, please refer to the bibliographic citation and contact the Technical Information Staff at the number listed above.Air Quality Criteria for Particulate Matter, Volume I, Extern...

  4. Field Surveys, IOC Valleys. Volume III, Part I. Cultural Resources Survey, Dry Lake Valley, Nevada.

    Science.gov (United States)

    1981-08-01

    Artemisia nova) but also include cliffrose (Cowania mexicana ) and broom snakeweed (Gutierrezia sarothreae) as dominant species. Other species include... CULTURA Ale ~~REOUC SURVEYa AREASczCAvE L CU 11U CUUI 3-2 E-TR-48-III-I 69 was used because it is considered intensive by the Bureau of Land Management and

  5. ICPP calcined solids storage facility closure study. Volume III: Engineering design files

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1998-02-01

    The following information was calculated to support cost estimates and radiation exposure calculations for closure activities at the Calcined Solids Storage Facility (CSSF). Within the estimate, volumes were calculated to determine the required amount of grout to be used during closure activities. The remaining calcine on the bin walls, supports, piping, and floor was also calculated to approximate the remaining residual calcine volumes at different stages of the removal process. The estimates for remaining calcine and vault void volume are higher than what would actually be experienced in the field, but are necessary for bounding purposes. The residual calcine in the bins may be higher than was is experienced in the field as it was assumed that the entire bin volume is full of calcine before removal activities commence. The vault void volumes are higher as the vault roof beam volumes were neglected. The estimations that follow should be considered rough order of magnitude, due to the time constraints as dictated by the project`s scope of work. Should more accurate numbers be required, a new analysis would be necessary.

  6. Sodium-NaK engineering handbook. Volume III. Sodium systems, safety, handling, and instrumentation. [LMFBR

    Energy Technology Data Exchange (ETDEWEB)

    Foust, O J [ed.

    1978-01-01

    The handbook is intended for use by present and future designers in the Liquid Metals Fast Breeder Reactor (LMFBR) Program and by the engineering and scientific community performing other type investigation and exprimentation requiring high-temperature sodium and NaK technology. The arrangement of subject matter progresses from a technological discussion of sodium and sodium--potassium alloy (NaK) to discussions of varius categories and uses of hardware in sodium and NaK systems. Emphasis is placed on sodium and NaK as heat-transport media. Sufficient detail is included for basic understanding of sodium and NaK technology and of technical aspects of sodium and NaK components and instrument systems. Information presented is considered adequate for use in feasibility studies and conceptual design, sizing components and systems, developing preliminary component and system descriptions, identifying technological limitations and problem areas, and defining basic constraints and parameters.

  7. Compact high order finite volume method on unstructured grids III: Variational reconstruction

    Science.gov (United States)

    Wang, Qian; Ren, Yu-Xin; Pan, Jianhua; Li, Wanai

    2017-05-01

    This paper presents a variational reconstruction for the high order finite volume method in solving the two-dimensional Navier-Stokes equations on arbitrary unstructured grids. In the variational reconstruction, an interfacial jump integration is defined to measure the jumps of the reconstruction polynomial and its spatial derivatives on each cell interface. The system of linear equations to determine the reconstruction polynomials is derived by minimizing the total interfacial jump integration in the computational domain using the variational method. On each control volume, the derived equations are implicit relations between the coefficients of the reconstruction polynomials defined on a compact stencil involving only the current cell and its direct face-neighbors. The reconstruction and time integration coupled iteration method proposed in our previous paper is used to achieve high computational efficiency. A problem-independent shock detector and the WBAP limiter are used to suppress non-physical oscillations in the simulation of flow with discontinuities. The advantages of the finite volume method using the variational reconstruction over the compact least-squares finite volume method proposed in our previous papers are higher accuracy, higher computational efficiency, more flexible boundary treatment and non-singularity of the reconstruction matrix. A number of numerical test cases are solved to verify the accuracy, efficiency and shock-capturing capability of the finite volume method using the variational reconstruction.

  8. Proceedings of the sixth international conference on fluidized bed combustion. Volume III. Technical sessions

    Energy Technology Data Exchange (ETDEWEB)

    None

    1980-08-01

    The Sixth International Conference on Fluidized Bed Combustion was held April 9-11, 1980, at the Atlanta Hilton, Atlanta, Georgia. It was sponsored by the US Department of Energy, the Electric Power Research Institute, the US Environmental Protection Agency, and the Tennessee Valley Authority. Forty-five papers from Vol. III of the proceedings have been entered individually into EDB and ERA. Two papers had been entered previously from other sources. (LTN)

  9. Recent regulatory experience of low-Btu coal gasification. Volume III. Supporting case studies

    Energy Technology Data Exchange (ETDEWEB)

    Ackerman, E.; Hart, D.; Lethi, M.; Park, W.; Rifkin, S.

    1980-02-01

    The MITRE Corporation conducted a five-month study for the Office of Resource Applications in the Department of Energy on the regulatory requirements of low-Btu coal gasification. During this study, MITRE interviewed representatives of five current low-Btu coal gasification projects and regulatory agencies in five states. From these interviews, MITRE has sought the experience of current low-Btu coal gasification users in order to recommend actions to improve the regulatory process. This report is the third of three volumes. It contains the results of interviews conducted for each of the case studies. Volume 1 of the report contains the analysis of the case studies and recommendations to potential industrial users of low-Btu coal gasification. Volume 2 contains recommendations to regulatory agencies.

  10. Alterations of thoraco-abdominal volumes and asynchronies in patients with spinal muscle atrophy type III.

    Science.gov (United States)

    LoMauro, Antonella; Romei, Marianna; Priori, Rita; Laviola, Marianna; D'Angelo, Maria Grazia; Aliverti, Andrea

    2014-06-15

    Spinal muscular atrophy (SMA) is characterized by degeneration of motor neurons resulting in muscle weakness. For the mild type III form, a sub-classification into type IIIA and IIIB, based on age of motor impairment, was recently proposed. To investigate if SMA IIIA (more severe) and IIIB differ also in terms of respiratory function, thoracoabdominal kinematics was measured during quiet breathing, inspiration preceding cough and inspiratory capacity on 5 type IIIA and 9 type IIIB patients. Four patients with SMA II (more severe than types III) and 19 healthy controls were also studied. Rib cage motion was similar in SMA IIIB and controls. Conversely, in SMA IIIA and SMA II it was significantly reduced and sometime paradoxical during quiet breathing in supine position. Our results suggest that in SMA IIIA intercostal muscles are weakened and the diaphragm is preserved similarly to SMA II, while in SMA IIIB the action of all inspiratory muscles is maintained. Sub-classification of type III seems feasible also for respiratory function.

  11. Recensione a "Collodi. Edizione Nazionale delle Opere di Carlo Lorenzini. Volume III"

    Directory of Open Access Journals (Sweden)

    Pina Paone

    2013-06-01

    Full Text Available Si presenta il terzo volume della collana Collodi, Edizione Nazionale delle Opere di Carlo Lorenzini, Giunti, Firenze, 2012, con Prefazione di Mario Vargas Llosa e Introduzione di Daniela Marcheschi. Il volume contiene il famosissimo Le Avventure di Pinocchio, sintesi del percorso artistico dello scrittore toscano ed espressione più compiuta della sua abilità e consapevolezza narrativa. La recensione ripercorrerà i tratti dell’opera, inserendola nel generale e più ampio contesto dell’attività letteraria di Collodi.

  12. Secretarial Science. Curriculum Guides for Two-Year Postsecondary Programs. Volume III.

    Science.gov (United States)

    North Carolina State Dept. of Community Colleges, Raleigh.

    The third of three volumes in a postsecondary secretarial science curriculum, this manual contains course syllabi for thirteen secretarial science technical courses. Course titles include Shorthand 1-3; Shorthand Dictation and Transcription, 1-3; Terminology and Vocabulary: Business, Legal, Medical; Typewriting, 1-5; and Word Processing. Each…

  13. Analysis and forecast of electrical distribution system materials. Final report. Volume III. Appendix

    Energy Technology Data Exchange (ETDEWEB)

    Love, C G

    1976-08-23

    These appendixes are referenced in Volume II of this report. They contain the detailed electrical distribution equipment requirements and input material requirements forecasts. Forecasts are given for three electric energy usage scenarios. Also included are data on worldwide reserves and demand for 30 raw materials required for the manufacture of electrical distribution equipment.

  14. Open Hardware Business Models

    Directory of Open Access Journals (Sweden)

    Edy Ferreira

    2008-04-01

    Full Text Available In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

  15. Does upper premolar extraction affect the changes of pharyngeal airway volume after bimaxillary surgery in skeletal class III patients?

    Science.gov (United States)

    Kim, Min-Ah; Park, Yang-Ho

    2014-01-01

    The purpose of this study was to assess the pharyngeal airway volume change after bimaxillary surgery in patients with skeletal Class III malocclusion and evaluate the difference in postoperative pharyngeal airway space between upper premolar extraction cases and nonextraction cases. Cone-beam computed tomographic scans were obtained for 23 patients (13 in extraction group and 10 in nonextraction group) who were diagnosed with mandibular prognathism before surgery (T0) and then 2 months (T2) and 6 months after surgery (T3). Using InVivoDental 3-dimensional imaging software, volumetric changes in the pharyngeal airway space were assessed at T0, T2, and T3. The Wilcoxon signed-rank test was used to determine whether there were significant changes in pharyngeal airway volume between time points. The Mann-Whitney U test was used to determine whether there were significant differences in volumetric changes between the extraction and nonextraction groups. Volumes in all subsections of the pharyngeal airway were decreased (P bimaxillary surgery. Copyright © 2014 American Association of Oral and Maxillofacial Surgeons. Published by Elsevier Inc. All rights reserved.

  16. Hardware-Accelerated Simulated Radiography

    Energy Technology Data Exchange (ETDEWEB)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-08-04

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester.

  17. Economic evaluation of the annual cycle energy system (ACES). Final report. Volume III, appendices

    Energy Technology Data Exchange (ETDEWEB)

    1980-06-01

    This volume consists of seven appendices related to ACES, the first three of which are concerned with computer programs. The appendices are entitled: (A) ACESIM: Residential Program Listing; (B) Typical Inputs and Outputs of ACESIM; (C) CACESS: Commercial Building Program Listing; (D) Typical Weather-Year Selection Requirements; (E) Building Characteristics; (F) List of Major Variables Used in the Computer Programs; and (G) Bibliography. 79 references.

  18. Freud on Holiday. Volume III. The Forgetting of a Foreign Name

    OpenAIRE

    Kivland, Sharon

    2011-01-01

    The third volume in the series Freud on Holiday describes a number of holiday possibilities, the problem of deciding where to go and when, the matters of cost and convenience, of appropriate companions and correct context. There are descriptions of train itineraries, of hotel rooms and restaurant menus, but the name of one restaurant resists recall for most of the book. There is a surprising connection with hysteria and another name is forgotten en route, accompanied by an embarrassing error ...

  19. Solar Central Receiver Hybrid Power Systems sodium-cooled receiver concept. Final report. Volume III. Appendices

    Energy Technology Data Exchange (ETDEWEB)

    None

    1980-01-01

    The overall, long term objective of the Solar Central Receiver Hybrid Power System is to identify, characterize, and ultimately demonstrate the viability and cost effectiveness of solar/fossil, steam Rankine cycle, hybrid power systems that: (1) consist of a combined solar central receiver energy source and a nonsolar energy source at a single, common site, (2) may operate in the base, intermediate, and peaking capacity modes, (3) produce the rated output independent of variations in solar insolation, (4) provide a significant savings (50% or more) in fuel consumpton, and (5) produce power at the minimum possible cost in mills/kWh. It is essential that these hybrid concepts be technically feasible and economically competitive with other systems in the near to mid-term time period (1985-1990) on a commercial scale. The program objective for Phase I is to identify and conceptually characterize solar/fossil steam Rankine cycle, commercial-scale, power plant systems that are economically viable and technically feasible. This volume contains appendices to the conceptual design and systems analysis studies gien in Volume II, Books 1 and 2. (WHK)

  20. Southwest Project: resource/institutional requirements analysis. Volume III. Systems integration studies

    Energy Technology Data Exchange (ETDEWEB)

    Ormsby, L. S.; Sawyer, T. G.; Brown, Dr., M. L.; Daviet, II, L. L; Weber, E. R.; Brown, J. E.; Arlidge, J. W.; Novak, H. R.; Sanesi, Norman; Klaiman, H. C.; Spangenberg, Jr., D. T.; Groves, D. J.; Maddox, J. D.; Hayslip, R. M.; Ijams, G.; Lacy, R. G.; Montgomery, J.; Carito, J. A.; Ballance, J. W.; Bluemle, C. F.; Smith, D. N.; Wehrey, M. C.; Ladd, K. L.; Evans, Dr., S. K.; Guild, D. H.; Brodfeld, B.; Cleveland, J. A.; Hicks, K. L.; Noga, M. W.; Ross, A. M.

    1979-12-01

    The purpose of this project is to provide information to DOE which can be used to establish its plans for accelerated commercialization and market penetration of solar electric generating plants in the southwestern region of the United States. The area of interest includes Arizona, California, Colorado, Nevada, New Mexico, Utah, and sections of Oklahoma and Texas. The system integration study establishes the investment that utilities could afford to make in solar thermal, photovoltaic, and wind energy systems, and to assess the sensitivity of the break-even cost to critical variables including fuel escalation rates, fixed charge rates, load growth rates, cloud cover, number of sites, load shape, and energy storage. This information will be used as input to Volume IV, Institutional Studies, one objective of which will be to determine the incentives required to close the gap between the break-even investment for the utilities of the Southwest and the estimated cost of solar generation.

  1. Solar Pilot Plant, Phase I. Preliminary design report. Volume III. Collector subsystem. CDRL item 2

    Energy Technology Data Exchange (ETDEWEB)

    None

    1977-05-01

    The Honeywell collector subsystem features a low-profile, multifaceted heliostat designed to provide high reflectivity and accurate angular and spatial positioning of the redirected solar energy under all conditions of wind load and mirror attitude within the design operational envelope. The heliostats are arranged in a circular field around a cavity receiver on a tower halfway south of the field center. A calibration array mounted on the receiver tower provides capability to measure individual heliostat beam location and energy periodically. This information and weather data from the collector field are transmitted to a computerized control subsystem that addresses the individual heliostat to correct pointing errors and determine when the mirrors need cleaning. This volume contains a detailed subsystem design description, a presentation of the design process, and the results of the SRE heliostat test program.

  2. Energy use in the marine transportation industry: Task II. Regulations and Tariffs. Final report, Volume III

    Energy Technology Data Exchange (ETDEWEB)

    None

    1977-12-01

    The evaluation of the energy impacts of regulations and tariffs is structured around three sequential steps: identification of agencies and organizations that impact the commercial marine transportation industry; identification of existing or proposed regulations that were perceived to have a significant energy impact; and quantification of the energy impacts. Following the introductory chapter, Chapter II describes the regulatory structure of the commercial marine transportation industry and includes a description of the role of each organization and the legislative basis for their jurisdiction and an identification of major areas of regulation and those areas that have an energy impact. Chapters III through IX each address one of the 7 existing or proposed regulatory or legislative actions that have an energy impact. Energy impacts of the state of Washington's tanker regulations, of tanker segregated ballast requirements, of inland waterway user charges, of cargo pooling and service rationalization, of the availability of intermodal container transportation services, of capacity limitations at lock and dam 26 on the Mississippi River and the energy implications of the transportation alternatives available for the West Coast crude oil supplies are discussed. (MCW)

  3. Hardware Accelerated Power Estimation

    CERN Document Server

    Coburn, Joel; Raghunathan, Anand

    2011-01-01

    In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc.) can be implemented as hardware circuits. Therefore, we can enhance any given design with "power estimation hardware", map it to a prototyping platform, and exercise it with any given test stimuli to obtain power consumption estimates. Our empirical studies with industrial designs reveal that power emulation can achieve significant speedups (10X to 500X) over state-of-the-art commercial register-transfer level (RTL) power estimation tools.

  4. OTEC modular experiment cold water pipe concept evaluation. Volume III. Appendices

    Energy Technology Data Exchange (ETDEWEB)

    1979-04-01

    The Cold Water Pipe System Design Study was undertaken to evaluate the diverse CWP concepts, recommend the most viable alternatives for a 1984 deployment of the 10 to 40 MWe MEP, and carry out preliminary designs of three concepts. The concept evaluation phase reported involved a systems analysis of design alternatives in the broad categories of rigid walled (with hinges), compliant walled, stockade and bottom mounted buoyant. Quantitative evaluations were made of concept performance, availability, deployment schedule, technical feasibility and cost. CWP concepts were analyzed to determine if they met or could be made to meet established system requirements and could be deployed by 1984. Fabrication, construction and installation plans were developed for successful concepts, and costs were determined in a WBS format. Evaluations were performed on the basis of technical and cost risk. This volume includes the following appendices: (A) materials and associated design criteria; (B) summary of results of dynamic flow and transportation analysis; (C) CWP sizing analysis; (D) CWP thermal performance; and (E) investigation of the APL/ABAM CWP design. (WHK)

  5. Hardware protection through obfuscation

    CERN Document Server

    Bhunia, Swarup; Tehranipoor, Mark

    2017-01-01

    This book introduces readers to various threats faced during design and fabrication by today’s integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs or “IC Overproduction,” insertion of malicious circuits, referred as “Hardware Trojans”, which cause in-field chip/system malfunction, and reverse engineering and piracy of hardware intellectual property (IP). The authors provide a timely discussion of these threats, along with techniques for IC protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for adversaries and untrusted parties with any reasonable amount of resources. This exhaustive study includes a review of the hardware obfuscation methods developed at each level of abstraction (RTL, gate, and layout) for conventional IC manufacturing, new forms of obfuscation for emerging integration strategies (split manufacturing, 2.5D ICs, and 3D ICs), and on-chip infrastructure needed for secure exchange o...

  6. Open Hardware at CERN

    CERN Multimedia

    CERN Knowledge Transfer Group

    2015-01-01

    CERN is actively making its knowledge and technology available for the benefit of society and does so through a variety of different mechanisms. Open hardware has in recent years established itself as a very effective way for CERN to make electronics designs and in particular printed circuit board layouts, accessible to anyone, while also facilitating collaboration and design re-use. It is creating an impact on many levels, from companies producing and selling products based on hardware designed at CERN, to new projects being released under the CERN Open Hardware Licence. Today the open hardware community includes large research institutes, universities, individual enthusiasts and companies. Many of the companies are actively involved in the entire process from design to production, delivering services and consultancy and even making their own products available under open licences.

  7. NOVEL CONCEPTS FOR THE COMPRESSION OF LARGE VOLUMES OF CARBON DIOXIDE-PHASE III

    Energy Technology Data Exchange (ETDEWEB)

    Moore, J. Jeffrey; Allison, Timothy; Evans, Neal; Moreland, Brian; Hernandez, Augusto; Day, Meera; Ridens, Brandon

    2014-06-30

    successfully demonstrated good performance and mechanical behavior. In Phase III, a pilot compression plant consisting of a multi-stage centrifugal compressor with cooled diaphragm technology has been designed, constructed, and tested. Comparative testing of adiabatic and cooled tests at equivalent inlet conditions shows that the cooled diaphragms reduce power consumption by 3-8% when the compressor is operated as a back-to-back unit and by up to 9% when operated as a straight-though compressor with no intercooler. The power savings, heat exchanger effectiveness, and temperature drops for the cooled diaphragm were all slightly higher than predicted values but showed the same trends.

  8. Genetic correlations between brain volumes and the WAIS-III dimensions of verbal comprehension, working memory, perceptual organization, and processing speed

    DEFF Research Database (Denmark)

    Posthuma, Daniëlle; Baare, Wim F.C.; Hulshoff Pol, Hilleke E.;

    2003-01-01

    to cerebellar volume. Verbal Comprehension was not related to any of the three brain volumes. It is concluded that brain volumes are genetically related to intelligence which suggests that genes that influence brain volume may also be important for intelligence. It is also noted however, that the direction......We recently showed that the correlation of gray and white matter volume with full scale IQ and the Working Memory dimension are completely mediated by common genetic factors (Posthuma et al., 2002). Here we examine whether the other WAIS III dimensions (Verbal Comprehension, Perceptual Organization...... to Working Memory capacity (r = 0.27). This phenotypic correlation is completely due to a common underlying genetic factor. Processing Speed was genetically related to white matter volume (r(g) = 0.39). Perceptual Organization was both genetically (r(g) = 0.39) and environmentally (r(e) = -0.71) related...

  9. Novel concepts for the compression of large volumes of carbon dioxide-phase III

    Energy Technology Data Exchange (ETDEWEB)

    Moore, J. Jeffrey [Southwest Research Inst., San Antonio, TX (United States); Allison, Timothy C. [Southwest Research Inst., San Antonio, TX (United States); Evans, Neal D. [Southwest Research Inst., San Antonio, TX (United States); Moreland, Brian [Southwest Research Inst., San Antonio, TX (United States); Hernandez, Augusto J. [Southwest Research Inst., San Antonio, TX (United States); Day, Meera [Southwest Research Inst., San Antonio, TX (United States); Ridens, Brandon L. [Southwest Research Inst., San Antonio, TX (United States)

    2014-06-30

    and tested in a closed loop compressor facility using CO2 . Both test programs successfully demonstrated good performance and mechanical behavior. In Phase III, a pilot compression plant consisting of a multi-stage centrifugal compressor with cooled diaphragm technology has been designed, constructed, and tested. Comparative testing of adiabatic and cooled tests at equivalent inlet conditions shows that the cooled diaphragms reduce power consumption by 3-8% when the compressor is operated as a back-to-back unit and by up to 9% when operated as a straight-though compressor with no intercooler. The power savings, heat exchanger effectiveness, and temperature drops for the cooled diaphragm were all slightly higher than predicted values but showed the same trends.

  10. Hardware Objects for Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Thalinger, Christian; Korsholm, Stephan

    2008-01-01

    Java, as a safe and platform independent language, avoids access to low-level I/O devices or direct memory access. In standard Java, low-level I/O it not a concern; it is handled by the operating system. However, in the embedded domain resources are scarce and a Java virtual machine (JVM) without...... an underlying middleware is an attractive architecture. When running the JVM on bare metal, we need access to I/O devices from Java; therefore we investigate a safe and efficient mechanism to represent I/O devices as first class Java objects, where device registers are represented by object fields. Access...... to those registers is safe as Java’s type system regulates it. The access is also fast as it is directly performed by the bytecodes getfield and putfield. Hardware objects thus provide an object-oriented abstraction of low-level hardware devices. As a proof of concept, we have implemented hardware objects...

  11. Hardware Objects for Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Thalinger, Christian; Korsholm, Stephan

    2008-01-01

    Java, as a safe and platform independent language, avoids access to low-level I/O devices or direct memory access. In standard Java, low-level I/O it not a concern; it is handled by the operating system. However, in the embedded domain resources are scarce and a Java virtual machine (JVM) without...... an underlying middleware is an attractive architecture. When running the JVM on bare metal, we need access to I/O devices from Java; therefore we investigate a safe and efficient mechanism to represent I/O devices as first class Java objects, where device registers are represented by object fields. Access...... to those registers is safe as Java’s type system regulates it. The access is also fast as it is directly performed by the bytecodes getfield and putfield. Hardware objects thus provide an object-oriented abstraction of low-level hardware devices. As a proof of concept, we have implemented hardware objects...

  12. Computer hardware fault administration

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  13. Hardware bitstream sequence recognizer

    OpenAIRE

    Karpin, Oleksandr; Sokil, Volodymyr

    2009-01-01

    This paper describes how to implement in hardware a bistream sequence recognizer using the PSoC Pseudo Random Sequence Generator (PRS) User Module. The PRS can be used in digital communication systems with the serial data interface for automatic preamble detection and extraction, control words selection, etc.

  14. Removal of broken hardware.

    Science.gov (United States)

    Hak, David J; McElvany, Matthew

    2008-02-01

    Despite advances in metallurgy, fatigue failure of hardware is common when a fracture fails to heal. Revision procedures can be difficult, usually requiring removal of intact or broken hardware. Several different methods may need to be attempted to successfully remove intact or broken hardware. Broken intramedullary nail cross-locking screws may be advanced out by impacting with a Steinmann pin. Broken open-section (Küntscher type) intramedullary nails may be removed using a hook. Closed-section cannulated intramedullary nails require additional techniques, such as the use of guidewires or commercially available extraction tools. Removal of broken solid nails requires use of a commercial ratchet grip extractor or a bone window to directly impact the broken segment. Screw extractors, trephines, and extraction bolts are useful for removing stripped or broken screws. Cold-welded screws and plates can complicate removal of locked implants and require the use of carbide drills or high-speed metal cutting tools. Hardware removal can be a time-consuming process, and no single technique is uniformly successful.

  15. The history of NATO TNF policy: The role of studies, analysis and exercises conference proceedings. Volume 3: Papers by Gen. Robert C. Richardson III (Ret.)

    Energy Technology Data Exchange (ETDEWEB)

    Rinne, R.L. [ed.

    1994-02-01

    This conference was organized to study and analyze the role of simulation, analysis, modeling, and exercises in the history of NATO policy. The premise was not that the results of past studies will apply to future policy, but rather that understanding what influenced the decision process-and how-would be of value. The structure of the conference was built around discussion panels. The panels were augmented by a series of papers and presentations focusing on particular TNF events, issues, studies, or exercises. The conference proceedings consist of three volumes. Volume 1 contains the conference introduction, agenda, biographical sketches of principal participants, and analytical summary of the presentations and discussion panels. Volume 2 contains a short introduction and the papers and presentations from the conference. This volume contains selected papers by Brig. Gen. Robert C. Richardson III (Ret.).

  16. Current and future industrial energy service characterizations. Volume III. Energy data on 15 selected states' manufacturing subsector

    Energy Technology Data Exchange (ETDEWEB)

    Krawiec, F.; Thomas, T.; Jackson, F.; Limaye, D.R.; Isser, S.; Karnofsky, K.; Davis, T.D.

    1980-11-01

    An examination is made of the current and future energy demands, and uses, and cost to characterize typical applications and resulting services in the US and industrial sectors of 15 selected states. Volume III presents tables containing data on selected states' manufacturing subsector energy consumption, functional uses, and cost in 1974 and 1976. Alabama, California, Illinois, Indiana, Louisiana, Michigan, Missouri, New Jersey, New York, Ohio, Oregon, Pennsylvania, Texas, West Virginia, and Wisconsin were chosen as having the greatest potential for replacing conventional fuel with solar energy. Basic data on the quantities, cost, and types of fuel and electric energy purchased by industr for heat and power were obtained from the 1974 and 1976 Annual Survey of Manufacturers. The specific indutrial energy servic cracteristics developed for each selected state include. 1974 and 1976 manufacturing subsector fuels and electricity consumption by 2-, 3-, and 4-digit SIC and primary fuel (quantity and relative share); 1974 and 1976 manufacturing subsector fuel consumption by 2-, 3-, and 4-digit SIC and primary fuel (quantity and relative share); 1974 and 1976 manufacturing subsector average cost of purchsed fuels and electricity per million Btu by 2-, 3-, and 4-digit SIC and primary fuel (in 1976 dollars); 1974 and 1976 manufacturing subsector fuels and electric energy intensity by 2-, 3-, and 4-digit SIC and primary fuel (in 1976 dollars); manufacturing subsector average annual growth rates of (1) fuels and electricity consumption, (2) fuels and electric energy intensity, and (3) average cost of purchased fuels and electricity (1974 to 1976). Data are compiled on purchased fuels, distillate fuel oil, residual ful oil, coal, coal, and breeze, and natural gas. (MCW)

  17. Genetic correlations between brain volumes and the WAIS-III dimensions of verbal comprehension, working memory, perceptual organization, and processing speed

    DEFF Research Database (Denmark)

    Posthuma, Daniëlle; Baare, Wim F.C.; Hulshoff Pol, Hilleke E.

    2003-01-01

    We recently showed that the correlation of gray and white matter volume with full scale IQ and the Working Memory dimension are completely mediated by common genetic factors (Posthuma et al., 2002). Here we examine whether the other WAIS III dimensions (Verbal Comprehension, Perceptual Organization...... to Working Memory capacity (r = 0.27). This phenotypic correlation is completely due to a common underlying genetic factor. Processing Speed was genetically related to white matter volume (r(g) = 0.39). Perceptual Organization was both genetically (r(g) = 0.39) and environmentally (r(e) = -0.71) related...

  18. DCSP hardware maintenance system

    Energy Technology Data Exchange (ETDEWEB)

    Pazmino, M.

    1995-11-01

    This paper discusses the necessary changes to be implemented on the hardware side of the DCSP database. DCSP is currently tracking hardware maintenance costs in six separate databases. The goal is to develop a system that combines all data and works off a single database. Some of the tasks that will be discussed in this paper include adding the capability for report generation, creating a help package and preparing a users guide, testing the executable file, and populating the new database with data taken from the old database. A brief description of the basic process used in developing the system will also be discussed. Conclusions about the future of the database and the delivery of the final product are then addressed, based on research and the desired use of the system.

  19. VHDL for hardware engineers

    Energy Technology Data Exchange (ETDEWEB)

    Park, Sehyun

    1999-02-15

    This book is comprised of nine chapters, which first describes of emergence of VHDL with design condition of hardware and VHDL, basic design for VHDL, object, data type and operator, behavioral description, structural description, package, procedure and function, combinational circuit design, order logic circuit and application of system design. Each chapter has the explanations of glossaries, sentences and the way of the design. It also has four appendixes on reserved words, predefined attributes VHDL syntax and std logic 464 package declaration.

  20. Nuclear proliferation and civilian nuclear power: report of the Nonproliferation Alternative Systems Assessment Program. Volume III. Resources and fuel cycle facilities

    Energy Technology Data Exchange (ETDEWEB)

    1979-12-01

    Volume III explores resources and fuel cycle facilities. Chapters are devoted to: estimates of US uranium resources and supply; comparison of US uranium demands with US production capability forecasts; estimates of foreign uranium resources and supply; comparison of foreign uranium demands with foreign production capability forecasts; and world supply and demand for other resources and fuel cycle services. An appendix gives uranium, fissile material, and separative work requirements for selected reactors and fuel cycles.

  1. Exploring coordinated software and hardware support for hardware resource allocation

    OpenAIRE

    Figueiredo Boneti, Carlos Santieri de

    2009-01-01

    Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the p...

  2. Industrial Fuel Gas Demonstration Plant Program. Conceptual design and evaluation of commercial plant. Volume III. Economic analyses (Deliverable Nos. 15 and 16)

    Energy Technology Data Exchange (ETDEWEB)

    None

    1978-01-01

    This report presents the results of Task I of Phase I in the form of a Conceptual Design and Evaluation of Commercial Plant report. The report is presented in four volumes as follows: I - Executive Summary, II - Commercial Plant Design, III - Economic Analyses, IV - Demonstration Plant Recommendations. Volume III presents the economic analyses for the commercial plant and the supporting data. General cost and financing factors used in the analyses are tabulated. Three financing modes are considered. The product gas cost calculation procedure is identified and appendices present computer inputs and sample computer outputs for the MLGW, Utility, and Industry Base Cases. The results of the base case cost analyses for plant fenceline gas costs are as follows: Municipal Utility, (e.g. MLGW), $3.76/MM Btu; Investor Owned Utility, (25% equity), $4.48/MM Btu; and Investor Case, (100% equity), $5.21/MM Btu. The results of 47 IFG product cost sensitivity cases involving a dozen sensitivity variables are presented. Plant half size, coal cost, plant investment, and return on equity (industrial) are the most important sensitivity variables. Volume III also presents a summary discussion of the socioeconomic impact of the plant and a discussion of possible commercial incentives for development of IFG plants.

  3. A Review of the Definition and Measurement of Poverty: Volume I, Summary Review Paper; Volume II, Annotated Bibliography. The Measure of Poverty, Technical Paper III.

    Science.gov (United States)

    Oster, Sharon; And Others

    This study reviews the existing literature on a series of issues associated with the defintion and measurement of poverty, and it consists of a summary report covering this research (Volume I), and an annotated bibliography (Volume II). Eleven specific issues were identified and reviewed in this study: (1) the historical definitions of poverty,…

  4. Orbital change following Le Fort III advancement in syndromic craniosynostosis: quantitative evaluation of orbital volume, infra-orbital rim and globe position.

    Science.gov (United States)

    Nout, Erik; van Bezooijen, Jine S; Koudstaal, Maarten J; Veenland, Jifke F; Hop, Wim C J; Wolvius, Eppo B; van der Wal, Karel G H

    2012-04-01

    Patients with syndromic craniosynostosis suffering from shallow orbits due to midface hypoplasia can be treated with a Le Fort III advancement osteotomy. This study evaluates the influence of Le Fort III advancement on orbital volume, position of the infra-orbital rim and globe. In pre- and post-operative CT-scans of 18 syndromic craniosynostosis patients, segmentation of the left and right orbit was performed and the infra-orbital rim and globe were marked. By superimposing the pre- and post-operative scans and by creating a reference coordinate system, movements of the infra-orbital rim and globe were assessed. Orbital volume increased significantly, by 27.2% for the left and 28.4% for the right orbit. Significant anterior movements of the left infra-orbital rim of 12.0mm (SD 4.2) and right infra-orbital rim of 12.8mm (SD 4.9) were demonstrated. Significant medial movements of 1.7mm (SD 2.2) of the left globe and 1.5mm (SD 1.9) of the right globe were demonstrated. There was a significant correlation between anterior infra-orbital rim movement and the increase in orbital volume. Significant orbital volume increase has been demonstrated following Le Fort III advancement. The position of the infra-orbital rim was moved forward significantly, whereas the globe position remained relatively unaffected. Copyright © 2011 European Association for Cranio-Maxillo-Facial Surgery. Published by Elsevier Ltd. All rights reserved.

  5. COMPUTER HARDWARE MARKING

    CERN Multimedia

    Groupe de protection des biens

    2000-01-01

    As part of the campaign to protect CERN property and for insurance reasons, all computer hardware belonging to the Organization must be marked with the words 'PROPRIETE CERN'.IT Division has recently introduced a new marking system that is both economical and easy to use. From now on all desktop hardware (PCs, Macintoshes, printers) issued by IT Division with a value equal to or exceeding 500 CHF will be marked using this new system.For equipment that is already installed but not yet marked, including UNIX workstations and X terminals, IT Division's Desktop Support Service offers the following services free of charge:Equipment-marking wherever the Service is called out to perform other work (please submit all work requests to the IT Helpdesk on 78888 or helpdesk@cern.ch; for unavoidable operational reasons, the Desktop Support Service will only respond to marking requests when these coincide with requests for other work such as repairs, system upgrades, etc.);Training of personnel designated by Division Leade...

  6. Open hardware for open science

    CERN Multimedia

    CERN Bulletin

    2011-01-01

    Inspired by the open source software movement, the Open Hardware Repository was created to enable hardware developers to share the results of their R&D activities. The recently published CERN Open Hardware Licence offers the legal framework to support this knowledge and technology exchange.   Two years ago, a group of electronics designers led by Javier Serrano, a CERN engineer, working in experimental physics laboratories created the Open Hardware Repository (OHR). This project was initiated in order to facilitate the exchange of hardware designs across the community in line with the ideals of “open science”. The main objectives include avoiding duplication of effort by sharing results across different teams that might be working on the same need. “For hardware developers, the advantages of open hardware are numerous. For example, it is a great learning tool for technologies some developers would not otherwise master, and it avoids unnecessary work if someone ha...

  7. Foundations of hardware IP protection

    CERN Document Server

    Torres, Lionel

    2017-01-01

    This book provides a comprehensive and up-to-date guide to the design of security-hardened, hardware intellectual property (IP). Readers will learn how IP can be threatened, as well as protected, by using means such as hardware obfuscation/camouflaging, watermarking, fingerprinting (PUF), functional locking, remote activation, hidden transmission of data, hardware Trojan detection, protection against hardware Trojan, use of secure element, ultra-lightweight cryptography, and digital rights management. This book serves as a single-source reference to design space exploration of hardware security and IP protection. · Provides readers with a comprehensive overview of hardware intellectual property (IP) security, describing threat models and presenting means of protection, from integrated circuit layout to digital rights management of IP; · Enables readers to transpose techniques fundamental to digital rights management (DRM) to the realm of hardware IP security; · Introduce designers to the concept of salutar...

  8. Contemporary American Success Stories. Famous People of Asian Ancestry. Volume III. A Mitchell Lane Multicultural Biography Series.

    Science.gov (United States)

    Marvis, Barbara J.

    As part of a five-volume series written at a reading level for grades five to six and as a tribute to the contributions Asian Americans have made to the United States, this volume presents biographical sketches of Asian Americans who can serve as role models for today's youth. The profiles in the series show the triumph of the human spirit. Volume…

  9. ATA50 TELESCOPE: HARDWARE

    Directory of Open Access Journals (Sweden)

    C. Yesilyaprak

    2014-01-01

    Full Text Available El telescopio ATA50 es un nuevo telescopio de 50cm de di ́amet ro con ́optica RC. Fue apoyado por el Proyecto de Investigaci ́on Cient ́ıfica de la Universidad de Atat ̈urk (2 010 y establecido a 2000 m.s.n.m. en Erzurum, Turqu ́ıa en 2012. Las observaciones empezaron en 2013 bajo la direcci ́on y control de el centro de aplicaciones e investi- gaci ́ones astrof ́ısicas de la Universidad de Atat ̈urk (ATA SAM. Las propiedades t ́ecnicas e infraestructuras del Telescopio ATA50 son presentadas y al igual que el trabajo en la automatizaci ́on rob ́otica del telescopio tanto en hardware como software para ser un candidato disponible par a redes de telescopios nacionales e internacionales.

  10. SOLVENT-BASED TO WATERBASED ADHESIVE-COATED SUBSTRATE RETROFIT - VOLUME III: LABEL MANUFACTURING CASE STUDY: NASHUA CORPORATION

    Science.gov (United States)

    This volume discusses Nashua Corporation's Omaha facility, a label and label stock manufacturing facility that no longer uses solvent-based adhesives. Information obtained includes issues related to the technical, economic, and environmental barriers and opportunities associated ...

  11. Soil Properties Database of Spanish Soils Volume III.- Extremadura; Base de Datos de Propiedades Edafologicas de los Suelos Espanoles Volumen III.- Extremadura

    Energy Technology Data Exchange (ETDEWEB)

    Trueba, C.; Millam, R.; Schmid, T.; Roquero, C.; Magister, M.

    1998-12-01

    The soil vulnerability determines the sensitivity of the soil after an accidental radioactive contamination due to Cs-137 and Sr-90. The Departamento de Impacto Ambiental de la Energia of CIEMAT is carrying out an assessment of the radiological vulnerability of the different Spanish soils found on the Iberian Peninsula. This requires the knowledge of the soil properties for the various types of existing soils. In order to achieve this aim, a bibliographical compilation of soil profiles has been made to characterize the different soil types and create a database of their properties. Depending on the year of publication and the type of documentary source, the information compiled from the available bibliography is very heterogeneous. Therefore, an important effort has been made to normalize and process the information prior to its incorporation to the database. This volume presents the criteria applied to normalize and process the data as well as the soil properties of the various soil types belonging to the Comunidad Autonoma de Extremadura. (Author) 50 refs.

  12. Alaska Regional Energy Resources Planning Project, Phase 2: coal, hydroelectric, and energy alternatives. Volume III. Alaska's alternative energies and regional assessment inventory update

    Energy Technology Data Exchange (ETDEWEB)

    1979-01-01

    The Alaska Regional Energy Resources Planning Project is presented in three volumes. This volume, Vol. III, considers alternative energies and the regional assessment inventory update. The introductory chapter, Chapter 12, examines the historical background, current technological status, environmental impact, applicability to Alaska, and siting considerations for a number of alternative systems. All of the systems considered use or could use renewable energy resources. The chapters that follow are entitled: Very Small Hydropower (about 12 kW or less for rural and remote villages); Low-Temperature Geothermal Space Heating; Wind; Fuel Cells; Siting Criteria and Preliminary Screening of Communities for Alternate Energy Use; Wood Residues; Waste Heat; and Regional Assessment Invntory Update. (MCW)

  13. Hardware Support for Embedded Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2012-01-01

    The general Java runtime environment is resource hungry and unfriendly for real-time systems. To reduce the resource consumption of Java in embedded systems, direct hardware support of the language is a valuable option. Furthermore, an implementation of the Java virtual machine in hardware enables...... worst-case execution time analysis of Java programs. This chapter gives an overview of current approaches to hardware support for embedded and real-time Java....

  14. Hardware Support for Embedded Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2012-01-01

    The general Java runtime environment is resource hungry and unfriendly for real-time systems. To reduce the resource consumption of Java in embedded systems, direct hardware support of the language is a valuable option. Furthermore, an implementation of the Java virtual machine in hardware enables...... worst-case execution time analysis of Java programs. This chapter gives an overview of current approaches to hardware support for embedded and real-time Java....

  15. Hardware multiplier processor

    Science.gov (United States)

    Pierce, Paul E.

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  16. Hardware Removal in Craniomaxillofacial Trauma

    Science.gov (United States)

    Cahill, Thomas J.; Gandhi, Rikesh; Allori, Alexander C.; Marcus, Jeffrey R.; Powers, David; Erdmann, Detlev; Hollenbeck, Scott T.; Levinson, Howard

    2015-01-01

    Background Craniomaxillofacial (CMF) fractures are typically treated with open reduction and internal fixation. Open reduction and internal fixation can be complicated by hardware exposure or infection. The literature often does not differentiate between these 2 entities; so for this study, we have considered all hardware exposures as hardware infections. Approximately 5% of adults with CMF trauma are thought to develop hardware infections. Management consists of either removing the hardware versus leaving it in situ. The optimal approach has not been investigated. Thus, a systematic review of the literature was undertaken and a resultant evidence-based approach to the treatment and management of CMF hardware infections was devised. Materials and Methods A comprehensive search of journal articles was performed in parallel using MEDLINE, Web of Science, and ScienceDirect electronic databases. Keywords and phrases used were maxillofacial injuries; facial bones; wounds and injuries; fracture fixation, internal; wound infection; and infection. Our search yielded 529 articles. To focus on CMF fractures with hardware infections, the full text of English-language articles was reviewed to identify articles focusing on the evaluation and management of infected hardware in CMF trauma. Each article’s reference list was manually reviewed and citation analysis performed to identify articles missed by the search strategy. There were 259 articles that met the full inclusion criteria and form the basis of this systematic review. The articles were rated based on the level of evidence. There were 81 grade II articles included in the meta-analysis. Result Our meta-analysis revealed that 7503 patients were treated with hardware for CMF fractures in the 81 grade II articles. Hardware infection occurred in 510 (6.8%) of these patients. Of those infections, hardware removal occurred in 264 (51.8%) patients; hardware was left in place in 166 (32.6%) patients; and in 80 (15.6%) cases

  17. Field Surveys, IOC Valleys. Volume III, Part II. Cultural Resources Survey, Pine and Wah Wah Valleys, Utah.

    Science.gov (United States)

    1981-08-01

    including horse, camel, mammoth, Ertm E-TR-48-III-II 20 musk ox, and certain species of bison, goat, and bear, which had previously inhabited the marsh and...34 - - -9,$.. 𔄃 Im I I I Si to * Location lype/Contents Affiliation 42B@644 rid e over cr ek - P/J depression, cleared areas, Fr elon (f4-5-18-92) ground

  18. Survey of fish impingement at power plants in the United States. Volume III. Estuaries and coastal waters

    Energy Technology Data Exchange (ETDEWEB)

    Stupka, Richard C.; Sharma, Rajendra K.

    1977-03-01

    Impingement of fish at cooling-water intakes of 32 power plants, located on estuaries and coastal waters has been surveyed and data are presented. Descriptions of site, plant, and intake design and operation are provided. Reports in this volume summarize impingement data for individual plants in tabular and histogram formats. Information was available from differing sources such as the utilities themselves, public documents, regulatory agencies, and others. Thus, the extent of detail in the reports varies greatly from plant to plant. Histogram preparation involved an extrapolation procedure that has inadequacies. The reader is cautioned in the use of information presented in this volume to determine intake-design acceptability or intensity of impacts on ecosystems. No conclusions are presented herein; data comparisons are made in Volume IV.

  19. Secure coupling of hardware components

    NARCIS (Netherlands)

    Knobbe, J.W.; Hoepman, J.H.; Joosten, H.J.M.

    2011-01-01

    A method and a system for securing communication between at least a first and a second hardware components of a mobile device is described. The method includes establishing a first shared secret between the first and the second hardware components during an initialization of the mobile device and, f

  20. Flight Avionics Hardware Roadmap

    Science.gov (United States)

    Some, Raphael; Goforth, Monte; Chen, Yuan; Powell, Wes; Paulick, Paul; Vitalpur, Sharada; Buscher, Deborah; Wade, Ray; West, John; Redifer, Matt; Partridge, Harry; Sherman, Aaron; McCabe, Mary

    2014-01-01

    The Avionics Technology Roadmap takes an 80% approach to technology investment in spacecraft avionics. It delineates a suite of technologies covering foundational, component, and subsystem-levels, which directly support 80% of future NASA space mission needs. The roadmap eschews high cost, limited utility technologies in favor of lower cost, and broadly applicable technologies with high return on investment. The roadmap is also phased to support future NASA mission needs and desires, with a view towards creating an optimized investment portfolio that matures specific, high impact technologies on a schedule that matches optimum insertion points of these technologies into NASA missions. The roadmap looks out over 15+ years and covers some 114 technologies, 58 of which are targeted for TRL6 within 5 years, with 23 additional technologies to be at TRL6 by 2020. Of that number, only a few are recommended for near term investment: 1. Rad Hard High Performance Computing 2. Extreme temperature capable electronics and packaging 3. RFID/SAW-based spacecraft sensors and instruments 4. Lightweight, low power 2D displays suitable for crewed missions 5. Radiation tolerant Graphics Processing Unit to drive crew displays 6. Distributed/reconfigurable, extreme temperature and radiation tolerant, spacecraft sensor controller and sensor modules 7. Spacecraft to spacecraft, long link data communication protocols 8. High performance and extreme temperature capable C&DH subsystem In addition, the roadmap team recommends several other activities that it believes are necessary to advance avionics technology across NASA: center dot Engage the OCT roadmap teams to coordinate avionics technology advances and infusion into these roadmaps and their mission set center dot Charter a team to develop a set of use cases for future avionics capabilities in order to decouple this roadmap from specific missions center dot Partner with the Software Steering Committee to coordinate computing hardware

  1. An Evaluation of the Mulligan Stew 4-H Television Series for Extension Service, USDA. Volume III: Case Studies.

    Science.gov (United States)

    Abt Associates, Inc., Cambridge, MA.

    Conducted on over 3,000 fourth, fifth, and sixth grade children in six states, this study documents changes in nutrition-related knowledge and behaviors which can be related to participating in the Mulligan Stew television series. The case studies which comprise this volume function as a brief organizational analysis of the Mulligan Stew effort at…

  2. International conference on high-energy physics. Volume 1. Sessions I to III. [Geneva, June 27-July 4, 1979

    Energy Technology Data Exchange (ETDEWEB)

    1980-02-01

    Volume 1 of the conference proceedings contains sessions on neutrino physics and weak interactions, e/sup +/e/sup -/ physics, and theory. Five of the papers have already been cited in ERA, and can be found by reference to the entry CONF-790642-- in the Report Number Index. The remaining 30 will be processed as they are received on the Atomindex tape. (RWR)

  3. Failure mode analysis for lime/limestone FGD system. Volume III. Plant profiles. Part 1 of 3

    Energy Technology Data Exchange (ETDEWEB)

    Kenney, S.M.; Rosenberg, H.S.; Nilsson, L.I.O.; Oxley, J.H.

    1984-08-01

    This volume contains plant profiles for: Petersburg 3; Hawthorn 3, 4; La Cygne 1; Jeffry 1, 2; Lawrence 4, 5; Green River 1-3; Cane Run 4, 5; Mill Creek 1, 3; Paddy's Run 6; Clay Boswell 4; Milton R. Young 2; Pleasants 1, 2; and Colstrip 1, 2. (DLC)

  4. Contemporary American Success Stories: Famous People of Hispanic Heritage. Volume III. A Mitchell Lane Multicultural Biography Series.

    Science.gov (United States)

    Marvis, Barbara J.

    The biographies in this projected eight volume series for elementary school children represent the diversity of Hispanic heritage in the United States. Those featured are contemporary figures with national origins in the United States or Latin America, with careers that cover many aspects of contemporary life. Every person profiled in the series…

  5. Inventory of Federal energy-related environment and safety research for FY 1977. Volume III. Interactive terminal users guide

    Energy Technology Data Exchange (ETDEWEB)

    Shriner, C.R.; Peck, L.J.; Miller, C.E.

    1978-07-01

    This users guide was prepared to provide interested persons access to, via computer terminals, federally funded energy-related environment and safety research projects for FY 1977. Although this information is also available in hardbound volumes, this on-line searching capability is expected to reduce the time required to answer ad hoc questions and, at the same time, produce meaningful reports.

  6. 48 CFR 1812.7000 - Prohibition on guaranteed customer bases for new commercial space hardware or services.

    Science.gov (United States)

    2010-10-01

    ... customer bases for new commercial space hardware or services. 1812.7000 Section 1812.7000 Federal... PLANNING ACQUISITION OF COMMERCIAL ITEMS Commercial Space Hardware or Services 1812.7000 Prohibition on guaranteed customer bases for new commercial space hardware or services. Public Law 102-139, title III...

  7. Florence Richardson Wyckoff (1905-1997), Fifty Years of Grassroots Social ActivismVolume III: Watsonville Years 1960-1985

    OpenAIRE

    1990-01-01

    Florence Wyckoff's three-volume oral history documents her remarkable, lifelong work as a social activist, during which she has become nationally recognized as an advocate of migrant families and children. From the depression years through the 1970s, she pursued grassroots, democratic, community-building efforts in the service of improving public health standards and providing health care, education, and housing for migrant families. Major legislative milestones in her career of advocacy were...

  8. West Hackberry Strategic Petroleum Reserve site brine-disposal monitoring, Year I report. Volume III. Biological oceanography. Final report

    Energy Technology Data Exchange (ETDEWEB)

    DeRouen, L.R.; Hann, R.W.; Casserly, D.M.; Giammona, C.; Lascara, V.J. (eds.)

    1983-02-01

    The Department of Energy's Strategic Petroleum Reserve Program began discharging brine into the Gulf of Mexico from its West Hackberry site near Cameron, Louisiana in May 1981. The brine originates from underground salt domes being leached with water from the Intracoastal Waterway, making available vast underground storage caverns for crude oil. The effects of brine discharge on aquatic organisms are presented in this volume. The topics covered are: benthos; nekton; phytoplankton; zooplankton; and data management.

  9. Hardware Accelerated Point Rendering of Isosurfaces

    DEFF Research Database (Denmark)

    Bærentzen, Jakob Andreas; Christensen, Niels Jørgen

    2003-01-01

    an approximate technique for point scaling using distance attenuation which makes it possible to render points stored in display lists or vertex arrays. This enables us to render points quickly using OpenGL. Our comparisons show that point generation is significantly faster than triangle generation...... and that the advantage of rendering points as opposed to triangles increases with the size and complexity of the volumes. To gauge the visual quality of future hardware accelerated point rendering schemes, we have implemented a software based point rendering method and compare the quality to both MC and our OpenGL based...

  10. NDAS Hardware Translation Layer Development

    Science.gov (United States)

    Nazaretian, Ryan N.; Holladay, Wendy T.

    2011-01-01

    The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

  11. Hardware Evolution of Control Electronics

    Science.gov (United States)

    Gwaltney, David; Steincamp, Jim; Corder, Eric; King, Ken; Ferguson, M. I.; Dutton, Ken

    2003-01-01

    The evolution of closed-loop motor speed controllers implemented on the JPL FPTA2 is presented. The response of evolved controller to sinusoidal commands, controller reconfiguration for fault tolerance,and hardware evolution are described.

  12. Transport of solid commodities via freight pipeline: cost estimating methodology. Volume III, parts A and B. First year final report

    Energy Technology Data Exchange (ETDEWEB)

    Warner, J.A.; Morlok, E.K.; Gimm, K.K.; Zandi, I.

    1976-07-01

    In order to examine the feasibility of an intercity freight pipeline, it was necessary to develop cost equations for various competing transportation modes. This volume presents cost-estimating equations for rail carload, trailer-on-flatcar, truck, and freight pipeline. Section A presents mathematical equations that approximate the fully allocated and variable costs contained in the ICC cost tables for rail carload, trailer-on-flatcar (TOFC) and truck common-carrier intercity freight movements. These equations were developed to enable the user to approximate the ICC costs quickly and easily. They should find use in initial studies of costs where exact values are not needed, such as in consideration of rate changes, studies of profitability, and in general inter-modal comparisons. Section B discusses the development of a set of engineering cost equations for pneumo-capsule pipelines. The development was based on an analysis of system components and can readily be extended to other types of pipeline. The model was developed for the purpose of a feasibility study. It employs a limited number of generalized parameters and its use is recommended when sufficient detailed and specific engineering information is lacking. These models were used in the comparison of modes presented in Volume I and hence no conclusions regarding relative costs or service of the modes are presented here. The primary conclusion is that the estimates of costs resulting from these models is subject to considerable uncertainty.

  13. Hardware accelerated computer graphics algorithms

    OpenAIRE

    Rhodes, DT

    2008-01-01

    The advent of shaders in the latest generations of graphics hardware, which has made consumer level graphics hardware partially programmable, makes now an ideal time to investigate new graphical techniques and algorithms as well as attempting to improve upon existing ones. This work looks at areas of current interest within the graphics community such as Texture Filtering, Bump Mapping and Depth of Field simulation. These are all areas which have enjoyed much interest over the history of comp...

  14. Inventory of Federal Energy-Related Environment and Safety Research for FY 1978. Volume III, interactive terminal users guide

    Energy Technology Data Exchange (ETDEWEB)

    Miller, C. E.; Barker, Janice F.

    1979-12-01

    This users' guide was prepared to provide interested persons access to, via computer terminals, federally funded energy-related environmental and safety research projects for FY 1978. Although this information is also available in hardbound volumes, this on-line searching capability is expected to reduce the time required to answer ad hoc questions and, at the same time, produce meaningful reports. The data contained in this data base are not exhaustive and represent research reported by the following agencies: Department of Agriculture, Department of Commerce, Department of Defense, Department of Energy, Department of Health, Education, and Welfare, Department of the Interior, Department of Transportation, Federal Energy Administration, National Aeronautics and Space Administration, National Science Foundation, Nuclear Regulatory Commission, Tennessee Valley Authority, U.S. Coast Guard, and the U.S. Environmental Protection Agency.

  15. Artificial heart development program. Volume II. System support. Phase III summary report, July 1, 1973--September 30, 1977

    Energy Technology Data Exchange (ETDEWEB)

    1977-01-01

    Volume 2 covers major activities of the Artificial Heart Development program that supported the design, fabrication, and test of the system demonstration units. Section A.1.0 provides a listing beyond that of the body of the report on the components needed for an implantation. It also presents glove box sterilization calibration results and results of an extensive mock circulation calibration. Section A.2.0 provides detailed procedures for assembly, preparing for use, and the use of the system and major components. Section A.3.0 covers the component research and development activities undertaken to improve components of the existing system units and to prepare for a future prototype system. Section A.4.0 provides a listing of the top assembly drawings of the major systems variations fabricated and tested.

  16. Imprinting Hatchery Reared Salmon and Steelhead Trout for Homing, Volume II of III; Data Summaries, 1978-1983 Final Report.

    Energy Technology Data Exchange (ETDEWEB)

    Slatick, Emil; Ringe, R.R.; Zaugg, Waldo S. (Northwest and Alaska Fisheries Science Center, Coastal Zone and Estuarine Studies Division, Seattle, WA)

    1988-02-02

    The main functions of the National Marine Fisheries Service (NMFS) aquaculture task biologists and contractual scientists involved in the 1978 homing studies were primarily a surveillance of fish physiology, disease, and relative survival during culture in marine net-pens, to determine if there were any unusual factors that might affect imprinting and homing behavior. The studies were conducted with little background knowledge of the implications of disease and physiology on imprinting and homing in salmonids. The health status or the stocks were quite variable as could be expected. The Dworshak and Wells Hatcheries steelhead suffered from some early stresses in seawater, probably osmoregulatory. The incidences of latent BKD in the Wells and Chelan Hatcheries steelhead and Kooskia Hatchery spring chinook salmon were extremely high, and how these will affect survival in the ocean is not known. Gill enzyme activity in the Dworshak and Chelan Hatcheries steelhead at release was low. Of the steelhead, survival in the Tucannon Hatchery stock will probably be the highest, with Dworshak Hatchery stock the lowest. This report contains the data for the narratives in Volume I.

  17. Black liquor combustion validated recovery boiler modeling: Final year report. Volume 3 (Appendices II, sections 2--3 and III)

    Energy Technology Data Exchange (ETDEWEB)

    Grace, T.M.; Frederick, W.J.; Salcudean, M.; Wessel, R.A.

    1998-08-01

    This project was initiated in October 1990, with the objective of developing and validating a new computer model of a recovery boiler furnace using a computational fluid dynamics (CFD) code specifically tailored to the requirements for solving recovery boiler flows, and using improved submodels for black liquor combustion based on continued laboratory fundamental studies. The key tasks to be accomplished were as follows: (1) Complete the development of enhanced furnace models that have the capability to accurately predict carryover, emissions behavior, dust concentrations, gas temperatures, and wall heat fluxes. (2) Validate the enhanced furnace models, so that users can have confidence in the predicted results. (3) Obtain fundamental information on aerosol formation, deposition, and hardening so as to develop the knowledge base needed to relate furnace model outputs to plugging and fouling in the convective sections of the boiler. (4) Facilitate the transfer of codes, black liquid submodels, and fundamental knowledge to the US kraft pulp industry. Volume 3 contains the following appendix sections: Formation and destruction of nitrogen oxides in recovery boilers; Sintering and densification of recovery boiler deposits laboratory data and a rate model; and Experimental data on rates of particulate formation during char bed burning.

  18. ELUCID - Exploring the Local Universe with reConstructed Initial Density field III: Constrained Simulation in the SDSS Volume

    CERN Document Server

    Wang, Huiyuan; Yang, Xiaohu; Zhang, Youcai; Shi, JingJing; Jing, Y P; Liu, Chengze; Li, Shijie; Kang, Xi; Gao, Yang

    2016-01-01

    A method we developed recently for the reconstruction of the initial density field in the nearby Universe is applied to the Sloan Digital Sky Survey Data Release 7. A high-resolution N-body constrained simulation (CS) of the reconstructed initial condition, with $3072^3$ particles evolved in a 500 Mpc/h box, is carried out and analyzed in terms of the statistical properties of the final density field and its relation with the distribution of SDSS galaxies. We find that the statistical properties of the cosmic web and the halo populations are accurately reproduced in the CS. The galaxy density field is strongly correlated with the CS density field, with a bias that depend on both galaxy luminosity and color. Our further investigations show that the CS provides robust quantities describing the environments within which the observed galaxies and galaxy systems reside. Cosmic variance is greatly reduced in the CS so that the statistical uncertainties can be controlled effectively even for samples of small volumes...

  19. Hardware cleanliness methodology and certification

    Science.gov (United States)

    Harvey, Gale A.; Lash, Thomas J.; Rawls, J. Richard

    1995-01-01

    Inadequacy of mass loss cleanliness criteria for selection of materials for contamination sensitive uses, and processing of flight hardware for contamination sensitive instruments is discussed. Materials selection for flight hardware is usually based on mass loss (ASTM E-595). However, flight hardware cleanliness (MIL 1246A) is a surface cleanliness assessment. It is possible for materials (e.g. Sil-Pad 2000) to pass ASTM E-595 and fail MIL 1246A class A by orders of magnitude. Conversely, it is possible for small amounts of nonconforming material (Huma-Seal conformal coating) to not present significant cleanliness problems to an optical flight instrument. Effective cleaning (precleaning, precision cleaning, and ultra cleaning) and cleanliness verification are essential for contamination sensitive flight instruments. Polish cleaning of hardware, e.g. vacuum baking for vacuum applications, and storage of clean hardware, e.g. laser optics, is discussed. Silicone materials present special concerns for use in space because of the rapid conversion of the outgassed residues to glass by solar ultraviolet radiation and/or atomic oxygen. Non ozone depleting solvent cleaning and institutional support for cleaning and certification are also discussed.

  20. Application analysis of solar total energy systems to the residential sector. Volume III, conceptual design. Final report

    Energy Technology Data Exchange (ETDEWEB)

    1979-07-01

    The objective of the work described in this volume was to conceptualize suitable designs for solar total energy systems for the following residential market segments: single-family detached homes, single-family attached units (townhouses), low-rise apartments, and high-rise apartments. Conceptual designs for the total energy systems are based on parabolic trough collectors in conjunction with a 100 kWe organic Rankine cycle heat engine or a flat-plate, water-cooled photovoltaic array. The ORC-based systems are designed to operate as either independent (stand alone) systems that burn fossil fuel for backup electricity or as systems that purchase electricity from a utility grid for electrical backup. The ORC designs are classified as (1) a high temperature system designed to operate at 600/sup 0/F and (2) a low temperature system designed to operate at 300/sup 0/F. The 600/sup 0/F ORC system that purchases grid electricity as backup utilizes the thermal tracking principle and the 300/sup 0/F ORC system tracks the combined thermal and electrical loads. Reject heat from the condenser supplies thermal energy for heating and cooling. All of the ORC systems utilize fossil fuel boilers to supply backup thermal energy to both the primary (electrical generating) cycle and the secondary (thermal) cycle. Space heating is supplied by a central hot water (hydronic) system and a central absorption chiller supplies the space cooling loads. A central hot water system supplies domestic hot water. The photovoltaic system uses a central electrical vapor compression air conditioning system for space cooling, with space heating and domestic hot water provided by reject heat from the water-cooled array. All of the systems incorporate low temperature thermal storage (based on water as the storage medium) and lead--acid battery storage for electricity; in addition, the 600/sup 0/F ORC system uses a therminol-rock high temperature storage for the primary cycle. (WHK)

  1. Raspberry Pi hardware projects 1

    CERN Document Server

    Robinson, Andrew

    2013-01-01

    Learn how to take full advantage of all of Raspberry Pi's amazing features and functions-and have a blast doing it! Congratulations on becoming a proud owner of a Raspberry Pi, the credit-card-sized computer! If you're ready to dive in and start finding out what this amazing little gizmo is really capable of, this ebook is for you. Taken from the forthcoming Raspberry Pi Projects, Raspberry Pi Hardware Projects 1 contains three cool hardware projects that let you have fun with the Raspberry Pi while developing your Raspberry Pi skills. The authors - PiFace inventor, Andrew Robinson and Rasp

  2. Fast DRR splat rendering using common consumer graphics hardware.

    Science.gov (United States)

    Spoerk, Jakob; Bergmann, Helmar; Wanschitz, Felix; Dong, Shuo; Birkfellner, Wolfgang

    2007-11-01

    Digitally rendered radiographs (DRR) are a vital part of various medical image processing applications such as 2D/3D registration for patient pose determination in image-guided radiotherapy procedures. This paper presents a technique to accelerate DRR creation by using conventional graphics hardware for the rendering process. DRR computation itself is done by an efficient volume rendering method named wobbled splatting. For programming the graphics hardware, NVIDIAs C for Graphics (Cg) is used. The description of an algorithm used for rendering DRRs on the graphics hardware is presented, together with a benchmark comparing this technique to a CPU-based wobbled splatting program. Results show a reduction of rendering time by about 70%-90% depending on the amount of data. For instance, rendering a volume of 2 x 10(6) voxels is feasible at an update rate of 38 Hz compared to 6 Hz on a common Intel-based PC using the graphics processing unit (GPU) of a conventional graphics adapter. In addition, wobbled splatting using graphics hardware for DRR computation provides higher resolution DRRs with comparable image quality due to special processing characteristics of the GPU. We conclude that DRR generation on common graphics hardware using the freely available Cg environment is a major step toward 2D/3D registration in clinical routine.

  3. LIQUID PHASE FISCHER-TROPSCH (III & IV) DEMONSTRATION IN THE LAPORTE ALTERNATIVE FUELS DEVELOPMENT UNIT. Final Topical Report. Volume I/II: Main Report. Task 1: Engineering Modifications (Fischer-Tropsch III & IV Demonstration) and Task 2: AFDU Shakedown, Operations, Deactivation (Shut-Down) and Disposal (Fischer-Tropsch III & IV Demonstration).

    Energy Technology Data Exchange (ETDEWEB)

    Bharat L. Bhatt

    1999-06-01

    Slurry phase Fischer-Tropsch technology was successfully demonstrated in DOE's Alternative Fuels Development Unit (AFDU) at LaPorte, Texas. Earlier work at LaPorte, with iron catalysts in 1992 and 1994, had established proof-of-concept status for the slurry phase process. The third campaign (Fischer-Tropsch III), in 1996, aimed at aggressively extending the operability of the slurry reactor using a proprietary cobalt catalyst. Due to an irreversible plugging of catalyst-wax separation filters as a result of unexpected catalyst fines generation, the operations had to be terminated after seven days on-stream. Following an extensive post-run investigation by the participants, the campaign was successfully completed in March-April 1998, with an improved proprietary cobalt catalyst. These runs were sponsored by the U. S. Department of Energy (DOE), Air Products & Chemicals, Inc., and Shell Synthetic Fuels, Inc. (SSFI). A productivity of approximately 140 grams (gm) of hydrocarbons (HC)/ hour (hr)-liter (lit) of expanded slurry volume was achieved at reasonable system stability during the second trial (Fischer-Tropsch IV). The productivity ranged from 110-140 at various conditions during the 18 days of operations. The catalyst/wax filters performed well throughout the demonstration, producing a clean wax product. For the most part, only one of the four filter housings was needed for catalyst/wax filtration. The filter flux appeared to exceed the design flux. A combination of use of a stronger catalyst and some innovative filtration techniques were responsible for this success. There was no sign of catalyst particle attrition and very little erosion of the slurry pump was observed, in contrast to the Fischer-Tropsch III operations. The reactor operated hydrodynamically stable with uniform temperature profile and gas hold-ups. Nuclear density and differential pressure measurements indicated somewhat higher than expected gas hold-up (45 - 50 vol%) during Fischer

  4. LWH & ACH Helmet Hardware Study

    Science.gov (United States)

    2015-11-30

    testing included dimensional measurements, Rockwell hardness and Vicker’s microhardness measurements, metallographic examination of the grain... microhardness measurements (ASTM E384 Standard Test Method for Microindentation Hardness of Materials) were made on the exterior surfaces of screws...hardware as reference values. However, we do not recommend use of surface Vicker’s microhardness testing for characterizing the nuts, because, as

  5. BIOLOGICALLY INSPIRED HARDWARE CELL ARCHITECTURE

    DEFF Research Database (Denmark)

    2010-01-01

    Disclosed is a system comprising: - a reconfigurable hardware platform; - a plurality of hardware units defined as cells adapted to be programmed to provide self-organization and self-maintenance of the system by means of implementing a program expressed in a programming language defined as DNA...... language, where each cell is adapted to communicate with one or more other cells in the system, and where the system further comprises a converter program adapted to convert keywords from the DNA language to a binary DNA code; where the self-organisation comprises that the DNA code is transmitted to one...... or more of the cells, and each of the one or more cells is adapted to determine its function in the system; where if a fault occurs in a first cell and the first cell ceases to perform its function, self-maintenance is performed by that the system transmits information to the cells that the first cell has...

  6. The principles of computer hardware

    CERN Document Server

    Clements, Alan

    2000-01-01

    Principles of Computer Hardware, now in its third edition, provides a first course in computer architecture or computer organization for undergraduates. The book covers the core topics of such a course, including Boolean algebra and logic design; number bases and binary arithmetic; the CPU; assembly language; memory systems; and input/output methods and devices. It then goes on to cover the related topics of computer peripherals such as printers; the hardware aspects of the operating system; and data communications, and hence provides a broader overview of the subject. Its readable, tutorial-based approach makes it an accessible introduction to the subject. The book has extensive in-depth coverage of two microprocessors, one of which (the 68000) is widely used in education. All chapters in the new edition have been updated. Major updates include: powerful software simulations of digital systems to accompany the chapters on digital design; a tutorial-based introduction to assembly language, including many exam...

  7. IRST system: hardware implementation issues

    Science.gov (United States)

    Deshpande, Suyog D.; Chan, Philip; Ser, W.; Venkateswarlu, Ronda

    1999-07-01

    Generally, Infrared Search and Track systems use linear focal-plane-arrays with time-delay and integration, because of their high sensitivity. However, the readout is a cumbersome process and needs special effort. This paper describes signal processing and hardware (HW) implementation issues related to front-end electronics, non-uniformity compensation, signal formatting, target detection, tracking and display system. This paper proposes parallel pipeline architecture with dedicated HW for computationally intensive algorithms and SW intensive DSP HW for reconfigurable architecture.

  8. Hardware Support for Software Debugging

    Science.gov (United States)

    2011-05-01

    Architecture • Concurrency Debugging - ReEnact • Conclusions Cost of Software Defects • Financial Costs • In a study by NIST in 2002 it was found that... ReEnact • Leverages modified Thread-Level Speculation (TLS) hardware • Create partial orderings of threads in a multithreaded program using...logical vector clocks • Using these orderings, ReEnact is able to detect and often repair data race conditions in a multithreaded program • Experiments

  9. Patent Abstract Digest. Volume III.

    Science.gov (United States)

    1981-09-01

    FOR TIlE MULTIPURPOSE 4.122,675 10/1978 Polyak ........................... 60/641 X UTILIZATION OF SOLAR ENERGY FOREIGN PATENT DOCUMENTS 1761 Inventor...contained in Ohio 40"menf .of em W arat thot such use be fro* ffe Pivately owned riht. A 00300 AFSC ar*P7 79c R&LD RECORD (PatentI Abet...., lv PATENT

  10. Meliolales of India - Volume III

    Directory of Open Access Journals (Sweden)

    V.B. Hosagoudar

    2013-04-01

    Full Text Available This work, is the continuation of my preceding two works on Meliolales of India, gives an account of 123 fungal species belonging to five genera, Amazonia (3, Appendiculella (1, Asteridiella (22, Ectendomeliola (1, Irenopsis (8 and Meliola (88, infecting 120 host plants belonging to 49 families. Generic key, digital formula, synoptic key to the species is provided. In the key, all the species are arranged under their alphabetically arranged host families. Description of the individual species is provided with the citation, detailed description, materials examined and their details including their herbarium details. Each species is supplemented with line drawings. Host and the species index is provided at the end. This work includes five new species: Meliola arippaensis, M. calycopteridis, M. cariappae, M. harpullicola and M. mutabilidis; a new variety: Irenopsis hiptages Yamam. Var. indica and two new names: Asteridiella micheliifolia (based on A. micheliae and Meliola strombosiicola (based on Meliola strombosiae

  11. Proceedings of the Twenty-First Water Reactor Safety Information Meeting: Volume 1, Plenary session; Advanced reactor research; advanced control system technology; advanced instrumentation and control hardware; human factors research; probabilistic risk assessment topics; thermal hydraulics; thermal hydraulic research for advanced passive LWRs

    Energy Technology Data Exchange (ETDEWEB)

    Monteleone, S. [Brookhaven National Lab., Upton, NY (United States)] [comp.

    1994-04-01

    This three-volume report contains 90 papers out of the 102 that were presented at the Twenty-First Water Reactor Safety Information Meeting held at the Bethesda Marriott Hotel, Bethesda, Maryland, during the week of October 25--27, 1993. The papers are printed in the order of their presentation in each session and describe progress and results of programs in nuclear safety research conducted in this country and abroad. Foreign participation in the meeting included papers presented by researchers from France, Germany, Japan, Russia, Switzerland, Taiwan, and United Kingdom. The titles of the papers and the names of the authors have been updated and may differ from those that appeared in the final program of the meeting. Individual papers have been cataloged separately. This document, Volume 1 covers the following topics: Advanced Reactor Research; Advanced Instrumentation and Control Hardware; Advanced Control System Technology; Human Factors Research; Probabilistic Risk Assessment Topics; Thermal Hydraulics; and Thermal Hydraulic Research for Advanced Passive Light Water Reactors.

  12. Hardware and software reliability estimation using simulations

    Science.gov (United States)

    Swern, Frederic L.

    1994-01-01

    The simulation technique is used to explore the validation of both hardware and software. It was concluded that simulation is a viable means for validating both hardware and software and associating a reliability number with each. This is useful in determining the overall probability of system failure of an embedded processor unit, and improving both the code and the hardware where necessary to meet reliability requirements. The methodologies were proved using some simple programs, and simple hardware models.

  13. Solid-Liquid Interface Characterization Hardware

    Science.gov (United States)

    Peters, Palmer N.

    2000-01-01

    The objective is to develop enabling technology to characterize the solid-liquid interface during directional solidification to unprecedented levels with real-time measurement hardware. Existing x-ray imaging hardware is combined with compact Seebeck furnaces and thermal profiling hardware, under development, to accomplish the measurements. Furnace thermal profiles are continuously measured in addition to the sample characteristics.

  14. 16 CFR 1508.6 - Hardware.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1508.6 Section 1508.6 Commercial... FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner that eliminates from any hardware accessible to a child within the crib the possibility of the...

  15. 16 CFR 1509.7 - Hardware.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1509.7 Section 1509.7 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall...

  16. Exascale Hardware Architectures Working Group

    Energy Technology Data Exchange (ETDEWEB)

    Hemmert, S; Ang, J; Chiang, P; Carnes, B; Doerfler, D; Leininger, M; Dosanjh, S; Fields, P; Koch, K; Laros, J; Noe, J; Quinn, T; Torrellas, J; Vetter, J; Wampler, C; White, A

    2011-03-15

    The ASC Exascale Hardware Architecture working group is challenged to provide input on the following areas impacting the future use and usability of potential exascale computer systems: processor, memory, and interconnect architectures, as well as the power and resilience of these systems. Going forward, there are many challenging issues that will need to be addressed. First, power constraints in processor technologies will lead to steady increases in parallelism within a socket. Additionally, all cores may not be fully independent nor fully general purpose. Second, there is a clear trend toward less balanced machines, in terms of compute capability compared to memory and interconnect performance. In order to mitigate the memory issues, memory technologies will introduce 3D stacking, eventually moving on-socket and likely on-die, providing greatly increased bandwidth but unfortunately also likely providing smaller memory capacity per core. Off-socket memory, possibly in the form of non-volatile memory, will create a complex memory hierarchy. Third, communication energy will dominate the energy required to compute, such that interconnect power and bandwidth will have a significant impact. All of the above changes are driven by the need for greatly increased energy efficiency, as current technology will prove unsuitable for exascale, due to unsustainable power requirements of such a system. These changes will have the most significant impact on programming models and algorithms, but they will be felt across all layers of the machine. There is clear need to engage all ASC working groups in planning for how to deal with technological changes of this magnitude. The primary function of the Hardware Architecture Working Group is to facilitate codesign with hardware vendors to ensure future exascale platforms are capable of efficiently supporting the ASC applications, which in turn need to meet the mission needs of the NNSA Stockpile Stewardship Program. This issue is

  17. Laser photography system: hardware configuration

    Science.gov (United States)

    Piszczek, Marek; Rutyna, Krzysztof; Kowalski, Marcin; Zyczkowski, Marek

    2012-06-01

    Solution presented in this article is a system using image acquisition time gating method. The time-spatial framing method developed by authors was used to build Laser Photography System (LPS). An active vision system for open space monitoring and terrorist threats detection is being built as an effect of recent work lead in the Institute of Optoelectronics, MUT. The device is destined to prevent and recognize possible terrorist threats in important land and marine areas. The aim of this article is to discuss the properties and hardware configuration of the Laser Photography System.

  18. Electronic processing and control system with programmable hardware

    Science.gov (United States)

    Alkalaj, Leon (Inventor); Fang, Wai-Chi (Inventor); Newell, Michael A. (Inventor)

    1998-01-01

    A computer system with reprogrammable hardware allowing dynamically allocating hardware resources for different functions and adaptability for different processors and different operating platforms. All hardware resources are physically partitioned into system-user hardware and application-user hardware depending on the specific operation requirements. A reprogrammable interface preferably interconnects the system-user hardware and application-user hardware.

  19. Hardware complications in scoliosis surgery

    Energy Technology Data Exchange (ETDEWEB)

    Bagchi, Kaushik; Mohaideen, Ahamed [Department of Orthopaedic Surgery and Musculoskeletal Services, Maimonides Medical Center, Brooklyn, NY (United States); Thomson, Jeffrey D. [Connecticut Children' s Medical Center, Department of Orthopaedics, Hartford, CT (United States); Foley, Christopher L. [Department of Radiology, Connecticut Children' s Medical Center, Hartford, Connecticut (United States)

    2002-07-01

    Background: Scoliosis surgery has undergone a dramatic evolution over the past 20 years with the advent of new surgical techniques and sophisticated instrumentation. Surgeons have realized scoliosis is a complex multiplanar deformity that requires thorough knowledge of spinal anatomy and pathophysiology in order to manage patients afflicted by it. Nonoperative modalities such as bracing and casting still play roles in the treatment of scoliosis; however, it is the operative treatment that has revolutionized the treatment of this deformity that affects millions worldwide. As part of the evolution of scoliosis surgery, newer implants have resulted in improved outcomes with respect to deformity correction, reliability of fixation, and paucity of complications. Each technique and implant has its own set of unique complications, and the surgeon must appreciate these when planning surgery. Materials and methods: Various surgical techniques and types of instrumentation typically used in scoliosis surgery are briefly discussed. Though scoliosis surgery is associated with a wide variety of complications, only those that directly involve the hardware are discussed. The current literature is reviewed and several illustrative cases of patients treated for scoliosis at the Connecticut Children's Medical Center and the Newington Children's Hospital in Connecticut are briefly presented. Conclusion: Spine surgeons and radiologists should be familiar with the different types of instrumentation in the treatment of scoliosis. Furthermore, they should recognize the clinical and roentgenographic signs of hardware failure as part of prompt and effective treatment of such complications. (orig.)

  20. Travel Software using GPU Hardware

    CERN Document Server

    Szalwinski, Chris M; Dimov, Veliko Atanasov; CERN. Geneva. ATS Department

    2015-01-01

    Travel is the main multi-particle tracking code being used at CERN for the beam dynamics calculations through hadron and ion linear accelerators. It uses two routines for the calculation of space charge forces, namely, rings of charges and point-to-point. This report presents the studies to improve the performance of Travel using GPU hardware. The studies showed that the performance of Travel with the point-to-point simulations of space-charge effects can be speeded up at least 72 times using current GPU hardware. Simple recompilation of the source code using an Intel compiler can improve performance at least 4 times without GPU support. The limited memory of the GPU is the bottleneck. Two algorithms were investigated on this point: repeated computation and tiling. The repeating computation algorithm is simpler and is the currently recommended solution. The tiling algorithm was more complicated and degraded performance. Both build and test instructions for the parallelized version of the software are inclu...

  1. Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...

  2. Proceedings of the International Conference on the Psychology of Mathematics Education (PME) (11th, Montreal, Canada, July 19-25, 1987). Volumes I-III.

    Science.gov (United States)

    Bergeron, Jacques C., Ed.; And Others

    The Proceedings of PME-XI has been published in three separate volumes because of the large total of 161 individual conference papers reported. Volume I contains four plenary papers, all on the subject of "constructivism," and 44 commented papers arranged under 4 themes. Volume II contains 56 papers (39 commented; 17 uncommented)…

  3. Proceedings of the International Conference on the Psychology of Mathematics Education (PME) (17th, Tsukuba, Japan, July 18-23, 1993). Volumes I-III.

    Science.gov (United States)

    Hirabayashi, Ichiei, Ed.; And Others

    The Proceedings of PME-XVII has been published in three volumes because of the large number of papers presented at the conference. Volume I contains a brief Plenary Panel report, 4 full-scale Plenary Addresses, the brief reports of 10 Working Groups and 4 Discussion Groups, and a total of 23 Research Reports grouped under 4 themes. Volume II…

  4. Hardware design for Hash functions

    Science.gov (United States)

    Lee, Yong Ki; Knežević, Miroslav; Verbauwhede, Ingrid M. R.

    Due to its cryptographic and operational key features such as the one-way function property, high speed and a fixed output size independent of input size the hash algorithm is one of the most important cryptographic primitives. A critical drawback of most cryptographic algorithms is the large computational overhead. This is getting more critical since the data amount to process or communicate is increasing a lot. In many cases, a proper use of the hash algorithm reduces the computational overhead. Digital signature generation and the message authentication are the most common applications of the hash algorithms. The increasing data size also motivates hardware designers to have a throughput optimal architecture for a given hash algorithm. In this chapter, some popular hash algorithms and their cryptanalysis are briefly introduced, and a design methodology for throughput optimal architectures of MD4-based hash algorithms is described in detail.

  5. Hardware Assisted ROP Detection Mode (HARD Mode)

    Science.gov (United States)

    2013-08-01

    Distribution A. Cleared for public release; unlimited distribution. USAFA-CN-2013-457 Hardware Assisted ROP Detection Mode (HARD Mode) NATHANIEL HART...457 This report, "Hardware Assisted ROP Detection Mode (HARD Mode)" is presented as a competent treatment of the subj ect, worthy of publication. The...Technical 20120810-20121215 Hardware Assisted ROP Detection Mode (HARD Mode) NATHANIEL HART MICHAEL WINSTEAD MARTIN CARLISLE RODNEY LYKINS MICHAEL

  6. Hardware/software partitioning in Verilog.

    OpenAIRE

    2002-01-01

    We propose in this paper an algebraic approach to hardware/software partitioning in Verilog HDL. We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog, which brings forth our successful verification for the correctness of the partitioning process by algebra of Ver...

  7. Identification of Hardware Trojans triggering signals

    OpenAIRE

    Dupuis, Sophie; Di Natale, Giorgio; Flottes, Marie-Lise; Rouzeyre, Bruno

    2013-01-01

    International audience; Hardware Trojans are malicious alterations to a circuit. These modifications can be inserted either during the design phase or during the fabrication process. Due to the diversity of Hardware Trojans (HTs), detecting and/or locating them are challenging tasks. Numerous approaches have been proposed to address this problem. Methods based on logic testing consist in trying to activate potential Hardware Trojans in order to detect erroneous outputs during simulation. Howe...

  8. Hardware Implementation of Singular Value Decomposition

    Science.gov (United States)

    Majumder, Swanirbhar; Shaw, Anil Kumar; Sarkar, Subir Kumar

    2016-06-01

    Singular value decomposition (SVD) is a useful decomposition technique which has important role in various engineering fields such as image compression, watermarking, signal processing, and numerous others. SVD does not involve convolution operation, which make it more suitable for hardware implementation, unlike the most popular transforms. This paper reviews the various methods of hardware implementation for SVD computation. This paper also studies the time complexity and hardware complexity in various methods of SVD computation.

  9. Multiple IMU system hardware interface design, volume 2

    Science.gov (United States)

    Landey, M.; Brown, D.

    1975-01-01

    The design of each system component is described. Emphasis is placed on functional requirements unique in this system, including data bus communication, data bus transmitters and receivers, and ternary-to-binary torquing decision logic. Mechanization drawings are presented.

  10. Thermal Hardware for the Thermal Analyst

    Science.gov (United States)

    Steinfeld, David

    2015-01-01

    The presentation will be given at the 26th Annual Thermal Fluids Analysis Workshop (TFAWS 2015) hosted by the Goddard Space Flight Center (GSFC) Thermal Engineering Branch (Code 545). NCTS 21070-1. Most Thermal analysts do not have a good background into the hardware which thermally controls the spacecraft they design. SINDA and Thermal Desktop models are nice, but knowing how this applies to the actual thermal hardware (heaters, thermostats, thermistors, MLI blanketing, optical coatings, etc...) is just as important. The course will delve into the thermal hardware and their application techniques on actual spacecraft. Knowledge of how thermal hardware is used and applied will make a thermal analyst a better engineer.

  11. An Algebraic Hardware/Software Partitioning Algorithm

    Institute of Scientific and Technical Information of China (English)

    秦胜潮; 何积丰; 裘宗燕; 张乃孝

    2002-01-01

    Hardware and software co-design is a design technique which delivers computer systems comprising hardware and software components. A critical phase of the co-design process is to decompose a program into hardware and software. This paper proposes an algebraic partitioning algorithm whose correctness is verified in program algebra. The authors introduce a program analysis phase before program partitioning and develop a collection of syntax-based splitting rules. The former provides the information for moving operations from software to hardware and reducing the interaction between components, and the latter supports a compositional approach to program partitioning.

  12. Open-source hardware for medical devices.

    Science.gov (United States)

    Niezen, Gerrit; Eslambolchilar, Parisa; Thimbleby, Harold

    2016-04-01

    Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device.

  13. Proceedings of the Conference of the International Group for the Psychology of Mathematics Education (PME) (16th, Durham, NH, August 6-11, 1992). Volumes I-III.

    Science.gov (United States)

    Geeslin, William, Ed.; Graham, Karen, Ed.

    The Proceedings of PME-XVI has been published in three volumes because of the large number of papers presented at the conference. Volume 1 contains: (1) brief reports from each of the 11 standing Working Groups on their respective roles in organizing PME-XVI; (2) brief reports from 6 Discussion Groups; and (3) 35 research reports covering authors…

  14. Manipulation hardware for microgravity research

    Energy Technology Data Exchange (ETDEWEB)

    Herndon, J.N.; Glassell, R.L.; Butler, P.L.; Williams, D.M. (Oak Ridge National Lab., TN (USA)); Rohn, D.A. (National Aeronautics and Space Administration, Cleveland, OH (USA). Lewis Research Center); Miller, J.H. (Sverdrup Technology, Inc., Brook Park, OH (USA))

    1990-01-01

    The establishment of permanent low earth orbit occupation on the Space Station Freedom will present new opportunities for the introduction of productive flexible automation systems into the microgravity environment of space. The need for robust and reliable robotic systems to support experimental activities normally intended by astronauts will assume great importance. Many experimental modules on the space station are expected to require robotic systems for ongoing experimental operations. When implementing these systems, care must be taken not to introduce deleterious effects on the experiments or on the space station itself. It is important to minimize the acceleration effects on the experimental items being handled while also minimizing manipulator base reaction effects on adjacent experiments and on the space station structure. NASA Lewis Research Center has been performing research on these manipulator applications, focusing on improving the basic manipulator hardware, as well as developing improved manipulator control algorithms. By utilizing the modular manipulator concepts developed during the Laboratory Telerobotic Manipulator program, Oak Ridge National Laboratory has developed an experimental testbed system called the Microgravity Manipulator, incorporating two pitch-yaw modular positioners to provide a 4 dof experimental manipulator arm. A key feature in the design for microgravity manipulation research was the use of traction drives for torque transmission in the modular pitch-yaw differentials.

  15. Life Sciences Division Spaceflight Hardware

    Science.gov (United States)

    Yost, B.

    1999-01-01

    The Ames Research Center (ARC) is responsible for the development, integration, and operation of non-human life sciences payloads in support of NASA's Gravitational Biology and Ecology (GB&E) program. To help stimulate discussion and interest in the development and application of novel technologies for incorporation within non-human life sciences experiment systems, three hardware system models will be displayed with associated graphics/text explanations. First, an Animal Enclosure Model (AEM) will be shown to communicate the nature and types of constraints physiological researchers must deal with during manned space flight experiments using rodent specimens. Second, a model of the Modular Cultivation System (MCS) under development by ESA will be presented to highlight technologies that may benefit cell-based research, including advanced imaging technologies. Finally, subsystems of the Cell Culture Unit (CCU) in development by ARC will also be shown. A discussion will be provided on candidate technology requirements in the areas of specimen environmental control, biotelemetry, telescience and telerobotics, and in situ analytical techniques and imaging. In addition, an overview of the Center for Gravitational Biology Research facilities will be provided.

  16. Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

    NARCIS (Netherlands)

    Pham-Quoc Cuong, P.

    2015-01-01

    Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and

  17. Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

    NARCIS (Netherlands)

    Pham-Quoc Cuong, P.

    2015-01-01

    Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and ar

  18. Analysis and Approach to the Development of an Advanced Multimedia Instructional System. Volume II. Appendix III. Media Cost Data. Final Report.

    Science.gov (United States)

    Rhode, William E.; And Others

    Basic cost estimates for selected instructional media are tabled in this document, Part II (Appendix III) of the report "Analysis and Approach to the Development of an Advanced Multimedia Instructional System" by William E. Rhode and others. Learning materials production costs are given for motion pictures, still visuals, videotapes, live…

  19. Nutrition and Health Characteristics of Low-Income Populations, Volume III, School-Age Children. E-FAN-04-014-3

    Science.gov (United States)

    Fox, Mary Kay; Cole, Nancy

    2004-01-01

    Data from the Third National Health and Nutrition Examination Survey (NHANES-III), conducted in 1988-94, were used to compare the nutrition and health characteristics of the Nation's school-age children--boys and girls ages 5-18. Three groups of children were compared based on household income: income at or below 130 percent of poverty (lowest…

  20. Energy use in the marine transportation industry: Task III. Efficiency improvements; Task IV. Industry future. Final report, Volume IV. [Projections for year 2000

    Energy Technology Data Exchange (ETDEWEB)

    None

    1977-12-01

    Tasks III and IV measure the characteristics of potential research and development programs that could be applied to the maritime industry. It was necessary to identify potential operating scenarios for the maritime industry in the year 2000 and determine the energy consumption that would result given those scenarios. After the introductory chapter the operational, regulatory, and vessel-size scenarios for the year 2000 are developed in Chapter II. In Chapter III, future cargo flows and expected levels of energy use for the baseline 2000 projection are determined. In Chapter IV, the research and development programs are introduced into the future US flag fleet and the energy-savings potential associated with each is determined. The first four appendices (A through D) describe each of the generic technologies. The fifth appendix (E) contains the baseline operating and cost parameters against which 15 program areas were evaluated. (MCW)

  1. JPL multipolarization workstation - Hardware, software and examples of data analysis

    Science.gov (United States)

    Burnette, Fred; Norikane, Lynne

    1987-01-01

    A low-cost stand-alone interactive image processing workstation has been developed for operations on multipolarization JPL aircraft SAR data, as well as data from future spaceborne imaging radars. A recently developed data compression technique is used to reduce the data volume to 10 Mbytes, for a typical data set, so that interactive analysis may be accomplished in a timely and efficient manner on a supermicrocomputer. In addition to presenting a hardware description of the work station, attention is given to the software that has been developed. Three illustrative examples of data analysis are presented.

  2. Applying a Genetic Algorithm to Reconfigurable Hardware

    Science.gov (United States)

    Wells, B. Earl; Weir, John; Trevino, Luis; Patrick, Clint; Steincamp, Jim

    2004-01-01

    This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

  3. Space shuttle main engine hardware simulation

    Science.gov (United States)

    Vick, H. G.; Hampton, P. W.

    1985-01-01

    The Huntsville Simulation Laboratory (HSL) provides a simulation facility to test and verify the space shuttle main engine (SSME) avionics and software system using a maximum complement of flight type hardware. The HSL permits evaluations and analyses of the SSME avionics hardware, software, control system, and mathematical models. The laboratory has performed a wide spectrum of tests and verified operational procedures to ensure system component compatibility under all operating conditions. It is a test bed for integration of hardware/software/hydraulics. The HSL is and has been an invaluable tool in the design and development of the SSME.

  4. Computer-Based Testing System. Project STEEL. A Special Project To Develop and Implement a Computer-Based Special Teacher Education and Evaluation Laboratory. Volume III. Final Report.

    Science.gov (United States)

    Frick, Theodore W.; And Others

    The document is part of the final report on Project STEEL (Special Teacher Education and Evaluation Laboratory) intended to extend the utilization of technology in the training of preservice special education teachers. This volume focuses on the third of four project objectives, the development and implementation of a computer-based testing…

  5. Study of Manpower Requirements by Occupation for Alternative Technologies in the Energy-Related Industries, 1970-1990. Volumes I, IIA, and III.

    Science.gov (United States)

    Gutmanis, Ivars; And Others

    The report presents the methodology used by the National Planning Association (NPA), under contract to the Federal Energy Administration (FEA), to estimate direct labor usage coefficients in some sixty different occupational categories involved in construction, operation, and maintenance of energy facilities. Volume 1 presents direct labor usage…

  6. Hardware device binding and mutual authentication

    Energy Technology Data Exchange (ETDEWEB)

    Hamlet, Jason R; Pierson, Lyndon G

    2014-03-04

    Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

  7. Hardware-in-the-Loop Testing

    Data.gov (United States)

    Federal Laboratory Consortium — RTC has a suite of Hardware-in-the Loop facilities that include three operational facilities that provide performance assessment and production acceptance testing of...

  8. Reliability of NFV Using COTS Hardware

    Institute of Scientific and Technical Information of China (English)

    Li Mo

    2014-01-01

    This paper describes a study on the feasibility of using com-mercial off -the -shelf (COTS) hardware for telecom equip-ment. The study outlines the conditions under which COTS hardware can be utilized in a network function virtualization environment. The concept of silent -error probability is intro-duced to account for software errors and/or undetectable hard-ware failures, and is included in both the theoretical work and simulations. Silent failures are critical to overall system availability. Site -related issues are created by combined site maintenance and site failure. Site maintenance does not no-ticeably limit system availability unless there are also site fail-ures. Because the theory becomes extremely involved when site failure is introduced, simulation is used to determine the impact of those facts that constitutes the undesirable features of using COTS hardware.

  9. IDD Archival Hardware Architecture and Workflow

    Energy Technology Data Exchange (ETDEWEB)

    Mendonsa, D; Nekoogar, F; Martz, H

    2008-10-09

    This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

  10. Development of robotics facility docking test hardware

    Science.gov (United States)

    Loughead, T. E.; Winkler, R. V.

    1984-01-01

    Design and fabricate test hardware for NASA's George C. Marshall Space Flight Center (MSFC) are reported. A docking device conceptually developed was fabricated, and two docking targets which provide high and low mass docking loads were required and were represented by an aft 61.0 cm section of a Hubble space telescope (ST) mockup and an upgrading of an existing multimission modular spacecraft (MSS) mockup respectively. A test plan is developed for testing the hardware.

  11. Cooperative communications hardware, channel and PHY

    CERN Document Server

    Dohler, Mischa

    2010-01-01

    Facilitating Cooperation for Wireless Systems Cooperative Communications: Hardware, Channel & PHY focuses on issues pertaining to the PHY layer of wireless communication networks, offering a rigorous taxonomy of this dispersed field, along with a range of application scenarios for cooperative and distributed schemes, demonstrating how these techniques can be employed. The authors discuss hardware, complexity and power consumption issues, which are vital for understanding what can be realized at the PHY layer, showing how wireless channel models differ from more traditional

  12. Software for Managing Inventory of Flight Hardware

    Science.gov (United States)

    Salisbury, John; Savage, Scott; Thomas, Shirman

    2003-01-01

    The Flight Hardware Support Request System (FHSRS) is a computer program that relieves engineers at Marshall Space Flight Center (MSFC) of most of the non-engineering administrative burden of managing an inventory of flight hardware. The FHSRS can also be adapted to perform similar functions for other organizations. The FHSRS affords a combination of capabilities, including those formerly provided by three separate programs in purchasing, inventorying, and inspecting hardware. The FHSRS provides a Web-based interface with a server computer that supports a relational database of inventory; electronic routing of requests and approvals; and electronic documentation from initial request through implementation of quality criteria, acquisition, receipt, inspection, storage, and final issue of flight materials and components. The database lists both hardware acquired for current projects and residual hardware from previous projects. The increased visibility of residual flight components provided by the FHSRS has dramatically improved the re-utilization of materials in lieu of new procurements, resulting in a cost savings of over $1.7 million. The FHSRS includes subprograms for manipulating the data in the database, informing of the status of a request or an item of hardware, and searching the database on any physical or other technical characteristic of a component or material. The software structure forces normalization of the data to facilitate inquiries and searches for which users have entered mixed or inconsistent values.

  13. Three-dimensional changes of the hyoid bone and airway volumes related to its relationship with horizontal anatomic planes after bimaxillary surgery in skeletal Class III patients.

    Science.gov (United States)

    Kim, Min-Ah; Kim, Bo-Ram; Choi, Jin-Young; Youn, Jong-Kuk; Kim, Yoon-Ji R; Park, Yang-Ho

    2013-07-01

    To evaluate longitudinal changes of the hyoid bone position and pharyngeal airway space after bimaxillary surgery in mandibular prognathism patients. Cone-beam computed tomography scans were taken for 25 mandibular prognathism patients before surgery (T0), 2 months after surgery (T1), and 6 months after surgery (T2). The positional displacement of the hyoid bone was assessed using the coordinates at T0, T1, and T2. Additionally, the volume of each subject's pharyngeal airway was measured. The mean amount of posterior maxilla impaction was 3.76 ± 1.33 mm as the palatal plane rotated 2.04° ± 2.28° in a clockwise direction as a result of bimaxillary surgery. The hyoid bone moved backward (P .05, P bimaxillary surgery. The decrease in the pharyngeal airway volume was correlated to the changes in the palatal plane inclination and the positional change of the hyoid bone.

  14. Central Receiver Solar Thermal Power System, Phase 1. CDRL Item 2. Pilot Plant preliminary design report. Volume III, Book 1. Collector subsystem

    Energy Technology Data Exchange (ETDEWEB)

    Hallet, Jr., R. W.; Gervais, R. L.

    1977-10-01

    The central receiver system consists of a field of heliostats, a central receiver, a thermal storage unit, an electrical power generation system, and balance of plant. This volume discusses the collector field geometry, requirements and configuration. The development of the collector system and subsystems are discussed and the selection rationale outlined. System safety and availability are covered. Finally, the plans for collector portion of the central receiver system are reviewed.

  15. Line-focus solar central power system, Phase I. Final report, 29 September 1978 to 30 April 1980. Volume III. Appendices

    Energy Technology Data Exchange (ETDEWEB)

    Slemmons, A J

    1980-04-01

    The conceptual design, parametric analysis, cost and performance analysis, and commercial assessment of a 100-MWe line-focus solar central receiver power plant are reported. This volume contains the appendices: (a) methods of determination of molten salt heat-transfer coefficients and tube-wall temperatures, (b) inputs for STEAEC programs, (c) description of system analysis computer program, (d) receiver analysis program, and (e) heliostat production plan and design methodology. (WHK)

  16. A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware Trojans

    OpenAIRE

    Dupuis, Sophie; Ba, Papa-Sidi; Ba, Papa-Sidy; Di Natale, Giorgio; Flottes, Marie-Lise; Rouzeyre, Bruno

    2014-01-01

    International audience; Hardware piracy is a threat that is becoming more and more serious these last years. The different types of threats include mask theft, illegal overproduction, as well as the insertion of malicious alterations to a circuit, referred to as Hardware Trojans. To protect circuits from overproduction, circuits can be encrypted so that only authorized users can use the circuits. In this paper, we propose an encryption technique that also helps thwarting Hardware Trojan inser...

  17. Evolvable Hardware Based Software-Hardware Co-Designing Platform ECDP

    Institute of Scientific and Technical Information of China (English)

    TU Hang; WU Tao-jun; LI Yuan-xiang

    2005-01-01

    Based on the theories of EA (Evolutionary Algorithm) and EHW (Evolvable Hardware), we devise an EHW-based software-hardware co-designing platform ECDP, on which we provided standards for hardware system encoding and evolving operation designing, as well as circuit emulating tools. The major features of this system are: two-layer-encoding of circuit structure, off-line evolving with software emulation and the evolving of genetic program designing. With this system, we implemented the auto-designing of some software-hardware systems, like the random number generator.

  18. Symptomatic Hardware Removal After First Tarsometatarsal Arthrodesis.

    Science.gov (United States)

    Peterson, Kyle S; McAlister, Jeffrey E; Hyer, Christopher F; Thompson, John

    2016-01-01

    Severe hallux valgus deformity with proximal instability creates pain and deformity in the forefoot. First tarsometatarsal joint arthrodesis is performed to reduce the intermetatarsal angle and stabilize the joint. Dorsomedial locking plate fixation with adjunctive lag screw fixation is used because of its superior construct strength and healing rate. Despite this, questions remain regarding whether this hardware is more prominent and more likely to need removal. The purpose of the present study was to determine the incidence of symptomatic hardware at the first tarsometatarsal joint and to determine the incidence of hardware removal resulting from prominence and/or discomfort. A review of 165 medical records of consecutive patients who had undergone first tarsometatarsal joint arthrodesis with plate fixation was conducted. The outcome of interest was the incidence of symptomatic hardware removal in patients with clinical union. The mean age was 55 (range 18.4 to 78.8) years. The mean follow-up duration was 65.9 ± 34.0 (range 7.0 to 369.0) weeks. In our cohort, 25 patients (15.2%) had undergone hardware removed because of pain and irritation. Of these patients, 18 (72.0%) had a locking plate and lag screw removed, and 7 (28.0%) had crossing lag screws removed. The fixation of a first tarsometatarsal joint fusion poses a difficult situation owing to minimal soft tissue coverage and the inherent need for robust fixation to promote fusion. Hardware can become prominent postoperatively and can become painful and/or induce cutaneous compromise. The results of the present observational investigation imply that surgeons can reasonably inform patients that the incidence of symptomatic hardware removal after first tarsometatarsal arthrodesis is approximately 15% within a median duration of 9.0 months after surgery.

  19. III-V microelectronics

    CERN Document Server

    Nougier, JP

    1991-01-01

    As is well known, Silicon widely dominates the market of semiconductor devices and circuits, and in particular is well suited for Ultra Large Scale Integration processes. However, a number of III-V compound semiconductor devices and circuits have recently been built, and the contributions in this volume are devoted to those types of materials, which offer a number of interesting properties. Taking into account the great variety of problems encountered and of their mutual correlations when fabricating a circuit or even a device, most of the aspects of III-V microelectronics, from fundamental p

  20. Variations in target volume definition for postoperative radiotherapy in stage III non-small-cell lung cancer: analysis of an international contouring study.

    Science.gov (United States)

    Spoelstra, Femke O B; Senan, Suresh; Le Péchoux, Cecile; Ishikura, Satoshi; Casas, Francesc; Ball, David; Price, Allan; De Ruysscher, Dirk; van Sörnsen de Koste, John R

    2010-03-15

    Postoperative radiotherapy (PORT) in patients with completely resected non-small-cell lung cancer with mediastinal involvement is controversial because of the failure of earlier trials to demonstrate a survival benefit. Improved techniques may reduce toxicity, but the treatment fields used in routine practice have not been well studied. We studied routine target volumes used by international experts and evaluated the impact of a contouring protocol developed for a new prospective study, the Lung Adjuvant Radiotherapy Trial (Lung ART). Seventeen thoracic radiation oncologists were invited to contour their routine clinical target volumes (CTV) for 2 representative patients using a validated CD-ROM-based contouring program. Subsequently, the Lung ART study protocol was provided, and both cases were contoured again. Variations in target volumes and their dosimetric impact were analyzed. Routine CTVs were received for each case from 10 clinicians, whereas six provided both routine and protocol CTVs for each case. Routine CTVs varied up to threefold between clinicians, but use of the Lung ART protocol significantly decreased variations. Routine CTVs in a postlobectomy patient resulted in V(20) values ranging from 12.7% to 54.0%, and Lung ART protocol CTVs resulted in values of 20.6% to 29.2%. Similar results were seen for other toxicity parameters and in the postpneumectomy patient. With the exception of upper paratracheal nodes, protocol contouring improved coverage of the required nodal stations. Even among experts, significant interclinician variations are observed in PORT fields. Inasmuch as contouring variations can confound the interpretation of PORT results, mandatory quality assurance procedures have been incorporated into the current Lung ART study. Copyright 2010 Elsevier Inc. All rights reserved.

  1. Evaluation of the Synthoil process. Volume III. Unit block flow diagrams for a 100,000 barrel/stream day facility

    Energy Technology Data Exchange (ETDEWEB)

    Salmon, R.; Edwards, M.S.; Ulrich, W.C.

    1977-06-01

    This volume consists of individual block flowsheets for the various units of the Synthoil facility, showing the overall flows into and out of each unit. Material balances for the following units are incomplete because these are proprietary processes and the information was not provided by the respective vendors: Unit 24-Claus Sulfur Plant; Unit 25-Oxygen Plant; Unit 27-Sulfur Plant (Redox Type); and Unit 28-Sour Water Stripper and Ammonia Recovery Plant. The process information in this form was specifically requested by ERDA/FE for inclusion in the final report.

  2. Quantitative hardware prediction modeling for hardware/software co-design

    NARCIS (Netherlands)

    Meeuws, R.J.

    2012-01-01

    Hardware estimation is an important factor in Hardware/Software Co-design. In this dissertation, we present the Quipu Modeling Approach, a high-level quantitative prediction model for HW/SW Partitioning using statistical methods. Our approach uses linear regression between software complexity metric

  3. Robot navigation system using intrinsic evolvable hardware

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    Recently there has been great interest in the idea that evolvable system based on the principle of ar tifcial intelligence can be used to continuously and autonomously adapt the behaviour of physically embedded systems such as autonomous mobile robots and intelligent home devices. Meanwhile, we have seen the introduc tion of evolvable hardware(EHW): new integrated electronic circuits that are able to continuously evolve to a dapt the chages in the environment implemented by evolutionary algorithms such as genetic algorithm(GA)and reinforcement learning. This paper concentrates on developing a robotic navigation system whose basic behav iours are obstacle avoidance and light source navigation. The results demonstrate that the intrinsic evolvable hardware system is able to create the stable robotiiuc behaviours as required in the real world instead of the tra ditional hardware systems.

  4. New Concepts in Fish Ladder Design, Volume III of IV, Assessment of Fishway Development and Design, 1982-1983 Final Report.

    Energy Technology Data Exchange (ETDEWEB)

    Powers, Patrick D.; Orsborn, John F.

    1985-08-01

    This volume covers the broad, though relatively short, historical basis for this project. The historical developments of certain design features, criteria and research activities are traced. Current design practices are summarized based on the results of an international survey and interviews with agency personnel and consultants. The fluid mechanics and hydraulics of fishway systems are discussed. Fishways (or fishpasses) can be classified in two ways: (1) on the basis of the method of water control (chutes, steps (ladders), or slots); and (2) on the basis of the degree and type of water control. This degree of control ranges from a natural waterfall to a totally artificial environment at a hatchery. Systematic procedures for analyzing fishways based on their configuration, species, and hydraulics are presented. Discussions of fish capabilities, energy expenditure, attraction flow, stress and other factors are included.

  5. Applied research on energy storage and conversion for photovoltaic and wind energy systems. Volume III. Wind conversion systems with energy storage. Final report

    Energy Technology Data Exchange (ETDEWEB)

    1978-01-01

    The variability of energy output inherent in wind energy conversion systems (WECS) has led to the investigation of energy storage as a means of managing the available energy when immediate, direct use is not possible or desirable. This portion of the General Electric study was directed at an evaluation of those energy storage technologies deemed best suited for use in conjunction with a wind energy conversion system in utility, residential and intermediate applications. Break-even cost goals are developed for several storage technologies in each application. These break-even costs are then compared with cost projections presented in Volume I of this report to show technologies and time frames of potential economic viability. The report summarizes the investigations performed and presents the results, conclusions and recommendations pertaining to use of energy storage with wind energy conversion systems.

  6. Sweet Lake geopressured-geothermal project, Magma Gulf-Technadril/DOE Amoco fee. Volume III. Final report. Annual report, February 1982-March 1985

    Energy Technology Data Exchange (ETDEWEB)

    Durham, C.O. Jr.; O' Brien, F.D.; Rodgers, R.W. (eds.)

    1985-01-01

    This report presents the results of the testing of Sand 3 (15,245 to 15,280 feet in depth) which occurred from November 1983 to March 1984 and evaluates these new data in comparison to results from the testing of Sand 5 (15,385 to 15,415 feet in depth) which occurred from June 1981 to February 1982. It also describes the reworking of the production and salt water disposal wells preparatory to the Sand 3 testing as well as the plug and abandon procedures requested to terminate the project. The volume contains two parts: Part 1 includes the text and accompanying plates, figures and tables; Part 2 consists of the appendixes including auxiliary reports and tabulations.

  7. Economic impact of syndesmosis hardware removal.

    Science.gov (United States)

    Lalli, Trapper A J; Matthews, Leslie J; Hanselman, Andrew E; Hubbard, David F; Bramer, Michelle A; Santrock, Robert D

    2015-09-01

    Ankle syndesmosis injuries are commonly seen with 5-10% of sprains and 10% of ankle fractures involving injury to the ankle syndesmosis. Anatomic reduction has been shown to be the most important predictor of clinical outcomes. Optimal surgical management has been a subject of debate in the literature. The method of fixation, number of screws, screw size, and number of cortices are all controversial. Postoperative hardware removal has also been widely debated in the literature. Some surgeons advocate for elective hardware removal prior to resuming full weightbearing. Returning to the operating room for elective hardware removal results in increased cost to the patient, potential for infection or complication(s), and missed work days for the patient. Suture button devices and bioabsorbable screw fixation present other options, but cortical screw fixation remains the gold standard. This retrospective review was designed to evaluate the economic impact of a second operative procedure for elective removal of 3.5mm cortical syndesmosis screws. Two hundred and two patients with ICD-9 code for "open treatment of distal tibiofibular joint (syndesmosis) disruption" were identified. The medical records were reviewed for those who underwent elective syndesmosis hardware removal. The primary outcome measurements included total hospital billing charges and total hospital billing collection. Secondary outcome measurements included average individual patient operative costs and average operating room time. Fifty-six patients were included in the study. Our institution billed a total of $188,271 (USD) and collected $106,284 (55%). The average individual patient operating room cost was $3579. The average operating room time was 67.9 min. To the best of our knowledge, no study has previously provided cost associated with syndesmosis hardware removal. Our study shows elective syndesmosis hardware removal places substantial economic burden on both the patient and the healthcare system.

  8. Developing Successful Proposals in Women's Educational Equity, Volume I: The Guide = Desarrollo de propuestas exitosas relacionadas con la equidad educativa de la mujer, volumen I: La guia. Volume II: The Supplement. Volume III: The Swipe File. Volume IV: Workshop Training Manual.

    Science.gov (United States)

    Matthews, Walter R.; And Others

    Four volumes present materials and a training workshop on proposal writing. The materials aim to give people the skills and resources with which to translate their ideas into fully developed grant proposals for projects related to educational equity for women. However, the information is applicable to most other funding procedures. The first…

  9. Language of CTO interventions - Focus on hardware.

    Science.gov (United States)

    Mishra, Sundeep

    2016-01-01

    The knowledge of variety of chronic total occlusion (CTO) hardware and the ability to use them represents the key to success of any CTO interventions. However, the multiplicity of CTO hardware and their physical character and the terminology used by experts create confusion in the mind of an average interventional cardiologist, particularly a beginner in this field. This knowledge is available but is scattered. We aim to classify and compare the currently used devices based on their properties focusing on how physical character of each device can be utilized in a specific situation, thus clarifying and simplifying the technical discourse. Copyright © 2016. Published by Elsevier B.V.

  10. Hardware Accelerated Sequence Alignment with Traceback

    Directory of Open Access Journals (Sweden)

    Scott Lloyd

    2009-01-01

    in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements.

  11. Magnetic Field Apparatus (MFA) Hardware Test

    Science.gov (United States)

    Anderson, Ken; Boody, April; Reed, Dave; Wang, Chung; Stuckey, Bob; Cox, Dave

    1999-01-01

    The objectives of this study are threefold: (1) Provide insight into water delivery in microgravity and determine optimal germination paper wetting for subsequent seed germination in microgravity; (2) Observe the behavior of water exposed to a strong localized magnetic field in microgravity; and (3) Simulate the flow of fixative (using water) through the hardware. The Magnetic Field Apparatus (MFA) is a new piece of hardware slated to fly on the Space Shuttle in early 2001. MFA is designed to expose plant tissue to magnets in a microgravity environment, deliver water to the plant tissue, record photographic images of plant tissue, and deliver fixative to the plant tissue.

  12. Hardware Trojan by Hot Carrier Injection

    CERN Document Server

    Shiyanovskii, Y; Papachristou, C; Weyer, D; Clay, W

    2009-01-01

    This paper discusses how hot carrier injection (HCI) can be exploited to create a trojan that will cause hardware failures. The trojan is produced not via additional logic circuitry but by controlled scenarios that maximize and accelerate the HCI effect in transistors. These scenarios range from manipulating the manufacturing process to varying the internal voltage distribution. This new type of trojan is difficult to test due to its gradual hardware degradation mechanism. This paper describes the HCI effect, detection techniques and discusses the possibility for maliciously induced HCI trojans.

  13. Human Centered Hardware Modeling and Collaboration

    Science.gov (United States)

    Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

    2013-01-01

    In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

  14. Quantum neuromorphic hardware for quantum artificial intelligence

    Science.gov (United States)

    Prati, Enrico

    2017-08-01

    The development of machine learning methods based on deep learning boosted the field of artificial intelligence towards unprecedented achievements and application in several fields. Such prominent results were made in parallel with the first successful demonstrations of fault tolerant hardware for quantum information processing. To which extent deep learning can take advantage of the existence of a hardware based on qubits behaving as a universal quantum computer is an open question under investigation. Here I review the convergence between the two fields towards implementation of advanced quantum algorithms, including quantum deep learning.

  15. REVIEW OF THE NEGOTIATION OF THE MODEL PROTOCOL ADDITIONAL TO THE AGREEMENT(S) BETWEEN STATE(S) AND THE INTERNATIONAL ATOMIC ENERGY AGENCY FOR THE APPLICATION OF SAFEGUARDS, INFCIRC/540 (Corrected) VOLUME III/III, IAEA COMMITTEE 24, DEVELOPMENT OF INFCIRC/540, ARTICLE-BY-ARTICLE REVIEW (1996-1997).

    Energy Technology Data Exchange (ETDEWEB)

    Rosenthal, M.D.; Houck, F.

    2010-01-01

    In this section of the report, the development of INFCIRC/540 is traced by a compilation of citations from the IAEA documents presented to the Board of Governors and the records of discussions in the Board that took place prior to the establishment of Committee 24 as well as the documents and discussions of that committee. The evolution of the text is presented separately for each article or, for the more complex articles, for each paragraph or group of paragraphs of the article. This section covers all articles, including those involving no issues. Background, issues, interpretations and conclusions, which were addressed in Volumes I, II, and III are not repeated here. The comments by states that are included are generally limited to objections and suggested changes. Requests for clarification or elaboration have been omitted, although it is recognized that such comments were sometimes veiled objections.

  16. High-Volume Transanal Surgery with CPH34 HV for the Treatment of III-IV Degree Haemorrhoids: Final Short-Term Results of an Italian Multicenter Clinical Study

    Directory of Open Access Journals (Sweden)

    Giuliano Reboa

    2016-01-01

    Full Text Available The clinical chart of 621 patients with III-IV haemorrhoids undergoing Stapled Hemorrhoidopexy (SH with CPH34 HV in 2012–2014 was consecutively reviewed to assess its safety and efficacy after at least 12 months of follow-up. Mean volume of prolapsectomy was significantly higher (13.0 mL; SD, 1.4 in larger prolapse (9.3 mL; SD, 1.2 (p<0.001. Residual or recurrent haemorrhoids occurred in 11 of 621 patients (1.8% and in 12 of 581 patients (1.9%, respectively. Relapse was correlated with higher preoperative Constipation Scoring System (CSS (p=0.000, Pescatori’s degree (p=0.000, Goligher’s grade (p=0.003, prolapse exceeding half of the length of the Circular Anal Dilator (CAD (p=0.000, and higher volume of prolapsectomy (p=0.000. At regression analysis, only the preoperative CSS, Pescatori’s degree, Goligher’s grade, and volume of resection were significantly predictive of relapse. A high level of satisfaction (VAS = 8.6; SD, 1.0 coupled with a reduction of 12-month CSS (Δ preoperative CSS/12 mo CSS = 3.4, SD, 2.0; p<0.001 was observed. The wider prolapsectomy achievable with CPH34 HV determined an overall 3.7% relapse rate in patients with high prevalence of large internal rectal prolapse, coupled with high satisfaction index, significant reduction of CSS, and very low complication rates.

  17. QCE : A Simulator for Quantum Computer Hardware

    NARCIS (Netherlands)

    Michielsen, Kristel; Raedt, Hans De

    2003-01-01

    The Quantum Computer Emulator (QCE) described in this paper consists of a simulator of a generic, general purpose quantum computer and a graphical user interface. The latter is used to control the simulator, to define the hardware of the quantum computer and to debug and execute quantum algorithms.

  18. Environmental Control System Software & Hardware Development

    Science.gov (United States)

    Vargas, Daniel Eduardo

    2017-01-01

    ECS hardware: (1) Provides controlled purge to SLS Rocket and Orion spacecraft. (2) Provide mission-focused engineering products and services. ECS software: (1) NASA requires Compact Unique Identifiers (CUIs); fixed-length identifier used to identify information items. (2) CUI structure; composed of nine semantic fields that aid the user in recognizing its purpose.

  19. Microprocessor Design Using Hardware Description Language

    Science.gov (United States)

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  20. A Hardware Abstraction Layer in Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Korsholm, Stephan; Kalibera, Tomas

    2011-01-01

    Embedded systems use specialized hardware devices to interact with their environment, and since they have to be dependable, it is attractive to use a modern, type-safe programming language like Java to develop programs for them. Standard Java, as a platform-independent language, delegates access ...

  1. Remote hardware-reconfigurable robotic camera

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

    2001-10-01

    In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

  2. LWH and ACH Helmet Hardware Study

    Science.gov (United States)

    2015-11-30

    testing included dimensional measurements, Rockwell hardness and Vicker’s microhardness measurements, metallographic examination of the grain... microhardness measurements (ASTM E384 Standard Test Method for Microindentation Hardness of Materials) were made on the exterior surfaces of screws...hardware as reference values. However, we do not recommend use of surface Vicker’s microhardness testing for characterizing the nuts, because, as

  3. Computer hardware for radiologists: Part I.

    Science.gov (United States)

    Indrajit, Ik; Alam, A

    2010-08-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium(®) 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  4. Computer hardware for radiologists: Part I

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM, Picture Archiving and Communication System (PACS, Radiology information system (RIS technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU, the chipset, the random access memory (RAM, the memory modules, bus, storage drives, and ports. The personnel computer (PC has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs. The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  5. Digital Hardware Design Teaching: An Alternative Approach

    Science.gov (United States)

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  6. Efficient Runtime Management of Reconfigurable Hardware Resources

    NARCIS (Netherlands)

    Marconi, T.

    2011-01-01

    Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction in overall hardware area, power efficiency, and economic cost in addition to the performance improvements due to better customization. However, the users of such systems have to be able to afford som

  7. Digital Hardware Design Teaching: An Alternative Approach

    Science.gov (United States)

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  8. A mathematical approach towards hardware design

    NARCIS (Netherlands)

    Smit, Gerard J.M.; Kuper, Jan; Baaij, Christiaan P.R.; Athanas, P.M.; Becker, J.; Teich, J.; Verbauwhede, I.

    2010-01-01

    Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications. There is a need of higher level abstraction mechanisms. In the embedded systems group of th

  9. Enabling Open Hardware through FOSS tools

    CERN Document Server

    CERN. Geneva

    2016-01-01

    Software developers often take open file formats and tools for granted. When you publish code on github, you do not ask yourself if somebody will be able to open it and modify it. We need the same freedom in the open hardware world, to make it truly accessible for everyone.

  10. Transistor Level Circuit Experiments using Evolvable Hardware

    Science.gov (United States)

    Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Daud, Taher; Thakoor, A.

    2005-01-01

    The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

  11. Arbitrary Hardware Software Trade-Offs

    NARCIS (Netherlands)

    Middelhoek, Peter F.A.

    1995-01-01

    This paper discusses a novel transformation-based design methodology and its use in the design of complex programmable VLSI systems. During the life-cycle of a complex system, the optimal trade-off between partially implementing in hardware or software is changing. This is due to varying system requ

  12. Hardware Model of a Shipboard Generator

    Science.gov (United States)

    2009-05-19

    13 2.3 DC Motor Characteristics...Figure 4: Motor Nameplate.............................................................................................. 14 Figure 5: DC Motor Circuit...used in the hardware model is briefly described in the first two sections of Chapter 2. Section 2.3 details the characterization of the DC motor and

  13. Associative Memory Hardware Elements for Cognitive Systems

    Science.gov (United States)

    2006-01-01

    basis for learning ............. 40 Figure 33: Historical examples of crossbar for associative memory hardware ................ 41 Figure 34: Recent...provide one and only one function such as classification, segmentation, or pattern completion, the lazy learning approach can provide all such...standard machine learning databases and shows exponential memory capacity. For example, one test with 200 patterns was learned by only 7 quantum

  14. Arbitrary Hardware/Software Trade Offs

    NARCIS (Netherlands)

    Middelhoek, P.F.A.; Middelhoek, Peter F.A.

    1995-01-01

    This paper discusses a novel transformation-based design methodology and its use in the design of complex programmable VLSI systems. During the life-cycle of a complex system, the optimal trade-off between partially implementing in hardware or software is changing. This is due to varying system

  15. Effect of spine hardware on small spinal stereotactic radiosurgery dosimetry

    Science.gov (United States)

    Wang, Xin; Yang, James N.; Li, Xiaoqiang; Tailor, Ramesh; Vassilliev, Oleg; Brown, Paul; Rhines, Laurence; Chang, Eric

    2013-10-01

    Monte Carlo (MC) modeling of a 6 MV photon beam was used to study the dose perturbation from a titanium rod 5 mm in diameter in various small fields range from 2 × 2 to 5 × 5 cm2. The results showed that the rod increased the dose to water by ˜6% at the water-rod interface because of electron backscattering and decreased the dose by ˜7% in the shadow of the rod because of photon attenuation. The Pinnacle3 treatment planning system calculations matched the MC results at the depths more than 1 cm past the rod when the correct titanium density of 4.5 g cm-3 was used, but significantly underestimated the backscattering dose at the water-rod interface. A CT-density table with a top density of 1.82 g cm-3 (cortical bone) is a practical way to reduce the dosimetric error from the artifacts by preventing high density assignment to them, but can underestimates the attenuation by the titanium rod by 6%. However, when multi-beam with intensity modulation is used in actual patient spinal stereotactic radiosurgery treatment, the dosimetric effect of assigning 4.5 instead of 1.82 g cm-3 to titanium implants is complicated. It ranged from minimal effect to 2% dose difference affecting 15% target volume in the study. When hardware is in the beam path, density override to the titanium hardware is recommended.

  16. Optical calibration hardware for the Sudbury Neutrino Observatory

    CERN Document Server

    Moffat, B A; Duncan, F A; Graham, K; Hallin, A L; Hearns, C A W; Maneira, J; Skensved, P; Grant, D R

    2005-01-01

    The optical properties of the Sudbury Neutrino Observatory (SNO) heavy water Cherenkov neutrino detector are measured in situ using a light diffusing sphere ("laserball"). This diffuser is connected to a pulsed nitrogen/dye laser via specially developed underwater optical fibre umbilical cables. The umbilical cables are designed to have a small bending radius, and can be easily adapted for a variety of calibration sources in SNO. The laserball is remotely manipulated to many positions in the D2O and H2O volumes, where data at six different wavelengths are acquired. These data are analysed to determine the absorption and scattering of light in the heavy water and light water, and the angular dependence of the response of the detector's photomultiplier tubes. This paper gives details of the physical properties, construction, and optical characteristics of the laserball and its associated hardware.

  17. Campus Information Network Hardware System Design%Campus Information Network Hardware System Design

    Institute of Scientific and Technical Information of China (English)

    刘正勇

    2011-01-01

    The emphasis of constructing and developing the campus information network is how to design and optimize the network hardware system. This paper mainly studies the network system structure design, the server system structure design and the network export

  18. Advanced hardware design for error correcting codes

    CERN Document Server

    Coussy, Philippe

    2015-01-01

    This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques.

  19. Hardware and software status of QCDOC

    CERN Document Server

    Boyle, P A; Christ, N H; Clark, M; Cohen, S D; Cristian, C; Dong, Z; Gara, A; Joó, B; Jung, C; Kim, C; Levkova, L; Liao, X; Liu, G; Mawhinney, Robert D; Ohta, S; Petrov, K V; Wettig, T; Yamaguchi, A

    2003-01-01

    QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

  20. Flexible Hardware-Based Stereo Matching

    Directory of Open Access Journals (Sweden)

    2009-02-01

    Full Text Available To enable adaptive stereo vision for hardware-based embedded stereo vision systems, we propose a novel technique for implementing a flexible block size, disparity range, and frame rate. By reusing existing resources of a static architecture, rather than dynamic reconfiguration, our technique is compatible with application specific integrated circuit (ASIC as well as field programmable gate array (FPGA implementations. We present the corresponding block diagrams and their implementation in our hardware-based stereo matching architecture. Furthermore, we show the impact of flexible stereo matching on the generated disparity maps for the sum of absolute differences (SADs, rank, and census transform algorithms. Finally, we discuss the resource usage and achievable performance when synthesized for an Altera Stratix II FPGA.

  1. Flexible Hardware-Based Stereo Matching

    Directory of Open Access Journals (Sweden)

    Steininger Andreas

    2008-01-01

    Full Text Available Abstract To enable adaptive stereo vision for hardware-based embedded stereo vision systems, we propose a novel technique for implementing a flexible block size, disparity range, and frame rate. By reusing existing resources of a static architecture, rather than dynamic reconfiguration, our technique is compatible with application specific integrated circuit (ASIC as well as field programmable gate array (FPGA implementations. We present the corresponding block diagrams and their implementation in our hardware-based stereo matching architecture. Furthermore, we show the impact of flexible stereo matching on the generated disparity maps for the sum of absolute differences (SADs, rank, and census transform algorithms. Finally, we discuss the resource usage and achievable performance when synthesized for an Altera Stratix II FPGA.

  2. Particle Transport Simulation on Heterogeneous Hardware

    CERN Document Server

    CERN. Geneva

    2014-01-01

    CPUs and GPGPUs. About the speaker Vladimir Koylazov is CTO and founder of Chaos Software and one of the original developers of the V-Ray raytracing software. Passionate about 3D graphics and programming, Vlado is the driving force behind Chaos Group's software solutions. He participated in the implementation of algorithms for accurate light simulations and support for different hardware platforms, including CPU and GPGPU, as well as distributed calculat...

  3. Hardware-Independent Proofs of Numerical Programs

    Science.gov (United States)

    Boldo, Sylvie; Nguyen, Thi Minh Tuyen

    2010-01-01

    On recent architectures, a numerical program may give different answers depending on the execution hardware and the compilation. Our goal is to formally prove properties about numerical programs that are true for multiple architectures and compilers. We propose an approach that states the rounding error of each floating-point computation whatever the environment. This approach is implemented in the Frama-C platform for static analysis of C code. Small case studies using this approach are entirely and automatically proved

  4. Hardware code generation from dataflow programs

    OpenAIRE

    Siret, Nicolas; Wipliez, Matthieu; Nezan, Jean Francois; Rhatay, Aimad

    2010-01-01

    International audience; The elaboration of new systems on embedded targets is becoming more and more complex. In particular, multimedia devices are now implemented using mixed hardware and software architecture, which improve the computational power but also increase the design complexity and the time to market. New design flows have been developed to help designers in the development of complex architecture. These design flows are often based on the use of languages with a higher level of ab...

  5. Computer hardware for radiologists: Part I

    OpenAIRE

    Indrajit I; Alam A

    2010-01-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware...

  6. Computer hardware for radiologists: Part I

    OpenAIRE

    Indrajit I; Alam A

    2010-01-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware...

  7. Exploiting Semiconductor Properties for Hardware Trojans

    OpenAIRE

    Shiyanovskii, Y.; Wolff, F; Papachristou, C.; D. Weyer; Clay, W.

    2009-01-01

    This paper discusses the possible introduction of hidden reliability defects during CMOS foundry fabrication processes that may lead to accelerated wearout of the devices. These hidden defects or hardware Trojans can be created by deviation from foundry design rules and processing parameters. The Trojans are produced by exploiting time-based wearing mechanisms (HCI, NBTI, TDDB and EM) and/or condition-based triggers (ESD, Latchup and Softerror). This class of latent damage is difficult to tes...

  8. A hardware implementation of neural network with modified HANNIBAL architecture

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Bum youb; Chung, Duck Jin [Inha University, Inchon (Korea, Republic of)

    1996-03-01

    A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). 14 refs., 10 figs., 3 tabs.

  9. A Hardware Lab Anywhere At Any Time

    Directory of Open Access Journals (Sweden)

    Tobias Schubert

    2004-12-01

    Full Text Available Scientific technical courses are an important component in any student's education. These courses are usually characterised by the fact that the students execute experiments in special laboratories. This leads to extremely high costs and a reduction in the maximum number of possible participants. From this traditional point of view, it doesn't seem possible to realise the concepts of a Virtual University in the context of sophisticated technical courses since the students must be "on the spot". In this paper we introduce the so-called Mobile Hardware Lab which makes student participation possible at any time and from any place. This lab nevertheless transfers a feeling of being present in a laboratory. This is accomplished with a special Learning Management System in combination with hardware components which correspond to a fully equipped laboratory workstation that are lent out to the students for the duration of the lab. The experiments are performed and solved at home, then handed in electronically. Judging and marking are also both performed electronically. Since 2003 the Mobile Hardware Lab is now offered in a completely web based form.

  10. "Greenbook Algorithms and Hardware Needs Analysis"

    Energy Technology Data Exchange (ETDEWEB)

    De Jong, Wibe A.; Oehmen, Chris S.; Baxter, Douglas J.

    2007-01-09

    "This document describes the algorithms, and hardware balance requirements needed to enable the solution of real scientific problems in the DOE core mission areas of environmental and subsurface chemistry, computational and systems biology, and climate science. The MSCF scientific drivers have been outlined in the Greenbook, which is available online at http://mscf.emsl.pnl.gov/docs/greenbook_for_web.pdf . Historically, the primary science driver has been the chemical and the molecular dynamics of the biological science area, whereas the remaining applications in the biological and environmental systems science areas have been occupying a smaller segment of the available hardware resources. To go from science drivers to hardware balance requirements, the major applications were identified. Major applications on the MSCF resources are low- to high-accuracy electronic structure methods, molecular dynamics, regional climate modeling, subsurface transport, and computational biology. The algorithms of these applications were analyzed to identify the computational kernels in both sequential and parallel execution. This analysis shows that a balanced architecture is needed with respect to processor speed, peak flop rate, peak integer operation rate, and memory hierarchy, interprocessor communication, and disk access and storage. A single architecture can satisfy the needs of all of the science areas, although some areas may take greater advantage of certain aspects of the architecture. "

  11. Testing Microshutter Arrays Using Commercial FPGA Hardware

    Science.gov (United States)

    Rapchun, David

    2008-01-01

    NASA is developing micro-shutter arrays for the Near Infrared Spectrometer (NIRSpec) instrument on the James Webb Space Telescope (JWST). These micro-shutter arrays allow NIRspec to do Multi Object Spectroscopy, a key part of the mission. Each array consists of 62414 individual 100 x 200 micron shutters. These shutters are magnetically opened and held electrostatically. Individual shutters are then programmatically closed using a simple row/column addressing technique. A common approach to provide these data/clock patterns is to use a Field Programmable Gate Array (FPGA). Such devices require complex VHSIC Hardware Description Language (VHDL) programming and custom electronic hardware. Due to JWST's rapid schedule on the development of the micro-shutters, rapid changes were required to the FPGA code to facilitate new approaches being discovered to optimize the array performance. Such rapid changes simply could not be made using conventional VHDL programming. Subsequently, National Instruments introduced an FPGA product that could be programmed through a Labview interface. Because Labview programming is considerably easier than VHDL programming, this method was adopted and brought success. The software/hardware allowed the rapid change the FPGA code and timely results of new micro-shutter array performance data. As a result, numerous labor hours and money to the project were conserved.

  12. Richard III

    DEFF Research Database (Denmark)

    Lauridsen, Palle Schantz

    2017-01-01

    Kort analyse af Shakespeares Richard III med fokus på, hvordan denne skurk fremstilles, så tilskuere (og læsere) langt henad vejen kan føle sympati med ham. Med paralleller til Netflix-serien "House of Cards"......Kort analyse af Shakespeares Richard III med fokus på, hvordan denne skurk fremstilles, så tilskuere (og læsere) langt henad vejen kan føle sympati med ham. Med paralleller til Netflix-serien "House of Cards"...

  13. A Comparative Study on Hardware Platforms for Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Thang Vu Chien

    2012-01-01

    Full Text Available Recently, Wireless Sensor Networks (WSNs attract a great deal of research attention, and are envisioned to support a variety of applications, including building monitoring, environment control, wild-life habitat monitoring, forest fire detection, industry automation, military, security, and health-care. Over the years, we have seen a variety of hardware platforms for WSNs to facilitate developing WSN applications. In this paper, we provide a comprehensive review of existing hardware platforms for WSNs. We first present the hardware architecture of a wireless sensor node. We then survey the major hardware platforms for WSNs and present a comparison of these hardware platforms. Finally we present some recommendations from the perspectives of hardware platform developers and hardware platform users. The authors hope that making information about existing hardware platforms will assist researchers working in this area to appreciate the diversity of platforms available to them and to help them select the most appropriate platform for their purposes.

  14. Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

    Science.gov (United States)

    Kizhner, Semion; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Petrick, David J.; Day, John H. (Technical Monitor)

    2001-01-01

    Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the

  15. Trusted Module Acquisition Through Proof-Carrying Hardware Intellectual Property

    Science.gov (United States)

    2015-05-22

    hardware intellectual property (PCHIP) framework, which aims to ensure the trustworthiness of third-party hardware IPs utilizing formal methods. We...published in non peer-reviewed journals: Final Report: Trusted Module Acquisition Through Proof-Carrying Hardware Intellectual Property Report Title By...borrowing ideas from the proof carrying code (PCC) in software domain, in this project we introduced the proof carrying hardware intellectual property

  16. The Impact of Flight Hardware Scavenging on Space Logistics

    Science.gov (United States)

    Oeftering, Richard C.

    2011-01-01

    For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

  17. Dynamically-Loaded Hardware Libraries (HLL) Technology for Audio Applications

    DEFF Research Database (Denmark)

    Esposito, A.; Lomuscio, A.; Nunzio, L. Di

    2016-01-01

    In this work, we apply hardware acceleration to embedded systems running audio applications. We present a new framework, Dynamically-Loaded Hardware Libraries or HLL, to dynamically load hardware libraries on reconfigurable platforms (FPGAs). Provided a library of application-specific processors,...

  18. PACE: A dynamic programming algorithm for hardware/software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    with a hardware area constraint and the problem of minimizing hardware area with a system execution time constraint. The target architecture consists of a single microprocessor and a single hardware chip (ASIC, FPGA, etc.) which are connected by a communication channel. The algorithm incorporates a realistic...

  19. CHeCS: International Space Station Medical Hardware Catalog

    Science.gov (United States)

    2008-01-01

    The purpose of this catalog is to provide a detailed description of each piece of hardware in the Crew Health Care System (CHeCS), including subpacks associated with the hardware, and to briefly describe the interfaces between the hardware and the ISS. The primary user of this document is the Space Medicine/Medical Operations ISS Biomedical Flight Controllers (ISS BMEs).

  20. Dynamically-Loaded Hardware Libraries (HLL) Technology for Audio Applications

    DEFF Research Database (Denmark)

    Esposito, A.; Lomuscio, A.; Nunzio, L. Di

    2016-01-01

    In this work, we apply hardware acceleration to embedded systems running audio applications. We present a new framework, Dynamically-Loaded Hardware Libraries or HLL, to dynamically load hardware libraries on reconfigurable platforms (FPGAs). Provided a library of application-specific processors...

  1. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    Hardware acceleration is a viable solution to obtain energy efficiency in data intensive computation. In this work, we present a hardware framework to dynamically load hardware libraries, HLL, on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on...

  2. Computer hardware for radiologists: Part 2

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU, chipset, random access memory (RAM, and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ′ever increasing′ digital future.

  3. Computer hardware for radiologists: Part 2.

    Science.gov (United States)

    Indrajit, Ik; Alam, A

    2010-11-01

    Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the 'ever increasing' digital future.

  4. Open Source Hardware for DIY Environmental Sensing

    Science.gov (United States)

    Aufdenkampe, A. K.; Hicks, S. D.; Damiano, S. G.; Montgomery, D. S.

    2014-12-01

    The Arduino open source electronics platform has been very popular within the DIY (Do It Yourself) community for several years, and it is now providing environmental science researchers with an inexpensive alternative to commercial data logging and transmission hardware. Here we present the designs for our latest series of custom Arduino-based dataloggers, which include wireless communication options like self-meshing radio networks and cellular phone modules. The main Arduino board uses a custom interface board to connect to various research-grade sensors to take readings of turbidity, dissolved oxygen, water depth and conductivity, soil moisture, solar radiation, and other parameters. Sensors with SDI-12 communications can be directly interfaced to the logger using our open Arduino-SDI-12 software library (https://github.com/StroudCenter/Arduino-SDI-12). Different deployment options are shown, like rugged enclosures to house the loggers and rigs for mounting the sensors in both fresh water and marine environments. After the data has been collected and transmitted by the logger, the data is received by a mySQL-PHP stack running on a web server that can be accessed from anywhere in the world. Once there, the data can be visualized on web pages or served though REST requests and Water One Flow (WOF) services. Since one of the main benefits of using open source hardware is the easy collaboration between users, we are introducing a new web platform for discussion and sharing of ideas and plans for hardware and software designs used with DIY environmental sensors and data loggers.

  5. Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

    Science.gov (United States)

    Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

    2008-01-01

    This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  6. Hardware Design of a Smart Meter

    Directory of Open Access Journals (Sweden)

    Ganiyu A. Ajenikoko

    2014-09-01

    Full Text Available Smart meters are electronic measurement devices used by utilities to communicate information for billing customers and operating their electric systems. This paper presents the hardware design of a smart meter. Sensing and circuit protection circuits are included in the design of the smart meter in which resistors are naturally a fundamental part of the electronic design. Smart meters provides a route for energy savings, real-time pricing, automated data collection and eliminating human errors due to manual readings which would ultimately reduce labour costs, diagnosis and instantaneous fault detection. This allows for predictive maintenance resulting in a more efficient and reliable distribution network.

  7. Methodology for Assessing Reusability of Spaceflight Hardware

    Science.gov (United States)

    Childress-Thompson, Rhonda; Thomas, L. Dale; Farrington, Phillip

    2017-01-01

    In 2011 the Space Shuttle, the only Reusable Launch Vehicle (RLV) in the world, returned to earth for the final time. Upon retirement of the Space Shuttle, the United States (U.S.) no longer possessed a reusable vehicle or the capability to send American astronauts to space. With the National Aeronautics and Space Administration (NASA) out of the RLV business and now only pursuing Expendable Launch Vehicles (ELV), not only did companies within the U.S. start to actively pursue the development of either RLVs or reusable components, but entities around the world began to venture into the reusable market. For example, SpaceX and Blue Origin are developing reusable vehicles and engines. The Indian Space Research Organization is developing a reusable space plane and Airbus is exploring the possibility of reusing its first stage engines and avionics housed in the flyback propulsion unit referred to as the Advanced Expendable Launcher with Innovative engine Economy (Adeline). Even United Launch Alliance (ULA) has announced plans for eventually replacing the Atlas and Delta expendable rockets with a family of RLVs called Vulcan. Reuse can be categorized as either fully reusable, the situation in which the entire vehicle is recovered, or partially reusable such as the National Space Transportation System (NSTS) where only the Space Shuttle, Space Shuttle Main Engines (SSME), and Solid Rocket Boosters (SRB) are reused. With this influx of renewed interest in reusability for space applications, it is imperative that a systematic approach be developed for assessing the reusability of spaceflight hardware. The partially reusable NSTS offered many opportunities to glean lessons learned; however, when it came to efficient operability for reuse the Space Shuttle and its associated hardware fell short primarily because of its two to four-month turnaround time. Although there have been several attempts at designing RLVs in the past with the X-33, Venture Star and Delta Clipper

  8. Development of Hardware Dual Modality Tomography System

    Directory of Open Access Journals (Sweden)

    R. M. Zain

    2009-06-01

    Full Text Available The paper describes the hardware development and performance of the Dual Modality Tomography (DMT system. DMT consists of optical and capacitance sensors. The optical sensors consist of 16 LEDs and 16 photodiodes. The Electrical Capacitance Tomography (ECT electrode design use eight electrode plates as the detecting sensor. The digital timing and the control unit have been developing in order to control the light projection of optical emitters, switching the capacitance electrodes and to synchronize the operation of data acquisition. As a result, the developed system is able to provide a maximum 529 set data per second received from the signal conditioning circuit to the computer.

  9. Coquet: a Coq library for verifying hardware

    CERN Document Server

    Braibant, Thomas

    2011-01-01

    We propose a new library to model and verify hardware circuits in the Coq proof assistant. This library allows one to easily build circuits by following the usual pen-and-paper diagrams. We define a deep-embedding: we use a (dependently typed) data-type that models the architecture of circuits, and a meaning function. We propose tactics that ease the reasoning about the behavior of the circuits, and we demonstrate that our approach is practicable by proving the correctness of various circuits: a text-book divide and conquer adder of parametric size, some higher-order combinators of circuits, and some sequential circuits: a buffer, and a register.

  10. Fast Gridding on Commodity Graphics Hardware

    DEFF Research Database (Denmark)

    Sørensen, Thomas Sangild; Schaeffter, Tobias; Noe, Karsten Østergaard

    2007-01-01

    The most commonly used algorithm for non-cartesian MRI reconstruction is the gridding algorithm [1]. It consists of three steps:                    1) convolution with a gridding kernel and resampling on a cartesian grid, 2) inverse FFT, and 3) deapodization. On the CPU the convolution step...... implemented on graphics hardware giving a significant speedup compared to CPU based alternatives. We present a novel GPU implementation of the convolution step that overcomes the problems of memory bandwidth that has limited the speed of previous GPU gridding algorithms [2]....

  11. Inventario hardware: Proyecto intermódulos

    OpenAIRE

    Francisco García, Jesús de; Camacho Ortega, Pedro Jesús; Pérez Alonso, David

    2014-01-01

    A través de la identificación de una necesidad real de una aplicación informática que sirviera para el control y gestión del inventario del material hardware de los laboratorios de prácticas de Ciclos Formativos de Grado Superior (CFGS), se propuso un Proyecto que involucrara a diferentes módulos de la titulación de Desarrollo de Aplicaciones Multiplataforma (DAM), a través del cual trabajasen las competencias específicas y generales de su titulación. En un primer paso los alumnos de 1º de...

  12. Exploiting Semiconductor Properties for Hardware Trojans

    CERN Document Server

    Shiyanovskii, Y; Papachristou, C; Weyer, D; Clay, W

    2009-01-01

    This paper discusses the possible introduction of hidden reliability defects during CMOS foundry fabrication processes that may lead to accelerated wearout of the devices. These hidden defects or hardware Trojans can be created by deviation from foundry design rules and processing parameters. The Trojans are produced by exploiting time-based wearing mechanisms (HCI, NBTI, TDDB and EM) and/or condition-based triggers (ESD, Latchup and Softerror). This class of latent damage is difficult to test due to its gradual degradation nature. The paper describes life-time expectancy results for various Trojan induced scenarios. Semiconductor properties, processing and design parameters critical for device reliability and Trojan creation are discussed.

  13. Commencement Bay Study. Volume III. Fish Wetlands.

    Science.gov (United States)

    1981-12-31

    area. Amish (1976) studied the occurrence of Philometra americana in English sole and rock sole of central Puget Sound. Amish’s sampling locations...Fisheries Biologist, Washington Department of Fisheries. Personal communication. Amish , R.A., 1976. The occurrence of the bloodworm Philometra americana...wildlife as well as the people of the Puyallup Nation who then inhabited the study area. Six major wetland habitat types have been recognized in the

  14. Design Options Study. Volume III. Qualitative Assessment.

    Science.gov (United States)

    1980-09-01

    would be obtained for a 500,000 lb- or 600,000 lb-payload- aircraft is uncertain. Assesment of De3ign-Option Substitutien TO summnarize the preceding...exhaust smoke and prohibit fuel venting to the atmosphere. In accordance with APR 80-36, as discussed previously in conjunction with the noise...Laboratory in terms of combustor efficiency, specific NO Xvalues, and specific levels Of Visible smoke . In the Most recent EPA proposals. emission

  15. Progress Report on Alzheimer Disease: Volume III.

    Science.gov (United States)

    National Inst. on Aging (DHHS/PHS), Bethesda, MD.

    This report summarizes advances in the understanding of Alzheimer's disease, the major cause of mental disability among older Americans. The demography of the disease is discussed, noting that approximately 2.5 million American adults are afflicted with the disease and that the large increase in the number of Alzheimer's disease patients is due to…

  16. Towboat Maneuvering Simulator. Volume III. Theoretical Description.

    Science.gov (United States)

    1979-05-01

    overshoot or :igzag maneuver;I - 1,2,3 .. . 6FL F- _’ Flan"ing rudder deflection rate a _ __ Steering rudder deflection rate Ship propulsion ratlol " elh...used with the equations are for the ship propulsion point (n - 1.0). The equations are written in terms of the complete barge flotillia towboat

  17. Great III - Cultural Resource Inventory. Volume 2

    Science.gov (United States)

    1982-05-01

    Historical Sketch of St. Louis University. Patrick Fox, • St. Louis. Historical look at the St. Louis mound complex. Holmes, Nathaniel 1868 Loess...Saint Louis to Me. St. Louis, Missouri: Hawthorn Pub- lishing Company, 1978. 305 p., illus. £ates, Giwendolyn Lewis 1976 Historic Sites Inventory for...Watercolors by Marilynne Bradley. St. Louis: Hawthorn Publishing Company, c. 1977. 259 p., illus. (part color). Includes: Old Courthouse, Old

  18. Hardware-Software Co-Simulation for SOC Functional Verification

    Institute of Scientific and Technical Information of China (English)

    YAN Ying-jian; LIU Ming-ye

    2005-01-01

    A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is described in C language provides the interface between the two. The bus interface model and the ISS are linked into a singleton program the software simulator, which communicate with the hardware simulator through Windows sockets. The implementation of the bus interface model and the synchronization between hardware and software simulator are discussed in detail. Co-simulation control of the hardware simulator is also discussed.

  19. Introduction to Hardware Security and Trust

    CERN Document Server

    Wang, Cliff

    2012-01-01

    The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g.,to act as a ‘kill switch’ to disable a chip, to integrated circuit (IC) piracy,and to attacks designed to extract encryption keys and IP from a chip. This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade.  Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.  This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of,and trust in, modern society�...

  20. Hardware simulator for photon correlation spectroscopy

    Science.gov (United States)

    Ferri, Fabio; Magatti, Davide

    2003-10-01

    We present a hardware simulator ideal for testing digital correlators in photon correlation spectroscopy. By using a PCI-6534 National Instrument I/O board, a personal computer (1.5 GHz Pentium 4), and an original algorithm developed in LabVIEW (National Instrument™), we realized an instrument capable of delivering a continuous stream of transistor-transistor logic pulses with the desired statistical properties over one or more channels. The pulse resolution could be set to values multiple of the clock period Δt=50 ns available on the board. When a single channel is used, the maximum count rate at Δt=50 ns was ˜350 kHz. With two channels we obtained ˜80 kHz at Δt=50 ns and ˜120 kHz at Δt=100 ns. Pulse streams with Gaussian statistics and in the presence of shot noise were simulated and measured with a commercial hardware correlator. Photodetector defects, such as the presence of afterpulses, were also simulated and their elimination by cross correlation techniques was checked. The simulator works also as a general purpose pulse pattern generator (PPG). Compared with commercial PPGs, our simulator is slower, but permits a continuous output of the pulse stream (not allowed in PPGs). At the same time it offers many other nontrivial advantages related to its flexibility, relatively low cost, and easy adaptability to future technology developments.

  1. ISS Logistics Hardware Disposition and Metrics Validation

    Science.gov (United States)

    Rogers, Toneka R.

    2010-01-01

    I was assigned to the Logistics Division of the International Space Station (ISS)/Spacecraft Processing Directorate. The Division consists of eight NASA engineers and specialists that oversee the logistics portion of the Checkout, Assembly, and Payload Processing Services (CAPPS) contract. Boeing, their sub-contractors and the Boeing Prime contract out of Johnson Space Center, provide the Integrated Logistics Support for the ISS activities at Kennedy Space Center. Essentially they ensure that spares are available to support flight hardware processing and the associated ground support equipment (GSE). Boeing maintains a Depot for electrical, mechanical and structural modifications and/or repair capability as required. My assigned task was to learn project management techniques utilized by NASA and its' contractors to provide an efficient and effective logistics support infrastructure to the ISS program. Within the Space Station Processing Facility (SSPF) I was exposed to Logistics support components, such as, the NASA Spacecraft Services Depot (NSSD) capabilities, Mission Processing tools, techniques and Warehouse support issues, required for integrating Space Station elements at the Kennedy Space Center. I also supported the identification of near-term ISS Hardware and Ground Support Equipment (GSE) candidates for excessing/disposition prior to October 2010; and the validation of several Logistics Metrics used by the contractor to measure logistics support effectiveness.

  2. ARM assembly language with hardware experiments

    CERN Document Server

    Elahi, Ata

    2015-01-01

    This book provides a hands-on approach to learning ARM assembly language with the use of a TI microcontroller. The book starts with an introduction to computer architecture and then discusses number systems and digital logic. The text covers ARM Assembly Language, ARM Cortex Architecture and its components, and Hardware Experiments using TILM3S1968. Written for those interested in learning embedded programming using an ARM Microcontroller. ·         Introduces number systems and signal transmission methods   ·         Reviews logic gates, registers, multiplexers, decoders and memory   ·         Provides an overview and examples of ARM instruction set   ·         Uses using Keil development tools for writing and debugging ARM assembly language Programs   ·         Hardware experiments using a Mbed NXP LPC1768 microcontroller; including General Purpose Input/Output (GPIO) configuration, real time clock configuration, binary input to 7-segment display, creating ...

  3. Movable Ground Based Recovery System for Reuseable Space Flight Hardware

    Science.gov (United States)

    Sarver, George L. (Inventor)

    2013-01-01

    A reusable space flight launch system is configured to eliminate complex descent and landing systems from the space flight hardware and move them to maneuverable ground based systems. Precision landing of the reusable space flight hardware is enabled using a simple, light weight aerodynamic device on board the flight hardware such as a parachute, and one or more translating ground based vehicles such as a hovercraft that include active speed, orientation and directional control. The ground based vehicle maneuvers itself into position beneath the descending flight hardware, matching its speed and direction and captures the flight hardware. The ground based vehicle will contain propulsion, command and GN&C functionality as well as space flight hardware landing cushioning and retaining hardware. The ground based vehicle propulsion system enables longitudinal and transverse maneuverability independent of its physical heading.

  4. Handbook of hardware/software codesign

    CERN Document Server

    Teich, Jürgen

    2017-01-01

    This handbook presents fundamental knowledge on the hardware/software (HW/SW) codesign methodology. Contributing expert authors look at key techniques in the design flow as well as selected codesign tools and design environments, building on basic knowledge to consider the latest techniques. The book enables readers to gain real benefits from the HW/SW codesign methodology through explanations and case studies which demonstrate its usefulness. Readers are invited to follow the progress of design techniques through this work, which assists readers in following current research directions and learning about state-of-the-art techniques. Students and researchers will appreciate the wide spectrum of subjects that belong to the design methodology from this handbook. .

  5. Locating hardware faults in a parallel computer

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  6. Current conveyors variants, applications and hardware implementations

    CERN Document Server

    Senani, Raj; Singh, A K

    2015-01-01

    This book serves as a single-source reference to Current Conveyors and their use in modern Analog Circuit Design. The authors describe the various types of current conveyors discovered over the past 45 years, details of all currently available, off-the-shelf integrated circuit current conveyors, and implementations of current conveyors using other, off-the-shelf IC building blocks. Coverage includes prominent bipolar/CMOS/Bi-CMOS architectures of current conveyors, as well as all varieties of starting from third generation current conveyors to universal current conveyors, their implementations and applications. •Describes all commercially available off-the-shelf IC current conveyors, as well as hardware implementations of current conveyors using other off-the-shelf ICs; • Describes numerous variants of current conveyors evolved over the past forty five years; • Describes a number of Bipolar/CMOS/Bi-CMOS architectures of current conveyors, along with their characteristic features; • Includes a comprehe...

  7. Extensible Hardware Architecture for Mobile Robots

    Science.gov (United States)

    Park, Eric; Kobayashi, Linda; Lee, Susan Y.

    2005-01-01

    The Intelligent Robotics Group at NASA Ames Research Center has developed a new mobile robot hardware architecture designed for extensibility and reconfigurability. Currently implemented on the k9 rover. and won to be integrated onto the K10 series of human-robot collaboration research robots, this architecture allows for rapid changes in instrumentation configuration and provides a high degree of modularity through a synergistic mix of off-the-shelf and custom designed components, allowing eased transplantation into a wide vane6 of mobile robot platforms. A component level overview of this architecture is presented along with a description of the changes required for implementation on K10 , followed by plans for future work.

  8. Compressive Sensing Image Sensors-Hardware Implementation

    Directory of Open Access Journals (Sweden)

    Shahram Shirani

    2013-04-01

    Full Text Available The compressive sensing (CS paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal–oxide–semiconductor technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed.

  9. Perspectives in Simulation Hardware and Software Architecture

    Directory of Open Access Journals (Sweden)

    W.O. Grierson

    1985-10-01

    Full Text Available Historically, analog and hybrid computer systems have provided effective real-time solutions for the simulation of large dynamic systems. In the mid 1970s, ADI concluded that these systems were no longer adequate to meet the demands of larger, more complex models and the demand for greater simulation accuracy. The decision was to design an all-digital system to satisfy these growing requirements (see Gilbert and Howe, (1978. This all-digital approach was called the SYSTEM 10. The SYSTEM 10 has been effective in solving time-critical simulation problems and in replacing the previous approach of utilizing hybrid computers. Recent advances in 100 K emitter coupled logic (ECL now make it possible to support a new generation of equipment that expands modeling capabilities to serve simulation needs. The hardware and software concepts of this system, called the SYSTEM 100, are the subject of this paper.

  10. Enabling Technologies for Improved Data Management: Hardware

    Directory of Open Access Journals (Sweden)

    Kerstin van Dam-Kleese

    2001-01-01

    Full Text Available The most valuable assets in every scientific community are the expert work force and the research results/data produced. The last decade has seen new experimental and computational techniques developing at an ever-faster pace, encouraging the production of ever-larger quantities of data in ever-shorter time spans. Concurrently the traditional scientific working environment has changed beyond recognition. Today scientists can use a wide spectrum of experimental, computational and analytical facilities, often widely distributed over the UK and Europe. In this environment new challenges are posed for the Management of Data every day, but are we ready to tackle them? Do we know exactly what the challenges are? Is the right technology available and is it applied where necessary? This part of enabling technologies investigates current hardware techniques and their functionalities and provides a comparison between various products.

  11. Protection of Accelerator Hardware: RF systems

    CERN Document Server

    Kim, S-H

    2016-01-01

    The radio-frequency (RF) system is the key element that generates electric fields for beam acceleration. To keep the system reliable, a highly sophisticated protection scheme is required, which also should be designed to ensure a good balance between beam availability and machine safety. Since RF systems are complex, incorporating high-voltage and high-power equipment, a good portion of machine downtime typically comes from RF systems. Equipment and component damage in RF systems results in long and expensive repairs. Protection of RF system hardware is one of the oldest machine protection concepts, dealing with the protection of individual high-power RF equipment from breakdowns. As beam power increases in modern accelerators, the protection of accelerating structures from beam-induced faults also becomes a critical aspect of protection schemes. In this article, an overview of the RF system is given, and selected topics of failure mechanisms and examples of protection requirements are introduced.

  12. Theorem Proving in Intel Hardware Design

    Science.gov (United States)

    O'Leary, John

    2009-01-01

    For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.

  13. Dual control vibration tests of flight hardware

    Science.gov (United States)

    Scharton, Terry D.

    1991-01-01

    A vibration retest of a spacecraft flight instrument, the Mars Observer Camera (MOC), was conducted using extremal dual control to automatically limit the shaker force and notch the shaker acceleration at resonances. This was the first application of extremal dual control with flight hardware at JPL. The retest was successful in that the environment was representative of flight plus some margin, the instrument survived without any structural or performance degradation, and the force limiting worked very well. The test set-up, force limiting procedure, and test results are described herein. It is concluded that dual control should be utilized when there is a concern about overtesting in hard-base-drive tests and the instrumentation for force measurement and control is available. Recommendations for improving the implementation of dual control are provided as a result of this first experience.

  14. Hardware implementation of stochastic spiking neural networks.

    Science.gov (United States)

    Rosselló, Josep L; Canals, Vincent; Morro, Antoni; Oliver, Antoni

    2012-08-01

    Spiking Neural Networks, the last generation of Artificial Neural Networks, are characterized by its bio-inspired nature and by a higher computational capacity with respect to other neural models. In real biological neurons, stochastic processes represent an important mechanism of neural behavior and are responsible of its special arithmetic capabilities. In this work we present a simple hardware implementation of spiking neurons that considers this probabilistic nature. The advantage of the proposed implementation is that it is fully digital and therefore can be massively implemented in Field Programmable Gate Arrays. The high computational capabilities of the proposed model are demonstrated by the study of both feed-forward and recurrent networks that are able to implement high-speed signal filtering and to solve complex systems of linear equations.

  15. Communication Estimation for Hardware/Software Codesign

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    This paper presents a general high level estimation model of communication throughput for the implementation of a given communication protocol. The model, which is part of a larger model that includes component price, software driver object code size and hardware driver area, is intended...... to be general enough to be able to capture the characteristics of a wide range of communication protocols and yet to be sufficiently detailed as to allow the designer or design tool to efficiently explore tradeoffs between throughput, bus widths, burst/non-burst transfers and data packing strategies. Thus...... it provides a basis for decision making with respect to communication protocols/components and communication driver design in the initial design space exploration phase of a co-synthesis process where a large number of possibilities must be examined and where fast estimators are therefore necessary. The fill...

  16. Rendering Falling Leaves on Graphics Hardware

    Directory of Open Access Journals (Sweden)

    Marcos Balsa

    2008-04-01

    Full Text Available There is a growing interest in simulating natural phenomena in computer graphics applications. Animating natural scenes in real time is one of the most challenging problems due to the inherent complexity of their structure, formed by millions of geometric entities, and the interactions that happen within. An example of natural scenario that is needed for games or simulation programs are forests. Forests are difficult to render because the huge amount of geometric entities and the large amount of detail to be represented. Moreover, the interactions between the objects (grass, leaves and external forces such as wind are complex to model. In this paper we concentrate in the rendering of falling leaves at low cost. We present a technique that exploits graphics hardware in order to render thousands of leaves with different falling paths in real time and low memory requirements.

  17. Application of hardwares in the process of training of skilled sportswomen

    Directory of Open Access Journals (Sweden)

    Kutek T.B.

    2013-10-01

    Full Text Available Purpose of work - to systematize information to scientifically-methodical literature and front-rank sporting practice about application of hardwares in the process of training of skilled sportswomen. Results. Some directions of application of hardwares are considered in track-and-field sport. The presented materials will be instrumental in intensification of process of training of skilled sportswomen. The prospects of further expansion of sphere of the use of hardwares are shown in track-and-field sport. Conclusions. It is marked that among the possible ways of development of method of training of skilled sportswomen all less than it is possible to hope on achievement of success, leaning only against further growth of volume and intensity of the training loading. With all by large attention trainers and representatives of sporting science will examine the prospects of the use of hardwares which provide moving toward higher trade. It is marked that for forming of proof motive skill creation of certain terms is needed for implementation of exercises. These terms must provide maximally possible probabilities for the effective achieving motive possibilities of sportswoman. Also, these terms must provide possibilities of process of implementation of exercises control on strengthening of skill which has large probability to reproducing in the attempt of desirable record result.

  18. Hardware Implementation of Lossless Adaptive and Scalable Hyperspectral Data Compression for Space

    Science.gov (United States)

    Aranki, Nazeeh; Keymeulen, Didier; Bakhshi, Alireza; Klimesh, Matthew

    2009-01-01

    On-board lossless hyperspectral data compression reduces data volume in order to meet NASA and DoD limited downlink capabilities. The technique also improves signature extraction, object recognition and feature classification capabilities by providing exact reconstructed data on constrained downlink resources. At JPL a novel, adaptive and predictive technique for lossless compression of hyperspectral data was recently developed. This technique uses an adaptive filtering method and achieves a combination of low complexity and compression effectiveness that far exceeds state-of-the-art techniques currently in use. The JPL-developed 'Fast Lossless' algorithm requires no training data or other specific information about the nature of the spectral bands for a fixed instrument dynamic range. It is of low computational complexity and thus well-suited for implementation in hardware. A modified form of the algorithm that is better suited for data from pushbroom instruments is generally appropriate for flight implementation. A scalable field programmable gate array (FPGA) hardware implementation was developed. The FPGA implementation achieves a throughput performance of 58 Msamples/sec, which can be increased to over 100 Msamples/sec in a parallel implementation that uses twice the hardware resources This paper describes the hardware implementation of the 'Modified Fast Lossless' compression algorithm on an FPGA. The FPGA implementation targets the current state-of-the-art FPGAs (Xilinx Virtex IV and V families) and compresses one sample every clock cycle to provide a fast and practical real-time solution for space applications.

  19. Tomo III

    OpenAIRE

    2015-01-01

    Memorias, histórico, físicas, crítico, apologéticas de la América Meridional con unas breves advertencias y noticias útiles, a los que de orden de Su Majestad, hubiesen de viajar y describir aquellas vastas regiones. Reino Animal. Tomo III. Por un anónimo americano en Cádiz por los años de 1757. Primera Parte Prólogo Artículo 1°De los cuadrúpedos útiles al hombre a varios usos y a su sustento. Vaca Caballos Carneros de la tierra, especie de camellos Vicuña Guanacos Puercos monteses Artículo 2...

  20. Hardware locks for a real-time Java chip multiprocessor

    DEFF Research Database (Denmark)

    Strøm, Torur Biskopstø; Puffitsch, Wolfgang; Schoeberl, Martin

    2016-01-01

    mechanisms are compared with a software locking solution as well as the original locking system of the processor. The hardware cost and performance are evaluated for all presented locking mechanisms. The performance of the better-performing hardware locks is comparable with that of the original single global...... lock when contending for the same lock. When several noncontending locks are used, the hardware locks enable true concurrency for critical sections. Benchmarks show that using the hardware locks yields performance ranging from no worse than the original locks to more than twice their best performance...... and may void a task set's schedulability. This paper presents 2 hardware locking mechanisms to reduce the worst-case time required to acquire and release synchronization locks. These solutions are implemented for the chip-multiprocessor version of the Java Optimized Processor. The 2 hardware locking...

  1. Expert System analysis of non-fuel assembly hardware and spent fuel disassembly hardware: Its generation and recommended disposal

    Energy Technology Data Exchange (ETDEWEB)

    Williamson, Douglas Alan [Univ. of Florida, Gainesville, FL (United States)

    1991-01-01

    Almost all of the effort being expended on radioactive waste disposal in the United States is being focused on the disposal of spent Nuclear Fuel, with little consideration for other areas that will have to be disposed of in the same facilities. one area of radioactive waste that has not been addressed adequately because it is considered a secondary part of the waste issue is the disposal of the various Non-Fuel Bearing Components of the reactor core. These hardware components fall somewhat arbitrarily into two categories: Non-Fuel Assembly (NFA) hardware and Spent Fuel Disassembly (SFD) hardware. This work provides a detailed examination of the generation and disposal of NFA hardware and SFD hardware by the nuclear utilities of the United States as it relates to the Civilian Radioactive Waste Management Program. All available sources of data on NFA and SFD hardware are analyzed with particular emphasis given to the Characteristics Data Base developed by Oak Ridge National Laboratory and the characterization work performed by Pacific Northwest Laboratories and Rochester Gas & Electric. An Expert System developed as a portion of this work is used to assist in the prediction of quantities of NFA hardware and SFD hardware that will be generated by the United States` utilities. Finally, the hardware waste management practices of the United Kingdom, France, Germany, Sweden, and Japan are studied for possible application to the disposal of domestic hardware wastes. As a result of this work, a general classification scheme for NFA and SFD hardware was developed. Only NFA and SFD hardware constructed of zircaloy and experiencing a burnup of less than 70,000 MWD/MTIHM and PWR control rods constructed of stainless steel are considered Low-Level Waste. All other hardware is classified as Greater-ThanClass-C waste.

  2. Hardware and software for prototyping industrial vision systems

    Science.gov (United States)

    Batchelor, Bruce G.; Daley, Michael W.; Griffiths, Eric C.

    1994-10-01

    A simple, low-cost device is described, which the authors have developed for prototyping industrial machine vision systems. The unit provides facilities for controlling the following devices, via a single serial (RS232) port, connected to a host computer: (a) Twelve ON/OFF mains devices (lamps, laser stripe generator, pattern projector, etc) (b) Four ON/OFF pneumatic valves (These are mounted on board the hardware module.) (c) One 8-way video multiplexor (d) Six programmable-speed serial (RS232) communication ports (e) Six opto- isolated 8-way parallel I/O ports. Using this unit, it is possible for software, running on the host computer and which contains only the most rudimentary I/O facilities, to operate a range of electro- mechanical devices. For example, a HyperCard program can switch lamps and pneumatic air lines ON/OFF, control the movements of an (X,Y,(theta) )-table and select different video cameras. These electro-mechanical devices form part of a flexible inspection cell, which the authors have built recently. This cell is being used to study the inspection of low-volume batch products, without the need for detailed instructions. The interface module has also been used to connect an image processing package, based on the Prolog programming language, to a gantry robot. This system plays dominoes against a human opponent.

  3. Graphics Gems III IBM version

    CERN Document Server

    Kirk, David

    1994-01-01

    This sequel to Graphics Gems (Academic Press, 1990), and Graphics Gems II (Academic Press, 1991) is a practical collection of computer graphics programming tools and techniques. Graphics Gems III contains a larger percentage of gems related to modeling and rendering, particularly lighting and shading. This new edition also covers image processing, numerical and programming techniques, modeling and transformations, 2D and 3D geometry and algorithms,ray tracing and radiosity, rendering, and more clever new tools and tricks for graphics programming. Volume III also includes a

  4. Exercise Countermeasure Hardware Evolution on ISS: The First Decade.

    Science.gov (United States)

    Korth, Deborah W

    2015-12-01

    The hardware systems necessary to support exercise countermeasures to the deconditioning associated with microgravity exposure have evolved and improved significantly during the first decade of the International Space Station (ISS), resulting in both new types of hardware and enhanced performance capabilities for initial hardware items. The original suite of countermeasure hardware supported the first crews to arrive on the ISS and the improved countermeasure system delivered in later missions continues to serve the astronauts today with increased efficacy. Due to aggressive hardware development schedules and constrained budgets, the initial approach was to identify existing spaceflight-certified exercise countermeasure equipment, when available, and modify it for use on the ISS. Program management encouraged the use of commercial-off-the-shelf (COTS) hardware, or hardware previously developed (heritage hardware) for the Space Shuttle Program. However, in many cases the resultant hardware did not meet the additional requirements necessary to support crew health maintenance during long-duration missions (3 to 12 mo) and anticipated future utilization activities in support of biomedical research. Hardware development was further complicated by performance requirements that were not fully defined at the outset and tended to evolve over the course of design and fabrication. Modifications, ranging from simple to extensive, were necessary to meet these evolving requirements in each case where heritage hardware was proposed. Heritage hardware was anticipated to be inherently reliable without the need for extensive ground testing, due to its prior positive history during operational spaceflight utilization. As a result, developmental budgets were typically insufficient and schedules were too constrained to permit long-term evaluation of dedicated ground-test units ("fleet leader" type testing) to identify reliability issues when applied to long-duration use. In most cases

  5. Architectural Support for Detection and Recovery using Hardware Wrappers

    Science.gov (United States)

    2013-04-01

    SECRYPT 2011, Seville, Spain 2011. 5. A. Baumgarten, M. Steffen, M. Clausman, and J. Zambreno. "A Case Study in Hardware Trojan Design and...AFRL-OSR-VA-TR-2013-0204 Architectural Support for Detection and Recovery using Hardware Wrappers Bhagirath Narahari Rahul...Include area code) 02-26-2013 FINAL REPORT March 1, 2009 - Nov 30, 2012 Architectural Support for Detection and Recovery using Hardware Wrappers

  6. Sequential (gemcitabine/vinorelbine and concurrent (gemcitabine radiochemotherapy with FDG-PET-based target volume definition in locally advanced non-small cell lung cancer: first results of a phase I/II study

    Directory of Open Access Journals (Sweden)

    Stanzel Sven

    2007-06-01

    Full Text Available Abstract Background The aim of the study was to determine the maximal tolerated dose (MTD of gemcitabine every two weeks concurrent to radiotherapy, administered during an aggressive program of sequential and simultaneous radiochemotherapy for locally advanced, unresectable non-small cell lung cancer (NSCLC and to evaluate the efficacy of this regime in a phase II study. Methods 33 patients with histologically confirmed NSCLC were enrolled in a combined radiochemotherapy protocol. 29 patients were assessable for evaluation of toxicity and tumor response. Treatment included two cycles of induction chemotherapy with gemcitabine (1200 mg/m2 and vinorelbine (30 mg/m2 at day 1, 8 and 22, 29 followed by concurrent radiotherapy (2.0 Gy/d; total dose 66.0 Gy and chemotherapy with gemcitabine every two weeks at day 43, 57 and 71. Radiotherapy planning included [18F] fluorodeoxyglucose positron emission tomography (FDG PET based target volume definition. 10 patients were included in the phase I study with an initial gemcitabine dose of 300 mg/m2. The dose of gemcitabine was increased in steps of 100 mg/m2 until the MTD was realized. Results MTD was defined for the patient group receiving gemcitabine 500 mg/m2 due to grade 2 (next to grade 3 esophagitis in all patients resulting in a mean body weight loss of 5 kg (SD = 1.4 kg, representing 8% of the initial weight. These patients showed persisting dysphagia 3 to 4 weeks after completing radiotherapy. In accordance with expected complications as esophagitis, dysphagia and odynophagia, we defined the MTD at this dose level, although no dose limiting toxicity (DLT grade 3 was reached. In the phase I/II median follow-up was 15.7 months (4.1 to 42.6 months. The overall response rate after completion of therapy was 64%. The median overall survival was 19.9 (95% CI: [10.1; 29.7] months for all eligible patients. The median disease-free survival for all patients was 8.7 (95% CI: [2.7; 14.6] months. Conclusion

  7. Environmental Friendly Coatings and Corrosion Prevention For Flight Hardware Project

    Science.gov (United States)

    Calle, Luz

    2014-01-01

    Identify, test and develop qualification criteria for environmentally friendly corrosion protective coatings and corrosion preventative compounds (CPC's) for flight hardware an ground support equipment.

  8. Hardware/Software Co-design using Primitive Interface

    Directory of Open Access Journals (Sweden)

    Navin Chourasia

    2011-08-01

    Full Text Available Most engineering designs can be viewed as systems, i.e., as collections of several components whose combined operation provides useful services. Components can be heterogeneous in nature and their interaction may be regulated by some simple or complex means. Interface between Hardware & Software plays a very important role in co-design of the embedded system. Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design. This paper shows how hardware & software interfaces can be implemented using primitive interface design

  9. Reliable software for unreliable hardware a cross layer perspective

    CERN Document Server

    Rehman, Semeen; Henkel, Jörg

    2016-01-01

    This book describes novel software concepts to increase reliability under user-defined constraints. The authors’ approach bridges, for the first time, the reliability gap between hardware and software. Readers will learn how to achieve increased soft error resilience on unreliable hardware, while exploiting the inherent error masking characteristics and error (stemming from soft errors, aging, and process variations) mitigations potential at different software layers. · Provides a comprehensive overview of reliability modeling and optimization techniques at different hardware and software levels; · Describes novel optimization techniques for software cross-layer reliability, targeting unreliable hardware.

  10. Advances in SPECT and PET Hardware.

    Science.gov (United States)

    Slomka, Piotr J; Pan, Tinsu; Berman, Daniel S; Germano, Guido

    2015-01-01

    There have been significant recent advances in single photon emission computed tomography (SPECT) and positron emission tomography (PET) hardware. Novel collimator designs, such as multi-pinhole and locally focusing collimators arranged in geometries that are optimized for cardiac imaging have been implemented to reduce imaging time and radiation dose. These new collimators have been coupled with solid state photon detectors to further improve image quality and reduce scanner size. The new SPECT scanners demonstrate up to a 7-fold increase in photon sensitivity and up to 2 times improvement in image resolution. Although PET scanners are used primarily for oncological imaging, cardiac imaging can benefit from the improved PET sensitivity of 3D systems without inter-plane septa and implementation of the time-of-flight reconstruction. Additionally, resolution recovery techniques are now implemented by all major PET vendors. These new methods improve image contrast, image resolution, and reduce image noise. Simultaneous PET/magnetic resonance (MR) hybrid systems have been developed. Solid state detectors with avalanche photodiodes or digital silicon photomultipliers have also been utilized in PET. These new detectors allow improved image resolution, higher count rate, as well as a reduced sensitivity to electromagnetic MR fields. Copyright © 2015. Published by Elsevier Inc.

  11. Nanorobot Hardware Architecture for Medical Defense

    Science.gov (United States)

    Cavalcanti, Adriano; Shirinzadeh, Bijan; Zhang, Mingjun; Kretly, Luiz C.

    2008-01-01

    This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease. PMID:27879858

  12. Fast Sparse Level Sets on Graphics Hardware.

    Science.gov (United States)

    Jalba, Andrei C; van der Laan, Wladimir J; Roerdink, Jos B T M

    2013-01-01

    The level-set method is one of the most popular techniques for capturing and tracking deformable interfaces. Although level sets have demonstrated great potential in visualization and computer graphics applications, such as surface editing and physically based modeling, their use for interactive simulations has been limited due to the high computational demands involved. In this paper, we address this computational challenge by leveraging the increased computing power of graphics processors, to achieve fast simulations based on level sets. Our efficient, sparse GPU level-set method is substantially faster than other state-of-the-art, parallel approaches on both CPU and GPU hardware. We further investigate its performance through a method for surface reconstruction, based on GPU level sets. Our novel multiresolution method for surface reconstruction from unorganized point clouds compares favorably with recent, existing techniques and other parallel implementations. Finally, we point out that both level-set computations and rendering of level-set surfaces can be performed at interactive rates, even on large volumetric grids. Therefore, many applications based on level sets can benefit from our sparse level-set method.

  13. Nanorobot Hardware Architecture for Medical Defense

    Directory of Open Access Journals (Sweden)

    Luiz C. Kretly

    2008-05-01

    Full Text Available This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease.

  14. Nanorobot Hardware Architecture for Medical Defense.

    Science.gov (United States)

    Cavalcanti, Adriano; Shirinzadeh, Bijan; Zhang, Mingjun; Kretly, Luiz C

    2008-05-06

    This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease.

  15. Live HDR video streaming on commodity hardware

    Science.gov (United States)

    McNamee, Joshua; Hatchett, Jonathan; Debattista, Kurt; Chalmers, Alan

    2015-09-01

    High Dynamic Range (HDR) video provides a step change in viewing experience, for example the ability to clearly see the soccer ball when it is kicked from the shadow of the stadium into sunshine. To achieve the full potential of HDR video, so-called true HDR, it is crucial that all the dynamic range that was captured is delivered to the display device and tone mapping is confined only to the display. Furthermore, to ensure widespread uptake of HDR imaging, it should be low cost and available on commodity hardware. This paper describes an end-to-end HDR pipeline for capturing, encoding and streaming high-definition HDR video in real-time using off-the-shelf components. All the lighting that is captured by HDR-enabled consumer cameras is delivered via the pipeline to any display, including HDR displays and even mobile devices with minimum latency. The system thus provides an integrated HDR video pipeline that includes everything from capture to post-production, archival and storage, compression, transmission, and display.

  16. Hardware upgrade for A2 data acquisition

    Energy Technology Data Exchange (ETDEWEB)

    Ostrick, Michael; Gradl, Wolfgang; Otte, Peter-Bernd; Neiser, Andreas; Steffen, Oliver; Wolfes, Martin; Koerner, Tito [Institut fuer Kernphysik, Mainz (Germany); Collaboration: A2-Collaboration

    2014-07-01

    The A2 Collaboration uses an energy tagged photon beam which is produced via bremsstrahlung off the MAMI electron beam. The detector system consists of Crystal Ball and TAPS and covers almost the whole solid angle. A frozen-spin polarized target allows to perform high precision measurements of polarization observables in meson photo-production. During the last summer, a major upgrade of the data acquisition system was performed, both on the hardware and the software side. The goal of this upgrade was increased reliability of the system and an improvement in the data rate to disk. By doubling the number of readout CPUs and employing special VME crates with a split backplane, the number of bus accesses per readout cycle and crate was cut by a factor of two, giving almost a factor of two gain in the readout rate. In the course of the upgrade, we also switched most of the detector control system to using the distributed control system EPICS. For the upgraded control system, some new tools were developed to make full use of the capabilities of this decentralised slow control and monitoring system. The poster presents some of the major contributions to this project.

  17. Open Hardware For CERN's Accelerator Control Systems

    CERN Document Server

    van der Bij, E; Ayass, M; Boccardi, A; Cattin, M; Gil Soriano, C; Gousiou, E; Iglesias Gonsálvez, S; Penacoba Fernandez, G; Serrano, J; Voumard, N; Wlostowski, T

    2011-01-01

    The accelerator control systems at CERN will be renovated and many electronics modules will be redesigned as the modules they will replace cannot be bought anymore or use obsolete components. The modules used in the control systems are diverse: analog and digital I/O, level converters and repeaters, serial links and timing modules. Overall around 120 modules are supported that are used in systems such as beam instrumentation, cryogenics and power converters. Only a small percentage of the currently used modules are commercially available, while most of them had been specifically designed at CERN. The new developments are based on VITA and PCI-SIG standards such as FMC (FPGA Mezzanine Card), PCI Express and VME64x using transition modules. As system-on-chip interconnect, the public domain Wishbone specification is used. For the renovation, it is considered imperative to have for each board access to the full hardware design and its firmware so that problems could quickly be resolved by CERN engineers or its ...

  18. Exposure Render: An Interactive Photo-Realistic Volume Rendering Framework

    NARCIS (Netherlands)

    Kroes, T.; Post, F.H.; Botha, C.P.

    2012-01-01

    The field of volume visualization has undergone rapid development during the past years, both due to advances in suitable computing hardware and due to the increasing availability of large volume datasets. Recent work has focused on increasing the visual realism in Direct Volume Rendering (DVR) by i

  19. Ultrasound and clinical evaluation of soft-tissue versus hardware biceps tenodesis: is hardware tenodesis worth the cost?

    Science.gov (United States)

    Elkousy, Hussein; Romero, Jose A; Edwards, T Bradley; Gartsman, Gary M; O'Connor, Daniel P

    2014-02-01

    This study assesses the failure rate of soft-tissue versus hardware fixation of biceps tenodesis by ultrasound to determine if the expense of a hardware tenodesis technique is warranted. Seventy-two patients that underwent arthroscopic biceps tenodesis over a 3-year period were evaluated using postoperative ultrasonography and clinical examination. The tenodesis technique employed was either a soft-tissue technique with sutures or an interference screw technique using hardware based on surgeon preference. Patient age was 57.9 years on average with ultrasound and clinical examination done at an average of 9.3 months postoperatively. Thirty-one patients had a hardware technique and 41 a soft-tissue technique. Overall, 67.7% of biceps tenodesis done with hardware were intact, compared with 75.6% for the soft-tissue technique by ultrasound (P = .46). Clinical evaluation indicated that 80.7% of hardware techniques and 78% of soft-tissue techniques were intact. Average material cost to the hospital for the hardware technique was $514.32, compared with $32.05 for the soft-tissue technique. Biceps tenodesis success, as determined by clinical deformity and ultrasound, was not improved using hardware as compared to soft-tissue techniques. Soft-tissue techniques are equally efficacious and more cost effective than hardware techniques.

  20. Neutron Imaging for Selective Laser Melting Inconel Hardware with Internal Passages

    Science.gov (United States)

    Tramel, Terri L.; Norwood, Joseph K.; Bilheux, Hassina

    2014-01-01

    Additive Manufacturing is showing great promise for the development of new innovative designs and large potential life cycle cost reduction for the Aerospace Industry. However, more development work is required to move this technology into space flight hardware production. With selective laser melting (SLM), hardware that once consisted of multiple, carefully machined and inspected pieces, joined together can be made in one part. However standard inspection techniques cannot be used to verify that the internal passages are within dimensional tolerances or surface finish requirements. NASA/MSFC traveled to Oak Ridge National Lab's (ORNL) Spallation Neutron Source to perform some non-destructive, proof of concept imaging measurements to assess the capabilities to understand internal dimensional tolerances and internal passages surface roughness. This presentation will describe 1) the goals of this proof of concept testing, 2) the lessons learned when designing and building these Inconel 718 test specimens to minimize beam time, 3) the neutron imaging test setup and test procedure to get the images, 4) the initial results in images, volume and a video, 4) the assessment of using this imaging technique to gather real data for designing internal flow passages in SLM manufacturing aerospace hardware, and lastly 5) how proper cleaning of the internal passages is critically important. In summary, the initial results are very promising and continued development of a technique to assist in SLM development for aerospace components is desired by both NASA and ORNL. A plan forward that benefits both ORNL and NASA will also be presented, based on the promising initial results. The initial images and volume reconstruction showed that clean, clear images of the internal passages geometry are obtainable. These clear images of the internal passages of simple geometries will be compared to the build model to determine any differences. One surprising result was that a new cleaning

  1. Design of a Data Storage Hierarchy. DSH-III--Software & Hardware.

    Science.gov (United States)

    1986-03-01

    Mlanagement Systems (DBPIS’s) are caoable of handling data bases on the order of a trillion (1012) bits of data, and can porocess transactions at rates of...level extracting the appropriate sub-page from the broadcast data. This strategy is called READ-THROUGH since the requested data is read through from...to all higher levels of the hierarchy. Section 3 describes the architecture which allows the destination levels to extract appropriate sub-pages from

  2. Hardware packet pacing using a DMA in a parallel computer

    Science.gov (United States)

    Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

    2013-08-13

    Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

  3. Teaching Robotics Software with the Open Hardware Mobile Manipulator

    Science.gov (United States)

    Vona, M.; Shekar, N. H.

    2013-01-01

    The "open hardware mobile manipulator" (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and…

  4. Videodisc Levels: A Case Study in Hardware Obsession.

    Science.gov (United States)

    Hofmeister, Alan M.; Thorkildsen, Ron J.

    1989-01-01

    The article reviews a 10-year history of research on videodisc programs with handicapped and nonhandicapped students. A trend from hardware-intensive programs concerned with physical individualization and self-pacing to more modest hardware involvement and a greater attention to the teacher's role in both group and individual instructional…

  5. Teaching Robotics Software with the Open Hardware Mobile Manipulator

    Science.gov (United States)

    Vona, M.; Shekar, N. H.

    2013-01-01

    The "open hardware mobile manipulator" (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and…

  6. Runtime task mapping based on hardware configuration reuse

    NARCIS (Netherlands)

    Sigdel, K.; Galuzzi, C.; Bertels, K.; Thompson, M.; Pimentel, A.D.; Prasanna, V.; Becker, J.; Cumplido, R.

    2010-01-01

    In this paper, we propose a new heuristic for runtime task mapping of application(s) onto reconfigurable architectures. The heuristic is based on hardware configuration reuse, which tries to avoid the reconfiguration overhead of few selected tasks, by reusing the hardware configurations already avai

  7. Reducing the overheads of hardware acceleration through datapath integration

    Science.gov (United States)

    Jääskeläinen, Pekka; Kultala, Heikki; Pitkänen, Teemu; Takala, Jarmo

    2008-02-01

    Hardware accelerators are used to speed up execution of specific tasks such as video coding. Often the purpose of hardware acceleration is to be able to use a cheaper or, for example, more energy economical processor for executing the majority of the application in software. However, when using hardware acceleration, new overheads are produced mainly due to the need to transfer data to and from the accelerator and signaling the readiness of the accelerator computation to the processor. We find the traditional mechanisms suboptimal for fine-grain hardware acceleration, especially when energy efficiency is important. This paper explores a technique unique to Transport Triggered Architectures to interface with hardware accelerators. The proposed technique places hardware accelerators to the processor data path, making them visible as regular function units to the programmer. This way communication costs are reduced as data can be transferred directly to the accelerator from other processor data path components and synchronization can be done by polling a simple ready flag in the accelerator function unit. Additionally, this setup enables the instruction scheduler of the compiler to schedule the hardware accelerator like any other operation, thus partially hide its latency with other program operations. The paper presents a case study with an audio decoder application in which fine-grain and coarse-grain hardware accelerators are integrated to the processor data path as function units. The case is used to study several different synchronization, communication, and latency-hiding techniques enabled by this kind of setup.

  8. [Hardware and software for X-ray therapy planning].

    Science.gov (United States)

    Zhizniakov, A L; Semenov, S I; Sushkova, L T; Troitskii, D P; Chirkov, K V

    2007-01-01

    Hardware, circuitry, and software suggested in this work make it possible to use the SLS-9 X-ray simulator for classical and computer tomographic imaging. The suggested hardware and software can be used as a basis for designing special-purpose tomographic systems.

  9. Zooplankton biomass (displacement volume) data collected in North Atlantic during ICNAF NORWESTLANT projects I-III in 1963 by different countries, data were acquired from the NMFS-COPEPOD database (NODC Accession 0070201)

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — Zooplankton biomass data (displacement volume) collected in North Atlantic during ICNAF (International Convention for the Northwest Atlantic Fisheries) NORWESTLANT...

  10. Zooplankton biomass (displacement and settled volume) data collected during the International Cooperative Investigations of the Tropical Atlantic EQUALANT I, EQUALANT II, and EQUALANT III projects from 1963-02-15 to 1964-07-09 (NODC Accession 0071432)

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — Zooplankton biomass (displacement and settled volume) data collected during the International Cooperative Investigations of the Tropical Atlantic EQUALANT I,...

  11. Mechatronic systems and materials III

    CERN Document Server

    Gosiewski, Zdzislaw

    2009-01-01

    This very interesting volume is divided into 24 sections; each of which covers, in detail, one aspect of the subject-matter: I. Industrial robots; II. Microrobotics; III. Mobile robots; IV. Teleoperation, telerobotics, teleoperated semi-autonomous systems; V. Sensors and actuators in mechatronics; VI. Control of mechatronic systems; VII. Analysis of vibration and deformation; VIII. Optimization, optimal design; IX. Integrated diagnostics; X. Failure analysis; XI. Tribology in mechatronic systems; XII. Analysis of signals; XIII. Measurement techniques; XIV. Multifunctional and smart materials;

  12. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  13. A Practical Introduction to HardwareSoftware Codesign

    CERN Document Server

    Schaumont, Patrick R

    2013-01-01

    This textbook provides an introduction to embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which make the material applicable to a greater number of courses where these tools are already in use.  Mo...

  14. Structural Analysis of Furniture Hardware Industry in Turkey

    Directory of Open Access Journals (Sweden)

    Tuncer Dilik

    2005-01-01

    Full Text Available Furniture hardware plays an important role in the appearance, comfort and function of the furniture. In this study, Turkish furniture hardware companies were examined for their technical and economical characteristics, production materials, standards and surface treating methods, legal structures as well as foreign and domestic trade policies. Altogether, 67 companies accounting for 80% of the hardware production were examined. In addition, imported hardware brands, foreign trade companies and their representatives in Turkey were listed along with their production statistics and export sales by product groups for the years 1996-2000. It is found that the Turkish furniture hardware industry lacks vision and mission. Recommendations were made for sustained industry growth and for becoming competitive in international market.

  15. Hardware efficient monitoring of input/output signals

    Science.gov (United States)

    Driscoll, Kevin R. (Inventor); Hall, Brendan (Inventor); Paulitsch, Michael (Inventor)

    2012-01-01

    A communication device comprises first and second circuits to implement a plurality of ports via which the communicative device is operable to communicate over a plurality of communication channels. For each of the plurality of ports, the communication device comprises: command hardware that includes a first transmitter to transmit data over a respective one of the plurality of channels and a first receiver to receive data from the respective one of the plurality of channels; and monitor hardware that includes a second receiver coupled to the first transmitter and a third receiver coupled to the respective one of the plurality of channels. The first circuit comprises the command hardware for a first subset of the plurality of ports. The second circuit comprises the monitor hardware for the first subset of the plurality of ports and the command hardware for a second subset of the plurality of ports.

  16. Advanced Programming Platform for efficient use of Data Parallel Hardware

    CERN Document Server

    Cabellos, Luis

    2012-01-01

    Graphics processing units (GPU) had evolved from a specialized hardware capable to render high quality graphics in games to a commodity hardware for effective processing blocks of data in a parallel schema. This evolution is particularly interesting for scientific groups, which traditionally use mainly CPU as a work horse, and now can profit of the arrival of GPU hardware to HPC clusters. This new GPU hardware promises a boost in peak performance, but it is not trivial to use. In this article a programming platform designed to promote a direct use of this specialized hardware is presented. This platform includes a visual editor of parallel data flows and it is oriented to the execution in distributed clusters with GPUs. Examples of application in two characteristic problems, Fast Fourier Transform and Image Compression, are also shown.

  17. Hardware Development Process for Human Research Facility Applications

    Science.gov (United States)

    Bauer, Liz

    2000-01-01

    The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. The source of hardware requirements is the science community and HRF program. The HRF Science Working Group, consisting of SCientists from various medical disciplines, defined a basic set of equipment with functional requirements. This established the performance requirements of the hardware. HRF program requirements focus on making the hardware safe and operational in a space environment. This includes structural, thermal, human factors, and material requirements. Science and HRF program requirements are defined in a hardware requirements document which includes verification methods. Once the hardware is fabricated, requirements are verified by inspection, test, analysis, or demonstration. All data is compiled and reviewed to certify the hardware for flight. Obviously, the basis for all hardware development activities is requirement definition. Full and complete requirement definition is ideal prior to initiating the hardware development. However, this is generally not the case, but the hardware team typically has functional inputs as a guide. The first step is for engineers to conduct market research based on the functional inputs provided by scientists. CommerCially available products are evaluated against the science requirements as

  18. Nova como sistema operativo embebido para hardware cubano Nova as embedded operating system for cuban hardware

    Directory of Open Access Journals (Sweden)

    José Ernesto Torres Sánchez

    2012-05-01

    Full Text Available Este trabajo expone los resultados de construir un sistema operativo embebido basado en Nova, el cual brinda las funcionalidades necesarias para crear el Cliente Ligero Cubano, utilizando como componente de hardware, la Computadora en una Tarjeta CID 300/9 diseñada por el Instituto Central de Investigación Digital. Obteniéndose la primera versión de Nova para la arquitectura de computadora Advanced RISC Machine y el primer sistema operativo base, estable y de propósito general para la CID 300/9. Se expone un estado del arte de los sistemas operativos embebidos más utilizados actualmente; la estructura de la solución, los métodos y herramientas empleados para obtenerla.This paper presents the results of the construction a an embedded operating system based on Nova, which provides the needed features to create the Cuban Thin Client, using as hardware component the Computer on a CID 300/9 Board designed by the Central Institute for Digital Research, obtaining the first version of Nova for the Advance RISC Machine  computer architecture and the first base operating system, stable and for general purposes for the CID 300/9. A state of the art of the currently most used embedded operating systems, the solution's structure, the methods and tools used for its development are presented.

  19. Nova as embedded operating system for cuban hardware Nova como sistema operativo embebido para hardware cubano

    Directory of Open Access Journals (Sweden)

    Mijail Hurtado Fedorovich

    2012-05-01

    Full Text Available This paper presents the results of the construction a an embedded operating system based on Nova, which provides the needed features to create the Cuban Thin Client, using as hardware component the Computer on a CID 300/9 Board designed by the Central Institute for Digital Research, obtaining the first version of Nova for the Advance RISC Machine  computer architecture and the first base operating system, stable and for general purposes for the CID 300/9. A state of the art of the currently most used embedded operating systems, the solution's structure, the methods and tools used for its development are presented. Este trabajo expone los resultados de construir un sistema operativo embebido basado en Nova, el cual brinda las funcionalidades necesarias para crear el Cliente Ligero Cubano, utilizando como componente de hardware, la Computadora en una Tarjeta CID 300/9 diseñada por el Instituto Central de Investigación Digital. Obteniéndose la primera versión de Nova para la arquitectura de computadora Advanced RISC Machine y el primer sistema operativo base, estable y de propósito general para la CID 300/9. Se expone un estado del arte de los sistemas operativos embebidos más utilizados actualmente; la estructura de la solución, los métodos y herramientas empleados para obtenerla.

  20. Memoir and Scientific Correspondence of the Late Sir George Gabriel Stokes, Bart. 2 Volume Paperback Set

    Science.gov (United States)

    Stokes, George Gabriel; Larmor, Joseph

    2010-06-01

    Volume 1: Preface; Part I. Personal and Biographical; Part II. General Scientific Career; Part IIIa. Special Scientific Correspondence; Appendix; Index. Volume 2: Part. III. Special Scientific Correspondence; Index.

  1. Monitoring Particulate Matter with Commodity Hardware

    Science.gov (United States)

    Holstius, David

    Health effects attributed to outdoor fine particulate matter (PM 2.5) rank it among the risk factors with the highest health burdens in the world, annually accounting for over 3.2 million premature deaths and over 76 million lost disability-adjusted life years. Existing PM2.5 monitoring infrastructure cannot, however, be used to resolve variations in ambient PM2.5 concentrations with adequate spatial and temporal density, or with adequate coverage of human time-activity patterns, such that the needs of modern exposure science and control can be met. Small, inexpensive, and portable devices, relying on newly available off-the-shelf sensors, may facilitate the creation of PM2.5 datasets with improved resolution and coverage, especially if many such devices can be deployed concurrently with low system cost. Datasets generated with such technology could be used to overcome many important problems associated with exposure misclassification in air pollution epidemiology. Chapter 2 presents an epidemiological study of PM2.5 that used data from ambient monitoring stations in the Los Angeles basin to observe a decrease of 6.1 g (95% CI: 3.5, 8.7) in population mean birthweight following in utero exposure to the Southern California wildfires of 2003, but was otherwise limited by the sparsity of the empirical basis for exposure assessment. Chapter 3 demonstrates technical potential for remedying PM2.5 monitoring deficiencies, beginning with the generation of low-cost yet useful estimates of hourly and daily PM2.5 concentrations at a regulatory monitoring site. The context (an urban neighborhood proximate to a major goods-movement corridor) and the method (an off-the-shelf sensor costing approximately USD $10, combined with other low-cost, open-source, readily available hardware) were selected to have special significance among researchers and practitioners affiliated with contemporary communities of practice in public health and citizen science. As operationalized by

  2. Hardware performance of a scanning system for high speed analysis of nuclear emulsions

    CERN Document Server

    Arrabito, L; Bozza, C; Buontempo, S; Consiglio, L; Coppola, D; Cozzi, M; Damet, J; D'Ambrosio, N; De Lellis, G; De Serio, M; Capua, F D; Ferdinando, D D; Marco, N D; Esposito, L S; Giacomelli, G; Grella, G; Hauger, M; Juget, F; Kreslo, I; Giorgini, M; Ieva, M; Laktineh, I; Manai, K; Mandrioli, G; Marotta, A; Manzoor, S; Migliozzi, P; Monacelli, P; Muciaccia, M T; Pastore, A; Patrizii, L; Pistillo, C; Pozzato, M; Royole-Degieux, P; Romano, G; Rosa, G; Savvinov, N; Schembri, A; Lavina, L S; Simone, S; Sioli, M; Sirignano, C; Sirri, G; Sorrentino, G; Strolin, P; Tioukov, V; Waelchli, T

    2006-01-01

    The use of nuclear emulsions in very large physics experiments is now possible thanks to the recent improvements in the industrial production of emulsions and to the development of fast automated microscopes. In this paper the hardware performances of the European Scanning System (ESS) are described. The ESS is a very fast automatic system developed for the mass scanning of the emulsions of the OPERA experiment, which requires microscopes with scanning speeds of about 20 cm^2/h in an emulsion volume of 44 micron thickness.

  3. Targeting multiple heterogeneous hardware platforms with OpenCL

    Science.gov (United States)

    Fox, Paul A.; Kozacik, Stephen T.; Humphrey, John R.; Paolini, Aaron; Kuller, Aryeh; Kelmelis, Eric J.

    2014-06-01

    The OpenCL API allows for the abstract expression of parallel, heterogeneous computing, but hardware implementations have substantial implementation differences. The abstractions provided by the OpenCL API are often insufficiently high-level to conceal differences in hardware architecture. Additionally, implementations often do not take advantage of potential performance gains from certain features due to hardware limitations and other factors. These factors make it challenging to produce code that is portable in practice, resulting in much OpenCL code being duplicated for each hardware platform being targeted. This duplication of effort offsets the principal advantage of OpenCL: portability. The use of certain coding practices can mitigate this problem, allowing a common code base to be adapted to perform well across a wide range of hardware platforms. To this end, we explore some general practices for producing performant code that are effective across platforms. Additionally, we explore some ways of modularizing code to enable optional optimizations that take advantage of hardware-specific characteristics. The minimum requirement for portability implies avoiding the use of OpenCL features that are optional, not widely implemented, poorly implemented, or missing in major implementations. Exposing multiple levels of parallelism allows hardware to take advantage of the types of parallelism it supports, from the task level down to explicit vector operations. Static optimizations and branch elimination in device code help the platform compiler to effectively optimize programs. Modularization of some code is important to allow operations to be chosen for performance on target hardware. Optional subroutines exploiting explicit memory locality allow for different memory hierarchies to be exploited for maximum performance. The C preprocessor and JIT compilation using the OpenCL runtime can be used to enable some of these techniques, as well as to factor in hardware

  4. Data collection system. Volume 1, Overview and operators manual; Volume 2, Maintenance manual; Appendices

    Energy Technology Data Exchange (ETDEWEB)

    Caudell, R.B.; Bauder, M.E.; Boyer, W.B.; French, R.E.; Isidoro, R.J.; Kaestner, P.C.; Perkins, W.G.

    1993-09-01

    Sandia National Laboratories (SNL) Instrumentation Development Department was tasked by the Defense Nuclear Agency (DNA) to record data on Tektronix RTD720 Digitizers on the HUNTERS TROPHY field test conducted at the Nevada Test Site (NTS) on September 18, 1992. This report contains a overview and description of the computer hardware and software that was used to acquire, reduce, and display the data. The document is divided into two volumes: an overview and operators manual (Volume 1) and a maintenance manual (Volume 2).

  5. A researching of the process of binding software to hardware

    OpenAIRE

    Piletskaia, A. Yu.; Kobenko, Yury Viktorovich

    2016-01-01

    Information security is one of the most important sphere in Cybernetics. And for Russia this problem is state-of-the-art because of the wide-spread internet piracy and a huge number of hackers. This article explores the commonest ways to protect software using binding to hardware, with a focus on the main approaches to a collection of data from hardware and ways of data processing. As a possible method of solution it is accepted to collect data from main parts of hardware using .Net Framework...

  6. Hardware implementation of an electrostatic MEMS-actuator linearization

    Science.gov (United States)

    Mair, F.; Egretzberger, M.; Kugi, A.

    2011-06-01

    In this paper, an electrostatic actuator linearization will be introduced, which is based on an existing hardware-efficient iterative square root algorithm. The algorithm is solely based on add and shift operations while just needing n/2 iterations for an n bit wide input signal. As a practical example, the nonlinear input transformation will be utilized for the design of the primary mode controller of a capacitive MEMS gyroscope and an implementation of the algorithm in the Verilog hardware description language will be instantiated. Finally, measurement results will validate the feasibility of the presented control concept and its hardware implementation.

  7. Hardware support for collecting performance counters directly to memory

    Science.gov (United States)

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

    2012-09-25

    Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

  8. Hardware based segmentation in iris recognition and authentication systems

    Science.gov (United States)

    Ulis, Bradley J.; Broussard, Randy P.; Rakvic, Ryan N.; Ives, Robert W.; Steiner, Neil; Ngo, Hau

    2009-05-01

    Iris recognition algorithms depend on image processing techniques for proper segmentation of the iris. In the Ridge Energy Direction (RED) iris recognition algorithm, the initial step in the segmentation process searches for the pupil by thresholding and using binary morphology functions to rectify artifacts obfuscating the pupil. These functions take substantial processing time in software on the order of a few hundred million operations. Alternatively, a hardware version of the binary morphology functions is implemented to assist in the segmentation process. The hardware binary morphology functions have negligible hardware footprint and power consumption while achieving speed up of 200 times compared to the original software functions.

  9. Aspects of system modelling in Hardware/Software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    This paper addresses fundamental aspects of system modelling and partitioning algorithms in the area of Hardware/Software Codesign. Three basic system models for partitioning are presented and the consequences of partitioning according to each of these are analyzed. The analysis shows...... the importance of making a clear distinction between the model used for partitioning and the model used for evaluation It also illustrates the importance of having a realistic hardware model such that hardware sharing can be taken into account. Finally, the importance of integrating scheduling and allocation...

  10. Hardware Realization of Chaos Based Symmetric Image Encryption

    KAUST Repository

    Barakat, Mohamed L.

    2012-06-01

    This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.

  11. Hardware Implementation of Serially Concatenated PPM Decoder

    Science.gov (United States)

    Moision, Bruce; Hamkins, Jon; Barsoum, Maged; Cheng, Michael; Nakashima, Michael

    2009-01-01

    A prototype decoder for a serially concatenated pulse position modulation (SCPPM) code has been implemented in a field-programmable gate array (FPGA). At the time of this reporting, this is the first known hardware SCPPM decoder. The SCPPM coding scheme, conceived for free-space optical communications with both deep-space and terrestrial applications in mind, is an improvement of several dB over the conventional Reed-Solomon PPM scheme. The design of the FPGA SCPPM decoder is based on a turbo decoding algorithm that requires relatively low computational complexity while delivering error-rate performance within approximately 1 dB of channel capacity. The SCPPM encoder consists of an outer convolutional encoder, an interleaver, an accumulator, and an inner modulation encoder (more precisely, a mapping of bits to PPM symbols). Each code is describable by a trellis (a finite directed graph). The SCPPM decoder consists of an inner soft-in-soft-out (SISO) module, a de-interleaver, an outer SISO module, and an interleaver connected in a loop (see figure). Each SISO module applies the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to compute a-posteriori bit log-likelihood ratios (LLRs) from apriori LLRs by traversing the code trellis in forward and backward directions. The SISO modules iteratively refine the LLRs by passing the estimates between one another much like the working of a turbine engine. Extrinsic information (the difference between the a-posteriori and a-priori LLRs) is exchanged rather than the a-posteriori LLRs to minimize undesired feedback. All computations are performed in the logarithmic domain, wherein multiplications are translated into additions, thereby reducing complexity and sensitivity to fixed-point implementation roundoff errors. To lower the required memory for storing channel likelihood data and the amounts of data transfer between the decoder and the receiver, one can discard the majority of channel likelihoods, using only the remainder in

  12. Culture of Schools. Final Report. Volume IV.

    Science.gov (United States)

    American Anthropological Association, Washington, DC.

    The final volume of this 4-volume report contains further selections from "Anthropological Perspectives on Education," a monograph to be published by Basic Books of New York. (Other selections are in Vol. III, SP 003 902.) Monograph selections appearing in this volume are: "Great Tradition, Little Tradition, and Formal Education;""Indians,…

  13. Hardware acceleration of EDA algorithms custom ICS, FPGAs and GPUs

    CERN Document Server

    Khatri, Sunil P

    2010-01-01

    This text covers the acceleration of EDA algorithms using hardware platforms such as FPGAs and GPUs. In it, widely applied CAD algorithms are evaluated and compared for potential acceleration on FPGAs and GPUs.

  14. New Model and Algorithm for Hardware/Software Partitioning

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan; Guang-Wei Zou

    2008-01-01

    This paper focuses on the algorithmic aspects for the hardware/software (HW/SW) partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O(n. A) for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.

  15. Hardware device to physical structure binding and authentication

    Energy Technology Data Exchange (ETDEWEB)

    Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

    2013-08-20

    Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

  16. Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware

    NARCIS (Netherlands)

    Rauwerda, Gerard K.; Heysters, Paul M.; Smit, Gerard J.M.; Jha, N.K.

    2008-01-01

    Mobile wireless terminals tend to become multimode wireless communication devices. Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware provides the flexibility, performance, and efficiency to enable the implementation of these devices. The implementation of a wideband c

  17. Towards hardware-intrinsic security foundations and practice

    CERN Document Server

    Sadeghi, Ahmad-Reza; Tuyls, Pim

    2010-01-01

    Hardware-intrinsic security is a young field dealing with secure secret key storage. This book features contributions from researchers and practitioners with backgrounds in physics, mathematics, cryptography, coding theory and processor theory.

  18. Scientific Computing Using Consumer Video-Gaming Hardware Devices

    CERN Document Server

    Volkema, Glenn

    2016-01-01

    Commodity video-gaming hardware (consoles, graphics cards, tablets, etc.) performance has been advancing at a rapid pace owing to strong consumer demand and stiff market competition. Gaming hardware devices are currently amongst the most powerful and cost-effective computational technologies available in quantity. In this article, we evaluate a sample of current generation video-gaming hardware devices for scientific computing and compare their performance with specialized supercomputing general purpose graphics processing units (GPGPUs). We use the OpenCL SHOC benchmark suite, which is a measure of the performance of compute hardware on various different scientific application kernels, and also a popular public distributed computing application, Einstein@Home in the field of gravitational physics for the purposes of this evaluation.

  19. Hardware Descriptive Languages: An Efficient Approach to Device ...

    African Journals Online (AJOL)

    ... to Device Independent Designs with Complex Programmable Logic Devices ... in the very large scale integration (VLSI) market segments, hardware engineers ... the device independent architecture (Ultra 3700 CPLD series) for synthesis, ...

  20. Hardware Virtualization Support In INTEL, AMD And IBM Power Processors

    CERN Document Server

    Biswas, Kamanashis

    2009-01-01

    At present, the mostly used and developed mechanism is hardware virtualization which provides a common platform to run multiple operating systems and applications in independent partitions. More precisely, it is all about resource virtualization as the term hardware virtualization is emphasized. In this paper, the aim is to find out the advantages and limitations of current virtualization techniques, analyze their cost and performance and also depict which forthcoming hardware virtualization techniques will able to provide efficient solutions for multiprocessor operating systems. This is done by making a methodical literature survey and statistical analysis of the benchmark reports provided by SPEC (Standard Performance Evaluation Corporation) and TPC (Transaction processing Performance Council). Finally, this paper presents the current aspects of hardware virtualization which will help the IT managers of the large organizations to take effective decision while choosing server with virtualization support. Aga...

  1. Security challenges and opportunities in adaptive and reconfigurable hardware

    OpenAIRE

    Costan, Victor Marius; Devadas, Srinivas

    2011-01-01

    We present a novel approach to building hardware support for providing strong security guarantees for computations running in the cloud (shared hardware in massive data centers), while maintaining the high performance and low cost that make cloud computing attractive in the first place. We propose augmenting regular cloud servers with a Trusted Computation Base (TCB) that can securely perform high-performance computations. Our TCB achieves cost savings by spreading functionality across two pa...

  2. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  3. PLC Hardware Discrimination using RF-DNA fingerprinting

    Science.gov (United States)

    2014-06-19

    PLC HARDWARE DISCRIMINATION USING RF-DNA FINGERPRINTING THESIS Bradley C. Wright, Civilian, USAF AFIT-ENG-T-14-J-12 DEPARTMENT OF THE AIR FORCE AIR...protection in the United States. AFIT-ENG-T-14-J-12 PLC HARDWARE DISCRIMINATION USING RF-DNA FINGERPRINTING THESIS Presented to the Faculty Department... DISCRIMINATION USING RF-DNA FINGERPRINTING Bradley C. Wright, B.S.E.E. Civilian, USAF Approved: /signed/ Maj Samuel J. Stone, PhD (Chairman) /signed/ Michael A

  4. Operating System Support for Shared Hardware Data Structures

    Science.gov (United States)

    2013-01-31

    to ride my bicycle more, and Scotty for putting up with our bicycle talk. To the great folks who work with RTEMS, especially Joel Sherrill, Chris...1-1 The advantage of hardware is parallelism. . . . . . . . . . . . . . . . . . . . . . 3 1-2 Limited hardware resources create disadvantages for... disadvantages however, most of which stem from limited hard- ware resources. Chip space allocated to the HWDS steals from other features such as cache

  5. Hardware And Software For Development Of Robot Arms

    Science.gov (United States)

    Usikov, Daniel

    1995-01-01

    System of modular, reusable hardware and software assembled for use in developing remotely controlled robotic arms. Includes (1) central computer and peripheral equipment at control and monitoring station and (2) remote mechanical platform that supports robotic arm. Central computer controls motor drives of robotic arm, but optically, platform holds on-board computer for autonomous operation. Consists mostly of commercial hardware and software. Simulated results of commands viewed in three dimensions.

  6. The aerospace energy systems laboratory: Hardware and software implementation

    Science.gov (United States)

    Glover, Richard D.; Oneil-Rood, Nora

    1989-01-01

    For many years NASA Ames Research Center, Dryden Flight Research Facility has employed automation in the servicing of flight critical aircraft batteries. Recently a major upgrade to Dryden's computerized Battery Systems Laboratory was initiated to incorporate distributed processing and a centralized database. The new facility, called the Aerospace Energy Systems Laboratory (AESL), is being mechanized with iAPX86 and iAPX286 hardware running iRMX86. The hardware configuration and software structure for the AESL are described.

  7. Memory Based Machine Intelligence Techniques in VLSI hardware

    CERN Document Server

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.

  8. Memristor Crossbar-based Hardware Implementation of IDS Method

    OpenAIRE

    Merrikh-Bayat, Farnood; Bagheri-Shouraki, Saeed; Rohani, Ali

    2010-01-01

    Ink Drop Spread (IDS) is the engine of Active Learning Method (ALM), which is the methodology of soft computing. IDS, as a pattern-based processing unit, extracts useful information from a system subjected to modeling. In spite of its excellent potential in solving problems such as classification and modeling compared to other soft computing tools, finding its simple and fast hardware implementation is still a challenge. This paper describes a new hardware implementation of IDS method based o...

  9. III-V semiconductor materials and devices

    CERN Document Server

    Malik, R J

    1989-01-01

    The main emphasis of this volume is on III-V semiconductor epitaxial and bulk crystal growth techniques. Chapters are also included on material characterization and ion implantation. In order to put these growth techniques into perspective a thorough review of the physics and technology of III-V devices is presented. This is the first book of its kind to discuss the theory of the various crystal growth techniques in relation to their advantages and limitations for use in III-V semiconductor devices.

  10. Use of hardware accelerators for ATLAS computing

    CERN Document Server

    Dankel, Maik; The ATLAS collaboration; Howard, Jacob; Bauce, Matteo; Boing, Rene

    2015-01-01

    Modern HEP experiments produce tremendous amounts of data. This data is processed by in-house built software frameworks which have lifetimes longer than the detector it- self. Such frameworks were traditionally based on serial code and relied on advances in CPU technologies, mainly clock frequency, to cope with increasing data volumes. With the advent of many-core architectures and GPGPUs this paradigm has to shift to paral- lel processing and has to include the use of co-processors. However, since the design of most existing frameworks is based on the assumption of frequency scaling and predate co-processors, parallelisation and integration of co-processors are not an easy task. The ATLAS experiment is an example of such a big experiment with a big software frame- work called Athena. In this proceedings we will present the studies on parallelisation and co-processor (GPGPU) use in data preparation and tracking for trigger and offline recon- struction as well as their integration into a multiple process based...

  11. Fundamentals of GPS Receivers A Hardware Approach

    CERN Document Server

    Doberstein, Dan

    2012-01-01

    While much of the current literature on GPS receivers is aimed at those intimately familiar with their workings, this volume summarizes the basic principles using as little mathematics as possible, and details the necessary specifications and circuits for constructing a GPS receiver that is accurate to within 300 meters. Dedicated sections deal with the features of the GPS signal and its data stream, the details of the receiver (using a hybrid design as exemplar), and more advanced receivers and topics including time and frequency measurements. Later segments discuss the Zarlink GPS receiver chip set, as well as providing a thorough examination of the TurboRogue receiver, one of the most accurate yet made. Guiding the reader through the concepts and circuitry, from the antenna to the solution of user position, the book’s deployment of a hybrid receiver as a basis for discussion allows for extrapolation of the core ideas to more complex, and more accurate designs. Digital methods are used, but any analogue c...

  12. Use of hardware accelerators for ATLAS computing

    CERN Document Server

    Bauce, Matteo; Dankel, Maik; Howard, Jacob; Kama, Sami

    2015-01-01

    Modern HEP experiments produce tremendous amounts of data. These data are processed by in-house built software frameworks which have lifetimes longer than the detector itself. Such frameworks were traditionally based on serial code and relied on advances in CPU technologies, mainly clock frequency, to cope with increasing data volumes. With the advent of many-core architectures and GPGPUs this paradigm has to shift to parallel processing and has to include the use of co-processors. However, since the design of most existing frameworks is based on the assumption of frequency scaling and predate co-processors, parallelisation and integration of co-processors are not an easy task. The ATLAS experiment is an example of such a big experiment with a big software framework called Athena. In this talk we will present the studies on parallelisation and co-processor (GPGPU) use in data preparation and tracking for trigger and offline reconstruction as well as their integration into a multiple process based Athena frame...

  13. On the use of inexact, pruned hardware in atmospheric modelling.

    Science.gov (United States)

    Düben, Peter D; Joven, Jaume; Lingamneni, Avinash; McNamara, Hugh; De Micheli, Giovanni; Palem, Krishna V; Palmer, T N

    2014-06-28

    Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz '96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models.

  14. Assuring Quality and Reliability in Complex Avionics Systems hardware & Software

    Directory of Open Access Journals (Sweden)

    V. Haridas

    1997-01-01

    Full Text Available It is conventional wisdom in defence systems that electronic brains are where much of the present and future weapons system capability is developed. Electronic hardware advances, particularly in microprocessor, allow highly complex and sophisticated software to provide high degree of system autonomy and customisation to mission at hand. Since modern military systems are so much dependent on the proper functioning of electronics, the quality and reliability of electronic hardware and software have a profound impact on defensive capability and readiness. At the hardware level, due to the advances in microelectronics, functional capabilities of today's systems have increased. The advances in the hardware field have an impact on software also. Now a days, it is possible to incorporate more and more system functions through software, rather than going for a pure hardware solution. On the other hand complexities the systems are increasing, working energy levels of the systems are decreasing and the areas of reliability and quality assurance are becoming more and more wide. This paper covers major failure modes in microelectronic devices. The various techniques used to improve component and system reliability are described. The recent trends in expanding the scope of traditional quality assurance techniques are also discussed, considering both hardware and software.

  15. Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras

    Directory of Open Access Journals (Sweden)

    Ali Akbar Zarezadeh

    2012-01-01

    Full Text Available Tracking individuals is a prominent application in such domains like surveillance or smart environments. This paper provides a development of a multiple camera setup with jointed view that observes moving persons in a site. It focuses on a geometry-based approach to establish correspondence among different views. The expensive computational parts of the tracker are hardware accelerated via a novel system-on-chip (SoC design. In conjunction with this vision application, a hardware object request broker (ORB middleware is presented as the underlying communication system. The hardware ORB provides a hardware/software architecture to achieve real-time intercommunication among multiple smart cameras. Via a probing mechanism, a performance analysis is performed to measure network latencies, that is, time traversing the TCP/IP stack, in both software and hardware ORB approaches on the same smart camera platform. The empirical results show that using the proposed hardware ORB as client and server in separate smart camera nodes will considerably reduce the network latency up to 100 times compared to the software ORB.

  16. MSAP Hardware Verification: Testing Multi-Mission System Architecture Platform Hardware Using Simulation and Bench Test Equipment

    Science.gov (United States)

    Crossin, Kent R.

    2005-01-01

    The Multi-Mission System Architecture Platform (MSAP) project aims to develop a system of hardware and software that will provide the core functionality necessary in many JPL missions and can be tailored to accommodate mission-specific requirements. The MSAP flight hardware is being developed in the Verilog hardware description language, allowing developers to simulate their design before releasing it to a field programmable gate array (FPGA). FPGAs can be updated in a matter of minutes, drastically reducing the time and expense required to produce traditional application-specific integrated circuits. Bench test equipment connected to the FPGAs can then probe and run Tcl scripts on the hardware. The Verilog and Tcl code can be reused or modified with each design. These steps are effective in confirming that the design operates according specifications.

  17. An Enhanced Hardware Description Language Implementation for Improved Design-Space Exploration in High-Energy Physics Hardware Design

    CERN Document Server

    Mücke, M; Jacobsson, R

    2007-01-01

    Detectors in High-Energy Physics (HEP) have increased tremendously in accuracy, speed and integration. Consequently HEP experiments are confronted with an immense amount of data to be read out, processed and stored. Originally low-level processing has been accomplished in hardware, while more elaborate algorithms have been executed on large computing farms. Field-Programmable Gate Arrays (FPGAs) meet HEP's need for ever higher real-time processing performance by providing programmable yet fast digital logic resources. With the fast move from HEP Digital Signal Processing (DSPing) applications into the domain of FPGAs, related design tools are crucial to realise the potential performance gains. This work reviews Hardware Description Languages (HDLs) in respect to the special needs present in the HEP digital hardware design process. It is especially concerned with the question, how features outside the scope of mainstream digital hardware design can be implemented efficiently into HDLs. It will argue that funct...

  18. Review of Maxillofacial Hardware Complications and Indications for Salvage.

    Science.gov (United States)

    Hernandez Rosa, Jonatan; Villanueva, Nathaniel L; Sanati-Mehrizy, Paymon; Factor, Stephanie H; Taub, Peter J

    2016-06-01

    From 2002 to 2006, more than 117,000 facial fractures were recorded in the U.S. National Trauma Database. These fractures are commonly treated with open reduction and internal fixation. While in place, the hardware facilitates successful bony union. However, when postoperative complications occur, the plates may require removal before bony union. Indications for salvage versus removal of the maxillofacial hardware are not well defined. A literature review was performed to identify instances when hardware may be salvaged. Articles considered for inclusion were found in the PubMed and Web of Science databases in August 2014 with the keywords maxillofacial trauma AND hardware complications OR indications for hardware removal. Included studies looked at human patients with only facial trauma and miniplate fixation, and presented data on complications and/or hardware removal. Fifteen articles were included. None were clinical trials. Complication data were presented by patient, fractures, and/or plate without consistency. The data described 1,075 fractures, 2,961 patients, and 2,592 plates, nonexclusive. Complication rates varied from 6 to 8% by fracture and 6 to 13% by patient. When their data were combined, 50% of complications were treated with plate removal; this was consistent across the mandible, midface, and upper face. All complications caused by loosening, nonunion, broken hardware, and severe/prolonged pain were treated with removal. Some complications caused by exposures, deformities, and infections were treated with salvage. Exposed plates were treated with flaps, plates with deformities were treated with secondary procedures including hardware revision, and hardware infections were treated with antibiotics alone or in conjunction with soft-tissue debridement and/or tooth extraction. Well-designed clinical trials evaluating hardware removal versus salvage are lacking. Some postoperative complications caused by exposure, deformity, and/or infection may be

  19. Space biology initiative program definition review. Trade study 5: Modification of existing hardware (COTS) versus new hardware build cost analysis

    Science.gov (United States)

    Jackson, L. Neal; Crenshaw, John, Sr.; Davidson, William L.; Blacknall, Carolyn; Bilodeau, James W.; Stoval, J. Michael; Sutton, Terry

    1989-01-01

    The JSC Life Sciences Project Division has been directly supporting NASA Headquarters, Life Sciences Division, in the preparation of data from JSC and ARC to assist in defining the Space Biology Initiative (SBI). GE Government Services and Horizon Aerospace have provided contract support for the development and integration of review data, reports, presentations, and detailed supporting data. An SBI Definition (Non-Advocate) Review at NASA Headquarters, Code B, has been scheduled for the June-July 1989 time period. In a previous NASA Headquarters review, NASA determined that additional supporting data would be beneficial to determine the potential advantages in modifying commercial off-the-shelf (COTS) hardware for some SBI hardware items. In order to meet the demands of program implementation planning with the definition review in late spring of 1989, the definition trade study analysis must be adjusted in scope and schedule to be complete for the SBI Definition (Non-Advocate) Review. The relative costs of modifying existing commercial off-the-shelf (COTS) hardware is compared to fabricating new hardware. An historical basis for new build versus modifying COTS to meet current NMI specifications for manned space flight hardware is surveyed and identified. Selected SBI hardware are identified as potential candidates for off-the-shelf modification and statistical estimates on the relative cost of modifying COTS versus new build are provided.

  20. Solar Neutrino Measurement at SK-III

    CERN Document Server

    Yang, B S

    2009-01-01

    The full Super-Kamiokande-III data-taking period, which ran from August of 2006 through August of 2008, yielded 298 live days worth of solar neutrino data with a lower total energy threshold of 4.5 MeV. During this period we made many improvements to the experiment's hardware and software, with particular emphasis on its water purification system and Monte Carlo simulations. As a result of these efforts, we have significantly reduced the low energy backgrounds as compared to earlier periods of detector operation, cut the systematic errors by nearly a factor of two, and achieved a 4.5 MeV energy threshold for the solar neutrino analysis. In this presentation, I will present the preliminary SK-III solar neutrino measurement results.

  1. Volume Entropy

    CERN Document Server

    Astuti, Valerio; Rovelli, Carlo

    2016-01-01

    Building on a technical result by Brunnemann and Rideout on the spectrum of the Volume operator in Loop Quantum Gravity, we show that the dimension of the space of the quadrivalent states --with finite-volume individual nodes-- describing a region with total volume smaller than $V$, has \\emph{finite} dimension, bounded by $V \\log V$. This allows us to introduce the notion of "volume entropy": the von Neumann entropy associated to the measurement of volume.

  2. Higher-Level Hardware Synthesis of the KASUMI Algorithm

    Institute of Scientific and Technical Information of China (English)

    Issam W. Damaj

    2007-01-01

    Programmable Logic Devices (PLDs) continue to grow in size and currently contain several millions of gates.At the same time, research effort is going into higher-level hardware synthesis methodologies for reconfigurable computing that can exploit PLD technology.In this paper, we explore the effectiveness and extend one such formal methodology in the design of massively parallel algorithms.We take a step-wise refinement approach to the development of correct reconfigurable hardware circuits from formal specifications.A functional programming notation is used for specifying algorithms and for reasoning about them.The specifications are realised through the use of a combination of function decomposition strategies, data refinement techniques, and off-the-shelf refinements based upon higher-order functions.The off-the-shelf refinements are inspired by the operators of Communicating Sequential Processes (CSP) and map easily to programs in Handel-C (a hardware description language).The Handel-C descriptions are directly compiled into reconfigurable hardware.The practical realisation of this methodology is evidenced by a case studying the third generation mobile communication security algorithms.The investigated algorithm is the KASUMI block cipher.In this paper, we obtain several hardware implementations with different performance characteristics by applying different refinements to the algorithm.The developed designs are compiled and tested under Celoxica's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA.Performance analysis and evaluation of these implementations are included.

  3. GOSH! A roadmap for open-source science hardware

    CERN Multimedia

    Stefania Pandolfi

    2016-01-01

    The goal of the Gathering for Open Science Hardware (GOSH! 2016), held from 2 to 5 March 2016 at IdeaSquare, was to lay the foundations of the open-source hardware for science movement.   The participants in the GOSH! 2016 meeting gathered in IdeaSquare. (Image: GOSH Community) “Despite advances in technology, many scientific innovations are held back because of a lack of affordable and customisable hardware,” says François Grey, a professor at the University of Geneva and coordinator of Citizen Cyberlab – a partnership between CERN, the UN Institute for Training and Research and the University of Geneva – which co-organised the GOSH! 2016 workshop. “This scarcity of accessible science hardware is particularly obstructive for citizen science groups and humanitarian organisations that don’t have the same economic means as a well-funded institution.” Instead, open sourcing science hardware co...

  4. OS friendly microprocessor architecture: Hardware level computer security

    Science.gov (United States)

    Jungwirth, Patrick; La Fratta, Patrick

    2016-05-01

    We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

  5. Hardware/Software Codesign in a Compact Ion Mobility Spectrometer Sensor System for Subsurface Contaminant Detection

    Directory of Open Access Journals (Sweden)

    Gribb MollyM

    2008-01-01

    Full Text Available Abstract A field-programmable-gate-array-(FPGA- based data acquisition and control system was designed in a hardware/software codesign environment using an embedded Xilinx Microblaze soft-core processor for use with a subsurface ion mobility spectrometer (IMS system, designed for detection of gaseous volatile organic compounds (VOCs. An FPGA is used to accelerate the digital signal processing algorithms and provide accurate timing and control. An embedded soft-core processor is used to ease development by implementing nontime critical portions of the design in software. The design was successfully implemented using a low-cost, off-the-shelf Xilinx Spartan-III FPGA and supporting digital and analog electronics.

  6. Design of a Hardware Track Finder (Fast Tracker) for the ATLAS Trigger

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00010976; Albicocco, P.; Alison, J.; Ancu, L.S.; Anderson, J.; Andari, N.; Andreani, A.; Andreazza, A.; Annovi, A.; Antonelli, M.; Asbah, N.; Atkinson, M.; Baines, J.; Barberio, E.; Beccherle, R.; Beretta, M.; Bertolucci, F.; Biesuz, N.V.; Blair, R.; Bogdan, M.; Boveia, A.; Britzger, D.; Bryant, P.; Burghgrave, B.; Calderini, G.; Camplani, A.; Cavasinni, V.; Chakraborty, D.; Chang, P.; Cheng, Y.; Citraro, S.; Citterio, M.; Crescioli, F.; Dawe, N.; Dell'Orso, M.; Donati, S.; Dondero, P.; Drake, G.; Gadomski, S.; Gatta, M.; Gentsos, C.; Giannetti, P.; Gkaitatzis, S.; Gramling, J.; Howarth, J.W.; Iizawa, T.; Ilic, N.; Jiang, Z.; Kaji, T.; Kasten, M.; Kawaguchi, Y.; Kim, Y.K.; Kimura, N.; Klimkovich, T.; Kolb, M.; Kordas, K.; Krizka, K.; Kubota, T.; Lanza, A.; Li, H.L.; Liberali, V.; Lisovyi, M.; Liu, L.; Love, J.; Luciano, P.; Luongo, C.; Magalotti, D.; Maznas, I.; Meroni, C.; Mitani, T.; Nasimi, H.; Negri, A.; Neroutsos, P.; Neubauer, M.; Nikolaidis, S.; Okumura, Y.; Pandini, C.; Petridou, C.; Piendibene, M.; Proudfoot, J.; Rados, P.; Roda, C.; Rossi, E.; Sakurai, Y.; Sampsonidis, D.; Saxon, J.; Schmitt, S.; Schoening, A.; Shochet, M.; Shojaii, S.; Soltveit, H.; Sotiropoulou, C.L.; Stabile, A.; Swiatlowski, M.; Tang, F.; Taylor, P.T.; Testa, M.; Tompkins, L.; Vercesi, V.; Volpi, G.; Wang, R.; Watari, R.; Webster, J.; Wu, X.; Yorita, K.; Yurkewicz, A.; Zeng, J.C.; Zhang, J.; Zou, R.

    2016-01-01

    The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger an data acquisition (TDAQ) system and will be even more so as contemporary collisions that occur at every bunch crossing will increase in Run III. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100$\\mu$s, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance.

  7. Design of a hardware track finder (Fast Tracker) for the ATLAS trigger

    Science.gov (United States)

    Cavaliere, V.; Adelman, J.; Albicocco, P.; Alison, J.; Ancu, L. S.; Anderson, J.; Andari, N.; Andreani, A.; Andreazza, A.; Annovi, A.; Antonelli, M.; Asbah, N.; Atkinson, M.; Baines, J.; Barberio, E.; Beccherle, R.; Beretta, M.; Bertolucci, F.; Biesuz, N. V.; Blair, R.; Bogdan, M.; Boveia, A.; Britzger, D.; Bryant, P.; Burghgrave, B.; Calderini, G.; Camplani, A.; Cavasinni, V.; Chakraborty, D.; Chang, P.; Cheng, Y.; Citraro, S.; Citterio, M.; Crescioli, F.; Dawe, N.; Dell'Orso, M.; Donati, S.; Dondero, P.; Drake, G.; Gadomski, S.; Gatta, M.; Gentsos, C.; Giannetti, P.; Gkaitatzis, S.; Gramling, J.; Howarth, J. W.; Iizawa, T.; Ilic, N.; Jiang, Z.; Kaji, T.; Kasten, M.; Kawaguchi, Y.; Kim, Y. K.; Kimura, N.; Klimkovich, T.; Kolb, M.; Kordas, K.; Krizka, K.; Kubota, T.; Lanza, A.; Li, H. L.; Liberali, V.; Lisovyi, M.; Liu, L.; Love, J.; Luciano, P.; Luongo, C.; Magalotti, D.; Maznas, I.; Meroni, C.; Mitani, T.; Nasimi, H.; Negri, A.; Neroutsos, P.; Neubauer, M.; Nikolaidis, S.; Okumura, Y.; Pandini, C.; Petridou, C.; Piendibene, M.; Proudfoot, J.; Rados, P.; Roda, C.; Rossi, E.; Sakurai, Y.; Sampsonidis, D.; Saxon, J.; Schmitt, S.; Schoening, A.; Shochet, M.; Shojaii, S.; Soltveit, H.; Sotiropoulou, C. L.; Stabile, A.; Swiatlowski, M.; Tang, F.; Taylor, P. T.; Testa, M.; Tompkins, L.; Vercesi, V.; Volpi, G.; Wang, R.; Watari, R.; Webster, J.; Wu, X.; Yorita, K.; Yurkewicz, A.; Zeng, J. C.; Zhang, J.; Zou, R.

    2016-02-01

    The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger and data acquisition system and will be even more so as contemporary collisions that occur at every bunch crossing will increase in Run III. The Fast TracKer is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100μs, full tracking information for tracks with momentum as low as 1 GeV . Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance.

  8. Floating point hardware emulator for RSX-11D

    Energy Technology Data Exchange (ETDEWEB)

    Kellogg, M.; Long, M.

    1977-01-01

    An RSX-11D task was written to simulate the FP-11 floating point hardware on systems that lack this hardware. The simulation is transparent to tasks using floating point instructions. All normal features of the hardware are simulated exactly, including its action on exception conditions. The emulator is a privileged task occupying about 2.7K words of memory. When it is loaded and run, it sets up a linkage to intercept the reserved instruction trap before it reaches the executive, and route it to a service routine that can decode and simulate the floating point instruction set. The results of a benchmark timing test are given, as are notes on converting the emulator to run under RSX-11M. 1 figure, 2 tables.

  9. Modular particle filtering FPGA hardware architecture for brain machine interfaces.

    Science.gov (United States)

    Mountney, John; Obeid, Iyad; Silage, Dennis

    2011-01-01

    As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform for performing parallel computations in real-time. The scalability and reconfigurability of the FPGA accommodates diverse sets of neural ensembles and a variety of decoding algorithms. Throughput is significantly increased by decomposing computations into independent parallel hardware modules on the FPGA. This increase in throughput is demonstrated through a parallel hardware implementation of the auxiliary particle filtering signal processing algorithm.

  10. Hardware Abstraction and Protocol Optimization for Coded Sensor Networks

    DEFF Research Database (Denmark)

    Nistor, Maricica; Roetter, Daniel Enrique Lucani; Barros, João

    2015-01-01

    -efficient protocols that use such an abstraction, as well as mechanisms to optimize a communication protocol in terms of energy consumption. The problem is modeled for different feedback-based techniques, where sensors are connected to a base station, either directly or through relays. We show that for four example......The design of the communication protocols in wireless sensor networks (WSNs) often neglects several key characteristics of the sensor's hardware, while assuming that the number of transmitted bits is the dominating factor behind the system's energy consumption. A closer look at the hardware...... platforms, the use of relays may decrease up to 4.5 times the total energy consumption when the protocol and the hardware are carefully matched. We conclude that: 1) the energy budget for a communication protocol varies significantly on different sensor platforms; and 2) the protocols can be judiciously...

  11. Combining high productivity with high performance on commodity hardware

    DEFF Research Database (Denmark)

    Skovhede, Kenneth

    The current advances in the natural sciences are increasingly dependent on the available in computer power. At the same time, the increase in computer power is no longer based on faster cores, but on multiple cores and specialized hardware. As most scientific software is written for sequential...... processing, the increase in hardware performance cannot be utilized. Most existing scientific software is written in low-level languages such as C or FORTRAN, making it difficult to rewrite these to work in parallel. As the brief CELL-BE processor history showed, writing solutions that are tied...... to a particular hardware platform, is a risky investment. To make this problem worse, the scientists that have the required field expertise to write the algorithms are not formally trained programmers. This usually leads to scientists writing buggy, inefficient and hard to maintain programs. Occasionally...

  12. DAQ hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed read-out hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  13. DAQ Hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment was extended by about 12 million pixels with the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented by employing newly designed read-out hardware, which supports the full detector bandwidth even for calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  14. Hardware/Software Co-Design for Spike Based Recognition

    CERN Document Server

    Ghani, Arfan; Maguire, Liam; Harkin, Jim

    2008-01-01

    The practical applications based on recurrent spiking neurons are limited due to their non-trivial learning algorithms. The temporal nature of spiking neurons is more favorable for hardware implementation where signals can be represented in binary form and communication can be done through the use of spikes. This work investigates the potential of recurrent spiking neurons implementations on reconfigurable platforms and their applicability in temporal based applications. A theoretical framework of reservoir computing is investigated for hardware/software implementation. In this framework, only readout neurons are trained which overcomes the burden of training at the network level. These recurrent neural networks are termed as microcircuits which are viewed as basic computational units in cortical computation. This paper investigates the potential of recurrent neural reservoirs and presents a novel hardware/software strategy for their implementation on FPGAs. The design is implemented and the functionality is ...

  15. Scalable Digital Hardware for a Trapped Ion Quantum Computer

    CERN Document Server

    Mount, Emily; Vrijsen, Geert; Adams, Michael; Baek, So-Young; Hudek, Kai; Isabella, Louis; Crain, Stephen; van Rynbach, Andre; Maunz, Peter; Kim, Jungsang

    2015-01-01

    Many of the challenges of scaling quantum computer hardware lie at the interface between the qubits and the classical control signals used to manipulate them. Modular ion trap quantum computer architectures address scalability by constructing individual quantum processors interconnected via a network of quantum communication channels. Successful operation of such quantum hardware requires a fully programmable classical control system capable of frequency stabilizing the continuous wave lasers necessary for trapping and cooling the ion qubits, stabilizing the optical frequency combs used to drive logic gate operations on the ion qubits, providing a large number of analog voltage sources to drive the trap electrodes, and a scheme for maintaining phase coherence among all the controllers that manipulate the qubits. In this work, we describe scalable solutions to these hardware development challenges.

  16. XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Gaurav Purohit

    2016-01-01

    Full Text Available This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW implementation of new architecture uses Lookup Table (LUT for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.

  17. Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps

    DEFF Research Database (Denmark)

    Bonnichsen, Lars Frydendal; Probst, Christian W.; Karlsson, Sven

    2015-01-01

    Synchronization of concurrent data structures is difficult to get right. Fine-grained synchronization locks small data chunks, but requires too high an overhead per chunk, traditional coarse-grained synchronization locks big data chunks, and thereby makes them unavailable to other threads. Neither...... synchronization method scales well. Recently, hardware transactional memory was introduced, which allows threads to use transactions instead of locks. So far, applying hardware transactional memory has shown mixed results. We believe this is because transactions are different from locks, and using them...... efficiently requires reasoning about those differences. In this paper we present 5 guidelines for applying hardware transactional memory efficiently, and apply the guidelines to BT-trees, a concurrent ordered map. Evaluating BT-trees on standard benchmarks shows that they are up to 5.3 times faster than...

  18. Asymmetric Hardware Distortions in Receive Diversity Systems: Outage Performance Analysis

    KAUST Repository

    Javed, Sidrah

    2017-02-22

    This paper studies the impact of asymmetric hardware distortion (HWD) on the performance of receive diversity systems using linear and switched combining receivers. The asymmetric attribute of the proposed model motivates the employment of improper Gaussian signaling (IGS) scheme rather than the traditional proper Gaussian signaling (PGS) scheme. The achievable rate performance is analyzed for the ideal and non-ideal hardware scenarios using PGS and IGS transmission schemes for different combining receivers. In addition, the IGS statistical characteristics are optimized to maximize the achievable rate performance. Moreover, the outage probability performance of the receive diversity systems is analyzed yielding closed form expressions for both PGS and IGS based transmission schemes. HWD systems that employ IGS is proven to efficiently combat the self interference caused by the HWD. Furthermore, the obtained analytic expressions are validated through Monte-Carlo simulations. Eventually, non-ideal hardware transceivers degradation and IGS scheme acquired compensation are quantified through suitable numerical results.

  19. Hardware Realization of Chaos-based Symmetric Video Encryption

    KAUST Repository

    Ibrahim, Mohamad A.

    2013-05-01

    This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.

  20. Scalable digital hardware for a trapped ion quantum computer

    Science.gov (United States)

    Mount, Emily; Gaultney, Daniel; Vrijsen, Geert; Adams, Michael; Baek, So-Young; Hudek, Kai; Isabella, Louis; Crain, Stephen; van Rynbach, Andre; Maunz, Peter; Kim, Jungsang

    2016-12-01

    Many of the challenges of scaling quantum computer hardware lie at the interface between the qubits and the classical control signals used to manipulate them. Modular ion trap quantum computer architectures address scalability by constructing individual quantum processors interconnected via a network of quantum communication channels. Successful operation of such quantum hardware requires a fully programmable classical control system capable of frequency stabilizing the continuous wave lasers necessary for loading, cooling, initialization, and detection of the ion qubits, stabilizing the optical frequency combs used to drive logic gate operations on the ion qubits, providing a large number of analog voltage sources to drive the trap electrodes, and a scheme for maintaining phase coherence among all the controllers that manipulate the qubits. In this work, we describe scalable solutions to these hardware development challenges.

  1. Hardware Architecture Study for NASA's Space Software Defined Radios

    Science.gov (United States)

    Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

    2008-01-01

    This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  2. CyberStorm III

    NARCIS (Netherlands)

    Luiijf, H.A.M.; et al

    2010-01-01

    Projectteam Cyber Storm III - De Verenigde Staten organiseerden de afgelopen jaren een reeks grootschalige ICT-crisisoefeningen met de naam Cyber Storm. Cyber Storm III is de derde oefening in de reeks. Het scenario van Cyber Storm III staat in het teken van grootschalige ICT-verstoringen, waarbij n

  3. Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs

    Directory of Open Access Journals (Sweden)

    Viktor K. Prasanna

    2006-09-01

    Full Text Available By allowing parts of the applications to be executed either on soft processors (as software programs or on customized hardware peripherals attached to the processors, FPGAs have made traditional energy estimation techniques inefficient for evaluating various design tradeoffs. In this paper, we propose a high-level simulation-based two-step rapid energy estimation technique for hardware-software codesign using FPGAs. In the first step, a high-level hardware-software cosimulation technique is applied to simulate both the hardware and software components of the target application. High-level simulation results of both software programs running on the processors and the customized hardware peripherals are gathered during the cosimulation process. In the second step, the high-level simulation results of the customized hardware peripherals are used to estimate the switching activities of their corresponding register-transfer/gate level (“low-level” implementations. We use this information to employ an instruction-level energy estimation technique and a domain-specific energy performance modeling technique to estimate the energy dissipation of the complete application. A Matlab/Simulink-based implementation of our approach and two numerical computation applications show that the proposed energy estimation technique can achieve more than 6000x speedup over low-level simulation-based techniques while sacrificing less than 10% estimation accuracy. Compared with the measured results, our experimental results show that the proposed technique achieves an average estimation error of less than 12%.

  4. Stretched Lens Array (SLA) Photovoltaic Concentrator Hardware Development and Testing

    Science.gov (United States)

    Piszczor, Michael; O'Neill, Mark J.; Eskenazi, Michael

    2003-01-01

    Over the past two years, the Stretched Lens Array (SLA) photovoltaic concentrator has evolved, under a NASA contract, from a concept with small component demonstrators to operational array hardware that is ready for space validation testing. A fully-functional four panel SLA solar array has been designed, built and tested. This paper will summarize the focus of the hardware development effort, discuss the results of recent testing conducted under this program and present the expected performance of a full size 7kW array designed to meet the requirements of future space missions.

  5. Combining high productivity with high performance on commodity hardware

    DEFF Research Database (Denmark)

    Skovhede, Kenneth

    The current advances in the natural sciences are increasingly dependent on the available in computer power. At the same time, the increase in computer power is no longer based on faster cores, but on multiple cores and specialized hardware. As most scientific software is written for sequential...... to a particular hardware platform, is a risky investment. To make this problem worse, the scientists that have the required field expertise to write the algorithms are not formally trained programmers. This usually leads to scientists writing buggy, inefficient and hard to maintain programs. Occasionally...

  6. Surface moisture measurement system hardware acceptance test report

    Energy Technology Data Exchange (ETDEWEB)

    Ritter, G.A., Westinghouse Hanford

    1996-05-28

    This document summarizes the results of the hardware acceptance test for the Surface Moisture Measurement System (SMMS). This test verified that the mechanical and electrical features of the SMMS functioned as designed and that the unit is ready for field service. The bulk of hardware testing was performed at the 306E Facility in the 300 Area and the Fuels and Materials Examination Facility in the 400 Area. The SMMS was developed primarily in support of Tank Waste Remediation System (TWRS) Safety Programs for moisture measurement in organic and ferrocyanide watch list tanks.

  7. Realizable Hardware-Based Method for Digital Modulation Classification

    Institute of Scientific and Technical Information of China (English)

    HAN Li; WAN Jin-bo

    2005-01-01

    A new method suited for hardware implementation is developed to classify 8 different digital modulation types with raised cosine base-band impulse without knowing the carrier frequency and symbol timing. The normalized histogram of stagnation points for instantaneous parameters is used to recognize both ideal rectangular and raised cosine base-band digital signals. Carrier frequency estimation is used to enhance the recognition rate of phase-modulated signals. In the condition of 10 dB signal noise ratio (SNR), the recognizing rate is over 80 %. The new algorithm is suited for hardware implementation.

  8. Computer organization and design the hardware/software interface

    CERN Document Server

    Hennessy, John L

    1994-01-01

    Computer Organization and Design: The Hardware/Software Interface presents the interaction between hardware and software at a variety of levels, which offers a framework for understanding the fundamentals of computing. This book focuses on the concepts that are the basis for computers.Organized into nine chapters, this book begins with an overview of the computer revolution. This text then explains the concepts and algorithms used in modern computer arithmetic. Other chapters consider the abstractions and concepts in memory hierarchies by starting with the simplest possible cache. This book di

  9. Hardware Evaluation of the Horizontal Exercise Fixture with Weight Stack

    Science.gov (United States)

    Newby, Nate; Leach, Mark; Fincke, Renita; Sharp, Carwyn

    2009-01-01

    HEF with weight stack seems to be a very sturdy and reliable exercise device that should function well in a bed rest training setting. A few improvements should be made to both the hardware and software to improve usage efficiency, but largely, this evaluation has demonstrated HEF's robustness. The hardware offers loading to muscles, bones, and joints, potentially sufficient to mitigate the loss of muscle mass and bone mineral density during long-duration bed rest campaigns. With some minor modifications, the HEF with weight stack equipment provides the best currently available means of performing squat, heel raise, prone row, bench press, and hip flexion/extension exercise in a supine orientation.

  10. Automating an EXAFS facility: hardware and software considerations

    Energy Technology Data Exchange (ETDEWEB)

    Georgopoulos, P; Sayers, D E; Bunker, B; Elam, T; Grote, W A

    1981-01-01

    The basic design considerations for computer hardware and software, applicable not only to laboratory EXAFS facilities, but also to synchrotron installations, are reviewed. Uniformity and standardization of both hardware configurations and program packages for data collection and analysis are heavily emphasized. Specific recommendations are made with respect to choice of computers, peripherals, and interfaces, and guidelines for the development of software packages are set forth. A description of two working computer-interfaced EXAFS facilities is presented which can serve as prototypes for future developments. 3 figures.

  11. Electrical, electronics, and digital hardware essentials for scientists and engineers

    CERN Document Server

    Lipiansky, Ed

    2012-01-01

    A practical guide for solving real-world circuit board problems Electrical, Electronics, and Digital Hardware Essentials for Scientists and Engineers arms engineers with the tools they need to test, evaluate, and solve circuit board problems. It explores a wide range of circuit analysis topics, supplementing the material with detailed circuit examples and extensive illustrations. The pros and cons of various methods of analysis, fundamental applications of electronic hardware, and issues in logic design are also thoroughly examined. The author draws on more than tw

  12. Hardware-assisted software clock synchronization for homogeneous distributed systems

    Science.gov (United States)

    Ramanathan, P.; Kandlur, Dilip D.; Shin, Kang G.

    1990-01-01

    A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

  13. Towards Shop Floor Hardware Reconfiguration for Industrial Collaborative Robots

    DEFF Research Database (Denmark)

    Schou, Casper; Madsen, Ole

    2016-01-01

    In this paper we propose a roadmap for hardware reconfiguration of industrial collaborative robots. As a flexible resource, the collaborative robot will often need transitioning to a new task. Our goal is, that this transitioning should be done by the shop floor operators, not highly specialized...... engineers. The hard- ware reconfiguration framework adopts a modular architecture for the collabo- rative robot which dictates a clear segmentation of the robot into well-defined exchangeable modules. Four main objectives for the hardware reconfiguration framework; 1) Modular architecture, 2) Module...

  14. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  15. Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain

    Directory of Open Access Journals (Sweden)

    Guillermo A. Jaquenod

    2014-01-01

    Full Text Available In digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs. This short paper focuses on the implementation of a dual chain of 14 stages of cascaded half band filters plus 2 : 1 decimators for complex signals (in-phase and quadrature with minimal hardware resources, using a small portion of an UT6325 Aeroflex FPGA, as a part of a receiver designed for a low data rate command and telemetry channel.

  16. Global Positioning System III (GPS III)

    Science.gov (United States)

    2015-12-01

    Military Operations in Urban Terrain; Defense-Wide Mission Support; Air Mobility; and Space Launch Orbital Support. For military users, the GPS III...program provides Precise Positioning Service (PPS) to military operations and force enhancement. It also provides increased anti-jam power to the earth ...to be modified . On January 31, 2016, USD(AT&L) signed the GPS III revised APB. This Change 1 to the APB was due to both cost and schedule breaches

  17. Towards LTE-U Interference Detection, Assessment and Mitigation in 802.11 Networks using Commodity Hardware

    OpenAIRE

    Olbrich, Michael; Zubow, Anatolij; Zehl, Sven; Wolisz, Adam

    2017-01-01

    We propose WiPLUS -- a system that enables WiFi to deal with the stealthy invasion of LTE-U into the frequency bands used by WiFi. Using solely MAC layer information extracted passively, during runtime, out of the hardware registers of the WiFi NIC at the WiFi access point, WiPLUS is able to: i) detect interfering LTE-U signals, ii) compute their duty-cycles, and iii) derive the effective medium airtime available for each WiFi link in a WiFi Basic Service Set (BSS). Moreover WiPLUS provides a...

  18. Speech Optimization at 9600 Bits/Second. Volume 2. Real-Time Software and Hardware.

    Science.gov (United States)

    1980-09-30

    resumed as follows: q s A r c ACCA -- S rUP > When resumed, the task closes the MAP and exits. If a complete, two MAP system is desired, the process...7 - -- r a - N - P7 .2 P £ C £ C P 2 a 2 ... C-C..UUUC.. t~t.~-7:~------------- - N 2 Cr. C ~t - NQt& NI 0C-N#rt NSOC~Nqt£rxOC.~Ne U N CCCL- C CCCCC

  19. Design requirements for SRB production control system. Volume 3: Package evaluation, modification and hardware

    Science.gov (United States)

    1981-01-01

    The software package evaluation was designed to analyze commercially available, field-proven, production control or manufacturing resource planning management technology and software package. The analysis was conducted by comparing SRB production control software requirements and conceptual system design to software package capabilities. The methodology of evaluation and the findings at each stage of evaluation are described. Topics covered include: vendor listing; request for information (RFI) document; RFI response rate and quality; RFI evaluation process; and capabilities versus requirements.

  20. Distributed Processing Tools Definition. Volume 1. Hardware and Software Technologies for Tightly-Coupled Distributed Systems.

    Science.gov (United States)

    1983-06-01

    SDLC MITRE X MITRE Coax Bus Hybr Broad Band Cambridge Cambridge Twisted 15 Ring Rotal Ring Univ. Pair Expand- Slot ( Logica cable able Ltd. Fiber Optic...Documentation, Analysis, Validation and Error-detection DEC - Digital Equipment Corporation DEDS - Data Entry Display Stations DOD - Department of

  1. The USAFA/8086 - A State of the Art Microprocessor System. Volume I. System Hardware.

    Science.gov (United States)

    1980-06-01

    August 1978 to March 1980. DD , It" 1473 EDITION 0 INOV 6S IS OBSOLETE UCASFE SECURITY CLASSIFICATION OF THIS PAGE (When Date latt TABLE OF CONTENTS...APPM71IX A COST ANALYSIS ESTIMATE This appendix estimates on a board by board basis the cost of the parts arid materials used in construction of the

  2. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele...

  3. Towards automated construction of dependable software/hardware systems

    Energy Technology Data Exchange (ETDEWEB)

    Yakhnis, A.; Yakhnis, V. [Pioneer Technologies & Rockwell Science Center, Albuquerque, NM (United States)

    1997-11-01

    This report contains viewgraphs on the automated construction of dependable computer architecture systems. The outline of this report is: examples of software/hardware systems; dependable systems; partial delivery of dependability; proposed approach; removing obstacles; advantages of the approach; criteria for success; current progress of the approach; and references.

  4. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA...

  5. Foundations of digital signal processing theory, algorithms and hardware design

    CERN Document Server

    Gaydecki, Patrick

    2005-01-01

    An excellent introductory text, this book covers the basic theoretical, algorithmic and real-time aspects of digital signal processing (DSP). Detailed information is provided on off-line, real-time and DSP programming and the reader is effortlessly guided through advanced topics such as DSP hardware design, FIR and IIR filter design and difference equation manipulation.

  6. On-Chip Reconfigurable Hardware Accelerators for Popcount Computations

    Directory of Open Access Journals (Sweden)

    Valery Sklyarov

    2016-01-01

    Full Text Available Popcount computations are widely used in such areas as combinatorial search, data processing, statistical analysis, and bio- and chemical informatics. In many practical problems the size of initial data is very large and increase in throughput is important. The paper suggests two types of hardware accelerators that are (1 designed in FPGAs and (2 implemented in Zynq-7000 all programmable systems-on-chip with partitioning of algorithms that use popcounts between software of ARM Cortex-A9 processing system and advanced programmable logic. A three-level system architecture that includes a general-purpose computer, the problem-specific ARM, and reconfigurable hardware is then proposed. The results of experiments and comparisons with existing benchmarks demonstrate that although throughput of popcount computations is increased in FPGA-based designs interacting with general-purpose computers, communication overheads (in experiments with PCI express are significant and actual advantages can be gained if not only popcount but also other types of relevant computations are implemented in hardware. The comparison of software/hardware designs for Zynq-7000 all programmable systems-on-chip with pure software implementations in the same Zynq-7000 devices demonstrates increase in performance by a factor ranging from 5 to 19 (taking into account all the involved communication overheads between the programmable logic and the processing systems.

  7. TreeBASIS Feature Descriptor and Its Hardware Implementation

    Directory of Open Access Journals (Sweden)

    Spencer Fowers

    2014-01-01

    Full Text Available This paper presents a novel feature descriptor called TreeBASIS that provides improvements in descriptor size, computation time, matching speed, and accuracy. This new descriptor uses a binary vocabulary tree that is computed using basis dictionary images and a test set of feature region images. To facilitate real-time implementation, a feature region image is binary quantized and the resulting quantized vector is passed into the BASIS vocabulary tree. A Hamming distance is then computed between the feature region image and the effectively descriptive basis dictionary image at a node to determine the branch taken and the path the feature region image takes is saved as a descriptor. The TreeBASIS feature descriptor is an excellent candidate for hardware implementation because of its reduced descriptor size and the fact that descriptors can be created and features matched without the use of floating point operations. The TreeBASIS descriptor is more computationally and space efficient than other descriptors such as BASIS, SIFT, and SURF. Moreover, it can be computed entirely in hardware without the support of a CPU for additional software-based computations. Experimental results and a hardware implementation show that the TreeBASIS descriptor compares well with other descriptors for frame-to-frame homography computation while requiring fewer hardware resources.

  8. The Educational Uses of Computers: Hardware, Software, and Strategies.

    Science.gov (United States)

    McMurray, Pamela; Hoover, Loretta W.

    1984-01-01

    Summarizes developments, trends, and strategies of computer use in education by discussing the history of computers in education, benefits of computers for instruction, hardware and software selection and use, and types of computer programs. Examples of computer programs and computer applications used in food and nutrition education are included.…

  9. Hardware-in-the-loop testing of marine control system

    Directory of Open Access Journals (Sweden)

    Roger Skjetne

    2006-10-01

    Full Text Available Hardware-in-the-Loop (HIL testing is proposed as a new methodology for verification and certification of marine control systems. Formalizing such testing necessitates the development of a vocabulary and set of definitions. This paper treats these issues by constructing a framework suitable for industrial HIL test applications and certification of marine systems.

  10. Chip-Multiprocessor Hardware Locks for Safety-Critical Java

    DEFF Research Database (Denmark)

    Strøm, Torur Biskopstø; Puffitsch, Wolfgang; Schoeberl, Martin

    2013-01-01

    and may void a task set's schedulability. In this paper we present a hardware locking mechanism to reduce the synchronization overhead. The solution is implemented for the chip-multiprocessor version of the Java Optimized Processor in the context of safety-critical Java. The implementation is compared...

  11. Hardware Approach for Real Time Machine Stereo Vision

    Directory of Open Access Journals (Sweden)

    Michael Tornow

    2006-02-01

    Full Text Available Image processing is an effective tool for the analysis of optical sensor information for driver assistance systems and controlling of autonomous robots. Algorithms for image processing are often very complex and costly in terms of computation. In robotics and driver assistance systems, real-time processing is necessary. Signal processing algorithms must often be drastically modified so they can be implemented in the hardware. This task is especially difficult for continuous real-time processing at high speeds. This article describes a hardware-software co-design for a multi-object position sensor based on a stereophotogrammetric measuring method. In order to cover a large measuring area, an optimized algorithm based on an image pyramid is implemented in an FPGA as a parallel hardware solution for depth map calculation. Object recognition and tracking are then executed in real-time in a processor with help of software. For this task a statistical cluster method is used. Stabilization of the tracking is realized through use of a Kalman filter. Keywords: stereophotogrammetry, hardware-software co-design, FPGA, 3-d image analysis, real-time, clustering and tracking.

  12. Choropleth Mapping on Personal Computers: Software Sources and Hardware Requirements.

    Science.gov (United States)

    Lewis, Lawrence T.

    1986-01-01

    Describes the hardware and some of the choropleth mapping software available for the IBM-PC, PC compatible and Apple II microcomputers. Reviewed are: Micromap II, Documap, Desktop Information Display System (DIDS) , Multimap, Execuvision, Iris Gis, Mapmaker, PC Map, Statmap, and Atlas Map. Vendors' addresses are provided. (JDH)

  13. Smart Home Hardware-in-the-Loop Testing

    Energy Technology Data Exchange (ETDEWEB)

    Pratt, Annabelle

    2017-07-12

    This presentation provides a high-level overview of NREL's smart home hardware-in-the-loop testing. It was presented at the Fourth International Workshop on Grid Simulator Testing of Energy Systems and Wind Turbine Powertrains, held April 25-26, 2017, hosted by NREL and Clemson University at the Energy Systems Integration Facility in Golden, Colorado.

  14. Use of Heritage Hardware on MPCV Exploration Flight Test One

    Science.gov (United States)

    Rains, George Edward; Cross, Cynthia D.

    2011-01-01

    Due to an aggressive schedule for the first orbital test flight of an unmanned Orion capsule, known as Exploration Flight Test One (EFT1), combined with severe programmatic funding constraints, an effort was made to identify heritage hardware, i.e., already existing, flight-certified components from previous manned space programs, which might be available for use on EFT1. With the end of the Space Shuttle Program, no current means exists to launch Multi Purpose Logistics Modules (MPLMs) to the International Space Station (ISS), and so the inventory of many flight-certified Shuttle and MPLM components are available for other purposes. Two of these items are the Shuttle Ground Support Equipment Heat Exchanger (GSE Hx) and the MPLM cabin Positive Pressure Relief Assembly (PPRA). In preparation for the utilization of these components by the Orion Program, analyses and testing of the hardware were performed. The PPRA had to be analyzed to determine its susceptibility to pyrotechnic shock, and vibration testing had to be performed, since those environments are predicted to be significantly more severe during an Orion mission than those the hardware was originally designed to accommodate. The GSE Hx had to be tested for performance with the Orion thermal working fluids, which are different from those used by the Space Shuttle. This paper summarizes the certification of the use of heritage hardware for EFT1.

  15. Hardware-Conscious DBMS Architecture for Data-Intensive Applications

    NARCIS (Netherlands)

    Zukowski, M.

    2005-01-01

    Recent research shows that traditional database technology does not efficiently exploit the features of modern computer hardware. This problem is especially visible in the area of computationally-intensive applications, where specialized programs achieve performance orders of magnitude higher than D

  16. Analog Hardware Description Language and Its Relations to VHDL

    Directory of Open Access Journals (Sweden)

    J. Popelek

    1996-09-01

    Full Text Available Primary motivations for analogue hardware description language (VHDL-A is to support the modelling of physical systems. The VHDL-A must therefore allow to model the physical conservation laws, such as the energy conservation law, which states that energy can neither be created nor destroyed, but it can only change its form.

  17. USAFSAM Waiver File Intelligent Terminal: Hardware Reference Manual.

    Science.gov (United States)

    1980-04-01

    I. SBC 80/20 single - board computer for the central processing unit (CPU) 2. SBC 104 general purpose input/output (I/0) and memory board 3. SBC 108...5 5 Carousel TXR 15 r APPENDIX A. REFERENCE MANUAL LIST 1. SBC 80/20 Single Board Computer Hardware Reference Manual. Intel, 1977. 2. SBC 104/108/116

  18. Hardware availability calculations and results of the IFMIF accelerator facility

    Energy Technology Data Exchange (ETDEWEB)

    Bargalló, Enric, E-mail: enric.bargallo-font@upc.edu [Fusion Energy Engineering Laboratory (FEEL), Technical University of Catalonia (UPC), Barcelona (Spain); Arroyo, Jose Manuel [Laboratorio Nacional de Fusión por Confinamiento Magnético – CIEMAT, Madrid (Spain); Abal, Javier [Fusion Energy Engineering Laboratory (FEEL), Technical University of Catalonia (UPC), Barcelona (Spain); Beauvais, Pierre-Yves; Gobin, Raphael; Orsini, Fabienne [Commissariat à l’Energie Atomique, Saclay (France); Weber, Moisés; Podadera, Ivan [Laboratorio Nacional de Fusión por Confinamiento Magnético – CIEMAT, Madrid (Spain); Grespan, Francesco; Fagotti, Enrico [Istituto Nazionale di Fisica Nucleare, Legnaro (Italy); De Blas, Alfredo; Dies, Javier; Tapia, Carlos [Fusion Energy Engineering Laboratory (FEEL), Technical University of Catalonia (UPC), Barcelona (Spain); Mollá, Joaquín; Ibarra, Ángel [Laboratorio Nacional de Fusión por Confinamiento Magnético – CIEMAT, Madrid (Spain)

    2014-10-15

    Highlights: • IFMIF accelerator facility hardware availability analyses methodology is described. • Results of the individual hardware availability analyses are shown for the reference design. • Accelerator design improvements are proposed for each system. • Availability results are evaluated and compared with the requirements. - Abstract: Hardware availability calculations have been done individually for each system of the deuteron accelerators of the International Fusion Materials Irradiation Facility (IFMIF). The principal goal of these analyses is to estimate the availability of the systems, compare it with the challenging IFMIF requirements and find new paths to improve availability performances. Major unavailability contributors are highlighted and possible design changes are proposed in order to achieve the hardware availability requirements established for each system. In this paper, such possible improvements are implemented in fault tree models and the availability results are evaluated. The parallel activity on the design and construction of the linear IFMIF prototype accelerator (LIPAc) provides detailed design information for the RAMI (reliability, availability, maintainability and inspectability) analyses and allows finding out the improvements that the final accelerator could have. Because of the R and D behavior of the LIPAc, RAMI improvements could be the major differences between the prototype and the IFMIF accelerator design.

  19. Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Christophe Bobda

    2009-01-01

    Full Text Available We present a methodology based on self-organization to manage resources in networked embedded systems based on reconfigurable hardware. Two points are detailed in this paper, the monitoring system used to analyse the system and the Local Marketplaces Global Symbiosis (LMGS concept defined for self-organization of dynamically reconfigurable nodes.

  20. Hardware Algorithms For Tile-Based Real-Time Rendering

    NARCIS (Netherlands)

    Crisu, D.

    2012-01-01

    In this dissertation, we present the GRAphics AcceLerator (GRAAL) framework for developing embedded tile-based rasterization hardware for mobile devices, meant to accelerate real-time 3-D graphics (OpenGL compliant) applications. The goal of the framework is a low-cost, low-power, high-performance

  1. Combining hardware and simulation for datacenter scaling studies

    DEFF Research Database (Denmark)

    Ruepp, Sarah Renée; Pilimon, Artur; Thrane, Jakob

    2017-01-01

    and simulation to illustrate the scalability and performance of datacenter networks. We simulate a Datacenter network and interconnect it with real world traffic generation hardware. Analysis of the introduced packet conversion and virtual queueing delays shows that the conversion efficiency is at the order...... of a few microseconds, but the virtual queuing may have significant implication on the performance analysis results....

  2. Hardware Algorithms For Tile-Based Real-Time Rendering

    NARCIS (Netherlands)

    Crisu, D.

    2012-01-01

    In this dissertation, we present the GRAphics AcceLerator (GRAAL) framework for developing embedded tile-based rasterization hardware for mobile devices, meant to accelerate real-time 3-D graphics (OpenGL compliant) applications. The goal of the framework is a low-cost, low-power, high-performance d

  3. Rapid space hardware development through computer-automated testing

    Energy Technology Data Exchange (ETDEWEB)

    Masters, D.S.; Ruud, K.K.

    1997-10-01

    FORTE, the Fast On-Orbit Recording of Transient Events small satellite designed and built by Los Alamos and Sandia National Laboratories, is scheduled for launch in August, 1997. In the spirit of {open_quotes}better, cheaper, faster{close_quotes} satellites, the RF experiment hardware (receiver and trigger sub-systems) necessitated rapid prototype testing and characterization in the development of space-flight components. This was accomplished with the assembly of engineering model hardware prior to construction of flight hardware and the design of component-specific, PC-based software control libraries. Using the LabVIEW{reg_sign} graphical programming language, together with off-the-shelf PC digital I/O and GPIB interface cards, hardware control and complete automation of test equipment was possible from one PC. Because the receiver and trigger sub-systems employed complex functions for signal discrimination and transient detection, thorough validation of all functions and illumination of any faults were priorities. These methods were successful in accelerating the development and characterization of space-flight components prior to integration and allowed more complete data to be gathered than could have been accomplished without automation. Additionally, automated control of input signal sources was carried over from bench-level to system-level with the use of networked Linux workstation utilizing a GPIB interface.

  4. 3D IBFV : Hardware-Accelerated 3D Flow Visualization

    NARCIS (Netherlands)

    Telea, Alexandru; Wijk, Jarke J. van

    2003-01-01

    We present a hardware-accelerated method for visualizing 3D flow fields. The method is based on insertion, advection, and decay of dye. To this aim, we extend the texture-based IBFV technique for 2D flow visualization in two main directions. First, we decompose the 3D flow visualization problem in a

  5. Efficient Architecture for Spike Sorting in Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Sheng-Ying Lai

    2013-11-01

    Full Text Available This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA and fuzzy C-means (FCM algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA. It is embedded in a System-on-Chip (SOC platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

  6. The Challenges of Hardware Synthesis from C-Like Languages

    CERN Document Server

    Edwards, Stephen A

    2011-01-01

    MANY TECHNIQUES for synthesizing digital hardware from C-like languages have been proposed, but none have emerged as successful as Verilog or VHDL for register-transfer-level design. This paper looks at two of the fundamental challenges: concurrency and timing control.

  7. Hardware Trojans - Prevention, Detection, Countermeasures (A Literature Review)

    Science.gov (United States)

    2011-07-01

    System on Chip TCB trusted Computing Base VHDL VHSIC Hardware Description Language x UNCLASSIFIED UNCLASSIFIED DSTO–TN–1012 1 Introduction Electronic...The authors introduced modi- fications at the VHDL level and provided both simulation and synthesised results using a 40MHz Leon 3 SPARC target

  8. Hardware-in-the-loop testing of marine control system

    OpenAIRE

    2006-01-01

    Hardware-in-the-Loop (HIL) testing is proposed as a new methodology for verification and certification of marine control systems. Formalizing such testing necessitates the development of a vocabulary and set of definitions. This paper treats these issues by constructing a framework suitable for industrial HIL test applications and certification of marine systems.

  9. Modules and supporting hardware for FASTBUS test and diagnostic purposes

    Energy Technology Data Exchange (ETDEWEB)

    Bertolucci, B.

    1981-10-01

    This paper contains detailed descriptions and circuitry of some modules and supporting hardware for the FASTBUS System developed at SLAC. A fast slave-only Memory Module (PRIMO), a Dummy Module (U2), a FASTBUS Test Box (LAIKA), and a Bus Display Bar (BBD) have been built, tested and used for test and diagnostic purposes for FASTBUS.

  10. RDV77 VLBA Hardware/Software Correlator Comparisons

    Science.gov (United States)

    Gordon, David

    2010-01-01

    Results of a hardware vs. software correlation of the RDV77 session are presented. Group delays are found to agree (WRMS differences) at an average level of 4.2 psec and with a noise floor of 2.5 psec. These RDV77 comparisons agree well with several previous correlator comparison studies.

  11. An Integrated Hardware Array for Very High Speed Logic Simulation

    Directory of Open Access Journals (Sweden)

    E. Scott Fehr

    1996-01-01

    boolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for hardware gate level simulation accelerators.

  12. Cache-based memory copy hardware accelerator for multicore systems

    NARCIS (Netherlands)

    Duarte, F.; Wong, S.

    2010-01-01

    In this paper, we present a new architecture of the cache-based memory copy hardware accelerator in a multicore system supporting message passing. The accelerator is able to accelerate memory data movements, in particular memory copies. We perform an analytical analysis based on open-queuing theory

  13. The Certification of Environmental Chambers for Testing Flight Hardware

    Science.gov (United States)

    Fields, Keith

    2010-01-01

    The JPL chamber certification process for ensuring that test chambers used to test flight hardware meet a minimum standard is critical to the safety of the hardware and personnel. Past history has demonstrated that this process is important due to the catastrophic incidents that could occur if the chamber is not set up correctly. Environmental testing is one of the last phases in the development of a subsystem, and it typically occurs just before integration of flight hardware into the fully assembled flight system. A seemingly insignificant -miscalculation or missed step can necessitate rebuilding or replacing a subsystem due to over-testing or damage from the test chamber. Conversely, under-testing might fail to detect weaknesses that might cause failure when the hardware is in service. This paper describes the process that identifies the many variables that comprise the testing scenario and screening of as built chambers, the training of qualified operators, and a general "what-to-look-for" in minimum standards.

  14. Hardware in Loop Simulation for Missile Guidance and Control Systems

    Directory of Open Access Journals (Sweden)

    S. K. Chaudhuri

    1997-07-01

    Full Text Available The purpose of the guidance law is to determine appropriate missile flight path dynamics to achieve mission objective in an efficient manner based on navigation information. Today, guided missiles which are aerodynamically unstable or non-linear in all or part of the flight envelopes need control systems for stability as well as for steering. Many classical guidance and control laws have been used for tactical missiles with varying degrees of performance, complexity and seeker/sensor requirements. Increased accuracy requirements and more dynamic tactics of modern warfare demand improvement of performance which is a trade-off between sophisticated hardware and more sophisticated software. To avoid increase in cost by hardware sophistication, today's trend is to exploit new theoretical methods and low cost high speed microprocessor techniques. Missile test flights are very expensive. The missile system with its sophisticated software and hardware is not reusable after a test launch. Hardware-in-loop Simulation (HILS facilities and methodology form a well integrated system aimed at transforming a preliminary guidance and control system design to flight software and hardware with trajectory right from lift-off till its impact. Various guidance and control law studies pertaining to gathering basket and stability margins, pre-flight, post-flight analyses and validation of support systems have been carried out using this methodology. Nearly full spectrum of dynamically accurate six-degrees-of-freedom (6-DOF model of missile systems has been realised in the HILS scenario. The HILS facility allows interconnection of missile hardware in flight configuration. Pre-flight HILS results have matched fairly well with actual flight trial results. It was possible to detect many hidden defects in the onboard guidance and control software as well as in hardware during HILS. Deficiencies in model, like tail-wag-dog (TWD, flexibility, seeker dynamics and defects in

  15. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

    Science.gov (United States)

    Fernandez, Edward B; Villarreal, Jason; Lonardi, Stefano; Najjar, Walid A

    2015-01-01

    While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat).

  16. Flight Hardware Packaging Design for Stringent EMC Radiated Emission Requirements

    Science.gov (United States)

    Lortz, Charlene L.; Huang, Chi-Chien N.; Ravich, Joshua A.; Steiner, Carl N.

    2013-01-01

    This packaging design approach can help heritage hardware meet a flight project's stringent EMC radiated emissions requirement. The approach requires only minor modifications to a hardware's chassis and mainly concentrates on its connector interfaces. The solution is to raise the surface area where the connector is mounted by a few millimeters using a pedestal, and then wrapping with conductive tape from the cable backshell down to the surface-mounted connector. This design approach has been applied to JPL flight project subsystems. The EMC radiated emissions requirements for flight projects can vary from benign to mission critical. If the project's EMC requirements are stringent, the best approach to meet EMC requirements would be to design an EMC control program for the project early on and implement EMC design techniques starting with the circuit board layout. This is the ideal scenario for hardware that is built from scratch. Implementation of EMC radiated emissions mitigation techniques can mature as the design progresses, with minimal impact to the design cycle. The real challenge exists for hardware that is planned to be flown following a built-to-print approach, in which heritage hardware from a past project with a different set of requirements is expected to perform satisfactorily for a new project. With acceptance of heritage, the design would already be established (circuit board layout and components have already been pre-determined), and hence any radiated emissions mitigation techniques would only be applicable at the packaging level. The key is to take a heritage design with its known radiated emissions spectrum and repackage, or modify its chassis design so that it would have a better chance of meeting the new project s radiated emissions requirements.

  17. Integrated Hardware and Software for No-Loss Computing

    Science.gov (United States)

    James, Mark

    2007-01-01

    When an algorithm is distributed across multiple threads executing on many distinct processors, a loss of one of those threads or processors can potentially result in the total loss of all the incremental results up to that point. When implementation is massively hardware distributed, then the probability of a hardware failure during the course of a long execution is potentially high. Traditionally, this problem has been addressed by establishing checkpoints where the current state of some or part of the execution is saved. Then in the event of a failure, this state information can be used to recompute that point in the execution and resume the computation from that point. A serious problem arises when one distributes a problem across multiple threads and physical processors is that one increases the likelihood of the algorithm failing due to no fault of the scientist but as a result of hardware faults coupled with operating system problems. With good reason, scientists expect their computing tools to serve them and not the other way around. What is novel here is a unique combination of hardware and software that reformulates an application into monolithic structure that can be monitored in real-time and dynamically reconfigured in the event of a failure. This unique reformulation of hardware and software will provide advanced aeronautical technologies to meet the challenges of next-generation systems in aviation, for civilian and scientific purposes, in our atmosphere and in atmospheres of other worlds. In particular, with respect to NASA s manned flight to Mars, this technology addresses the critical requirements for improving safety and increasing reliability of manned spacecraft.

  18. The CMS Trigger Supervisor: Control and Hardware Monitoring System of the CMS Level-1 Trigger at CERN

    CERN Document Server

    Ildefons Magrans de Abril

    2008-01-01

    The experiments CMS (Compact Muon Solenoid) and ATLAS (A Toroidal LHC ApparatuS) at the LargeHadron Collider (LHC) are the greatest exponents of the rising complexity in High Energy Physics (HEP) datahandling instrumentation. Tens of millions of readout channels, tens of thousands of hardware boards and thesame order of connections are figures of merit. However, the hardware volume is not the only complexitydimension, the unprecedented large number of research institutes and scientists that form the internationalcollaborations, and the long design, development, commissioning and operational phases are additional factorsthat must be taken into account.The Level-1 (L1) trigger decision loop is an excellent example of these difficulties. This system is based on apipelined logic destined to analyze without deadtime the data from each LHC bunch crossing occurring every25_ns, using special coarsely segmented trigger data from the detectors. The L1 trigger is responsible forreducing the rate of accepted crossings to...

  19. Metallothionein (MT)-III

    DEFF Research Database (Denmark)

    Carrasco, J; Giralt, M; Molinero, A

    1999-01-01

    Metallothionein-III is a low molecular weight, heavy-metal binding protein expressed mainly in the central nervous system. First identified as a growth inhibitory factor (GIF) of rat cortical neurons in vitro, it has subsequently been shown to be a member of the metallothionein (MT) gene family...... and renamed as MT-III. In this study we have raised polyclonal antibodies in rabbits against recombinant rat MT-III (rMT-III). The sera obtained reacted specifically against recombinant zinc-and cadmium-saturated rMT-III, and did not cross-react with native rat MT-I and MT-II purified from the liver of zinc...... injected rats. The specificity of the antibody was also demonstrated in immunocytochemical studies by the elimination of the immunostaining by preincubation of the antibody with brain (but not liver) extracts, and by the results obtained in MT-III null mice. The antibody was used to characterize...

  20. Bare-Hand Volume Cracker for Raw Volume Data Analysis

    Directory of Open Access Journals (Sweden)

    Bireswar Laha

    2016-09-01

    Full Text Available Analysis of raw volume data generated from different scanning technologies faces a variety of challenges, related to search, pattern recognition, spatial understanding, quantitative estimation, and shape description. In a previous study, we found that the Volume Cracker (VC 3D interaction (3DI technique mitigated some of these problems, but this result was from a tethered glove-based system with users analyzing simulated data. Here, we redesigned the VC by using untethered bare-hand interaction with real volume datasets, with a broader aim of adoption of this technique in research labs. We developed symmetric and asymmetric interfaces for the Bare-Hand Volume Cracker (BHVC through design iterations with a biomechanics scientist. We evaluated our asymmetric BHVC technique against standard 2D and widely used 3D interaction techniques with experts analyzing scanned beetle datasets. We found that our BHVC design significantly outperformed the other two techniques. This study contributes a practical 3DI design for scientists, documents lessons learned while redesigning for bare-hand trackers, and provides evidence suggesting that 3D interaction could improve volume data analysis for a variety of visual analysis tasks. Our contribution is in the realm of 3D user interfaces tightly integrated with visualization, for improving the effectiveness of visual analysis of volume datasets. Based on our experience, we also provide some insights into hardware-agnostic principles for design of effective interaction techniques.

  1. Brain inspired hardware architectures - Can they be used for particle physics ?

    CERN Document Server

    CERN. Geneva

    2016-01-01

    After their inception in the 1940s and several decades of moderate success, artificial neural networks have recently demonstrated impressive achievements in analysing big data volumes. Wide and deep network architectures can now be trained using high performance computing systems, graphics card clusters in particular. Despite their successes these state-of-the-art approaches suffer from very long training times and huge energy consumption, in particular during the training phase. The biological brain can perform similar and superior classification tasks in the space and time domains, but at the same time exhibits very low power consumption, rapid unsupervised learning capabilities and fault tolerance. In the talk the differences between classical neural networks and neural circuits in the brain will be presented. Recent hardware implementations of neuromorphic computing systems and their applications will be shown. Finally, some initial ideas to use accelerated neural architectures as trigger processors i...

  2. Nuclear volume and prognosis in ovarian cancer

    DEFF Research Database (Denmark)

    Mogensen, O.; Sørensen, Flemming Brandt; Bichel, P.

    1992-01-01

    The prognostic value of the volume-weighted mean nuclear volume (MNV) was investigated retrospectively in 100 ovarian cancer patients with FIGO-stage IB-II (n = 51) and stage III-IV (n = 49) serous tumors. No association was demonstrated between the MNV and the survival or between the MNV and two...

  3. Nuclear volume and prognosis in ovarian cancer

    DEFF Research Database (Denmark)

    Mogensen, O.; Sørensen, Flemming Brandt; Bichel, P.;

    1992-01-01

    The prognostic value of the volume-weighted mean nuclear volume (MNV) was investigated retrospectively in 100 ovarian cancer patients with FIGO-stage IB-II (n = 51) and stage III-IV (n = 49) serous tumors. No association was demonstrated between the MNV and the survival or between the MNV and two...

  4. Signal-To Ratio Improvement in NMR via Receiver Hardware Optimization.

    Science.gov (United States)

    Duensing, George Randall

    The goal of this research was to increase available signal-to-noise ratio (SNR) in magnetic resonance imaging (MRI) by applying specific knowledge of the imaging system to improve receiver probes (coils) and receiving hardware. A brief history of improvements in MRI receiver and coil design is presented, including the transition from large linear volume coils to local surface coils and quadrature volume coils. Then quadrature surface coils are introduced and finally multi-coil arrays with independent acquisition systems. The research covers improvements in these areas and begins with a surface coil which is adjustable in size to optimize performance given the region of interest. By careful design of trombone-like coil elements, physical adjustment can be made without electrical adjustment. Second, new understanding of noise correlation and crosstalk between coils is developed and applied to multi-coil arrays. This provides the ability to increase available SNR for such systems. Third, a method for optimally combining multiple coils in a transverse (extending perpendicular to the static magnetic field) array into a single channel by proper signal combination is presented. This method is termed generalized quadrature because of the similarity of the method to standard quadrature combination, but with freedom in weighting and phasing in the combination process. Fourth, several methods of manipulating the multiple signals from an array to allow separation after acquisition are presented. These methods require new hardware demands but allow significant improvements in SNR for either transverse or longitudinal arrays. Fifth, several novel design methods are demonstrated, including an algorithm for impedance matching, a generalized quadrature combination method, transmission synchronized rf shielding and a bird-cage surface coil. Finally, the potential future applications and benefits of this research are presented.

  5. Industrial fuel gas demonstration plant program. Current working estimate. Phase III and III

    Energy Technology Data Exchange (ETDEWEB)

    1979-12-01

    The United States Department of Energy (DOE) executed a contract with Memphis Light, Gas and Water Division (MLGW) which requires MLGW to perform process analysis, design, procurement, construction, testing, operation, and evaluation of a plant which will demonstrate the feasibility of converting high sulfur bituminous coal to industrial fuel gas with a heating value of 300 +- 30 Btu per standard cubic foot (SCF). The demonstration plant is based on the U-Gas process, and its product gas is to be used in commercial applications in Memphis, Tenn. The contract specifies that the work is to be conducted in three phases. The Phases are: Phase I - Program Development and Conceptual Design; Phase II - Demonstration Plant Final Design, Procurement and Construction; and Phase III - Demonstration Plant Operation. Under Task III of Phase I, a Cost Estimate for the Demonstration Plant was completed as well as estimates for other Phase II and III work. The output of this Estimate is presented in this volume. This Current Working Estimate for Phases II and III is based on the Process and Mechanical Designs presented in the Task II report (second issue) and the 12 volumes of the Task III report. In addition, the capital cost estimate summarized in the appendix has been used in the Economic Analysis (Task III) Report.

  6. Fast and Reliable Mouse Picking Using Graphics Hardware

    Directory of Open Access Journals (Sweden)

    Hanli Zhao

    2009-01-01

    Full Text Available Mouse picking is the most commonly used intuitive operation to interact with 3D scenes in a variety of 3D graphics applications. High performance for such operation is necessary in order to provide users with fast responses. This paper proposes a fast and reliable mouse picking algorithm using graphics hardware for 3D triangular scenes. Our approach uses a multi-layer rendering algorithm to perform the picking operation in linear time complexity. The objectspace based ray-triangle intersection test is implemented in a highly parallelized geometry shader. After applying the hardware-supported occlusion queries, only a small number of objects (or sub-objects are rendered in subsequent layers, which accelerates the picking efficiency. Experimental results demonstrate the high performance of our novel approach. Due to its simplicity, our algorithm can be easily integrated into existing real-time rendering systems.

  7. The LISA Pathfinder interferometry—hardware and system testing

    Science.gov (United States)

    Audley, H.; Danzmann, K.; García Marín, A.; Heinzel, G.; Monsky, A.; Nofrarias, M.; Steier, F.; Gerardi, D.; Gerndt, R.; Hechenblaikner, G.; Johann, U.; Luetzow-Wentzky, P.; Wand, V.; Antonucci, F.; Armano, M.; Auger, G.; Benedetti, M.; Binetruy, P.; Boatella, C.; Bogenstahl, J.; Bortoluzzi, D.; Bosetti, P.; Caleno, M.; Cavalleri, A.; Cesa, M.; Chmeissani, M.; Ciani, G.; Conchillo, A.; Congedo, G.; Cristofolini, I.; Cruise, M.; De Marchi, F.; Diaz-Aguilo, M.; Diepholz, I.; Dixon, G.; Dolesi, R.; Fauste, J.; Ferraioli, L.; Fertin, D.; Fichter, W.; Fitzsimons, E.; Freschi, M.; García Marirrodriga, C.; Gesa, L.; Gibert, F.; Giardini, D.; Grimani, C.; Grynagier, A.; Guillaume, B.; Guzmán, F.; Harrison, I.; Hewitson, M.; Hollington, D.; Hough, J.; Hoyland, D.; Hueller, M.; Huesler, J.; Jeannin, O.; Jennrich, O.; Jetzer, P.; Johlander, B.; Killow, C.; Llamas, X.; Lloro, I.; Lobo, A.; Maarschalkerweerd, R.; Madden, S.; Mance, D.; Mateos, I.; McNamara, P. W.; Mendes, J.; Mitchell, E.; Nicolini, D.; Nicolodi, D.; Pedersen, F.; Perreur-Lloyd, M.; Perreca, A.; Plagnol, E.; Prat, P.; Racca, G. D.; Rais, B.; Ramos-Castro, J.; Reiche, J.; Romera Perez, J. A.; Robertson, D.; Rozemeijer, H.; Sanjuan, J.; Schulte, M.; Shaul, D.; Stagnaro, L.; Strandmoe, S.; Sumner, T. J.; Taylor, A.; Texier, D.; Trenkel, C.; Tombolato, D.; Vitale, S.; Wanner, G.; Ward, H.; Waschke, S.; Wass, P.; Weber, W. J.; Zweifel, P.

    2011-05-01

    Preparations for the LISA Pathfinder mission have reached an exciting stage. Tests of the engineering model (EM) of the optical metrology system have recently been completed at the Albert Einstein Institute, Hannover, and flight model tests are now underway. Significantly, they represent the first complete integration and testing of the space-qualified hardware and are the first tests on an optical system level. The results and test procedures of these campaigns will be utilized directly in the ground-based flight hardware tests, and subsequently during in-flight operations. In addition, they allow valuable testing of the data analysis methods using the MATLAB-based LTP data analysis toolbox. This paper presents an overview of the results from the EM test campaign that was successfully completed in December 2009.

  8. Object oriented hardware-software test bench for OMTF diagnosis

    Science.gov (United States)

    Drabik, Pawel; Pozniak, Krzysztof T.; Bunkowski, Karol; Zawistowski, Krystian; Byszuk, Adrian; Bluj, Michał; Doroba, Krzysztof; Górski, Maciej; Kalinowski, Artur; Kierzkowski, Krzysztof; Konecki, Marcin; Królikowski, Jan; Oklinski, Wojciech; Olszewski, Michał; Skala, Aleksander; Zabołotny, Wojciech M.

    2015-09-01

    In this paper the object oriented hardware-software model and its sample implementation of diagnostics for the Overlap Muon Track Finder trigger for the CMS experiment in CERN is described. It presents realization of test-bench for control and diagnosis class of multichannel, distributed measurement systems based on FPGA chips. The test-bench fulfills requirements for system's rapid changes, configurability and efficiency. This ability is very significant and desirable by expanded electronic systems. The solution described is a software model based on a method of address space management called the Component Internal Interface (CII). Establishment of stable link between hardware and software, as a purpose of designed and realized programming environment, is presented. The test-bench implementation and example of OMTF algorithm test is presented.

  9. Computer organization and design the hardware/software interface

    CERN Document Server

    Patterson, David A

    2013-01-01

    The 5th edition of Computer Organization and Design moves forward into the post-PC era with new examples, exercises, and material highlighting the emergence of mobile computing and the cloud. This generational change is emphasized and explored with updated content featuring tablet computers, cloud infrastructure, and the ARM (mobile computing devices) and x86 (cloud computing) architectures. Because an understanding of modern hardware is essential to achieving good performance and energy efficiency, this edition adds a new concrete example, "Going Faster," used throughout the text to demonstrate extremely effective optimization techniques. Also new to this edition is discussion of the "Eight Great Ideas" of computer architecture. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Optimization techniques featured throughout the text. It covers parallelism in depth with...

  10. Hardware/software co-verification platform for EOS design

    Institute of Scientific and Technical Information of China (English)

    2005-01-01

    Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.

  11. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  12. Function Interface Models for Hardware Compilation: Types, Signatures, Protocols

    CERN Document Server

    Ghica, Dan R

    2009-01-01

    The problem of synthesis of gate-level descriptions of digital circuits from behavioural specifications written in higher-level programming languages (hardware compilation) has been studied for a long time yet a definitive solution has not been forthcoming. The argument of this essay is mainly methodological, bringing a perspective that is informed by recent developments in programming-language theory. We argue that one of the major obstacles in the way of hardware compilation becoming a useful and mature technology is the lack of a well defined function interface model, i.e. a canonical way in which functions communicate with arguments. We discuss the consequences of this problem and propose a solution based on new developments in programming language theory. We conclude by presenting a prototype implementation and some examples illustrating our principles.

  13. Binary Associative Memories as a Benchmark for Spiking Neuromorphic Hardware

    Directory of Open Access Journals (Sweden)

    Andreas Stöckel

    2017-08-01

    Full Text Available Large-scale neuromorphic hardware platforms, specialized computer systems for energy efficient simulation of spiking neural networks, are being developed around the world, for example as part of the European Human Brain Project (HBP. Due to conceptual differences, a universal performance analysis of these systems in terms of runtime, accuracy and energy efficiency is non-trivial, yet indispensable for further hard- and software development. In this paper we describe a scalable benchmark based on a spiking neural network implementation of the binary neural associative memory. We treat neuromorphic hardware and software simulators as black-boxes and execute exactly the same network description across all devices. Experiments on the HBP platforms under varying configurations of the associative memory show that the presented method allows to test the quality of the neuron model implementation, and to explain significant deviations from the expected reference output.

  14. Summary of multi-core hardware and programming model investigations

    Energy Technology Data Exchange (ETDEWEB)

    Kelly, Suzanne Marie; Pedretti, Kevin Thomas Tauke; Levenhagen, Michael J.

    2008-05-01

    This report summarizes our investigations into multi-core processors and programming models for parallel scientific applications. The motivation for this study was to better understand the landscape of multi-core hardware, future trends, and the implications on system software for capability supercomputers. The results of this study are being used as input into the design of a new open-source light-weight kernel operating system being targeted at future capability supercomputers made up of multi-core processors. A goal of this effort is to create an agile system that is able to adapt to and efficiently support whatever multi-core hardware and programming models gain acceptance by the community.

  15. Verification of OpenSSL version via hardware performance counters

    Science.gov (United States)

    Bruska, James; Blasingame, Zander; Liu, Chen

    2017-05-01

    Many forms of malware and security breaches exist today. One type of breach downgrades a cryptographic program by employing a man-in-the-middle attack. In this work, we explore the utilization of hardware events in conjunction with machine learning algorithms to detect which version of OpenSSL is being run during the encryption process. This allows for the immediate detection of any unknown downgrade attacks in real time. Our experimental results indicated this detection method is both feasible and practical. When trained with normal TLS and SSL data, our classifier was able to detect which protocol was being used with 99.995% accuracy. After the scope of the hardware event recording was enlarged, the accuracy diminished greatly, but to 53.244%. Upon removal of TLS 1.1 from the data set, the accuracy returned to 99.905%.

  16. Outline of a fast hardware implementation of Winograd's DFT algorithm

    Science.gov (United States)

    Zohar, S.

    1980-01-01

    The main characteristics of the discrete Fourier transform (DFT) algorithm considered by Winograd (1976) is a significant reduction in the number of multiplications. Its primary disadvantage is a higher structural complexity. It is, therefore, difficult to translate the reduced number of multiplications into faster execution of the DFT by means of a software implementation of the algorithm. For this reason, a hardware implementation is considered in the current study, taking into account a design based on the algorithm prescription discussed by Zohar (1979). The hardware implementation of a FORTRAN subroutine is proposed, giving attention to a pipelining scheme in which 5 consecutive data batches are being operated on simultaneously, each batch undergoing one of 5 processing phases.

  17. Advances in neuromorphic hardware exploiting emerging nanoscale devices

    CERN Document Server

    2017-01-01

    This book covers all major aspects of cutting-edge research in the field of neuromorphic hardware engineering involving emerging nanoscale devices. Special emphasis is given to leading works in hybrid low-power CMOS-Nanodevice design. The book offers readers a bidirectional (top-down and bottom-up) perspective on designing efficient bio-inspired hardware. At the nanodevice level, it focuses on various flavors of emerging resistive memory (RRAM) technology. At the algorithm level, it addresses optimized implementations of supervised and stochastic learning paradigms such as: spike-time-dependent plasticity (STDP), long-term potentiation (LTP), long-term depression (LTD), extreme learning machines (ELM) and early adoptions of restricted Boltzmann machines (RBM) to name a few. The contributions discuss system-level power/energy/parasitic trade-offs, and complex real-world applications. The book is suited for both advanced researchers and students interested in the field.

  18. Cumulative Measurement Errors for Dynamic Testing of Space Flight Hardware

    Science.gov (United States)

    Winnitoy, Susan

    2012-01-01

    Located at the NASA Johnson Space Center in Houston, TX, the Six-Degree-of-Freedom Dynamic Test System (SDTS) is a real-time, six degree-of-freedom, short range motion base simulator originally designed to simulate the relative dynamics of two bodies in space mating together (i.e., docking or berthing). The SDTS has the capability to test full scale docking and berthing systems utilizing a two body dynamic docking simulation for docking operations and a Space Station Remote Manipulator System (SSRMS) simulation for berthing operations. The SDTS can also be used for nonmating applications such as sensors and instruments evaluations requiring proximity or short range motion operations. The motion base is a hydraulic powered Stewart platform, capable of supporting a 3,500 lb payload with a positional accuracy of 0.03 inches. The SDTS is currently being used for the NASA Docking System testing and has been also used by other government agencies. The SDTS is also under consideration for use by commercial companies. Examples of tests include the verification of on-orbit robotic inspection systems, space vehicle assembly procedures and docking/berthing systems. The facility integrates a dynamic simulation of on-orbit spacecraft mating or de-mating using flight-like mechanical interface hardware. A force moment sensor is used for input during the contact phase, thus simulating the contact dynamics. While the verification of flight hardware presents unique challenges, one particular area of interest involves the use of external measurement systems to ensure accurate feedback of dynamic contact. The measurement systems for the test facility have two separate functions. The first is to take static measurements of facility and test hardware to determine both the static and moving frames used in the simulation and control system. The test hardware must be measured after each configuration change to determine both sets of reference frames. The second function is to take dynamic

  19. Commercial Aircraft Maintenance Experience Relating to Engine External Hardware

    Science.gov (United States)

    Soditus, Sharon M.

    2006-01-01

    Airlines are extremely sensitive to the amount of dollars spent on maintaining the external engine hardware in the field. Analysis reveals that many problems revolve around a central issue, reliability. Fuel and oil leakage due to seal failure and electrical fault messages due to wire harness failures play a major role in aircraft delays and cancellations (D&C's) and scheduled maintenance. Correcting these items on the line requires a large investment of engineering resources and manpower after the fact. The smartest and most cost effective philosophy is to build the best hardware the first time. The only way to do that is to completely understand and model the operating environment, study the field experience of similar designs and to perform extensive testing.

  20. Web tools to monitor and debug DAQ hardware

    Energy Technology Data Exchange (ETDEWEB)

    Eugene Desavouret; Jerzy M. Nogiec

    2003-06-04

    A web-based toolkit to monitor and diagnose data acquisition hardware has been developed. It allows for remote testing, monitoring, and control of VxWorks data acquisition computers and associated instrumentation using the HTTP protocol and a web browser. This solution provides concurrent and platform independent access, supplementary to the standard single-user rlogin mechanism. The toolkit is based on a specialized web server, and allows remote access and execution of select system commands and tasks, execution of test procedures, and provides remote monitoring of computer system resources and connected hardware. Various DAQ components such as multiplexers, digital I/O boards, analog to digital converters, or current sources can be accessed and diagnosed remotely in a uniform and well-organized manner. Additionally, the toolkit application supports user authentication and is able to enforce specified access restrictions.

  1. [Software and hardware for computer equipment designed for psychophysiological examination].

    Science.gov (United States)

    Matveev, E V; Gal'etov, I V; Vasil'ev, A A; Kravchuk, A Iu; Tereshkina, D V

    2005-01-01

    Principles of designing software and hardware for new computer equipment for psychophysiological examination were elaborated on the basis of theoretical prerequisites and of analysis of the use of equipment manufactured serially for quantitation of indices of the human higher nervous activity (HNA). The hierarchic structuring of software and hardware enabled, through unification of solutions, the development of new modifications of two equipment sets: computer-based unit "Psihomat" KPFK-99 for psychophysiological examination and computer-based unit "STABILOTEST" ST-01 for the evaluation of the central nervous system by the stability parameters in maintaining the vertical posture. The units have new improved functional features and provide the users with new computer technologies for dealing with research and practical tasks related with examination of human HNA parameters in health and pathology.

  2. Fabrication of light weight radioisotope heater unit hardware components

    Science.gov (United States)

    McNeil, Dennis C.

    1996-03-01

    The Light Weight Radioisotope Heater Unit (LWRHU) is planned to be used on the National Aeronautics and Space Administration (NASA) Cassini Mission, to provide localized thermal energy as strategic locations on the spacecraft. These one watt heater units will support the operation of many on-board instruments that require a specific temperature range to function properly. The system incorporates a fuel pellet encapsulated in a vented metallic clad fabricated from platinum-30% rhodium (Pt-30%Rh) tubing, sheet and foil materials. To complete the package, the clad assemblies are placed inside a combination of graphite components. This report describes the techniques employed by Mound related to the fabrication and sub assembly processes of the LWRHU clad hardware components. Included are details concerning configuration control systems, material procurement and certification, hardware fabrication specifics, and special processes that are utilized.

  3. New Techniques for Implementation of Hardware Algorithms inside FPGA Circuits

    Directory of Open Access Journals (Sweden)

    IOAN, A. D.

    2010-05-01

    Full Text Available This work presents a less known theoretical method for the synthesis of complex hardware automata by using the transition matrix, together with a new practical method for visual implementation inside FPGA circuits, with library schematic symbols from the "Altium Designer" software environment. Because these techniques need to be presented by example, the classical shift and add unsigned multiply algorithm was chosen for review. Obviously, this is not the most efficient algorithm, but it serves the declared purpose and it can still be used in a real system when the hardware must be minimal. Furthermore, an essential correction to the optimal version of this algorithm was made. The techniques are exemplified by doing an original implementation: starting from the initial organigram, passing through transition matrix synthesis stage and reaching to the final fully functional system on a "Digilent Spartan-3" FPGA development board, which includes the user interface too.

  4. Memristor Crossbar-based Hardware Implementation of IDS Method

    CERN Document Server

    Merrikh-Bayat, Farnood; Rohani, Ali

    2010-01-01

    Ink Drop Spread (IDS) is the engine of Active Learning Method (ALM), which is the methodology of soft computing. IDS, as a pattern-based processing unit, extracts useful information from a system subjected to modeling. In spite of its excellent potential in solving problems such as classification and modeling compared to other soft computing tools, finding its simple and fast hardware implementation is still a challenge. This paper describes a new hardware implementation of IDS method based on the memristor crossbar structure. In addition of simplicity, being completely real-time, having low latency and the ability to continue working after the occurrence of power breakdown are some of the advantages of our proposed circuit.

  5. Development of space telescope non-ORU hardware

    Science.gov (United States)

    Robertson, K. B.; Henderson, D. E.

    1985-12-01

    Since 1979 work has progressed in the development of the Hubble Space Telescope (HST) mockup. Underwater simulations to evaluate proposed on-orbit servicing tasks have also been done. These tasks involve the planned changeout of scientific instruments and the unscheduled changeout of other orbital replacement units (ORUs) such as batteries and computers. The HST components and subsystems that originally were designated ORUs were the items that were mission critical and were designed for easy changeout. Mockups of 14 non-ORU items were designed and fabricated for the purpose of evaluating the EVA changetasks in the MSFC Neutral Buoyancy Simulator (NBS). The objectives of this design/fabrication/test activity were to design and fabricate the potential ORUs so they contained realistic interfaces and were compatible with the NBS environments. The attachment of the mockup hardware to the spacecraft mockup was similar to the flight version. Also, the hardware connectors were flight-like.

  6. Hardware Design of the Energy Efficient Fall Detection Device

    Science.gov (United States)

    Skorodumovs, A.; Avots, E.; Hofmanis, J.; Korāts, G.

    2016-04-01

    Health issues for elderly people may lead to different injuries obtained during simple activities of daily living. Potentially the most dangerous are unintentional falls that may be critical or even lethal to some patients due to the heavy injury risk. In the project "Wireless Sensor Systems in Telecare Application for Elderly People", we have developed a robust fall detection algorithm for a wearable wireless sensor. To optimise the algorithm for hardware performance and test it in field, we have designed an accelerometer based wireless fall detector. Our main considerations were: a) functionality - so that the algorithm can be applied to the chosen hardware, and b) power efficiency - so that it can run for a very long time. We have picked and tested the parts, built a prototype, optimised the firmware for lowest consumption, tested the performance and measured the consumption parameters. In this paper, we discuss our design choices and present the results of our work.

  7. White River Falls Fish Passage Project, Tygh Valley, Oregon : Final Technical Report, Volume III, Appendix B, Fisheries Report; Appendix C, Engineering Alternative Evaluation; Appendix D, Benefit/Cost Analysis.

    Energy Technology Data Exchange (ETDEWEB)

    Oregon. Dept. of Fish and Wildlife; Mount Hood National Forest (Or.)

    1985-06-01

    Studies were conducted to describe current habitat conditions in the White River basin above White River Falls and to evaluate the potential to produce anadromous fish. An inventory of spawning and rearing habitats, irrigation diversions, and enhancement opportunities for anadromous fish in the White River drainage was conducted. Survival of juvenile fish at White River Falls was estimated by releasing juvenile chinook and steelhead above the falls during high and low flow periods and recapturing them below the falls in 1983 and 1984. Four alternatives to provide upstream passage for adult salmon and steelhead were developd to a predesign level. The cost of adult passage and the estimated run size of anadromous fish were used to determine the benefit/cost of the preferred alternative. Possible effects of the introduction of anadromous fish on resident fish and on nearby Oak Springs Hatchery were evaluated. This included an inventory of resident species, a genetic study of native rainbow, and the identification of fish diseases in the basin. This volume contains appendices of habitat survey data, potential production, resident fish population data, upstream passage designs, and benefit/cost calculations. (ACR)

  8. SOFTWARE AND HARDWARE SYSTEMS FOR SOUNDING METEOR TRAILS

    Directory of Open Access Journals (Sweden)

    Lebedeva, A.A.

    2016-06-01

    Full Text Available The article describes the basic physical principles of meteor radio. A block diagram of hardware and software for sensing meteor trails. The principles of software-defined radio system lies at the heart of the complex. The paper presents a functional diagram of a digital oscillator, as well as software description with an example of the received data. This complex allows eliminating a number of shortcomings meteor radio, as well as increasing its range and security.

  9. Perforating the atretic pulmonary valve with CTO hardware: Technical aspects.

    Science.gov (United States)

    Patil, Nilkanth C; Saxena, Anita; Gupta, Saurabh K; Juneja, Rajnish; Mishra, Sundeep; Ramakrishnan, Sivasubramanian; Kothari, Shyam S

    2016-11-01

    To review the success and technical aspects of pulmonary valve (PV) perforation using chronic total occlusion (CTO) hardware in patients with pulmonary atresia and intact ventricular septum (PA-IVS). Interventional therapy is possible in selected patients with PA-IVS. Among the various interventional options available, radiofrequency and laser assisted perforation may be more successful, but require expertise and may be substantially costly. We describe the technique of mechanical catheter PV perforation using currently available coronary hardware meant for coronary CTO in nine cases with PA-IVS. After complete echocardiographic evaluation and informed parental consent was obtained, patients were electively intubated, mechanically ventilated, adequately heparinized and were placed on intravenous prostaglandin infusion. Basic steps involved were-localizing the atretic segment and accomplishing coaxial alignment of catheters using biplane fluoroscopy, crossing the atretic segment with the soft end of perforating guidewire, stabilizing the assembly and performing graded balloon dilatation with the balloon size never exceeding 130% of pulmonary annulus diameter. For crossing the atretic PV, a retrograde approach was used in one patient where the antegrade approach was not possible. The procedure was successful in 8/9 cases (89%). Valve opening was achieved in all eight patients with immediate fall in right ventricular (RV) systolic pressures. One neonate died following surgery after catheter induced RV perforation. All surviving cases were discharged from the hospital in good general condition with no evidence of heart failure and a room air oxygen saturation of >85%. No patient required an additional pulmonary irrigation procedure. With appropriate patient and hardware selection, PV perforation using readily available coronary hardware is feasible in PA-IVS. © 2014 Wiley Periodicals, Inc. © 2014 Wiley Periodicals, Inc.

  10. Enhancing GNU Radio for Hardware Accelerated Radio Design

    OpenAIRE

    Irick, Charles Robert

    2010-01-01

    As technology evolves and new methods for designing radios arise, it becomes necessary to continue the search for fast and flexible development environments. Some of these new technologies include software defined radio (SDR), Field Programmable Gate Arrays (FPGAs), and the open source project GNU Radio. Software defined radio is a concept that GNU Radio has harnessed to allow developers to quickly create flexible radio designs. In terms of hardware, the maturity of FPGAs give ...

  11. A Methodology for Formal Hardware Verification, with Application to Microprocessors.

    Science.gov (United States)

    1993-08-29

    Sekar and Srivas verified a simplified version of Wirth’s Lilith . Tamarack Mike Gordon illustrated his early ideas on hardware verification using a...include FM8501 [137, 86] and related designs [136, 239], simplified versions of Cayuga [227] and Lilith [2131, Tamarack [150], Viper [77], SECD [119, 120...techniques in a different proof system, called SBL, to verify a simplified version of Wirth’s LILITH processor. Their model included a simplified form

  12. On the MIMO capacity with residual transceiver hardware impairments

    OpenAIRE

    Zhang, Xinlin; Matthaiou, Michail; Bjornson, Emil; Coldrey, Mikael; Debbah, Merouane

    2014-01-01

    International audience; —Radio-frequency (RF) impairments in the transceiver hardware of communication systems (e.g., phase noise (PN), high power amplifier (HPA) nonlinearities, or in-phase/quadrature-phase (I/Q) imbalance) can severely degrade the performance of traditional multiple-input multiple-output (MIMO) systems. Although calibration algorithms can partially compensate these impairments, the remaining distortion still has substantial impact. Despite this, most prior works have not an...

  13. FY16 ISCP Nuclear Counting Facility Hardware Expansion Summary

    Energy Technology Data Exchange (ETDEWEB)

    Church, Jennifer A. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Kashgarian, Michaele [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Wooddy, Todd [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Haslett, Bob [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Torretto, Phil [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

    2016-09-15

    Hardware expansion and detector calibrations were the focus of FY 16 ISCP efforts in the Nuclear Counting Facility. Work focused on four main objectives: 1) Installation, calibration, and validation of 4 additional HPGe gamma spectrometry systems; including two Low Energy Photon Spectrometers (LEPS). 2) Re-Calibration and validation of 3 previously installed gamma-ray detectors, 3) Integration of the new systems into the NCF IT infrastructure, and 4) QA/QC and maintenance of current detector systems.

  14. A Parameterized Design Framework for Hardware Implementation of Particle Filters

    Science.gov (United States)

    2008-03-01

    synchronization operations. 2.2 Design Framework Figure 2 shows the overall design framework. We use Xilinx’s System Generator for design and functional...verification and the Xilinx ISE tool-set for synthesis. Xilinx System Generator pro- vides a hardware library that consists of various architectural units, such...Interface modules Parameterized HDL libraries Xilinx System Generator modules Parameterized particle filter system Synthesis and Code Generation C D B

  15. Hardware realization of chaos based block cipher for image encryption

    KAUST Repository

    Barakat, Mohamed L.

    2011-12-01

    Unlike stream ciphers, block ciphers are very essential for parallel processing applications. In this paper, the first hardware realization of chaotic-based block cipher is proposed for image encryption applications. The proposed system is tested for known cryptanalysis attacks and for different block sizes. When implemented on Virtex-IV, system performance showed high throughput and utilized small area. Passing successfully in all tests, our system proved to be secure with all block sizes. © 2011 IEEE.

  16. TH-C-BRB-01: Open Source Hardware: General Overview.

    Science.gov (United States)

    Therriault-Proulx, F

    2016-06-01

    By definition, Open Source Hardware (OSH) is "hardware whose design is made publicly available so that anyone can study, modify, distribute, make, and sell the design or hardware based on that design". The advantages of OSH are multiple and the movement has been growing exponentially over the last couple years, leading to the spread and evolution of 3D printing technologies, the creation of affordable and easy to use micro-controller boards (Arduino, Raspberry Pi, etc.), as well as a plurality of other "hands-on"/DIY projects. As we have seen over the past few years with 3D printing, where the number of projects benefiting clinical practice as grown significantly, the highly educated and technology savvy Medical Physics community is positioned to take advantage of and benefit from paradigm-shifting movements. Sharing of knowledge, know-how, and technology can be a key factor in furthering the impact medical physicists can have. Whether it is to develop phantoms, applicators, detector holders or devices based on the use of motors and sensors, sharing design files significantly enables further development. Because these designs would be massively peer-reviewed through their online publication, improvements would be made, and the creators of the design would be rewarded with an increase number of citation of their work. A curated database of software and hardware projects can be an invaluable to the field, but a critical mass of contributors is likely needed to guarantee the most impact. This symposium will discuss the benefits and hurdles for such an endeavor.

  17. The technological future of 7 T MRI hardware.

    Science.gov (United States)

    Webb, A G; Van de Moortele, P F

    2016-09-01

    In this article we present our projections of future hardware developments on 7 T human MRI systems. These include compact cryogen-light magnets, improved gradient performance, integrated RF-receive and direct current shimming coil arrays, new RF technology with adaptive impedance matching, patient-specific specific absorption rate estimation and monitoring, and increased integration of physiological monitoring systems. Copyright © 2015 John Wiley & Sons, Ltd.

  18. Hardware-Assisted Large-Scale Neuroevolution for Multiagent Learning

    Science.gov (United States)

    2014-12-30

    commercial, stackable full speed multi-FPGA based prototyping platform, in- tegrated with DAC/ ADC modules for mixed signal and digital communications ... communications , but also has high reusability, i.e., a new application needs not change a BCM’s hardware design, only new task graph processing and code...where the pipeline stages seldom exceed 10 due to data dependencies, in the proposed multiagent training platform, we pipeline each process- ing

  19. Subway Train Braking System: A Fuzzy Based Hardware Approach

    Directory of Open Access Journals (Sweden)

    Mamun B.I. Reaz

    2011-01-01

    Full Text Available Problem statement: Automated subway train-braking system require perfection, efficiency and fast response. In order to cope with this concerns, an appropriate algorithm need to be developed which need to be implemented in hardware for faster response. Approach: In this research, the FPGA realization of fuzzy based subway train braking system has been presented on an Alter FLEX10K device to provide an accurate and increased speed of convergence of the network. The fuzzy based subway train braking system is comprised of fusilier, inference, rule selector and defuzzifier modules. Sixteen rules are identified for the rule selector module. After determining the membership functions and its fuzzy variables, the Max-Min Composition method and Madman-Min implication operator are used for the inference module and the Centre of Gravity method is used for the defuzzification module. Each module is modeled individually using behavioral VHDL. The layers are then connected using structural VHDL. Two 8-bit and one 8-bit unsigned digital signals are used for input and output respectively. Six ROMs are defined in order to decrease the chances of processing and increasing the throughput of the system. Results: Functional simulations were commenced to verify the functionality of the individual modules and the system as well. We have validated the hardware implementation of the proposed approach through comparison, verification and analysis. The design has utilized 2372 units of LC with a system frequency of 139.8MHz. Conclusion: In this research, the FPGA realization of fuzzy brake system of subway train has been successfully implemented with minimum usage of logic cells. The validation study with C model shows that the hardware model is appropriate and the hardware approach shows faster and accurate response with full automatic control.

  20. BCI meeting 2005--workshop on technology: hardware and software.

    Science.gov (United States)

    Cincotti, Febo; Bianchi, Luigi; Birch, Gary; Guger, Christoph; Mellinger, Jürgen; Scherer, Reinhold; Schmidt, Robert N; Yáñez Suárez, Oscar; Schalk, Gerwin

    2006-06-01

    This paper describes the outcome of discussions held during the Third International BCI Meeting at a workshop to review and evaluate the current state of BCI-related hardware and software. Technical requirements and current technologies, standardization procedures and future trends are covered. The main conclusion was recognition of the need to focus technical requirements on the users' needs and the need for consistent standards in BCI research.